Patent ID: 11916559
Assignee: SAMBANOVA SYSTEMS, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. The DLL of claim 1, wherein:
the PFD comprises:
a first flipflop with a first flipflop clock input coupled with the first PFD input, and a first flipflop output coupled with the first PFD output;
a second flipflop with a second flipflop clock input coupled with the second PFD input, and a second flipflop output coupled with the second PFD output; and
a logic gate with a first input coupled with the first PFD output and a second input coupled with the second PFD output, and an output coupled with a reset input of the first flipflop and coupled with a reset input of the second flipflop;

the first flipflop asserts the first PFD output when the first flipflop clock input is asserted;
the second flipflop asserts the second PFD output when the second flipflop clock input is asserted; and
the logic gate resets the first flipflop and the second flipflop when both the first PFD output and the second PFD output are asserted.