Patent ID: 11966606
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 3:
4. A memory system connectable to a host device, the memory system comprising:
a flash memory comprising a plurality of first blocks each of which includes a plurality of memory cells and to which data is writable in either of a first mode and a second mode, the first mode being a mode in which a value having a first number of bits is written per memory cell, the second mode being a mode in which a value having a second number of bits is written per memory cell, the second number being more than the first number, and
a controller configured to:
use a plurality of second blocks in the first mode, the plurality of second blocks being part of the plurality of first blocks,
use a plurality of third blocks in the second mode, the plurality of third blocks being another part of the plurality of first blocks,
sequentially write data from the host device to the plurality of second blocks,
execute a first transcription process including selecting one second block from one or more second blocks in which data writing is completed among the plurality of second blocks, and placing the one second block into a reusable state by sequentially writing valid data from the one second block to the plurality of third blocks,
execute a second transcription process including selecting one fourth block from a plurality of fourth blocks each being a third block in which data writing is completed among the plurality of third blocks, and placing the one fourth block into a reusable state by writing valid data from the one fourth block to a third block in which data writing is not completed, and
decrease a number of second blocks in the plurality of first blocks when among the plurality of fourth blocks, a fourth number of fourth blocks in which data writing has been completed most previously include a fourth block storing a more amount of valid data than a second threshold value.