Patent ID: 11900998
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. At least one non-transitory machine readable storage medium having instructions stored thereon, the instructions when executed by a machine to cause the machine to:
select a target memory cell of a memory array comprising a plurality of memory cells and address lines, the address lines including bitlines (BLs) and wordlines (WLs), each of the memory cells connected between one of the BLs and one of the WLs, wherein selection of the target memory cell comprises applying a first bias to a BL coupled to the selected memory cell through a first transistor pair of a first bias circuit and applying a second bias to a WL coupled to the selected memory cell through a second transistor pair of a second bias circuit; and
deselect the other memory cells of the memory array by applying one or more neutral biases to the other BLs and WLs through a plurality of additional bias circuits, each additional bias circuit comprising an additional transistor coupled to a transistor pair, wherein the one or more neutral biases are applied through the additional transistors of the additional bias circuits.