Patent ID: 11960764
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 16:
17. A system, comprising:
a plurality of memory components that share a peak power characteristic, wherein each memory component is associated with a ready/busy pin (R/B #) among a plurality of R/B # pins; and
a processor operatively coupled to the plurality of memory components, to:
select a particular R/B # pin from the plurality of R/B # pins to have a singular status for the plurality of memory components;
receive, by at least one memory die among a plurality of memory dice, signaling indicative of performance of a memory access of a first memory component of the plurality of memory components;
receive, by the at least one memory die among the plurality of memory dice, signaling indicative of performance of the memory access of a second memory component of the plurality of memory components responsive to signaling indicative of completion of the performance of the memory access of the first memory component of the plurality of memory components; and
initiate an internal clocking signal subsequent to receipt of the signaling indicative of completion of performance of the memory access of a last memory component of the plurality of memory components.