Patent ID: 11955159
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 8:
9. The semiconductor memory device of claim 1, further comprising:
an error correction code (ECC) engine configured to:
perform an ECC decoding operation on the read count data from the target memory cell row, and
perform an ECC encoding operation on the updated count data provided from the row hammer management circuit,
wherein the memory cell array includes a normal cell array configured to store user data and the count data and a redundancy cell array configured to store a parity data associated with the user data and a count parity data associated with the count data, and
wherein the ECC engine is configured to perform the ECC encoding operation and the ECC decoding operation on the user data and the count data which are input/output through a same global input/output line, based on time multiplexing.