Patent ID: 11961887
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 16:
17. A method for forming a semiconductor device structure, comprising:
forming first and second fin structures each comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers alternatingly stacked;
forming a sacrificial layer on exposed sidewall surfaces of the first and second fin structures;
forming a sacrificial gate structure over a portion of the first and second fin structures and the sacrificial layer;
removing portions of the first and second fin structures and the sacrificial layer not covered by the sacrificial gate structure;
removing edge portions of the sacrificial layer and edge portions of each of the plurality of second semiconductor layers in the first and second fin structures to form cavities, wherein edge portions of the sacrificial layer are etched at a first amount and edge portions of each of the plurality of second semiconductor layers are etched at a second amount less than the first amount;
forming a dielectric spacer in the cavities;
forming an epitaxial source/drain feature on opposite sides of the sacrificial gate structure, the source/drain feature being in contact with the dielectric spacer and each of the plurality of first semiconductor layers in the first and second fin structures;
removing the sacrificial layer and the second semiconductor layers to expose portions of each of the plurality of first semiconductor layers of the first and second fin structures; and
forming a gate electrode layer to surround each of the plurality of first semiconductor layers of the first and second fin structures.