Patent ID: 11880585
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 2:
3. The semiconductor memory according to claim 2, wherein the check data comprises error correction check data, the written data and the error correction check data both comprising a plurality of data bits, and number of data bits of the written data being more than number of data bits of the error correction check data, the check module comprising:
an error correction check unit, connected to the data transmission module, the error correction check unit being configured to generate the error correction check data according to the written data;
wherein data of one of the plurality of data bits are correspondingly stored in one of the plurality of data storage units or one of the plurality of check bit storage units, a transmission time duration required for the written data, configured for defining each of the plurality of data bits, to be transmitted from the data transmission module to a corresponding one of the plurality of data storage units being a data transmission time duration, and a transmission time duration required for the error correction check data, configured for defining each of the plurality of data bits, to be transmitted from the data transmission module to a corresponding one of the plurality of check bit storage units being a check transmission time duration.