Patent ID: 11876045
Assignee: NANYA TECHNOLOGY CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 3:
4. A method for preparing a semiconductor device, comprising:
forming an opening structure in a first dielectric layer, wherein the opening structure has a first portion, a second portion and a third portion disposed between and physically connecting the first portion and the second portion;
forming a lining material lining the first portion and the second portion of the opening structure and completely filling the third portion of the opening structure, wherein the lining material includes copper-manganese (CuMn);
filling the first portion and the second portion of the opening structure with a conductive material after the lining material is formed; and
performing a planarization process on the lining material and the conductive material;
wherein after the planarization process is performed, a remaining portion of the lining material in the third portion of the opening structure is configured as a fuse link, a remaining portion of the conductive material in the first portion of the opening structure is configured as a first electrode, and a remaining portion of the conductive material in the second portion of the opening structure is configured as a second electrode, and wherein the first electrode, the second electrode and the fuse link form a fuse structure.