Patent ID: 11929253
Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for manufacturing a nanowire structure comprising:
providing a substrate;
forming a buffer region over the substrate;
eliminating a sacrificial top portion of the buffer region to provide a buffer layer with a planarized top surface, wherein:
the planarized top surface has a surface roughness below 10 Å; and
the buffer layer comprises a plurality of discrete layers;

forming a patterned mask over the planarized top surface of the buffer layer, wherein the patterned mask comprises an opening through which a portion of the planarized top surface of the buffer layer is exposed; and
forming a nanowire after the patterned mask is formed, wherein the nanowire is formed over the exposed portion of the planarized top surface of the buffer layer through the opening of the patterned mask, and the nanowire protrudes vertically beyond a top surface of the patterned mask, wherein:
the substrate comprises indium phosphide;
the nanowire comprises indium arsenide; and
within the buffer layer, certain ones of the plurality of discrete layers comprise indium aluminum arsenide with variations in both indium concentration and aluminum concentration, and at least another one of the plurality of discrete layers comprises indium gallium arsenide.