Patent ID: 11916026
Assignee: QUALCOMM INCORPORATED
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A clamp, comprising:
first and second transistors coupled in series between a power bus and a ground;
a resistive voltage divider configured to bias a gate of the first transistor and a gate of the second transistor based on a supply voltage on the power bus; and
a capacitive voltage divider including a first capacitor coupled between the gate of the first transistor and the gate of the second transistor, and a second capacitor coupled between the gate of the second transistor and the ground, wherein the capacitive voltage divider is configured to turn on the first and second transistors in response to a voltage transient on the power bus exceeding a trigger threshold voltage,
wherein the clamp is coupled between the power bus and the ground, in parallel with a circuit that is supplied with power by the power bus.