Patent ID: 11910617
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A method of forming a ferroelectric memory device, comprising:
forming a multi-layer stack over a substrate, the multi-layer stack comprising a plurality of dielectric layers interleaved between a plurality of conductive layers;
patterning the multi-layer stack to form a trench extending through the multi-layer stack;
forming a plurality of self-assembled monolayers on sidewalls of the plurality of dielectric layers exposed by the trench;
forming a plurality of ferroelectric segments on sidewalls of the plurality of conductive layers and vertically outside of the plurality of self-assembled monolayers;
forming a channel layer directly on upper surfaces, lower surfaces, or sidewalls of the plurality of ferroelectric segments and the sidewalls of the plurality of dielectric layers; and
forming a conductive pillar along sidewalls of the channel layer.