Patent ID: 11875842
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 5:
6. A memory system, comprising:
a memory device;
a first row decoder coupled to a first sub-block of a first memory block;
a second row decoder, separate from the first row decoder, coupled to a second sub-block of the first memory block; and
a controller operatively coupled to the memory device, the controller being configured to:
access, by the first row decoder, the first sub-block of the first memory block at a first time; and
access, by the second row decoder, the second sub-block of the first memory block at a second different from the first time,

wherein the second time defines a time delay that is chronologically after the first time, and
wherein the time delay is determined based upon a word line voltage ramp rate control.