Patent ID: 11967633
Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for forming at least one doped region intended to form a source or a drain of a transistor, comprising the following steps:
providing a stack comprising in a direction at least one insulating layer, one active layer made of a semiconductor material overlying the insulating layer, and one transistor gate pattern overlying the active layer and having at least one lateral flank extending on a plane substantially perpendicular to an upper face of the active layer;
removing a first portion of the active layer not overlaid by the gate pattern, the first portion extending down to the gate pattern directly at an edge of a second portion of the active layer, the second portion being located under the gate pattern, so as to expose an edge of the second portion, the edge extending in a continuation of the at least one lateral flank of the gate pattern;
forming a first spacer made of a first material on the at least one lateral flank and on the edge, the first spacer having an L shape and comprising a basal portion in contact with the insulating layer, and a lateral portion in contact with the at least one lateral flank, the basal portion having a thickness along the direction substantially equal to a thickness of the active layer;
forming a second spacer made of a second material on the first spacer, the second spacer having a shape complementary to that of the first spacer;
removing the basal portion of the first spacer by selectively etching the first material with respect to the second material of the second spacer and the semiconductor material, so as to expose the edge of the second portion by at least partially retaining the lateral portion of the first spacer on the at least one lateral flank of the gate pattern; and
forming the doped region by epitaxy from the exposed edge.