Patent ID: 11972789
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. A counter circuit, comprising:
a counting circuit, configured to output a count value when the count value exceeds a predetermined threshold;
a decoding circuit, coupled to the counting circuit, and configured to decode the count value to obtain decoding information corresponding to the count value, wherein the decoding information represents a numerical interval in which the count value is located; and
a comparison circuit, coupled to the decoding circuit, and configured to compare the decoding information with historical maximum decoding information and latch current maximum decoding information and output the current maximum decoding information;
wherein the comparison circuit comprises a comparison sub-circuit and a first latch sub-circuit;
wherein the comparison sub-circuit has a first input terminal connected to the decoding circuit and a second input terminal connected to an output terminal of the first latch sub-circuit, and the comparison sub-circuit is configured to compare the decoding information with the historical maximum decoding information outputted by the first latch sub-circuit and output an enable signal based on a comparison result;
wherein the first latch sub-circuit has an input terminal connected to the decoding circuit and an enable terminal connected to an output terminal of the comparison sub-circuit, and the first latch sub-circuit is configured to latch the current maximum decoding information and output the current maximum decoding information in response to the enable signal;
wherein the comparison sub-circuit is configured to output a valid enable signal when the decoding information is greater than the historical maximum decoding information outputted by the first latch sub-circuit, and output an invalid enable signal when the decoding information is not greater than the historical maximum decoding information outputted by the first latch sub-circuit; and
wherein the first latch sub-circuit is configured to latch and output, in response to the valid enable signal, the decoding information outputted by the decoding circuit, and maintain-4e outputting the historical maximum decoding information in response to the invalid enable signal.