Patent ID: 11942181
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. The semiconductor device of claim 1,
wherein the receiver comprises:
a first reception circuit configured to:
receive the first power supply voltage and the ground voltage,
determine a logic level of the second signal inputted through the third transmission path on the basis of a first reference voltage level according to a first clock signal, and
determine a logic level of a first intermediate signal depending on a determination result;
a second reception circuit configured to:
receive the first power supply voltage and the ground voltage,
determine a logic level of the second signal inputted through the third transmission path on the basis of a second reference voltage level according to a second clock signal,
determine a logic level of a second intermediate signal depending on a determination result, and
initialize a logic level of the second intermediate signal in response to the enable signal;
a first level regulation circuit configured to:
receive the first power supply voltage and the ground voltage, and
regulate, according to the first clock signal, the first reference voltage level depending on a logic level of the second intermediate signal fed back from the second reception circuit;
a second level regulation circuit configured to:
receive the first power supply voltage and the ground voltage, and
regulate, according to the second clock signal, the second reference voltage level depending on a logic level of the first intermediate signal fed back from the first reception circuit;
a selection circuit configured to select one of the first and second intermediate signals according to a clock generated by delaying the first clock signal by a preset time; and
a selective driving circuit configured to:
receive the first power supply voltage and the ground voltage, and
pull-up or pull-down drive the first or second transmission path to the first power supply voltage or the ground voltage, respectively, according to an output signal of the selection circuit, and
wherein the first clock signal and the second clock signal have a phase difference of 180 degrees and the first clock signal is activated earlier than the second clock signal.