Patent ID: 11914439
Assignee: ROHM CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 10:
11. The digital processing device according to claim 10,
wherein
the first clock fault determination circuit includes:
a first frequency divider configured to generate a first frequency-divided clock signal by dividing a frequency of the first clock signal; and
a first monitoring circuit configured to monitor, using the second clock signal, intervals of predetermined level changes in the first frequency-divided clock signal,
the first clock fault determination circuit being configured to determine, based on a result of the monitoring, presence or absence of the fault in the first clock signal or a fault in the first frequency divider, and

the second clock fault determination circuit includes:
a second frequency divider configured to generate a second frequency-divided clock signal by dividing a frequency of the second clock signal; and
a second monitoring circuit configured to monitor, using the first clock signal, intervals of predetermined level changes in the second frequency-divided clock signal,
the second clock fault determination circuit being configured to determine, based on a result of the monitoring, presence or absence of the fault in the second clock signal or a fault in the second frequency divider.