Patent ID: 11967977
Assignee: MURATA MANUFACTURING CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A switch circuit comprising:
a first input/output terminal connected to a first radio frequency load;
a second input/output terminal connected to a second radio frequency load, the first input/output terminal being connected to the second input/output terminal by a first path;
a first transistor having a first terminal, a second terminal, and a first control terminal, the first terminal being connected to the first input/output terminal, the second terminal being connected to a first node on the first path, and the first transistor being configured to selectively switch between a conductive state and a non-conductive state based on a first control signal supplied to the first control terminal;
a second transistor having a third terminal, a fourth terminal, and a second control terminal, the fourth terminal being connected to the second input/output terminal, the third terminal being connected to the first node, and the second transistor being configured to selectively switch between a conductive state and a non-conductive state in synchronization with the first transistor;
a third transistor having a fifth terminal, a sixth terminal, and a third control terminal, the fifth terminal and the sixth terminal being connected to a second path connecting the first node and ground, the third transistor being configured to selectively switch between a conductive state and a non-conductive state mutually exclusively with the first transistor and the second transistor;
a fourth transistor having a seventh terminal, an eighth terminal, and a fourth control terminal, the seventh terminal and the eighth terminal being connected to a third path connecting the first node and ground, the third path being different from the second path, and the fourth transistor being configured to selectively switch between a conductive state and a non-conductive state in synchronization with the first transistor and the second transistor;
an inductive element in the third path, the inductive element being connected in series with the fourth transistor; and
a capacitive element in the second path, the capacitive element being connected in series with the third transistor.