Patent ID: 11894102
Assignee: SK HYNIX INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 12:
13. The semiconductor device of claim 7, further comprising:
a second alignment circuit configured to align the write data in response to the first to fourth write clock signals received through the first clock transmission path, the write data received through the first data transmission path, and to transmit the first to fourth write clock signals and the write data through a second clock transmission path and a second data transmission path,
wherein each of first to fourth duty correction devices is configured to receive the first to fourth write clock signals transferred through the second clock transmission path respectively, receive one of the first to fourth write clock signals as the reference clock signal and remaining ones of the first to fourth write clock signals as the first to third divided clock signals alternatively according to the phases of the first to fourth write clock signals, detect the phase difference between the reference clock signal and the first to third divided clock signals, and perform the duty correction operation on the reference clock signal.