Patent ID: 11922172
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 6:
7. A semiconductor apparatus comprising:
one or more substrates; and
logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable logic or fixed-functionality hardware logic, the logic coupled to the one or more substrates to:
enable, during a boot sequence, a first set of ranks in a memory module based on a battery status and a user interface;
disable, during the boot sequence, a second set of ranks in the memory module based on the battery status and the user interface;
generate a map between a system address space and a first set of banks in the first set of ranks; and
exclude a second set of banks in the first set of ranks from the map.