Patent ID: 11887912
Assignee: SHANGHAI INTEGRATED CIRCUIT MANUVACTURING INNOVATION CENTER CO., LTD
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 1:
2. The manufacturing method of a through silicon via structure for three-dimensional integrated circuit packaging of claim 1, wherein the step of obtaining a substrate for making a through silicon via comprises:
first, growing a layer of silicon dioxide film on a surface of the silicon wafer by thermal oxidation;
then, implanting hydrogen ions into the silicon wafer by ion implantation, the hydrogen ions diffusing into the silicon wafer through the silicon dioxide;
afterwards, annealing the silicon wafer to foam hydrogen in a micro cavity where the hydrogen is implanted, such that the silicon wafer is lifted off and splits into an upper silicon wafer and a lower silicon wafer; and
finally, removing, by a wet etching process, the silicon dioxide on a surface of the upper silicon wafer resulting from the lifting off, and planarizing the bottom of the upper silicon wafer by a chemical-mechanical polishing method, thereby obtaining a substrate for making a through silicon via.