Patent ID: 11878388
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC B  H | IPC B  H

Claim 5:
6. A method of manufacturing a semiconductor package, comprising:
forming a material layer over a carrier; and
polishing the material layer using a polishing pad, wherein the polishing pad comprises a plurality of grooves and a plurality of openings, and the grooves are distributed uniformly across the polishing pad while the openings are distributed locally across the polishing pad,
wherein during the polishing, the plurality of openings of the polishing pad are overlapped with the carrier,
wherein the grooves are intersecting X-Y patterns of continuous grooves, and some of the openings intersect at least three of the continuous grooves, and
wherein the openings penetrate through the polishing pad, while the grooves do not penetrate through the polishing pad.