Patent ID: 11915125
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. An arithmetic device comprising:
a mode register configured to store an electrical signal including a table set signal, an input selection signal, and a table input signal through a mode register set; and
an activation function (AF) circuit including a first table storage circuit, configured to store the table input signal into one variable latch selected based on the input selection signal among variable latches included in the first table storage circuit in a look-up table form when the table set signal is activated, and configured to extract a result value of a first activation function realized by the look-up table based on an input distribution signal to output the extracted result value as a first table output signal for generating an output distribution signal,
wherein the table input signal is an electrical signal that is received by the AF circuit and propagated through AF circuit and output from the AF circuit as the output distribution signal.