Patent ID: 11955482
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An integrated circuit structure, comprising:
a fin having a lower fin portion and an upper fin portion;
a gate stack over the upper fin portion of the fin, the gate stack having a first side opposite a second side;
a first source or drain structure comprising an epitaxial structure embedded in the fin at the first side of the gate stack; and
a second source or drain structure comprising an epitaxial structure embedded in the fin at the second side of the gate stack, each of the epitaxial structures of the first and second source or drain structures comprising a core region of silicon and a peripheral region of silicon and having phosphorous therein, the phosphorous having an atomic concentration in the core region of silicon greater than an atomic concentration in the peripheral region of silicon, wherein the core region of silicon is laterally within and is on a bottom of the peripheral region of silicon, and wherein the core region of silicon has an uppermost surface at a same level as an uppermost surface of the peripheral region of silicon.