Patent ID: 11895780
Assignee: UNIMICRON TECHNOLOGY CORP.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  Y | IPC H

Claim 0:
1. A method of manufacturing package structures, comprising:
providing a carrier, wherein the carrier comprises a supporting layer having opposite two surfaces, a release layer disposed on each of the two surfaces, and a metal layer disposed on each of the release layers;
disposing a composite layer of a non-conductor inorganic material and an organic material on each of the metal layers;
bonding a chip embedded substrate on each of the composite layers of the non-conductor inorganic material and the organic material, wherein the chip embedded substrate comprises a plurality of chips and a sealant, the chips are embedded in the sealant, each of the chips has a plurality of electrode pads, and the electrode pads are exposed from the sealant;
forming a circuit layer structure on each of the chip embedded substrates, wherein each of the circuit layer structures comprises at least one dielectric layer and at least one circuit layer, the at least one dielectric layer has a plurality of conductive blind holes, the at least one circuit layer is located on the at least one dielectric layer and extends into the conductive blind holes, and a bottommost circuit layer is electrically connected to the electrode pads through the conductive blind holes;
forming an insulating protective layer on each of the circuit layer structures, wherein the insulating protective layer has a plurality of openings, so as to expose parts of a surface of the circuit layer structure in the openings;
removing each of the supporting layers and each of the release layers to form two package substrates; and
cutting each of the package substrates to obtain a plurality of the package structures.