Patent ID: 11887668
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 18:
19. A memory device comprising:
a memory array comprising a plurality of memory cells; and
control logic, operatively coupled with the memory array, to perform operations comprising:
applying, during a first time period of a program operation, a ramping wordline voltage to a set of wordlines associated with a set of memory cells of the memory array;
floating, at a first set of different times during the first time period, a respective pillar of a set of pillars associated with of memory cells, wherein each pillar voltage, when floated, is boosted in accordance with each increase of the ramping wordline voltage; and
causing, during a second time period, a first programming pulse to be applied to the set of memory cells, wherein the first programming pulse programs each programming level of the set of programming levels associated with the set of memory cells.