Patent ID: 11901486
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. The chip according to claim 8, wherein
the first chip bonding structure comprises a first main pillar, a first platform and a first auxiliary pillar which are sequentially stacked in a direction going away from the chip body, wherein axes of the first main pillar, the first platform and the first auxiliary pillar are collinear, the first platform is provided with a first bottom surface and a second bottom surface parallel to each other, wherein a size of the first bottom surface is greater than a size of the second bottom surface, the second bottom surface, bottom surfaces of the first main pillar and bottom surfaces of the first auxiliary pillar are congruent, the first bottom surface is stacked over one bottom surface of the first main pillar, the second bottom surface is stacked over one bottom surface of the first auxiliary pillar, and a portion of the first platform protruding from a side surface of the first main pillar defines the first chip engaging portion; and
the second chip bonding structure comprises a second main pillar, a second platform and a second auxiliary pillar which are sequentially stacked in the direction distal from the chip body, wherein axes of the second main pillar, the second platform and the second auxiliary pillar are collinear, and the second platform is provided with a first bottom surface and a second bottom surface parallel to each other, wherein a size of the first bottom surface is greater than a size of the second bottom surface, the second bottom surface, bottom surfaces of the second main pillar and bottom surfaces of the second auxiliary pillar are congruent, the first bottom surface is stacked over one bottom surface of the second main pillar, the second bottom surface is stacked over one bottom surface of the second auxiliary pillar, and a portion of the second platform protruding from a side surface of the second main pillar defines the second chip engaging portion.