Patent ID: 11948872
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor package, comprising:
a redistribution substrate;
a semiconductor chip on a top surface of the redistribution substrate; and
a solder terminal on a bottom surface of the redistribution substrate,
wherein the redistribution substrate includes:
an under-bump pattern in contact with the solder terminal;
a dielectric layer on a sidewall of the under-bump pattern;
an under-bump seed pattern between the dielectric layer and the sidewall of the under-bump pattern, the under-bump seed pattern exposing a bottom surface of the under-bump pattern; and
a redistribution pattern on the under-bump pattern,

wherein the under-bump pattern has a central region and an edge region when viewed in plan,
wherein a first top surface of the under-bump pattern at the edge region of the under-bump pattern is at a level higher than a level of a second top surface of the under-bump pattern at the central region of the under-bump pattern, and
wherein an angle between the bottom surface and the sidewall of the under-bump pattern is in a range of 110° to 140°.