Patent ID: 11937421
Assignee: SK HYNIX INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor memory device comprising:
a gate stack including a plurality of conductive patterns stacked apart from each other, the plurality of conductive patterns including at least one gate pattern and a drain select pattern formed over the gate pattern; and
a plurality of channel structures formed in the gate stack; and
a plurality of contact plugs arranged over the gate stack and contacted with the plurality of channel structures, respectively,
wherein at least one of the channel structures comprises:
a first channel pillar formed in the gate pattern;
a second channel pillar formed in the drain select pattern to make contact with an upper portion of the first channel pillar, and the second channel pillar including a junction region formed in an upper portion of the second channel pillar;
a gate insulation layer interposed between the drain select pattern and the first and second channel pillars; and
a memory layer formed to surround a side surface of the first channel pillar,
wherein an upper surface of the first channel pillar is positioned lower than an upper surface of the memory layer, and
an upper surface of the junction region and an upper side surface of the junction region extending from the upper surface of the junction region are inserted into the one of the contact plugs, respectively.