Patent ID: 11972822
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus, comprising:
a memory array comprising a plurality of reversible resistivity memory cells; and
a control circuit in communication with the memory array, the control circuit configured to:
read a group of selected memory cells using a referenced read;
decode data read from the group using the referenced read with a first error correction code (ECC) mode that is capable of correcting up to a first number of bits in the group, the first ECC mode has a first error mis-correction rate for a given raw bit error rate;
read the group of selected memory cells using a self-referenced read in response to a failure to decode the data in the group using the first ECC mode; and
decode data read from the group using the self-referenced read with a second ECC mode that is capable of correcting up to a second number of bits in the group, wherein the second number of bits is greater than the first number of bits, the second ECC mode has a second error mis-correction rate that is greater than the first error mis-correction rate for the given raw bit error rate, wherein data read using the self-referenced read has a lower raw bit error rate than data read using the referenced read, wherein a reduction in raw bit error rate reduces error mis-correction rate in the second ECC mode.