Patent ID: 11929350
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: nan (nan)
Classification: CPC nan | IPC H

Claim 19:
20. A package, comprising:
a substrate having a first surface and a second surface arranged opposite to each other, the first surface having at least one groove, wherein a plurality of electrically conductive pillars are provided at a bottom of a given one of the plurality of grooves, and the plurality of electrically conductive pillars penetrate through the bottom of the given groove to the second surface of the substrate wafer;
at least one semiconductor die stack placed in the given groove, wherein an upper surface of the given semiconductor die stack is lower than or flush with an upper edge of the corresponding groove, and a bottom of the given semiconductor die stack is electrically connected to the plurality of electrically conductive pillars provided at the bottom of the corresponding groove; and
an insulating dielectric layer filling gaps among sidewalls of the plurality of grooves and the plurality of semiconductor die stacks, the insulating dielectric layer being covering the upper surface of the plurality of semiconductor die stacks to seal up the plurality of semiconductor die stacks.