Patent ID: 11900979
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. The apparatus of claim 2, wherein:
a first input voltage to be applied to a first input line of the plurality of input lines is multiplied by a conductance of a first set of p-bits of the plurality of p-bits connected to the first input line, and is to cause first current to flow through respective accumulation lines to which the first set of p-bits are connected,
a second input voltage to be applied to a second input line of the plurality of input lines is multiplied by a conductance of a second set of p-bits of the plurality of p-bits connected to the second input line, and is to cause second current to flow through respective accumulation lines to which the second set of p-bits are connected, and
the first current is to accumulate with the second current at respective intersection points of the second input line and the respective accumulation lines.