Patent ID: 11935616
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 4:
5. The comparison system of claim 3, wherein the second logical unit comprises:
a second PMOS transistor, having a gate for receiving the third signal and a source connected to a drain of the zeroth PMOS transistor;
a second NMOS transistor, having a gate for receiving the fourth signal, a drain connected to a drain of the second PMOS transistor, and a source connected to a drain of the zeroth NMOS transistor;
a fifth PMOS transistor, having a gate for receiving the fourth signal and a source connected to a drain of the seventh PMOS transistor; and
a fifth NMOS transistor, having a gate for receiving the third signal, a drain connected to a drain of the fifth PMOS transistor, and a source connected to a drain of the seventh NMOS transistor.