Patent ID: 11972838
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A signal processing circuit, comprising:
a first signal latch circuit that receives a command address signal and is driven by an even clock;
a second signal latch circuit that receives the command address signal and is driven by an odd clock;
a first decoder that is connected to the first signal latch circuit and outputs an even control signal; and
a second decoder that is connected to the second signal latch circuit and outputs an odd control signal;
wherein, a frequency of the even clock and a frequency of the odd clock are both equal to half a frequency of a reference clock, and a rising edge of the even clock is aligned with a rising edge of the reference clock, and a falling edge of the odd clock is aligned with the rising edge of the reference clock.