Patent ID: 11967278
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A shift register, comprising:
a first transistor having a control electrode coupled to a first clock signal line to receive a first clock signal, a first electrode coupled to a signal input terminal, and a second electrode coupled to a first node;
a second transistor having a control electrode coupled to the first node, a first electrode coupled to a second node, and a second electrode coupled to the first clock signal line to receive the first clock signal;
a third transistor having a control electrode coupled to the first clock signal line to receive the first clock signal, a first electrode coupled to a first power terminal, and a second electrode coupled to the second node;
a fourth transistor having a control electrode coupled to a second clock signal line to receive a second clock signal, a first electrode coupled to a second electrode of a fifth transistor, and a second electrode coupled to the first node;
the fifth transistor having a control electrode coupled to a third node and a first electrode coupled to a second power terminal;
a first capacitor having a first electrode coupled to a fourth node and a second electrode coupled to the second clock signal line, the first node being coupled to the fourth node;
an impedance transistor having a control electrode coupled to the first power terminal, a first electrode coupled to the second node, and a second electrode coupled to the third node;
a first output control circuit coupled to the third node, the fourth node and a first signal output terminal, and configured to output a first driving signal to the first signal output terminal in response to the control of signals at the third node and the fourth node; and
a second output control circuit coupled to at least the first signal output terminal and a second signal output terminal, and configured to output a second driving signal with a phase opposite to that of the first driving signal, to the second signal output terminal, according to the first driving signal output from the first signal output terminal,
wherein the second output control circuit comprises:
an eleventh transistor having a control electrode coupled to a fifth node, a first electrode coupled to the first power terminal, and a second electrode coupled to a seventh node;
a twelfth transistor having a control electrode coupled to the first signal output terminal, a first electrode coupled to the seventh node, and a second electrode coupled to the second power terminal;
a thirteenth transistor having a control electrode coupled to the seventh node, a first electrode coupled to the first clock signal line, and a second electrode coupled to a first electrode of a fourth capacitor;
the fourth capacitor having a second electrode coupled to the seventh node;
a fourteenth transistor having a control electrode coupled to the seventh node, a first electrode coupled to the first power terminal, and a second electrode coupled to the second signal output terminal; and
a fifteenth transistor having a control electrode coupled to the first signal output terminal, a first electrode coupled to the second signal output terminal, and a second electrode coupled to the second power terminal.