Patent ID: 11915000
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A method comprising:
decoding an instruction into a decoded instruction with a decoder of a hardware processor comprising a first level data cache and a store buffer;
executing the decoded instruction with an execution circuit of the hardware processor to produce a resultant;
retiring the instruction with a retirement circuit of the hardware processor when a store request for the resultant is queued into the store buffer for storage into a memory but is not yet completed to the memory;
monitoring, by a performance monitoring circuit of the hardware processor, post-retirement performance information of the retired instruction between the store request being accepted into the first level data cache and being completed to the memory, wherein the post-retirement performance information comprises a first value to indicate the store request missed in the first level data cache and a second value to indicate the store request missed in a translation lookaside buffer; and
storing, by the performance monitoring circuit, the post-retirement performance information in storage of the performance monitoring circuit.