Patent ID: 11916022
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 9:
10. A processing system, comprising:
a bonding apparatus configured to bond a semiconductor wafer to a handle wafer, wherein a plurality of upper alignment marks is disposed on the semiconductor wafer and a plurality of lower alignment marks is disposed on the handle wafer;
a shift measurement apparatus configured to measure a shift between the plurality of upper alignment marks and the plurality of lower alignment marks;
a photolithography tool configured to expose a photoresist layer on the semiconductor wafer to patterned radiation;
a controller configured to perform a photolithography alignment process on the photolithography tool according to the shift, wherein the photolithography alignment process compensates for the shift; and
a memory unit connected to the controller and the shift measurement apparatus, wherein the memory unit is configured to store the shift and provide the shift to the photolithography tool during subsequent photolithography processes.