Patent ID: 11949625
Assignee: LG ELECTRONICS INC.
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 18:
19. An apparatus comprising: one or more memories and one or more processors functionally connected to the one or more memories,
wherein the one or more processors control the apparatus to:
receive first control information based on a first control resource set (CORESET) of a first CORESET group;
receive second control information based on a second CORESET of a second CORESET group;
receive at least one of (i) a first data scheduled based on the first control information or (ii) a second data scheduled based on the second control information; and
transmit, first feedback information corresponded to the first data and second feedback information corresponded to the second data,
wherein an index of the first CORESET group and an index of the second CORESET group have different values
wherein each of the first control information and the second control information includes a Downlink Assignment Index (DAI) field, and
wherein a value of the DAI field is configured based on the index of the first CORESET group and the index of the second CORESET group.