Patent ID: 11908861
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 16:
17. A semiconductor device, comprising:
an active pattern on a substrate;
a pair of source/drain patterns on the active pattern;
fence spacers on opposing side surfaces of each of the pair of source/drain patterns;
a channel pattern extending between the pair of source/drain patterns;
a gate electrode crossing the channel pattern and extending in a first direction;
a gate insulating layer between the gate electrode and the channel pattern;
a gate spacer on a side surface of the gate electrode;
a gate capping pattern on a top surface of the gate electrode;
a first interlayer insulating layer on the gate capping pattern;
active contacts extending through the first interlayer insulating layer and contacting the source/drain patterns;
gate contacts extending through the first interlayer insulating layer and contacting the gate electrode;
a second interlayer insulating layer on the first interlayer insulating layer;
a first metal layer in the second interlayer insulating layer, the first metal layer comprising first interconnection lines, which are electrically and respectively connected to the active contacts and the gate contacts and extend in a second direction crossing the first direction to be parallel to each other;
a third interlayer insulating layer on the second interlayer insulating layer; and
a second metal layer in the third interlayer insulating layer,
wherein the second metal layer comprises second interconnection lines, which are electrically connected to the first interconnection lines and extend in the first direction to be parallel to each other, and
a first thickness of an upper portion of the fence spacers in the first direction is greater than a second thickness of the gate spacer in the second direction, and is greater than a third thickness of a lower portion of the fence spacers in the first direction.