Patent ID: 11908932
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 23:
24. A memory array, comprising:
memory cells, at least one memory cell of the memory cells comprising at least one vertical transistor, comprising:
a channel region comprising an upper region and a lower region, a width of the lower region being less than a width of the upper region;
gate electrodes laterally adjacent to the lower region of the channel region, at least a portion of the gate electrodes recessed below the upper region of the channel region;
a gate dielectric material extending along an entirety of two sides of the gate electrodes, and along only a portion of upper ends of the gate electrodes proximal to the upper region of the channel region; and
an insulative material laterally separating the gate electrodes of adjacent vertical transistors from one another, the insulative material abutting side surfaces of the gate dielectric material proximal to the upper ends of the gate electrodes and abutting additional side surfaces of the gate dielectric material proximal to lower ends of the gate electrodes; and

a storage element in operative communication with the at least one vertical transistor.