Patent ID: 11936504
Assignee: CEREMORPHIC, INC.
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. A decision feedback equalizer, comprising:
a summer;
a slicer including a first slicer and a second slicer; and
a feedback circuit,
wherein the summer is configured to receive an input signal and a correction signal from the feedback circuit to generate a summer output signal,
wherein the first slicer and the second slicer are configured to receive the summer output signal as an input, sample the received input, and output a slicer output signal,
wherein the feedback circuit is configured to receive the slicer output signal, and based on the slicer output signal, generate the correction signal,
wherein the input signal is received at a first clock rate,
wherein the first slicer and the second slicer sample the received input at a second clock rate approximately half the first clock rate, and
wherein the feedback circuit includes a plurality of DFE taps, each of the plurality of decision feedback equalizer (DFE) taps configured to receive a DFE tap correction signal, a polarity of the DFE tap correction signal is determined by the slicer output signal, and a plurality of DFE tap correction signals from the plurality of DFE taps are collectively fed as the correction signal to the summer.