Patent ID: 11861366
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A method comprising:
identifying a nested loop in a set of instructions;
determining a first value of a first initiation interval of a first processing element of a set of interconnected processing elements and a second value of a second initiation interval of a second processing element of the set of interconnected processing elements based upon a number of instructions in an inner loop and outer loop of the nested loop and a number of processing elements in the set of interconnected processing elements, the second value a multiple of the first value, the first and second initiation intervals specifying a number of consecutive instructions allowed within a processing pipeline of each respective processing element;
configuring the first initiation interval of the first processing element to the first value and the second initiation interval of the second processing element to the second value;
assigning instructions of an inner loop of the nested loop to the first processing element and instructions of an outer loop of the nested loop to the second processing element; and
causing execution of the set of instructions by the first and second processing elements.