Patent ID: 11881246
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. The electronic device according to claim 7, further comprising:
an active control circuit configured to, by receiving an active command and a refresh command, generate the internal read signal to control the internal read operation and the internal write signal and generate an internal comparison signal to control the internal write operation;
an internal address generation circuit configured to generate the internal address based on the address;
an input/output control circuit coupled to the first memory region through a row hammering input/output line, configured to receive and output the read counting signal through the row hammering input/output line during the internal read operation, and configured to receive and output the write counting signal through the row hammering input/output line during the internal write operation; and
a column control circuit coupled to the second memory region through a local input/output line, configured to receive and output the first data through the local input/output line and output during the read operation, and configured to receive and output the second data through the local input/output line during the write operation.