Patent ID: 11917831
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. An integrated chip comprising:
a substrate;
a wire spaced over the substrate;
a memory cell overlying and on the wire, wherein the memory cell comprises:
a ferroelectric memory layer overlying the wire;
a semiconductor layer overlying the ferroelectric memory layer; and
a ferroelectric seed layer between the ferroelectric memory layer and the wire, and directly contacting the ferroelectric memory layer; and

a first etch stop layer overlying and directly contacting a top surface of the semiconductor layer; and
a second etch stop layer spaced from and underlying the first etch stop layer, wherein the second etch stop layer is on sidewalls of the ferroelectric seed layer and comprises a same material as the first etch stop layer;
wherein the ferroelectric memory layer comprises hafnium zirconium oxide, and wherein the ferroelectric seed layer is configured to increase an orthorhombic phase in the ferroelectric memory layer to at least 35 percent.