Patent ID: 11934251
Assignee: ADVANCED MICRO DEVICES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 6:
7. A method, comprising:
receiving a power state command at a memory controller, and in response changing an operating frequency of at least one of a memory controller clock domain and a memory clock domain, resynchronizing a memory controller bus interface with a data fabric clock domain, and resynchronizing a physical layer interface (PHY) with the memory controller; and
receiving a request to resynchronize the memory controller with a frequency of only a first clock signal of the data fabric clock domain, and in response, changing a set of timing parameters of a clock interface circuit between the data fabric clock domain and the memory controller clock domain without resynchronizing the PHY with the memory controller, changing a set of timing parameters of a memory or the memory controller besides the timing parameters of the clock interface circuit.