Patent ID: 11942546
Assignee: NATIONAL TAIWAN UNIVERSITY
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A method, comprising:
forming semiconductor layers vertically stacked over a substrate;
forming a dummy gate structure over the semiconductor layers;
forming gate spacers on opposite sidewalls of the dummy gate structure;
forming inner spacers vertically between two adjacent semiconductor layers;
forming source/drain structures on opposite sides of the dummy gate structure after forming the inner spacers;
removing the dummy gate structure after forming the source/drain structures;
forming an interfacial layer in contact with each of the semiconductor layers;
forming a quasi-antiferroelectric (QAFE) layer over the interfacial layer, wherein the QAFE layer has a rectangular ring-shape cross-section vertically between the semiconductor layers, wherein a thickness of the QAFE layer is in a range from about 8 nm to about 12 nm, such that in a polarization-voltage curve of the QAFE layer, when a sweep voltage of 3 V is applied, a remnant polarization (Pr) of the QAFE layer is in a range from about 0.5 μC/cm2 to about 5 μC/cm2 and a coercive voltage (Vc) of the QAFE layer is in a range from about 0.1 V to about 0.5 V, wherein the QAFE layer comprises Hf1-xZrxO2, x being greater than 0.5 and lower than 1;
forming a gate electrode over the QAFE layer, wherein the QAFE layer is in direct contact with the interfacial layer, the inner spacers, the gate spacers, and the gate electrode; and
performing a planarization process to the interfacial layer, the QAFE layer, and the gate electrode to form a semiconductor device.