Patent ID: 11922032
Assignee: DREAMBIG SEMICONDUCTOR INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G

Claim 6:
7. A content addressable memory circuit comprising:
multiple integrated circuit memory devices that include wordlines that share common wordline addresses and that are coupled for simultaneous access;
multiple buffer circuits, each output buffer circuit operatively coupled to a different one of the multiple memory devices;
a hash table that includes a plurality of hash values, wherein each respective hash value corresponding to one or more key values;
one or more processor circuits;
non-transitory memory including instructions incorporated into the non-transitory memory, the instructions configuring the one or more processors to perform operations comprising:
assigning each hash value to a wordline address based upon a first portion of the hash value;
storing each key value at the worldline having a wordline address assigned to a first portion of a hash value that corresponds to the key value;
causing a memory device to copy a first key value from a first wordline having a first wordline address within the memory device to a buffer circuit operatively coupled to the memory device;
causing the memory device to copy the first key value from the buffer circuit operatively coupled to the memory device to a second wordline having a second wordline address within the memory device; and
assigning a second portion of a hash value that corresponds to the first key value to the second wordline address of the memory device.