Patent ID: 11967552
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A structure comprising:
a via in a dielectric layer, wherein the via includes a first barrier layer and a bulk layer over the first barrier layer; and
a conductive line over a top surface of the via, wherein the conductive line includes a ruthenium-containing conductive layer over the top surface of the via and a top surface of the dielectric layer and in physical contact with the bulk layer, wherein the conductive line further includes a second barrier layer over sidewalls of the ruthenium-containing conductive layer, wherein the structure is free of a nitride layer between the bulk layer and the ruthenium-containing conductive layer, and wherein a thickness of the conductive line is less than a thickness of the via.