Patent ID: 11973082
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 12:
13. An integrated circuit device comprising:
a semiconductor on insulator (SOI) substrate layer comprising a base substrate layer, an insulating substrate layer, and a cover substrate layer in a first region;
a semiconductor substrate layer in a second region;
a plurality of first fin-type active areas and a plurality of second fin-type active areas defined by a plurality of trenches and extending in a first horizontal direction, on the SOI substrate layer and the semiconductor substrate layer, respectively;
a plurality of first nanosheets extending in parallel with each other and spaced apart in a vertical direction from the plurality of first fin-type active areas;
a plurality of gate electrodes extending in a second horizontal direction that crosses the first horizontal direction, the plurality of gate electrodes on the plurality of first fin-type active areas and the plurality of second fin-type active areas, first portions of the plurality of gate electrodes between vertically adjacent first nanosheets;
a gate dielectric layer between the first nanosheets and plurality of first fin-type active areas;
a plurality of first source/drain regions between horizontally adjacent first nanosheets above the plurality of first fin-type active areas, each of the plurality of first source/drain regions extending into the SOI substrate layer to contact the insulating substrate layer and having a lower surface at a first vertical level above the plurality of first fin-type active areas; and
a plurality of second source/drain regions above the plurality of second fin-type active areas, each of the plurality of second source/drain regions extending into the semiconductor substrate layer and having a lower surface that is at a second vertical level above the plurality of second fin-type active areas that is higher than the first vertical level.