Patent ID: 11903200
Assignee: SK HYNIX INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 5:
6. A semiconductor memory device comprising:
a gate stack formed on a source layer, and having a plurality of interlayer dielectric layers and a plurality of gate conductive layers which are alternately stacked therein; and
a plurality of channel structures formed through the gate stack, and each having a lower end extended into the source layer,
wherein each of the channel structures comprises:
a channel layer having a first region faced to the gate stack and a second region extending toward the source line from the first region; and
a channel passivation layer formed on a surface of the channel layer of the first region,
wherein the channel layer of the first region has a smaller thickness than the channel layer of the second region, and
wherein an upper surface of the channel layer of the second region is contacted with bottom surfaces of the channel layer of the first region and the channel passivation layer.