Patent ID: 11869607
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A method comprising:
while a memory die is powered on and after a portion of preloaded data is stored on a set of physical memory locations of the memory die, measuring a charge distribution of an aging bin to determine a reference charge distribution, the aging bin comprising one or more physical memory locations of the memory die that are different from the set of physical memory locations, the aging bin storing a program-erase count for the set of physical memory locations, the program-erase count describing a number of times data has been written to or erased from the set of physical memory locations;
after the memory die is powered off, solder mounting the memory die to a printed circuit board; and
after the printed circuit board is powered on:
determining, by a processing device operatively coupled to the printed circuit board, a charge loss value of the aging bin based on a difference between a current charge distribution of the aging bin and the reference charge distribution;
determining, by the processing device, a voltage level threshold for reading data from the set of physical memory locations, the voltage level threshold being determined based on the charge loss value; and
reading, by the processing device, the portion of preloaded data from the set of physical memory locations based on the voltage level threshold.