Patent ID: 11942053
Assignee: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
Field: Optics (Instruments)
Classification: CPC G  H | IPC G  H

Claim 16:
17. The display panel according to claim 1, further comprising:
a gate insulating layer between the source conducting layer and the base substrate; and
the gate conducting layer between the gate insulating layer and the base substrate; wherein the gate conducting layer comprises a plurality of first gate lines, a plurality of second gate lines and a plurality of third gate lines;
the gate conducting layer further comprises: a plurality of first compensating electrodes disposed at intervals; wherein an orthographic projection of one first compensating electrode on the base substrate is in one first partition; in the same first partition, the orthographic projection of the first pixel electrode on the base substrate covers the orthographic projection of the first compensating electrode on the base substrate, and the orthographic projection of the first compensating electrode on the base substrate has an overlapping region with the orthographic projection of the first drain electrode part of the first transistor on the base substrate; and/or,
the gate conducting layer further comprises: a plurality of second compensating electrodes disposed at intervals; wherein an orthographic projection of one second compensating electrode on the base substrate is in one second partition; and in the same second partition, the orthographic projection of the second pixel electrode on the base substrate covers the orthographic projection of the second compensating electrode on the base substrate, and the orthographic projection of the second compensating electrode on the base substrate has an overlapping region with the orthographic projection of the second drain electrode part of the second transistor on the base substrate.