Patent ID: 11915773
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. The nonvolatile memory device of claim 1, wherein the wordline defect detection circuit includes:
a comparison circuit configured to generate a comparison result signal based on a reference voltage and the measurement voltage decreasing by the path leakage current in the compensation mode and generate the comparison result signal based on the reference voltage and the measurement voltage decreasing by both of the path leakage current and each wordline leakage current in the defect detection mode;
a compensation circuit configured to generate the offset value based on transition timing of the comparison result signal in the compensation mode; and
a defect determination circuit configured to generate a pass-fail signal indicating weather a defect exits in each wordline based on a logic level of the comparison result signal at a latch time point that is determined based on the offset value in the defect detection mode.