Patent ID: 11947468
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A method of operation in a memory device including a plurality of sub-banks of memory including a first sub-bank and a second sub-bank, a first data interface circuit to couple to a memory controller via a first data bus, and a second data interface circuit to couple to the memory controller via a second data bus, the method comprising:
receiving, from the memory controller, a first refresh command to refresh the first sub-bank and a first calibration command; and
while the first sub-bank is being refreshed responsive to the first refresh command and a first calibration operation is performed on the first data interface circuit responsive to the first calibration command, transferring data, via the second data interface circuit, between the memory controller and the second sub-bank that is not being refreshed.