Patent ID: 11972986
Assignee: SILTRONIC AG
Field: Measurement (Instruments)
Classification: CPC H  C  G | IPC C  G  H

Claim 11:
12. A process for producing a plurality of stress free or stress optimized semiconductor wafers having a front side, a rear side, and a circumferential edge, comprising the following steps:
a) receiving a thermal budget for fabricating semiconductor devices on a semiconductor wafer;
b) pulling a single-crystal rod of the semiconductor and optionally cylindrically grinding the rod;
c) separating a plurality of semiconductor wafers from the single-crystal rod;
d) identifying a test semiconductor wafer having properties representative of the plurality of semiconductor wafers;
e) performing a first thermal treatment step corresponding to the thermal budget referred to in step a) on the test semiconductor wafer;
f) performing a second thermal treatment on the test semiconductor wafer following step e) to establish a radial temperature gradient in at least one interior zone of the semiconductor wafer, the at least one interior zone positioned at least 10 mm inward from the circumferential edge of the test semiconductor wafer;
g) analyzing the test wafer for stress fields to determine whether the test semiconductor wafer has no stress or a level of stress suitable for fabricating semiconductor devices according to the thermal budget; and
h) classifying the remaining plurality of semiconductor wafers as stress optimized wafers or rejected wafers in accordance with the result of step g).