Patent ID: 11907546
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G

Claim 0:
1. An apparatus, comprising:
a first array of memory cells configured for access operations;
a first interface for communicating first data with a host device, wherein the first interface is configured to support a first modulation scheme using a first quantity of voltage levels;
a second interface for communicating second data with a memory die, the memory die comprising a second array of memory cells configured for access operations, wherein the second interface comprises a set of buffers configured to store the second data transferred between the memory die and the first array of memory cells, and wherein the second interface is configured to support a second modulation scheme using a second Quantity of voltage levels that is different than the first Quantity of voltage levels; and
a third interface configured for communicating control information with a controller that is coupled with the apparatus and the memory die.