Patent ID: 11915931
Assignee: TOKYO ELECTRON LIMITED
Field: Optics (Instruments)
Classification: CPC H  G | IPC H

Claim 0:
1. A method for fabricating a semiconductor device comprising:
forming a base layer over a top layer of a substrate, the base layer comprising a silicon based dielectric having a thickness less than or equal to 5 nm and greater than or equal to 0.5 nm;
forming a photoresist layer over the base layer, the photoresist comprising a first side and an opposite second side;
exposing a first portion of the photoresist layer to a pattern of extreme ultraviolet (EUV) radiation from the first side;
exposing a second portion of the photoresist layer with a pattern of electron flux from the second side, the electron flux being directed into the photoresist layer from the base layer in response to the EUV radiation;
developing the exposed photoresist layer to form a patterned photoresist layer; and
transferring the pattern of the patterned photoresist layer to the base layer and the top layer.