Patent ID: 11892956
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An electronic device, comprising:
a memory system comprising a memory controller and a plurality of memory locations, the memory controller being programmed to perform operations comprising:
communicating, by the memory system and to a host device, a first message describing background operations to be performed at the memory system;
after communicating the first message, receiving, by the memory system and from the host device, a second message indicating permission to execute the background operations;
after receiving the second message, initiating, by the memory system, execution of at least one of the background operations;
reading time data from a descriptor memory location, the time data describing a time period when the memory system is to execute the at least one of the background operations, the descriptor memory location being a memory location of the plurality of memory locations that is accessible to the host device;
determining that the time period when the memory system is to execute the at least one of the background operations has expired prior to completing the at least one of the background operations; and
stopping execution of the at least one of the background operations.