Patent ID: 11961761
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. A method for forming a semiconductor structure associated with mitigating pattern collapse, comprising:
etching a first trench within a first dielectric layer;
forming a first metal line within the first trench;
forming a second dielectric layer above the first metal line and the first dielectric layer;
etching a second trench within the second dielectric layer;
forming a first metal line barrier layer within the second trench;
filling a remainder of the second trench with a first metal material; and
performing an anneal process after the filling a remainder of the second trench with a first metal material to change a composition of the first metal line barrier layer, wherein the anneal process forms a top barrier layer over the first metal material.