Patent ID: 11862547
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A substrate, comprising:
a body having a top surface and a bottom surface that is opposite from the top surface, wherein the top surface has a first conductive layer and a first dielectric layer, and wherein the bottom surface has a second conductive layer and a second dielectric layer;
a plurality of interconnects in the body, wherein the plurality of interconnects have a plurality of first conductive pads on the top surface of the body, and a plurality of second conductive pads on the bottom surface of the body, wherein the plurality of interconnects vertically extend from the plurality of first conductive pads to the plurality of second conductive pads, and wherein the plurality of interconnects conductively couple the plurality of first conductive pads to the plurality of second conductive pads; and
a first interconnect and a second interconnect in the body, wherein the first interconnect has a first conductive pad on the bottom surface of the body, and a second conductive pad on the top surface of the body, wherein the second interconnect has a third conductive pad on the bottom surface of the body, and a fourth conductive pad on the top surface of the body, wherein the first interconnect is directly adjacent to the second interconnect, wherein the first and second interconnects are in between the plurality of interconnects, wherein the first and second interconnects are part of a swapped structure in the body, wherein the second conductive pad of the first interconnect is at least partially within a footprint of the third conductive pad of the second interconnect, and wherein the fourth conductive pad of the second interconnect is at least partially within a footprint of the first conductive pad of the first interconnect.