Patent ID: 11954045
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 20:
21. An apparatus, comprising circuitry to:
receive a first request associated with an application to perform a store operation for an address range in a memory allocation, wherein the address range includes at least one address in a first cacheline of memory and at least one address in a second cacheline of the memory;
receive the first cacheline of stored data from memory;
store first buffered contents in the first cacheline beginning at a first memory address of the address range;
identify a first portion of the first cacheline, wherein the first portion of the first cacheline includes some of the address range and is to be identified based at least in part on a first data bounds value stored in a metadata region located within the first cacheline, wherein the first data bounds value indicates a size of the first buffered contents contained within the first portion of the first cacheline;
generate a first integrity value based on the first portion of the first cacheline; and
store the first integrity value in the metadata region of the first cacheline.