Patent ID: 11923043
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: nan (nan)
Classification: CPC nan | IPC G  H

Claim 3:
4. The memory of claim 3, wherein the logical unit comprises:
a counter, configured to;
when the first input terminal of the integral unit receives the first internal signal in response to the inversion identification signal being at the low level and receives the second internal signal in response to the inversion identification signal being at the high level, and the second input terminal of the integral unit receives the second internal signal in response to the inversion identification signal being at the low level and receives the first internal signal in response to the inversion identification signal being at the high level, adjust the at least one of the duty cycle of the first internal signal or the duty cycle of the second internal signal,

or,
when the first input terminal receives the first oscillation signal in response to the inversion identification signal being at the low level and receives the second oscillation signal in response to the inversion identification signal being at the high level, and the second input terminal receives the second oscillation signal in response to the inversion identification signal being at the low level and receives the first oscillation signal in response to the inversion identification signal being at the high level, configured to adjust the at least one of the duty cycle of the first oscillation signal or the duty cycle of the second oscillation signal;

a first register group, configured to store a first value of the counter according to an output of the comparator in response to the inversion identification signal being at the low level; and
a second register group, configured to store a second value of the counter according to an output of the comparator in response to the inversion identification signal being at the high level.