Patent ID: 11870441
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: nan (nan)
Classification: CPC nan | IPC G  H

Claim 9:
10. The clock gating circuit of claim 9, wherein the NOR logic gate further comprises:
a third transistor of the first type including a gate terminal of the third transistor, a drain terminal of the third transistor and a source terminal of the third transistor, the gate terminal of the third transistor being configured to receive the second enable signal, and the source terminal of the third transistor being coupled to the voltage supply; and
a fourth transistor of the first type including a gate terminal of the fourth transistor, a drain terminal of the fourth transistor and a source terminal of the fourth transistor, the gate terminal of the fourth transistor being configured to receive the first enable signal, and the drain terminal of the fourth transistor being coupled to the first node, the drain terminal of the second transistor, and the drain terminal of the first transistor,
wherein each of the drain terminal of the third transistor and the source terminal of the fourth transistor being coupled together.