Patent ID: 11887923
Assignee: NEXTVPU (SHANGHAI) CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 18:
19. A wiring design method for a package substrate in a flip chip, wherein the flip chip comprises the package substrate and a flip chip die opposite to the package substrate, the method comprises the following steps:
arranging bump pads in an array of rows and columns, wherein the bump pads are configured to bond with conductive bumps on the flip chip die, the bump pads comprise signal pads and non-signal pads, and the non-signal pads comprise power pads and ground pads, wherein the signal pads are arranged over an entire area in which the bump pads are arranged, and the non-signal pads are arranged over the entire area in which the bump pads are arranged, and wherein bump pads of odd-numbered rows and bump pads of even-numbered rows are staggered relative to each other in a column direction of the array;
providing the non-signal pad with a via hole to electrically connect the power pad to a power layer in the package substrate and electrically connect the ground pad to a ground layer in the package substrate; and
using a layer of wiring to lead a subset of the signal pads out of an orthographic projection region of the flip chip die on the package substrate, wherein the subset of the signal pads is configured to carry all functional signals required by design specifications of the flip chip die for the array of the bump pads.