Patent ID: 11954370
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. A system, comprising:
a host; and
a memory device coupled to the host, wherein the host is configured to:
identify and send a first command to be queued at the memory device;
receive a first response to the first command from memory device indicating a command queue on the memory device is ready to receive commands;
send a second command to the memory device in response to receiving the first response;
receive a second response to the second command from memory device;
send a third command to execute a data transaction in response to receiving the first response and the second response, wherein the third response includes a direction bit that indicates a direction of data transfer;
receive a third response to the third command from memory device, wherein the third response includes a direction bit that indicates a direction of data transfer; and
transfer data to or reading data from memory device in response to receiving the third response from memory device.