Patent ID: 11895837
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A semiconductor device comprising:
a substrate including a memory cell region and a connection region;
a plurality of gate electrodes stacked on the substrate;
a channel structure disposed in the memory cell region and penetrating the plurality of gate electrodes, the channel structure including a channel layer extending in a vertical direction perpendicular to an upper surface of the substrate;
a dummy channel structure disposed in the connection region and penetrating the plurality of gate electrodes, the dummy channel structure including a dummy channel layer extending in the vertical direction;
a common source line disposed in a word line cut region penetrating the plurality of gate electrodes and extending in a first horizontal direction;
a first semiconductor layer disposed in the memory cell region and disposed between the substrate and a lowermost gate electrode of the plurality of gate electrodes, the first semiconductor layer at least partially surrounding the channel structure and the dummy channel structure;
a first insulation layer disposed in the connection region and between the substrate and the lowermost gate electrode and at least partially surrounding the dummy channel structure; and
an etch stop layer disposed in the connection region and surrounding the first insulation layer, the etch stop layer including a first portion and a second portion, the first portion being vertically overlapped with the common source line and extending in the first horizontal direction, the second portion being between the first semiconductor layer and the first insulation layer and extending in a second horizontal direction.