Patent ID: 11948644
Assignee: LODESTAR LICENSING GROUP LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. A memory, comprising:
an array of memory cells comprising a plurality of memory cells, wherein each memory cell of the plurality of memory cells is selected for programming to a respective data state of a plurality of data states for a programming operation; and
control logic;
wherein the control logic is configured to cause the memory to:
increase respective threshold voltages of a first subset of memory cells of a plurality of memory cells to threshold voltage levels higher than a particular voltage level in response to applying a first plurality of programming pulses to control gates of the plurality of memory cells, wherein the first plurality of programming pulses each have a respective voltage level within a first range of voltage levels;
after applying the first plurality of programming pulses to the control gates of the plurality of memory cells, increase respective threshold voltages of a second subset of memory cells of the plurality of memory cells to threshold voltage levels lower than a second voltage level that is lower than the particular voltage level in response to applying a second plurality of programming pulses to the control gates of the plurality of memory cells, wherein the second plurality of programming pulses each have a respective voltage level within a second range of voltage levels; and
increase respective threshold voltages of a third subset of memory cells of the plurality of memory cells to threshold voltage levels higher than or equal to the second voltage level and lower than or equal to the particular voltage level in response to applying the first plurality of programming pulses to the control gates of the plurality of memory cells;
wherein a lowest voltage level of the first range of voltage levels is lower than or equal to a highest voltage level of the second range of voltage levels;
wherein the first subset of memory cells comprises each memory cell of the plurality of memory cells having its respective data state higher than or equal to a first particular data state of the plurality of data states that is lower than a highest data state of the plurality of data states; and
wherein the second subset of memory cells comprises each memory cell of the plurality of memory cells having its respective data state higher than a lowest data state of the plurality of data states and lower than or equal to a second particular data state of the plurality of data states that is lower than the first particular data state.