Patent ID: 11953629
Assignee: GUANGZHOU TYRAFOS SEMICONDUCTOR TECHNOLOGIES CO., LTD
Field: Measurement (Instruments)
Classification: CPC G  H | IPC G  H

Claim 16:
17. The ranging method as claimed in claim 12, wherein the counting circuit further comprises:
a plurality of delay units, wherein a plurality of first terminals of the delay units are coupled to the second terminal of the second switches;
a plurality of flip-flops, wherein a plurality of clock signal input terminals of the flip-flops are coupled to the second terminal of the second switches, and a plurality of data input terminals of the flip-flops are coupled to a reference voltage;
a plurality of first AND gates, wherein a plurality of first input terminals of the first AND gates are coupled to a plurality of data output terminals of the flip-flops;
a plurality of inverters, wherein a plurality of input terminals of the inverters are respectively coupled to a plurality of data output terminals of the inverters at a next level, and a plurality of output terminals of the inverters are coupled to a plurality of second input terminals of the first AND gates; and
a plurality of second AND gates, wherein a plurality of first input terminals of the second AND gates are coupled to a plurality of data output terminals of the first AND gates, a plurality of second input terminals of the second AND gates are coupled a plurality of second terminals of the delay units, and a plurality of output terminals of the second AND gates are coupled to the counting units.