Patent ID: 11948921
Assignee: nan
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. The method of claim 8, further comprising:
laminating a polymer film over an active surface of a singulated semiconductor die devoid of through silicon vias (TSVs);
forming through polymer via holes to expose bond pads of the singulated semiconductor die devoid of TSVs;
filling the through polymer via holes of the polymer film laminated to the singulated semiconductor die devoid of TSVs with conductive material; and
inverting the singulated semiconductor die devoid of TSVs and stacking the singulated semiconductor die devoid of TSVS on the at least one other singulated semiconductor die with the polymer film of the singulated semiconductor die devoid of TSVs in contact with the at least one other singulated semiconductor die and the conductive material-filled through polymer via holes of the singulated semiconductor die devoid of TSVs aligned with terminal pads of the at least one other singulated semiconductor die.