Patent ID: 11971829
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A non-volatile memory device, comprising:
a control circuit configured to connect to one or more planes of non-volatile memory cells, the control circuit comprising:
a first cache buffer configured to store data read from a first of the one or more planes;
an input-output interface configured to convert data from a parallel format to a serial format and provide the serial format data to an external data bus;
an internal data bus configured to transfer data from the first cache buffer to the input-output interface in the parallel format; and
a compression circuit configured to compress data transferred from the internal data bus to the input-output interface,

wherein the control circuit is configured to:
read a page of hard bit data and corresponding soft bit data from the first plane and store the read page of hard bit data and corresponding soft bit data in the first cache buffer; and
transfer the page of hard bit data and corresponding soft bit data over the internal data bus in a parallel format from the first cache buffer to the input-output interface along a first path for the page of hard bit data and along a second path for the corresponding soft bit data, the second path including compressing the corresponding soft bit data in the compression circuit.