Patent ID: 11910587
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 7:
8. An apparatus, comprising:
a first memory cell and a second memory cell, the first memory cell comprising:
a first storage unit comprising n-type transistors formed in a first n-plus (NP) region and p-type transistors formed in a first p-plus (PP) region between the first NP region and a second NP region;
a plurality of first write access transistors formed in the first NP region or in the first PP region; and
a plurality of first read access transistors formed in the second NP region;

wherein a first write port is laid out in the first NP region of the first memory cell and a first read port laid out in the second NP region of the first memory cell, the first read port being separated from the first write port by a second write port of the second memory cell.