Patent ID: 11894421
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A device comprising:
a first silicon-containing channel region disposed over a substrate;
a first gate structure wrapping around the first silicon-containing channel region;
a first epitaxial source/drain feature disposed over the substrate and associated with the first silicon-containing channel region; and
a first electrically insulating layer disposed under and interfacing with the first epitaxial source/drain feature and the first silicon-containing channel region, wherein the first electrically insulating layer extends from under the first epitaxial source/drain feature towards the first silicon-containing channel region such that the thickness of the first electrically insulating layer decreases as the first epitaxial source/drain feature extends towards the first silicon-containing channel region.