Patent ID: 11868258
Assignee: APPLE INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. An apparatus comprising:
a directory configured to track at least: (i) which of a plurality of coherent agent circuits is caching copies of a plurality of cache blocks in a memory, and (ii) states of the cached copies in the plurality of coherent agent circuits; and
a coherency controller circuit coupled to the directory, wherein based on a first request for a first cache block by a first agent circuit of the plurality of coherent agent circuits, the coherency controller circuit is configured to:
read an entry corresponding to the first cache block from the directory, and
issue a message to a second agent circuit of the plurality of coherent agent circuits that has a cached copy of the first cache block according to the entry, wherein the message requests a state change in the state of the cached copy in the second agent circuit, and
include an identifier of a first state of the first cache block in the second agent circuit in the message.