Patent ID: 11961585
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G  H

Claim 9:
10. A memory device comprising:
a centralized command and address (CA) interface region including two or more CA input circuits operably coupled to two or more CA input signals;
wherein at least two of the two or more CA input circuits are configured in CA pairs and each CA pair comprises:
a first CA input circuit and a second CA input circuit adjacently arranged in a mirror relationship; and
a swap circuit configured to:
select for a first operation, one of a first CA output and a second CA output for a first internal CA signal and the other of the first CA output and the second CA output for a second internal CA signal responsive to a control signal being in a first state; and
select, for a second, different operation, the one of the first CA output and the second CA output for the second internal CA signal and the other of the first CA output and the second CA output for the first internal CA signal responsive to the control signal being in a second, different state;

wherein the centralized CA interface region:
is configured in a layout arrangement such that the two or more CA input circuits comprises eight CA input circuits adjacently arranged in a two-by-four matrix; and
includes a clock buffer circuit adjacent to at least one of the two or more CA input circuits.