Patent ID: 11955548
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. An integrated chip, comprising:
an interconnect structure disposed over a substrate comprising a lower metal layer and an upper metal layer stacked over the lower metal layer; and
a ferroelectric field-effect transistor (FeFET) device inserted between the lower metal layer and the upper metal layer, comprising:
a gate electrode disposed on the lower metal layer;
a ferroelectric layer disposed on the gate electrode;
an oxide semiconductor (OS) channel layer disposed over the ferroelectric layer, the OS channel layer having a first doping type;
a pair of source/drain regions disposed on opposite sides of the OS channel layer; and

a two-dimensional (2D) contacting layer separating the pair of source/drain regions and the OS channel layer, the 2D contacting layer having a second doping type different than the first doping type;
wherein the 2D contacting layer is a monolayer or multilayer two-dimensional material consisting of a single layer of atoms that contacts the pair of source/drain regions and the OS channel layer.