Patent ID: 11972112
Assignee: DELL PRODUCTS L.P.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. A system for implementing read operations on a storage engine having two compute nodes, each compute node having a separate PCIe root complex and a memory connected to the PCIe root complex, the two root complexes being interconnected by a non-transparent bridge, comprising:
one or more computers and one or more storage devices storing instructions that are operable, when executed by the one or more computers, to cause the one or more computers to perform operations comprising:
receiving a host read operation by a host IO device on one of the compute nodes, the one of the compute nodes being a local compute node to the host IO device;
determining a physical address for the host read operation, the physical address for the host read operation being a local memory address of the memory connected to the PCI root complex of the local compute node or being a peer memory address of the memory connected to the PCIe root complex of the peer compute node;
in response to a determination that the physical address is the local memory address, generating a transaction layer packet addressed to the address in local memory and directly implementing the read operation from the local memory; and
in response to a determination that the physical address is the peer memory address, generating a transaction layer packet addressed to the address in peer memory, forwarding the transaction layer packet over the non-transparent bridge to the PCIe root complex of the peer compute node, and directly implementing the read operation from the peer memory.