Patent ID: 11961548
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 18:
19. A method of operating a memory device including a plurality of memory cell rows, the method comprising:
detecting a first hammer address and a second hammer address by monitoring the number of accesses of addresses for the memory cell rows;
storing the first hammer address as a row hammer address of memory cell rows having the number of accesses equal to or more than a predetermined number of times or having a relatively higher number of accesses as compared with other access addresses during a first row hammer monitoring time frame;
storing the second hammer address as a malicious row hammer address of memory cell rows accessed at random sampling time points during a second row hammer monitoring time frame, and being the same as the row hammer address;
counting the number of malicious row hammer addresses;
performing a refresh operation on a memory cell row physically adjacent to a memory cell row corresponding to the row hammer address; and
performing a refresh operation on a memory cell row physically adjacent to a memory cell row corresponding to the malicious row hammer address when the counted number of malicious row hammer addresses exceeds a threshold value.