Patent ID: 11917603
Assignee: QUALCOMM INCORPORATED
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 18:
19. The apparatus of claim 18, wherein, responsive to determining that the first number of coded bits after the rate matching for the first PUCCH repetition and the second number of coded bits after rate matching for the second PUCCH repetition would result in the same mother polar code length for both the first and the second PUCCH repetitions, the at least one processor is further configured to:
perform the polar encoding by performing a same polar encoding on the information bits of the UCI for the first PUCCH repetition and for the second PUCCH repetition based on the same mother polar code length, and
perform the rate matching by performing rate matching for the first PUCCH repetition based on the first number of coded bits and, separately, performing rate matching for the second PUCCH repetition based on the second number of coded bits.