Patent ID: 11907529
Assignee: PHISON ELECTRONICS CORP.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. A memory storage device, comprising:
a connection interface unit, used to couple to a host system;
a rewritable non-volatile memory module; and
a memory control circuit unit, coupled to the connection interface unit and the rewritable non-volatile memory module, wherein
the memory control circuit unit is used to:
obtain a first weight value corresponding to a first command in a command queue, wherein the command queue is used to store at least one command to be executed;
obtain a second weight value corresponding to at least one second command being executed;
in response to a sum of the first weight value and the second weight value being greater than a base value, delay an execution of the first command;
after delaying the execution of the first command, obtain a third weight value corresponding to a third command in the command queue, wherein the third command is used to execute a second operation on a second memory module in the idle state among a plurality of memory modules; and
in response to a sum of the third weight value and the second weight value being not greater than the base value, execute the third command

wherein the rewritable non-volatile memory module comprises the plurality of memory modules, and the first command is used to execute a first operation on a first memory module in an idle state among the memory modules.