Patent ID: 11917684
Assignee: LG ELECTRONICS INC.
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. An apparatus, comprising:
at least one memory; and
at least one processor being operatively connected to the at least one memory,
wherein the processor is configured to:
determine a contention window size (CWS) as a first CWS value; and
perform a channel access procedure for a first channel based on the first CWS value,
wherein the channel access procedure comprises:
i) setting a value for a counter (N) as Ninit, where Ninit is a random number between 0 and the determined CWS, wherein the determined CWS is based on a channel access priority class signaled to the apparatus,
ii) sensing a channel for an additional sensing slot duration,
iii) based on the additional sensing slot duration being idle, N being larger than 0, and the terminal choosing to decrement the counter, setting N equal to N−1, and
iv) transmitting a signal through the channel after N is zero, and
wherein, based on a transmission history of a second channel to be reflected in the determining of the CWS being absent for a specific time duration, the CWS is changed from the first CWS value to a second CWS value which is a minimum CWS value in a specific channel access priority class (CAPC).