Patent ID: 11869568
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. The memory system of claim 12,
wherein the target address generation circuit and a first refresh control circuit of the refresh control circuit, corresponding to the first memory bank, are in a first row area located on one side of the right and left sides of the first memory bank,
wherein a first column repair circuit of the column repair circuit, corresponding to the first memory bank, is in a first column area located on one side of the top and bottom sides of the first memory bank,
wherein a second refresh control circuit of the refresh control circuit, corresponding to the second memory bank, is in a second row area located on one side of the right and left sides of the second memory bank,
wherein a second column repair circuit of the column repair circuit, corresponding to the second memory bank, is in a second column area located on one side of the top and bottom sides of the second memory bank, and
wherein the second cell mat is located closer to the first row area than the first cell mat.