Patent ID: 11973079
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 10:
11. A method for forming an integrated chip (IC), the method comprising:
forming a stack of semiconductor layers over a semiconductor substrate, wherein the stack of semiconductor layers comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers;
forming a masking structure over the stack of semiconductor layers and the semiconductor substrate, wherein the masking structure comprises a plurality of masking layers;
forming a plurality of mandrel structures over the masking structure, wherein the plurality of mandrel structures includes a first mandrel structure that overlies the stack of semiconductor layers and a second mandrel structure that is laterally offset from the stack of semiconductor layers by a non-zero distance;
forming a first sidewall spacer structure along opposing sidewalls of the first mandrel structure and a second sidewall spacer structure along opposing sidewalls of the second mandrel structure;
forming a first protection layer over the second mandrel structure;
performing a first patterning process according to the first protection layer to remove the first sidewall spacer structure;
forming a second protection layer over the first mandrel structure;
performing a second patterning process according to the second protection layer to remove the second mandrel structure;
performing a third patterning process according to the first mandrel structure and the second sidewall spacer structure to remove portions of the masking structure, thereby defining a first stack of masking layers over the stack of semiconductor layers with a first width and a second stack of masking layers laterally offset from the stack of semiconductor layers with a second width less than the first width; and
performing a fourth patterning process on the semiconductor substrate and the stack of semiconductor layers according to the first and second stack of masking layers, thereby defining a first fin structure laterally adjacent to a second fin structure, wherein the first fin structure has the first width and the second fin structure has the second width, and wherein the stack of semiconductor layers directly overlies the first fin structure.