Patent ID: 11908821
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An integrated circuit (IC) package, comprising:
a level of metallization structures spaced apart within an area of the package;
a dielectric material over the level of metallization structures, wherein a first of the level of metallization structures comprises a bond pad on an embedded multichip interconnect bridge (EMIB) embedded within the dielectric material;
a plurality of first bond pad structures within the area of the package, wherein each of the first bond pad structures extends over a portion of the dielectric material, and comprises an integral via that is adjacent to a sidewall of the dielectric material and is in contact with a corresponding one of the level of metallization structures;
an IC die comprising a plurality of second bond pad structures within an area of the IC die; and
a plurality of interconnect structures that couple the first bond pad structures to the second bond pad structures.