Patent ID: 11960987
Assignee: GUOBIAO ZHANG
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 6:
7. The 3-D processor according to claim 3, wherein:
said first and second dice are vertically stacked; or,
said first and second dice are face-to-face bonded; or,
said first and second dice have a same die size; or,
a first edge of said first die is aligned with a second edge of said second die; or,
the projection of said 3D-M array on said second die at least partially overlaps said non-memory circuit; or,
each 3D-M array is vertically aligned and communicatively coupled with a non-memory circuit; or,
each non-memory circuit is vertically aligned and communicatively coupled with at least a 3D-M array; or,
the pitch of said non-memory circuit is an integer multiple of the pitch of said 3D-M array; or,
said inter-die connections include bond wires, micro-bumps, through-silicon-vias (TSV's), and/or vertical interconnect access (VIA's).