Patent ID: 11894457
Assignee: JOULWATT TECHNOLOGY CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. The manufacturing method according to claim 9, wherein the step of forming the gate structure comprises:
forming a first trench structure and a second trench structure by etching at a side of the well region, wherein the side of the well region is adjacent to said drain-end doped region;
forming a gate oxide layer on inner walls of the first trench structure and the second trench structure;
forming a polysilicon layer on the gate oxide layer, to form a first trench gate and a second trench gate;
forming a gate oxide layer and a polysilicon layer sequentially on a surface of the semiconductor device, which is obtained after forming the first trench gate and the second trench gate; and
forming a planar gate on an upper portion between the first trench gate and the second trench gate by etching the gate oxide layer and the polysilicon layer.