Patent ID: 11908507
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 7:
8. The semiconductor memory device according to claim 7, wherein the row address comprises a first row address to a fourth row address, and
wherein the row decoder comprises:
a selector configured to select the row address in response to the active command and select the refresh row address in response to the refresh command or the hammer refresh command, to generate the first row address to the fourth row address;
a block selection signal generator configured to decode the first row address to generate a plurality of block selection signals for selecting the plurality of memory cell array blocks;
a plurality of first decoders configured to decode the first row address in response to at least one among the plurality of block selection signals so as to generate a plurality of main word line selection signals for selecting the plurality of main word lines; and
a plurality of second decoders configured to decode the second row address in response to at least one among the plurality of block selection signals to generate a plurality of selection signals for selecting the plurality of selection signal lines, and
wherein the fourth row address is the page selection signal.