Patent ID: 11955488
Assignee: CAMBRIDGE GAN DEVICES LIMITED
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 19:
20. A method of manufacturing a III-nitride semiconductor based heterojunction power device, the method comprising:
forming a substrate;
forming a first III-nitride semiconductor region formed over the substrate, wherein the first III-nitride semiconductor region comprises a first heterojunction comprising at least one two-dimensional carrier gas of second conductivity type;
forming a first terminal operatively connected to the first III-nitride semiconductor region;
forming a second terminal laterally spaced from the first terminal and operatively connected to the first III-nitride semiconductor region; and
forming a first gate region over the first III-nitride semiconductor region;
forming a second III-nitride semiconductor region formed over the substrate, wherein the second III-nitride semiconductor region comprises a second heterojunction comprising at least one two-dimensional carrier gas of second conductivity type;
forming a third terminal operatively connected to the second III-nitride semiconductor region;
forming a fourth terminal laterally spaced from the third terminal in a first dimension and operatively connected to the second III-nitride semiconductor region;
forming a first plurality of highly doped semiconductor regions of the first conductivity type over the second III-nitride semiconductor region, between the third terminal and the fourth terminal; and
forming a second gate region over the first plurality of highly doped semiconductor regions,
wherein one of the first and second heterojunction transistors is an enhancement mode field effect transistor and the other of the first and second heterojunction transistors is a depletion mode field effect transistor;
wherein the first heterojunction transistor further comprises at least one highly doped semiconductor region of the first conductivity type formed over the first III-nitride semiconductor region, the at least one highly doped semiconductor region formed between the first terminal and the second terminal, and
wherein the first gate region is formed over the at least one highly doped semiconductor region.