Patent ID: 11860227
Assignee: SYNOPSYS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A method for delay estimation, the method comprising:
receiving a plurality of logic blocks of a DUT;
identifying a combinatorial path based on the DUT, the combinatorial path connecting one or more logic blocks of the plurality of logic blocks;
generating a feature vector including values of one or more orthogonal features representing characteristics of the combinatorial path;
applying a pre-trained machine learning delay model to the feature vector to determine a wire delay of the combinatorial path, the pre-trained machine learning delay model trained using (1) values of the one or more orthogonal features representing the characteristics of a plurality of combinatorial paths, and (2) measured wire delays of the plurality of combinatorial paths;
generating, by a processor, a timing graph based on the delay of the combinatorial path; and
providing the timing graph to a compiler for performance of placement and routing of the DUT.