Patent ID: 11868813
Assignee: HT RESEARCH INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 36:
37. A computer system comprising:
a fifth execution pylon; and
a fifth fail-over pylon coupled to the fifth execution pylon through a fifth workgroup fail-over link, wherein the fifth fail-over pylon is configured to provide real time fail-over support to the fifth execution pylon, wherein the fifth fail-over pylon includes a fifth fail-over communication link,
wherein the fifth execution pylon comprises:
a fifth top control block;
a fifth mid-memory block coupled to the fifth top control block through a fifth plurality of first workgroup execution links; and
a fifth base attribute block coupled to the fifth mid-memory block through a fifth plurality of second workgroup execution links;

wherein the fifth base attribute block comprises:
a plurality of fourth execution pylons; and
a third plurality of third execution pylons disposed between the fifth mid-memory block and the plurality of the fourth execution pylons, wherein each of the third plurality of the third execution pylons in the fifth base attribute block is coupled to the fifth mid-memory block through the fifth plurality of second workgroup execution links,

wherein the fifth top control block comprises a fourth plurality of the third execution pylons, wherein each of the fourth plurality of the third execution pylons in the fifth top control block is coupled to the fifth mid-memory block through the fifth plurality of first workgroup execution links,
wherein each of the third execution pylons comprises:
a third top control block;
a third mid-memory block coupled to the third top control block through a third plurality of first workgroup execution links; and
a third base attribute block coupled to the third mid-memory block through a third plurality of second workgroup execution links;

wherein the third base attribute block comprises:
an array execution pylon coupled to the third mid-memory block through the third plurality of second workgroup execution links;
a matrix execution pylon coupled to the third mid-memory block through the third plurality of second workgroup execution links; and
a tie execution pylon coupled to the third mid-memory block through the third plurality of second workgroup execution links,

wherein the fourth execution pylon comprises:
a fourth top control block;
a fourth mid-memory block coupled to the fourth top control block through a fourth plurality of first workgroup execution links; and
a fourth base attribute block coupled to the fourth mid-memory block through a fourth plurality of second workgroup execution links;
wherein the fourth top control block comprises a first plurality of the third execution pylons, wherein each of the first plurality of the third execution pylons in the fourth top control block is coupled to the fourth mid-memory block through the fourth plurality of first workgroup execution links;
wherein the fourth base attribute block comprises a second plurality of the third execution pylons, wherein each of the second plurality of the third execution pylons in the fourth base attribute block is coupled to the fourth mid-memory block through the fourth plurality of second workgroup execution links.