Patent ID: 11862288
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A memory system, comprising:
a memory controller;
a plurality of memory chips, each of the memory chips including a first pad and a second pad;
a first conductive line commonly connecting the first pad of each memory chip to the memory controller; and
a second conductive line commonly connecting the second pad of each memory chip to the memory controller, wherein
each of the memory chips receives a first signal at the first pad from the memory controller through the first conductive line, and receives a second signal at the second pad from the memory controller through the second conductive line, and
in response to an assertion of the second signal over the second conductive line and a transmission of the first signal over the first conductive line during a time period that starts with the assertion of the chip enable signal and is prior to receipt of a command sequence, one of the memory chips enters a chip enabled state and the remainder of the memory chips enters a chip disenabled state.