Patent ID: 11947474
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory module comprising:
an address buffer circuit;
a command/address channel; and
a memory rank controlled by the address buffer circuit via the command/address channel, the memory rank including a plurality of memory components where each memory component comprises:
a respective plurality of memory component data ports;
a respective memory core to store data; and
a respective data interface to transfer data between the respective memory core and the respective plurality of memory component data ports, the respective data interface supporting a first data width mode in which the respective data interface transfers data at a first bit width and a first burst length via a first set of the respective plurality of memory component data ports, the respective data interface supporting a second data width mode in which the respective data interface transfers data at a second bit width and a second burst length via a second set of the respective plurality of memory component data ports; and
a respective data path between the respective data interface and the respective memory core, the respective data path having a third bit width that is greater than the first bit width of the first data width mode and the second bit width of the second data width mode;

a plurality of memory module data pins to transfer the data between the plurality of memory component data ports and a memory controller.