Patent ID: 11963299
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 9:
10. A method of operating a command and address (CA) buffer device of a first memory module comprising a plurality of device sites, each device site, of the plurality of device sites, being a location on a circuit board at which at least one respective memory device is disposed, the method comprising:
receiving, at a first terminal of a primary interface of the CA buffer device, a first chip select (CS) signal from a memory controller;
receiving, at a second terminal of the primary interface, a second CS signal from a second memory module;
when the first CS signal is received on the first terminal, selecting on a secondary interface of the CA buffer device a first set of one or more of a plurality of device sites; and
when the second CS signal is received on the second terminal, selecting a second set of one or more of the plurality of device sites.