Patent ID: 11949510
Assignee: QUALCOMM INCORPORATED
Field: Digital communication (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 6:
7. The computing device of claim 1, wherein the copy engine further comprises:
a memory-mapped subsystem configured to:
generate a first status ring descriptor including the first CRC value and a first status bit;
generate a second status ring descriptor including the second CRC value and a second status bit;
set the first status bit in response to the first stream-wise CRC engine generating the first CRC value; and
set the second status bit in response to the second stream-wise CRC engine generating the second CRC value,

wherein the copy engine is further configured to:
transmit the first stream-wise CRC message via the interface bus in response to the memory-mapped subsystem setting the first status bit; and
transmit the second stream-wise CRC message via the interface bus in response to the memory-mapped subsystem setting the second status bit.