Patent ID: 11868796
Assignee: RED HAT, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A system comprising:
a memory comprising a plurality of memory addresses on a host system; and
a hypervisor configured to execute on one or more processors to:
generate a page table associated with the memory;
in response to receiving a write-protection command to prevent write-access to data from a portion of the memory, write-protect a first range of memory addresses comprising the data write protected from the portion of the memory, wherein a second range of memory addresses comprises data not write protected in the memory; and
modify the page table to include a page table entry associated with the first range of memory addresses being write-protected, wherein write access to a memory address in the first range of memory addresses by a device during write-protection is tracked.