Patent ID: 11881276
Assignee: SK HYNIX INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H  Y | IPC G  H

Claim 0:
1. An error correcting code (ECC) decoder, comprising:
a memory comprising a memory region;
a first converter configured to transmit a hard bit, received from a channel, to the memory to store the hard bit in a first area of the memory region;
a second converter configured to receive the hard bit read from the first area and output a reliability value corresponding to the hard bit, whenever a hard decoding operation on the hard bit is iterated; and
a variable node configured to perform the hard decoding operation using the reliability value,
wherein the second converter decides a sign of the reliability value according to the hard bit, decides a fixed value as a magnitude of the reliability value, and outputs the reliability value to the variable node.