Patent ID: 11950434
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 0:
1. A method for forming an integrated chip, the method comprising:
depositing a data storage layer over a first conductive layer;
patterning the data storage layer to form a first line structure and a second line structure that are elongated in a first direction;
patterning the first conductive layer to form a first word line and a second word line that are elongated in the first direction and that respectively underlie the first and second line structures;
depositing a first dielectric layer between the first line structure and the second line structure, and between the first word line and the second word line; and
patterning the first line structure and the second line structure to form a first memory cell from the first line structure and to form a second memory cell from the second line structure,
wherein depositing the first dielectric layer forms a void within the first dielectric layer and laterally between the first memory cell and the second memory cell.