Patent ID: 11947462
Assignee: APPLE INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. A method, comprising:
performing, by execution circuitry of a computing device, operations for instructions from multiple threads in parallel;
caching, by the computing device in a cache, information operated on by threads executed by the execution circuitry;
arbitrating, by the computing device, among threads to schedule threads for execution by the execution circuitry;
determining, by the computing device, one or more performance metrics for the cache;
reducing, by the computing device based on the one or more performance metrics meeting a threshold, a limit on a number of threads considered for arbitration, to control a footprint of cached information; and
based on a bypass indicator for a thread, the computing device considering the thread for scheduling regardless of the limit on the number of threads, wherein the considering allows the number of threads concurrently executed to exceed the reduced limit on the number of threads during a portion of execution of the thread.