Patent ID: 11901345
Assignee: SK HYNIX INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. The semiconductor package according to claim 3,
wherein the second internal channel pad includes a plurality of second internal channel pads arranged along a first side surface of the first buffer chip facing the first memory chip,
wherein the second redistribution line includes a plurality of second redistribution lines connected to the plurality of second internal channel pads, respectively,
wherein a plurality of redistribution pads provided at end portions of the plurality of second redistribution lines, respectively, are arranged along a direction parallel to the first side surface of the first buffer chip,
wherein at least one of the plurality of second redistribution lines includes horizontal portions substantially parallel to the first side surface of the first buffer chip, and
wherein, when a number of the horizontal portions disposed between the second internal channel pad and the redistribution pad is M, where M is a natural number equal to or greater than 2, a width of the second redistribution line is W2, and a distance between adjacent horizontal portions is S2, a distance between the second internal channel pad and the redistribution pad has a value greater than M*W2+(M+1)*S2.