Patent ID: 11868813
Assignee: HT RESEARCH INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 23:
24. A computer system comprising:
a fourth execution pylon; and
a fourth fail-over pylon coupled to the fourth execution pylon through a fourth workgroup fail-over link, wherein the fourth fail-over pylon is configured to provide real time fail-over support to the fourth execution pylon, wherein the fourth fail-over pylon includes a fourth fail-over communication link,
wherein the fourth execution pylon comprises:
a fourth top control block;
a fourth mid-memory block coupled to the fourth top control block through a fourth plurality of first workgroup execution links; and
a fourth base attribute block coupled to the fourth mid-memory block through a fourth plurality of second workgroup execution links;

wherein the fourth top control block comprises a first plurality of third execution pylons, wherein each of the first plurality of the third execution pylons in the fourth top control block is coupled to the fourth mid-memory block through the fourth plurality of first workgroup execution links;
wherein the fourth base attribute block comprises a second plurality of the third execution pylons, wherein each of the second plurality of the third execution pylons in the fourth base attribute block is coupled to the fourth mid-memory block through the fourth plurality of second workgroup execution links,
wherein each of the third execution pylons comprises:
a third top control block;
a third mid-memory block coupled to the third top control block through a third plurality of first workgroup execution links; and
a third base attribute block coupled to the third mid-memory block through a third plurality of second workgroup execution links;

wherein the third base attribute block comprises:
an array execution pylon coupled to the third mid-memory block through the third plurality of second workgroup execution links;
a matrix execution pylon coupled to the third mid-memory block through the third plurality of second workgroup execution links; and
a tie execution pylon coupled to the third mid-memory block through the third plurality of second workgroup execution links.