Patent ID: 11956970
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 17:
18. A method, comprising:
performing an access operation on a row of memory cells of a level above a substrate of a memory die, wherein the access operation comprises:
biasing a word line to activate a plurality of first transistors of the level above the substrate for coupling a respective storage element of each memory cell of the row of memory cells with each digit line of a plurality of digit lines;
biasing a first activation line to deactivate a plurality of second transistors of the level above the substrate for disconnecting a respective digit line of a first set of digit lines of the plurality of digit lines from a first plate node; and
biasing a second activation line to deactivate a plurality of third transistors of the level above the substrate for disconnecting a respective digit line of a second set of digit lines of the plurality of digit lines from a second plate node.