Patent ID: 11972034
Assignee: AMAZON TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A system, comprising:
a hardware processor and memory;
a cache controller configured to utilize a plurality of security keys, comprising a first security key and a second security key different from the first security key, to perform respective memory accesses, including a first access and a second access, for respective ones of a plurality of different threads comprising a first thread of execution and a second thread of execution, wherein the first thread of execution is a member of a first security group, wherein the second thread of execution is a member of a second security group, and wherein to utilize the plurality of security keys the cache controller is configured to:
receive a first access to an address of the memory from the first thread of execution executing on the hardware processor and associated with the first security group, and responsive to the receiving the first access:
identify the first security key according to an identifier of the first security group;
scramble a portion of the address of the memory according to the selected first security key using a first scrambling function to generate a first index; and
identify a first set of candidate cache locations mapping to the address of the memory using the generated first index; and

receive second access to another address of the memory from the second thread of execution executing on the hardware processor and associated with the second security group, and responsive to the receiving the second access:
identify the second security key according to an identifier of the second security group;
scramble the portion of the other address of the memory according to the selected second security key using the first scrambling function to generate a second index; and
identify a second set of candidate cache locations mapping to the address of the memory using the generated second index, wherein the second security key differs from the first security key, wherein the second index differs from the first index according to a difference between the second security key and the first security key, and wherein the second set of candidate cache locations differs from the first set of candidate cache locations.