Patent ID: 11907680
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. The MAC operator of claim 1, wherein the mantissa pre-processing circuit includes:
a first shifting circuit that performs first shifting on the plurality of mantissa data of the plurality of multiplication data to generate and output a plurality of shifted mantissa data;
a negative number processing circuit that receives a plurality of sign data of the plurality of multiplication data and the plurality of shifted mantissa data to output each of the plurality of shifted mantissa data or 2's complement of each of the plurality of shifted mantissa data as each of a plurality of intermediate mantissa data according to a value of each of the plurality of sign data; and
a second shifting circuit that performs second shifting on the plurality of intermediate mantissa data by a value of each of the plurality of shift data to generate and output the plurality of pre-processed mantissa data.