Patent ID: 11894811
Assignee: HUAWEI TECHNOLOGIES CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An operational amplifier, comprising:
a first amplifying unit;
a second amplifying unit coupled to the first amplifying unit;
a current source coupled to the first amplifying unit and comprising:
a first current source end; and
a second current source end;

a first compensation capacitor coupled to the second amplifying unit;
a second compensation capacitor coupled to the second amplifying unit;
a first input end coupled to the first current source end;
a second input end;
a first voltage input end coupled to the first amplifying unit and the second amplifying unit, wherein the first voltage input end is a first differential voltage signal input end; and
a second voltage input end coupled to the first amplifying unit and the second amplifying unit, wherein the second voltage input end is a second differential voltage signal input end,
wherein the first amplifying unit comprises:
a first transistor coupled to the first voltage input end and comprising:
a first source coupled to the second current source end;
a first gate; and
a first drain;

a second transistor coupled to the second voltage input end and comprising:
a second source coupled to the second current source end;
a second gate; and
a second drain;

a third transistor comprising:
a third source coupled to the second input end;
a third gate; and
a third drain; and

a fourth transistor comprising:
a fourth source coupled to the second input end;
a fourth gate coupled to the gate of the third transistor; and
a fourth drain,

wherein the second amplifying unit comprises:
a fifth transistor coupled to the second voltage input end and comprising:
a fifth source coupled to the first voltage end;
a fifth gate; and
a fifth drain coupled to the first compensation capacitor, wherein the fifth drain is a first differential voltage signal output end and configured to output a first signal;

a sixth transistor coupled to the first voltage input end and comprising:
a sixth source coupled to the first voltage end;
a sixth gate; and
a sixth drain coupled to the second compensation capacitor, wherein the sixth drain is a second differential voltage signal output end and configured to output a second signal that is different from the first signal;

a seventh transistor comprising:
a seventh source coupled to the second input end;
a seventh gate coupled to the second drain, the fourth drain, and the second compensation capacitor; and
a seventh drain coupled to the first compensation capacitor; and

an eighth transistor comprising:
an eighth source coupled to the second input end;
an eighth gate directly coupled to the first drain, the third drain, and the first compensation capacitor; and
an eighth drain coupled to the second compensation capacitor.