Patent ID: 11914481
Assignee: NETLIST, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory system having programmable reliability levels, the memory system comprising:
a non-volatile memory (NVM) subsystem comprising a plurality of blocks each including a plurality of pages, each page including a plurality of NVM cells and configured to store an associated number of bytes;
a plurality of programmable registers including first and second programmable threshold registers configured to store first and second programmable threshold values, respectively, wherein the second programmable threshold value is less than the first programmable threshold value; and
a controller coupled to the NVM subsystem and the plurality of programmable registers including the first and second programmable threshold registers, the controller configured to determine if operation reliability for a first memory portion of the NVM subsystem has reached first or second reliability levels,
wherein the first memory portion is a page or a block of the NVM subsystem,
wherein the operation reliability for the first memory portion reaches the first reliability level when a first parameter for the first memory portion matches or exceeds the first programmable threshold value,
wherein the operation reliability for the first memory portion reaches the second reliability level when the first parameter matches or exceeds the second programmable threshold value,
wherein, in response to the operation reliability for the first memory portion reaching the first reliability level, the controller is further configured to perform a first remediation action, and
wherein, in response to the operation reliability for the first memory portion reaching the second reliability level, the controller is further configured to perform a second remediation action.