Patent ID: 11893271
Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 1:
2. The computing-in-memory circuit according to claim 1, wherein each memory cell is configured to store a data of two bits, and the RRAM array comprises M word lines, N first bit lines, N second bit lines, N first source lines, N second source lines, and memory cells of M rows and N columns, wherein M and N are positive integers;
wherein each memory cell comprises a first unit and a second unit, the first unit comprises a first switch and a first memristor, and the second unit comprises a second switch and a second memristor;
wherein a control end of the first switch serves as a first end of the memory cell, one end of the first switch serves as a second end of the memory cell, another end of the first switch is connected to one end of the first memristor, another end of the first memristor serves as a third end of the memory cell, a control end of the second switch serves as a fourth end of the memory cell, one end of the second switch serves as a fifth end of the memory cell, another end of the second switch is connected to one end of the second memristor, and another end of the second memristor serves as a sixth end of the memory cell;
wherein the first end and the fourth end of each of the memory cells located in a same row are connected to a same word line, the second end of each of the memory cells located in a same column is connected to a same first source line, the third end of each of the memory cells located in the same column is connected to a same first bit line, the fifth end of each of the memory cells located in the same column is connected to a same second source line, and the sixth end of each of the memory cells located in the same column is connected to a same second bit line.