Patent ID: 11869894
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A method of forming a stacked transistor structure, the method comprising:
receiving a workpiece comprising a semiconductor material separated from a lower transistor structure by an intervening insulator layer;
forming a semiconductor body comprising the semiconductor material;
forming a gate coupled to the semiconductor body;
forming a spacer adjacent to the gate;
forming an opening through the insulator layer and removing a portion of the semiconductor body adjacent to the spacer, the opening further exposing a terminal of the lower transistor structure;
laterally recessing a sidewall of the semiconductor body;
forming a source or drain material in contact with the sidewall of the semiconductor body; and
forming a metallization structure in the opening, the metallization structure in contact with the source or drain material, and in contact with the terminal of the lower transistor structure.