Patent ID: 11928023
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. An apparatus, comprising:
a memory device coupled with a host device; and
a controller associated with the memory device, wherein the controller is configured to cause the apparatus to:
receive, from the host device, a write command, data, and a first set of error control bits for the data, the data and the first set of error control bits being associated with the write command;
determine that the data includes an uncorrectable error using the first set of error control bits in response to receiving the data and the first set of error control bits;
generate a second set of error control bits for the data based at least in part on determining that the data includes the uncorrectable error, wherein the second set of error control bits indicate that the data received from the host device included the uncorrectable error; and
transmit, to the host device, the data and an indication that the data received from the host device included the uncorrectable error based at least in part on the second set of error control bits.