Patent ID: 11892502
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 8:
9. The integrated circuit of claim 6, wherein the output control unit comprises a third transmission gate and a fourth inverter, the third transmission gate comprising a first control terminal, a second control terminal, an input and an output, the fourth inverter comprising a first terminal and a second terminal,
wherein the first terminal of the fourth inverter is coupled to the output of the decoder, the second terminal of the fourth inverter is coupled to the first control terminal of the third transmission gate,
the second control terminal of the third transmission gate is coupled to the output of the decoder, the input of the third transmission gate is coupled to the output of the spare TSV, the output of the third transmission gate is coupled to the output of the operational TSV.