Patent ID: 11960762
Assignee: PHISON ELECTRONICS CORP.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A memory control circuit unit, configured to control a memory storage apparatus, wherein the memory storage apparatus comprises a rewriteable non-volatile memory module, the rewriteable non-volatile memory module stores a plurality of logical-to-physical address mapping tables, the memory control circuit unit comprising:
a host interface, configured to couple to a host system;
a memory interface, configured to couple to the rewriteable non-volatile memory module;
a buffer memory, coupled to the host interface and the memory interface; and
a memory management circuit, coupled to the host interface, the memory interface, and the buffer memory, wherein the memory management circuit is configured to:
receive a plurality of consecutive first commands from the host system,
calculate a command ratio of read command corresponding to a random read operation mode among the plurality of first commands and
decide whether to configure the memory storage apparatus in a first mode or a second mode according to the command ratio and a ratio threshold,
wherein the memory management circuit is further configured to configure a first buffer in the buffer memory to temporarily store the logical-to-physical address mapping table in response to the memory storage apparatus being configured in the first mode, wherein the first buffer has a first capacity, and
the memory management circuit is further configured to configure a second buffer in the buffer memory to temporarily store the logical-to-physical address mapping table in response to the memory storage apparatus being configured in the second mode, wherein the second buffer has a second capacity,
wherein the second capacity is greater than the first capacity,
the memory management circuit is further configured to adjust the ratio threshold according to an effective ratio,
wherein in response to the memory storage apparatus being configured in the second mode, the memory management circuit is further configured to configure a third buffer in the buffer memory to temporarily store data associated with a write command of the host system,
wherein the third buffer is different from the second buffer and the third buffer has a third capacity,
wherein the memory management circuit is further configured to record a total number of times of the memory storage apparatus switching from being configured in the second mode to being configured in the first mode and a number of times of the cache unit comprised in the third buffer being full during switching,
wherein the memory management circuit is further configured to obtain the effective ratio according to the number of times and the total number of times.