Patent ID: 11916133
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A structure, comprising:
a first gate structure sandwiched between and in contact with a first spacer feature and a second spacer feature;
a second gate structure sandwiched between and in contact with a third spacer feature and a fourth spacer feature;
a first gate self-aligned contact (SAC) dielectric feature over the first spacer feature and the second spacer feature;
a liner disposed between a sidewall of the first spacer feature and the first gate SAC dielectric feature and between a sidewall of the second spacer feature and the first gate SAC dielectric feature;
a second gate SAC dielectric feature over the third spacer feature, the second gate structure, and the fourth spacer feature;
a contact etch stop layer over the first gate SAC dielectric feature and the second gate SAC dielectric feature;
a source/drain contact sandwiched between the second spacer feature and the third spacer feature; and
a gate contact feature extending through the contact etch stop layer and the first gate SAC dielectric feature, and between the first spacer feature and the second spacer feature to be in contact with the first gate structure,
wherein the first gate SAC dielectric feature is in direct contact with top surfaces of the first spacer feature and the second spacer feature.