Patent ID: 11948851
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 18:
19. A semiconductor package comprising:
a wiring structure;
a semiconductor chip on the wiring structure;
a plurality of internal terminals between the wiring structure and the semiconductor chip;
a high thermal conductivity layer between the wiring structure and the semiconductor chip; and
an encapsulator on the high thermal conductivity layer and contacting the semiconductor chip,
wherein sidewalls of at least the wiring structure and the encapsulator are substantially coplanar,
at least one sidewall of the high thermal conductivity layer is coplanar to at least one of the coplanar sidewalls of the wiring structure and the encapsulator,
wherein an uppermost end of the high thermal conductivity layer is at a higher level than a lowermost end of the semiconductor chip,
wherein the uppermost end of the high thermal conductivity layer is at a lower level than an uppermost end of the semiconductor chip,
wherein the high thermal conductivity layer directly contacts a side surface of the semiconductor chip,
a maximum contact height between the high thermal conductivity layer and the semiconductor chip is a first length, a height of the semiconductor chip is a second length, and the first length is greater than half of the second length, and
an upper surface of the encapsulator includes a flat portion substantially parallel to an upper surface of the wiring structure and an inclined portion between the flat portion and the semiconductor chip.