Patent ID: 11960893
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A method of prefetching instructions in a processor, the method comprising:
detecting a branch instruction that misses in an instruction cache;
sending the branch instruction that misses in the instruction cache to an instruction prefetcher separate from a branch prediction unit, wherein the instruction prefetcher has multiple different types of branch instruction prefetch tables, wherein a first type branch instruction prefetch table of the multiple different types of branch instruction prefetch tables stores target addresses for uni-target branch instructions and a second type branch instruction prefetch table of the multiple different types of branch instruction prefetch tables stores target addresses for multi-target branch instructions;
determining whether the branch instruction that missed in the instruction cache hits in one of multiple different types of branch instruction prefetch tables in the instruction prefetcher for prefetching instructions into the instruction cache before needed for later execution in the processor;
reading, in response to the branch instruction that missed in the instruction cache hitting in one of the multiple different types of branch instruction prefetch tables in the instruction prefetcher, a target address for the branch instruction from a respective branch instruction prefetch table in which the branch instruction hit; and
prefetching the instruction at the target address for the branch instruction to the instruction cache.