Patent ID: 11967556
Assignee: nan
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for forming a microelectronic device, the method comprising:
forming a staircase structure in a stack structure comprising a vertically alternating sequence of insulative material and conductive material arranged in tiers, the staircase structure comprising steps at lateral ends of the tiers of the stack structure;
forming a fill material adjacent the staircase structure;
forming contact openings with different aspect ratios in the fill material, some of the contact openings terminating in the fill material, others of the contact openings exposing portions of the conductive material of upper tiers of the stack structure;
selectively forming additional conductive material on the portions of the conductive material in the others of the contact openings;
extending the some of the contact openings to form extended contact openings that expose portions of the conductive material of lower tiers of the stack structure; and
forming contacts in the others of the contact openings and in the extended contact openings, the contact extending through the fill material, some of the contacts extending to the additional conductive material on the portions of the conductive material of the upper tiers of the stack structure, the some of the contacts comprising a liner, the additional conductive material being between the liner and the portions of the conductive material of the upper tiers of the stack structure, and others of the contacts extending to the portions of the conductive material of the lower tiers of the stack structure.