Patent ID: 11972292
Assignee: XCONN TECHNOLOGIES HOLDINGS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A Peripheral Component Interconnect Express (PCIe) switch, comprising:
a plurality of ports through which packets ingress and egress the PCIe switch, each of the packets being divisible into a plurality of packet segments;
a memory including a plurality of banks, each of the plurality of banks having a numerical designation; and
a scheduler coupled with the plurality of ports and the memory, the scheduler configured to allocate memory to store the plurality of packet segments in the plurality of banks such that a beginning packet segment of a packet is stored in a selected bank of the plurality of banks and each subsequent packet segment in the packet is stored in ascending order of the numerical designation in a next adjacent bank of the plurality of banks, the next adjacent bank for a highest numerical designation bank being a lowest numerical designation bank, the scheduler further being configured to allocate memory segments within each of the plurality of banks such that one packet segment of the plurality of packet segments is stored in a first memory segment in a bank and for a subsequent packet segment of the plurality of packet segments stored in a second memory segment of the bank, the second memory segment can be noncontiguous to the first memory segment, wherein the allocating of the memory comprises to:
store the beginning packet segment to the selected bank;
lock the next adjacent bank for a next packet segment, wherein the locking of the next adjacent bank includes preventing a beginning segment for a new packet from being stored in the same cycle at the next adjacent bank; and
store the next packet segment in the next adjacent bank.