Patent ID: 11901286
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 12:
13. A method of generating an integrated circuit (IC) layout diagram, the method comprising:
obtaining a grid comprising grid intersections of first and second pluralities of tracks corresponding to adjacent metal layers, wherein the first and second pluralities of tracks have respective first and second pitches;
confirming that one or both of:
the first and/or second pitch is less than a minimum via spacing rule, or
a ratio of a greater one of the first or second pitches to a lesser one of the first or second pitches is less than √{square root over (3)};

applying a via positioning pattern to the grid whereby via region placement is restricted to alternating diagonal grid lines;
positioning via regions at some or all of the grid intersections of the alternating diagonal grid lines; and
generating the IC layout diagram including the via regions positioned along the alternating diagonal grid lines.