Patent ID: 11963369
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. An integrated circuit, comprising:
a plurality of bit-line stacks disposed over a substrate and respectively comprising a plurality of bit-lines stacked onto one another;
a data storage structure over the plurality of bit-line stacks;
a selector over the data storage structure;
a word-line over the selector, wherein the selector is configured to selectively allow current to pass between the plurality of bit-lines and the word-line;
wherein the plurality of bit-line stacks comprise a first bit-line stack, a second bit-line stack, and a third bit-line stack, the first bit-line stack and the third bit-line stack are closest bit-line stacks to opposing sides of the second bit-line stack; and
wherein the second bit-line stack is separated from the first bit-line stack by a first distance and is further separated from the third bit-line stack by a second distance larger than the first distance.