Patent ID: 11947379
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 3:
4. The host interface of claim 3, wherein the positive edge detector includes:
a first positive edge synchronizer that allows a first-positive synchronizer signal to toggle at a next positive edge of the internal clock signal in response to toggling of the response;
a second positive edge synchronizer that allows a second-positive synchronizer signal to toggle at a next positive edge of the internal clock signal in response to toggling of the first-positive synchronizer signal;
a third positive edge synchronizer that allows a third-positive synchronizer signal to toggle at a next positive edge of the internal clock signal in response to toggling of the second-positive synchronizer signal; and
an AND gate that performs a logical AND operation on the third-positive synchronizer signal and an inverted version of the second-positive synchronizer signal to generate the positive edge detection signal.