Patent ID: 11948897
Assignee: PSEMI CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 3:
4. A circuit fabricated on a high resistivity silicon-on-insulator (SOI) substrate as part of an integrated circuit susceptible to accumulated charge, the circuit including, the circuit including:
(a) at least one field effect transistor (FET) having a drain, a source, a gate, a VGS characteristic, and a signal path through the FET between the drain and the source;
(b) a switch coupled to the signal path of the FET, configured to selectively couple the signal path to a load or interrupt current flow through the signal path of the FET; and
(c) at least one substrate contact near at least one FET, each substrate contact comprising a resistive conduction path formed between a first contact region at a surface of a layer of the integrated circuit and a second contact region at or near a surface of the high resistivity SOI substrate, wherein each substrate contact penetrates through at least one dielectric layer;
wherein, in an active mode, the switch couples the signal path of the FET to the load; and
wherein, in a standby mode, the switch interrupts current flow through the signal path of the FET, thereby maintaining essentially the same VGS characteristic as during the active mode, and thereby eliminating or reducing changes in accumulated charge.