Patent ID: 11935613
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. A device, comprising:
a memory storing instructions; and
a processor adapted to be coupled to a Double Data Rate (DDR) flash memory by way of a Serial Peripheral Interface (SPI), the processor configured to execute the instructions stored in the memory to:
determine final largest and smallest successful values of a receive clock delay by:
determining first largest and smallest successful values of a receive clock delay at a first value of a transmit clock delay and determining second largest and smallest successful values of the receive clock delay at a second value of the transmit clock delay; and
setting the final largest successful value of the receive clock delay to a larger of the first and second largest values of the receive clock delay and setting the final smallest successful value of the receive clock delay to a smaller of the first and second smallest values of the receive clock delay;

determine final largest and smallest successful values of the transmit clock delay by:
determining first largest and smallest successful values of the transmit clock delay at a first value of the receive clock delay and determining second largest and smallest successful values of the transmit clock delay at a second value of the receive clock delay; and
setting the final largest successful value of the transmit clock delay to a larger of the first and second largest values of the transmit clock delay and setting the final smallest successful value of the transmit clock delay to a smaller of the first and second smallest values of the transmit clock delay;

set a first set of parameters for the SPI, the first set of parameters comprising the final largest value of the transmit clock delay, the final largest successful value of the receive clock delay, and a first value of a reference clock delay (RD) cycle;
set a second set of parameters for the SPI, the second set of parameters comprising the final smallest value of the transmit clock delay, the final smallest successful value of the receive clock delay, and a second value of the RD cycle;
based on a determination that the first value of the RD cycle is not equal to the second value of the RD cycle, determine an unsuccessful set of parameters that, when used by the processor, causes the SPI not to read successfully from the DDR flash memory, the unsuccessful set of parameters comprising:
one of the first value of the RD cycle and the second value of the RD cycle;
an unsuccessful value of the transmit clock delay between the final smallest successful value of the transmit clock delay and the final largest successful value of the transmit clock delay; and
an unsuccessful value of the receive clock delay between the final smallest successful value of the receive clock delay and the final largest successful value of the receive clock delay;

determine whether the first set of parameters are usable by the processor to read successfully from the DDR flash memory over a larger range of operating temperatures of the device than the second set of parameters based on a comparison of the unsuccessful set of parameters to the first set of parameters and to the second set of parameters;
select one of the first and second sets of parameters based on the determination of whether the first set of parameters is usable by the processor to read successfully from the DDR flash memory over a larger range of operating temperatures of the device than the second set of parameters; and
program the SPI using the selected one of the first and second sets of parameters.