Patent ID: 11961548
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. A memory device comprising:
a memory cell array including a plurality of memory cell rows;
a control logic circuit configured to detect:
a row hammer address of memory cell rows having the number of accesses equal to or more than a predetermined number of times or having a relatively higher number of accesses as compared with other access addresses during a first row hammer monitoring time frame, and
a malicious row hammer address of memory cell rows accessed at random sampling time points during a second row hammer monitoring time frame, and being the same as the row hammer address; and
a refresh control circuit configured to refresh a memory cell row physically adjacent to a memory cell row corresponding to the row hammer address,
wherein the control logic circuit comprises:
a first register configured to store random sampling addresses of memory cell rows accessed at the random sampling time points; and
a comparator configured to compare the row hammer address with the random sampling addresses, and output the row hammer address as the malicious row hammer address when one of the random sampling addresses is identical to the row hammer address based on a result of the comparison; and
a similarity counter circuit configured to count the number of malicious row hammer addresses, and
wherein the refresh control circuit is configured to refresh a memory cell row physically adjacent to a memory cell row corresponding to the malicious row hammer address when the counted number of malicious row hammer addresses exceeds a threshold value.