Patent ID: 11894274
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method comprising:
forming a semiconductor fin and a dummy fin protruding higher than top surfaces of isolation regions, wherein the semiconductor fin is parallel to the dummy fin;
forming a gate stack on a first portion of the semiconductor fin and a first portion of the dummy fin;
after the gate stack is formed, etching a second portion of the dummy fin, and simultaneously etching a second portion of the semiconductor fin to form a source/drain recess, wherein the second portion of the dummy fin is etched slower than the second portion of the semiconductor fin, and the etching is performed until an entirety of the second portion of the semiconductor fin is removed; and
after the second portion of the dummy fin is etched, growing an epitaxy semiconductor region based on a second portion of the semiconductor fin, wherein the epitaxy semiconductor region is grown toward the dummy fin.