Patent ID: 11869821
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A semiconductor package comprising:
a first semiconductor chip comprising a first surface and a second surface opposite to each other;
at least one second semiconductor chip stacked on the first surface of the first semiconductor chip; and
a molding layer contacting the first surface of the first semiconductor chip and a side wall of the at least one second semiconductor chip,
wherein an external side wall of the molding layer comprises:
a first external side wall portion extending with a first slope from a lower end of the molding layer adjacent to the first semiconductor chip to a first height;
a second external side wall portion extending with a second slope, which is different from the first slope, from the first height to a second height; and
a third external side wall portion extending with a third slope, which is different from the first slope and the second slope, from the second height to a third height.