Patent ID: 11870461
Assignee: MICRON TECHNOLOGY, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 9:
10. A method comprising:
obtaining a plurality of codewords, wherein each codeword is an element of an error correcting code for a memory sub-system;
assigning a plurality of dies of the memory sub-system to each codeword of the plurality of codewords, wherein a number of codewords in the plurality of codewords is equal to a number of dies in the plurality of dies;
separating each codeword of the plurality of codewords into a plurality of segments, wherein the plurality of segments are distributed across the plurality of dies of the memory sub-system;
calculating an exclusive-OR (XOR) value based on the plurality of codewords;
applying respective shifts to the plurality of segments of the plurality of codewords to arrange the plurality of segments into a first layout spread across the plurality of dies of the memory sub-system, wherein a codeword segment along a column or row of the first layout is unique; and
storing the plurality of segments of the plurality of codewords and the calculated XOR value in an error correcting (EC) layout across the plurality of dies, wherein the first layout constitutes at least a portion of the EC layout.