Patent ID: 11948848
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. An electronic package, comprising:
a substrate, the substrate comprising a dielectric layer;
a plurality of conductive traces over the substrate, wherein sidewall surfaces of the plurality of conductive traces are non-vertical, each one of the plurality of conductive traces having a first width proximate to a top portion of the conductive trace, a second width proximate to a middle portion of the conductive trace, and a third width proximate to a bottom portion of the conductive trace, the bottom portion of the conductive trace directly on the dielectric layer of the substrate, wherein the second width is smaller than the first width, and the second width is smaller than the third width; and
a plurality of metallic masks, wherein each metallic mask is over a top surface of one of the plurality of conductive traces, and wherein each metallic mask extends a distance beyond edges of the underlying one of the plurality of conductive traces, and wherein each metallic mask has a lateral width greater than a maximum lateral width of the underlying one of the plurality of conductive traces.