Patent ID: 11928415
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A method, comprising:
training a machine learning model with a plurality of electronic circuit placement layouts;
predicting, by the machine learning model, fix rates of design rule check (DRC) violations of a new electronic circuit placement layout;
identifying hard-to-fix (HTF) DRC violations among the DRC violations based on the fix rates of the DRC violations of the new electronic circuit placement layout; and
fixing, by an engineering change order (ECO) tool, the DRC violations,
wherein the training the machine learning model comprises:
extracting a plurality of feature combinations of the plurality of electronic circuit placement layouts;
calculating fix rates of DRC violations present on the plurality of electronic circuit placement layouts;
establishing a relationship between the fix rates and the plurality of feature combinations; and
normalizing the plurality of feature combinations of the plurality of electronic circuit placement layouts.