Patent ID: 11937431
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor device comprising:
a peripheral circuit area formed on a substrate;
a semiconductor layer covering the peripheral circuit area; and
a memory cell array area formed on the semiconductor layer, p1 wherein the memory cell array area comprises:
a first cell laminated structure and a second cell laminated structure on the first cell laminated structure each including a plurality of insulating layers and a plurality of word line structures alternately laminated on the semiconductor layer; and
a plurality of channel structures filling a plurality of first channel holes passing through the first cell laminated structure and a plurality of second channel holes connected to the plurality of first channel holes and passing through the second cell laminated structure,
wherein the peripheral circuit area comprises:
an active area limited by an isolation layer in the substrate;
a gate dielectric layer disposed on the active area;
a gate electrode including a lower gate layer and an upper gate layer on the lower gate layer, the lower gate layer being on the gate dielectric layer; and
a pair of impurity areas formed in portions of the active area on both sides of the gate electrode in a gate length direction,
wherein the upper gate layer covers an uppermost surface of the lower gate layer and parts of side surfaces of the lower gate layer in a gate width direction orthogonal to the gate length direction of the gate electrode, and
wherein a lowermost surface of the upper gate layer is directly on top of a portion of an uppermost surface of the isolation layer.