Patent ID: 11953990
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 4:
5. The memory system of claim 1, wherein the controller comprises;
a host controller performing an encryption operation on a data which is received from the host, organizing a third data set by adding a first parity and a second parity to the data, and outputting the third data set;
a buffer temporarily storing the third data set which is output from the host controller; and
a memory controller checking the third data set by performing a decoding operation and a syndrome check operation,
wherein the memory controller comprises:
a first ecc decoder configured to decode the third data set which is received from the buffer, and produce a fourth data set;
a first checker configured to add a low density parity check (ldpc) parity to the fourth data set by ldpc encoding on the fourth data set, and produce a fifth data set; and
a second checker configured to perform the syndrome check operation on the fifth data set.