Patent ID: 11868259
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A method comprising:
providing a cache coherent computing system comprising a plurality of boards, each board comprising a plurality of processors;
requesting cached data for a first core in a first processor on a first board of the plurality of boards;
upon determining that another core on the first processor does not have the requested cached data, broadcasting a request from the first processor to the other processors on the first board to determine whether one of the other processors is an intervention master (IM) of the requested cached data;
receiving, at the first processor, partial responses (PRESP) from the other processors on the first board;
determining, based on the PRESPs, none of the other processors on the first board are the IM, wherein a first one of the other processors indicates in its PRESP that it is not the IM but it is still participating in the request so it can forward the request to a second board of the plurality of boards; and
broadcasting, after determining none of the other processors on the first board are the IM, a request to the other boards of the plurality of boards to determine whether one of the processors in the other boards is the IM.