Patent ID: 11949020
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A manufacturing method of a transistor, comprising:
providing a dielectric layer;
forming a first gate electrode in the dielectric layer;
sequentially depositing a first gate dielectric layer, a first capping layer, a semiconductor oxide layer, and a second capping layer over the first gate electrode and the dielectric layer;
altering a crystallinity of the semiconductor oxide layer through a thermal annealing process, so as to form a crystalline semiconductor oxide layer;
patterning the first gate dielectric layer, the first capping layer, the crystalline semiconductor oxide layer, and the second capping layer simultaneously such that sidewalls of the second capping layer are aligned along a line perpendicular to a top surface of the first gate electrode with sidewalls of the crystalline semiconductor oxide layer; and
forming source/drain contacts on the second capping layer, wherein the crystalline semiconductor oxide layer and the source/drain contacts are located on two opposite sides of the second capping layer.