Patent ID: 11961789
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A semiconductor package, comprising:
a chip; and
a redistribution layer disposed on the chip and electrically connected with the chip, wherein the redistribution layer comprises a first dielectric layer, a metallization layer, and a second dielectric layer sequentially stacked on each other, the metallization layer comprises joining portions and routing portions, the joining portions comprise first pads and second pads, and the routing portions comprise first routing traces and second routing traces respectively connected to the first pads and the second pads,
wherein the second pads are located closer to an outer edge of the semiconductor package than the first pads,
the first routing traces and the second routing traces extend in between the first dielectric layer and the second dielectric layer along a first direction,
a size of the second pads along a second direction perpendicular to the first direction is larger than a size of the first pads along the second direction, a size of the second pads along the first direction is substantially equal to a size of the first pads along the first direction,
the first direction is a direction extending from an outer edge of the semiconductor package toward the chip, and the first and second directions are substantially parallel to an active surface of the chip.