Patent ID: 11861758
Assignee: NVIDIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 34:
35. A computer-implemented method comprising:
initiating, by a second processor, execution of at least one process, the second processor being associated with a memory storing packet data transmitted by a set of packets;
flushing, by the memory, at least a portion of the memory in response to an instruction from a first processor;
after initiating execution of at least one process, the second processor polling a memory location in the memory for an indication written by the first processor after the portion of the memory is flushed, the indication indicating that the set of packets has been received by a network interface, the first processor being different from the second processor, the memory location being accessible to both the first processor and the second processor; and
processing, by the second processor, the packet data after the second processor detects the indication that the set of packets has been received by the network interface.