Patent ID: 11860714
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus, comprising:
an interface controller configured to cause the apparatus to:
receive, via a host-driven logical block interface, a write command comprising first data and first parity information associated with the first data; and
acknowledge, via the host-driven logical block interface in response to receiving the write command, that the first data has been received based on determining that the first parity information matches second parity information generated from the first data; and

a memory controller configured to cause the apparatus to:
perform one or more operations on second data and third parity information associated with the second data, wherein the second data comprises the first data;
identify an error associated with performing the one or more operations on the second data after acknowledging that the first data has been received; and
transmit an indication of the error over a channel external to the host-driven logical block interface.