Patent ID: 11971815
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A non-transitory computer storage medium storing instructions which when executed in a computing device, cause the computing device to perform a method, comprising:
hosting a plurality of logical partitions on memory cells formed on an integrated circuit die;
performing wear leveling across the logical partitions, including a first logical partition and a second logical partition;
receiving, via a command received via user interface, a write threshold for the first logical partition, wherein the write threshold specifies a quantity of program erase cycles in the memory cells utilized to host the first logical partition and a threshold amount of data to be written to the first logical partition;
tracking an accumulated amount of program erase cycles in the memory cells utilized to host the first logical partition that are consumed based on write requests identifying the first logical partition; and
blocking, in response to the accumulated amount of program erase cycles and the accumulated amount of data reaching the write threshold, write requests to the first logical partition.