Patent ID: 11941338
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. An integrated circuit (IC), comprising:
a plurality of macros, each comprising a macro boundary and a main pattern surrounded by the macro boundary; and
a top channel comprising a plurality of first sub-channels and a plurality of second sub-channels,
wherein each of the first sub-channels is arranged between a first macro and a second macro of the macros, and is formed by a plurality of first dummy boundary cells,
wherein each of the second sub-channels is arranged between two of the second macros, and is formed by a plurality of second dummy boundary cells,
wherein the macro boundaries of the first macros are formed by the first dummy boundary cells, and the macro boundaries of the second macros are formed by the second dummy boundary cells,
wherein a first gate length of dummy patterns within the first dummy boundary cells is greater than a second gate length of dummy patterns within the second dummy boundary cells, and the first and second dummy boundary cells are the same size.