Patent ID: 11935613
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. The device of claim 7, wherein the processor is configured to execute the instructions stored in the memory to:
determine the unsuccessful set of parameters based on a comparison of results of a plurality of read transactions with the DDR flash memory, each read transaction performed at one of successful values of the RD cycle and selected values of the transmit clock delay and the receive clock delay,
wherein the selected values of the transmit clock delay and the receive clock delay are different values in each of the plurality of read transactions and the selected values lie along a line between the values of the transmit clock delay and the receive clock delay of the first set of parameters and the values of the transmit clock delay and the receive clock delay of the second set of parameters.