Patent ID: 11899608
Assignee: GOWIN SEMICONDUCTOR CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 11:
12. A method for providing a C physical layer (“C-PHY”) input output (“IO”) interface via a field programmable gate arrays (“FPGA”), comprising:
coupling a first wire of data lane 0 to a first terminal of first IO serializer of FPGA for receiving first data from a D physical layer (“D-PHY”) transmitter of a first device;
coupling a second wire of the data lane 0 to a second terminal of the first IO serializer of FPGA for receiving second data from the D-PHY transmitter;
activating a first low-voltage differential signaling (“LVDS”) to generate a first value on P channel of the first LVDS and a second value on N channel of the LVDS in response to the first data and the second data; and
generating a first signal on first wire of trio 0 for a C-PHY output based on the first value on the P channel of the first LVDS.