Patent ID: 11879933
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Measurement (Instruments)
Classification: CPC G | IPC G

Claim 18:
19. A testing system comprising:
an integrated circuit;
a test circuit board coupled to the integrated circuit;
a carrier wafer coupled to at least the integrated circuit or the test circuit board; and
a first system electrically coupled to the integrated circuit, the first system comprising:
a non-transitory computer readable medium configured to store executable instructions; and
a processor coupled to the non-transitory computer readable medium, wherein the processor is configured to execute the executable instructions for: performing a simulation of a first heat distribution throughout an integrated circuit design, the integrated circuit design being configured to operate at simulated design power levels, and to generate the first heat distribution, and corresponding to the integrated circuit;

wherein the testing system is configured to simultaneously perform a burn-in test of the integrated circuit and an automated test of the integrated circuit, the integrated circuit being configured to operate according to the simulated design power levels, wherein the burn-in test has a minimum burn-in temperature of the integrated circuit and a burn-in heat distribution across the integrated circuit.