Patent ID: 11946970
Assignee: TEKTRONIX, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A test device, comprising:
one or more printed circuit boards (PCBs);
at least one interface coupled to the one or more PCBs;
margin test circuitry on the one or more PCBs, the margin test circuitry including:
a margin test transmitter and/or a margin test receiver; and
a controller coupled to the at least one interface,
wherein the margin test transmitter and/or the margin test receiver are under control of the controller, and
wherein the controller is configured to:
establish a single-lane or multi-lane high speed input/output (I/O) link of a device under test (DUT) in which, for one or more lanes of the single-lane or multi-lane high speed I/O link, the controller implements physical and logical link layers that communicatively connect the margin test circuitry of the test device with the DUT via the at least one interface; and
assess an electrical margin of the one or more lanes of the single-lane or multi-lane high speed I/O link in either or both transmit (Tx) and receive (Rx) directions, wherein in the Tx direction the controller causes the margin test transmitter to transmit data generated by the margin test circuitry to the DUT, and in the Rx direction the margin test receiver receives data from the DUT.