Patent ID: 11956944
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 9:
10. A semiconductor structure, comprising:
a substrate comprising a contact region and a dummy region arranged adjacent to each other;
a bitline structure and a dielectric layer, an extension direction of the dielectric layer intersecting with that of the bitline structure, and the bitline structure and the dielectric layer defining discrete capacitor contact openings,
wherein the bitline structure comprises a first bitline structure and a second bitline structure, the dielectric layer comprises a first dielectric layer and a second dielectric layer, the second bitline structure and the second dielectric layer are located in the dummy region, the first bitline structure and the first dielectric layer are located in the contact region, a height of the second bitline structure is less than that of the first bitline structure, and a height of the second dielectric layer is less than that of the first dielectric layer;
a second sacrificial layer filling the capacitor contact openings in the dummy region;
an insulation layer located on top surfaces of the second bitline structure, the second dielectric layer and the second sacrificial layer in the dummy region, a top surface of the insulation layer being flush with a top surface of the first bitline structure; and
a capacitor contact structure filling the capacitor contact openings in the contact region.