Patent ID: 11967357
Assignee: NATIONAL TSING HUA UNIVERSITY
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 1:
2. The memory unit with time domain edge delay accumulation for computing-in-memory applications of claim 1, wherein the at least one memory cell further comprises:
a first node storing the weight;
a second node storing an inverted weight opposite to the weight of the first node;
a local bit line bar connected to the at least one edge-delay cell multiplexor and transmitting the inverted weight to the at least one edge-delay cell multiplexor;
a first memory cell transistor connected to the first node, the local bit line and the first word line;
a second memory cell transistor connected to the second node, the local bit line bar and the first word line;
a first inverter located between the first node and the second node; and
a second inverter connected to the first inverter.