Patent ID: 11961469
Assignee: HUAWEI TECHNOLOGIES CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A display module, comprising:
a display;
a display drive circuit; and
at least one driver group;
wherein the display comprises M rows of sub-pixels arranged in a matrix form, wherein a pixel circuit of each sub-pixel comprises a driving transistor, a first reset transistor, a first capacitor, and a light emitting device, wherein M≥2, and wherein M is a positive integer;
wherein a first node of the first reset transistor is coupled to a gate of the driving transistor and a first terminal of the first capacitor, wherein a second terminal of the first capacitor is coupled to a first power voltage input, wherein a first node of the driving transistor is coupled to the first power voltage input and a data voltage output port of the display drive circuit, wherein a second node of the driving transistor is coupled to the light emitting device, wherein the first node of the first reset transistor is a source and a second node is a drain, or the first node of the first reset transistor is the drain and the second node is the source, wherein the first node of the driving transistor is a source and the second node is a drain, or the first node of the driving transistor is a drain and the second node is a source, wherein the first power voltage input is configured to provide a first power voltage, and wherein the data voltage output port is configured to output a data voltage;
wherein each driver group of the at least one drive group comprises M selecting circuits, wherein each selecting circuit is coupled to the display drive circuit, and is configured to receive a first initial voltage Vint1 and a second initial voltage Vint2 that are output by the display drive circuit, and wherein |Vint2|>|Vint1|;
wherein an Nth selecting circuit of the M selecting circuits is coupled to a second node of a first reset transistor in a pixel circuit of an Nth row of sub-pixels of the M rows of sub-pixels, wherein each selecting circuit is further configured to output the second initial voltage Vint2 to the second node of the first reset transistor when the pixel circuit is in a reset phase and a data voltage writing phase, wherein each selecting circuit is further configured to output the first initial voltage Vint1 to the second node of the first reset transistor when the pixel circuit is in a light emitting phase, wherein 1≤N≤M, and wherein N is a positive integer; and
wherein the reset phase is a phase in which the first reset transistor is on, wherein the data voltage writing phase is a phase in which the data voltage is applied to the first node of the driving transistor, and wherein the light emitting phase is a phase in which the light emitting device emits light.