Patent ID: 11955470
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. The semiconductor device of claim 1, wherein the cell region further comprises a plurality of memory cell blocks and a plurality of first bonding metal pads,
each of plurality of the memory cell blocks comprises a gate stack comprising a plurality of gate lines,
the second peripheral circuit region further comprises a plurality of second bonding metal pads,
each of the plurality of gate lines included in a first memory cell block selected from the plurality of memory cell blocks connects to the first peripheral circuit region through a contact structure comprising a contact plug that passes through at least one of the plurality of gate lines, and
each of the plurality of gate lines included in a second memory cell block selected from the plurality of memory cell blocks connects to the second peripheral circuit region through a plurality of bonding structures including the plurality of first bonding metal pads and the plurality of second bonding metal pads.