Patent ID: 11895845
Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A memory device, comprising:
a substrate;
an electrode structure on the substrate, wherein the electrode structure comprises a plurality of first electrode layers and a plurality of second electrode layers that are alternately stacked;
a plurality of vertical active regions penetrating the electrode structure;
a first gate dielectric layer and a second gate dielectric layer, wherein the first gate dielectric layer is provided between the vertical active region and each first electrode layer in the electrode structure, and the second gate dielectric layer is provided between the vertical active region and each second electrode layer in the electrode structure, and each of the first gate dielectric layer and the second gate dielectric layer constitutes a data memory structure,
wherein a first effective work function of a combination of the first electrode layer and the first gate dielectric layer is different from a second effective work function of a combination of the second electrode layer and the second gate dielectric layer.