Patent ID: 11930633
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 0:
1. A method for preparing a semiconductor device, comprising:
providing a substrate, wherein a word line structure is formed in the substrate and a supporting structure is formed on the substrate, the supporting structure comprising a bit line supporting layer and a word line supporting layer above the word line structure, wherein a bit line structure is formed in the bit line supporting layer, the bit line supporting layer comprises a first oxide layer and a first nitride layer, the bit line structure is formed in the first nitride layer, and the first oxide layer is formed on both sides of the bit line structure and located in the first nitride layer;
patterning the supporting structure to form a first via corresponding to the bit line structure in the bit line supporting layer; and
etching the bit line supporting layer to a preset height along the first via, adjusting an etching parameter and a selective etching ratio of etching gas for an oxide layer to a nitride layer, and continuing to etch the bit line supporting layer until the bit line structure is exposed, to form a polymer layer above the bit line structure, wherein the polymer layer is formed on part of a sidewall of the first via and located on both sides of the bit line structure.