Patent ID: 11960402
Assignee: SIGMASTAR TECHNOLOGY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. A configuration method of an integrated circuit, comprising:
partitioning tensor memories needed for a calculation of a neural network model into to a plurality of corresponding predetermined unit pages;
performing data dependency analysis individually on the plurality of predetermined unit pages to establish a plurality of data dependencies, and allocating a plurality of virtual buffers to the plurality of predetermined unit pages according to the plurality of data dependencies;
performing life cycle analysis individually on the plurality of virtual buffers, wherein an analysis result of the life cycle analysis indicates respective life cycles of the plurality of virtual buffers;
allocating a plurality of physical buffers according to the analysis result; and
establishing a plurality of predetermined memory management unit (MMU) tables to record mapping relationships between virtual addresses and physical addresses, so as to allow the integrated circuit to look up at least one physical address for data access according to at least one mapping relationship in a pre-loaded MMU table in a utilization stage, wherein the pre-loaded MMU table is selected from the plurality of predetermined MMU tables.