Patent ID: 11894043
Assignee: INTEGRATED SILICON SOLUTION INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. The power management circuit in the low-power double data rate memory of claim 7, wherein the first low dropout regulator comprises:
a first transistor electrically connected between the first transmitting terminal and the second transmitting terminal; and
a first comparator electrically connected to the first transmitting terminal, the second transmitting terminal and the first transistor, wherein the first comparator is configured to compare the first reference voltage and the second voltage to generate a first comparison signal, and the first comparison signal is electrically connected to the first transistor to adjust the first voltage difference between the first voltage and the second voltage;
wherein the first transistor is a PMOS transistor and has a source electrode, a gate electrode and a drain electrode, and the source electrode, the gate electrode and the drain electrode are electrically connected to the first voltage, the first comparison signal and the second voltage, respectively.