Patent ID: 11880311
Assignee: REALTEK SEMICONDUCTOR CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. A method for controlling operations of an asynchronous FIFO memory, wherein the asynchronous FIFO memory is coupled between a master device and a slave device for buffering data written by the master device, the method comprising:
determining a current depth of the asynchronous FIFO memory according to at least one of a clock ratio, a burst length and a continuous transmission length, wherein the clock ratio is a ratio of a frequency of a first clock signal used by the master device to a frequency of a second clock signal used by the slave device;
configuring one or more entries of the asynchronous FIFO memory to be used according to the current depth, wherein the asynchronous FIFO memory comprises a plurality of entries and the current depth is smaller than or equal to a total number of the entries; and
controlling a plurality of FIFO clock signals provided to the asynchronous FIFO memory according to the current depth, wherein one FIFO clock signal corresponds to one entry, and one or more FIFO clock signals corresponding to one or more entries that are not configured according to the current depth are disabled.