Patent ID: 11935867
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A semiconductor package, comprising:
a package substrate that extends in a first direction and a second direction perpendicular to the first direction and that includes a plurality of edge regions and a central region between the edge regions;
an interposer substrate mounted in the package substrate;
a dielectric film between the package substrate and the interposer substrate;
a plurality of logic dies on the plurality of edge regions of the package substrate;
a memory stack structure on the central region of the package substrate, the memory stack structure including a buffer die and a plurality of memory dies that are stacked on the buffer die;
a plurality of first connection terminals between the package substrate and the logic dies;
a plurality of second connection terminals between the interposer substrate and the logic dies;
a plurality of third connection terminals between the memory stack structure and the interposer substrate;
a plurality of pads on lower portions of the first, second, and third connection terminals;
an under-fill layer that encapsulates the first, second, and third connection terminals; and
a plurality of external terminals on a bottom surface of the package substrate,
wherein the interposer substrate includes:
a base substrate;
an interlayer dielectric layer on the base substrate;
a plurality of wiring lines in the interlayer dielectric layer; and
a plurality of vias in the interlayer dielectric layer, the plurality of vias electrically connecting the wiring lines to each other,

wherein the memory stack structure and at least one of the logic dies are electrically connected to each other through the wiring lines of the interposer substrate,
wherein the entirety of the memory stack structure vertically overlaps the interposer substrate,
wherein each of the logic dies includes:
a first part that is horizontally offset from the interposer substrate; and
a second part that vertically overlaps the interposer substrate,

wherein a bottom surface of the interposer substrate is in contact with the package substrate, and
wherein the interposer substrate does not include a conductive structure providing an electrical connection between the wiring lines of the interposer substrate and the bottom surface of the interposer substrate.