Patent ID: 11941249
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. The memory device of claim 1, wherein
the plurality of HPB entry storage region includes a first HPB entry type storage region and a second HPB entry type storage region; and
the device controller is further configured to,
receive a command from the host device related to the memory operation, and in response to execution of the memory operation related to the command,
generate the mapping information between the logical address associated with the memory operation and the physical address associated with the memory operation,
generate a first type HPB entry to be stored in the first HPB entry storage region, the first type HPB entry including the indexing information indicating the location of the second HPB entry storage region associated with the memory operation, and
generate a second type HPB entry to be stored in the second HPB entry storage region, the second type HPB entry including the additional information associated with a read operation of the plurality of storage units.