Patent ID: 11923437
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. A method comprising:
forming a first semiconductor fin protruding higher than first isolation regions on opposite sides of the first semiconductor fin;
forming a second semiconductor fin protruding higher than second isolation regions on opposite sides of the second semiconductor fin;
measuring a first fin width of the first semiconductor fin;
measuring a second fin width of the second semiconductor fin;
thinning the first semiconductor fin based on the first fin width using a first etching chemical, wherein when the first semiconductor fin is thinned, the second semiconductor fin is also thinned, and a first etching rate of the first semiconductor fin is greater than a second etching rate of the second semiconductor fin; and
forming a dummy gate stack on the first semiconductor fin that has been thinned by the thinning the first semiconductor fin.