Patent ID: 11955549
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A manufacturing method of a semiconductor device, comprising:
forming a channel layer and a high-k dielectric layer sequentially on a first dielectric layer over a substrate;
patterning the channel layer and the high-k dielectric layer to form a channel pattern and a high-k dielectric pattern sequentially on the first dielectric layer;
forming a second dielectric layer over the channel pattern and the high-k dielectric pattern;
patterning the second dielectric layer to form a gate trench;
patterning the second dielectric layer and the high-k dielectric pattern to form two contact openings;
forming a gate pattern in the gate trench and forming two contacts in the contact openings;
forming a bottom metallic layer electrically connected to one of the contacts;
forming a film stack comprising crystalline oxide blanket layers and ferroelectric blanket layers alternately stacked on the bottom metallic layer;
forming a top metallic layer over the film stack; and
patterning the bottom metallic layer, the film stack, and the top metallic layer to respectively form a bottom electrode, a layered structure comprising crystalline oxide layers and ferroelectric layers alternately stacked, and a top electrode of a ferroelectric tunnel junction.