Patent ID: 11963359
Assignee: MICRON TECHNOLOGY, INC.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 0:
1. A method of forming an integrated assembly, comprising:
forming a construction to include a first memory region, a second memory region laterally offset from the first memory region, and an intermediate region laterally between the first and second memory regions; the construction including a first stack extending across the first memory region, the second memory region and the intermediate region; the first stack comprising alternating semiconductor-material-containing regions and intervening regions; there being at least three of the semiconductor-material-containing regions, with one of the semiconductor-material-containing regions being a central semiconductor-material-containing region and being vertically between two others of the semiconductor-material-containing regions; the construction also including a second stack extending across the first memory region, the second memory region and the intermediate region, with the second stack being over the first stack; the second stack comprising alternating first and second levels, with the first levels comprising sacrificial material and the second levels comprising insulative material; the intermediate region having a first edge proximate the first memory region and a second edge proximate the second memory region; the central semiconductor-material-containing region having a relatively-doped-portion and a relatively-undoped-portion; the relatively-undoped-portion being within the memory regions and within the intermediate region; the relatively-doped-portion being only within the intermediate region and being configured as a substantially H-shaped structure having a first leg region along the first edge, a second leg region along the second edge, and a belt region extending from the first leg region to the second leg region;
forming pillars extending through the second stacks of the first and second memory regions and at least partially into the first stacks of the first and second memory regions, the pillars including cell materials and channel material;
forming posts extending through the second stack of the intermediate region and into the first stack of the intermediate region;
forming a slit-opening to pass through the second stack and to the central semiconductor-material-containing region of the first stack; the slit-opening extending across the first memory region, the intermediate region and the second memory region, and being over and along the belt region;
removing the central semiconductor-material-containing region from within the first and second memory regions with one or more etchants flowed into the slit-opening, the relatively-doped-portion of the central semiconductor-material-containing region being resistant to said one or more etchants; the removing of the central semiconductor-material-containing region forming conduits in the first stacks within the first and second memory regions;
extending the conduits through the cell materials and to the channel material of the pillars;
forming doped-semiconductor-material within the extended conduits;
out-diffusing dopant from the doped-semiconductor-material into the channel material, the out-diffused dopant extending upwardly to at least one of the first levels; and
replacing at least some of the sacrificial material of the first levels with conductive material.