Patent ID: 11870881
Assignee: THE GOVERNING COUNCIL OF THE UNIVERSITY OF TORONTO
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 2:
3. The circuit of claim 1, wherein the NTT circuitry further includes a high input word path and a low input word path, wherein:
the high input word path includes
a first adder/subtractor,
a first multiplier, and
wherein the selection circuitry is coupled to the first adder/subtractor and the first multiplier and including respective first bypass paths to selectively bypass the first adder/subtractor and the first multiplier; and

the low input word path includes
a second adder/subtractor,
a second multiplier, and
wherein the selection circuitry is coupled to the second adder/subtractor and the second multiplier and including respective second bypass paths to selectively bypass the second adder/subtractor and the second multiplier.