Patent ID: 11888479
Assignee: KEPLER COMPUTING INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 10:
11. An apparatus comprising:
an AND gate comprising a majority gate or a minority gate having non-linear polar material, wherein the AND gate is to receive a multiplier and a multiplicand;
a 1-bit full adder comprising a majority gate or a minority gate coupled to the AND gate, wherein the 1-bit full adder comprises non-linear polar material, and wherein the 1-bit full adder is to receive a sum input and a carry input; and
a reset mechanism comprising logic to condition first terminals of capacitors of the AND gate and the 1-bit full adder, the capacitors comprising the non-linear polar material, wherein the reset mechanism is to reset second terminals of the capacitors during a reset phase separate from an evaluation phase, and wherein the reset mechanism is to apply a predetermined input to the multiplier, the multiplicand, the sum input, and the carry input during the reset phase.