Patent ID: 11910590
Assignee: SK HYNIX INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 22:
23. A semiconductor memory device, comprising:
a substrate; and
a memory cell array including memory cells stacked along a direction vertical to the substrate,
wherein each of the memory cells comprises:
a bit line vertically oriented to the substrate;
a capacitor laterally spaced apart from the bit line;
an active layer laterally oriented between the bit line and the capacitor, and including a first source/drain region, a second source/drain region and a thin-body channel between the first source/drain region and the second source/drain region;
a word line disposed on an upper portion of the active layer and laterally oriented to intersect with the active layer,
wherein a thickness of the thin-body channel is smaller than a thickness of the word line, wherein
a thickness of the thin-body channel is smaller than that of first source/drain region, and
the thickness of the thin-body channel is equal to that of the second source/drain region.