Patent ID: 11907151
Assignee: DRUT TECHNOLOGIES INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A computing system comprising:
a first fabric interface device coupled to receive first multi-lane serial peripheral component interconnect express (PCIe) data from first functional elements of a first computing asset through a first multi-lane PCIe bus, wherein the first fabric interface device is configured to transparently extend the first multi-lane PCIe bus by converting the first multi-lane PCIe data into a retimed parallel version of the first PCIe multi-lane data to be sent on a first bidirectional data communication path, wherein the first multi-lane PCIe bus has a first number of lanes and the first bidirectional data communication path has a second number of lanes; and wherein the first number does not equal the second number;
the first computing asset configured to be coupled to a data path transport by the first bidirectional data communication path; and
a second computing asset having second functional elements and configured to be coupled to the data path transport by a second bidirectional data communication path, wherein the second computing asset includes:
a second fabric interface device coupled to receive second multi-lane serial peripheral component interconnect express (PCIe) data from the second functional elements through a second multi-lane PCIe bus, wherein the second fabric interface device is configured to transparently extend the second multi-lane PCIe bus by converting the second multi-lane PCIe data into a second retimed parallel version of the second PCIe multi-lane data to be sent on the second bidirectional data communication path, wherein the second multi-lane PCIe bus has a third number of lanes and the second bidirectional data communication path has a fourth number of lanes; and wherein the third number does not equal the fourth number.