Patent ID: 11881441
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 3:
4. The semiconductor package of claim 1, further comprising:
a second die stack having a second die stack footprint area;
wherein a combined footprint area of the first die stack and the second die stack is less than the substrate footprint area;
wherein the first die stack and the second die stack footprint are spaced apart to provide an interstitial space between the first die stack footprint and the second die stack footprint;
wherein at least some of the plurality contact pads are disposed on the second surface of the substrate in the interstitial space between the first die stack footprint and the second die stack footprint such that the contact pads disposed in the interstitial space are partially overlapped from the plan view perspective by at least one of:
the first die stack footprint or the second die stack footprint;
wherein the spacer die is disposed between the upper surface of the substrate and the first and the second die stacks; and
wherein the spacer die footprint area completely overlaps the portion of the plurality of peripheral electrical contact pads at least partially overlapped by the first die stack footprint and the contact pads disposed in the interstitial space between the first die stack and the second die stack from the plan view perspective.