Patent ID: 11925020
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 16:
17. A vertical semiconductor device, comprising:
a stacked structure including insulation layers and gate patterns on a substrate, the insulation layers alternately and repeatedly stacked with the gate patterns on the substrate, the stacked structure extending in a first direction parallel to an upper surface of the substrate; and
a plurality of channel structures passing through the stacked structure, each of the channel structures extending to the upper surface of the substrate, and each of the channel structures including a charge storage structure and a channel,
wherein a plurality of the gate patterns is formed at at least one level in the stacked structure, and at least two trenches for cutting the gate patterns are disposed at the same level,
wherein, in a plan view cut along a horizontal direction of the trenches and the gate patterns at sides of the trenches, one sidewall of each of the trenches overlaps sidewalls of the channel structures.