Patent ID: 11908545
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. The memory device according to claim 1, wherein each of the plurality of memory banks further comprising:
a second memory array;
a third latch circuit, coupled the second memory array, configured to latch a third data from the second memory array in a first read cycle; and
a fourth latch circuit, coupled the second memory array, configured to latch a fourth data from the second memory array in a second read cycle,
wherein the local MAC circuit performs the first stage CIM operation on at least one of the first latched data, the second latched data, a third latched data latched in the third latch circuit and a fourth latched data latched in the fourth latch circuit to provide the first stage CIM result.