Patent ID: 11942185
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A memory device comprising:
a memory array comprising a plurality of rows and a plurality of columns, wherein each of the plurality of columns comprises a first plurality of memory cells connected to a bit line of a plurality of bitlines;
a plurality of multiplexers, each of the plurality of multiplexers associated with a predetermined number of bitlines of the plurality of bitlines; and
a plurality of Input/Output (I/O) circuits, wherein each of the plurality of I/O circuits is associated with one of the plurality of multiplexers, wherein a multiplexer connects an I/O circuit associated with the multiplexer to a bitline of the predetermined number of bitlines, and wherein the I/O circuit senses multiply-accumulate value for the bitline in time domain.