Patent ID: 11901840
Assignee: GREE ELECTRIC APPLIANCES, INC. OF ZHUHAI
Field: Semiconductors (Electrical engineering)
Classification: CPC H  Y | IPC H

Claim 2:
3. The preparation method according to claim 1, wherein the forming a chip device layer on the potential energy barrier layer comprises:
forming an ohmic metal layer on a side of the potential energy barrier layer away from the substrate, and forming the source electrode and the drain electrode by a patterning process;
forming a gate electrode metal layer on the side of the potential energy barrier layer away from the substrate, and forming the gate electrode by the patterning process;
forming a first dielectric layer on a side of the source electrode, the drain electrode and the gate electrode away from substrate;
forming first through-holes at portions of the first dielectric layer, the portions of the first dielectric layer corresponding to the source electrode, the drain electrode and the gate electrode;
forming a first metal layer on a side of the first dielectric layer away from the substrate;
portions of the first metal layer, which are opposite to the first through-holes, sinking into the first through-holes;
forming a first metal part of the first bond pad, a first metal part of the second bond pad, a first metal part of the third bond pad, and a first metal part of the fourth bond pad in the isolation area by the first metal layer through the patterning process;
forming a source electrode first metal part at a position opposite to the source electrode;
forming a drain electrode first metal part at a position opposite to the drain electrode; and
forming a gate electrode first metal part at a position opposite to the gate electrode, to connect the gate electrode and the first metal part of the fourth bond pad;
forming a second dielectric layer on a side of the first metal layer away from the substrate;
forming second through-holes at portions of the second dielectric layer, wherein the portions of the second dielectric layer correspond to the first metal part of the first bond pad, the first metal part of the second bond pad, the first metal part of the third bond pad, the first metal part of the fourth bond pad, the source electrode, the drain electrode and the gate electrode;
forming a second metal layer on a side of the second dielectric layer away from the substrate;
portions of the second metal layer, which are opposite to the second through-holes, sinking into the second through-holes, respectively;
forming a second metal part of the first bond pad, a second metal part of the second bond pad, a second metal part of the third bond pad and a second metal part of the fourth bond pad in the isolation area by the second metal layer through the patterning process;
forming a source electrode second metal part at a position opposite to the source electrode, to connect the source electrode first metal part and the second metal part of the second bond pad or the second metal part of the third bond pad;
forming a drain electrode second metal part at a position opposite to the drain electrode, to connect the drain electrode first metal part and the second metal part of the first bond pad or the second metal part of the second bond pad; and
forming a gate electrode second metal part at a position opposite to the gate electrode.