Patent ID: 11879917
Assignee: MITSUBISHI ELECTRIC CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 1:
2. The phase detector according to claim 1, wherein
the multiplication circuit includes:
a first multiplier to multiply the first positive-phase signal included in the first differential signal by the second positive-phase signal phase-shifted by the phase shift circuit, and output a first multiplication signal indicating a result of the multiplication to the phase difference calculating circuit;
a second multiplier to multiply the first positive-phase signal included in the first differential signal by the second negative-phase signal phase-shifted by the phase shift circuit, and output a second multiplication signal indicating a result of the multiplication to the phase difference calculating circuit;
a third multiplier to multiply the first negative-phase signal included in the first differential signal by the second negative-phase signal phase-shifted by the phase shift circuit, and output a third multiplication signal indicating a result of the multiplication to the phase difference calculating circuit;
a fourth multiplier to multiply the first negative-phase signal included in the first differential signal by the second positive-phase signal phase-shifted by the phase shift circuit, and output a fourth multiplication signal indicating a result of the multiplication to the phase difference calculating circuit; and
a fifth multiplier to multiply the first positive-phase signal phase-shifted by the phase shift circuit by the second positive-phase signal included in the second differential signal, and output a fifth multiplication signal indicating a result of the multiplication to the phase difference calculating circuit;
a sixth multiplier to multiply the first negative-phase signal phase-shifted by the phase shift circuit by the second positive-phase signal included in the second differential signal, and output a sixth multiplication signal indicating a result of the multiplication to the phase difference calculating circuit;
a seventh multiplier to multiply the first negative-phase signal phase-shifted by the phase shift circuit by the second negative-phase signal included in the second differential signal, and output a seventh multiplication signal indicating a result of the multiplication to the phase difference calculating circuit; and
an eighth multiplier to multiply the first positive-phase signal phase-shifted by the phase shift circuit by the second negative-phase signal included in the second differential signal, and output an eighth multiplication signal indicating a result of the multiplication to the phase difference calculating circuit.