Patent ID: 11862709
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 15:
16. An integrated circuit (IC) device, comprising:
a semiconductor substrate having a top surface;
a source feature and a drain feature over and in direct contact with the semiconductor substrate;
a first semiconductor layer suspended over the top surface and connecting the source feature and the drain feature along a horizontal direction;
a second semiconductor layer suspended over the top surface and in contact with a sidewall of the source feature such that the source feature is sandwiched between the first semiconductor layer and the second semiconductor layer along the horizontal direction;
a gate spacer layer disposed over the second semiconductor layer;
a gate electrode wrapping around and engaging the first semiconductor layer;
a spacer vertically between an end portion of the first semiconductor layer and the top surface and horizontally between the source feature and the gate electrode, the spacer having a lateral dimension along the horizontal direction and a vertical dimension along a vertical direction perpendicular to the top surface; and
a contact etch stop layer disposed on and in contact with a top surface of the source feature and a top surface of the gate spacer layer,
wherein the lateral dimension varies in length across the vertical dimension and has a first length at an interface between the spacer and the first semiconductor layer, and a second length at a half-height level of spacer, and
wherein a ratio of the first length to the second length is about 0.65 to about 1,
wherein the source feature and the drain feature partially below the top surface of the semiconductor substrate,
wherein the source feature and the drain feature partially extend along the horizontal direction between the first semiconductor layer and the semiconductor substrate.