Patent ID: 11921632
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. The apparatus of claim 2, the page table comprising a guest page table of the VM, the target memory page comprising the target guest memory page in the DRAM, the VM comprising the instructions to migrate the first guest memory page, the instructions to migrate the first guest memory page executable by the processor to cause the processor to:
determine that the guest page table maps a first virtual address to the first guest memory page and maps a second virtual address to the target guest memory page;
allocate a temporary memory page in the DRAM;
copy the first guest memory page to the temporary memory page;
copy the target guest memory page to a first host memory page;
copy the temporary memory page to the target guest memory page;
modify the guest page table to map the first virtual address to the target guest memory page;
free the first guest memory page;
flush a translation lookaside buffer (TLB) of an entry for the first guest memory page; and
resume execution of the VM and the application.