Patent ID: 11914541
Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A computing device, comprising:
an expansion interface comprising a plurality of slots, wherein two slots of the plurality of slots are controlled by a single reset signal;
a first device connected to a first slot of the two slots, wherein the first device has a feature compatible with the single reset signal;
a second device connected to a second slot of the two slots, wherein the second device does not have the feature compatible with the single reset signal; and
a processor communicatively coupled to the expansion interface, wherein the processor is to:
detect the first device connected to the first slot and the second device connected to the second slot;
determine that the first device has the feature compatible with the single reset signal and that the second device does not have the feature compatible with the single reset signal; and
disable the feature by preventing the first slot and the second slot from receiving the single reset signal.