Patent ID: 11967293
Assignee: JAPAN DISPLAY INC.
Field: Optics (Instruments)
Classification: CPC G | IPC G

Claim 3:
4. An electronic device comprising:
a plurality of scanning lines extending along a first direction and aligned along a second direction intersecting the first direction;
a plurality of signal lines extending along the second direction and aligned along the first direction;
a plurality of pixels disposed in a display area and provided at intersections of the plurality of scanning lines and the plurality of signal lines; and
an inspection circuit disposed in a non-display area different from the display area, including a plurality of first switch elements connected to the plurality of scanning lines, wherein
the plurality of first switch elements of the inspection circuit are oxide semiconductor transistors each including an oxide semiconductor layer,
each of the plurality of first switch elements includes a first transistor and at least one transistor pair,
the at least one transistor pair includes a second transistor and a third transistor which are bi-directionally connected each other and each of which is diode-connected,
a gate of the first transistor is connected to a first wiring line,
one of a source and a drain of the first transistor is connected to one of a source and a drain of the second transistor and the other of a source and a drain and a gate of the third transistor,
the other of the source and the drain of the first transistor is connected to a first scanning line of the plurality of scanning lines,
a gate of the second transistor is connected to the other of the source and the drain of the second transistor, one of the source and the drain of the third transistor and a second wiring line, and
the second wiring line is connected to the gate and the other of the source and the drain of the second transistor connected to a second scanning line different from the first scanning line, and one of a source and a drain of the third transistor.