Patent ID: 11955484
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. The semiconductor device according to claim 7, wherein the first gate stack comprises:
a first gate dielectric layer over the first semiconductor fin;
a first gate electrode disposed over the first gate dielectric layer; and
a plurality of first spacers disposed on sidewalls of the first gate dielectric layer and the first gate electrode;
the second gate stack comprises:
a second gate dielectric layer over the at least one second semiconductor fin;
a second gate electrode disposed over the second gate dielectric layer, wherein the second gate electrode is in contact with side surfaces of the source/drain regions of the at least one second semiconductor fin; and
a plurality of second spacers disposed on sidewalls of the second gate dielectric layer and the second gate electrode.