Patent ID: 11877447
Assignee: WINBOND ELECTRONICS CORP.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 3:
4. The manufacturing method of claim 3, wherein a forming method of the first isolation structures, the second isolation structures, the oxide layer and the memory structure comprises:
forming an oxide material layer, a first conductive layer and a first mask layer in sequence on the substrate;
patterning the first conductive layer and the first mask layer in the peripheral region to form a first patterned conductive layer and a first patterned mask layer in the peripheral region, wherein the first patterned conductive layer and the first patterned mask layer constitute a first stack structure;
partially removing the first patterned conductive layer in the first stack structure;
patterning the first conductive layer and the first mask layer in the memory region to form a second patterned conductive layer and a second patterned mask layer in the memory region, wherein the second patterned conductive layer and the second patterned mask layer constitute a second stack structure;
partially removing the oxide material layer and the substrate using the first stack structure and the second stack structure as masks to form first trenches in the peripheral region and second trenches in the memory region, and to form the tunneling dielectric layer and the floating gate of the memory structure;
forming the first isolation structures in the first trenches and forming the second isolation structures in the second trenches, wherein the first isolation structures cover a part of the oxide material layer;
removing the first patterned mask layer and the second patterned mask layer;
removing the first patterned conductive layer; and
removing the oxide material layer not covered by the first isolation structures to form the oxide layer.