Patent ID: 11894308
Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A substrate, comprising:
a first dielectric layer, having a first surface and a second surface opposite to the first surface;
a first conductive via extending between the first surface and the second surface of the first dielectric layer and including a first bottom surface exposed from the second surface of the first dielectric layer, the first bottom surface of the first conductive via including a first recess surface, the first recess surface including a first curved surface, the first conductive via comprising a first pattern, wherein the first pattern comprises at least two geometric centers corresponding to at least two geometric patterns, respectively;
a second dielectric layer, having a first surface and a second surface opposite to the first surface;
a second conductive via under the first dielectric layer and extending between the first surface and the second surface of the second dielectric layer, the second conductive via including a second top surface facing the conductive via and a second bottom surface opposite to the second top surface, the second bottom surface of the second conductive via including a second recess surface, the second recess surface including a second curved surface; and
a third conductive via under the first dielectric layer and extending between the first surface and the second surface of the second dielectric layer, wherein a first portion of the second conductive via is directly connected to the third conductive via, and a second portion of the second conductive via is separated from the third conductive via through the second dielectric layer.