Patent ID: 11923318
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC B  H | IPC B  H

Claim 8:
9. A method of manufacturing a semiconductor package, comprising:
forming a backside redistribution structure, wherein the backside redistribution structure comprises a first dielectric layer, and a redistribution circuit layer over the first dielectric layer, wherein the redistribution circuit layer comprises a plurality of first dummy pads and a plurality of second dummy pads disposed between the first dummy pads, and a size of each of the first dummy pads is substantially greater than a size of each of the second dummy pads;
forming an encapsulated semiconductor device on the backside redistribution structure;
forming a front side redistribution structure on the encapsulated semiconductor device, wherein the front side redistribution structure is electrically connected to the semiconductor device; and
performing a patterning process on the first dielectric layer to form a marking pattern opening partially exposing one of the plurality of first dummy pads.