Patent ID: 11916002
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A semiconductor package, comprising:
a package substrate;
an interposer substrate on the package substrate, the interposer substrate including a first redistribution substrate, a second redistribution substrate below a bottom surface of the first redistribution substrate, and an interposer molding layer between the first redistribution substrate and the second redistribution substrate;
a connection substrate on the interposer substrate, the connection substrate having a connection hole that penetrates through the connection substrate;
a first semiconductor chip on the interposer substrate in the connection hole;
a second semiconductor chip on the interposer substrate in the connection hole and horizontally spaced apart from the first semiconductor chip;
a connection semiconductor chip in the interposer molding layer and on the bottom surface of the first redistribution substrate;
a capacitor chip in the interposer molding layer on the bottom surface of the first redistribution substrate, the capacitor chip being horizontally spaced apart from the connection semiconductor chip; and
a molding layer on the interposer substrate, the molding layer extending between the first semiconductor chip and the second semiconductor chip, the first semiconductor chip and the connection substrate, and the second semiconductor chip and the connection substrate and the molding layer covering a sidewall of the first semiconductor chip, a sidewall of the second semiconductor chip, a sidewall of the connection substrate, and an upper surface of the connection substrate.