Patent ID: 11948831
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. An apparatus comprising:
a first set of one or more layers of a first wafer including an active device and first one or more vias, wherein the first set of one or more layers and the active device comprise a first material formed using a first temperature;
a second set of one or more layers of a second wafer including second one or more vias, wherein the second set of one or more layers comprises a second material formed using a second temperature different from the first temperature; and
a layer between the first wafer and the second wafer, wherein the layer is configured to bond the first wafer to the second wafer;
wherein the first one or more vias and the second one or more vias at least partially overlap with one another at the layer that bonds the first wafer to the second wafer.