Patent ID: 11950411
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 10:
11. A memory device, comprising:
a plurality of memory cells, each one of which includes a first transistor and a resistor operatively coupled to each other in series;
wherein the first transistor includes:
a first channel structure including a plurality of first nanostructures;
a first source/drain structure coupled to a first sidewall of each of the plurality of first nanostructures; and
a first gate structure coupled to a top surface, a bottom surface, and a second sidewall of each of the plurality of first nanostructures, with a third sidewall of the first nanostructures coupled to a dielectric fin structure; and

wherein the resistor includes:
a metal structure disposed above the first gate structure.