Patent ID: 11934700
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A storage device, comprising:
a memory including a data structure, wherein the data structure is associated with a submission queue; and
one or more processors coupled to the memory, the one or more processors, individually or in combination, configured to:
receive a first command for a fused operation from the submission queue, the first command indicating a first logical address range,
store the first command in the data structure,
receive a second command for a different operation from the submission queue, the second command indicating a second logical address range,
determine whether the second command corresponds to the fused operation,
in response to determining that the second command does not correspond to the fused operation, perform the different operation prior to the fused operation,
receive a third command from the submission queue, the third command indicating a third logical address range,
determine whether the third command corresponds to the fused operation and the third logical address range overlaps with the first logical address range, and
in response to determining that the third command corresponds to the fused operation and that the third logical address range overlaps with the first logical address range, store the third command in the data structure and perform the fused operation.