Patent ID: 11925028
Assignee: SK HYNIX INC.
Field: nan (nan)
Classification: CPC nan | IPC H

Claim 9:
10. A semiconductor memory device comprising:
a peripheral transistor;
a first insulating layer covering the peripheral transistor;
a source layer on the first insulating layer;
a stack structure on the source layer, the stack structure including alternately stacked insulating patterns and conductive patterns;
a peripheral contact structure penetrating the stack structure and the source layer, the peripheral contact structure being electrically connected to the peripheral transistor; and
a word line contact electrically connected to at least one of the conductive patterns,
wherein the peripheral contact structure is electrically connected to the at least one of the conductive patterns through the word line contact, and
wherein a level of an uppermost portion of the peripheral contact structure is higher than a level of an uppermost conductive pattern among the conductive patterns.