Patent ID: 11955512
Assignee: KEPLER COMPUTING INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 0:
1. A method of fabricating a device structure, the method comprising:
forming an electrode structure in a memory region by a first process comprising:
etching a first opening in an etch stop layer and exposing a first conductive interconnect below the etch stop layer;
depositing a first conductive hydrogen barrier layer in the first opening; and
depositing a first conductive material on the first conductive hydrogen barrier layer;

depositing a first dielectric comprising an amorphous, greater than 90% film density hydrogen barrier material on the electrode structure;
forming a trench capacitor by a second process comprising:
forming a trench in the first dielectric, the trench exposing at least a portion of the electrode structure;
depositing a first electrode layer on a base and on sidewalls of the trench;
depositing a dielectric layer comprising a ferroelectric material or a paraelectric material on the first electrode layer; and
depositing a second electrode layer on the dielectric layer;

depositing a second dielectric comprising a less than 90% film density material on the etch stop layer in an adjacent logic region;
forming a via electrode on the trench capacitor by a third process comprising:
depositing a second conductive hydrogen barrier layer on the second electrode layer; and
depositing a second conductive material on the second conductive hydrogen barrier layer;

forming a second opening in the second dielectric and in the etch stop layer; and
depositing a conductive material in the second opening to form a via structure on a second conductive interconnect.