Patent ID: 11886874
Assignee: HITACHI ASTEMO, LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. An arithmetic operation method by an arithmetic operation device that causes a convolution arithmetic unit to perform a convolution arithmetic operation between a filter and target data corresponding to a size of the filter in each of a plurality of convolution layers constituting a neural network, wherein the arithmetic operation device is configured to:
reduce a bit string corresponding to a first bit number from a least significant bit of the target data and reduces a bit string corresponding to a second bit number from a least significant bit of a weight for each convolution layer; and
add a bit string corresponding to a third bit number obtained by adding the first bit number and the second bit number to a least significant bit of a convolution arithmetic operation result output from the convolution arithmetic unit by inputting the target data and the weight that is an element of the filter after being reduced by the bit reduction unit to the convolution arithmetic unit.