Patent ID: 11903194
Assignee: MACRONIX INTERNATIONAL CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 10:
11. An integrated circuit, comprising:
two adjacent first memory blocks and two adjacent second memory blocks respectively disposed on two sides of the integrated circuit, wherein each of the two first memory blocks and the two second memory blocks comprises a memory cell array having a three-dimensional architecture and a shortest spacing distance between the memory cell array of the two adjacent first memory blocks; and
a pad disposing area disposed between the two adjacent first memory blocks and the two adjacent second memory blocks, wherein a plurality of pads are disposed in the pad disposing area, and the pads are respectively electrically coupled to the two adjacent first memory blocks and the two adjacent second memory blocks,
wherein each of the two adjacent first memory block comprises a first control circuit generating a first control signal to control an access operation of the corresponding first memory cell array, each of the two adjacent second memory block comprises a second control circuit generating a second control signal to control an access operation of the corresponding second memory cell array, and the two first control circuits and the second control circuits are symmetrically disposed about the pad disposing area.