Patent ID: 11877439
Assignee: INVENTION AND COLLABORATION LABORATORY PTE. LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 5:
6. The IC system of claim 5, wherein the 3D structure of the second transistor comprising:
a first concave formed in the logic chip and a first isolating layer configured in the first concave and above a bottom wall of the first concave;
a second concave formed in the logic chip and a second isolating layer configured in the second concave and above a bottom wall of the second concave;
a first conductive region positioned on the top of the first isolating layer;
a second conductive region positioned on the top of the second isolating layer;
a gate between the first conductive region and the second conductive region; and
a channel region under the gate and electrically coupled to the first conductive region and the second conductive region.