Patent ID: 11923864
Assignee: SHAOXING YUANFANG SEMICONDUCTOR CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 1:
2. The PLL of claim 1, wherein said second PLL comprises:
a third oscillator to generate a second input clock with a first frequency;
a second phase detector to receive said second input clock divided by an integer greater than or equal to one, on a corresponding input path and a second feedback clock on a second feedback path, said phase detector to generate a second error signal representing a second phase difference between said second input clock and said second feedback clock;
a second oscillator to generate said output clock from said second error signal;
a second feedback divider to divide said output clock by a second divisor to generate said second feedback clock,
wherein said changing configuration of said second PLL comprises changing said second divisor to a new value corresponding to said different frequency.