Patent ID: 11921652
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. An apparatus comprising: at least one core; and an interface circuit coupled to the at least one core, the interface circuit comprising: a first input/output (I/O) buffer to couple to a first communication line of an I3C bus, the I3C bus to couple to a first device group including two or more first memory devices and a second device group including two or more second memory devices; and a second I/O buffer to couple to a second communication line of the I3C bus, wherein the interface circuit is to: send a first message including a data signal addressed to a first memory device of the first device group via the second I/O buffer, wherein the two or more first memory devices of the first device group are to receive only the data signal via data circuitry and the two or more second memory devices of the second device group are to receive only the data signal via clock circuitry; and concurrently, while the first message is being sent, sending only a clock signal via the second I/O buffer, wherein the two or more first memory devices of the first device group are to receive the clock signal via clock circuitry and the two or more second memory devices of the second device group are to receive the clock signal via data circuitry, the two or more second memory devices of the second device group coupled in opposition to the two or more first memory devices of the first device group with respect to the clock signal.