Patent ID: 11935587
Assignee: CEREMORPHIC, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device comprising:
a wordline controller configured to activate a wordline signal, the wordline controller causing a pulse width of the activated wordline signal to be associated with one of at least two data retrieval error rates;
at least one memory array arranged as a sequence of columns of data, each column of data activated by a wordline, the activated wordline causing data to be asserted to bitlines coupled to an input/output driver;
the wordline controller decoding an address to activate a corresponding wordline associated with a column of data in the memory array, the activated wordline held active for a pulse width based on a desired data error rate;
the column of data in the memory array transferred through the bitlines to an output of the memory device, the controller selecting the pulse width corresponding to the one of at least two data retrieval error rates.