Patent ID: 11888064
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A method comprising:
depositing a contact etch stop layer (CESL) having a first portion on an upper surface of a source/drain region and having a second portion on a lower surface of the source/drain region;
depositing an inter-layer dielectric (ILD) layer on the CESL;
removing the first portion of the CESL with an anisotropic etching process to expose the upper surface of the source/drain region;
removing the second portion of the CESL with an isotropic etching process to expose the lower surface of the source/drain region, wherein removing the second portion of the CESL forms a first undercut and a second undercut, the first undercut between the ILD layer and the upper surface of the source/drain region, the second undercut between the ILD layer and the lower surface of the source/drain region; and
after the anisotropic etching process and after the isotropic etching process, forming a silicide on the upper surface of the source/drain region and on the lower surface of the source/drain region.