Patent ID: 11901869
Assignee: DB HITEK, CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. The amplifier according to claim 8, wherein
the first current determiner comprises:
a seventh transistor having one terminal connected to a first supply voltage; and
a ninth transistor having one terminal connected to another terminal of the seventh transistor, a gate configured to receive a third bias voltage, and another terminal connected to a gate of the seventh transistor and one terminal of the first transmission gate, wherein the other terminal of the ninth transistor is the first current determination and/or voltage generation node,

the first current follower comprises:
an eighth transistor having one terminal connected to the first supply voltage, another terminal connected to one terminal of the first compensation capacitor, and a gate connected to the first current determination and/or voltage generation node; and
a tenth transistor having one terminal connected to the other terminal of the eighth transistor, a gate configured to receive the third bias voltage, and another terminal configured to provide the first conversion voltage and connected to one terminal of the second transmission gate,

the second current determiner comprises:
an eleventh transistor having one terminal connected to another terminal of the first transmission gate and a gate configured to receive a fourth bias voltage, wherein the one terminal of the eleventh transistor is the second current determination and/or voltage generation node; and
a thirteenth transistor having one terminal connected to another terminal of the eleventh transistor, another terminal connected to a second supply voltage, and a gate connected to the second current determination and/or voltage generation node, and

the second current follower comprises:
a twelfth transistor having one terminal configured to provide the second conversion voltage and connected to another terminal of the second transmission gate, and a gate configured to receive the fourth bias voltage; and
a fourteenth transistor having one terminal connected to another terminal of the twelfth transistor, a gate connected to the second current determination and/or voltage generation node, and another terminal connected to the second supply voltage.