Patent ID: 11875059
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. A memory system connectable to a host via each of a first bus and a second bus, the memory system comprising:
a nonvolatile memory; and
a controller configured to execute, via the first bus, communication related to an I/O command with the host for writing or reading data to or from the nonvolatile memory, and execute, via the second bus, communication related to a management command with the host for acquiring a status of the memory system, wherein
the controller is configured to:
acquire, from the nonvolatile memory, first data that is necessary for responding to a management command for acquiring a status of the memory system before causing the memory system to transition from a normal mode in which the I/O command and the management command received from the host are processed to a low power mode in which the I/O command and the management command are not processed, the first data indicating the status of the memory system, and store the acquired first data in a first volatile memory included in the controller;
cause the memory system to transition from the normal mode to the low power mode by stopping supply of power to each of components of the controller except for a first interface circuit that communicates with the host via the first bus, a second interface circuit that communicates with the host via the second bus, and the first volatile memory and stopping the supply of power to the nonvolatile memory after storing the acquired first data in the first volatile memory; and
when the management command is received by the second interface circuit via the second bus while the memory system is in the low power mode, start a process of restoring the memory system to the normal mode by restarting the supply of power to each of the components of the controller and the supply of power to the nonvolatile memory, and when the controller becomes accessible to the first volatile memory, read the first data from the first volatile memory and transmit the read first data to the host over the second bus.