Patent ID: 11903199
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A semiconductor device comprising:
lower circuit patterns on a substrate;
a common source plate (CSP) over the lower circuit patterns;
a gate electrode structure on the CSP, the gate electrode structure including gate electrodes spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, and each of the gate electrodes extending in a second direction parallel to the upper surface of the substrate;
a memory channel structure extending through the gate electrode structure on the substrate and connected to the CSP, the memory channel structure including
a channel extending in the vertical direction, and
a charge storage structure surrounding an outer sidewall of the channel;
and
a through via structure including a through via having
a metal pattern extending in the vertical direction and fully enclosing a gap in the metal pattern, wherein the metal pattern includes a seam extending vertically from the gap in the metal pattern, and wherein an etching gas used to form the metal pattern remains in the gap in the metal pattern,
and
a barrier pattern on a sidewall and a lower surface of the metal pattern, and
a capping pattern contacting an upper surface of the through via, the capping pattern including a lowermost edge portion of the capping pattern, the lowermost edge portion is not higher than a lowermost surface of a central portion of the capping pattern.