Patent ID: 11954589
Assignee: STMICROELECTRONICS S.R.L.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 8:
9. A refractory circuit configured to inhibit operation of an integrator circuit after delivery of an output signal, the refractory circuit comprising:
a first transistor having a first conduction terminal coupled to a supply node, a second conduction terminal coupled to a common node, and a control terminal coupled to an output node at which the output signal is delivered;
a second transistor having a first conduction terminal coupled to an input node, a second conduction terminal coupled to a reference node at which a reference voltage is received, and a control terminal coupled to the common node; and
a resistive-capacitive circuit comprising a capacitor coupled between the supply node and the common node and a resistor coupled between the common node and the reference node, wherein a duration of inhabitation of the integrated circuit by the refractory circuit is dependent upon a time constant of the resistive-capacitive circuit.