Patent ID: 11907118
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. A semiconductor apparatus comprising:
one or more substrates; and
logic coupled to the one or more substrates, wherein the logic is implemented in one or more of configurable logic or fixed-functionality logic hardware, the logic coupled to the one or more substrates to:
identify first data and second data to be stored in a data storage, wherein each of the first data and the second data are to be in a first data format;
interleave the first data with the second data to generate interleaved data, wherein the interleaved data is to be in a second data format, and wherein the second data format is different from the first data format;
generate decoded first values from the interleaved data, wherein the decoded first values include the second data being treated as first noise and the first data being maintained; and
execute a mathematical operation based on the decoded first values such that the second data is treated as the first noise and the first data is processed.