Patent ID: 11901013
Assignee: SEAGATE TECHNOLOGY LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. An apparatus comprising:
a non-volatile memory (NVM) comprising semiconductor memory cells;
a read circuit configured to read a programmed state of the memory cells responsive to application of a first of read voltages thereto; and
a read voltage manager circuit configured to perform a first calibration operation to generate the first set of read voltages, accumulate the first set of read voltages into a history distribution comprising additional sets of read voltages obtained by the read voltage manager circuit from a time-ordered sequence of previously performed calibration operations, select a second set of read voltages based on the history distribution, and perform a second calibration operation upon the memory cells by incrementally adjusting the second set of read voltages to arrive at a third set of read voltages that provide an error rate that meets predetermined criteria, the read circuit thereafter using the third set of read voltages during a subsequent read operation after a conclusion of the calibration operation, the read voltage manager circuit appending the third set of read voltages to the history distribution for use during subsequent calibration operations.