Patent ID: 11967566
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 2:
3. A method for fabricating an electronic device, comprising:
exposing first conductive leads to an exterior of a package structure;
exposing second conductive leads to the exterior of the package structure;
placing a multilevel lamination structure in the package structure, the multilevel lamination structure including:
a first patterned conductive feature having multiple turns in a first level to form a first winding coupled to at least one of the first conductive leads in a first circuit;
a second patterned conductive feature having multiple turns in a different level to form a second winding coupled to at least one of the second conductive leads in a second circuit isolated from the first circuit; and
a conductive shield trace having multiple turns in a second level spaced apart from and between the first patterned conductive feature and the second patterned conductive feature, the conductive shield trace coupled in the first circuit.