Patent ID: 11874736
Assignee: APPLE INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 9:
10. A method for data storage, comprising: in a memory controller that communicates with a plurality of memory cells organized in multiple Word Lines (WLs), reading a Code Word (CW) of an Error Correction Code (ECC) from a group of multiple memory cells belonging to a target WL; calculating for a given memory cell in the group, (i) a first soft metric indicative of a first reliability level assigned to the given memory cell depending on a first threshold voltage of a first neighbor memory cell in a first WL neighboring the target WL, and (ii) a second soft metric indicative of a second reliability level assigned to the given memory cell depending on a second threshold voltage of a second neighbor memory cell in a second WL neighboring the target WL; calculating a combined soft metric based on both the first soft metric indicative of a first reliability level assigned to the given memory cell depending on a first threshold voltage of a first neighbor memory cell in a first WL neighboring the target WL and the second soft metric indicative of a second reliability level assigned to the given memory cell depending on a second threshold voltage of a second neighbor memory cell in a second WL neighboring the target WL, and assigning the combined soft metric to the given memory cell; and decoding the CW based at least on the combined soft metric, to produce a decoded CW.