Patent ID: 11923340
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. A semiconductor package, comprising:
a package substrate;
a sub-semiconductor package disposed on the package substrate, the sub-semiconductor package comprising a base chip disposed on the package substrate, a first semiconductor chip disposed on the base chip, a second semiconductor chip disposed on the first semiconductor chip, and an inner mold layer covering an upper surface of the base chip while covering respective side surfaces of the first semiconductor chip and the second semiconductor chip;
a main semiconductor chip disposed on the package substrate while being spaced apart from the sub-semiconductor package; and
an outer mold layer covering the sub-semiconductor package and the main semiconductor chip,
wherein the outer mold layer comprises a first outer mold layer interposed between the package substrate and the base chip and between the package substrate and the main semiconductor chip, and a second outer mold layer covering an upper surface of the first outer mold layer while being spaced apart from the package substrate,
wherein the first outer mold layer and the second outer mold layer have different viscosities, respectively,
wherein an under surface of the first outer mold layer is in contact with the package substrate,
wherein an upper surface of the first outer mold layer is in contact with an under surface of the second outer mold layer,
wherein the upper surface of the first outer mold layer and an outer side surface of the first outer mold layer intersect, and
wherein the under surface of the second outer mold layer and an outer side surface of the second outer mold layer intersect.