Patent ID: 11886538
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. A system, comprising:
a host processor; and
a processor-in-memory device coupled to the host processor, wherein the processor-in-memory device comprises:
a memory array including a plurality of memory locations, wherein each of the memory locations stores a value;
an accumulator coupled to a first group of the plurality of memory locations;
a sense amplifier storing a plurality of bits, wherein the sense amplifier is coupled to the accumulator and the memory array; and

wherein the processor-in-memory device is configured to:
receive a data set comprising a plurality of data batches, wherein each data batch comprises a plurality of data points;
determine to which category of a plurality of categories each data point in a first data batch of the plurality of data batches belongs;
set a value of a flag bit in the sense amplifier, wherein the flag bit corresponds, in a bit position, to the category of the plurality of categories to which a data point in the first data batch of data is determined to belong;
after having set a value of each of a first subset of a set of flag bits in the sense amplifier, each flag bit of the first subset respectively corresponding, in bit position, to a category of data determined to be present in the first data batch of the plurality of data batches, performing, a bit-wise OR operation using the value of the first subset of the set of flag bits stored in the sense amplifier and values in the accumulator as operands to generate a result;
modify one or more values stored in the memory array using the result; and
generate a histogram of the first data batch using the one or more values stored in the memory array.