Patent ID: 11973094
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 13:
14. The manufacturing method of claim 12, wherein the step of forming the first transistor and the second transistor comprises:
forming a low-temperature polysilicon active layer and a first gate insulating layer on the low-temperature polysilicon active layer;
forming the gate of the first transistor and a light-shielding layer of the second transistor by one patterning process;
forming a first interlayer insulating layer, a metal oxide active layer, a second gate insulating layer, a gate of the second transistor, and a second interlayer insulating layer, and performing a patterning process on the second interlayer insulating layer to form a third through hole and a fourth through hole that penetrate through the second interlayer insulating layer to expose the metal oxide active layer;
forming a photoresist layer on the second interlayer insulating layer, the photoresist layer being disposed in the third through hole and the fourth through hole;
patterning the photoresist layer to form a photoresist removal area and a photoresist remaining area;
performing etching by using the photoresist layer as a mask to form a second through hole penetrating through the first interlayer insulating layer and the second interlayer insulating layer to expose the gate of the first transistor and form a fifth through hole and a sixth through hole that penetrate through the first interlayer insulating layer, the second interlayer insulating layer, and the first gate insulating layer to expose the low-temperature polysilicon active layer of the second transistor;
cleaning a surface of the low-temperature polysilicon active layer exposed by the fifth through hole and the sixth through hole with hydrofluoric acid;
removing the photoresist layer; and
forming a source and drain material layer and performing one patterning process to form a source and a drain of the first transistor filling the fifth through hole and the sixth through hole, a second connection electrode filling the second through hole, and a source and a drain of the second transistor filling the third through hole and the fourth through hole.