Patent ID: 11942151
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. A method comprising:
performing a read operation of a memory device having a memory array of resistive memory cells, the read operation including:
precharging a digit line coupled from a sense circuit of the memory device to a memory cell of the memory array, with a first switch between the sense circuit and an access line biasing circuit of the memory device closed to provide a reference current to the sense circuit, with a second switch open, the second switch coupling the access line biasing circuit to an access line to the memory cell, and with a third switch open, the third switch configured in the access line biasing circuit to couple an additional current to a path of the reference current with the third switch closed; and
sensing the memory cell with the first switch open, the second switch closed, and the third switch closed.