Patent ID: 11875244
Assignee: SHANGHAITECH UNIVERSITY
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 2:
3. The eDRAM-based CIM CNN accelerator according to claim 1, wherein the noise compensation circuit comprises an operational amplifier and a write noise compensation cell (WNCC); a target current is permutated, combined, and stacked to obtain a unit current that is 0 to 32 times the target current; after a magnification of the target current is set, the operational amplifier calculates an analog voltage required by the eDRAM cell storage node; the analog voltage is written into 20 WNCCs by using write transistors of the WNCCs, and then a write transistor of each WNCC is turned off, and a read transistor of each WNCC is turned on; and in this case, the reverse turn-off noise is obtained for the analog voltage stored in the 20 WNCCs, and the analog voltage with the reverse turn-off noise drives each write bit line (WBL) by using a rear-stage voltage follower to write to each eDRAM cell storage node of the 5T1C ping-pong eDRAM bit cell array by row.