Patent ID: 11942406
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A method, comprising:
embedding an interconnect bridge within one or more first build-up layers on at least one side of a cored substrate;
forming a first via within the one or more first build-up layers, the first via having a first taper that narrows towards a core of the cored substrate;
attaching, prior to separating the interconnect bridge and the one or more first build-up layers from the core, a carrier to the interconnect bridge and the one or more first build-up layers opposite the core;
separating the interconnect bridge and the one or more first build-up layers from the core;
forming one or more second build-up layers over the interconnect bridge and the one or more first build-up layers opposite the carrier; and
forming a second via within the one or more second build-up layers, the second via having a second taper that is oriented opposite the first taper.