Patent ID: 11868695
Assignee: CADENCE DESIGN SYSTEMS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A method comprising:
accessing an integrated circuit design stored in a database in memory of a hardware device, the integrated circuit design comprising a net comprising a set of driver cells;
performing, by multiple processing threads, resizing of multiple driver cells in parallel, the performing of the resizing of the multiple driver cells comprising:
determining a capacitance increase margin for resizing a driver cell in the net based on a total capacitance of the net and a transition time target of the driver cell;
selecting, from a cell library, an alternative driver cell for resizing the driver cell such that a pin capacitance of the alternative driver cell exceeds an initial pin capacitance corresponding to the driver cell by no more than the capacitance increase margin;
resizing the driver cell using the alternative driver cell, the resizing including replacing the driver cell with the alternative driver cell;

storing an update to the integrated circuit design in the database in memory based on the alternative driver; and
generating, by one or more hardware processors, a layout instance for the integrated circuit design based on the alternative driver, the layout instance describing physical layout dimensions of the integrated circuit design.