Patent ID: 11960770
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus, comprising:
a group of memory devices; and
a controller configured to manage the group of memory devices, the controller further configured to:
receive an access request to access one or more memory devices of the group of memory devices;
issue a set of sub-commands corresponding to the access request to cause the set of sub-commands to be executed on one or more memory devices of the group;
responsive to receiving respective sub-responses for the set of sub-commands indicating completed performance of respective operations corresponding to the respective sub-responses, updating respective statuses of the set of sub-commands to indicate the completed performance; and
responsive to at least one of the respective sub-responses indicating one or more errors on data stored in the group of memory devices:
perform an error recovery operation to recover the data stored in the group of memory devices; and
update the respective statuses of the set of sub-commands to indicate the completed performance subsequent to performing the error recovery operation;

subsequent to updating the respective statuses of the set of sub-commands, transmit a response corresponding to the access request based at least in part on a status of one or more sub-commands of the set.