Patent ID: 11971821
Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. The computing system as claimed in claim 1, further comprising:
a second processor fabricated on a second die, including a third core and a second last-level cache, wherein the third core includes a third in-core cache module;
wherein:
through a channel between the first die and the second die, the first last-level cache further provides the write-back and invalidation request received from the first in-core cache module to the second last-level cache; and
in response to the write-back and invalidation request, the second last-level cache searches itself to determine which cache lines within the second last-level cache match the designated key identification code, wherein: if a matched cache line has been modified and does not exist in any upper-level cache, the second last-level cache writes back the matched cache line to the system memory; and, whether modified or not, all matched cache lines within the second last-level cache are invalidated.