Patent ID: 11880683
Assignee: ADVANCED MICRO DEVICES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A processor comprising:
a register file configured to store data;
a plurality of arithmetic logic units (ALUs); and
circuitry configured to:
receive a first instruction;
read, from the register file, an M-bit source operand indicated by the first instruction, the M-bit source operand comprising a plurality of N-bit source operands;
in response to the first instruction comprising a packed math operation, execute the packed math operation to perform a plurality of operations on data with a size of N bits, wherein to execute the packed math operation the circuitry is configured to:
responsive to fewer than all of the plurality of N-bit source operands having been sent to an ALU, repeatedly send an N-bit source operand of the plurality of N-bit source operands to an ALU of the plurality of ALUs until all of the plurality of N-bit source operands have been sent; and
responsive to all of the plurality of N-bit source operands having been sent to an ALU of the plurality of ALUs,
send an indication to each of the plurality of ALUs specifying a same operation to perform on data with a size of N bits.