Patent ID: 11929329
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A method of forming a semiconductor device, comprising:
forming a low-k dielectric layer over a substrate;
forming a cap layer on the low-k dielectric layer, wherein a carbon atom content of the cap layer ranges from 20 at % to 35 at % and is higher than a carbon atom content of the low-k dielectric layer;
forming a hard mask layer on the cap layer, wherein the hard mask layer comprises an oxide-based mask layer and a metal-containing mask layer on the oxide- based mask layer;
patterning the cap layer and the low-k dielectric layer by using the hard mask layer as a mask, thereby forming a damascene opening in the cap layer and the low-k dielectric layer, wherein the damascene opening has a stepped sidewall in which a step is in the low-k dielectric layer; and
forming a conductive layer in the damascene opening,
wherein the method further comprises forming a four-layer etch stop structure between the low-k dielectric layer and the substrate, wherein the damascene opening has a lower opening and an upper opening wider than the lower opening, and the entire four-layer etch stop structure is located around a lower sidewall of the lower opening.