Patent ID: 11888048
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor device, comprising:
a first nanosheet transistor structure disposed on a semiconductor substrate, the first nanosheet transistor structure including a first nanosheet stack having a first number of first channel layers with adjacent ones of the first channel layers being spaced a first predetermined distance; and
a second nanosheet transistor structure disposed on the semiconductor substrate, the second nanosheet transistor structure including a second nanosheet stack having a second number of second channel layers with adjacent ones of the second channel layers being spaced a second predetermined distance;
wherein the first number of the first channel layers is greater than the second number of the second channel layers;
wherein the second predetermined distance is greater than the first predetermined distance;
wherein a second channel layer that is closest to the semiconductor substrate among the second channel layers is spaced farther from a top surface of the semiconductor substrate than a first channel layer that is closest to the semiconductor substrate among the first channel layers;
wherein the first and second nanosheet transistor structures each include:
a plurality of gate structures respectively comprising at least a gate dielectric layer and a metal gate on the gate dielectric layer;
a plurality of source/drain regions on sides of the first and second nanosheet transistor structures; and
a plurality of dielectric spacers disposed between the plurality of gate structures and the plurality of source/drain regions; and

wherein the second nanosheet transistor structure further includes a plurality of oxide layers disposed around the plurality of gate structures of the second nanosheet transistor structure, wherein a portion of the plurality of oxide layers contacts one or more of the plurality of source/drain regions of the second nanosheet transistor structure.