Patent ID: 11874773
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A method comprising:
accessing a cache that stores cache lines by a processor;
tracking page and cache line accesses to the cache for a single access signature;
generating a spatial bit pattern, for the cache line accesses for each page of a plurality of pages, that is shifted to a first cache line access for each page;
generating a single spatial bit pattern for the single access signature for each of the spatial bit patterns that have a same spatial bit pattern to form a plurality of single spatial bit patterns, performing a logical OR operation on the plurality of single spatial bit patterns to create a first modulated bit pattern for the single access signature;
performing a logical AND operation on the plurality of single spatial bit patterns to create a second modulated bit pattern for the single access signature;
receiving a prefetch request for the single access signature; and
performing a prefetch operation, to prefetch a cache line into the cache from a memory, for the prefetch request using the first modulated bit pattern when a threshold is not exceeded and the second modulated bit pattern when the threshold is exceeded.