Patent ID: 11907720
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A data processing system comprising:
a first data processing apparatus according to claim 1; and
a second data processing apparatus comprising a plurality of registers, each of the registers having data bits to store data, and metadata bits to store metadata, wherein each of the registers is adapted to operate in a metadata mode in which the metadata bits and the data bits are valid, and a data mode in which the data bits are valid and the metadata bits are invalid;
mode bit storage circuitry adapted to indicate whether each of the registers is in the data mode or the metadata mode; and,
execution circuitry, responsive to a memory operation that is a load operation on one or more given elements of a data structure in a memory:
to determine whether an element in the one or more given elements is of a data type or a combined type;
to load the element into the data bits of one of the registers and to set the mode bit storage circuitry to indicate that the one of the registers is in the data mode when the element is of the data type; and,
to load the element into the data bits and the metadata bits of one of the registers when the element is of the combined type.