Patent ID: 11869616
Assignee: CYPRESS SEMICONDUCTOR CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 18:
19. A memory device, comprising:
a plurality of memory banks;
a plurality of comparators, each coupled to a respective memory bank of the plurality of memory banks;
a plurality of error capture units, each coupled to a respective comparator of the plurality of comparators; and
a queue coupled to the plurality of error capture units, wherein the queue configured to store one or more error packets associated with the plurality of memory banks;
wherein each comparator configured to:
perform a memory test on the respective memory bank to generate a respective set of comparison results; and
send the respective set of comparison results to the respective error capture unit;

wherein each error capture unit configured to:
determine a respective set of failure diagnostic information based on the respective set of comparison results;
generate a respective error packet comprising the respective set of failure diagnostic information and the respective set of comparison results;
determine that the first algorithm was used to perform the memory test associated with the respective error packet;
tag the respective error packet with an identifier to the first algorithm to generate a tagged error packet; and
place the tagged error packet in the queue.