Patent ID: 11879939
Assignee: NXP B.V.
Field: Measurement (Instruments)
Classification: CPC G  H | IPC G  H

Claim 17:
18. The IC of claim 16, wherein the clocking system further comprises:
a first clock generator configured to generate an eighth clock signal associated with a shift phase of the at-speed testing mode;
a second clock generator configured to generate a ninth clock signal associated with the capture phase; and
a multiplexer that is coupled to the first clock generator and the second clock generator, and configured to generate the first clock signal based on the eighth clock signal, the ninth clock signal, and a scan enable signal, wherein based on an assertion of the scan enable signal, the first clock signal is same as the eighth clock signal, and based on a de-assertion of the scan enable signal, the first clock signal is same as the ninth clock signal.