Patent ID: 11942954
Assignee: GIGADEVICE SEMICONDUCTOR (SHANGHAI) INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 9:
10. The DLL circuitry system of claim 1, wherein the DLL circuit comprises:
a DLL delay line configured to delay the external clock signal and output the delayed external clock signal;
a clock buffer circuit coupled to the DLL delay line and configured to output the clock signal output from the DLL delay line as the internal clock signal;
a replica clock buffer circuit coupled to the DLL delay line and configured to generate a feedback clock signal based on the clock signal output from the DLL delay line;
a DLL phase detector coupled to the replica clock buffer circuit and configured to compare the external clock signal with the feedback clock signal and determine a phase difference therebetween; and
a DLL controller coupled to the DLL phase detector and the DLL delay line and configured to adjust, based on a comparison result from the DLL phase detector, a delay provided by the DLL delay line and hence the phase difference between internal clock signal and the external clock signal,
wherein the timer unit is coupled to the DLL phase detector, the DLL controller and the replica clock buffer circuit.