Patent ID: 11875869
Assignee: NAVAL UNIVERSITY OF ENGINEERING
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 7:
8. The method of claim 1, wherein the model parameters that affect a turn-on delay tdon are the gate-emitter capacitance CGS, the threshold voltage Vth and the Miller capacitance CGD; the model parameters that affect a current rise time tr are the trans-conductance coefficient Kp, the threshold voltage Vth, the gate-emitter capacitance CGS and the base doping concentration NL; the model parameters that affect a turn-off delay tdoff are the gate-emitter capacitance CGS, the threshold voltage Vth, the trans-conductance coefficient Kp and the gate oxide layer capacitance COXD; the model parameters that affect a current fall time tf are the lifetime of excess carrier in the buffer layer τH, the lifetime of excess carrier in the base region τL, the width of the buffer layer WH, the base width WL and the base doping concentration NL.