Patent ID: 11886882
Assignee: MARVELL ASIA PTE LTD
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 10:
11. A method comprising:
fetching a first instruction of a first thread from a memory into a processor pipeline that is configured to execute instructions from two or more threads in parallel using execution units of the processor pipeline;
detecting that the first instruction has been dispatched into a pipeline stage of the processor;
responsive to detection of dispatch of the first instruction, disabling dispatch of instructions of threads other than the first thread into one or more predetermined pipeline stages of the processor pipeline during execution of the first instruction by an execution unit in at least one of the one or more predetermined pipeline stages of the processor pipeline while one or more of the instructions of threads other than the first thread remain in the processor pipeline;
executing the first instruction using an execution unit of the processor pipeline; and
responsive to completion of execution of the first instruction, enabling dispatch of instructions of threads other than the first thread into the one or more predetermined pipeline stages of the processor pipeline.