Patent ID: 11950407
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A method for forming a memory device, comprising:
forming a first transistor and a second transistor, wherein the first transistor includes a first gate electrode, a first contact electrode, and a shared contact electrode, wherein the shared contact electrode is coupled to a source area or a drain area of the first transistor, and the first gate electrode is coupled to a first word line by a first via, and wherein the second transistor includes a second gate electrode, a second contact electrode, and the shared contact electrode, wherein the shared contact electrode is coupled to a source area or a drain area of the second transistor, the second gate electrode is coupled to a second word line by a second via, wherein the shared contact electrode is on a side of a first channel area and a second channel area opposite the first gate electrode and the second gate electrode of the first and second transistors, respectively;
forming a bit line above the first transistor and the second transistor, and coupled to the shared contact electrode;
forming a first capacitor via in contact with the first contact electrode, and forming a second capacitor via in contact with the second contact electrode; and
forming a first capacitor in contact with the first capacitor via, and forming a second capacitor in contact with the second capacitor via.