Patent ID: 11901027
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. The memory system of claim 7, wherein the sub-input/output circuit group includes:
a third output driver configured to transmit first sub-data among the sub-data, which are divided from the main data by the first modulation circuit, to a first memory device among the memory devices through a first sub-channel included in the sub-channels;
a fourth output driver configured to transmit a first sub-data strobe clock among the sub-data strobe clocks, which are modulated from the main data strobe clock by the second modulation circuit, to the first memory device through the first sub-channel;
a fifth output driver configured to transmit second sub-data among the sub-data, which are divided from the main data by the first modulation circuit, to a second memory device among the memory devices, through a second sub-channel included in the sub-channels; and
a sixth output driver configured to transmit a second sub-data strobe clock among the sub-data strobe clocks, which are modulated from the main data strobe clock by the second modulation circuit, to the second memory device through the second sub-channel.