Patent ID: 11973122
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 0:
1. A method comprising:
forming a first fin protruding from a substrate, the first fin including a second nanostructure over a first nanostructure;
forming an insulating structure laterally surrounding the first fin;
removing a portion of the first fin and forming a boundary structure in the first fin;
forming a dummy gate over the first fin, the dummy gate overlapping an edge of the boundary structure;
etching a recess in the first fin adjacent the dummy gate, the recess exposing the first nanostructure and the second nanostructure;
etching a sidewall recess in the first nanostructure;
depositing a first inner spacer layer over the dummy gate, in the recess, and in the sidewall recess, the first inner spacer layer having a first coefficient of thermal expansion (CTE);
depositing a second inner spacer layer over the dummy gate, in the recess, and in the sidewall recess, the second inner spacer layer having a second CTE;
cooling the first inner spacer layer and the second inner spacer layer; and
etching the first inner spacer layer and the second inner spacer layer to form a first inner spacer and a second inner spacer in the sidewall recess.