Patent ID: 11907725
Assignee: GRAPHCORE LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A system comprising:
a plurality of chips, the plurality of chips including a first chip and a second chip, wherein the first chip includes:
at least one storage comprising a program having a set of executable instructions and an index value identifying the first chip among the plurality of chips;
at least one data memory configured to store data for use in calculations specified by the set of executable instructions; and
at least one execution unit configured to execute the set of executable instructions,

wherein the at least one execution unit is configured to execute the set of executable instructions to:
generate a data packet having first data from the at least one data memory, including selecting the second chip as a destination to which the data packet is to be sent in dependence upon the index value identifying the first chip, and providing an address of the second chip in the data packet; and
dispatch the data packet via routing hardware configured to route the data packet to the second chip.