Patent ID: 11947453
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device, comprising:
a plurality of bank groups, wherein each bank group comprises a plurality of memory banks;
a plurality of row buffers, wherein at least one row buffer of the plurality of row buffers is associated with each memory bank of the plurality of memory banks;
a cache comprising a plurality of cache lines, wherein a size of each cache line of the plurality of cache lines is equal to a size of a first row buffer of the plurality of row buffers;
a processing logic communicatively coupled to the plurality of bank groups and the plurality of row buffers, the processing logic to perform operations comprising:
receiving an activate command comprising a cache hint and an identifier of a row of a memory bank of the plurality of memory banks, wherein the cache hint is encoded by one or more bits and instructs the memory device to cache a content of the identified row;
fetching data from the row identified by the activate command to a second row buffer of the plurality of row buffers; and
copying, based on the cache hint and a caching policy specifying selective data caching, the data to a cache line of the plurality of cache lines.