Patent ID: 11947810
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. The memory system of claim 14,
wherein the on-die ECC engine comprises an ECC encoder and the ECC decoder,
wherein the ECC encoder, during the write operation, is configured to perform the ECC encoding operation on the main data and the system parity data to generate a parity data and is configured to store the main data, the system parity data, and the parity data in a target page of the memory cell array, and
wherein the ECC decoder, during a read operation based on a read command from the memory controller, is configured to perform operations comprising:
reading the main data, the system parity data, and the parity data from the target page;
performing the ECC decoding operation on the main data and the system parity data using the parity data to correct a correctable error in the main data and the system parity data; and
transmitting the main data and the system parity data to the memory controller.