Patent ID: 11901210
Assignee: MONOLITHIC 3D INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H  B | IPC G  H

Claim 14:
15. A 3D semiconductor device, the device comprising:
a first level comprising a plurality of first single-crystal transistors;
a plurality of memory control circuits formed from at least a portion of said plurality of first single-crystal transistors;
a first metal layer disposed atop said plurality of first single-crystal transistors;
a second metal layer disposed atop said first metal layer;
a second level disposed atop said second metal layer, said second level comprising a plurality of second transistors;
a third level comprising a plurality of third transistors,
wherein said third level is disposed above said second level;

a third metal layer disposed above said third level; and
a fourth metal layer disposed above said third metal layer,
wherein said plurality of second transistors are aligned to said plurality of first single crystal transistors with a less than 140 nm and greater than 2 nm of alignment error,
wherein said second level comprises a plurality of first memory cells,
wherein said third level comprises a plurality of second memory cells,
wherein one of said plurality of second transistors is at least partially self-aligned to at least one of said plurality of third transistors, being processed following a same lithography step,
wherein each of said plurality of second memory cells comprises at least one of said plurality of third transistors, and
wherein said memory control circuits perform a mapping of memory addresses from a first address to a second address.