Patent ID: 11881453
Assignee: NANYA TECHNOLOGY CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for preparing a semiconductor device, comprising:
forming a sacrificial source/drain structure over a first carrier substrate;
forming a redistribution structure over the sacrificial source/drain structure;
attaching the redistribution structure to a second carrier substrate;
removing the first carrier substrate after the redistribution structure is attached to the second carrier substrate;
replacing the sacrificial source/drain structure with a first source/drain structure;
forming a backside contact over and electrically connected to the first source/drain structure;
forming an interconnect part over the backside contact, wherein the step of forming the interconnect part comprises:
forming a lower redistribution layer electrically connected to the backside contact;
forming an interconnect structure over and electrically connected to the lower redistribution layer; and
forming an upper redistribution layer over and electrically connected to the interconnect structure;
forming a second source/drain structure between the upper redistribution layer of the interconnect part and the second carrier substrate; and
forming a frontside contact between the second source/drain structure and the second carrier substrate, wherein the second source/drain structure is electrically connected to the second carrier substrate through the frontside contact, wherein a top surface of the first source/drain structure is higher than a top surface of the second source drain structure.