Patent ID: 11868264
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 7:
8. A method comprising:
on a general-purpose graphics processor having a cache memory communicatively coupled with a memory interface:
performing a general-purpose compute operation on compute data associated with multiple cache lines of the cache memory via a processing resource communicatively coupled with the memory interface and the cache memory;
compressing the compute data at cache sector granularity via circuitry communicatively coupled with the cache memory and the memory interface, wherein the cache sector granularity is a sub-block granularity and the circuitry is configured to compress multiple cache lines of the compute data associated with the sector before a write of the compressed compute data via the memory interface;
in association with a read of the compressed compute data associated with the multiple cache lines via the memory interface, decompressing the compressed compute data via the circuitry to generate decompressed compute data; and
providing the decompressed compute data to the processing resource for performance of the general-purpose compute operation.