Patent ID: 11881477
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 13:
14. A method of integrated circuit design, the method comprising:
inserting into an integrated circuit layout file specifications for the locations of a first active device area and of a second active device area;
inserting into the integrated circuit layout file specifications for an isolation structure, wherein the isolation structure surrounds the first active device area, surrounds the second active device area, and extends across a dummy device region from the first active device area to the second active device area;
inserting into the integrated circuit layout file specifications for a first array of linear features, wherein the first array of linear features which are in the first active device area and the first array of linear features has a pitch;
specifying a grid having the pitch, wherein the first array of linear features are on the grid;
inserting into the integrated circuit layout file specifications for a second array of linear features, wherein the second array of linear features are in the second active device area and are on the grid;
inserting specifications for dummy fill into the integrated circuit layout file, wherein the dummy fill comprises a third array of linear features that are on the grid and are between the first active device area and the second active device area;
inserting specifications for a metal interconnect into the integrated circuit layout file, wherein the metal interconnect includes connections to the first array of linear features and connections to the second array of linear features but no connections to the third array of linear features.