Patent ID: 11869567
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. The refresh control circuit of claim 9, wherein the control sub-circuit comprises:
a second random sub-circuit, configured to generate and output a second random number, the second random number being a positive integer;
a first counting sub-circuit, configured to receive L row activation commands one by one, and count the number of the received row activation commands to output a first count value, wherein each row activation command corresponds to a single-row address, and the L row activation commands correspond to the L single-row addresses; and
a value comparison sub-circuit, connected to an output end and a reset end of the second random sub-circuit, connected to an output end and a reset end of the first counting sub-circuit, connected to an input end of the second latch sub-circuit, and configured to: receive the second random number and the first count value; and when the first count value is equal to the second random number, output the trigger signals, and reset the second random sub-circuit and the first counting sub-circuit, to enable the second random sub-circuit to generate and output a new second random number, and to enable the first counting sub-circuit to count from zero again.