Patent ID: 11886341
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. An apparatus, comprising:
a memory system comprising memory configured as a first cache; and
a controller coupled with the memory system, wherein the controller is configured to:
receive a read request, the read request comprising a logical address of the memory system;
load into a memory of the controller, from a portion of a storage area of the memory system, a mapping between logical addresses and physical addresses associated with a region of the memory system associated with the read request based at least in part on receiving the read request, wherein the region of the memory system comprises the logical address of the read request;
store a first entry comprising the mapping to a first location of the first cache based at least in part on loading the mapping, wherein the first cache comprises a plurality of entries in locations determined by an order of read operation recency and the first location of the first cache is associated with a most recent read operation, each entry configured to store a mapping between logical addresses and physical addresses for a respective region of the memory system;
transmit data from a physical address associated with the logical address of the read request based at least in part on storing the first entry;
remove a second entry from the first cache based at least in part on storing the first entry; and
store, to a second cache of the memory system, an index associated with the second entry removed from the first cache, wherein the index identifies a region of the memory system associated with the second entry removed from the first cache.