Patent ID: 11966272
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 3:
4. The system of claim 1,
wherein the host device is configured to control a power mode of the storage device, the power mode comprising an active power mode, an idle power mode, and a deep idle power mode, wherein the communication interface is configured to be placed in an active state in the active power mode and in a hibernate state in the idle power mode and the deep idle power mode, and
wherein, after completing an operation, the control circuitry is configured to transition from the active power mode to the idle power mode, the idle power mode having a first power level and a first exit latency, and
wherein, after a first threshold time after entering the idle power mode, the control circuitry is configured to move host data stored in volatile memory of the storage device to non-volatile memory of the storage device and transition to the deep idle power mode, the deep idle power mode having a second power level lower than the first power level and a second exit latency higher than the first latency.