Patent ID: 11879939
Assignee: NXP B.V.
Field: Measurement (Instruments)
Classification: CPC G  H | IPC G  H

Claim 11:
12. The IC of claim 10, wherein the reset controller further comprises:
a second logic gate that is coupled to the fourth flip-flop and the third inverter, and configured to generate a fourth control signal based on the second control signal, the third control signal, and an inverted version of the first pipeline enable signal, wherein the fourth control signal is de-asserted based on at least one of (i) the de-assertion of the second control signal, (ii) a de-assertion of the third control signal, and (iii) the assertion of the first pipeline enable signal, and wherein the fourth control signal is asserted based on the assertion of the second control signal, the assertion of the third control signal, and the de-assertion of the first pipeline enable signal; and
a third logic gate that is coupled to the counter and the second logic gate, and configured to generate the reset signal based on the fourth control signal and a scan enable signal, and provide the reset signal to the counter, wherein during the capture phase, the scan enable signal is de-asserted and the reset signal is same as the fourth control signal.