Patent ID: 11862267
Assignee: NETLIST, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. The method of claim 11, wherein the data module includes first and second data handlers in first and second integrated circuit packages, respectively, the method further comprising:
during the normal memory read or write operation, propagating, by the first integrated circuit package, first data signals between a first n-bit-wide portion of the memory devices and a first n-bit-wide segment of the system memory bus, and propagating, by the second integrated circuit package, second data signals between a second n-bit-wide portion of the memory devices and a second n-bit-wide segment of the system memory bus independently of and concurrently with the first integrated circuit package propagating the first data signals; and
during testing of the memory module, outputting, by the first integrated circuit package, first test data signal including first test data, and outputting, by the second integrated circuit package, second test data signals including second test independently of and concurrently with the first integrated circuit package outputting the first test data signals, the first data being written into at least one first memory device, the second data being written into at least one second memory device.