Patent ID: 11901180
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A method comprising:
forming a first contact plug extending through a second interlayer dielectric (ILD), an etch stop, and a gate mask dielectric, the first contact plug contacting a source/drain contact, wherein the first contact plug is free from etch damage at an upper surface of the first contact plug; and
forming a second contact plug extending through the second ILD, the etch stop, and the gate mask dielectric, the second contact plug contacting a gate electrode of a gate structure, the gate structure disposed over a semiconductor fin that extends from a substrate, the gate structure comprising: a gate dielectric on the semiconductor fin, the gate electrode on the gate dielectric, and a gate mask over the gate electrode, wherein a first ILD material laterally surrounds the gate structure, the gate mask dielectric extending continuously over an upper surface of the first ILD material, wherein the etch stop is disposed over the gate mask dielectric.