Patent ID: 11908921
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 7:
8. A method, comprising:
forming a fin structure on a substrate, wherein the fin structure comprises alternating first and second nanostructure elements;
forming a sacrificial gate structure over the fin structure, wherein edge portions of the fin structure are not covered by the sacrificial gate structure;
removing the edge portions of the fin structure;
etching edge portions of the first nanostructure elements in the fin structure to form cavities;
depositing a spacer material on the sacrificial gate structure and the fin structure to fill the cavities;
treating the spacer material with a post-deposition treatment;
removing a portion of the spacer material in the cavities to form an opening in the spacer material; and
forming source/drain (S/D) epitaxial structures on the substrate to abut the fin structure so that the S/D epitaxial structures are in contact with the second nanostructure elements and isolated from the first nanostructure elements by the spacer material, wherein sidewall portions of the S/D epitaxial structures seal the opening in the spacer material to form an air gap in the spacer material.