Patent ID: 11923472
Assignee: THE UNITED STATES OF AMERICA AS REPRESENTED BY THE SECRETARY OF THE ARMY
Field: Semiconductors (Electrical engineering)
Classification: CPC H  Y | IPC H

Claim 15:
16. A deformable array of semiconductor devices comprising:
a plurality of islands arranged in an auxetic geometry so that the array exhibits a negative Poisson's ratio when loaded under tensile strain; and
a plurality of serpentine interconnects coupling the plurality of islands to one another, each having a first end which connects to one island and a second end which connects to an adjacent island and a plurality of bends therebetween,
wherein the islands and interconnects lie in the same plane in an unstretched condition,
wherein, in the unstretched condition, each interconnect couples, at its first end, to the one island near one corner of the one island, extends in a direction toward another corner of the one island, bends in the same plane to extend in the opposite direction to back towards the one corner of the one island, at least twice, and couples, at its second end, to the adjacent island, and
wherein a semiconductor device is formed within or on at least one of the islands and/or at least one of the serpentine interconnects.