Patent ID: 11972835
Assignee: DENSO TEN LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A latch circuit device for a microcomputer having a normal state and a sleep state, comprising:
a latch circuit latching an input signal to the microcomputer;
a detection circuit detecting the input signal during the sleep state to output a detection signal;
a wake-up circuit outputting a wake-up signal to the microcomputer in response to the detection signal;
a sampling circuit having a sampling input to receive the input signal from the latch circuit;
a transmission circuit having a transmission input to receive the input signal from the sampling circuit and to output the input signal to the microcomputer in response to the wake-up signal; and
a release circuit outputting a latch release signal to the latch circuit upon the input signal being read to the microcomputer,
wherein, in the normal state, the sampling circuit periodically receives a read request signal from the microcomputer and receives the input signal from the latch circuit in response to the read request signal, and the transmission circuit receives the input signal from the sampling circuit to output the input signal to the microcomputer.