Patent ID: 11972347
Assignee: TECHNION RESEARCH & DEVELOPMENT FOUNDATION LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. The system of claim 7, wherein the at least one hardware processor is further adapted to:
cluster the plurality of training iterations into a plurality of iteration groups;
in each of a first plurality of training iterations of a first iteration group compute the set of transformed values using the first set consisting of the first identified amount of values and the second set consisting of the second identified amount of values; and
for each subsequent group of the plurality of iteration groups not the first iteration group:
in each of a subsequent plurality of training iterations of the subsequent group compute the set of transformed values using a new first set consisting of a new first identified amount of values, and a new second set consisting of a new second identified amount of values;
wherein each of the new first set and second new set is a value from 0 to 1;
wherein the new first identified amount of values is less than or equal the first identified amount of values; and
wherein the new second identified amount of values is less than or equal the second identified amount of values.