Patent ID: 11897539
Assignee: SEIKO EPSON CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC B  G  H | IPC B  G  H

Claim 4:
5. The circuit device according to claim 1, wherein
the first integration period is zoned by a transition timing of the first integration polarity switching signal into a first anterior half period and a first posterior half period,
the first integration circuit performs the first integrating process in a first polarity in the first anterior half period, and performs the first integrating process in a second polarity as an opposite polarity to the first polarity in the first posterior half period,
the second integration period is zoned by a transition timing of the second integration polarity switching signal into a second anterior half period and a second posterior half period, and
the second integration circuit performs the second integrating process in the first polarity in the second anterior half period, and performs the second integrating process in the second polarity in the second posterior half period.