Patent ID: 11881771
Assignee: NXP USA, INC.
Field: Electrical machinery, apparatus, energy (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 16:
17. The method of claim 16, further comprising:
during the falling phase of the half-bridge voltage, the controller circuit comparing a value of the multi-bit status signal with a second lower limit value corresponding to a second lower limit voltage, to determine whether the half-bridge voltage is lower than the second lower limit voltage; and
the low-side delay circuit generating the low-side control signal using the delay control signal to add a predetermined delay time into the current third delay time in response to the half-bridge voltage being lower than the second lower limit voltage;
and wherein the method further comprises:
during the falling phase of the half-bridge phase, the high-side delay circuit generating the high-side control signal using the delay control signal to reduce a predetermined delay time from a current fourth delay time in response to the half-bridge voltage being lower than the second lower limit voltage.