Patent ID: 11875040
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. The semiconductor system of claim 10, wherein the controller comprises:
a queuing circuit configured to:
store external addresses for performing a tracking write operation and the write operation as first and second write addresses,
store external addresses for performing a tracking read operation and the read operation as first and second read addresses, and
output one of the stored first and second write addresses and the stored first and second read addresses as a selection address based on a write read selection signal; and

a bank control circuit configured to:
generate, from a request signal, the command for performing an active operation, the tracking read operation, the read operation, the tracking write operation, and the write operation based on a flag signal that is disabled when the tracking write operation is performed, and
generate the address from the selection address.