Patent ID: 11869593
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 12:
13. A semiconductor memory device, comprising:
a memory cell;
a first word line coupled between a control end of the memory cell and a first node;
a resistance element coupled between the first node and a second node;
a control circuit configured to output a voltage to the second node; and
a detection circuit coupled to the first node and the second node and configured to:
selectively acquire a voltage of one of the first node and the second node and then acquire a voltage of the other node of the first node and the second node; and
change a level of a voltage of a first signal to be output, in accordance with the voltage of the other node being higher than the selectively acquired voltage, or
change the level of the voltage of the first signal in accordance with the voltage of the other node being lower than the selectively acquired voltage.