Patent ID: 11901865
Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A low power crystal oscillator circuit, comprising:
a crystal having an input terminal and an output terminal;
a high power supply;
a low power supply;
a first capacitor having a first terminal coupled to the crystal input terminal and a second terminal coupled to the low power supply;
a first current mirror transistor having a first terminal coupled to the high power supply and a gate terminal coupled to a second terminal of the first current mirror transistor, the first current mirror transistor having a channel with a first width to length ratio;
a first current source outputting current of a first value, the first current source having a first terminal coupled to the second terminal of the first current mirror transi sior and a second terminal coupled to the low power supply;
a second current mirror transistor having a first terminal coupled to the high power supply and a gate coupled to the gate terminal of the first current mirror transistor and a second terminal, the second current mirror transistor having a second width to length ratio that is X times greater than the first width to length ratio;
a first startup control transistor having a first terminal coupled to the second terminal of the second current mirror transistor, a gate terminal configured to receive a startup control signal and a second terminal coupled to the crystal output terminal;
a third current mirror transistor having a first terminal coupled to the high power supply and a gate terminal coupled to a second terminal of the third current mirror transistor, the third current mirror transistor having a third width to length ratio;
a second current source outputting current of a second value, the second current source having a first terminal coupled to the second terminal of the third current mirror transistor and a second terminal coupled to the low power supply, the current of the second value being less than the current of the first value;
a fourth current mirror transistor having a first terminal coupled to the high power supply, a gate coupled to the gate terminal of the third current mirror transistor and a second terminal, the fourth current mirror transistor having a fourth width to length ratio that is Y times greater than the third width to length ratio;
a second startup control transistor having a first terminal coupled to the second terminal of the fourth current mirror transistor, a gate terminal configured to receive an inverse startup control signal and a second terminal coupled to the crystal output terminal; and
a third capacitor having a first terminal coupled to the gates of the third and fourth current mirror transistors and a second terminal coupled to the input terminal of the crystal.