Patent ID: 11880597
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 1:
2. The read operation circuit according to claim 1, wherein the data determination module comprises:
a data comparison unit, an input terminal of the data comparison unit being connected to the memory bank, wherein the data comparison unit is configured to set the change flag data to Low if there is no change between the current read data and the previous read data, and set the change flag data to High if there is the change between the current read data and the previous read data;
a data determination unit, an input terminal of the data determination unit being connected to an output terminal of the data comparison unit to receive the change flag data, an output terminal of the data determination unit being connected to the inversion flag signal line, wherein the data determination unit is configured to set the inversion flag data to High if the number of bits of the high data in the change flag data is greater than the preset value, and set the inversion flag data to Low if the number of bits of the high data in the change flag data is less than or equal to the preset value; and
a data selector, an input terminal of the data selector being configured to receive the inversion flag data through the inversion flag signal line, an output terminal of the data selector being connected to the global bus, wherein the data selector is configured to output inverted data of the current read data as the global bus data if the inversion flag data is High, and output the original current read data as the global bus data if the inversion flag data is Low.