Patent ID: 11914525
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. A system comprising:
a last-level cache (LLC);
a processor having deep learning (DL) hardware circuitry communicatively coupled to the LLC by an interconnect, wherein the DL hardware circuitry execute one or more layers of a DL network using the LLC; and
a system cache controller communicably coupled to the DL hardware circuitry and the LLC, the system cache controller to:
receive, from the DL hardware circuitry, a cache access request;
responsive to a cache line conflict in the LLC for the cache access request, implement a context-based eviction policy to determine a cache way in the LLC to evict in order to resolve the cache line conflict; and
responsive to a cache miss for the cache access request, select a variable cache line size to allocate and fill from the LLC, wherein the variable cache line size is selected based on a total size of data indicated in metadata received with the cache access request and based on data utilization of the LLC by the DL network.