Patent ID: 11948871
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A method of fabricating an integrated circuit (IC) in a package comprising:
forming first and second conductive lines, each having first and second surfaces, wherein the first surfaces of the first and second conductive lines are directly coupled to a silicon wafer, and having a space between the first and second conductive lines;
applying a first insulation block having first and second portions, wherein the first portion has a first surface directly coupled to the silicon wafer, and the second portion has a first surface directly coupled to the second surface of the first conductive line;
applying a second insulation block having third, fourth and fifth portions, wherein the third portion has a first surface directly coupled to the second surface of the first conductive line, the fourth portion is coupled to the silicon wafer, the first conductive line and the second conductive line, and the fifth portion is directly coupled to the second surface of the second conductive line;
applying a third insulation block having sixth, seventh and eighth portions, wherein the sixth portion is directly coupled to the second surface of the second conductive line, and the seventh portion is directly coupled to the silicon wafer;
forming a conductive pillar that is directly coupled to the second surface of the first conductive line, to the second portion, and to the third portion;
applying a first conductive adhesive to the second surface of the second conductive line filling a space between the second insulation block and the third insulation block;
bonding a first capacitor terminal to a first lead frame terminal using a second conductive adhesive; and
mating a second lead frame terminal to the conductive pillar using a third conductive adhesive, and mating a second capacitor terminal to the second conductive line using the first conductive adhesive.