Patent ID: 11971780
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A data error correction circuit, comprising:
a decoding circuit, having an input terminal connected to a data bus, and configured to receive first data and a check code of the first data and output an error correction code of the first data based on the check code; and
an error correction latch module, comprising a first latch unit, an error correction unit, and a second latch unit, the error correction latch module having a first input terminal connected to the data bus and a second input terminal connected to an output terminal of the decoding circuit, and configured to latch the first data corresponding to the error correction code and generate and output second data according to the error correction code and the corresponding first data;
wherein the first data comprises M bits of data, and the first latch unit comprises N L-bit latches, wherein N*L=M, and N≥1:
N=1, L=M, the first latch unit performs serial output, the decoding circuit performs serial output, the error correction unit comprises one error corrector, an input terminal of the error corrector is connected to an output terminal of the first latch unit, an enable terminal of the error correction unit is connected to the output terminal of the decoding circuit, and an output timing of the error correction code is the same as a data output timing of the first latch unit, the second latch unit comprises one M-bit shift register, and the second latch unit performs serial input; or
the first latch unit performs parallel output and comprises M output terminals, the decoding circuit performs parallel output and comprises M output terminals, the error correction unit comprises M error correctors, each of the M error correctors has an enable terminal connected to one of the M output terminals of the decoding circuit, and each of the M error correctors has an input terminal connected to one of the M output terminals of the first latch unit, the second latch unit comprises S K-bit shift registers, S*K=M, the second latch unit performs parallel input, and S≥1;

the error corrector or each of the M error correctors comprises an inverter and a pass transistor connected in parallel.