Patent ID: 11916006
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A microelectronic assembly, comprising:
a package substrate having a surface;
a die having a first surface and an opposing second surface, wherein the first surface of the die is coupled to the surface of the package substrate by first interconnects;
a chiplet, having a third surface and an opposing fourth surface, between the surface of the package substrate and the first surface of the die, wherein the first interconnects are between the surface of the package substrate and the first surface of the die and adjacent to the chiplet, and wherein the chiplet includes:
an element at the third surface of the chiplet, wherein the element is coupled to the surface of the package substrate by second interconnects between the surface of the package substrate and the third surface of the chiplet, and wherein the element includes a switching transistor or a diode; and
a capacitor at the fourth surface of the chiplet, wherein the capacitor is coupled to the first surface of the die by third interconnects.