Patent ID: 11860775
Assignee: SILICON MOTION, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. An apparatus for programming data into flash memory, comprising:
a first processing unit;
a random access memory (RAM);
a host interface (I/F), coupled to a host side;
a redundant array of independent disks (RAID) engine;
a data access engine, coupled to a flash module;
a routing engine, coupled to the first processing unit and the host I/F, arranged operably to: receive operating settings and a front-end parameter set of a first data-programming transaction from the first processing unit, wherein the operating settings indicate whether each of a front-end processing stage, a mid-end processing stage and a back-end processing stage is required to be activated; and drive the host I/F to obtain first data from the host side and store the first data in a first designated address of the RAM through a shared bus architecture according to the front-end parameter set when determining that the front-end processing stage needs to be activated for the first data-programming transaction according to the operation settings; and
an accelerator, coupled to the first processing unit, the routing engine, the RAID engine and the data access engine, arranged operably to: receive the operation settings, a mid-end parameter set and a back-end parameter set from the first processing unit; drive the RAID engine to obtain second data from a second designated address of the RAM through the shared bus architecture, and encrypt the second data or generate a parity-page data in terms of multiple pages of the second data according to the mid-end parameter set when receiving an activation message for the first data-programming transaction from the routing engine and determining that the mid-end processing stage needs to be activated for the first data-programming transaction according to the operation settings; and drive the data access engine to obtain third data from a third designated address of the RAM through the shared bus architecture and program the third data into a designated address of the flash module when determining that the mid-end processing stage does not need to be activated for the first data-programming transaction according to the operation settings or the mid-end processing stage has been completed, and the back-end processing stage needs to be activated for the first data-programming transaction according to the operation settings.