Patent ID: 11862697
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 19:
20. A method for manufacturing a buried gate, comprising:
providing a trench on an active region of a substrate;
filling a gate structure in a bottom of the trench, and exposing a trench sidewall above the gate structure, which comprises:
forming a dielectric layer on an inner wall of the trench; and
filling a first conductive layer in the trench, and back-etching the first conductive layer to a preset depth;

growing an epitaxial layer on the exposed trench sidewall with an epitaxial growth process, wherein the epitaxial layer does not close the trench; and
filling an isolation layer in the trench,
wherein the first conductive layer is metal; and
wherein after back-etching the first conductive layer to the preset depth, the method further comprises:
forming a polysilicon layer covering the first conductive layer in the trench, the polysilicon layer not fully filling the trench.