Patent ID: 11868245
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A memory device comprising:
a memory array; and
a memory controller configured to receive commands from a host device, the memory controller including processing circuitry including one or more processors, and is configured to perform operations including:
receiving a first memory access command from a host, the first memory access command to access the memory arrays of the memory device;
determining that the first memory access command is a sequential read command;
determining whether an LBA-to-physical address (L2P) region of an L2P cache includes a first LBA received with the first memory access command;
in response to determining that the L2P cache does not include the first LBA of the first memory access command, and that the first memory access command is a sequential read command, performing one load of multiple L2P regions of an L2P table from the memory array to the L2P cache;
determining a first physical address of the memory array based on the first LBA and a first L2P region of the multiple L2P regions within the L2P cache; and
executing the first memory access command based at least in part on the first physical address.