Patent ID: 11950468
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 7:
8. The display panel according to claim 1, wherein the display panel further comprises:
a gate line layer, wherein the gate line layer includes a gate line pattern located in each of the plurality of sub-pixel areas, and at least part of the gate line pattern extends along the first direction;
a data line layer, wherein the data line layer includes a data line pattern located in each of the plurality of sub-pixel areas, at least part of the data line pattern extends along the second direction, and an orthographic projection of the data line pattern on the substrate overlaps an orthographic projection of the gate line pattern on the substrate;
a conductive connection portion layer, wherein the conductive connection portion layer includes a third conductive connection portion and a fourth conductive connection portion located in each of the plurality of sub-pixel areas;
sub-pixel driving circuits corresponding to the plurality of sub-pixel areas in a one-to-one manner, each of the plurality of sub-pixel driving circuits includes: a driving transistor, a storage capacitor, a first transistor and a second transistor; a gate electrode of the driving transistor is multiplexed as a first electrode plate of the storage capacitor, and the gate electrode of the driving transistor is coupled to a second electrode of the second transistor through the fourth conductive connection portion in the corresponding sub-pixel area, and the second electrode plate of the storage capacitor is coupled to a second electrode of the first transistor through the third conductive connection portion in the corresponding sub-pixel area; a gate electrode of the first transistor and a gate electrode of the second transistor are respectively coupled to the gate line pattern in the corresponding sub-pixel area; an orthographic projection of the gate line pattern on the substrate does not overlap an orthographic projection of the third conductive connection portion on the substrate, and/or the orthographic projection of the gate line pattern on the substrate does not overlap an orthographic projection of the fourth conductive connection portion on the substrate.