Patent ID: 11868403
Assignee: JPMORGAN CHASE BANK, N.A.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A computing device configured to implement an execution of a method for utilizing a graph path cache to facilitate real-time data consumption by a plurality of machine learning models, the computing device comprising:
a processor;
a memory; and
a communication interface coupled to each of the processor and the memory,
wherein the processor is configured to:
receive at least one input from at least one source, the at least one input relating to a request to characterize at least one data element;
retrieve at least one data attribute that corresponds to the at least one data element from at least one data management system;
determine, in real-time by using the graph path cache, at least one graph attribute that corresponds to the at least one data element by performing deep link analysis on a graph database,
wherein the graph path cache includes a precomputation of at least one graph path hop for each of a plurality of high-density vertices; and
wherein the at least one graph path hop corresponds to a phase in a first sequence of at least one edge that joins a second sequence of distinct vertices;

execute, in real-time, at least one model by using the at least one data attribute and the at least one graph attribute, the at least one model corresponding to the request in the at least one input; and
transmit, in real-time, a result of the executed at least one model to the at least one source in response to the at least one input.