Patent ID: 11955332
Assignee: APPLIED MATERIALS, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A processing system, comprising:
a first processing chamber;
a second processing chamber;
a third processing chamber;
a fourth processing chamber;
a fifth processing chamber;
a sixth processing chamber;
a seventh processing chamber;
an eighth processing chamber;
a ninth processing chamber; and
a system controller configured to cause the processing system to:
pre-clean a surface of a substrate in the first processing chamber;
form an interfacial layer on the pre-cleaned surface of the substrate in the second processing chamber;
deposit a high-κ gate dielectric layer on the interfacial layer in the third processing chamber;
perform a plasma nitridation process to insert nitrogen atoms in the deposited high-κ gate dielectric layer in the fourth processing chamber;
subsequent to the plasma nitridation process, perform a post-nitridation anneal process in the fifth processing chamber, to passivate chemical bonds in the plasma nitridated high-κ gate dielectric layer;
deposit a high-κ dielectric cap layer on the plasma nitridated high-κ gate dielectric layer in the sixth processing chamber;
deposit a sacrificial silicon cap layer on the high-κ dielectric cap layer in the seventh processing chamber;
perform a post cap anneal process to harden and densify the as-deposited high-κ dielectric cap layer in the eighth processing chamber; and
remove the sacrificial silicon cap layer in the ninth processing chamber.