Patent ID: 11875836
Assignee: KEPLER COMPUTING INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus comprising:
a memory organized in a plurality of memory banks, wherein the plurality of memory banks comprises memory bit-cells, wherein an individual memory bit-cell includes a non-volatile material to store data, and wherein the non-volatile material includes one of: a non-linear polar material, a magnet, or a resistive material; and
a memory controller coupled to the memory, wherein the memory controller includes one or more circuitries which improve memory endurance of the memory via wear leveling, wherein the wear leveling is applied during read or write operations to the memory, wherein the memory controller is to apply an outlier compensation scheme before or after the wear leveling, and wherein an array outside of a memory bank of the plurality of memory banks is queried.