Patent ID: 11877442
Assignee: NANYA TECHNOLOGY CORPORATION
Field: nan (nan)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor memory device, comprising:
a substrate, which has a storage area and a peripheral area, wherein the storage area has a contact plug,
a bit line structure adjacent to the contact plug,
an air gap between the bit line structure and the contact plug,
a barrier layer conformally overlaying the bit line structure, and
a landing pad above the barrier layer,
wherein the substrate comprises:
a trench between the storage area and the peripheral area;
a nitride material being filled in the trench at a position that a top surface of the nitride material is coplanar with a top surface of the trench;
a first oxide layer formed above the nitride material in the trench and on the landing pad at a position that a bottom surface of the first oxide layer is in direct contact with the top surfaces of the trench and the nitride material;
a nitride layer formed above the first oxide layer at a position that a bottom surface of the nitride layer is in direct contact with a top surface of the first oxide layer; and
a second oxide layer formed above the nitride layer at a position that a bottom surface of the second oxide layer is in direct contact with a top surface of the nitride layer.