Patent ID: 11875229
Assignee: CLASSIQ TECHNOLOGIES LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. An apparatus comprising a processor and coupled memory, said processor being adapted to:
obtain a logical representation of a quantum circuit, wherein the logical representation comprises a plurality of logical qubits, wherein the logical representation defines gate operations on subsets of the plurality of logical qubits in a plurality of cycles, wherein the plurality of logical qubits comprises one or more logical output qubits, wherein the quantum circuit is configured to provide an output via the one or more logical output qubits;
modify the quantum circuit to transfer a gate operation defined in a first cycle to be performed in a second cycle, thereby obtaining a modified quantum circuit, wherein said modifying does not change a functionality of the quantum circuit; and
synthesize the modified quantum circuit, the synthesized modified quantum circuit implements a dynamic error correction scheme, wherein the dynamic error correction scheme implements error correction operations using a first assignment of first physical qubits to a logical qubit for a first set of cycles and using a second assignment of second physical qubits to the logical qubit for a second set of cycles, wherein the first set of cycles comprises the first cycle, and the second set of cycles comprises the second cycle, wherein a number of the second physical qubits is greater than a number of the first physical qubits, wherein the dynamic error correction scheme utilizes a larger number of physical qubits than a number of represented logical qubits at least in the second set of cycles.