Patent ID: 11937444
Assignee: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G  Y | IPC H

Claim 5:
6. The flexible display substrate according to claim 5, wherein the film layers in the first bonding region and the second bonding region are arranged according to any of the following configurations:
the film layers in the first bonding region comprise a gate layer, an interlayer dielectric layer, and a source and drain layer that are sequentially on the base substrate, and the film layers in the second bonding region comprise an interlayer dielectric layer and a source and drain layer that are sequentially on the base substrate;
the film layers in the first bonding region comprise a first gate layer, a gate insulating layer, a second gate layer, an interlayer dielectric layer, and a source and drain layer that are sequentially on the base substrate, and the film layers in the second bonding region comprise an interlayer dielectric layer and a source and drain layer that are sequentially on the base substrate;
the film layers in the first bonding region comprise a gate layer, an interlayer dielectric layer, a first source and drain layer, a planarization layer, and a second source and drain layer that are sequentially on the base substrate, and the film layers in the second bonding region comprise an interlayer dielectric layer and one of the first source and drain layer and the second source and drain layer that are sequentially on the base substrate;
the film layers in the first bonding region comprise a gate layer, an interlayer dielectric layer, a first source and drain layer, a planarization layer, and a second source and drain layer that are sequentially on the base substrate, and the film layers in the second bonding region comprise a gate layer, an interlayer dielectric layer, and one of the first source and drain layer and the second source and drain layer that are sequentially on the base substrate;
the film layers in the first bonding region comprise a first gate layer, a gate insulating layer, a second gate layer, an interlayer dielectric layer, a first source and drain layer, a planarization layer, and a second source and drain layer that are sequentially on the base substrate, and the film layers in the second bonding region comprise a first gate layer, a gate insulating layer, and one of the first source and drain layer and the second source and drain layer that are sequentially on the base substrate;
the film layers in the first bonding region comprise a first gate layer, a gate insulating layer, a second gate layer, an interlayer dielectric layer, a first source and drain layer, a planarization layer, and a second source and drain layer that are sequentially on the base substrate, and the film layers in the second bonding region comprise a gate insulating layer and one of the first source and drain layer and the second source and drain layer that is on the base substrate that are sequentially on the base substrate;
the film layers in the first bonding region comprise a buffer layer, a gate layer, an interlayer dielectric layer, and a source and drain layer that are sequentially on the base substrate, and the film layers in the second bonding region comprise a gate layer, an interlayer dielectric layer, and a source and drain layer that are sequentially on the base substrate; and
the film layers in the first bonding region comprise a gate layer, an interlayer dielectric layer, and a source and drain layer that are sequentially on the base substrate, and the film layers in the second bonding region comprise a source and drain layer on the base substrate.