Patent ID: 11942422
Assignee: nan
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 8:
9. A method of forming a microelectronic device, comprising:
forming a stack structure comprising tiers individually including insulative material and additional material vertically adjacent the insulative material;
forming a trench extending into the stack structure;
forming insulative spacer material on side surfaces of the stack structure partially defining the trench;
forming liner material on inner side surfaces of the insulative spacer material, the liner material physically contacting the additional material of at least one of the tiers of the stack structure;
extending a portion of the trench horizontally inward of vertically extending portions the liner material vertically deeper into the stack structure to form an extended trench;
forming additional insulative spacer material on inner side surfaces of remaining portions of the liner material after forming the extended trench;
forming additional liner material on inner side surfaces of the additional insulative spacer material, the additional liner material physically contacting the additional material of at least one other of the tiers of the stack structure; and
at least partially replacing the liner material, the additional liner material, and the additional material of the tiers of stack structure with conductive material.