Patent ID: 11862703
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 10:
11. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a first vertical arrangement of nanowires above a substrate, the first vertical arrangement of nanowires having an uppermost nanowire, each nanowire of the first vertical arrangement of nanowires having a channel region;
a dielectric cap over the first vertical arrangement of nanowires, wherein the dielectric cap is vertically spaced apart from the uppermost nanowire of the first vertical arrangement of nanowires, and wherein the dielectric cap extends laterally across an entirety of the channel region of the uppermost nanowire of the first vertical arrangement of nanowires;
a gate stack over the first vertical arrangement of nanowires and over the dielectric cap, the gate stack vertically surrounding the channel region of each nanowire of the first vertical arrangement of nanowires, and the gate stack vertically surrounding the dielectric cap; and
a second vertical arrangement of nanowires laterally spaced apart from the first vertical arrangement of nanowires, wherein the dielectric cap is at a height above an uppermost nanowire of the second vertical arrangement of nanowires.