Patent ID: 11876727
Assignee: PANASONIC HOLDINGS CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A transmitter comprising:
an input terminal into which cells are to be input from a block interleaver, the block interleaver including a matrix for block interleaving, the matrix having N columns, the cells being generated using low-density parity check (LDPC) coding;
an output terminal from which the cells are to be output such that each of the cells is classified in any one of M interleaving units;
a convolutional delay circuit comprising: M branches; and first in, first out (FIFO) registers to delay cells, a number of the FIFO registers provided in an M'th branch being M'-1, M' being an integer from 1 to M;
a first switch provided between the input terminal and the convolutional delay circuit;
a second switch provided between the convolutional delay circuit and the output terminal; and
an antenna that transmits a radio wave according to the cells output from the output terminal, wherein
the first switch and the second switch are each configured to connect to an identical branch of the M branches such that the input terminal and the output terminal are connected via the identical branch, and
the first switch and the second switch are each configured to connect to an L+1th branch or a first branch when N cells are input into the input terminal while the first switch and the second switch each connect to an Lth branch, L being an integer from 1 to M.