Patent ID: 11891298
Assignee: STMICROELECTRONICS S.R.L.
Field: Micro-structural and nano-technology (Chemistry)
Classification: CPC B  H | IPC B  H

Claim 9:
10. A device, comprising:
a coating region having a first surface and a second surface opposite to the first surface of the coating region;
a dielectric region of a redistribution structure having a first surface, in contact with the first surface of the coating region, and a second surface opposite to the first surface of the dielectric region;
a die in the coating region;
a plurality of conductive regions in the coating region, extending to the first surface of the coating region, and electrically coupled to the die;
a plurality of conductive paths in the dielectric region of the redistribution structure and extending from the first surface of the dielectric region to the second surface of the dielectric region;
a plurality of conductive pillars extending outward from the second surface of the dielectric region of the redistribution structure and coupled to the plurality of conductive regions by the plurality of conductive paths;
a multilayer region including a plurality of membranes;
a plurality of pads on the multilayer region and in electrical contact with the plurality of conductive pillars;
a plurality of actuators on the plurality of membranes and electrically coupled to the plurality of pads;
a bonding region couples the multilayer region to the dielectric region of the redistribution structure, the bonding region including a surface facing away from the multilayer region and spaced apart from the multilayer region;
an interstitial region on and in contact with the surface of the bonding region, the interstitial region including a plurality of sidewalls transverse to the surface of the bonding region;
a semiconductor region on the multilayer region and between respective sidewalls of the plurality of sidewalls of the interstitial region;
a buried dielectric region on the semiconductor region; and
a covering region between the plurality of sidewalls of the interstitial region, on the multilayer region, and covering the semiconductor region and the buried dielectric region.