Patent ID: 11925011
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. The memory structure of claim 1, wherein:
the dummy FinFET is a first dummy FinFET;
the n-type epitaxial source/drains are first n-type epitaxial source/drains and the p-type epitaxial source/drains are first p-type epitaxial source/drains;
the n-well, the first p-well, and the second p-well further span a third region along the second direction; and
the memory structure further includes:
in the first region, a pull-up FinFET disposed over the n-well, wherein:
the pull-up FinFET include a first n-type semiconductor fin extending from the n-well, wherein the first n-type semiconductor fin extends lengthwise along the second direction and the first n-type semiconductor fin has a third width along the first direction, and
the pull-up FinFET includes second p-type epitaxial source/drains disposed on the first n-type semiconductor fin; and

in the third region, a second dummy FinFET is disposed over the n-well, wherein:
the second dummy FinFET includes a second n-type semiconductor fin extending from the n-well, wherein the second n-type semiconductor fin extends lengthwise along the second direction and the second n-type semiconductor fin has a fourth width along the first direction,
the second dummy FinFET includes second n-type epitaxial source/drains disposed on the second n-type semiconductor fin, and
the fourth width is greater than the third width.