Patent ID: 11886346
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. A system comprising:
a memory device comprising a memory array configured with a plurality of memory planes; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
sending, to the memory device, a plurality of cache read commands requesting first data from the memory array spread across a plurality of memory planes;
sending, to the memory device, a cache read context switch command and a snap read command requesting second data from a single plane of the plurality of memory planes of the memory array, the cache read context switch command to cause the memory device to suspend processing of the plurality of cache read commands and process the snap read command to read the second data from the single plane of the plurality of memory planes of the memory array, wherein the cache read context switch command and the snap read command are sent to the memory device with an indication of a higher priority than the plurality of cache read commands; and
receiving the second data from the memory device.