Patent ID: 11881258
Assignee: GLOBALFOUNDRIES U.S. INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 7:
8. An apparatus comprising:
an amplifier coupled to a bit cell of a memory array to detect a first voltage indicating a memory state of the bit cell at a first instance;
a latch coupled to the amplifier to store a second voltage indicating a memory state of the bit cell at a second instance; and
logic coupled to the latch and the amplifier, wherein the logic outputs a first signal in response to the first voltage not being equal to the second voltage, and outputs a second signal in response to the first voltage being equal to the second voltage, wherein the first signal indicates the bit cell as being unstable, and the second signal indicates the bit cell as being stable, and wherein the logic includes:
an exclusive or (XOR) gate receiving the first voltage and the second voltage from the sensing circuit and configured to output the signal indicating the memory state of the bit cell as a flag bit; and
an OR gate receiving the first voltage and the second voltage, and configured to configured to output one of the first signal and the second signal in parallel with the flag bit.