Patent ID: 11876535
Assignee: SILICON MOTION, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. The method as claimed in claim 8, wherein the decoder comprises a check-node circuit and a variable-node circuit, and the decoding pipeline comprises a first stage, a second stage, a third stage, and a fourth stage in sequence, and the first stage indicates that a read operation of an input codeword required by a current clock cycle performed by the variable-node circuit to read the input codeword from the variable-node memory through the memory-index control circuit, and the second stage indicates a first calculation stage of one or more input codewords performed by the variable-node circuit, and the third stage indicates a second calculation stage of the one or more input codewords performed by the check-node circuit, and the fourth stage indicates that a write operation of a syndrome calculated by the check-node circuit in the current clock cycle performed by the check-node circuit to write the syndrome to the variable-node memory.