Patent ID: 11862604
Assignee: ADEIA SEMICONDUCTOR INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A chip comprising:
an individual chip having a first surface and a second surface opposite the first surface, wherein the first surface comprises a plurality of interconnects;
a plurality of chiplets bonded to the first surface of the individual chip, each of the plurality of chiplets having a first chiplet surface and a second chiplet surface opposite the first chiplet surface; and
a plurality of plated posts, wherein at least some of the plurality of plated posts are disposed on the first surface of the individual chip and at least some of the plurality of plated posts are disposed on the first surface of one or more of the plurality of chiplets, the plurality of plated posts terminating in a single level across an upper portion of the individual chip,
wherein at least one of the plurality of chiplets are direct bonded to the first surface of the individual chip without an adhesive layer.