Patent ID: 11894326
Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A method, comprising:
providing a microelectronic component comprising:
providing a first substrate having a recess or opening extending from a first surface of the first substrate, at least a portion of the first surface of the first substrate having a planarized topography;
disposing a first conductive material having a first melting point within the recess or opening, extending normal to a plane of the first substrate and forming a first portion of a first interconnect structure of the microelectronic component;
disposing a second conductive material having a second melting point different from the first melting point within the recess or opening, extending normal to the plane of the first substrate and forming a second portion of the first interconnect structure of the microelectronic component, the second portion of the first interconnect structure comprising a plurality of conductive portions at least partially surrounded by the first conductive material; and
bonding a second interconnect structure of a second substrate to the first interconnect structure by at least one of a direct bond of an insulator material to another insulator material without an adhesive or by a metal to metal diffusion bond, thereby forming one of an electrical contact pad or a via with the first interconnect structure and the second interconnect structure.