Patent ID: 11869609
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 8:
9. An apparatus for testing a memory, comprising:
a first-data writing circuit configured to write first data into each of memory cells of a memory array having a plurality of columns;
a second-data writing circuit configured to enable a data mask mode and latching the first data into predetermined memory cells, and write second data only into other memory cells other than the predetermined memory cells;
a leakage circuit configured to enable a leakage mode, and write the first data into a memory cell corresponding to a column under test of the plurality of columns; and
a test circuit configured to disable, after preset leakage time, the leakage mode, and read data from the memory cell corresponding to the column under test for testing;
read data from the memory cells corresponding to columns of the plurality of columns; and
determining whether at least two columns of the plurality of columns include first data; wherein the test circuit is configured to determine, when determining that there are at least two columns simultaneously turned on in the memory array, that a row decoder of the memory is abnormal.