Patent ID: 11955487
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 0:
1. A semiconductor device, comprising:
semiconductor patterns vertically stacked on a substrate;
a gate electrode extended in a first direction to fill a space between the semiconductor patterns;
a source/drain pattern disposed at a side of the gate electrode and connected to the semiconductor patterns;
an interlayer insulating layer covering the gate electrode and the source/drain pattern;
a contact plug including a first portion, which is buried in the source/drain pattern, and a second portion, which penetrates the interlayer insulating layer and is connected to the first portion;
an interface layer between the first portion and the source/drain pattern; and
a metal oxide between the second portion and the interlayer insulating layer,
wherein the interlayer insulating layer covers a portion of a top surface of the first portion.