Patent ID: 11934327
Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
Field: Control (Instruments)
Classification: CPC G  H | IPC G

Claim 15:
16. A method for accelerating computations in a field programmable gate array (FPGA) comprising a configurable interconnect fabric connecting a plurality of logic blocks, the method comprising:
receiving, by a machine learning model training application executed by a computing device comprising a processor, memory, and the FPGA, labeled training data;
supplying, by the machine learning model training application, the labeled training data to the machine learning model to generate input data;
supplying, by the machine learning model training application, the input data to a data masking circuit implemented in the FPGA to generate masked data;
receiving, at the data masking circuit implemented in the logic blocks and configurable interconnect fabric of the FPGA, input data including data values at a plurality of indices of the input data;
selecting, by a masking multiplexer of the data masking circuit, between a data value of the data values and an alternative value to generate the masked data, the masking multiplexer being controlled by a mask value of a plurality of mask values at indices corresponding to the indices of the input data;
outputting the masked data;
computing a plurality of output scores of the machine learning model based on the masked data computed by the machine learning model in response to the labeled training data;
updating the machine learning model based on the output scores; and
outputting the updated machine learning model as a trained machine learning model.