Patent ID: 11962309
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G  Y | IPC H

Claim 8:
9. The phase adjusting circuit of claim 1, wherein the adjustment circuit comprises a first adjustment circuit and a second adjustment circuit; wherein,
the first adjustment circuit is configured to receive a preset fixed value and a first original clock signal, and perform transmission of the first original clock signal based on the preset fixed value to obtain the first clock signal; and
the second adjustment circuit is configured to receive the count value and a second original clock signal, and perform transmission of the second original clock signal based on the count value to obtain the second clock signal;
wherein, in a case that the count value is greater than the preset fixed value, a rising edge of the second clock signal moves in a first direction relative to a rising edge of the first clock signal; or in a case that the count value is less than the preset fixed value, a rising edge of the second clock signal moves in a second direction relative to a rising edge of the first clock signal.