Patent ID: 11947801
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A method comprising:
receiving, by a network interface card (NIC) of a hardware accelerator device, data as part of data transfer from application of remote application server platform;
identifying, by the hardware accelerator device, a destination address of memory of the hardware accelerator device to write the data;
determining that access control bits of the destination address in page tables maintained by a memory management unit (MMU) indicate that memory pages of the destination address are both registered and free;
in response to the access control bits indicating that the memory pages of the destination address are both registered and free, writing the data to the memory pages of the destination address; and
subsequent to writing the data to the memory pages, updating the access control bits for the memory pages of the destination address to indicate that the memory pages are restricted,
wherein setting the access control bits to restricted prevents the NIC and a compute kernel of the hardware accelerator device from accessing the memory pages.