Patent ID: 11875836
Assignee: KEPLER COMPUTING INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. A method to improve memory endurance of the memory via wear leveling, the method comprising:
requesting a write to an address of an individual memory bank, wherein the individual memory bank is part of a plurality of memory banks comprising memory bit cells, wherein an individual memory bit-cell includes a capacitor comprising non-linear polar material, and wherein requesting the write is a reference to the individual memory bank, wherein an individual memory bank of the plurality of memory banks includes N cache lines/words and a gap word, where N is a positive integer;
incrementing a number of references by one upon requesting the write;
comparing the number of references with a threshold;
swapping the gap word with an adjacent cache line or word in response to the number of references is equal to the threshold; and
applying an outlier compensation scheme before or after the wear leveling, wherein an array outside of a memory bank of the plurality of memory banks is queried.