Patent ID: 11862592
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. An integrated chip (IC), comprising:
a semiconductor substrate;
an interconnect structure disposed over the semiconductor substrate;
a first dielectric layer disposed over the interconnect structure, wherein an upper surface of a conductive feature of the interconnect structure is at least partially disposed between opposite sidewalls of the first dielectric layer;
a sidewall spacer disposed along the opposite sidewalls of the first dielectric layer;
a conductive structure disposed over the first dielectric layer, the sidewall spacer, and the upper surface of the conductive feature of the interconnect structure; and
a second dielectric layer disposed between the first dielectric layer and the interconnect structure, wherein a first sidewall of the second dielectric layer and a first sidewall of the sidewall spacer are substantially aligned and define, at least partially, a first common sidewall, wherein a second sidewall of the second dielectric layer and a second sidewall of the sidewall spacer are substantially aligned and define, at least partially, a second common sidewall, wherein the first common sidewall faces the second common sidewall, wherein the first common sidewall and the second common sidewall are laterally spaced a first distance apart along a first plane, wherein the first common sidewall and the second common sidewall are laterally spaced a second distance apart along a second plane, wherein the first plane extends laterally in parallel with the second plane, wherein the first plane is disposed between the second plane and the semiconductor substrate, wherein the second distance is greater than the first distance, and wherein the conductive structure is disposed along the first common sidewall and the second common sidewall.