Patent ID: 11935857
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A method of fabricating an electronic package, the method comprising:
forming first conductive pads formed over a package substrate, wherein the first conductive pads have a first surface area;
forming second conductive pads over the package substrate, wherein the second conductive pads have a second surface area that is greater than the first surface area;
forming a solder resist layer over the first conductive pads and the second conductive pads;
forming a plurality of solder resist openings through the solder resist layer, wherein each of the solder resist openings expose one of the first conductive pads or the second conductive pads, wherein the solder resist openings are filled with conductive material, and wherein a top surface of the conductive material is substantially coplanar with a top surface of the solder resist layer; and
forming solder bumps over the conductive material in the solder resist openings.