Patent ID: 11861051
Assignee: RAMBUS INC.
Field: Digital communication (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 14:
15. A method, comprising:
providing, to an input buffer, a first set of data blocks in a first memory address order, the first set of data blocks arriving at the input buffer in the first memory address order which corresponds to locations in an external memory where the first set of data blocks are stored;
providing, to the input buffer, a second set of data blocks in a second memory address order, the second set of data blocks arriving at the input buffer in the second memory address order which corresponds to locations in the external memory where the second set of data blocks are stored, where the first set of data blocks and the second set of data blocks are to be cryptographically processed, and where cryptographic processing is a one of ciphering and deciphering;
providing, to a cryptographic processing engine, the first set of data blocks in a first randomly selected cryptographic processing order that is a permutation of the first memory address order, the first randomly selected cryptographic processing order based at least in part on randomly selecting blocks from a subset of the first set of data blocks that have already arrived at cryptographic processing device;
cryptographically processing, by the cryptographic processing engine, the first set of data blocks in the first randomly selected cryptographic processing order;
providing, to the cryptographic processing engine, the second set of data blocks in a second randomly selected cryptographic processing order that is a permutation of the second memory address order;
cryptographically processing, by the cryptographic processing engine, the second set of data blocks in the second randomly selected cryptographic processing order;
storing cryptographically processed versions of the first set of data blocks in an output buffer in a third memory address order that is determined by the first randomly selected cryptographic processing order and that is different from the first memory address order; and,
storing cryptographically processed versions of the second set of data blocks in the output buffer in a fourth memory address order that is determined by the second randomly selected cryptographic processing order and that is different from the second memory address order.