Patent ID: 11923325
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 13:
14. A memory chip unit comprising:
a memory structure including a plurality of first conductor layers stacked in a first direction above a substrate, a first semiconductor layer extending in the first direction in the plurality of first conductor layers, and a first charge storage layer provided between the plurality of first conductor layers and the first semiconductor layer;
a first interconnect layer and a second interconnect layer provided above the memory structure so as to be electrically insulated from each other;
a second conductor layer provided on a top surface of a first portion of the first interconnect layer;
a third conductor layer provided on a top surface of a second portion of the first interconnect layer;
a fourth conductor layer provided on a top surface of the first portion of the second interconnect layer; and
a fifth conductor layer provided on a top surface of a second portion of the second interconnect layer, wherein
the second conductor layer, the third conductor layer, the fourth conductor layer, and the fifth conductor layer include aluminum (Al), and
a relative position of the fourth conductor layer with respect to the second conductor layer is matched with a relative position of the fifth conductor layer with respect to the third conductor layer in a plane parallel to the substrate.