Patent ID: 11908915
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 0:
1. A gate structure of a semiconductor device, comprising:
a gate dielectric layer disposed over a channel region;
one or more work function adjustment material layers over the gate dielectric layer; and
a metal gate electrode layer disposed over the one or more work function adjustment material layers,
wherein the one or more work function adjustment material layers include a first layer made of WCN and a second layer made of TiAl or TiAlC
a third layer containing Al and Ti is disposed at at least one of a bottom portion or a top portion of the second layer,
the third layer is a Ti-rich layer having a higher Ti concentration than a center of the second layer, and
a Ti concentration in the third layer increases from a side on the center portion to a surface of the second layer.