Patent ID: 11862241
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 22:
23. The memory system of claim 18, wherein the first hierarchical bit line structure comprises a first local bit line that is selectively connected to the bit line by a first local bit line switch, and a first global bit line that is selectively connected to the first local bit line by a first global bit line switch, the first global bit line configured to selectively receive the first voltage,
wherein the first hierarchical word line structure comprises a first local word line that is selectively connected to the word line by a first local word line switch, and a first global word line that is selectively connected to the first local word line by a first global word line switch, the first global word line configured to selectively receive the second voltage,
wherein the second hierarchical word line structure comprises a second local word line that is selectively connected to the word line by a second local word line switch, and a second global word line that is selectively connected to the second local word line by a second global word line switch, the second global word line configured to selectively receive the first voltage, and
wherein the second hierarchical bit line structure comprises a second local bit line that is selectively connected to the bit line by a second local bit line switch, and a second global bit line that is selectively connected to the second local bit line by a second global bit line switch, the second global bit line configured to selectively receive the second voltage.