Patent ID: 11862259
Assignee: CHINA FLASH CO., LTD. SHANGHAI
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. An over-erase detection and elimination method for memory cells, comprising:
S1: performing an erase operation on memory cells in a storage device;
S2: selecting, from the memory cells, a memory cell to be tested and measuring a threshold voltage of the memory cell to be tested; executing operation S5 if the measured threshold voltage is within a predetermined threshold range; and executing operation S3 if the measured threshold voltage is less than the lower limit of the predetermined threshold range;
S3: performing a soft-write operation on the memory cell to be tested, in order to raise the threshold voltage of the memory cell to be tested; wherein a third positive voltage is applied to the word line of the memory cell to be tested, a fourth positive voltage is applied to the bit line of the memory cell to be tested, and the source of the memory cell to be tested floats, wherein the third positive voltage is less than a programing word line voltage, and the fourth positive voltage is equal to a programing bit line voltage;
S4: measuring again the threshold value of the memory cell to be tested, executing operation S5 if the measured threshold voltage is within the predetermined threshold range; repeating operation S3 if the measured threshold voltage is less than the lower limit of the predetermined threshold range; and
S5: selecting, from the memory cells, a next memory cell and returning to operation S2, and repeating the process until threshold voltages of all the memory cells selected are within the predetermined threshold range;
wherein in operation S2 and operation S4, a first positive voltage is applied to a word line of the memory cell to be tested, a second positive voltage is applied to a bit line of the memory cell to be tested, and a source of the memory cell to be tested is connected to a 0 V voltage;
wherein a negative voltage is applied to word lines of memory cells that are not selected, bit lines of the memory cells that are not selected are connected to a 0 V voltage, and sources of the memory cells that are not selected are connected to a 0 V voltage.