Patent ID: 11886972
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 17:
18. A non-volatile memory (NVM) crossbar, comprising:
a plurality of row signal lines configured to receive input analog voltage signals;
a plurality of multiply-and-accumulate (MAC) column signal lines;
a correction column signal line;
a MAC cell disposed at each intersection of a row signal line and a MAC column signal line; and
a correction cell disposed at each intersection of a row signal line and the correction column signal line,
where each MAC cell includes one or more NVM elements programmed to a conductance level representing one of a plurality of unipolar weights of an ANN, and each correction cell includes one or more NVM elements programmed to a predetermined conductance level,
where each MAC column signal line is configured to generate a MAC signal based on the input analog voltage signals and the respective MAC cells, and the correction column signal line is configured to generate a correction signal based on the input analog voltage signals and the correction cells, and
where each MAC signal is corrected based on the correction signal.