Patent ID: 11869604
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. A method, comprising:
initiating performance of an erase phase involving a memory device;
prior to a power-up of the memory device, storing a particular pattern in a dummy row of the memory device, wherein the dummy row is associated with an address space that is outside an address space of respective memory block of the memory device;
subsequent to the power-up of the memory device, determining whether the particular pattern is written to the dummy row, wherein a determination that the particular pattern is not written to in the dummy row is indicative of an incomplete erase of the memory blocks of the memory device;
responsive to determining that the particular pattern is not written to the dummy row, executing an erase phase involving the memory blocks of the memory device; and
responsive to a completion of the execution of the erase phase on the memory blocks of the memory device, storing, in the dummy row, parameters of the completed erase phase as the parameters of the recently completed erasing operation in the memory blocks of the memory device.