Patent ID: 11901039
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 27:
28. An apparatus comprising:
an interface configured to be coupled to a memory device via an interconnect; and
clock circuitry coupled to the interface and configured to:
generate a first differential write clock signal comprising a first signal having a first phase and a second signal having a second phase that differs from the first phase by approximately 180 degrees;
generate a second differential write clock signal comprising a third signal having a third phase that differs from the first phase by approximately ninety degrees and a fourth signal having a fourth phase that differs from the third phase by approximately 180 degrees; and
transmit, through the interface, the first differential write clock signal and the second differential write clock signal over the interconnect to the memory device.