Patent ID: 11914417
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 2:
3. The memory of claim 1, wherein each storage chip comprises at least one channel; the channel comprises: a plurality of storage banks, wherein each storage bank comprises a plurality of storage units, and the plurality of storage banks are configured to perform read/write operation alternately; a command port, wherein the command port is configured to receive a command signal at a corresponding clock edge, and the command signal is configured to control the read/write operation of the storage banks; and a data port, wherein the data port is configured to receive a data signal to be written into the storage banks or send a data signal at the corresponding clock edge; and the command port comprises a row address port and a column address port, the row address port is configured to receive a row address signal of a position where a target storage unit is located, the column address port is configured to receive a column address signal of the position where the target storage unit is located, and the target storage unit is a storage unit selected from the plurality of storage units.