Patent ID: 11962309
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G  Y | IPC H

Claim 12:
13. The phase adjusting circuit of claim 12, wherein each of the inverting sub-circuits comprises a fifth switch transistor, a sixth switch transistor, a seventh switch transistor, and an eighth switch transistor;
a first terminal of the fifth switch transistor is connected to a power supply signal, a second terminal of the fifth switch transistor is connected to a first terminal of the sixth switch transistor, a second terminal of the seventh switch transistor is connected to a first terminal of the eighth switch transistor, and a second terminal of the eighth switch transistor is connected to a ground signal;
in the first inverting sub-circuit, a control terminal of the sixth switch transistor is connected to the ground signal, and a control terminal of the seventh switch transistor is connected to the power supply signal, so that the first inverting sub-circuit is always in the on state;
in the (i+1)-th inverting sub-circuit, the control terminal of the sixth switch transistor is connected to an i-th control signal, the control terminal of the seventh switch transistor is connected to an inverted signal of the i-th control signal, and a level state of the i-th control signal depends on the i-th bit of the count value or the i-th bit of the preset fixed value, so that whether the (i+1)-th inverting sub-circuit is turned on depends on the i-th bit of the count value or the i-th bit of the preset fixed value; and
a control terminal of the fifth switch transistor and a control terminal of the eighth switch transistor together form an input terminal of the inverting sub-circuit, and a second terminal of the sixth switch transistor and a first terminal of the seventh switch transistor together form an output terminal of the inverting sub-circuit.