Patent ID: 11956342
Assignee: NVIDIA CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 18:
19. The system of claim 18, wherein:
the first device is further to:
transmit a second set of bits associated with the second pattern via the one or more lanes associated with transmitting the clock signal; and

the second device is further to:
receive the second set of bits associated with the second pattern;
determine a second number of pulses associated with the second set of bits over the period;
determine the second number of pulses associated with the second set of bits satisfies the predetermined condition relating to the specified number of pulses for the period; and
refrain from initiating the power-down sequence in response to determining the second number of pulses satisfies the predetermined condition relating to the specified number of pulses for the period.