Patent ID: 11869562
Assignee: KEPLER COMPUTING INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. A method to improve memory endurance of a memory via wear leveling, the method comprising:
requesting a read or write request to an address of a memory organized in a plurality of memory banks, wherein the plurality of memory banks comprises memory bit-cells, wherein the plurality of memory banks includes a first memory bank and a second memory bank, wherein the first memory bank is next to the second memory bank, and wherein an individual memory bit-cell includes a non-volatile material which includes one of: a non-linear polar material, a magnet, or a resistive material; and
applying wear leveling to the first memory bank and the second memory bank in a round-robin fashion to improve memory endurance of the memory, wherein the first memory bank has a first gap word, wherein the first gap word has a first gap pointer, wherein the second memory bank has a second gap word, and wherein the second gap word has a second gap pointer, wherein the method comprising:
swapping the first gap word with an adjacent cache line or word in response to requesting the read or write request.