Patent ID: 11863188
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. The flip-flop circuit of claim 1, further comprising:
a second master latch circuit configured to transmit an inverted signal of a second input signal received from the external device to an eighth node and transmit a fourth inverted signal of the inverted signal at the eighth node to a ninth node, according to the first control signal having the first logic level or the second control signal having the second logic level;
a second slave latch circuit configured to transmit a fifth inverted signal of the fourth inverted signal to a tenth node according to the first control signal having the second logic level or the second control signal having the first logic level;
a second output inverter configured to generate a second output signal by inverting the fifth inverted signal of the tenth node; and
a second control signal generation circuit configured to generate the second control signal based on the clock signal and the fourth inverted signal of the ninth node.