Patent ID: 11966676
Assignee: FERMI RESEARCH ALLIANCE, LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A soft error-mitigating semiconductor design system comprising:
a synthesis subsystem configured to:
receive a circuit design specification comprising at least one sequential element definition, and
determine, using the at least one sequential element definition, a triple modular redundancy (TMR) configuration comprising three redundant sequential element definitions; and

a physical design subsystem configured to:
determine, using the TMR configuration, a clock skew insertion definition and a spatial separation definition, and
generate a layout characterized by the TMR configuration, by the clock skew insertion definition, and by the spatial separation definition;
wherein the clock skew insertion definition comprises one of:
a single global clock signal configured to drive each of three delay logic elements each comprising a respective distinct offset, and
three clock signals each configured to drive a respective one of three delay logic elements each comprising a respective asynchronous offset.