Patent ID: 11955195
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H  B | IPC G

Claim 15:
16. A semiconductor memory device, comprising:
a substrate that includes a memory cell region and a test region;
an active pattern on the memory cell region;
a source/drain pattern on the active pattern;
a dummy pattern on the test region;
a device isolation layer on the substrate, a lower sidewall of each of the active pattern and the dummy pattern, wherein an upper portion of each of the active pattern and the dummy pattern protrudes upwardly from the device isolation layer;
a first gate electrode on the active pattern and extending in a first direction, wherein the first gate electrode and the source/drain pattern are adjacent to each other in a second direction that intersects the first direction;
a first common contact coupled to the source/drain pattern and the first gate electrode, wherein the first common contact electrically connects the source/drain pattern and the first gate electrode to each other;
a second gate electrode that extends in the first direction on the dummy pattern;
a second common contact in contact with the dummy pattern and the second gate electrode;
a gate spacer on a sidewall of each of the first and second gate electrodes;
a gate capping pattern on a top surface of each of the first and second gate electrodes;
an interlayer dielectric layer on the gate capping pattern; and
a first wiring layer, a second wiring layer, and a third wiring layer that are sequentially stacked on the interlayer dielectric layer,
wherein the first common contact comprises:
an active contact that penetrates the interlayer dielectric layer and electrically connects with the source/drain pattern; and
a first gate contact that penetrates the gate capping pattern and electrically connects with the first gate electrode,

wherein the second common contact comprises:
a first contact pattern that penetrates the interlayer dielectric layer and contacts the dummy pattern; and

a second gate contact that penetrates the gate capping pattern and electrically connects with the second gate electrode,
wherein the first gate contact comprises:
a first body part coupled to the first gate electrode; and
a first protrusion part that extends from the first body part and into the active pattern,

wherein the second gate contact comprises:
a second body part coupled to the second gate electrode; and
a second protrusion part that extends from the second body part and into the first contact pattern,

wherein the first wiring layer includes a first test line electrically connected to the second common contact, the first test line extending in the second direction, and
wherein a lowermost level of a top surface of the active pattern is lower than a lowermost level of a top surface of the dummy pattern.