Patent ID: 11925017
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A semiconductor device, comprising:
a substrate, comprising an isolation structure and an active area defined by the isolation structure, wherein the substrate has a memory region and a periphery region;
a memory cell, disposed on the memory region of the substrate;
a wall structure, disposed on the periphery region of the substrate, wherein the wall structure comprises a plurality of stacks arranged along both a first direction and a second direction perpendicular to the first direction, wherein the stacks are extended continuously along the first direction and segmented in the second direction;
a first conductive layer, wherein the first conductive layer is disposed between segmented portions of the stacks of the wall structure along the second direction, and each of the stacks comprises at least one first dielectric layer and at least one second conductive layer; and
a second dielectric layer, wherein the second dielectric layer is continuously disposed on top surfaces of the segmented portions of the stacks and under a bottom surface of the first conductive layer.