Patent ID: 11914473
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 31:
32. The method of claim 31, wherein receiving the plurality of protocol units comprises receiving a plurality of first sets of parity bits associated with the plurality of protocol units, and wherein determining the error further comprises:
generating a plurality of second sets of parity bits associated with the plurality of protocol units, wherein each protocol unit has a respective set of second parity bits;
comparing respective parity bits from the plurality of first sets of parity bits with respective parity bits from the plurality of second sets of parity bits; and
determining that one or more parity bits from the plurality of first sets of parity bits do not match corresponding parity bits from the plurality of second sets of parity bits, wherein determining the error associated with the one or more protocol units of the plurality of protocol units is based at least in part on determining that the one or more parity bits from the plurality of first sets of parity bits do not match the corresponding parity bits from the plurality of second sets of parity bits.