Patent ID: 11972135
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory system comprising:
a plurality of dice having a plurality of planes; and
a processing device coupled to the plurality of dice, the processing device to perform controller operations comprising:
receiving a status indicator signal comprising at least a first pulse that is asserted by a first plane and a second pulse that is asserted by a second plane of the plurality of dice, wherein the first pulse and the second pulse partially overlap to comprise an extended pulse that is longer than either of the first pulse or the second pulse;
initiating a polling delay period in response to detecting assertion of the extended pulse, wherein the polling delay period is greater than a pulse width of either of the first or second pulses; and
performing a first status check of dice operations being performed by the plurality of dice in response to detecting expiration of the polling delay period.