Patent ID: 11908747
Assignee: TOKYO ELECTRON LIMITED
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 12:
13. A method of processing a substrate, the method comprising:
forming a first stack of layers on a substrate, the first stack of layers including metal layers and dielectric layers that alternate in the first stack of layers, and a capping layer formed over the first stack of layers;
forming openings in the first stack of layers and depositing a first semiconductor layer in the openings uncovered in the first stack of layers such that the first semiconductor layer rests over the substrate, wherein the openings in the first stack of layers include a first opening and a second opening, and wherein the first opening and the second opening has a base that is formed by a substrate layer;
forming a second stack of layers within the openings over the first semiconductor layer by epitaxial growth, the second stack of layers including second semiconductor layers and epitaxial layers that alternate in the second stack of layers and are aligned with respective layers of the first stack of layers;
forming transistor channels from the epitaxial layers of the second stack of layers in a same plane as the metal layers from the first stack of layers such that the transistor channels extend between the metal layers and the epitaxial layers within the openings;
forming a second stack of layers within each of the first opening and the second opening; and
depositing another capping layer over each of the second stack of layers formed within the first opening and the second opening; and
depositing a second mask layer over the another capping layer of the second stack of layers, such that the second mask layer extends over the another capping layer to overlap a portion of the capping layer, wherein a width of the second mask layer is equal to a second predetermined distance.