Patent ID: 11973042
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A semiconductor package having a top and a bottom, comprising:
a semiconductor chip disposed within the semiconductor package between the top of the semiconductor package and the bottom of the semiconductor package, wherein the semiconductor chip has a top surface on which at least one connection pad disposed, and a bottom surface opposing to the top surface;
a plurality of wiring layers disposed adjacently to the semiconductor chip;
a first conductive bump disposed on the at least one connection pad of the semiconductor chip;
a second conductive bump disposed on an uppermost wiring layer among the plurality of wiring layers;
an adhesive layer disposed on the bottom surface of the semiconductor chip;
an insulating post disposed on the adhesive layer, and extending towards the top of the semiconductor package and the bottom of the semiconductor package;
an encapsulant disposed on side surfaces of the first and second conductive bumps, the insulating post, and the semiconductor chip; and
a redistribution structure including a redistribution layer electrically connected to the first and second conductive bumps,
wherein the insulating post and the semiconductor chip are directly in contact with the adhesive layer.