Patent ID: 11881456
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 17:
18. A semiconductor package, comprising:
a package substrate;
an interposer substrate disposed on the package substrate;
first semiconductor chip structures and at least one second semiconductor chip structure spaced apart from each other on the interposer substrate;
a molding member covering at least a side surface of each of the first semiconductor chip structures and the at least one second semiconductor chip structures on the interposer substrate; and
a capping structure disposed on the first and second semiconductor chip structures and the molding member,
wherein the capping structure includes a first capping portion disposed on upper surfaces of the first and second semiconductor chip structures on the interposer substrate, a second capping portion extending from an edge region of the first capping portion in a direction toward the interposer substrate, and a third capping portion extending horizontally from the second capping portion across an upper surface of the molding member, an upper surface of the third capping portion is at a level lower than an upper surface of the second capping portion,
wherein a distance from a lower surface of the package substrate to an upper surface of the package substrate is greater than a distance from an upper surface of the package substrate to upper surfaces of the first and second semiconductor chip structures.