Patent ID: 11930645
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Measurement (Instruments)
Classification: CPC H  G | IPC G  H

Claim 8:
9. A semiconductor structure, comprising:
a substrate;
a transistor region, comprising a gate over the substrate, and a first doped region and a second doped region at least partially in the substrate;
a MTJ region over the transistor region, the MTJ region comprises:
two first metal vias over the gate and the first doped region, respectively; and
a magnetic tunneling junction (MTJ) structure over the second doped region, the first metal vias are leveled with the MTJ structure; and

a metal interconnect over the MTJ region, the metal interconnect comprises:
a plurality of second metal vias in contact with an upper surface of each first metal via and an upper surface of the MTJ structure, respectively.