Patent ID: 11914515
Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A data cache method, applied in a cache memory device, comprising:
outputting, by a reservation station of the cache memory device, a load instruction to a memory order buffer (MOB) circuit of the cache memory device;
generating, by a first address generation circuit (AGC) of the MOB circuit, a virtual address based on the load instruction from the reservation station;
obtaining, by a compression circuit of the MOB circuit, a higher part of the virtual address from the first AGC and generating, by the compression circuit, a target hash value based on the higher part of the virtual address;
generating, by a second AGC of the MOB circuit, a lower part of the virtual address based on the load instruction;
obtaining, by a virtual tag array of the MOB circuit, the lower part of the virtual address from the second AGC and selecting, by the virtual tag array, a set of memory units from the virtual tag array;
comparing, by a comparator circuit of the MOB circuit, the target hash value to a hash value stored by each memory unit of the set of memory units to generate a virtual tag hit signal or a virtual tag miss signal; and
when the comparator circuit generates the virtual tag miss signal, transmitting, by the MOB circuit, the virtual tag miss signal to the reservation station.