Patent ID: 11954047
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 5:
6. The apparatus of claim 1, wherein the at least one persistent range register comprises at least one first persistent range register for a first persistent range of memory and at least one second persistent range register for a second persistent range of memory, and the address modifying circuit is to:
when the address is within the first persistent range of memory, remove a first persistent base address indicated by at least one persistent base address register from the address to generate a first offset into the persistent range, and append the unique identifier value to the first offset to generate the modified address; and
when the address is within the second persistent range of memory, remove a second, different persistent base address indicated by the at least one persistent base address register from the address to generate a second offset into the persistent range, and append the unique identifier value to the second offset to generate the modified address.