Patent ID: 11960733
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory controller, comprising:
a plurality of control cores configured to control a plurality of memory devices, respectively;
a host core configured to allocate write requests received from a host to each of the plurality of control cores based on predefined criteria; and
a shared memory configured to be accessed by the host core and the plurality of control cores,
wherein the host core is further configured to store, in the shared memory in response to occurrence of a sudden power-off, dump information including information about logical addresses corresponding to the write requests, and
wherein a first control core is further configured to store, in a memory device controlled by the first control core, the dump information of a second control core associated with the first control core in response to occurrence of the sudden power-off, the first and second control cores being among the plurality of control cores.