Patent ID: 11907033
Assignee: LATTICE SEMICONDUCTOR CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 8:
9. A programmable logic device (PLD) comprising the adaptive POR signal generator of claim 1, wherein:
the PLD comprises a PLD fabric, a programmable input/output (I/O) interface configured to interface with a user device and/or a semiconductor device separate from the PLD over an external bus coupled to the PLD, and/or a configuration engine configured to manage configurations of and/or communications amongst the configuration engine, the PLD fabric and/or the programmable I/O interface;
the PLD is configured to receive the supply voltage provided over a power bus coupled between the PLD and the power supply;
the adaptive POR signal generator is integrated with the PLD and is configured to receive the supply voltage provided over the power bus to the PLD and to provide the generated POR signal to, and release one or more reset states of, the PLD fabric, the programmable I/O interface, and/or the configuration engine of the PLD.