Patent ID: 11968822
Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 4:
5. The memory device using a semiconductor element according to claim 1, wherein
the first impurity layer is connected to a first bit line,
the first gate conductor layer is connected to a first plate line,
the second gate conductor layer is connected to a first word line,
the second impurity layer is connected to a first source line,
the third gate conductor layer is connected to a second word line,
the fourth gate conductor layer is connected to a second plate line,
the third impurity layer is connected to a second bit line, and
in plan view, the first word line and the second word line extend in a first direction, and the first bit line and the second bit line extend in a second direction perpendicular to the first direction.