Patent ID: 11923331
Assignee: nan
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. An integrated chip (IC), comprising:
a substrate including a plurality of metal pads on a top surface of the substrate;
a die disposed over the substrate, the die including a first side over the top surface of the substrate and a second side over the first side;
a housing structure disposed over the second side of the die and surrounding sidewalls of the die;
a plurality of die stopper bumps arranged as a plurality of groups of die stopper bumps, wherein each group of the plurality of groups of die stopper bumps is disposed between the first side of the die and a first corresponding metal pad of the plurality of metal pads, and at least one group of the plurality of groups of die stopper bumps comprises at least two rows of die stopper bumps directly contacting corresponding metal pad of the plurality of metal pads;
a first plurality of adhesive structures, wherein each of the first plurality of adhesive structures is disposed on and surrounds a corresponding group of the plurality of groups of die stopper bumps;
a plurality of housing stopper bumps disposed between a bottommost surface of the housing structure and the substrate, wherein the plurality of housing stopper bumps is arranged as a plurality of groups of housing stopper bumps; and
a second plurality of adhesive structures, wherein each of the plurality of housing stopper bumps is disposed on and surrounds a corresponding group of the plurality of groups of housing stopper bumps.