Patent ID: 11886354
Assignee: APPLE INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A non-transitory computer readable storage medium having stored thereon design information that specifies a design of at least a portion of a hardware integrated circuit in a format recognized by a semiconductor fabrication system that is configured to use the design information to produce the circuit according to the design, wherein the design information specifies that the circuit includes:
first cache circuitry at a first level in a cache hierarchy;
second cache circuitry at a second, different level in the cache hierarchy;
one or more processors configured to execute program instructions that cause access to the first cache circuitry and the second cache circuitry;
cache controller circuitry configured to:
over a first set of processor cycles, insert data into the first cache circuitry according to a first cache insertion policy;
evaluate respective values of a performance metric for the first cache circuitry and for the second cache circuitry; and
in response to detecting that the value of the performance metric for the first cache circuitry does not meet a first threshold and that the value of the performance metric for the second cache circuitry meets a second threshold, determine to replace the first cache insertion policy with a second cache insertion policy over a second set of processor cycles, wherein the second threshold is greater than the first threshold.