Patent ID: 11862234
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 18:
19. A memory system comprising:
a memory device; and
a memory controller configured to store first to fourth codes in the memory device by performing a training operation, the first code including information of a first reference voltage level associated with a first data line, the second code including information of a first decision feedback equalization (DFE) level associated with the first data line, the third code including information of a second reference voltage level associated with a second data line, and the fourth code including information of a second DFE level associated with the second data line;
wherein the memory device comprises:
a first data line driver circuit configured to generate a first upper reference voltage and a first lower reference voltage based on the first code and the second code; and
a second data line driver circuit configured to generate a second upper reference voltage and a second lower reference voltage based on the third code and the fourth code.