Patent ID: 11971741
Assignee: QUALCOMM INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 14:
15. The system of claim 14, wherein:
the circular shifter register is configured to store bits, each of the bits corresponding to a respective one of the N consecutive idle periods, and to output one of the bits at a time at the output of the circular shift register;
the control circuit is configured to:
receive the mode indicator signal via the input of the control circuit;
if the mode indicator signal has the first logic value, instruct the multiplexer to select the first input; and
if the mode indicator signal has the second logic value, instruct the multiplexer to select the second input via the first output, and instruct the circular shift register to shift the bits in the circular shift register via the second output.