Patent ID: 11869610
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. The storage device according to claim 14, wherein the first control unit comprises:
a ninth transistor, configured with a source to be electrically connected to the first voltage, and a drain to be electrically connected to the first positive data wire;
a tenth transistor, configured with a drain to be electrically connected to both the drain of the ninth transistor and the first positive data wire, and a source to be electrically connected to the second voltage;
a first NOR gate, configured with an output end to be electrically connected to a gate of the ninth transistor, and a first input end to be electrically connected to the output end of the second inverter;
a second NOR gate, configured with an output end to be electrically connected to a gate of the tenth transistor, and a second input end to be electrically connected to the second data wire;
a first NAND gate, configured with an output end to be electrically connected to a first input end of the second NOR gate, a first input end to be electrically connected to the writing enable signal, and a second input end to be electrically connected to the equalizing signal; and
a first AND gate, configured with an output end to be electrically connected to a second input end of the first NOR gate, a first input end to be electrically connected to the writing enable signal, and a second input end to be electrically connected to the second data wire.