Patent ID: 11935624
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 7:
8. A method comprising:
depositing a multi-layer stack over a semiconductor substrate, the multi-layer stack comprising alternating layers of a first material and a second material;
patterning the multi-layer stack such that the multi-layer stack comprises a staircase structure in a cross-sectional view;
forming an inter-metal dielectric (IMD) over the staircase structure of the multi-layer stack;
forming a plurality of word lines in the multi-layer stack;
depositing a memory film in the multi-layer stack adjacent the plurality of word lines;
depositing an oxide semiconductor (OS) layer over the memory film;
etching the IMD to form a first opening exposing a first word line of the plurality of word lines and a second opening exposing a second word line of the plurality of word lines, wherein the first opening extends to a first depth, and wherein the second opening extends to a second depth different from the first depth;
forming a first conductive contact in the first opening and electrically coupled to the first word line and a second conductive contact in the second opening and electrically coupled to the second word line; and
forming a first conductive line over the IMD, the first conductive contact, and the second conductive contact, wherein the first conductive line electrically couples the first conductive contact to the second conductive contact.