Patent ID: 11948891
Assignee: NEPES CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor package, comprising:
a redistributed layer comprising an insulating layer and a wiring pattern, wherein the insulating layer is not formed on a top surface and side surfaces of the uppermost wiring pattern among the wiring pattern;
a plurality of semiconductor chips disposed on both upper and lower portions of the redistributed layer; and
a mold provided to cover the plurality of semiconductor chips on the upper portion of the redistributed layer,
wherein the redistributed layer is composed of multiple layers including a plurality of insulating layers and a plurality of wiring patterns, and
wherein in the wiring pattern, the thickness of the uppermost wiring pattern or the lowermost wiring pattern is thicker than that of the wiring pattern located between the uppermost wiring pattern and the lowermost wiring pattern such that it is possible to omit an insulating layer covering the uppermost wiring pattern or a UBM under the redistributed layer.