Patent ID: 11869928
Assignee: KEPLER COMPUTING INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A device comprising:
a first region comprising:
a first conductive interconnect within a first dielectric in a first level;
a second level above the first level, the second level comprising:
an electrode structure on the first conductive interconnect, the electrode structure comprising:
a first conductive hydrogen barrier layer; and
a first conductive fill material on the first conductive hydrogen barrier layer, wherein the electrode structure comprises a first lateral thickness;

an etch stop layer comprising an insulator, the etch stop layer laterally surrounding the electrode structure;
a memory device comprising a ferroelectric material or a paraelectric material on least a portion of the electrode structure, the memory device further comprising a second lateral thickness, wherein the second lateral thickness is less than the first lateral thickness;
a second dielectric spanning the first region and on the etch stop layer, the second dielectric comprising an amorphous, greater than 90% film density hydrogen barrier material, wherein the memory device is directly adjacent to and embedded within the second dielectric; and
a via electrode on at least a portion of the memory device, the via electrode comprising:
a second conductive hydrogen barrier layer comprising a lateral portion in contact with the memory device;
substantially vertical portions directly adjacent to the second dielectric; and
a second conductive fill material adjacent to the second conductive hydrogen barrier layer; and

a second region adjacent to the first region, the second region comprising:
a second conductive interconnect within the first level, wherein the second level further comprising:
a third conductive interconnect;
a via structure coupled between the second conductive interconnect and the third conductive interconnect; and
a third dielectric on the etch stop layer, the third dielectric directly adjacent to the second dielectric, wherein the third dielectric comprises a less than 90% film density material, and wherein the third dielectric laterally surrounds a portion of the via structure.