Patent ID: 11923456
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC B  H | IPC H

Claim 10:
11. A semiconductor device comprising:
channels at a plurality of levels, respectively, the channels spaced apart from each other in a vertical direction on an upper surface of a substrate;
a gate structure on the substrate, the gate structure at least partially surrounding a surface of each of the channels and extending in a first direction substantially parallel to the upper surface of the substrate, and the gate structure including an interface pattern, a gate insulation pattern, a workfunction control pattern, and a gate electrode sequentially stacked from a surface of each of the channels;
a source/drain layer at each of opposite sides of the gate structure in a second direction substantially parallel to the upper surface of the substrate and crossing the first direction, the source/drain layer being connected to sidewalls of the channels;
a first spacer on each of opposite sidewalls of an upper portion of the gate structure in the second direction, the upper portion of the gate structure being on an upper surface of an uppermost one of the channels and overlapping the channels in the vertical direction; and
a second spacer on each of opposite sidewalls of a lower portion of the gate structure in the second direction, the lower portion of the gate structure being between the channels and between the substrate and a lowermost one of the channels, and overlapping the channels in the vertical direction,
wherein an air gap is formed between the second spacer and a sidewall of the source/drain layer and overlapping the workfunction control pattern having a side surface concave theretoward in the second direction.