Patent ID: 11930679
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 10:
11. A preparation method for the array substrate according to claim 1, comprising:
forming patterns of the gate, the active layer, and the source-drain electrode of the thin film transistor in a sub-pixel region of the substrate;
forming a pattern of the passivation layer on the thin film transistor;
forming a pattern of the color resist in the monochromatic light-emitting regions on the passivation layer;
forming a pattern of the planarization layer on the color resist and the passivation layer; and
forming a pattern of the anode on the planarization layer; wherein the anode is electrically connected to the drain electrode in the source-drain electrode through the first through hole penetrating through the passivation layer and the planarization layer; wherein
the forming the thin film transistor further comprises: forming a pattern of the dielectric layers between the source-drain electrode and the substrate, wherein the pattern of at least one of the dielectric layers formed through a half-tone mask and a once patterning process is formed in a mode that: the thickness of the at least one of the dielectric layers between the first through hole and the substrate is greater than the thickness of the at least one of the dielectric layers between the color resist and the substrate.