Patent ID: 11874759
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. An integrated circuit comprising:
an address and data bus;
memory circuitry coupled to the address and data bus, the memory circuitry configured to contain processor instructions;
processor circuitry coupled to the address and data bus, the processor circuitry configured to execute the processor instructions in processor cycles, in which a processor cycle corresponds to one cycle of a processor instruction pipeline execution;
trigger detection circuitry coupled to the address and data bus, the trigger detection circuitry having a trigger event register that includes a trigger bit;
event trace module circuitry coupled to the processor circuitry, coupled to the address and data bus, and coupled to the trigger detection circuitry, wherein the event trace module circuitry is configured to:
provide an indication of a first event based on the trigger detection circuitry;
provide a time stamp associated with the first event; and
determine whether to provide a count of cycles between the first event and a second event based on the trigger bit of the trigger detection circuitry; and

a control bus coupled to the memory circuitry, to the event trace module circuitry, to the trigger detection circuitry, and to the processor circuitry.