Patent ID: 11923318
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC B  H | IPC B  H

Claim 15:
16. A method of manufacturing a semiconductor package, comprising:
forming a backside redistribution structure, wherein the backside redistribution structure comprises a first dielectric layer, and a redistribution metal layer over the first dielectric layer and comprising a dummy pattern;
providing a semiconductor device over the backside redistribution structure, wherein an active surface of the semiconductor device faces away from the backside redistribution structure, the semiconductor device is electrically insulated from the dummy pattern and overlapped with the dummy pattern from a top view of the semiconductor package;
forming a front side redistribution structure over the semiconductor device, wherein the front side redistribution structure is electrically connected to the semiconductor device; and
performing a patterning process on the first dielectric layer to form a marking pattern opening exposing a part of the dummy pattern.