Patent ID: 11921581
Assignee: MICRON TECHNOLOGY, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 8:
9. An apparatus, comprising:
a memory configured to:
store a hard bit, a first soft bit, and a second soft bit associated with a raw read of a translation unit (TU); and
store a third soft bit based on a redundant array of independent NAND (RAIN) drop corresponding to the TU and the raw read of the TU; and

control circuitry coupled to the memory and configured to direct:
performance of the raw read of the TU;
performance of an exclusive OR (XOR) operation on the RAIN drop and the raw read of the TU to generate the third soft bit; and
execution of an error handling flow in response to a read error of the TU, wherein execution of the error handling flow comprises:
performance of a number of read retries on the TU;
in response to the number of read retries being unsuccessful, performing the XOR operation on the RAIN drop and the raw read of the TU to generate the third soft bit; and
decode a low-density parity-check (LDPC) codeword comprising the hard bit and the first, second, and third soft bits.