Patent ID: 11948897
Assignee: PSEMI CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. A circuit fabricated on a high resistivity silicon-on-insulator (SOI) substrate as part of an integrated circuit susceptible to accumulated charge, the circuit including:
(a) at least one field effect transistor (FET) having a drain, a source, a gate, a VDS characteristic, a VGS characteristic, and a signal path through the FET between the drain and the source; and
(b) a switch coupled to the signal path of the FET, configured to selectively couple the signal path to a first current source or to a second current source, the second current source providing a lower current than the first current source; and
(c) at least one substrate contact near at least one FET, each substrate contact comprising a resistive conduction path formed between a first contact region at a surface of a layer of the integrated circuit and a second contact region at or near a surface of the high resistivity SOI substrate, wherein each substrate contact penetrates through at least one dielectric layer;
wherein, in an active mode, the switch couples the signal path of the FET to the first current source; and
wherein, in a standby mode, the switch couples the signal path of the FET to the second current source, such that both the VGS characteristic and the VDS characteristic of the FET are close to respective active mode operational voltages for the VGS characteristic and the VDS characteristic, thereby reducing changes in accumulated charge.