Patent ID: 11876052
Assignee: SK HYNIX INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 17:
18. A semiconductor die bonding structure, comprising:
a lower die including a lower top bonding dielectric layer and lower connection structures;
an upper die stacked over the lower die and including an upper bottom bonding dielectric layer and upper connection structures,
wherein:
the lower top bonding dielectric layer and the upper bottom bonding dielectric layer are directly bonded to each other,
each of the lower connection structures and each of the upper connection structures are aligned in a vertical direction, to be directly bonded,
the lower connection structures and the upper connection structures are arranged side by side in a first horizontal direction, respectively;
an upper surface of each of the lower connection structures has a first width in the first horizontal direction and a second width in a second horizontal direction,
a lower surface of each of the upper connection structures has a third width in the first horizontal direction and a fourth width in the second horizontal direction,
the first horizontal direction, the second horizontal direction, and the vertical direction are substantially mutually perpendicular; and
the second width is greater than the first width and the fourth width.