Patent ID: 11967357
Assignee: NATIONAL TSING HUA UNIVERSITY
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 2:
3. The memory unit with time domain edge delay accumulation for computing-in-memory applications of claim 2, further comprising:
a global bit line connected to the at least one edge-delay cell multiplexor; and
a global bit line bar connected to the at least one edge-delay cell multiplexor;
wherein the at least one edge-delay cell multiplexor comprises:
a first edge-delay cell multiplex transistor configured to connect the global bit line to the local bit line for read and write operations according to the second word line; and
a second edge-delay cell multiplex transistor configured to connect the global bit line bar to the local bit line bar for the read and write operations according to the second word line.