Patent ID: 11956663
Assignee: INTEL CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 1:
2. The MLD of claim 1, wherein the processing circuitry is further configured to:
generate a third TIM comprising a third bitmap comprising a third indication that no traffic is to be sent by the first AP device of the MLD to the first non-AP device of the second MLD during a second beacon interval occurring after a second beacon using the first communication link;
generate a fourth TIM comprising a fourth bitmap comprising a fourth indication that traffic is to be sent by the second AP device of the MLD to the second non-AP device of the second MLD during the second beacon interval using the second communication link;
cause to send, using the first AP device of the MLD and the first communication link, the second beacon, the second beacon comprising the first TIM and the second TIM; and
cause to send, using the first AP device of the MLD and the first communication link, a data frame to the first non-AP device of the second MLD during the second beacon interval.