Patent ID: 11935894
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 10:
11. An integrated circuit device, comprising:
a first instance of a device at a first location having a first cell layout; and
a second instance of the device at a second location having a second cell layout;
wherein the cell layouts includes a device layer, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer,
wherein a ratio in the cell layouts of a metal line pitch in the second metal interconnection layer to a polysilicon line pitch in the device layer is less than 1, and
wherein the first and second cell layouts differ in a relative location of at least one metal line in the second metal interconnection layer with respect to a common feature in the cell layouts,
wherein the cell layouts conform with the equation M0_Enc≤(Max_M0_Length−Max_M1_Pitch_Length−VIA0 Width)/2, where:
Max_M0_Length represents a maximum possible length of a line in the first metal interconnection layer in the cell layouts;
Max_M1_Pitch_Length represents a maximum possible pitch between two lines in the second metal interconnection layer in the cell layouts;
VIA0_Width represents a width of a via that connects a line in the first metal interconnection layer with a line in the second metal interconnection layer; and
M0_Enc represents a distance from an outermost edge of the line in the first metal interconnection layer to an edge of a nearest possible via connecting the line in the first metal interconnection layer to the line in the second metal interconnection layer.