Patent ID: 11934701
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 2:
3. The method as claimed in claim 1, wherein the first count value indicates a number of memory cells corresponding to a low area count of the first read voltage, from among a plurality of memory cells of the memory region,
wherein the second count value indicates a number of memory cells corresponding to a high area count of the first read voltage, from among the plurality of memory cells of the memory region,
wherein the third count value indicates a number of memory cells corresponding to a low area count of the second read voltage, from among the plurality of memory cells of the memory region, and
wherein the fourth count value indicates a number of memory cells corresponding to a high area count of the second read voltage, from among the plurality of memory cells of the memory region.