Patent ID: 11916125
Assignee: nan
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 8:
9. A method, comprising:
receiving a substrate comprising:
a bottom layer,
a middle layer over the bottom layer,
a top layer over the middle layer, and
a sacrificial layer over the top layer;

forming a stack over the substrate, the stack comprising a plurality of first semiconductor layers interleaved by a plurality of second semiconductor layers;
patterning the stack and a portion of the substrate to form a fin-shaped structure comprising a drain region, a source region, and a channel region disposed between the drain region and the source region;
forming an isolation feature around the fin-shaped structure;
forming a dummy gate stack over the channel region;
recessing the drain region and the source region to form a drain trench and a source trench, respectively, such that the drain trench and the source trench do not extend into the sacrificial layer;
selectively extending the source trench through the sacrificial layer to form an extended source trench;
selectively and partially recessing sidewalls of the plurality of second semiconductor layers to form inner spacer recesses;
forming inner spacer feature in the inner spacer recesses;
after the forming of the inner spacer features, replacing the sacrificial layer with a bottom dielectric layer; and
after the replacing, forming a drain feature in the drain trench and a source feature in the extended source trench,
wherein the middle layer comprises silicon germanium.