Patent ID: 11868281
Assignee: META PLATFORMS TECHNOLOGIES, LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 16:
17. The integrated circuit of claim 9, wherein the network is configured to:
connect the first port to the second bank through the first switch and the second switch so that access latency from the first port to the second bank is higher than access latency from the first port to the first bank;
connect the second port to the first bank through the second switch and the first switch so that access latency from the second port to the first bank is higher than access latency from the second port the second bank;
receive, from the first port, a request to access memory in the second bank of memory; and
enable the first port to access memory in the second bank by routing the request through the first switch and the second switch, and performing arbitration to avoid contention with other requests to access the second bank.