Patent ID: 11971447
Assignee: NXP USA, INC.
Field: Measurement (Instruments)
Classification: CPC G | IPC G

Claim 5:
6. An integrated circuit comprising:
logic circuitry configured to perform a function within the integrated circuit;
a clock source configured to provide a clock signal to the logic circuitry, wherein the clock signal is specified to operate at an operating frequency; and
a clock monitor unit configured to monitor the clock signal, wherein the clock monitor unit is further configured to:
perform, in a functional operating mode, a first comparison of an operating frequency of the clock signal to a high frequency threshold value;
perform, in the functional operating mode, a second comparison of the operating frequency of the clock signal to a low frequency threshold value;
selectively assert or deassert, in the functional operating mode, a first event signal based on the first comparison;
selectively assert or deassert, in the functional operating mode, a second event signal based on the second comparison;
perform, in a fault injection operating mode, a third comparison of the operating frequency of the clock signal to the low frequency threshold value,
perform, in the fault injection operating mode, a fourth comparison of the operating frequency of the clock signal to the high frequency threshold value;
selectively assert or deassert, in the fault injection operating mode, the first event signal based on the third comparison;
selectively assert or deassert, in the fault injection operating mode, a second event signal based on the fourth comparison; and
generate, in the fault injection operating mode, at least one signal indicating successful or failed detection of a fault based on the first event signal and the second event signal.