Patent ID: 11963468
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An integrated chip, comprising:
a first conductive structure disposed on a first interconnect within a dielectric structure on a substrate;
a diffusion barrier on the first conductive structure;
a data storage structure on the diffusion barrier;
a second conductive structure on the data storage structure;
a dielectric spacer disposed along sidewalls and an upper surface of the second conductive structure;
an insulating layer disposed along sidewalls and an upper surface of the dielectric spacer, the insulating layer vertically extending from below a bottom of the dielectric spacer to over a top of the dielectric spacer;
a second interconnect extending through the dielectric spacer and the insulating layer to contact the second conductive structure;
a first access device comprising a first gate structure disposed on the substrate between a first source region and a common drain; and
a second access device comprising a second gate structure disposed on the substrate between a second source region and the common drain, wherein the first interconnect is electrically coupled to the common drain.