Patent ID: 11864386
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 8:
9. A memory structure, comprising:
a plurality of memory cells stacked elevationally over a base, each of the memory cells comprising;
a transistor comprising first and second source/drain regions having a horizontally-oriented channel region there-between and a gate operatively proximate the channel region; and
a capacitor comprising first and second capacitor electrodes having a capacitor insulator there-between, the first electrode being electrically coupled to the first source/drain region;
a conductive structure extending elevationally over the base, all of the gates comprised by the plurality of memory cells being directly electrically coupled to the conductive structure; and
a vertically extending electrode structure that electrically couples second electrodes of multiple memory cells within the memory structure.