Patent ID: 11869625
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. The data transmission circuit of claim 8, wherein the write enable module comprises:
a first inverter having an input end electrically connected to the initial write enable signal, and an output end for outputting a first write enable inverted signal;
a first NOR gate having an input end electrically connected to the data polarity identification signal and the output end of the first inverter, and an output end for outputting the write enable signal;
a second inverter having an input end electrically connected to the data polarity identification signal, and an output end for outputting a data polarity identification inverted signal; and
a second NOR gate having an input end electrically connected to the output end of the second inverter and the output end of the first inverter, and an output end for outputting a write enable inverted signal.