Patent ID: 11861284
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A method of designing an integrated circuit, the method comprising:
generating a placement comprising a plurality of Manhattan edges and a plurality of diagonal edges by decomposing a minimum spanning tree having non-Manhattan, non-45 degree, and non-135-degree edges;
determining, by the processing device, a tree for each respective net in the integrated circuit based on the placement;
determining, by the processing device, a number of conductor layers to be used for Manhattan routing of conductors, the determining comprising calculating a first ratio for Manhattan edges in the trees;
determining, by the processing device, a number of conductor layers to be used for diagonal routing of conductors, the determining comprising calculating a second ratio for diagonal edges in the trees;
selecting, by the processing device, a conductor scheme for the integrated circuit based on the first and the second ratios; and
producing a layout of the integrated circuit.