Patent ID: 11923340
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. The semiconductor package according to claim 1, wherein:
the first semiconductor chip comprises a first lower connecting pad and a first connecting bump disposed on a bottom surface of the first semiconductor chip, and a first upper connecting pad disposed on an upper surface of the first semiconductor chip;
the second semiconductor chip comprises a second lower connecting pad and a second connecting bump disposed on a bottom surface of the second semiconductor chip; and
the inner mold layer is interposed between the first base chip and the first semiconductor chip while contacting the first lower connecting pad and the first connecting bump, and is interposed between the first semiconductor chip and the second semiconductor chip while contacting the first upper connecting pad, the second lower connecting pad and the second connecting bump.