Patent ID: 11962309
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G  Y | IPC H

Claim 15:
16. The phase adjusting circuit of claim 7, wherein each of the first switch transistor and the third switch transistor is a P-channel field effect transistor, and each of the second switch transistor and the fourth switch transistor is an N-channel field effect transistor; and
wherein a control terminal of the P-channel field effect transistor is a gate electrode, a first terminal of the P-channel field effect transistor is a source electrode, a second terminal of the P-channel field effect transistor is a drain electrode, a control terminal of the N-channel field effect transistor is a gate electrode, a first terminal of the N-channel field effect transistor is a drain electrode, and a second terminal of the N-channel field effect transistor is a source electrode.