Patent ID: 11917809
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. An apparatus comprising:
a set of first memory cells of a memory die, the set of first memory cells associated with a first level above a substrate of the memory die;
a set of second memory cells of the memory die, the set of second memory cells associated with the first level;
a set of third memory cells of the memory die, the set of third memory cells associated with a second level above the substrate of the memory die;
a set of fourth memory cells of the memory die, the set of fourth memory cells associated with the second level;
a plurality of first access lines, each first access line of the plurality of first access lines coupled with a respective subset of the set of first memory cells and operable to couple with circuitry of a third level via a respective first transistor of a plurality of first transistors of the first level;
a plurality of second access lines, each second access line of the plurality of second access lines coupled with a respective subset of the set of second memory cells and operable to couple with the circuitry of the third level via a respective second transistor of a plurality of second transistors of the first level;
a plurality of third access lines, each third access line of the plurality of third access lines coupled with a respective subset of the set of third memory cells and operable to couple with the circuitry of the third level via a respective third transistor of a plurality of third transistors of the second level; and
a plurality of fourth access lines, each fourth access line of the plurality of fourth access lines coupled with a respective subset of the set of fourth memory cells and operable to couple with the circuitry of the third level via a respective fourth transistor of a plurality of fourth transistors of the second level.