Patent ID: 11899583
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A device comprising:
a multi-layered logic structure with multiple layers including a first layer and a second layer arranged vertically in a stacked configuration, wherein:
the first layer includes core processing logic and a first cache memory with first interconnect logic and a first router, wherein the core processing logic includes L1 cache memory disposed in the first layer,
the second layer includes a second cache memory with second interconnect logic and a second router,
the second interconnect logic in the second layer is linked to the first interconnect logic in the first layer with a first data link, and
the second router in the second layer is linked to the first router in the first layer with a second data link that is different than the first data link.