Patent ID: 11935608
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 14:
15. A semiconductor memory, comprising a signal generation circuit, wherein the signal generation circuit comprises:
a clock module, configured to generate a clock signal based on a flag signal;
a control module, configured to generate a control signal according to number of transitions of the clock signal within a fixed time; and
a generation module, respectively connected to the clock module and the control module, and configured to receive the clock signal, the control signal, and the flag signal, and to generate a target signal;
wherein
when the flag signal changes from a first level to a second level, the target signal changes from a third level to a fourth level;
after being maintained at the fourth level for a target duration, the target signal changes from the fourth level to the third level; and
the generation module is further configured to determine the target duration according to the clock signal and the control signal.