Patent ID: 11887672
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A nonvolatile memory device comprising:
a peripheral circuit formed on a semiconductor substrate;
a memory cell array formed on the peripheral circuit and including a plurality of cell strings; and
a metal layer formed on the memory cell array, wherein:
the metal layer includes:
a plurality of bit lines connected with the plurality of cell strings;

a common source line connected with the plurality of cell strings; and
at least one dummy bit line provided between the plurality of bit lines and the common source line, and

the peripheral circuit includes:
a control logic circuit configured to generate at least one dummy bit line driving signal in response to a command from an external device; and
a dummy bit line driver configured to selectively provide a first voltage to the at least one dummy bit line in response to the at least one dummy bit line driving signal, wherein the dummy bit line driver includes:
a first switch connected between the at least one dummy bit line and a first terminal receiving the first voltage and configured to operate in response to a first dummy bit line driving signal of the at least one dummy bit line driving signal; and
a second switch connected between the at least one dummy bit line and the common source line and configured to operate in response to a second dummy bit line driving signal of the at least one dummy bit line driving signal.