Patent ID: 11868880
Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 6:
7. A computing system, comprising:
a processor; and
a computer-readable storage medium having instructions stored thereupon which, when executed by the processor, cause the processor to:
determine an interconnect topology for transmitting data between a plurality of graphical processing units (GPUs), the interconnect topology comprising an inter-GPU point-to-point topology and a shared interconnect topology;
pack a quantity of directed spanning trees corresponding to the interconnect topology for transmitting the data between the plurality of GPUs, wherein the directed spanning trees comprise data defining communication links between the GPUs and an amount of the data to be transmitted on the communication links, and wherein the quantity of directed spanning trees is selected to minimize the number of directed spanning trees and to maximize utilization of bandwidth available on the communication links; and
generate program code which, when executed, will cause the data to be transmitted between the GPUs based on the directed spanning trees, the program code configured to select a chunk size for chunks of the data to be transferred between the plurality of GPUs by testing throughput between the plurality of GPUs at a range of chunk sizes following a multiplicative increase, additive decrease scheme across iterations, and to pipeline transmission of the chunks of the data between the GPUs.