Patent ID: 11967532
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 14:
15. A method, comprising:
forming a semiconductor structure that includes a dummy gate stack disposed over a fin that protrudes from a substrate;
forming a first gate spacer layer over the dummy gate stack;
forming a second gate spacer layer over the first gate spacer layer;
etching the first gate spacer layer and the second gate spacer layer to form a gate spacer along a sidewall of the dummy gate stack, the gate spacer comprising the etched first gate spacer layer and the etched second gate spacer layer;
forming a source/drain (S/D) feature in the fin adjacent to the gate spacer;
after the forming of the source/drain (S/D) feature, selectively removing the etched second gate spacer layer; and
after the selectively removing of the etched second gate spacer layer, replacing the dummy gate stack with a metal gate stack.