Patent ID: 11916011
Assignee: MACRONIX INTERNATIONAL CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 5:
6. The vertical memory structure of claim 5, wherein the plurality of series in the array are arranged in a plurality of distinct subarrays of the array, each distinct subarray including at least one series in the plurality of series, and further including:
a plurality of conductive strips disposed in a pillar select layer over the stack, including for each distinct subarray of the array, a corresponding conductive strip of the plurality of conductive strips, and including for each distinct subarray of the array a plurality of vertical channel structures through the corresponding conductive strip contacting respective conductive pillars in the distinct subarrays; and
a plurality of bit line conductors disposed over the pillar select layer over the stack, each bit line conductor having contacts to one vertical channel transistor in a plurality of vertical channel transistors in each of the distinct subarrays.