Patent ID: 11922868
Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A display panel, wherein the display panel comprises a pixel driving circuit comprising N pixel driving units cascaded, and a pixel driving unit of an nth stage is any one of the N pixel driving units, and the pixel driving unit of the nth stage comprises:
a light-emitting module comprising a light-emitting device for emitting light;
a switch module connected to the light-emitting module, wherein the switch module is connected to a first control signal of the nth stage and a data signal, and the switch module is configured to transmit the data signal to the light-emitting module under control of the first control signal of the nth stage;
a detection module connected to the light-emitting module, wherein the detection module is connected to a second control signal of the nth stage, and the detection module is configured to detect a monitoring voltage of a first node in the light-emitting module and generate a compensation voltage of the light-emitting module according to a preset voltage; and
a reset module connected to the light-emitting module, wherein the reset module is connected to a reset signal of the nth stage, and the reset signal of the nth stage is connected to an output terminal that outputs a control signal of an mth stage prior to the nth stage, and the reset module is configured to reset a potential of the first node to a threshold potential, wherein N, n, and m are positive integers, n and m are both less than or equal to N,
wherein at least two of the N pixel driving units are electrically connected to a same data signal line,
wherein the switch module comprises a storage capacitor and a first thin film transistor;
wherein a first terminal of the storage capacitor is electrically connected to a second node, and a second terminal of the storage capacitor is electrically connected to the first node; and
wherein a gate of the first thin film transistor is electrically connected to the first control signal of the nth stage, a source of the first thin film transistor is electrically connected to the data signal, and a drain of the first thin film transistor is electrically connected to the second node.