Patent ID: 11940918
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC A  G  Y | IPC G

Claim 12:
13. A circuit device comprising:
a processor core;
a level-one (L1) cache controller coupled to the processor core and configured to provide a first transaction;
a level-two (L2) cache controller coupled to the processor core; and
an L2 cache memory coupled to the L2 cache controller, wherein the L2 cache controller includes:
a scheduler circuit coupled to the L1 cache controller;
a pipeline coupled to the scheduler circuit and to the L2 cache memory;
a bypass path coupled to the scheduler circuit in parallel with the pipeline, wherein the scheduler circuit is configured to:
receive the first transaction;
determine whether the first transaction is associated with a write of data to the L2 cache memory; and
based on the first transaction not being associated with the write to the L2 cache memory, determine when to provide the first transaction to the bypass path based on whether a second transaction is in the pipeline.