Patent ID: 11914253
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 14:
15. The manufacturing method according to claim 10, wherein the forming a gate insulation layer, an active layer, a source electrode, a drain electrode and a data line, forming a conductive channel between the source electrode and the drain electrode by means of one patterning process comprises:
depositing a gate insulation film, a semiconductor film and a second metal film on the base on which the pixel electrode, the gate line and the gate electrode are formed;
coating a layer of photoresist on the second metal film, gradient exposing and developing the photoresist using a halftone mask or a gray tone mask, forming an unexposed region at a location where the source electrode, the drain electrode and the data line to be formed are located, the unexposed region being with a photoresist having a first thickness, forming a partially exposed region at a location where the conductive channel to be formed is located, the partially exposed region being with a photoresist having a second thickness, forming a fully exposed region at other locations without a photoresist, and the first thickness is greater than the second thickness;
etching away the second metal film and the semiconductor film in the fully exposed region by means of a first etching process;
removing the photoresist in the partially exposed region by means of an ashing process, exposing the second metal film;
etching away the second metal film in the partially exposed region by means of a second etching process, removing a remaining portion of the photoresist, forming the gate insulation layer, the active layer, the source electrode, the drain electrode and the data line, forming a conductive channel between the source electrode and the drain electrode.