Patent ID: 11869577
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 11:
12. The method of claim 10, further comprising:
applying the second voltage to a set of pillars coupled with the first pillar column line comprising the first pillar based at least in part on activating one or more additional pillar row lines via the second pillar decoder while the first pillar column line is activated, wherein each activated pillar row line is separated by at least one inactivated pillar row line; and
concurrently accessing, based at least in part on applying the second voltage to the set of pillars, a first plurality of memory cells comprising the first memory cell, each memory cell of the first plurality of memory cells coupled between respective pillars of the set of pillars and respective word lines of the plurality of first word lines.