Patent ID: 11961545
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 14:
15. A memory device, comprising:
a first transistor and a second transistor over a substrate and each having a first source/drain region and a second source/drain region;
an interconnect structure over and electrically coupled to the first and second transistors and further comprising a plurality of wires and a plurality of vias that are alternatingly stacked; and
a first memory cell and a second memory cell over the first and second transistors, in the interconnect structure, and each having a first electrode and a second electrode;
wherein the interconnect structure electrically shorts the first electrodes of the first and second memory cells and the first source/drain regions of the first and second transistors together.