Patent ID: 11900112
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A processor comprising:
an instruction fetch unit configured to receive a vector reverse instruction that specifies a single vector reverse operation; and
a datapath coupled to the instruction fetch unit that includes:
a global register file that includes a source register including a set of n lanes configured to store a first vector that includes a set of n elements, in which a first element of the set of n elements is stored in a first lane of the set of n lanes and each succeeding element of the set of n elements is stored in a respective succeeding lane of the set of n lanes, and a destination register including a set of n lanes respectively corresponding to the set of n lanes of the source register, wherein n is an integer of 4 or greater; and
a set of functional units coupled to the global register file that includes a first functional unit, wherein:
the vector reverse instruction specifies the first functional unit from among the set of functional units; and
the first functional unit is configured to, based on the vector reverse instruction:
receive the first vector from the source register;
reverse an order of the set of n elements of the first vector to produce a second vector; and
cause the second vector to be stored in the destination register, in which a first element of the second vector is stored in the nth lane of the destination register and each of succeeding element of the second vector is stored in a respective preceding lane of the destination register,

wherein the vector reverse instruction is completed in a single operation.