Patent ID: 11892501
Assignee: CADENCE DESIGN SYSTEMS, INC.
Field: Measurement (Instruments)
Classification: CPC G | IPC G

Claim 18:
19. The method of claim 18, wherein the sim-shifting of the subset of the N-cycle at-speed test patterns comprises:
fault-simulating a scan-in shift interval of a respective N-cycle at-speed test pattern of the subset of the N-cycle at-speed test patterns to identify a set of values prior to a fault initialization cycle of the respective N-cycle at-speed test pattern; and
employing the set of values prior to the fault initialization cycle during the scan-in shift interval of the respective N-cycle at-speed test pattern as extra fault initialization cycles for a corresponding N+P cycle at-speed test pattern, where P is a positive integer to diagnose a respective transition fault and/or defect of the second set of transition faults and/or defects.