Patent ID: 11967621
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of manufacturing a semiconductor structure comprising:
forming an active region having a first portion which is doped;
forming a first silicide layer over and electrically coupled to the first portion of the active region;
forming a second silicide layer under and electrically coupled to the first portion of the active region;
forming a first metal-to-drain/source (MD) contact structure over and electrically coupled to the first silicide layer;
forming a first via-to-MD (VD) structure over and electrically coupled to the MD contact structure; and
forming a buried via-to-source/drain (BVD) structure under and electrically coupled to the second silicide layer.