Patent ID: 11948981
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A method comprising:
forming a first gate spacer and a second gate spacer over a semiconductor region; and
forming a gate stack over the semiconductor region and between the first gate spacer and the second gate spacer, the forming the gate stack comprising:
forming a conductive layer; and
filling a silicon-containing layer into the conductive layer, wherein in a top view of the conductive layer, the silicon-containing layer is separated by the conductive layer into a first portion and a second portion, wherein the silicon-containing layer extends to a middle line between the first gate spacer and the second gate spacer, and wherein the silicon-containing layer has a higher silicon concentration than the conductive layer.