Patent ID: 11935601
Assignee: SUPERMEM, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A memory system, comprising:
a sense amplifier; and
a memory array comprising:
a word line;
a first bit line corresponding to the sense amplifier;
a second bit line corresponding to the sense amplifier;
a first memory bitcell at the word line and the first bit line; and
a second memory bitcell at the word line and the second bit line, wherein the memory system is configured to:
access the word line;
while accessing the word line:
access the first bit line;
sample and hold a first developed voltage associated with a state of the first memory bitcell;
access the second bit line; and
sample and hold a second developed voltage associated with a state of the second memory bitcell;

provide, to the sense amplifier, the held first developed voltage;
generate a reference voltage;
sense, with the sense amplifier, the held first developed voltage, wherein:
the second bit line is accessed while the held first developed voltage is sensed, and
sensing the held first developed voltage comprises amplifying a difference between the held first developed voltage and the reference voltage;

provide, to the sense amplifier, the held second developed voltage; and
sense, with the sense amplifier, the held second developed voltage, wherein sensing the held second developed voltage comprises amplifying a difference between the held second developed voltage and the reference voltage.