Patent ID: 11973017
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 5:
6. A semiconductor package, comprising:
a multilayer package substrate, comprising:
a core layer;
a top patterned metal layer on a top side of the core layer and a bottom patterned metal layer on a bottom side of the core layer;
a plurality of dielectric layers including a top dielectric layer on the top patterned metal layer and a bottom dielectric layer on the bottom patterned metal layer;
wherein at least one of the top dielectric layer and the bottom dielectric layer comprise a porous dielectric layer including a plurality of pores and having an average porosity of at least 5% averaged over its thickness, and
an integrated circuit (IC) die comprising a substrate including a top side semiconductor surface including circuitry having a plurality of bond pads electrically connected to nodes in the circuitry,
wherein the IC die is mounted on the multilayer package substrate or is embedded therein, and
wherein the plurality of bond pads are electrically connected to the multilayer package substrate.