Patent ID: 11874792
Assignee: GOWIN SEMICONDUCTOR CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. An apparatus for network communication containing a host, a bus, and a programmable device able to perform user configurable logic functions, comprising:
a host computer capable of facilitating high-speed (“HS”) network data transmission;
a bus coupled to the host computer for providing HS serial data transmission; and
a programmable logic device (“PLD”) coupled to the bus and configured to have,
a drive block configured to establish a handshaking process between the host computer and the PLD via the bus for HS data transmissions;
an IO serdes block (“ISB”) coupled to the drive block and configured to facilitate serdes operation at HS data rate without employing clock synchronizing circuitry, the ISB including a first input deserializer configured to obtain first two samples of data signals on a P-channel in accordance with a first clock having a clock cycle running twice speed as data rate at the P-channel, the ISB including a second input deserializer configured to obtain second two samples of data signals on an N-channel in accordance with a second clock with a ninety (90) degree phase shift of the first clock wherein the second clock has a clock cycle running twice speed as data rate at the N-channel.