Patent ID: 11923331
Assignee: nan
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An integrated chip (IC), comprising:
a substrate;
a first die disposed over the substrate;
a metal wire attached to a frontside of the first die;
a first plurality of die stopper bumps disposed along a backside of the first die, wherein:
the first plurality of die stopper bumps directly contacts the backside of the first die; and
the first plurality of die stopper bumps is arranged as a plurality of groups of die stopper bumps;

a plurality of adhesive structures, wherein each of the plurality of adhesive structures surrounds a corresponding group of the plurality of groups of die stopper bumps and provides adhesion between the first die and the substrate;
a housing structure disposed over the first die and surrounding sidewalls of the first die;
a plurality of housing stopper bumps directly contacting and disposed between the housing structure and the substrate; and
a cavity arranged directly between the housing structure and an uppermost surface of the first die and separating the housing structure from the uppermost surface of the first die;
wherein the plurality of housing stopper bumps and the first plurality of die stopper bumps comprise a same material.