Patent ID: 11929324
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 16:
17. A semiconductor device, comprising:
a substrate including a device isolation region and an active region;
a buffer pattern on the device isolation region;
a bit line structure on the buffer pattern;
a contact structure on the active region, the contact structure including a first portion, a second portion that is on the first portion, and a third portion that is on the second portion;
a spacer structure between the bit line structure and the contact structure, the spacer structure including a first spacer, a second spacer that is on the first spacer, and a third spacer that is on the second spacer; and
a capacitor bottom electrode on the contact structure,
wherein the first portion of the contact structure is in contact with a side surface of the device isolation region and a top surface of the active region,
wherein the first spacer of the spacer structure is in contact with a top surface of the buffer pattern,
wherein a top surface of the third spacer of the spacer structure is lower than a top surface of each of the first spacer and the second spacer of the spacer structure, and
wherein a bottom surface of each of the second spacer and the third spacer of the spacer structure is lower than a top surface of the device isolation region.