Patent ID: 11901035
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 4:
5. The system of claim 3, wherein:
the banks of the HBM are arranged in corresponding groups;
the first set of one or more of the memory cells is contained within at least a first block of one or more of the groups;
the second set of one or more of the memory cells is contained within at least a second block of one or more of the groups;
in terms of membership, the first and second blocks are non-overlapping of each other; and
the DDVFS device is further configured to perform the following:
adjusting the first clock or the first PS voltage of the first block resulting in a first group-wide adjustment of temperatures amongst the memory cells of the groups of the first block; and
adjusting the second clock or the second PS voltage of the second block resulting in second group-wide adjustment of temperatures amongst the memory cells of the groups of the second block.