Patent ID: 11901956
Assignee: nan
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 0:
1. A computing system that comprises one or more hybrid computing modules that further comprise at least one high peak bandwidth I/O channel embedded within a multilayer surface interface, wherein,
the high peak bandwidth I/O link additionally comprises vias that form an electrical interface with input and output ports on semiconductor die, the semiconductor carrier, or an interposer circuit embedded within a stacked assembly of semiconductor chips;
the multilayer surface interface comprises conducting means that forms a channel link within a data signal plane that electrically interfaces signal transmission between the vias, low permittivity/ultra-low loss dielectric, additional conductive means to form power planes and ground planes, and
the multilayer surface interface further comprises a passive network filtering circuit comprising capacitive, inductive, and resistive elements embedded within the high peak bandwidth I/O channel,, wherein,
the passive network filtering circuit further comprises high energy density electroceramic dielectric components that polarize and depolarize with femto-second response times.