Patent ID: 11953990
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A memory system comprising:
a controller, during a write operation, adding a parity to data which is received from a host, performing an ldpc encoding operation by adding an ldpc parity to a first data set which includes the parity, and performing a syndrome check operation on a second data set, which includes the parity and the ldpc parity; and
a memory device storing the second data set, which is output from the controller,
wherein, during a read operation, the controller receives the second data set from the memory device, performs an error correction operation on the second data set, and outputs the data to the host,
wherein, during the write operation, the controller:
performs an ecc encoding operation and adds an ecc parity to organize a data set;
temporarily stores an ecc encoded data in a buffer;
decodes the data set including the ecc parity to organize the first data set;
performs the ldpc encoding operation to the first data set to organize the second data set; and
performs the syndrome check operation on the second data set and transfers the second data set to the memory device.