Patent ID: 11908892
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 17:
18. A method comprising:
forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers over a substrate;
forming a dielectric wall on a first longitudinal side of the fin structure but not on a second longitudinal side of the fin structure;
recessing a portion of the fin structure after forming the dielectric wall;
forming an epitaxial source/drain structure on the recessed portion of the fin structure, the epitaxial source/drain structure contacting a side surface of the dielectric wall;
performing a first etching process that etches the second semiconductor layers at a faster etch rate than etching the first semiconductor layers;
after performing the first etching process, performing a second etching process to remove the dielectric wall; and
after removing the dielectric wall, forming a gate structure over the first semiconductor layers and the second semiconductor layers.