Patent ID: 11955481
Assignee: STMICROELECTRONICS (CROLLES 2) SAS
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A microelectronic device including a PNP transistor and NPN transistor, comprising:
a semiconductor substrate;
a P+ doped region in the semiconductor substrate;
a collector region for the PNP transistor arranged on the P+ doped region in the semiconductor substrate;
an N+ doped well in the semiconductor substrate;
a collector region for the NPN transistor arranged on the N+ doped well in the semiconductor substrate;
a first epitaxial semiconductor layer;
wherein said P+ doped region for the PNP transistor extends at least partly into the first epitaxial semiconductor layer; and
a second epitaxial semiconductor layer arranged on the first epitaxial semiconductor layer;
wherein the N+ doped well for the NPN transistor extends through the first epitaxial semiconductor layer and at least partly into the second epitaxial semiconductor layer; and
wherein a portion of the P+ doped region for the PNP transistor is located farther from an upper device surface of the microelectronic device than any portion of the N+ doped well for the NPN transistor.