Patent ID: 11954589
Assignee: STMICROELECTRONICS S.R.L.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 14:
15. A refractory circuit configured to inhibit operation of an integrator circuit after delivery of an output signal, the refractory circuit comprising:
a first transistor comprising a first n-channel MOS transistor having a drain coupled to a supply node, a source coupled to a common node, and a gate coupled to an output node at which the output signal is delivered;
a second transistor comprising a second n-channel MOS transistor having a drain coupled to an input node, a source coupled to a reference node at which a reference voltage is received, and a gate coupled to the common node; and
a resistive-capacitive circuit coupled between the supply node and the reference node and having a tap coupled to the common node, wherein a duration of inhabitation of the integrator circuit by the refractory circuit is dependent upon a time constant of the resistive-capacitive circuit.