Patent ID: 11869574
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 11:
12. The semiconductor memory device of claim 5, wherein the phase skew adjusting circuit comprises first, second, third, and fourth phase skew adjusters, and wherein, after the duty training interval:
the first phase skew adjuster is configured to provide the first adjusted clock signal by adjusting a phase skew of the first divided clock signal based on the second control code set stored in the register set;
the second phase skew adjuster is configured to provide the third adjusted clock signal by adjusting a phase skew of the third divided clock signal based on the second control code set stored in the register set;
the third phase skew adjuster is configured to provide the second adjusted clock signal by adjusting a phase skew of the second divided clock signal based on the third control code set stored in the register set; and
the fourth phase skew adjuster is configured to provide the fourth adjusted clock signal by adjusting a phase skew of the fourth divided clock signal based on the third control code set stored in the register set.