Patent ID: 11879941
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Measurement (Instruments)
Classification: CPC G | IPC G

Claim 0:
1. A test architecture within an integrated circuit comprising:
serial-to-parallel circuitry including a serial input for receiving stimulus data and a command, and parallel outputs;
parallel scan paths including serial scan inputs coupled to the parallel outputs for receiving the stimulus data and serial scan outputs for outputting response data;
parallel-to-serial circuitry including parallel inputs coupled to the serial scan outputs for receiving the response data, and a serial output; and
a controller coupled to at least one output of the parallel outputs for receiving the command, wherein the controller includes:
a scan clock input;
a test enable input;
a state machine operable in accordance with the command; and
a clock control circuitry coupled to the scan clock input, coupled to the test enable input, and including a clock output CK2 coupled to the parallel scan paths,
wherein the clock control circuitry is configurable to control the clock output CK2 for performing a capture operation by the parallel scan paths.