Patent ID: 11908705
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. A method for aligning interconnects comprising:
trimming and forming a frame of strips of interconnects, wherein the frame of strips of interconnects comprises interdigitated pins;
removing siderails from the frame of strips of interconnects to provide an array of strips of interconnects, including cutting a first edge and a second edge of the strips of interconnects in the frame of strips of interconnects;
aligning a first set of strips of interconnects in the array of strips of interconnects such that pins of the first set of strips of interconnects are aligned with pins of a second set of strips of interconnects in the array of strips of interconnects, wherein a strip of interconnects of the first set of strips of interconnects are adjacent to a strip of interconnects of the second set of strips of interconnects to provide an aligned array of strips of interconnects,
moving a given strip of interconnects of the first set of strips of interconnects from an initial position along a first axis;
measuring an offset of pins on the given strip of interconnects of the first set of strips of interconnects relative to pins of the second set of strips of interconnects;
moving the first set of strips of interconnects along a second axis by the measured offset, wherein the second axis is perpendicular to the first axis;
returning the first set of strips of interconnects to the initial position; and
singulating the aligned array of strips of interconnects to provide interconnects for dies of integrated circuit (IC) chips.