Patent ID: 11909748
Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An anti-fraud control system in an onboard network under a time-triggered communication protocol based on time slots, the on-hoard network being connected, for each of branches, to one or more electronic control devices each transmitting and receiving a frame within a predetermined time slot, the anti-fraud control system comprising:
error monitoring devices each for a corresponding one of the branches, wherein
a first error monitoring device among the error monitoring devices includes:
a first frame transmitting and receiving hardware unit that receives the frame flowing on the on-board network; and
a first hardware error detector that monitors whether an error occurs in the frame received by the first frame transmitting and receiving hardware unit, and causes the first frame transmitting and receiving hardware unit to transmit an error notification frame when detecting an occurrence of an error in the frame received by the first frame transmitting and receiving hardware unit, the error notification frame containing information identifying a type of the frame subjected to the error and for notifying of the occurrence of the error in the frame, and

each of one or more second error monitoring devices different from the first error monitoring device among the error monitoring devices includes:
a second frame transmitting and receiving hardware unit that receives the error notification frame; and
a second hardware error detector that regards, as a frame to be invalidated, the frame subjected to the error and included in the error notification frame received, and shifts the second error monitoring device to an invalidation mode for invalidating reception of subsequent frames, when no error is detected in the corresponding one of the branches with respect to the frame.