Patent ID: 11955095
Assignee: LAPIS TECHNOLOGY CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. The output circuit according to claim 7,
wherein the second current source is connected between the back gate of the first NMOS transistor switch and a negative power supply voltage terminal that receives a negative power supply voltage,
wherein the second back gate control switch is connected between the back gate of the first NMOS transistor switch and a reference power supply voltage terminal that receives the reference power supply voltage, and
wherein
the first NMOS transistor is configured such that a drain is connected to one of the source and the drain of the first NMOS transistor switch, a gate is connected to the other of the source and the drain of the first NMOS transistor switch, and a source is connected to the back gate of the first NMOS transistor switch, and
the second NMOS transistor is configured such that a drain is connected to the other of the source and the drain of the first NMOS transistor switch, a source is connected to the one of the source and the drain of the first NMOS transistor switch, and a source is connected to the back gate of the first PMOS transistor switch.