Patent ID: 11901292
Assignee: nan
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A memory device, comprising:
a stack structure comprising conductive structures vertically interleaved with insulative structures;
strings of memory cells vertically extending through the stack structure;
a source structure vertically underlying the stack structure and coupled to the strings of memory cells;
conductive plug structures vertically overlying and in electrical communication with the strings of memory cells, at least one of the conductive plug structures comprising:
a first portion having a substantially uniform horizontal width across a vertical height thereof; and
a second portion underlying and unitary with the first portion and having variable horizontal widths across a vertical height thereof, the second portion comprising:
a largest horizontal width at a vertical position most proximate to the first portion; and
a smallest horizontal width at an additional vertical position most proximate to the strings of memory cells; and

digit line structures vertically overlying and in electrical communication with the conductive plug structures.