Patent ID: 11869826
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. A memory module comprising:
a substrate having a surface, the surface having a central portion, a first array area on one side of the central portion and a second array area on an opposite side of the central portion, wherein the first array area is cooler than the second array area during operation;
a first semiconductor die attached to the substrate in the first array area on the surface such that the first semiconductor die is located upstream of the central portion with respect to an airflow across the surface, wherein the first semiconductor die has a first degree of susceptibility to temperature, wherein the first degree of susceptibility to temperature is based on a change in an operating parameter at different temperatures; and
a second semiconductor die attached to the substrate in the second array area such that the second semiconductor die is located downstream of the central portion with respect to the airflow across the surface, wherein the second semiconductor die has a second degree of susceptibility to temperature, wherein the second degree of susceptibility to temperature is based on a change in the operating parameter at different temperatures, wherein the second degree is smaller than the first degree such that the second semiconductor die operates more effectively than the first semiconductor die at a temperature of the second array area during operation, and wherein the first and second semiconductor dies are the same type of dies.