Patent ID: 11955179
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 5:
6. The semiconductor memory device according to claim 1, further comprising:
a second memory pillar extending in the third direction from the substrate surface, the second memory pillar including
a plurality of fifth memory cell transistors electrically connected in series with each other and having a ninth end and a tenth end,
a ninth selection transistor electrically connected to the ninth end,
a tenth selection transistor electrically connected to the tenth end,
a plurality of sixth memory cell transistors electrically connected in series with each other, the sixth memory cell transistors having an eleventh end and a twelfth end, and the sixth memory cell transistors being electrically insulated from the fifth memory cell transistors,
an eleventh selection transistor electrically connecting the ninth selection transistor and the eleventh end,
a twelfth selection transistor electrically connecting the tenth selection transistor and the twelfth end,
a plurality of seventh memory cell transistors electrically connected in series with each other and the seventh memory cell transistors having a thirteenth end and a fourteenth end,
a thirteenth selection transistor electrically connecting the tenth selection transistor, the twelfth selection transistor, and the thirteenth end,
a fourteenth selection transistor electrically connected to the fourteenth end,
a plurality of eighth memory cell transistors electrically connected in series with each other, the eighth memory cell transistors having a fifteenth end and a sixteenth end, and the eighth memory cell transistors being electrically insulated from the seventh memory cell transistors,
a fifteenth selection transistor electrically connecting the tenth selection transistor, the twelfth selection transistor, the thirteenth selection transistor and the fifteenth end, and
a sixteenth selection transistor electrically connecting the eighth selection transistor and the sixteenth end;

a ninth select gate line provided above the first word lines to extend in parallel to the substrate surface, the ninth select gate line facing a third side of the second memory pillar, and the ninth select gate line being electrically connected to a gate of the tenth selection transistor;
a tenth select gate line provided above the second word lines to extend in parallel to the substrate surface, the tenth select gate line facing a fourth side of the second memory pillar, and the tenth select gate line being electrically connected to a gate of the twelfth selection transistor;
an eleventh select gate line provided above the third word lines to extend in parallel to the substrate surface, the eleventh select gate line facing the third side of the second memory pillar, and the eleventh select gate line being electrically connected to a gate of the fourteenth selection transistor; and
a twelfth select gate line provided above the fourth word lines to extend in parallel to the substrate surface, the twelfth select gate line facing the fourth side of the second memory pillar, and the twelfth select gate line being electrically connected to a gate of the sixteenth selection transistor,
wherein the first word lines are electrically connected to the gates of the fifth memory cell transistors and the gates of the seventh memory cell transistors, respectively,
wherein the second word lines are electrically connected to the gates of the sixth memory cell transistors and the gates of the eighth memory cell transistors, respectively,
wherein the first select gate line is further electrically connected to the gate of the ninth selection transistor,
wherein the third select gate line is further electrically connected to the gate of the eleventh selection transistor,
wherein the fifth select gate line is further electrically connected to the gate of the thirteenth selection transistor, and
wherein the seventh select gate line is further electrically connected to the gate of the fifteenth selection transistor.