Patent ID: 11869825
Assignee: QORVO US, INC.
Field: nan (nan)
Classification: CPC nan | IPC H

Claim 13:
14. The method of claim 11 wherein forming the device wafer comprises:
providing a Si—SiGe—Si wafer that includes a common silicon epitaxial layer, a common interfacial layer over the common silicon epitaxial layer, and the silicon handle substrate over the common interfacial layer, wherein:
the common interfacial layer comprises SiGe; and
the common interfacial layer has the plurality of interfacial layers that are connected to each other;

performing a CMOS process to provide a precursor wafer that includes a plurality of device regions, wherein:
the isolation sections extend through the common silicon epitaxial layer and extend into the common interfacial layer, such that the common silicon epitaxial layer separates into a plurality of individual silicon epitaxial layers and the plurality of interfacial layers remains connected to each other;
each active layer of the plurality of device regions is formed from a corresponding individual silicon epitaxial layer; and
each of the plurality of interfacial layers directly resides over a top surface of a corresponding active layer, and the silicon handle substrate remains directly over the common interfacial layer; and

forming the plurality of first bump structures at the bottom surface of each BEOL portion to complete the plurality of device dies from the plurality of device regions.