Patent ID: 11914887
Assignee: MACRONIX INTERNATIONAL CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A data accessing method, for applying to a memory circuit which stores a plurality of first bits in a first page, a plurality of second bits in a second page and a plurality of third bits in a third page, wherein the memory circuit includes a plurality of multi-level cells, each of the multi-level cells is of a same type and configured to store a same number of bits of data which include at least a corresponding first bit of the plurality of first bits in the first page, a corresponding second bit of the plurality of second bits in the second page and a corresponding third bit of the plurality of third bits in the third page, such that the plurality of multi-level cells store the first page, the second page, and the third page, and data accessing method comprising:
encoding weight data with parity fields placed after data fields in the weight data and storing the encoded weight data in the plurality of first bits in the first page;
extending normal data with padding in locations to correspond to locations of the parity fields and storing the extended normal data in the plurality of second bits in the second page and the plurality of third bits in the third page;
reading the plurality of first bits according to a one-time reading operation related to the corresponding first bit of each multi-level cell;
reading the plurality of second bits according to M reading operations related to the corresponding second bit of each multi-level cell; and
reading the plurality of third bits according to N reading operations related to the corresponding third bit of each multi-level cell,
wherein a magnitude of a difference between M and N is less than or equal to 1, the weight data is used in a multiplication and accumulation operation, and the normal data is data other than weight data.