Patent ID: 11880569
Assignee: MOSAID TECHNOLOGIES INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G  H

Claim 0:
1. A configurable memory device having a first operating mode and a second operating mode, the configurable memory device comprising:
a plurality of memory blocks to store user data;
a chip enable port configured to receive a chip enable signal for enabling the configurable memory device;
a first clock input port configured to receive a first clock input signal;
a second clock input port configured to receive a second clock input signal, the second clock input signal being complementary to the first clock input signal;
a clock output port configured to transmit a clock output signal when the configurable memory device is configured to the first operating mode, wherein the clock output signal is referenced to the first clock input signal;
one or more common data ports configured to transfer common data signals carrying command data, address data, input data and output data, the input data to be written into one of the plurality of memory blocks accessible based on the command data and the address data, and the output data to be retrievable from the one of the plurality of memory blocks;
a clock input circuitry configurable, to a differential signaling configuration when the configurable memory device is configured to the first operating mode, and to a single ended signaling configuration when the configurable memory device is configured to the second operating mode, the differential signaling configuration for utilizing the first clock input signal and the second clock input signal as differential signals, and the single ended signaling configuration for utilizing one of the first clock input signal and the second clock input signal as a single ended signal; and
one or more output buffers configurable to one of a plurality of output buffer drive strengths to transfer the output data retrieved from the one of the plurality of memory blocks, wherein the output data is synchronized with the clock output signal when the configurable memory device is configured to the first operating mode.