Patent ID: 11862700
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 0:
1. A method for forming a semiconductor device structure, comprising:
forming first and second fin structures from a substrate, wherein the first fin includes a first plurality of semiconductor layers, and the second fin includes a second plurality of semiconductor layers, wherein each of the first and second plurality of semiconductor layers comprises first semiconductor layers and second semiconductor layers;
forming a first dielectric feature between the first plurality of semiconductor layers and the second plurality of semiconductor layers;
forming a second dielectric feature adjacent the first plurality of semiconductor layers;
forming a third dielectric feature adjacent the second plurality of semiconductor layers;
forming a sacrificial gate stack on a portion of the first fin, the second fin, and the first, second, and third dielectric features, wherein a portion of the first fin, the second fin, and the first, second, and third dielectric features are exposed;
removing a portion of exposed portions of the first and second fins not covered by the sacrificial gate stack;
removing the sacrificial gate stack to expose portions of the first and second fins;
removing the second semiconductor layers of the first and second plurality of semiconductor layers so that the first semiconductor layers are spaced apart from each other by a first spacing, and the second dielectric feature is spaced apart from the first semiconductor layers by a second spacing smaller than the first spacing; and
forming a dummy material over the first, second, and third dielectric features and to surround at least three surfaces of the first semiconductor layers of the first and second plurality of semiconductor layers;
removing a portion of the dummy material to expose a portion of the first, second, and third dielectric features;
forming a mask layer over the exposed portion of the first, second, and third dielectric features;
removing the mask layer and a portion of the dummy material to expose the third dielectric feature and at least three surfaces of the first semiconductor layers of the first plurality of semiconductor layers; and
forming a first gate electrode layer to surround at least three surfaces of the first semiconductor layers of the first plurality of semiconductor layers, wherein the first gate electrode layer is exposed to a first air gap defined by the first spacing.