Patent ID: 11948645
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A page buffer, comprising:
a sensing node configured to sense a potential of a bit line coupled to a memory cell;
a precharging circuit coupled to the sensing node and configured to precharge a potential of the sensing node to a first voltage during an evaluation operation on the memory cell;
a discharging circuit coupled to the sensing node and configured to discharge the potential of the sensing node from the first voltage to a second voltage; and
a latch circuit coupled to the discharging circuit and configured to store therein data sensed from the memory cell based on a result of comparing the potential of the sensing node with a reference voltage after the potential of the sensing node is discharged to the second voltage and a predetermined period elapses,
wherein the evaluation operation is an operation of sensing a threshold voltage of the memory cell through the comparing the potential of the sensing node with the reference voltage,
wherein the precharging circuit includes a first transistor and a second transistor coupled in series between a power voltage node and the sensing node,
wherein the discharging circuit includes a third transistor, a fourth transistor, and a fifth transistor coupled between the sensing node and a ground node,
wherein the fourth transistor and the fifth transistor are coupled in parallel, and
wherein the third transistor is coupled in series to the parallel coupling of the fourth transistor and the fifth transistor,
wherein the first transistor and the second transistor are turned on in a first period and are turned off in a second period,
wherein the third transistor and the fifth transistor are turned on in the second period,
wherein the fourth transistor is turned off in the second period.