Patent ID: 11869829
Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A semiconductor device comprising:
a substrate having a top major surface and a bottom major surface opposite to the top major surface;
an electrically conductive pattern on the top major surface;
conductive lands on the bottom major surface including a first conductive land and a second conductive land;
conductive vias within the substrate electrically connecting portions of the electrically conductive pattern to the conductive lands, the conductive vias including a first conductive via connected to the first conductive land, wherein the first conductive via comprises a first width in a cross-sectional view;
a semiconductor component;
first bond pads on the semiconductor component;
conductive bumps directly connecting the first bond pads to the conductive lands other than the first conductive land and the second conductive land;
an electronic component mounted on the top major surface of the substrate;
a second bond pad on the electronic component;
a conductive interconnect directly connecting the second bond pad to the electrically conductive pattern;
a first package body portion encapsulating the semiconductor component, the conductive bumps, and at least portions of the bottom major surface of the substrate and comprising a bottom exterior surface distal to the bottom major surface of the substrate;
a second package body portion encapsulating the conductive interconnect and the electronic component;
a first electrically conductive path physically and electrically connected to the first conductive land and comprising a first outer surface exposed from the bottom exterior surface wherein the first electrically conductive path comprises a second width in the cross-sectional view that is greater than the first width; and
a second electrically conductive path physically and electrically connected to the second conductive land and comprising a second outer surface exposed from the bottom exterior surface, wherein:
the second package body portion contacts the top major surface of the substrate; and
the bottom exterior surface of the first package body portion is exposed outside of the semiconductor device.