Patent ID: 11947379
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 4:
5. The host interface of claim 3, wherein the negative edge detector includes:
a first negative edge synchronizer that allows a first-negative synchronizer signal to toggle at a next negative edge of the internal clock signal in response to toggling of the response;
a second negative edge synchronizer that allows a second-negative synchronizer signal to toggle at a next negative edge of the internal clock signal in response to toggling of the first-negative synchronizer signal;
a third negative edge synchronizer that allows a third-negative synchronizer signal to toggle at a next negative edge of the internal clock signal in response to toggling of the second-negative synchronizer signal; and
an AND gate that performs a logical AND operation on the third-negative synchronizer signal and an inverted version of the second-negative synchronizer signal to generate the negative edge detection signal.