Patent ID: 11889689
Assignee: KIOXIA CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor memory device comprising:
a first conductive layer and a second conductive layer provided in a first plane; and
at least one memory structure provided between the first conductive layer and the second conductive layer,
wherein the first conductive layer includes:
a first portion, a second portion, and a third portion each extending along a first direction in the first plane, the first portion being provided between the second portion and the third portion in a second direction in the first plane which intersects the first direction;
a fourth portion that connects the first portion and the second portion; and
a fifth portion that connects the first portion and the third portion,

wherein the second conductive layer includes:
a sixth portion, a seventh portion, and an eighth portion each extending along the first direction, the sixth portion being provided between the seventh portion and the eighth portion in the second direction;
a ninth portion that connects the sixth portion and the seventh portion; and
a tenth portion that connects the sixth portion and the eighth portion, and

wherein the second portion is provided between the sixth portion and the eighth portion in the second direction,
wherein the first conductive layer further includes an eleventh portion provided at one end of the first portion in the first direction, and
wherein the eleventh portion is electrically connected to a first contact on an upper surface in the first plane.