Patent ID: 11973061
Assignee: YIBU SEMICONDUCTOR CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A chip package, comprising:
a redistribution layer having a first side and an opposing second side, wherein a plurality of solder bumps are formed on the first side of the redistribution layer;
at least one chip stack disposed on the second side of the redistribution layer, each chip stack including stacked first chips, the stacked first chips including a bottom chip and one or more middle chips, each chip in the stacked first chips having chip contacts on a front side and the front side facing the redistribution layer;
at least one chip coupler stack disposed on the second side of the redistribution layer, wherein chip couplers in each chip coupler stack of the at least one chip coupler stack respectively correspond to first chips in the stacked first chips, the each chip coupler stack including a bottom chip coupler corresponding to the bottom chip, and one or more middle chip couplers corresponding to respective ones of the one or more middle chips, each chip coupler of the stacked chip couplers having a top surface facing away from the redistribution layer, a bottom surface facing the redistribution layer, top coupler contacts formed on the top surface, bottom coupler contacts formed on the bottom surface, and through vias between the top surface and the bottom surface, each respective through via of the through vias extending through the each chip coupler to couple a respective top coupler contact to a respective bottom coupler contact; and
at least one second chip placed over the at least one chip stack and assembled over the at least one chip coupler stack; wherein the at least one second chip, the at least one chip stack and the at least one chip coupler stack are encapsulated in a molding compound; and
wherein the redistribution layer is formed on the at least one bottom chip of each of the at least one chip stack and on the bottom chip coupler of each of the at least one chip coupler stack.