Patent ID: 11910611
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A nonvolatile memory device comprising:
a substrate including a cell region and a peripheral circuit region;
a stacked structure on the cell region, the stacked structure including a ground selection line, a plurality of word lines and a string selection line stacked sequentially from a top surface of the substrate, a lowermost word line of the plurality of word lines being a word line most adjacent to the ground selection line;
a peripheral circuit element on the peripheral circuit region;
a semiconductor pattern penetrating through the stacked structure;
a peripheral circuit contact including a lower contact and an upper contact, the lower contact being connected to the peripheral circuit element, and the upper contact being connected to the lower contact on the lower contact; and
a first cell contact connected to the ground selection line,
wherein a height of a top surface of the lower contact being higher than a top surface of the ground selection line, and being lower than or equal to a height of a bottom surface of the lowermost word line of the plurality of word lines, the upper contact has a bottom surface below the top surface of the lower contact and the bottom surface of the upper contact is within the lower contact, and
wherein a bottom surface of the first cell contact is below the top surface of the lower contact and in direct contact with the ground selection line.