Patent ID: 11963368
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 7:
8. A memory device, comprising:
a plurality of dielectric fins formed over a substrate; and
a plurality of memory cells disposed along respective sidewalls of the plurality of dielectric fins, each memory cells comprising: a first conductor layer, a selector layer; a resistive material layer, and a second conductor layer, wherein each of the first conductor layer, the selector layer, the resistive material layer and the second conductor layer of each memory cell directly contacts a respective flat surface of a respective sidewall of a respective dielectric fin, wherein lower and upper boundaries of the selector layer are each tilted away from the respective flat surface by an angle, wherein the angle is less than 90 degrees; and
a capping layer disposed along and directly contacting each of the first conductor layer, the selector layer, the resistive material layer, and the second conductor layer such that the at least one memory cell is disposed directly between the capping layer and a respective dielectric fin of the plurality of dielectric fins.