Patent ID: 11915746
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A memory device, comprising:
a memory array including a plurality of memory cells;
a word line (WL), connected to one of the plurality of memory cells, that is configured to provide a first WL pulse;
a first tracking WL, formed adjacent to the memory array, that is configured to provide, via a bit line (BL), a second WL pulse;
a first tracking BL, coupled to the first tracking WL, that is configured to emulate the BL and increase a width of the first WL pulse based on the second WL pulse;
a second tracking BL configured to emulate the BL; and
a second tracking WL, connected to the second tracking BL and closely coupled to the first tracking WL, that is configured to present a logic state inverse to a logic state of the first tracking WL so as to cause a rising edge of the second WL pulse to present a decreased slope.