Patent ID: 11887667
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 14:
15. A memory system comprising:
multiple memory devices, with one or more of the memory devices including:
data lines;
a memory array having vertical strings of memory cells with each vertical string arranged as a pillar coupled to a transistor, the transistor coupling the string to
a data line of the data lines, the transistor having:
a channel structure and a gate, the channel structure separated from the gate;
a first portion of the channel structure coupled to channel material of the vertical string and extending vertically from the channel material; and
a segmented portion of the channel structure extending vertically from the first portion, the segmented portion having a fin contacting and extending vertically from the first portion of the channel structure and a non-conductive region contacting and extending vertically from the first portion of the channel structure; and
a fanged region extending from the fin into the first portion of the channel structure; and

a memory controller including processing circuitry, the memory controller configured to perform operations including performance of an erase operation on a selected string of the memory array with application of an erase voltage to the gate of the transistor coupling the selected string to the data line associated with the selected string.