Patent ID: 11881281
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 12:
13. The equalizer circuit of claim 12, wherein the target values of the original code, the first code and the second code are set by the following operations:
a first operation of setting initial values of the original code, the first code and the second code as 0;
a second operation of adding 1 to the value of the original code, and testing a magnitude of the timing margin in the eye diagram corresponding to the received data of the equalizer circuit;
a third operation of repeatedly performing the second operation until the maximum value of the timing margin is obtained;
a fourth operation of setting the target value of the original code as a value of the original code when the timing margin is at the maximum value;
a fifth operation of respectively adding 1 to the values of the first code and the second code, and testing a magnitude of the voltage margin in the eye diagram corresponding to the received data of the equalizer circuit;
a sixth operation of repeatedly performing the fifth operation until the maximum value of the voltage margin is obtained; and
a seventh operation of setting the target values of the first code and the second code as values of the first code and the second code when the voltage margin is at the maximum value.