Patent ID: 11972791
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. A nonvolatile memory device comprising:
a memory cell array including a plurality of memory cells having a plurality of states including a first state and a second state; and
a control circuit configured to perform a first read operation for the first state and a second read operation for the second state,
wherein, to perform the first read operation, the control circuit obtains cell counts for a valley of the first state by performing a valley cell count operation for the first state, determines a first read voltage level for the first state based on the cell counts and at least one first reference parameter for the first state, and performs a first sensing operation for the first state by using the first read voltage level,
wherein the cell counts comprise a first cell count of a first region where the first state overlaps the second state in a plot characterizing a number of on-cells of the first state and a number of on-cells of the second state against threshold voltage, and
wherein, to perform the second read operation, the control circuit determines a second read voltage level for the second state based on the cell counts and at least one second reference parameter for the second state, and performs a second sensing operation for the second state by using the second read voltage level.