Patent ID: 11968879
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  Y | IPC H

Claim 8:
9. A method for manufacturing a display substrate, comprising:
providing a display substrate motherboard, wherein the display substrate motherboard comprises at least one display substrate area, the display substrate area comprises a silicon base substrate, and a plurality of metal traces for connecting a display area and a cathode ring with a bonding area respectively are contained in the silicon base substrate;
forming a color film layer on the silicon base substrate, wherein the color film layer comprises a first align mark, the first align mark has a hollowed-out structure, and a projection of the first align mark on the silicon base substrate and projections of the metal traces on the silicon base substrate comprise overlapping areas; and
cutting the display substrate motherboard to obtain a separate display substrate,
wherein the display area comprise a light-emitting structural layer disposed on the silicon base substrate, and the light-emitting structural layer comprises a reflective layer, an anode layer, an organic light-emitting layer and a cathode layer which are sequentially stacked,
wherein a driving circuit layer is disposed in the silicon base substrate in the display area and comprises a first scanning line, a first power line, a data line, a switching transistor and a driving transistor; a control electrode of the switching transistor is connected with the first scanning line, a first electrode of the switching transistor is connected with the data line, a second electrode of the switching transistor is connected with a control electrode of the driving transistor, and a first electrode of the driving transistor is connected with the first power line; the switching transistor is configured to receive a data signal transmitted by the data line under the control of a first scanning signal output by the first scanning line, to make the control electrode of the driving transistor receive the data signals, and the driving transistor is configured to generate a corresponding current at the second electrode under the control of the data signal received by the control electrode thereof, and
wherein the metal traces and the driving circuit layer are disposed on the same layer.