Patent ID: 11860980
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A system, the system comprising:
a memory, the memory containing one or more instructions; and
a processor, the processor communicatively coupled to the memory, the processor, in response to reading the one or more instructions, configured to:
receive source code for the monolithic application;
map the source code into a directed graph;
split the graph into subgraphs and optimizing the subgraph;
provide the detailing of the micro service application split, based on the subgraphs; and
perform multiple iterations to optimize a subgraph of the subgraphs; wherein:

the split of the graph further comprises the processor being configured to utilize a discovery algorithm and a label classification model for the split of the directed graph into the subgraphs;
the iterative optimization comprises the processor being configured to verify each iterative result based on predefined constraints;
the predefined constraints comprise:
different sub graphs can only be called one-way and not in a loop; and
a division of subgraphs follows a horizontal split according to a level label, and not on a vertical; and

the label classification model causes the processor to label each class node, wherein the label for each class node is selectable from the hierarchical group comprising “basic service layer”, “composite service layer”, and “controller layer”.