Patent ID: 11942528
Assignee: nan
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor device comprising:
a substrate;
a first fin, a second fin, a third fin and a fourth fin on the substrate;
a first isolation on the substrate;
a second isolation on the substrate and between the first fin and the second fin, the first fin between the first isolation and the second isolation;
a third isolation on the substrate and between the second fin and the third fin;
a fourth isolation on the substrate and between the third fin and the fourth fin;
a fifth isolation on the substrate, the fourth fin between the fourth isolation and the fifth isolation;
a first gate on the first through fourth fins and the first through fifth isolations;
a second gate on the first through fourth fins and the first through fifth isolations;
a first epitaxial source/drain on the first fin and between the first gate and the second gate;
a second epitaxial source/drain on the second fin and between the first gate and the second gate;
a third epitaxial source/drain on the third fin and between the first gate and the second gate;
a fourth epitaxial source/drain on the fourth fin and between the first gate and the second gate; and
a contact on the first through fourth epitaxial source/drain,
wherein the first, second, third and fourth epitaxial source/drains are merged into a merged epitaxial source/drain, and
wherein an upper surface of the merged epitaxial source/drain includes a first recess and a second recess.