Patent ID: 11900983
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device comprising:
a plurality of memory cells; and
circuitry configured to:
store a plurality of values, each value of the plurality of values corresponding to a subset of memory cells of the plurality of memory cells, and
perform, when a first value of the plurality of values corresponding to a first subset of memory cells exceeds a first threshold, a first maintenance operation on the first subset of memory cells;
update the first value of the plurality of values based at least in part on performing the first maintenance operation;
perform, when a second value of the plurality of values corresponding to a second subset of memory cells exceeds a second threshold, a second maintenance operation on the second subset of memory cells; and
update the second value of the plurality of values based at least in part on performing the second maintenance operation.