Patent ID: 11901223
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A stress analysis method comprising:
dividing, in chip design data, a surface of an object into a plurality of first rectangles each having a first size;
acquiring a first type value for each of the first rectangles;
specifying, from among the first rectangles, a plurality of second rectangles that have the first type value of a magnitude that falls within a first range and form a rectangle; and
generating a stress model for a set of the second rectangles by using the second rectangles as an element, wherein
the acquiring of the first type value for each of the first rectangles includes:
acquiring a second type value for each of the first rectangles; and
calculating a first median value of the second type value of a third rectangle included in the first rectangles and the second type values of a plurality of fourth rectangles that are included in the first rectangles and aligned with the third rectangle.