Patent ID: 11862635
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A method of fabricating an integrated circuit structure, the method comprising:
forming a first fin having a longest dimension along a first direction;
forming a first nanowire over the first fin;
forming a second fin having a longest dimension along the first direction;
forming a second nanowire over the second fin, wherein the second nanowire is wider than the first nanowire;
forming a first gate structure over the first nanowire and the first fin, the first gate structure having a longest dimension along a second direction, the second direction orthogonal to the first direction;
forming a second gate structure over the second nanowire and over the second fin, the second gate structure having a longest dimension along the second direction, the second gate structure continuous with the first gate structure along the second direction;
forming first epitaxial source or drain structures at ends of the first nanowire;
forming second epitaxial source or drain structures at ends of the second nanowire wherein neighboring ones of the first epitaxial source or drain structures and of the second epitaxial source or drain structures have a laterally merged region there between;
removing the laterally merged region to disjoin the neighboring ones of the first epitaxial source or drain structures and of the second epitaxial source or drain structures; and
forming an intervening dielectric structure between the neighboring ones of the first epitaxial source or drain structures and of the second epitaxial source or drain structures.