Patent ID: 11929379
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for forming an integrated chip, the method comprising:
forming a through substrate via (TSV) in a first substrate, wherein the TSV continuously extends from a first surface of the first substrate to a second surface of the first substrate;
forming a conductive contact on the second surface of the first substrate, wherein the conductive contact comprises a first conductive layer disposed on the TSV; and
forming an upper conductive layer between the conductive contact and the TSV, wherein the upper conductive layer comprises a silicide of a conductive material of the first conductive layer, wherein the upper conductive layer is formed after forming the conductive contact on the TSV, wherein the upper conductive layer extends from a bottom surface of the upper conductive layer to a point below the second surface of the first substrate.