Patent ID: 11882704
Assignee: SK HYNIX INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of manufacturing a semiconductor memory device, comprising:
forming a preliminary stacked body including alternately stacked interlayer insulating layers and sacrificial layers;
forming a channel hole passing through the preliminary stacked body;
forming a memory layer extending along a sidewall of the channel hole;
forming a channel layer extending along a surface of the memory layer;
forming a core insulating layer along a surface of the channel layer and the core insulating layer filling the channel hole;
etching the core insulating layer, the channel layer, and the memory layer disposed in an upper portion of the channel hole such that the channel layer has a protrusion protruding with respect to the core insulating layer and the memory layer; and
forming a doped semiconductor pattern in the upper portion of the channel hole,
wherein the memory laver is etched such that an upper surface of the memory layer is placed at a height corresponding to a portion of a sidewall of an upper sacrificial layer disposed uppermost, among the sacrificial layers.