Patent ID: 11901299
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 22:
23. An electronic package comprising:
a package substrate, the package substrate having a plurality of interconnect bridges thereon;
a first interposer over the package substrate, the first interposer comprising silicon;
a first plurality of die stacks on the first interposer, wherein each of the first plurality of die stacks comprises a field-programmable gate array (FPGA), and wherein the first plurality of die stacks are electrically coupled together by conductive traces in the first interposer, and wherein first interconnects electrically couple the first plurality of die stacks to the first interposer, wherein the first interconnects have a first pitch; and
a first die on the package substrate, wherein the first die is electrically coupled to the first interposer by the one of the interconnect bridges in the plurality of interconnect bridges, wherein second interconnects electrically couple the first interposer to the one of the interconnect bridges and the first die to the one of the interconnect bridges, wherein the second interconnects have a second pitch that is larger than the first pitch.