Patent ID: 11960776
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G  H

Claim 11:
12. A method, comprising:
during a first portion of a burst length:
sending a signal indicative of first host data from a respective primary memory die of each memory unit of a first number of memory units via a first external data link; and
sending a signal indicative of first parity data for performing an error correction operation on the first host data from a primary memory die of a second memory unit via a second external data link; and

during a second portion of the burst length:
sending a signal indicative of second host data from a secondary memory die of each memory unit of the first number of memory units via the first external data link; and
sending a signal indicative of second parity data for performing the error correction operation on the second host data from a secondary memory die of the second memory unit via the second external data link.