Patent ID: 11955384
Assignee: NATIONAL TAIWAN UNIVERSITY
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 13:
14. A method comprising:
providing a workpiece comprising:
a fin structure comprising a bottom channel layer over a substrate, a sacrificial layer over the bottom channel layer, and a top channel layer over the sacrificial layer; and
a dummy gate across the fin structure;

forming bottom source/drain epitaxial structures on opposite sides of the bottom channel layer;
after forming the bottom source/drain epitaxial structures, forming dielectric blocking layers on opposite sides of the top channel layer;
forming isolation structures over the bottom source/drain epitaxial structures, respectively;
after forming the isolation structures, removing the dielectric blocking layers to expose the top channel layer, wherein after removing the dielectric blocking layers, a length of the bottom channel layer is greater than a length of the top channel layer;
forming top source/drain epitaxial structures on opposite sides of the top channel layer; and
replacing the dummy gate and the sacrificial layer with a gate structure.