Patent ID: 11942326
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. A process of forming an electronic device comprising:
forming a gate electrode layer comprising:
forming a first film of the gate electrode layer, wherein the first film includes a first III-V material;
forming a first dopant region of the gate electrode layer, wherein the first dopant region has a first conductivity type; and
forming a second film of the gate electrode layer overlying the first film of the gate electrode layer, wherein the second film includes a second III-V material;

forming a silicon nitride layer over the second film of the gate electrode layer, wherein:
forming the silicon nitride layer is performed using a silicon-containing gas and a nitrogen-containing gas at a temperature of at least 750° C., and
the silicon-containing gas includes SiH4, SiH3Cl, SiH2Cl2, or SiHCl3, and the nitrogen-containing gas includes NH3, N2, N2O, or N2H4;

patterning the gate electrode layer to form a gate electrode;
thermally annealing the silicon nitride layer such that some Si from the silicon nitride layer migrates into the gate electrode layer or the gate electrode and forms a Si-doped region within the gate electrode layer or the gate electrode, and the Si-doped region has a second conductivity type that is opposite the first conductive type, wherein thermally annealing is performed after forming the silicon nitride layer; and
forming a gate interconnect that contacts the Si-doped region of the gate electrode.