Patent ID: 11948638
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 1:
2. The apparatus of claim 1, wherein the controller is further configured to:
apply a first sequence of voltages to a first subset of the plurality of bit lines during the first duration, the second duration, the third duration, or a combination thereof, wherein the at least one memory cell of the first subset of the first tier of memory cells thresholds and is written to the first logic state based at least in part on applying the first sequence of voltages; and
apply a second sequence of voltages to a second subset of the plurality of bit lines during the first duration, the second duration, the third duration, or a combination thereof, wherein the at least one memory cell of the second subset of the first tier of memory cells thresholds and is written to the second logic state based at least in part on applying the second sequence of voltages.