Patent ID: 11908411
Assignee: HKC CORPORATION LIMITED
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A display panel, comprising:
a plurality of pixel driving circuits arranged in an array along a row direction and a column direction;
wherein the display panel further comprises a plurality of first control lines, a plurality of second control lines, a plurality of data lines, and a plurality of power lines;
wherein each of the pixel driving circuits is correspondingly connected to the first control line, the second control line, the data line, and two power lines, and the two power lines comprises a first power line and a second power line;
wherein the pixel driving circuit, comprises:
a driving transistor having a control terminal connected to a point G, a first terminal connected to a point D, and a second terminal connected to ground;
a storage capacitor having a first terminal connected to the point G, and a second terminal connected to ground;
a sampling compensation assembly, comprising a first response terminal connected to the point G, a first connection terminal connected to a point A, and a second connection terminal connected to a point B, the first response terminal being configured to respond to a level signal at the point G to control an on-off state between the first connection terminal and the second connection terminal;
a first switch assembly, comprising a second response terminal connected to the first control line, a third connection terminal connected to the first power line of the two power lines, and a fourth connection terminal connected to the point B, the second response terminal being configured to respond to a level signal provided by the first control line to control an on-off state between the third connection terminal and the fourth connection terminal;
a second switch assembly, comprising a third response terminal connected to the second control line, a data writing terminal connected to the data line, a fifth connection terminal connected to the point A, a sixth connection terminal connected to the point B, and a seventh connection terminal connected to the point G, the third response terminal being configured to respond to a level signal provided by the second control line to control an on-off state between the data writing terminal and the fifth connection terminal and an on-off state between the sixth connection terminal and the seventh connection terminal; and
a light emitting device having a cathode connected to the point D and an anode connected to the second power line of the two power lines, the second power line being configured to provide a high level signal during a displaying light emitting stage and a low level signal in other stages;

wherein the power lines extend in a row direction, and the power lines and the pixel driving circuit each comprises N rows;
wherein in a first row of the pixel driving circuit, the anode of the light emitting device is connected to a first row of the power line, and the third connection terminal of the first switch assembly is connected to an N-th row of the power line, wherein the first row of the power line is the second power line of the two power lines, and the N-th row of the power line is the first power line of the two power lines;
wherein in an n-th first row of the pixel driving circuit, the anode of the light emitting device is connected to the n-th row of the power line, and the third connection terminal of the first switch assembly is connected to an n-1-th row of the power line;
wherein the n-th row of the power line is the second power line of the two power lines, and the n-1-th row of the power line is the first power line of the two power lines;
wherein n and N are positive integers, and 1<n≤N;
wherein the sampling compensation assembly comprises a sampling compensation transistor having a control terminal serving as the first response terminal, a first terminal serving as the first connection terminal, and a second terminal serving as the second connection terminal;
the first switch assembly comprising a first switch transistor having a control terminal serving as the second response terminal, a first terminal serving as the third connection terminal, and a second terminal serving as the fourth connection terminal;
the second switch assembly comprising a second switch transistor and a third switch transistor having control terminals of the second switch transistor and the third switch transistor connected to the third response terminal, a first terminal of the second switch transistor serving as the data writing terminal, a second terminal of the second switch transistor serving as the fifth connection terminal, a first terminal of the third switch transistor serving as the sixth connection terminal, and a second terminal of the third switch transistor serving as the seventh connection terminal;
wherein the types of the driving transistor, the sampling compensation transistor, the first switch transistor, the second switch transistor, and the third switch transistor are the same;
wherein the control terminal of the sampling compensation transistor and the control terminal of the driving transistor are arranged on the same layer; wherein the first terminal of the sampling compensation transistor is arranged on the same layer as the first terminal of the driving transistor, and the second terminal of the sampling compensation transistor is arranged on the same layer as the second terminal of the driving transistor.