Patent ID: 11901176
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for fabricating a semiconductor arrangement, comprising:
forming a first dielectric layer;
forming a first semiconductive layer over the first dielectric layer;
forming a photoresist layer over the first semiconductive layer;
patterning the first semiconductive layer using the photoresist layer to form a patterned first semiconductive layer, wherein a first portion of the first dielectric layer is exposed through the patterned first semiconductive layer;
forming a second photoresist layer over the patterned first semiconductive layer, wherein a second portion of the first dielectric layer is exposed through the second photoresist layer, the second portion of the first dielectric layer being a portion of but less than all of the first portion of the first dielectric layer; and
recessing the second portion of the first dielectric layer using the second photoresist layer.