Patent ID: 11869892
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A semiconductor device structure, comprising:
a first source/drain epitaxial feature disposed in an N-type region;
a first conductive feature disposed over the first source/drain epitaxial feature;
a first fin in contact with the first source/drain epitaxial feature, wherein the first fin comprises a first semiconductor layer;
a contact etch stop layer (CESL) disposed adjacent the first conductive feature;
a first gate dielectric layer in contact with the first fin;
a first gate electrode layer disposed over the first gate dielectric layer; and
a first spacer in contact with the first fin, the first spacer comprising:
a first portion disposed between and in contact with the CESL and the first gate dielectric layer; and
a second portion disposed between and in contact with the first gate dielectric layer and the first source/drain epitaxial feature, wherein the second portion has a bottom at a level higher than a bottom of the first gate dielectric layer, and the bottom of the second portion has a slope with a highest point adjacent the first gate dielectric layer and a lowest point away from the first gate dielectric layer.