Patent ID: 11862622
Assignee: WINBOND ELECTRONICS CORP.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC H

Claim 14:
15. The integrated circuit layout according to claim 11, wherein:
the third gate line width equals to a sum of the first gate line width and a variable;
the first gate lines comprise a first gate line space between edges of the first gate lines, the third gate lines comprise a third gate line space between the edges of the third gate lines, wherein the third gate line space is smaller than the first gate line space by the variable; and
an edge of the dummy gate line and an edge of the first gate lines adjacent to the edge of the dummy gate lines comprise a first dummy gate line space, another edge of the dummy gate line and an edge of the third gate lines adjacent to the another edge of the dummy gate lines comprise a third dummy gate line space, wherein the third dummy gate line space is smaller than the first dummy gate line space by 0.5 of the variable.