Patent ID: 11922998
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device, comprising:
a memory bank including a memory cell connected to a local bit line and a word line;
a first local data latch connected to the local bit line, the first local data latch having an enable terminal configured to receive a first local clock signal;
a first global data latch connected to the first local data latch by a global bit line, the first global data latch having an enable terminal configured to receive a global clock signal; and
a NOR gate including:
a first input connected to receive an output of the first local data latch;
a second input connected to the first local clock signal via an inverter; and
an output connected to the local bit line.