Patent ID: 11948935
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 6:
7. A method of forming an integrated circuit structure, comprising:
providing a substrate having a standard cell and a tap cell adjacent to each other;
forming a first well having a first dopant type in the substrate, wherein the first well continuously extends through the standard cell and the tap cell in an X direction;
forming a second well having a second dopant type in the substrate, wherein the second well continuously extends through the standard cell and the tap cell in the X direction, and the first well in the tap cell has a first jog extending into the second well;
forming a first set of implants having the first dopant type in the first jog of the first well to be coupled to a first supply voltage; and
forming a first active region continuously extending from the first jog of the first well through the tap cell and the standard cell along the X direction
wherein the second well in the tap cell has a second jog extending into the first well, the second jog of the second well are adjacent to the first jog of the first well.