Patent ID: 11876080
Assignee: KIOXIA CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 14:
15. A semiconductor memory device comprising:
a plurality of memory chips each extending in a first direction and a second direction and stacked to partially overlap each other in a third direction, the first, second, and third directions crossing one another, each memory chip including
a core circuit in which a plurality of memory cells are provided, the core circuit being arranged in a first rectangular region with a first side extending in the first direction and a second side extending in the second direction orthogonal to the first direction,
a first area adjacent to the first side and extending in the first direction,
a second area adjacent to the second side and extending in the second direction,
a third area adjacent to the first area in the first direction and adjacent to the second area in the second direction,
a first power supply pad provided in the first area,
a second power supply pad provided in the first area,
a third power supply pad provided in the third area,
a first signal pad provided in the second area, and
a second signal pad provided in the second area;

a first bonding wire that connects the second and third power supply pads of each of the memory chips;
a plurality of second bonding wires, each of which connects the third power supply pads of two memory chips that are adjacent to each other in the third direction.