Patent ID: 11935586
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. The memory device of claim 1, further comprising a third computation circuit and a fourth computation circuit, wherein
the memory cells in each of the plurality of columns further comprise third memory cells and fourth memory cells,
the first through fourth memory cells are alternately arranged in each of the plurality of columns,
the third computation circuit is coupled to the third memory cells in each of the plurality of columns, and configured to generate third output data corresponding to a third computation performed on third weight data stored in the third memory cells; and
the fourth computation circuit is coupled to the fourth memory cells in each of the plurality of columns, and configured to generate fourth output data corresponding to a fourth computation performed on fourth weight data stored in the fourth memory cells.