Patent ID: 11942047
Assignee: SHANGHAI TIANMA MICRO-ELECTRONICS CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A display panel, comprising:
at least one pixel circuit; and
a light emitting element,
wherein one pixel circuit of the at least one pixel circuit comprises a driving transistor, a second transistor, a third transistor, a reset module, and a first light-emission controlling module, wherein the second transistor is connected between a data line and a source of the driving transistor, the third transistor is connected between a voltage adjusting signal line and the source of the driving transistor, the reset module is connected between a reset voltage input terminal and a gate of the driving transistor, and the first light-emission controlling module is connected between a first power supply terminal and the source of the driving transistor; and
wherein an operation process of the display panel comprises a light emitting phase, a data writing phase, a reset and adjustment phase, and a reset phase,
wherein during the light emitting phase, the first light-emission controlling module is turned on, the first power supply terminal is configured to provide a power supply voltage to the source of the driving transistor, and the power supply voltage is VP;
wherein, during the data writing phase, the second transistor is turned on, the data line is configured to provide a data signal to the source of the driving transistor, the data signal is VData, the gate of the driving transistor is configured to receive the data signal, and a voltage of the gate of the driving transistor is VData+Vth, where Vth denotes a threshold voltage of the driving transistor;
wherein, during the reset and adjustment phase, the third transistor is turned on, the voltage adjusting signal line is configured to provide an adjusting voltage to the source of the driving transistor, the adjusting voltage is VJ, a voltage of the source of the driving transistor is VJ, and the voltage of the gate of the driving transistor remains VData+Vth;
wherein, during the reset phase, the reset module is turned on, the reset voltage input terminal is configured to provide a reset signal to the gate of the driving transistor, the reset signal is VR, the voltage of the gate of the driving transistor is VR, and the voltage of the source of the driving transistor is VP, where −3V≤(VR−VP)−(VData+Vth−VJ)≤3V, the voltage of the source of the driving transistor is VData, where −3V≤(VR−VData)−(VData+Vth−VJ)≤3V, or the voltage of the source of the driving transistor is VJ, where −3V≤(VR−VJ)−(VData+Vth−VJ)≤3V.