Patent ID: 11955184
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. The method of claim 11, wherein reading the first set of the memory cells with the first set of read parameters and reading the second set of the memory cells with the second set of read parameters comprises:
applying a read reference voltage to a selected word line connected to the first set of memory cells and the second set of memory cells;
sensing the first set of memory cells while applying a first bit line voltage to a first set of the bit lines associated with first NAND strings having the first set of memory cells and while applying the read reference voltage to the selected word line; and
sensing the second set of memory cells while applying a second bit line voltage to a second set of the bit lines associated with second NAND strings having the second set of memory cells and while applying the read reference voltage to the selected word line, wherein the second bit line voltage has a different magnitude than the first bit line voltage to compensate for the different threshold voltage ranges.