Patent ID: 11922992
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A memory device comprising:
a memory cell array including a plurality of memory cells connected to a plurality of word lines;
a row address decoder configured to:
generate a plurality of main word line driving signals and a plurality of sub word line driving signals based on a row address, and
generate a plurality of encoded sub word line driving signals for driving a target word line among the plurality of word lines by outputting the plurality of sub word line driving signals in different orders in accordance with an odd even signal representing whether an odd main word line or an even main word line is activated; and

a word line driving circuit configured to drive the target word line based on the odd even signal and the plurality of encoded sub word line driving signals.