Patent ID: 11906332
Assignee: STMICROELECTRONICS (ROUSSET) SAS
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 19:
20. A system, comprising:
an integrated circuit, including:
a first substrate; and

a first MOS transistor having a first polysilicon region electrically isolated from the first substrate and including a gate region, a second polysilicon region electrically isolated from the first polysilicon region and from the first substrate, said second polysilicon region including a source region, a substrate region and a drain region of said first MOS transistor, wherein the first polysilicon region is located between an area of the first substrate and the second polysilicon region;
wherein the integrated circuit further comprises:
an isolation trench located in the first substrate; and
a dielectric layer surrounding the first polysilicon region, wherein the first polysilicon region is surrounded by the dielectric layer thereof extending through the isolation trench into the first substrate, and wherein the substrate region of the first MOS transistor rests at least partially on one end of the first polysilicon region surrounded by said dielectric layer and the source and drain regions resting on the isolation trench.