Patent ID: 11861279
Assignee: KEPLER COMPUTING INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 18:
19. A system comprising:
a memory to store one or more instructions;
a processor coupled to the memory, wherein the processor is to execute the one or more instructions; and
a communication interface to allow the processor to communicate with another device, wherein the processor is to perform inverter minimization, and wherein the processor is to:
receive one or more inputs including a majority or minority inverter graph and a synthesis objective, wherein a logic circuit is associated with the majority or minority inverter graph;
collect a list of majority or minority gates, for an individual depth, in an order, wherein the list of majority or minority gates includes ‘r’ majority or minority gates;
for the individual depth, select the ‘r’ majority or minority gates;
generate a function of ‘r’ new majority or minority inverter graphs from the majority or minority inverter graph at the individual depth;
simplify the function of ‘r’ new majority or minority inverter graphs to generate a simplified function of the ‘r’ new majority or minority inverter graphs;
determine whether the synthesis objective is delay minimization; and
determine a second majority or minority inverter graph, that results in a smallest delay in the individual depth, based on determining that the synthesis objective is delay minimization and based on the simplified function of the ‘r’ new majority or minority inverter graphs.