Patent ID: 11916548
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A buffer circuit comprising:
an input terminal configured to receive an input signal;
an output terminal;
an inverter; and
a resistor-capacitor (RC) circuit coupled in series with the inverter between the input terminal and the output terminal,
wherein
the RC circuit comprises:
an NMOS transistor coupled between an RC circuit output terminal and a reference node;
a resistor coupled between the RC circuit output terminal and a power supply node; and
a capacitor coupled between the RC circuit output terminal and one of the power supply node or the reference node,

a gate of the NMOS transistor is coupled to the input terminal, and
the inverter and the RC circuit are configured to generate an output signal at the output terminal based on the input signal.