Patent ID: 11929118
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 17:
18. A non-volatile memory device comprising:
a plurality of word lines including a first group including word lines relatively close to a substrate and a second group including word lines relatively far from the substrate;
a string select line above the plurality of word lines;
a memory cell array including a plurality of cell strings, each cell string extending in a vertical direction above the substrate and each cell string being connected to the plurality of word lines and the string select line;
a page buffer circuit including a plurality of page buffers connected to the memory cell array, each page buffer being connected to a selected cell string through a bit line and including a bit line shut-off transistor configured to be driven in response to a bit line shut-off signal and a forcing latch configured to store forcing information; and
a control logic circuit configured to, in a program operation on a selected word line, control a voltage applied to the string select line to perform a bit line forcing operation of transferring the forcing information to the selected cell string through the bit line and a bit line shut-off voltage corresponding to the bit line shut-off signal,
the control logic circuit being further configured to
control a first voltage applied to the string select line in a first interval before the bit line forcing operation is performed differently with respect to the first group and the second group, and
control a delay interval in which the bit line shut-off voltage maintains a voltage level corresponding to a ground voltage before the bit line forcing operation is performed differently with respect to the first group and the second group.