Patent ID: 11955956
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A circuit comprising:
a drain voltage input terminal configured to receive a first voltage;
a source voltage input terminal configured to receive a second voltage;
a main circuit connected between the drain voltage input terminal and the source voltage input terminal and comprising a plurality of first transistors in parallel connection;
a second transistor comprising a drain terminal electrically coupled to the drain voltage input terminal, a source terminal electrically coupled to the source voltage input terminal, and a gate terminal;
a capacitive element comprising a first terminal and a second terminal, the first terminal of the capacitive element being electrically coupled to the drain voltage input terminal, wherein in response to situations where the first voltage is greater than a breakdown voltage of the plurality of first transistors, the capacitive element is configured to provide a voltage to turn on the second transistor; and
a resistive element comprising a third terminal and a fourth terminal, the third terminal being electrically coupled to the second terminal, and the fourth terminal being electrically coupled to the source voltage input terminal,
wherein the gate terminal of the second transistor is electrically coupled to the second terminal of the capacitive element.