Patent ID: 11922032
Assignee: DREAMBIG SEMICONDUCTOR INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G

Claim 0:
1. A content addressable memory circuit comprising:
multiple integrated circuit memory devices that include memory address locations that share common memory addresses and that are coupled for simultaneous access;
multiple buffer circuits, each buffer circuit operatively coupled to a different one of the multiple memory devices;
a hash table that includes a plurality of hash values, wherein each hash value corresponding to one or more key values;
one or more processor circuits;
non-transitory memory including instructions incorporated into the non-transitory memory, the instructions configuring the one or more processors to perform operations comprising:
assigning each hash value to a memory address location based upon a first portion of the hash value;
causing the storing of each key value at the memory address location assigned to a first portion of a hash value that corresponds to the key value;
causing a memory device to copy a first key value from a first memory address location within the memory device to a buffer circuit operatively coupled to the memory device;
causing the memory device to copy the first key value from the buffer circuit operatively coupled to the memory device to a second memory address location of the memory device; and
assigning a second portion of a hash value that corresponds to the first key value to the second memory address location of the memory device.