Patent ID: 11910592
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. A DRAM device, comprising:
a cell transistor on a substrate, the cell transistor including a gate structure, a first impurity region, and a second impurity region;
a bit line structure electrically connected to the first impurity region;
a capacitor on the bit line structure, the capacitor electrically connected to the second impurity region,
wherein the capacitor comprises:
a lower electrode;
a dielectric layer structure on the lower electrode, the dielectric layer structure including a plurality of dielectric layers and at least one insert layer structure between ones of the plurality of dielectric layers, the dielectric layer structure having a thickness of 30 Å to 60 Å; and
an upper electrode on the dielectric layer structure,
wherein the at least one insert layer structure comprises at least a first zirconium oxide layer, an aluminum oxide layer, and a second zirconium oxide layer stacked sequentially, and
wherein the dielectric layer structure includes a plurality of aluminum oxide layers,
wherein the at least one insert layer structure comprises a single insert layer structure in the dielectric layer structure, and wherein the single insert layer structure includes the plurality of aluminum oxide layers spaced apart from each other and the single insert layer structure comprising the plurality of aluminum oxide layers is higher than a central portion in a vertical direction of the dielectric layer structure.