Patent ID: 11922885
Assignee: XIAMEN TIANMA DISPLAY TECHNOLOGY CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A display panel, comprising:
a plurality of rows of pixel circuits;
a gate drive circuit configured to be switched between a first drive mode and a second drive mode, wherein the first drive mode comprises that the gate drive circuit provides gate signals to n rows of the pixel circuits simultaneously, and the second drive mode comprises that the gate drive circuit provides gate signals to m*n rows of the pixel circuits simultaneously, wherein n is a positive integer, and m is an integer greater than or equal to 2,
wherein m=2, and the gate drive circuit comprises a plurality of stages of first shift register units and a plurality of stages of second shift register units;
each of the first shift register units comprises a first start signal input terminal and a first output terminal, and each of the second shift register units comprises a second start signal input terminal and a second output terminal;
a first output terminal of a first shift register unit of a ith stage is electrically connected to a first start signal input terminal of a first shift register unit of a (i+1)th stage via a first switch, and the first output terminal of the first shift register unit of the ith stage is directly electrically connected to (2*i*n−2*n+1)th to (2*i*n−n)th rows of the pixel circuits via connecting lines, and the first output terminal of the first shift register unit of the ith stage is electrically connected to (2*i*n−n+1)th to (2*i*n)th rows of the pixel circuits via a second switch;
the first output terminal of the first shift register unit of the ith stage is electrically connected to a second start signal input terminal of a second shift register unit of a ith stage via a third switch;
a second output terminal of the second shift register unit of the ith stage is electrically connected to the first start signal input terminal of the first shift register unit of the (i+1)th stage via a fourth switch; and
the second output terminal of the second shift register unit of the ith stage is electrically connected to (2*i*n−n+1)th to (2*i*n)th rows of the pixel circuits via a fifth switch,
wherein i is a positive integer.