Patent ID: 11907084
Assignee: ATLIS MOTOR VEHICLES, INC.
Field: Control (Instruments)
Classification: CPC G | IPC G

Claim 8:
9. A vehicle comprising: a control bus; a first system adapted to be connected to the control bus, the first system adapted to perform a first function of the vehicle; a second system adapted to be connected to the control bus, the second system adapted to perform a second function of the vehicle; a first system controller, the first system controller includes a first translator, a first processing circuit, and a first tri-state buffer, the first system controller adapted to be connected to the first system via a first bus, the first system controller further adapted to be connected to the control bus, the first system controller adapted to provide a first plurality of control signals to the first system via the first bus, the first system controller is further adapted to provide a second plurality of control signals to the second system via the control bus, the first plurality of control signals for controlling the first system to perform the first function; a second system controller, the second system controller includes a second translator, a second processing circuit, and a second tri-state buffer, the second system controller adapted to be connected to the second system via a second bus, the second system controller further adapted to be connected to the control bus, the second system controller adapted to provide the second plurality of control signals to the second system via a second bus, the second system controller is further adapted to provide the first plurality of control signals to the first system via the control bus, the second plurality of control signals for controlling the second system to perform the second function; and a central control system, the central control system adapted to couple the first processing circuit to the first bus or the control bus to the first bus via the first translator, the second processing circuit to the second bus or the control bus to the second bus via the second translator, the first processing circuit to the control bus via the first tri-state buffer, and the second processing circuit to the control bus via the second tri-state buffer; wherein: while all system controllers are functional, the central control system controls the first translator and the second translator to connect the first processing circuit to the first bus and the second processing circuit to the second bus respectively, whereby the first processing circuit provides the first plurality of control signals to the first system via the first bus and second processing circuit provides the second plurality of control signals to the second system via the second bus; while all system controllers are functional, the central control system further controls the first tri-state buffer and the second tri-state buffer to disconnect the first processing circuit from the control bus and the second processing circuit from the control bus respectively, whereby no control signal is provided via the control bus; responsive to a failure of the first system controller, the second system controller provides the second plurality of control signals to the second system via the second bus and the first plurality of control signals to the first system via the control bus and the first bus; and responsive to a failure of the second system controller, the first system controller provides the first plurality of control signals to the first system via the first bus and the second plurality of control signals to the second system via the control bus and the second bus.