Patent ID: 11868746
Assignee: KINAXIS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A computing apparatus comprising:
a processor; and
a memory storing instructions that, when executed by the processor, configure the apparatus to:
execute, by the processor, a first process in parallel with a second process;
with regards to the first process, the apparatus is configured to:
generate, by the processor, a first schema having one or more dropped fields;

with regards to the second process, the apparatus is configured to:
generate, by the processor, a software development kit (SDK) that supports the one or more dropped fields;
generate, by the processor, a second schema having one or more undropped fields; and
compile, by the processor, a third-party code;

after executing both the first process and the second process, the apparatus is configured to:
run, by the processor, the third-party code;
initialize, by the processor, a record layout; and
access, by the processor, one or more high performance fields, one or more regular performance fields, and the one or more dropped fields.