Patent ID: 11894369
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 10:
11. A semiconductor device, comprising:
a substrate;
a plurality of active patterns on the substrate and extending in a first direction;
a plurality of gate structures that are spaced apart from each other in the first direction on the substrate, the plurality of gate structures extending in a second direction intersecting the first direction, and crossing the plurality of active patterns;
a plurality of source/drain patterns on the plurality of active patterns on opposite sides of each gate structure of the plurality of gate structures;
a plurality of first isolation patterns that correspondingly penetrate adjacent gate structures of the plurality of gate structures, the plurality of first isolation patterns being aligned in the first direction; and
a second isolation pattern that extends in the second direction between adjacent source/drain patterns of the plurality of source/drain patterns, and that penetrates at least one gate structure of the plurality of gate structures,
wherein each first isolation pattern of the plurality of first isolation patterns separates two gate structures of the plurality of gate structures such that the two gate structures of the plurality of gate structures are spaced apart from each other in the second direction, and
wherein a bottom surface of the second isolation pattern is substantially coplanar with a bottom surface of one first isolation pattern of the plurality of first isolation patterns.