Patent ID: 11886674
Assignee: LG DISPLAY CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A touch display apparatus comprising:
a device substrate;
a driving transistor on the device substrate, the driving transistor including a semiconductor pattern, a gate electrode, a drain electrode and a source electrode;
a lower planarization layer on the driving transistor;
an upper planarization layer on the lower planarization layer;
a pixel electrode on an emission area of the device substrate, the pixel electrode being on the upper planarization layer;
an intermediate electrode contacting the driving transistor and the pixel electrode, the intermediate electrode being disposed on a surface of the lower planarization layer and below the upper planarization layer;
a bank insulating layer on the device substrate, the bank insulating layer covering an edge of the pixel electrode;
a light-emitting layer on a portion of the pixel electrode which is exposed by the bank insulating layer;
an upper electrode on the light-emitting layer, and including a first electrode region and a second electrode region which is spaced away from the first electrode region, the first electrode region including a portion overlapping the light-emitting layer;
an encapsulating element on the upper electrode;
a first link wire disposed between the device substrate and the bank insulating layer, the first link wire being electrically connected to the first electrode region; and
a second link wire being spaced away from the first link wire, the second link wire being electrically connected to the second electrode region;
a first contact hole that extends fully through the upper planarization layer to expose an upper surface of the lower planarization layer and an upper surface of the first link wire;
a second contact hole that extends fully through the bank insulating layer and overlaps the first contact hole;
wherein the first electrode region extends into the second contact hole and the first contact hole, is in direct contact with the upper surface of the lower planarization layer and is in direct contact with the upper surface of the first link wire;
wherein the first link wire and the second link wire are disposed in a same layer as the intermediate electrode.