Patent ID: 11907831
Assignee: UNIVERSITY OF DAYTON
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An analog neuromorphic circuit that implements a plurality of resistive memories, comprising:
a plurality of input voltages applied to a plurality of inputs of the analog neuromorphic circuit;
a plurality of resistive memories configured to:
provide a conductance to each input voltage applied to each of the inputs of so that each input voltage is multiplied in parallel by the corresponding conductance of each corresponding resistive memory to generate a corresponding current for each input voltage and each corresponding current is added in parallel,
wherein a first conductance of the resistive memories positioned on a first wire and a second conductance of the resistive memories positioned on a second wire are adjusted relative to each other based on a first voltage value associated with a first accumulative current that is conducted by the first wire and a second voltage value associated with a second accumulative current that is conducted by the second wire to obtain a functionality of the analog neuromorphic circuit; and

an output signal that is configured to execute the functionality of the analog neuromorphic circuit that is generated from each of the input voltages multiplied in parallel with each of the corresponding currents for each of the input voltages added in parallel and the adjusted first conductance and second conductance.