Patent ID: 11955095
Assignee: LAPIS TECHNOLOGY CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. The output circuit according to claim 1, comprising:
a second output terminal;
a third node and a fourth node;
a fifth switch which is composed of a second PMOS transistor switch in which a source is connected to the third node and a drain is connected to the second output terminal, and connects the second output terminal and the third node when the fifth switch is turned on, and cuts off connection between the second output terminal and the third node when the fifth switch is turned off;
a sixth switch which is composed of a second NMOS transistor switch in which a source is connected to the fourth node and a drain is connected to the second output terminal, and connects the second output terminal and the fourth node when the sixth switch is turned on and cuts off connection between the second output terminal and the fourth node when the sixth switch is turned off;
a seventh switch that applies the reference power supply voltage to the third node when the seventh switch is turned on and stops application of the reference power supply voltage to the third node when the seventh switch is turned off;
an eighth switch that applies the reference power supply voltage to the fourth node when the eighth switch is turned on and stops application of the reference power supply voltage to the fourth node when the eighth switch is turned off;
a fifth voltage control circuit that is connected to a gate of the fifth switch and controls the fifth switch such that the fifth switch is brought into an on state;
a sixth voltage control circuit that is connected to a gate of the sixth switch and controls the sixth switch such that the sixth switch is brought into an on state;
a third control device that is connected to a gate of the fifth switch and controls the fifth switch such that the fifth switch is brought into an off state;
a fourth control device that is connected to a gate of the sixth switch and controls the sixth switch such that the sixth switch is brought into an off state;
a seventh voltage control circuit that sets the voltage of the source or the drain of the second PMOS transistor switch as a fifth voltage, and controls whether a sixth voltage obtained by shifting the level of the fifth voltage to a high potential side is supplied to a back gate of the second PMOS transistor switch or the reference power supply voltage is supplied to a back gate of the second PMOS transistor switch; and
an eighth voltage control circuit that sets the voltage of the source or the drain of the second NMOS transistor switch as a seventh voltage, and controls whether an eighth voltage obtained by shifting the level of the seventh voltage to a low potential side is supplied to a back gate of the second NMOS transistor switch or the reference power supply voltage is supplied to a back gate of the second NMOS transistor switch,
wherein the positive voltage signal supply circuit controls supply or cut off of the positive voltage signal to the first node or the third node, and
wherein the negative voltage signal supply circuit controls supply or cut off of the negative voltage signal to the second node or the fourth node.