Patent ID: 11869898
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Optics (Instruments)
Classification: CPC H  G | IPC G  H

Claim 1:
2. The array substrate according to claim 1, a first gate line and a second gate line being arranged between two adjacent rows of the sub-pixels; wherein
the compensation blocks and the first gate line are connected with each other to form an integrated structure; and
the sub-pixels comprise thin film transistors and pixel electrodes, the thin film transistors comprise first poles, second poles and gate electrodes, the pixel electrodes are electrically connected with the second poles of the thin film transistors, the gate electrodes of the thin film transistors in the second pixel areas are electrically connected with the second gate lines, and the first poles of the thin film transistors in the second pixel areas are electrically connected with the second data lines, or the first data lines adjacent to the second data lines.