Patent ID: 11876649
Assignee: MARVELL ASIA PTE LTD
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. The equalization circuitry of claim 1 wherein:
at least one of (1) the incoming signals and (2) outputs of at least one of the feed-forward equalization circuitry portion and the decision circuitry portion are configured to be input as at least one of (a) precursors to a feed-forward equalization circuitry portion of a first other interleaved equalization block in the plurality of equalization blocks, (b) post-cursors to a feed-forward equalization circuitry portion of a second other interleaved equalization block in the plurality of equalization blocks, and (c) post-cursors to a decision-feedback equalization circuitry portion of a third other interleaved equalization block in the plurality of equalization blocks.