Patent ID: 11869951
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for forming an integrated chip, the method comprising:
forming a first control-gate stack and a second control-gate stack elongated in parallel with a first axis, wherein the first control-gate stack has a first protrusion protruding towards the second control-gate stack from a first sidewall of the first control-pate stack and has a second protrusion protruding away from the second control-gate stack from a second sidewall of the first control-pate stack, and wherein the first and second protrusions define a pad, overlap with and protrude along a second axis orthogonal to the first axis;
depositing a gate layer over the first and second control-gate stacks; and
patterning the gate layer to form an erase gate and a word line respectively on opposite sides of the first control-gate stack, wherein a sidewall of the word line has a first indent receiving and conforming to the first protrusion, and
wherein a sidewall of the erase gate has a second indent receiving and conforming to the second protrusion; wherein the pad is between the erase gate and the word line along the second axis, wherein the first sidewall of the first control-pate stack faces and borders the sidewall of the word line, wherein the second sidewall of the first control-pate stack faces and borders the sidewall of the erase pate, and wherein the first and second sidewalls of the first control-pate stack extend linearly and continuously from the pad to a second pad with a constant separation between the first and second sidewalls.