Patent ID: 11889210
Assignee: STMICROELECTRONICS (GRENOBLE 2) SAS
Field: Audio-visual technology (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. An electronic device, comprising:
a first array of image pixels having inputs coupled to first selection tracks and outputs coupled to first output tracks;
at least one second array of test pixels having inputs coupled to second selection tracks and outputs coupled to the first output tracks;
at least one third array of test pixels having inputs coupled to the first selection tracks and outputs coupled to second output tracks; and
a processor coupled to receive output signals on the first and second output tracks;
wherein each test pixel of the second and third arrays is configured to generate the output signal at one of only two possible values set by a circuit connection of the test pixel in the absence of a selection track defect or output track defect; and
wherein the processor is configured to identify existence of the selection track defect or output track defect in response to the output signal received from one or a plurality of the test pixels having a value other than said one of the two possible values set by the circuit connection;
wherein each test pixel comprises a first MOS transistor having a drain coupled to an input node, a source coupled to a second node, and a gate coupled to one of the selection tracks, a second MOS transistor having a drain coupled to a high reference voltage, a source coupled to the second node, and a gate coupled to a reset signal track, a first follower coupled to the second node and configured to replicate a voltage on the second node towards an output of the first follower, and a third transistor having a drain coupled to the output of the second follower, a source coupled to a read output, and a gate coupled to a readout signal track; and
wherein each image pixel comprises a photodiode, a fourth MOS transistor having a drain coupled to the anode or the cathode of the photodiode, a source coupled to a third node, and a gate coupled to one of the selection tracks, a fifth MOS transistor having a drain coupled to the high reference voltage, a source coupled to the third node, and a gate coupled to a reset signal track, a second follower coupled to the third node and configured to replicate a voltage on the third node towards an output of the second follower, and a sixth transistor having a drain coupled to the output of the second follower, a source coupled to a read output, and a gate coupled to a readout signal track.