Patent ID: 11953966
Assignee: META PLATFORMS TECHNOLOGIES, LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. A method, comprising:
receiving, by a clock gate controller in a clock distribution network, a root clock signal to be distributed to a plurality of processing elements in a systolic array, wherein the plurality of processing elements is arranged in at least two dimensions, a first dimension corresponding to rows, and a second dimension corresponding to columns, and wherein inputs to the systolic array include a separate input stream of input values at each column;
passing, by the clock gate controller, the root clock signal as a gated clock signal from which local clock signals are derived for processing elements in a first column of the systolic array;
checking, by the clock gate controller at each clock cycle, whether a most recent value input to the first column from a corresponding input stream is zero, and
disabling, by the clock gate controller, the gated clock signal based on detecting that the most recent value input to the first column is zero.