Patent ID: 11949019
Assignee: ZINITE CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 21:
22. A vertical thin film transistor comprising:
a substantially planar substrate;
an insulating layer formed on the substrate;
a drain formed on the insulating layer;
a second insulating layer formed on the drain and forming a vertical well having an inner surface extending upward from the drain;
an n-type semiconductor material formed on inner surface of the well and the drain;
a gate dielectric layer formed over the n-type semiconductor material;
a gate formed over the dielectric layer; and
a source and a source-channel interfacial member formed on the second insulating layer, the source-channel interfacial member electrically connecting the source to the n-type semiconductor material wherein, when the transistor is in an on state current can flow from the source to the drain through the source-channel interfacial member and through a channel formed in the n-type semiconductor material.