Patent ID: 11935873
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of inspection of a semiconductor package, the method comprising:
preparing a first semiconductor chip including a first lower chip pad, a second lower chip pad and an upper dummy pad;
placing a second semiconductor chip including a lower dummy pad on the first semiconductor chip; and
measuring an alignment accuracy between the first semiconductor chip and the second semiconductor chip,
wherein the first and second lower chip pads are located on a bottom surface of the first semiconductor chip and spaced apart from each other,
wherein the upper dummy pad is located on a top surface of the first semiconductor chip and connected to the second lower chip pad,
wherein the lower dummy pad is located on a bottom surface of the second semiconductor chip and connected to the first lower chip pad, and
wherein measuring the alignment accuracy includes measuring whether the lower dummy pad and the upper dummy pad are electrically connected.