Patent ID: 11882701
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 4:
5. A semiconductor device comprising:
a substrate having a cell region and a connection region adjacent to the cell region;
a lower stack structure including a plurality of lower insulating layers and a plurality of lower conductive layers, the plurality of lower insulating layers and the plurality of lower conductive layers being alternately stacked on each other on the substrate, each of the plurality of lower conductive layers including,
a lower gate electrode portion in the cell region, and
a lower extension line portion in the connection region, the lower extension line portion extending from the lower gate electrode portion;
an upper stack structure including a plurality of upper insulating layers and a plurality of upper conductive layers, the plurality of upper insulating layers and the plurality of upper conductive layers alternately stacked on each other on the lower stack structure, each of the plurality of upper conductive layers including,
an upper gate electrode portion in the cell region, and
an upper extension line portion in the connection region, the upper extension line portion extending from the upper gate electrode portion;
a channel structure passing through the upper stack structure and the lower stack structure; and
at least one middle spacer structure in the connection region, the middle spacer structure including a dummy conductive layer, the dummy conductive layer including at least one dummy extension line portion, the at least one dummy extension line portion being between the upper stack structure and the lower stack structure, the middle spacer structure being in contact with a side surface of at least one of the plurality of lower insulating layers or the plurality of upper insulating layers,
wherein a first distance between lower extension line portions of two neighboring ones of the plurality of lower conductive layers, a second distance between upper extension line portions of two neighboring ones of the plurality of upper conductive layers, a third distance between an uppermost surface of the plurality of lower conductive layers and a lowermost surface of the at least one dummy extension line portion, and a fourth distance between a lowermost surface of the plurality of upper conductive layers and an uppermost surface of the at least one dummy extension line portion are substantially equal to each other.