Patent ID: 11894850
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 7:
8. The delay circuit according to claim 6,
wherein a gate of the first NMOS is connected to a gate of the second NMOS, a source of the first NMOS is grounded, a drain of the first NMOS and the connected gates of the first NMOS and the second NMOS receive the zero temperature coefficient current;
wherein a source of the second NMOS is grounded, the drain of the second NMOS is connected to a drain and a gate of the PMOS, respectively, and wherein the commonly connected gates of the first NMOS and the second NMOS output the negative temperature coefficient voltage; and
wherein a source of the PMOS is connected to a preset voltage, and wherein a gate of the PMOS outputs the positive temperature coefficient voltage.