Patent ID: 11868163
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G  H

Claim 14:
15. A configurable circuit, comprising:
a configurable computation circuit;
a plurality of synchronous network inputs coupled to a synchronous network and to the configurable computation circuit;
a plurality of synchronous network outputs coupled to the synchronous network and to the configurable computation circuit;
an asynchronous network input queue coupled to an asynchronous packet network;
an asynchronous network output queue coupled to the asynchronous packet network;
a configuration memory coupled to the configurable computation circuit, to the plurality of synchronous network inputs, and to the plurality of synchronous network outputs, the configuration memory comprising:
a first instruction memory configured to store a first plurality of data path configuration instructions to configure an internal data path of the configurable computation circuit; and
a second instruction memory configured to store a second plurality of data path configuration instructions or instruction indices for selection of a master synchronous network input of the plurality of synchronous network inputs for receipt of a current data path configuration instruction or instruction index from an adjacent configurable circuit;, and
a control circuit coupled to the configurable computation circuit, the control circuit comprising:
a plurality of control registers configured to store a completion table having a plurality of thread identifiers and a loop count of an active number of loop threads, the plurality of control registers further configured to store a thread identifier pool having a predetermined number of thread identifiers of the plurality of thread identifiers; and
a thread control circuit configured, in response to receipt of an asynchronous packet network message returning a thread identifier of the plurality of thread identifiers to the thread identifier pool, to decrement the loop count and, when the loop count reaches zero, to generate an asynchronous packet network completion message for transmission on the asynchronous packet network from the asynchronous network output queue.