Patent ID: 11968844
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A memory device, comprising:
a transistor, disposed on a substrate; and
an interconnect structure, overlying the transistor, wherein the interconnect structure comprises:
a bit line extending along a first direction;
a source line extending along a second direction perpendicular to the first direction; and
a memory cell vertically disposed between the bit line and the source line, wherein the transistor is configured to control a write signal flowing between the bit line and a source of the transistor, and control a read signal flowing between the bit line and a drain of the transistor, wherein the source line is directly under the memory cell, wherein the memory cell comprises:
a selector, electrically coupled to the source of the transistor through the source line;
a magnetic tunnel junction (MTJ) structure, disposed on the selector and electrically coupled to the drain of the transistor; and
a spin orbit torque (SOT) layer, disposed between the selector and the MTJ structure, and electrically coupled to the bit line.