Patent ID: 11869939
Assignee: SONY GROUP CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC B  H

Claim 3:
4. A semiconductor device comprising:
a nanowire stack disposed above a substrate, the nanowire stack including vertically-stacked nanowires;
a gate structure wrapped around each of the nanowires to define a channel region of the device, the gate structure including gate sidewalls;
a pair of source/drain regions on opposite sides of the channel region;
an internal spacer arranged along at least a portion of one of the gate sidewalls between two adjacent ones of the nanowires; and
a pair of external spacers on the portion of one of the gate sidewalls external to the nanowire stack, wherein
the external spacers have a first thickness normal to the surface of the one of the gate sidewalls, wherein the internal spacer has a second thickness normal to the surface of one of the gate sidewalls, and wherein the second thickness is equal to the first thickness.