Patent ID: 11935597
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A semiconductor device comprising:
a first structure including a semiconductor substrate having a first surface and a second surface opposing each other, a front side structure on the first surface of the semiconductor substrate, a back side structure below the second surface of the semiconductor substrate and a through-electrode structure including a portion penetrating through the semiconductor substrate; and
a second structure disposed on the first structure and including gate layers, stacked in a vertical direction, and a vertical memory structure penetrating through the gate layers, wherein:
the front side structure includes a first circuit device, including a first gate structure including a gate dielectric layer and a gate electrode stacked in order and a first source/drain region, and an internal input/output conductive pattern having a portion disposed on the same level as at least a portion of the gate electrode,
the back side structure includes a back side insulating layer below the second surface of the semiconductor substrate and an external input/output conductive pattern below the back side insulating layer,
the through-electrode structure includes a through-electrode, electrically connected to the external input/output conductive pattern and the internal input/output conductive pattern, and an insulating spacer on a side surface of the through-electrode,
each of the gate electrode and the internal input/output conductive pattern includes
a lower conductive pattern, and
an upper conductive pattern on the lower conductive pattern,

the front side structure includes
a gate capping pattern on the gate electrode,
a pad capping pattern on the internal input/output conductive pattern,
lower interconnections including an input/output connection wiring and a circuit wiring disposed on the same height level, and
an input/output connection contact plug electrically connecting the input/output connection wiring and the internal input/output conductive pattern to each other between a portion of the input/output connection wiring, overlapping the internal input/output conductive pattern, and the internal input/output conductive pattern,

a thickness of the gate capping pattern is substantially the same as a thickness of the pad capping pattern, and
the input/output connection contact plug penetrates through the pad capping pattern.