Patent ID: 11869616
Assignee: CYPRESS SEMICONDUCTOR CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A method, comprising:
performing, by a built-in self-test (BIST) unit of a memory device, a memory test on one or more memory banks of the memory device using a first algorithm;
generating, by the BIST unit, miscompare results responsive to performing the memory test on the one or more memory banks of the memory device;
determining, by the BIST unit, failure diagnostic information based on the miscompare results;
generating, by the BIST unit, an error packet comprising the failure diagnostic information and the miscompare results;
determining, by the BIST unit, that the first algorithm was used to perform the memory test associated with the error packet;
tagging, by the BIST unit, the error packet with an identifier to the first algorithm to generate a tagged error packet; and
placing, by the BIST unit, the tagged error packet in a queue of a plurality of error packets to generate a queued error packet.