Patent ID: 11955191
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 17:
18. A memory device, comprising:
a plurality of memory cells arranged along a column of a memory array;
wherein each of the plurality of memory cells comprises N cell-rows, each of the N cell-rows comprising a first transistor, a second transistor, N third transistors, a diode-connected transistor, N being a positive integer;
wherein the N cell-rows are commonly connected to a capacitor;
wherein, within each of the N cell-rows, the first transistor, the second transistor, the N third transistors, and the diode-connected transistor are connected in series, with one terminal of the capacitor connected to a node between the second transistor and the third transistor; and
wherein the other terminal of the capacitor is connected to a bit line (BL) configured to provide a programming voltage.