Patent ID: 11901009
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 7:
8. The address decoding circuit of claim 6, further comprising a second NOR gate, second inverters, and first transmission gates; wherein
the first transmission gates have one-to-one correspondence with the block address input signals, an input end of each first transmission gate is connected to a corresponding block address input signal, and an output end of the first transmission gate is configured to output the block address input signal;
at least one block address input signal is connected to a first input end of the second NOR gate, a second input end of the second NOR gate is connected to the enable signal, and an output end of the second NOR gate is configured to output the inverted signal of the block address input signal when the enable signal is not activated, and output a fixed signal when the enable signal is activated;
the second inverters have one-to-one correspondence with the remaining block address input signals, an input end of each second inverter is connected to a corresponding block address input signal, and an output end of the second inverter is configured to output the inverted signal of the block address input signal.