Patent ID: 11862237
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 4:
5. The memory of claim 4, wherein the bit-line write circuit comprises a first transistor and a second transistor;
wherein the first transistor is turned on in response to the low write control signal, and the second transistor is turned on in response to the high write control signal, and wherein a source of the first transistor is coupled to a power terminal, a drain of the first transistor is coupled to a drain of the second transistor, a source of the second transistor is grounded, and a gate of the first transistor is connected to a gate of the second transistor and is coupled to the first AND gate; or
wherein the first transistor and the second transistor are turned on in response to the low write control signal, and wherein the source of the first transistor is coupled to the power terminal, the drain of the first transistor is coupled to the plurality of bit lines, the source of the second transistor is coupled to the complementary bit line, the drain of the second transistor is grounded, and the gate of the first transistor is connected to the gate of the second transistor and is coupled to the first AND gate; or
wherein the first transistor and the second transistor are turned on in response to the high write control signal, and wherein the drain of the first transistor is coupled to the power terminal, the source of the first transistor is coupled to the plurality of bit lines, the drain of the second transistor is coupled to the complementary bit line, the source of the second transistor is grounded, and the gate of the first transistor is connected to the gate of the second transistor and is coupled to the first AND gate.