Patent ID: 11962318
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 4:
5. The ADC of claim 4 configured to operate in a delay- calibration mode, a memory-calibration mode, and a mission mode, wherein the delay-calibration mode includes a plurality of cycles, and in a cycle of the plurality of cycles:
the calibration circuit is configured to modify the delay value of a first delay block in the first stage;
the calibration circuit is configured to generate the plurality of input codes;
the VD block is configured to generate a plurality of delay signals in response to the plurality of input codes;
the first stage is configured to generate a digital code in response to the plurality of delay signals; and
the accumulator is configured to determine the error count of the first stage, in which the error count is an absolute difference in a number of ones and zeroes in the digital code.