Patent ID: 11942364
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A method of forming an interconnect, comprising:
forming an etch stop structure over a lower conductive structure;
forming one or more dielectric layers over the etch stop structure;
performing a first patterning process on the one or more dielectric layers to form an interconnect opening;
forming a protective layer on one or more sidewalls of the one or more dielectric layers that form the interconnect opening, the protective layer being formed by a selective deposition process that deposits the protective layer to have an opening between sidewalls of the protective layer, the opening exposing the etch stop structure;
performing a second patterning process to remove a part of the etch stop structure that is laterally between the sidewall of the protective layer; and
forming a conductive material within the interconnect opening.