Patent ID: 11886536
Assignee: IMAGINATION TECHNOLOGIES LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. The system of claim 8, wherein in a first hardware pass of the system the one or more convolution engines are configured to generate a first subset of the sub-output tensors from a first subset of the plurality of sub-filters and the interleave engine is configured to generate a first set of blocks of the final output tensor by interleaving the output elements of the first subset of the sub-output tensors; and in a second hardware pass of the system the one or more convolution engines are configured to generate a second subset of the sub-output tensors from a second subset of the plurality of sub-filters and the interleave engine is configured to generate a second set of blocks of the final output tensor by interleaving the output elements of the second subset of the sub-output tensors.