Patent ID: 11894300
Assignee: SK HYNIX INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A semiconductor memory device, comprising:
a source structure;
a stacked conductive layer overlapping with the source structure;
a first select conductive layer and a second select conductive layer disposed between the source structure and the stacked conductive layer;
a stacked insulating layer disposed between the first select conductive layer and the stacked conductive layer and between the second select conductive layer and the stacked conductive layer;
a first slit structure and a second slit structure passing through the stacked conductive layer and the stacked insulating layer, and spaced apart from each other in a first direction; and
a separation insulating structure disposed between the first and second slit structures,
wherein the first and second select conductive layers are spaced apart from each other due to the first slit structure, the second slit structure, and the separation insulating structure, and
wherein a width of the separation insulating structure is greater than widths of the first and second slit structures.