Patent ID: 11941300
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. An apparatus, comprising:
a memory device; and
a controller coupled with the memory device and configured to cause the apparatus to:
receive a plurality of write commands for a set of physical addresses of a non-volatile memory device;
determine whether the set of physical addresses are consecutively indexed based at least on receiving the plurality of write commands;
generate a pivot table to be included in a first subset of a mapping based at least in part on the set of physical addresses being consecutively indexed, the mapping comprising the first subset, a second subset, and a third subset;
set, based at least in part on generating the pivot table, a flag in an entry of the first subset of the mapping, the entry of the first subset comprising at least a portion of the pivot table associated with the set of physical addresses; and
output data to the set of physical addresses based at least in part on setting the flag.