Patent ID: 11916110
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 9:
10. A method for forming a semiconductor device structure, comprising:
forming a sacrificial gate structure over a portion of a fin structure having a stack of semiconductor layers, wherein the stack of semiconductor layers comprises silicon-containing layers and germanium-containing layers alternatingly arranged, and at least some germanium-containing layers of the stack of the semiconductor layers have a first germanium atomic percentage, and at least some germanium-containing layers of the stack of the semiconductor layers have a second germanium atomic percentage greater than the first germanium atomic percentage;
removing the silicon-containing layers and the germanium-containing layers not covered by the sacrificial gate structure;
forming an epitaxial source/drain feature in regions where the silicon-containing layers and the germanium-containing layers were removed;
removing portions of the sacrificial gate structure to expose the silicon-containing layers and the germanium-containing layers;
selectively removing portions of the germanium-containing layers so that at least one germanium-containing layer remaining between two adjacent silicon-containing layers has a height and the two adjacent silicon-containing layers have a width that is greater than the height; and
forming a gate electrode layer over exposed surfaces of the silicon-containing layers and the germanium-containing layers.