Patent ID: 11955471
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 8:
9. An integrated circuit comprising:
a first active region and a second active region, each extending on a substrate in a first horizontal direction in parallel to each other, wherein the first active region and the second active region have conductivity types different from each other;
a first gate line extending in a second horizontal direction that crosses the first horizontal direction, the first gate line comprising a first partial gate line and a second partial gate line, wherein the first partial gate line forms a first transistor with the first active region and the second partial gate line forms a second transistor with the second active region;
a second gate line extending in the second horizontal direction and comprising a third partial gate line and a fourth partial gate line, wherein the third partial gate line forms a third transistor with the first active region and the fourth partial gate line forms a fourth transistor with the second active region;
a third gate line extending in the second horizontal direction between the first and second gate lines;
a first jumper electrically interconnecting, on the first active region, a drain region of the first transistor and a drain region of the third transistor to the third gate line;
a second jumper electrically interconnecting, on the second active region, a drain region of the second transistor and a drain region of the fourth transistor to the third gate line; and
a gate contact,
wherein the third gate line comprises a fifth partial gate line electrically connected to the first jumper and a sixth partial gate line electrically connected to the second jumper, and
wherein the gate contact has a bottom surface connected to the fifth and sixth partial gate lines and extending in the second horizontal direction.