Patent ID: 11864383
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 17:
18. A vertical-type memory device, comprising:
a lower substrate;
circuit devices on the lower substrate;
an upper substrate on the lower substrate and the circuit devices;
a plurality of gate electrodes stacked on the upper substrate;
a channel layer that penetrates the plurality of gate electrodes in a first direction, perpendicular to an upper surface of the upper substrate;
a liner comprising a semiconductor material that is in contact with an upper internal side wall of the channel layer and includes n-type impurities;
a first filling layer that at least partially fills an internal space of the channel layer below the liner; and
a pad on the liner and in contact with the liner,
wherein each of a bottom surface of the liner and a bottom surface of the pad is convexly rounded toward the upper surface of the upper substrate,
wherein a top of the channel layer is on a substantially same level as a top of the liner,
wherein the bottom surface of the liner is lower than a lower surface of an uppermost first gate electrode among the plurality of gate electrodes and is higher than an upper surface of a second gate electrode directly below the first gate electrode.