Patent ID: 11876025
Assignee: NANYA TECHNOLOGY CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. A semiconductor structure, comprising:
a wafer; and
a test structure, disposed on the wafer and comprising:
a first source/drain layer;
a second source/drain layer; and
a gate layer, which has a T-shaped configuration, having a first portion and a second portion, the first portion disposed above the first source/drain layer, and the second portion disposed above the second source/drain layer, wherein the first portion has two free ends and has a uniform width between the two free ends thereof, wherein the second portion has a connecting end and an opposed free end, and has a uniform width between the connecting end and the free end;
wherein the first source/drain layer is disposed between two free ends of the first portion of the gate layer;
wherein the second source/drain layer is disposed between the connecting end and the free end of the second portion of the gate layer;
wherein the first portion is disposed along a first direction and the second portion is disposed along a second direction orthogonal to the first direction, wherein the connecting end of the second portion is integrated with a mid-portion of the first portion between the two free ends thereof to form the T-shaped configuration;
a third source/drain layer, disposed adjacent to the first source/drain layer, wherein the first source/drain layer, the second source/drain layer, and the third source/drain layer are spaced apart from each other and are independent from each other;
wherein the first portion of the gate layer is disposed above the third source/drain layer at a position that the third source/drain layer is disposed between the two free ends of the first portion of the gate layer.