Patent ID: 11892955
Assignee: MICROCHIP TECHNOLOGY INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. A compute express link (CXL) memory controller comprising:
read bypass detection logic to receive a plurality of CXL flits from a CXL physical layer of a CXL memory controller and to analyze each of the received plurality of CXL flits to identify a bypass memory read request from the plurality of CXL flits;
a read request bypass path comprising the read bypass detection logic, the read request bypass path connecting the CXL physical layer to a transaction/application layer of the CXL memory controller, the read request bypass path bypassing an arbitration/multiplexing layer of the CXL memory controller and a link layer of the CXL memory controller;
the transaction/application layer to:
generate a memory read command on an interface of a memory device associated with the CXL memory controller in response to the bypass memory read request received at the transaction/application layer when a read request queue is empty;
receive read data from the memory device in response to the memory read command; and
forward the read data received at the transaction/application layer to the link layer when there is a link layer memory read request at the transaction/application layer that matches the bypass memory read request that generated the memory read command.