Patent ID: 11967833
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  B | IPC G  H

Claim 14:
15. The method for controlling the memory device according to claim 1, further comprising
a plurality of first dummy word lines electrically connected between the first drain side selective transistor and the first source side selective transistor,
a plurality of second dummy word lines electrically connected between the second drain side selective transistor and the second source side selective transistor, wherein
the first erase operation includes
applying a first voltage to the first source side select gate line,
applying a second voltage to the second source side select gate line,
applying a third voltage to the source line,
applying a fourth voltage to one of the first word lines,
applying a fifth voltage to one of the second word lines,
applying a sixth voltage to one of the first dummy word lines,
applying a seventh voltage to one of the second dummy word lines,
the first voltage is lower than the third voltage,
the sixth voltage is lower than the first voltage, and
the fourth voltage is lower than the sixth voltage.