Patent ID: 11967365
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. A method comprising:
providing a bitcell architecture with transistor logic and passgates, wherein the transistor logic is configured to store data, wherein the passgates are configured to access the data stored in the transistor logic, wherein the passgates include a first write passgate and a second write passgate with outputs coupled together, wherein the passgates include a third write passgate and a fourth write passgate with outputs coupled together, wherein the wordlines include first write wordlines coupled to the first write passgate, wherein the wordlines include second write wordlines coupled to the second write passgate, wherein the wordlines include third write wordlines coupled to the third write passgate, and wherein the wordlines include fourth write wordlines coupled to the fourth write passgate;
reducing a number of the transistors in the transistor logic so as to reduce a layout area associated with fabricating the bitcell architecture; and
reducing a number of wordlines and bitlines coupled to the transistor logic so as to reduce a number of metal structures associated with fabricating the bitcell architecture.