Patent ID: 11935951
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A device comprising:
a first gate stack disposed over a first fin structure;
a first source/drain feature disposed on the first fin structure, wherein the first source/drain feature is formed of a first semiconductor material that includes a first-type dopant;
a first passivation material layer disposed within the first fin structure and interfacing with a first side and a second side of the first source/drain feature, the first side of the first source/drain feature being opposite the second side of the first source/drain feature, the first passivation material layer formed of a second semiconductor material that includes a second-type dopant, the second-type being opposite the first-type, wherein the second semiconductor material that includes the second-type dopant interfaces with the first semiconductor material that includes the first-type dopant of the first source/drain feature; and
a second source/drain feature disposed in the first fin structure, the second source/drain feature including a first portion extending from the first passivation material layer that is interfacing with the first source/drain feature to under the first gate stack.