Patent ID: 11862712
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A method of semiconductor device fabrication, comprising:
forming a first fin structure and a second fin structure extending from a substrate and having an isolation region interposing the first fin structure and the second fin structure;
forming a gate structure over each of the first fin structure and the second fin structure;
forming a source/drain feature adjacent the gate structure, wherein the forming the source/drain feature includes:
growing a first epitaxial feature having a first portion over the first fin structure and a second portion over the second fin structure, wherein the growing the first epitaxial feature includes growing a first silicon phosphorous (SiP) epitaxial feature using an N2 carrier gas;
growing a second silicon phosphorous (SiP) epitaxial feature over the first and second portions of the first epitaxial feature wherein the growing the second SiP epitaxial feature uses an H2 carrier gas, wherein the second silicon phosphorous epitaxial feature includes a merged portion between the first fin structure and the second fin structure; and
growing a third epitaxial feature over the second SiP epitaxial feature; and
forming a contact element to the third epitaxial feature.