Patent ID: 11860786
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A cache system, comprising:
a first cache;
a second cache;
a register configured to store a configurable data bit; and
a logic circuit, configured to:
select the first cache for use by a processor, based on the configurable data bit being in a first state, when an execution-type signal line receives an indication of a first type of execution;
select the second cache for use by the processor, based on the configurable data bit being in the first state, when the execution-type signal line receives an indication of a second type of execution;
select the second cache for use by the processor, based on the configurable data bit being in a second state, when the execution-type signal line receives an indication of the first type of execution; and
select the first cache for use by the processor, based on the configurable data bit being in the second state, when the execution-type signal line receives an indication of the second type of execution.