Patent ID: 11942474
Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 1:
2. The method according to claim 1, wherein,
the first electronically conductive channel vertically extends along the sidewall of the isolation layer on the substrate, and occupies a first range in a circumferential direction of the active region, and those of the source/drain layers in contact with the first electronically conductive channel pass through the isolation layer at the first range to expose;
the second electronically conductive channel vertically extends along the sidewall of the isolation layer on the substrate, and occupies a second range different from the first range in the circumferential direction of the active region, and those of the source/drain layers in contact with the second electronically conductive channel pass through the isolation layer at the second range to expose;
the third electronically conductive channel vertically extends along the sidewall of the isolation layer on the substrate, and occupies a third range different from the first range and the second range in the circumferential direction of the active region, and the gate stacks pass through the isolation layer at the third range to expose.