Patent ID: 11894063
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 14:
15. A semiconductor memory device comprising:
a substrate;
a plurality of first conductive layers arranged in a first direction intersecting with a surface of the substrate;
a second conductive layer disposed at a position overlapping with the plurality of first conductive layers viewed from the first direction;
a third conductive layer disposed at a position overlapping with the plurality of first conductive layers viewed from the first direction, the third conductive layer being arranged with the second conductive layer in a second direction intersecting with the first direction;
a first semiconductor column extending in the first direction and opposed to the plurality of first conductive layers and the second conductive layer;
a first gate insulating film disposed between the plurality of first conductive layers and the first semiconductor column, the first gate insulating film being separated from the third conductive layer in the second direction and including a first electric charge accumulating layer;
a second semiconductor column extending in the first direction and opposed to the plurality of first conductive layers and the third conductive layer;
a second gate insulating film disposed between the plurality of first conductive layers and the second semiconductor column, the second gate insulating film being separated from the second conductive layer in the second direction and including a second electric charge accumulating layer;
a third electric charge accumulating layer disposed between the second conductive layer and the third conductive layer;
a first insulating layer disposed between the second conductive layer and the third electric charge accumulating layer; and
a second insulating layer disposed between the third conductive layer and the third electric charge accumulating layer, wherein
a part of an outer peripheral surface of the first semiconductor column is opposed to the second conductive layer, and another part of the outer peripheral surface of the first semiconductor column is opposed to the third electric charge accumulating layer without via the second conductive layer, and
a part of an outer peripheral surface of the second semiconductor column is opposed to the third conductive layer, and another part of the outer peripheral surface of the second semiconductor column is opposed to the third electric charge accumulating layer without via the third conductive layer.