Patent ID: 11967619
Assignee: TELEDYNE SCIENTIFIC & IMAGING, LLC
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A field-effect transistor (FET), comprising:
a substrate;
source and drain electrodes on the substrate;
a channel layer;
a gate electrode structure comprising:
a gate electrode in contact with the channel layer, wherein the gate electrode has a surface proximal to either the source or the drain electrode; and
a first lateral field plate adjacent to the gate electrode;

a first dielectric layer disposed between the first lateral field plate and the channel layer; and
a dielectric structure buried in the substrate remote from the gate electrode structure;
wherein the first lateral field plate is in contact with the first dielectric layer and is configured to modulate an electric field proximal to the gate electrode proximal to at least one of or both the drain or source electrodes; and
wherein the gate electrode and the first lateral field plate comprise top and bottom portions, wherein the bottom portions of the gate electrode and the first lateral field plate are buried in an aperture defined in the substrate to a depth extending to the channel layer and the top portions of the gate electrode and the first lateral field plate extend above a surface of the substrate.