Patent ID: 11871555
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 5:
6. A semiconductor structure, formed by the method for forming the semiconductor structure of claim 1, wherein the semiconductor structure comprises:
the semiconductor substrate, having the plurality of separate active areas that are isolated from each other by the shallow trench isolation areas; and
the word lines located in the trenches comprising the first trenches and the second trenches, wherein the word lines comprise the first word lines and the second word lines, the first word lines are located in the first trenches in the active areas, the second word lines are located in the second trenches in the shallow trench isolation areas, and the first word lines have the width greater than the width of the second word lines,
wherein the first trenches have the width greater than the width of the second trenches.