Patent ID: 11894850
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 3:
4. The delay circuit according to claim 3, wherein the first power supply control unit comprises a third transistor, wherein a channel type of the third transistor and the channel type of the first transistor are same, and wherein a source of the third transistor is connected to the first power supply control unit, wherein a drain of the third transistor is connected to the source of the first transistor, and wherein a gate of the third transistor receives the first power supply control signal;
wherein the second power supply control unit comprises a fourth transistor, wherein a channel type of the fourth transistor and the channel type of the second transistor are same, wherein a source of the fourth transistor is grounded, and wherein a drain of the fourth transistor is connected to the source of the second transistor, and wherein the gate of the fourth transistor receives the second power supply control signal.