Patent ID: 11922108
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 2:
3. The method of claim 2, wherein the generating the layout design of the memory cell array further comprises:
generating a fifth set of conductive feature layout patterns extending in the first direction, the fifth set of conductive feature layout patterns being located on the second layout level, the fifth set of conductive feature layout patterns being separated from the fourth set of conductive feature layout patterns in the second direction, the fifth set of conductive feature layout patterns corresponding to fabricating a second portion of the second bit line;
generating a second set of via layout patterns, the second set of via layout patterns being located between the second layout level and the first layout level, and the second set of via layout patterns corresponding to fabricating vias coupled between the first portion of the second bit line and the second portion of the second bit line.