Patent ID: 11862232
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 3:
4. The circuit for data transmission of claim 3, wherein the first class mode register read-write module further comprises a fifth mode register read-write module, a sixth mode register read-write module, a seventh mode register read-write module, and an eighth mode register read-write module; the first logic gate unit further comprises a fifth OR gate and a sixth OR gate; the second logic gate unit comprises a seventh OR gate and an eighth OR gate;
the fifth OR gate is configured such that: a first input end is electrically connected to the fifth mode register read-write module, and a second input end is electrically connected to the sixth mode register read-write module;
the sixth OR gate is configured such that: a first input end is electrically connected to the seventh mode register read-write module, and a second input end is electrically connected to the eighth mode register read-write module;
the seventh OR gate is configured such that: a first input end is electrically connected to an output end of the fifth OR gate, and a second input end is electrically connected to an output end of the fourth OR gate; and
the eighth OR gate is configured such that: a first input end is electrically connected to an output end of the sixth OR gate, a second input end is electrically connected to an output end of the seventh OR gate, and an output end is electrically connected to the first cache module.