Patent ID: 11968634
Assignee: QUALCOMM INCORPORATED
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 20:
21. A wireless communication device comprising:
a memory;
a transceiver; and
at least one processor coupled to the memory and the transceiver, wherein the wireless communication device is configured to:
receive a synchronization signal block (SSB) transmission schedule, the SSB transmission schedule including a first frequency resource at least partially overlapping with an uplink (UL) frequency portion of a full-duplex slot;
receive one or more SSBs in at least a slot different than the full-duplex slot or in a downlink (DL) frequency portion of the full-duplex slot; and
receive an indicator indicating a direction for frequency shifting the first frequency resource of the SSB transmission schedule to a second frequency resource not overlapping with the UL frequency portion of the full-duplex slot.