Patent ID: 11864382
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 19:
20. A three-dimensional semiconductor memory device, comprising:
a substrate including a cell array region and a connection region;
an electrode structure including a plurality of electrodes vertically stacked on the substrate;
a plurality of first vertical channels that penetrate the electrode structure on the cell array region; and
a plurality of second vertical channels that penetrate the electrode structure on the connection region,
wherein each of the plurality of first vertical channels and each of the plurality of second vertical channels includes a lower channel pattern in direct contact with the substrate and an upper channel pattern connected to the lower channel pattern and a sidewall of the second lower channel pattern is spaced apart from the substrate,
wherein a lowermost electrode of the plurality of electrodes surrounds the lower channel pattern of each of the plurality of first vertical channels and the upper channel pattern of each of the plurality of second vertical channels,
wherein top surfaces of the lower channel pattern of each of the plurality of second vertical channels are positioned at a lower level than a bottom surface of the lowermost electrode,
wherein the top surfaces of each of the plurality of lower channel patterns of the second vertical channels are positioned at a lower level than a top surface of the substrate, and
wherein each of the lower channel patterns of the first and second vertical channels comprises a pillar-shaped epitaxial pattern directly contacting the substrate.