Patent ID: 11942162
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. The memory device of claim 9, wherein:
the voltage generating circuit includes a first voltage terminal, a second voltage terminal, and a third voltage terminal respectively providing the first voltage, the second voltage, and the third voltage;
the level shifter includes: a first PMOS transistor and a second PMOS transistor, each connected to the third voltage terminal of the voltage generating circuit,
a first NMOS transistor connected to the first voltage terminal and to the first PMOS transistor through a first node, and
a second NMOS transistor connected to the first voltage terminal and to the second PMOS transistor through a second node;

a complementary signal of the control signal is provided to a gate terminal of the first PMOS transistor;
the control signal is provided to a gate terminal of the second PMOS transistor;
a gate terminal of the first NMOS transistor is connected to the second node; and
a gate terminal of the second NMOS transistor is connected to the first node.