Patent ID: 11934824
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 18:
19. A system, comprising:
at least one input device;
at least one output device;
at least one processor device coupled to the input device and the output device; and
at least one memory device coupled to the at least one processor device and comprising:
at least one memory cell array; and
logic coupled to at least one memory array, the logic comprising a sequencer and a sense amplifier array, the logic configured to:
receive, at the sequencer, a first operand;
receive, at the sense amplifier array in a bit-parallel manner, a row of a memory array of the at least one memory cell array;
multiply-shift-accumulate a number of bits of the row of the memory array by a number bits of the first operand to generate a first scaled row;
receive at least one additional operand;
multiply-shift-accumulate the number of bits of the row by bits of the at least one additional operand to generate at least one additional scaled row; and
generate a row of an output matrix based on the first scaled row and at least one additional scaled row.