Patent ID: 11875753
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 2:
3. The display device of claim 1, wherein, in the case where the display panel is the dead space reduced display panel, the address line memory stores a value of (N+K) as a (2K−1)-th address of the first through (2N)-th addresses, stores a value of (N−K+1) as a (2K)-th address of the first through (2N)-th addresses, stores a value of (2N+K) as a (2N+2K−1)-th address of the (2N+1)-th through (4N)-th addresses, and stores a value of (4N−K+1) as a (2N+2K)-th address of the (2N+1)-th through (4N)-th addresses, where K is an integer greater than 0 and less than or equal to N, and the controller outputs (N+K)-th pixel data and (N−K+1)-th pixel data of the first through (2N)-th pixel data as the output image data in response to the first through (2N)-th addresses having the value of (N+K) and the value of (N−K+1), and outputs (2N+K)-th pixel data and (4N−K+1)-th pixel data of the (2N+1)-th through (4N)-th pixel data as the output image data in response to the (2N+1)-th through (4N)-th addresses having the value of (2N+K) and the value of (4N−K+1).