Patent ID: 11966480
Assignee: NVIDIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. An accelerator circuit comprising:
a secure memory;
a scheduler circuit; and
a direct memory access (DMA) circuit coupled to the scheduler circuit and the secure memory, wherein the DMA circuit comprises a cryptographic circuit that implements an authenticated encryption algorithm to encrypt retrieved data from the secure memory or decrypt received data to be stored in the secure memory,
wherein the scheduler circuit is to:
receive, from a first application, a first descriptor of a first data transfer of a first size, the first descriptor specifying a first index in the secure memory corresponding to the first application; and
split the first data transfer into a first set of portions, each portion being less than or equal to the first size and required to complete execution before a context switch to another application;

wherein the DMA circuit is to:
during a first period, execute a first subset of the first set of portions sequentially using a first initialization vector (IV) and a first encryption key associated with the first application, and store a first computed hash key and a first block counter in the secure memory at the specified first index; and
during a second period subsequent to the first period, execute a second subset of the first set of portions sequentially using the first computed hash key and the first block counter stored in the secure memory at the specified first index, and store a first authentication tag associated with the first data transfer.