Patent ID: 11947798
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus comprising:
a semiconductor memory device configured to carry multiple first stacked memory dies for storing data, the semiconductor memory device comprising:
a memory controller;
two or more memory interfaces;
packet relay logic configured to control the two or more memory interfaces; and
a switch configured to:
receive a packet through a first memory interface of the two or more memory interfaces, the received packet indicating a write request and including data and a physical memory address;
pass the received packet to the memory controller for writing the data to one of the multiple first stacked memory dies at the physical memory address responsive to a determination that the received packet indicates the semiconductor memory device as a destination of the received packet; and
pass the received packet through a second memory interface of the two or more memory interfaces toward another semiconductor memory device for writing the data to one of multiple second stacked memory dies of the other semiconductor memory device at the physical memory address responsive to a determination that the received packet indicates the other semiconductor memory device as the destination of the received packet.