Patent ID: 11954585
Assignee: ZJU-HANGZHOU GLOBAL SCIENTIFIC AND TECHNOLOGICAL INNOVATION CENTER
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. The multi-mode array structure for in-memory computing according to claim 3, wherein when the convolutional neural network (CNN) or the spiking neural network (SNN) operation function is performed, the first transistor, the second transistor, and the differential amplifier are all in the on state; the memory cell is configured to calculate the analogue signal or the pulse signal input from the corresponding function line with a neural network positive or negative weight value set in the memory cell, wherein the memory cell realizes the neural network positive or negative weight value by setting a conductance of the first memristor and the second memristor in the memory cell and setting the first input end of the differential amplifier as a positive input end or a negative input end.