Patent ID: 11921640
Assignee: APPLE INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A system comprising:
one or more processors configured to issue memory requests to access a memory system; and
a cache coupled to the one or more processors and configured to cache data from the memory system for access by one or more processors, wherein the cache comprises a control circuit and wherein:
the control circuit is configured to assign criticality values to cache lines, wherein a given criticality value corresponds to a given cache line;
during selection of a victim cache line for replacement, the cache is configured to preferentially retain cache lines identified as critical by the corresponding criticality values over cache lines not identified as critical, wherein the cache is further configured to select the victim cache line according to replacement data maintained by the cache separate from the criticality values;
the cache is configured to monitor a cache hit rate for cache lines having criticality values indicating critical status;
the control circuit is configured to detect one or more indications that at least some of the cache lines identified as critical are no longer critical, wherein one of the one or more indications is based on the cache hit rate being below a threshold level; and
the control circuit is configured to accelerate eviction of the cache lines identified as critical based on the one or more indications; and

prefetch circuitry configured to prefetch data into the cache.