Patent ID: 11915744
Assignee: SOCIONEXT INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A semiconductor memory device, comprising a 2-port SRAM cell,
wherein the 2-port SRAM cell comprises:
a first transistor having one node connected to a first power source that supplies a first voltage, another node connected to a first node, and a gate connected to a second node;
a second transistor having one node connected to the first power source, another node connected to the second node, and a gate connected to the first node;
a third transistor having one node connected to the first node, another node connected to a second power source that supplies a second voltage different from the first voltage, and a gate connected to the second node;
a fourth transistor having one node connected to the second node, another node connected to the second power source, and a gate connected to the first node;
a fifth transistor having one node connected to a first write-bit line, another node connected to the first node, and a gate connected to a write-word line;
a sixth transistor having one node connected to a second write-bit line constituting a complementary bit line pair with the first write-bit line, another node connected to the second node, and a gate connected to the write-word line;
a seventh transistor having one node connected to the second power source, and a gate connected to the second node; and
an eighth transistor having one node connected to another node of the seventh transistor, another node connected to a read-bit line, and a gate connected to a read-word line,
wherein each of the third to sixth transistors is a three-dimensional transistor of a first conductive type formed in a first layer,
wherein each of the first and second transistors is a three-dimensional transistor of a second conductive type different from the first conductive type, the first and second transistors being formed in a second layer different from the first layer, and the first and second transistors at least partially overlapping the third and fourth transistors in plan view, respectively, and
wherein the seventh and eighth transistors include a three-dimensional transistor of the first conductive type formed in the first layer, and are arranged to align in a first direction that is a direction in which channel portions of the first to eighth transistors extend.