Patent ID: 11907563
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. An apparatus, comprising:
an array of memory cells comprising one or more chalcogenide storage elements;
a first component associated with the array of memory cells and having a first clock domain;
a second component associated with the array of memory cells and having a second clock domain; and
a queue coupled with the first component and the second component and configured to transform information from the first clock domain to the second clock domain, wherein the queue further comprises:
a receiver configured to receive a first command to store data in the queue from the first component and to receive a second command to cause the second component to retrieve the data;
a storage component comprising a first location and a second location for storing information and configured to overwrite information previously stored in the first location based on the queue being full;
a synchronizer configured to generate a third command for the second component to retrieve the data from the queue, the third command synchronized with a clock of the second clock domain and based at least in part on receiving the second command;
a retriever configured to retrieve the data from the first location of the storage component based at least in part on generating the third command; and
a transmitter configured to transmit the data to the second component based at least in part on retrieving the data.