Patent ID: 11868694
Assignee: SYNOPSYS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A method, comprising:
analyzing each of a first set of sequential elements of a plurality of sequential elements to determine an edge of a clock signal pattern of a clock associated with each of the first set of sequential elements causing an output change at corresponding one or more sequential elements of the first set of sequential elements;
discarding one or more cycles of the clock signal pattern of the clock from emulation that do not include the edge of the clock signal pattern that causes at least one sequential element of the first set of sequential elements to change an output;
generating a divided clock of the clock for a second set of sequential elements of the plurality of sequential elements;
analyzing each of the second set of sequential elements of the plurality of sequential elements to determine an edge of a clock signal pattern of the divided clock associated with each of the second set of sequential elements causing an output change at corresponding one or more sequential elements of the second set of sequential elements; and
emulating the one or more discarded cycles of the clock signal pattern of the clock upon determining that the one or more discarded cycles include the edge of the clock signal pattern of the divided clock that causes at least one sequential element of the second set of sequential elements to change the output.