Patent ID: 11956965
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 7:
8. A memory device, comprising:
a substrate;
a circuit pattern on the substrate;
a base semiconductor pattern on the circuit pattern;
a first insulation layer on the base semiconductor pattern;
a ground selection line on the first insulation layer, a cutting portion cutting the ground selection line;
an uppermost first insulation layer and a first word line stacked immediately above the ground selection line;
a lower insulation pattern passing through a portion of the uppermost first insulation layer, the first insulation layer, and the cutting portion;
second insulation layers and second word lines alternately stacked on the first word line; and
a channel structure passing through the ground selection line, the uppermost first insulation layer, the first word line, the second insulation layers, and the second word lines, the channel structure extending in a vertical direction,
wherein:
the first word line includes a first portion laterally offset from the cutting portion and a second portion overlying the cutting portion,
the first portion of the first word line has a first thickness,
the second portion of the first word line has a second thickness less than the first thickness,
an upper surface of the lower insulation pattern protrudes above a lower surface of the first word line at the first portion of the first word line,
each of the second word lines has the first thickness, and
the uppermost first insulation layer has a thickness that is about 2 times to about 5 times a thickness of the first insulation layer.