Patent ID: 11942138
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory system, comprising:
a memory device suitable for:
providing row-hammer data to set refresh rates for adjacent word lines of a target word line, and
performing a target refresh operation on one or more word lines corresponding to a first row-hammer address according to a first target refresh command; and
a memory controller suitable for:
generating a plurality of sampling addresses by sampling an active address,
generating a plurality of counting values corresponding to the plurality of sampling addresses by comparing the plurality of sampling addresses with the active address and incrementing a counting value of the plurality of counting values for a match in the comparing of the plurality of sampling addresses with the active address,
calculating, when there is the match between the plurality of sampling addresses and the active address, a plurality of adjacent addresses corresponding to and incrementally changed from the plurality of sampling addresses based on the plurality of counting values and the row-hammer data, and
providing the plurality of adjacent addresses as the first row-hammer address with the first target refresh command.