Patent ID: 11862589
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A method of manufacturing a wafer-level semiconductor package, the method comprising:
forming a redistribution layer on a semiconductor chip;
forming an under bump metal (UBM) layer on the redistribution layer;
forming a preliminary solder layer to cover a surface of the UBM layer;
providing flux to a top surface of the preliminary solder layer;
dropping a solder ball on the preliminary solder layer and the flux; and
reflowing the preliminary solder layer, the flux, and the solder ball and forming a solder bump,
wherein the forming of the preliminary solder layer comprises
forming a photoresist pattern having a contact hole configured to expose the UBM layer, and
forming the preliminary solder layer inside the contact hole.