Patent ID: 11923150
Assignee: INTEL CORPORATION
Field: Electrical machinery, apparatus, energy (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A method for fabricating an integrated circuit (IC) structure, the method comprising:
providing, in a support structure, an opening for a through-silicon via (TSV) and an opening for a decoupling capacitor, wherein a depth of the opening for the decoupling capacitor is between about 1.1 and 4 times smaller than a depth of the opening for the TSV;
providing a first capacitor electrode of the decoupling capacitor as a liner of a first electrically conductive material on sidewalls and a bottom of the opening for the decoupling capacitor;
providing a capacitor insulator of the decoupling capacitor as a liner of a capacitor insulator material on sidewalls and a bottom of the opening for the decoupling capacitor lined with the first electrically conductive material;
providing a second capacitor electrode of the decoupling capacitor by providing a second electrically conductive material filling at least a portion of the opening for the decoupling capacitor lined with the first electrically conductive material and with the capacitor insulator material;
providing a third electrically conductive material to at least partially fill the opening for the TSV;
providing a liner of a dielectric material on the sidewalls and the bottom of the opening for the decoupling capacitor before providing the first capacitor electrode; and
providing a liner of the dielectric material on sidewalls of the opening for the TSV before providing the third electrically conductive material to at least partially fill the opening for the TSV.