Patent ID: 11913971
Assignee: GLOBALFOUNDRIES U.S. INC.
Field: Measurement (Instruments)
Classification: CPC G | IPC G

Claim 11:
12. The system of claim 8,
wherein the gate structure comprises: a first gate electrode comprising a stack of electrically isolated first sub-electrodes adjacent to a first side of the reservoir; and a second gate electrode comprising a stack of electrically isolated second sub-electrodes adjacent to a second side of the reservoir,
wherein fixed locations of the first gate electrode and the second gate electrode within the reservoir and a fill level of the conductive fluid within the reservoir are such that:
when the channel region and the top surface of the conductive fluid are parallel, lower ones of the first sub-electrodes and lower ones of the second sub-electrodes are in contact with the conductive fluid and upper ones of the first sub-electrodes and upper ones of the second sub-electrodes are physically separated from the conductive fluid,
when the channel region is angled to progressively increasing first degrees relative to the top surface of the conductive fluid, the lower ones of the first sub-electrodes become physically separated from the conductive fluid in order from top down and the upper ones of the second sub-electrodes contact the conductive fluid in order from bottom up, and
when the channel region is angled to progressively increasing second degrees relative to the top surface of the conductive fluid, the lower ones of the second sub-electrodes become physically separated from the conductive fluid in order from top down and the upper ones of the first sub-electrodes contact the conductive fluid in order from bottom up,

wherein the specific bias conditions comprise a fixed drain-source voltage, a fixed first gate voltage on each of the first sub-electrodes, and a fixed second gate voltage on each of the second sub-electrodes,
wherein the fixed first gate voltage is less than the fixed second gate electrode, and
wherein the electrical property is drain current, and
wherein the drain current is indicative of any of (a) chip tilt direction and angle and (b) chip acceleration direction and rate.