Patent ID: 11923283
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor package comprising:
a first package substrate;
a first semiconductor chip on a top surface of the first package substrate;
an interposer electrically connected to the first package substrate on a top surface of the first semiconductor chip; and
a molding layer configured to cover the first package substrate and the first semiconductor chip,
wherein the interposer includes an interposer trench recessed from a bottom surface of the interposer and an interposer hole penetrating the interposer, the bottom surface of the interposer facing both the top surface of the first semiconductor chip and the top surface of the first package substrate,
the molding layer includes a filling portion filling a region between the first package substrate and the interposer, a through portion filling the interposer hole, and a cover portion covering at least a part of a top surface of the interposer,
a bottommost surface of the interposer is directly above the top surface of the first semiconductor chip, based on the top surface of the first package substrate, and
a maximum width of the interposer trench is smaller than a maximum width of the first semiconductor chip.