Patent ID: 11900996
Assignee: GLOBALFOUNDRIES U.S. INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 18:
19. The memory structure of claim 16, wherein the digital voltage boost circuit further comprises:
a first input node connected to the first wordline;
a second input node connected to the second wordline;
a third input node that receives a mode select signal indicating one of a read mode and a write mode;
a first output node connected to the first voltage boost line;
a second output node connected to the fourth voltage boost line;
a third output node connected to the second voltage boost line and the third voltage boost line;
a first pair of inverters connected in series between the first input node and the first output node;
a second pair of inverters connected in series between the second input node and the second output node;
an NOR gate receiving input signals from the first input node and the second input node; and
an additional NOR gate receiving input signals from the NOR gate and the third input node and outputting an output signal to the third output node.