Patent ID: 11934964
Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An integrated circuit, comprising:
a memory including a finite automata (FA) graph, wherein the FA graph includes a plurality of nodes connected by directional arcs, wherein:
each arc representing transitions between nodes of the FA graph based on criteria specified for the respective arc,
the plurality of nodes including a skip node and a root node;
the directional arcs include an arc from the skip node to the root node; and

one or more hardware-based regular expression (RegEx) accelerators connected to the memory, wherein each RegEx accelerator includes a regular expression engine, the regular expression engine configured to receive the FA graph from the memory and to perform a regular expression operation on a stream of data units based on the received FA graph by initially traversing the root node,
wherein the regular expression engine is further configured to, a to reaching the skip node, consume a predefined number of data units in the stream of data units before traversing the arc from the skip node to the root node, wherein the predefined number of data units is provided by a counter used to detect an end of a payload.