Patent ID: 11910590
Assignee: SK HYNIX INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A semiconductor memory device, comprising:
a substrate;
an active layer spaced apart from the substrate, extending in a direction parallel to the substrate, and including a first source/drain region, a second source/drain region and a thin-body channel between the first source/drain region and the second source/drain region;
a bit line extending in a direction vertical to the substrate and connected to the first source/drain region;
a capacitor connected to the second source/drain region; and
a first word line and a second word line extending in a direction crossing the thin-body channel with the thin-body channel interposed therebetween,
wherein a thickness of the thin-body channel is smaller than thicknesses of the first word line and the second word line, wherein
the thickness of the thin-body channel is smaller than that of first source/drain region, and
the thickness of the thin-body channel is equal to that of the second source/drain region.