Patent ID: 11868967
Assignee: HITACHI, LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A schedule creation assisting device comprising one or more memory devices having a program stored therein that, when executed by one or more processors, cause the one or more processors to:
store information on a total working time length in a specified period of each of workers who work in cooperation in a specified operation, a number of the workers necessary at each timing during the specified period, and a constraint condition regarding allocation of the workers to the specified operation; and
compute an Ising model, regarding an objective function including, as terms, the total working time length in the specified period, the number of necessary workers, and a constraint condition function that is minimized when the constraint condition is satisfied, wherein whether each of the workers is to attend work is set as a spin, and a sensitivity between variables of the constraint condition function is set as an intensity of interaction between the spins;
identify a ground state of the Ising model in which the objective function is satisfied; and
generate an output indicating a schedule for the workers, in a specified device, by associating a first set of spins having a first spin state in the ground state of the Ising model with a first set of workers to attend work and associating a second set of spins having a second spin state in the ground state of the Ising model with a second set of workers to not attend work.