Patent ID: 11908505
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 2:
3. The data processing device of claim 2, wherein:
each of the single-transistor memory element is a ferroelectric field-effect transistor (“FeFET”); and
each of the ML switching transistors and input switching transistors is a field-effect transistor (“FET”) having a gate, a source and a drain,
the gates of the ML switching transistors in the first and second data storage units being connected to each other and being adapted to receive an matchline (“ML”)-enable signal,
the gates of the FeFETs in the first and second data storage units being connected to each other and adapted to receive a wordline (“WL”) signal, and
the gates of the input switching transistors being adapted to receive respective input signals.