Patent ID: 11881858
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 8:
9. The clock generation circuit of claim 1, wherein the oscillation circuit comprises:
an oscillator, configured to generate a first initial oscillation signal and a second initial oscillation signal, wherein a frequency of the first initial oscillation signal is same as a frequency of the second initial oscillation signal, and a phase of the first initial oscillation signal is opposite to a phase of the second initial oscillation signal; and
a path simulation circuit, located between the oscillator and the comparison unit, wherein one end of the path simulation circuit is connected to an output end of the oscillator, another end of the path simulation circuit is connected to an input end of the comparison unit, and the path simulation circuit is configured to simulate circuit characteristics of a first path, generate the first oscillation signal by receiving the first initial oscillation signal, and generate the second oscillation signal by receiving the second initial oscillation signal.