Patent ID: 11973042
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A semiconductor package having a top and a bottom, comprising:
a semiconductor chip disposed within the semiconductor package between the top of the semiconductor package and the bottom of the semiconductor package, wherein the semiconductor chip includes at least one connection pad disposed on a top surface thereof;
a plurality of wiring layers disposed adjacently to the semiconductor chip, and stacked vertically between the top of the semiconductor package and the bottom of the semiconductor package;
a first conductive bump disposed on the at least one connection pad of the semiconductor chip;
a second conductive bump disposed on an uppermost wiring layer among the plurality of wiring layers;
an insulating post disposed between the semiconductor chip and the plurality of wiring layers, and extending towards the top of the semiconductor package and the bottom of the semiconductor package;
an encapsulant disposed on side surfaces of the first and second conductive bumps, the insulating post, and the semiconductor chip; and
a redistribution structure including a redistribution layer electrically connected to the first and second conductive bumps,
wherein an upper surface of the insulating post is substantially coplanar with an upper surface of the encapsulant, an upper surface of the first conductive bump, and an upper surface of the second conductive bump.