Patent ID: 11862291
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 4:
5. The memory device of claim 3, wherein the bit counter comprises:
a sum signal generator configured to output a sum signal of a corresponding bit by performing AND logic processing on a sum signal output by the bit counter of a lower bit and an internal count value;
a pulse filter configured to generate an internal counter pulse synchronized with the counter pulse on condition that the sum signal output by the sum signal generator is logic high;
a shift register configured to output the internal count value by toggling the internal count value in synchronization with the internal counter pulse and reset the internal count value responding to the mask signal;
a register configured to store a value of a corresponding bit of the start address in synchronization with the register pulse and output the stored value as a register value; and
an adder configured to generate the carry output signal and an address output signal by using the internal count value, the register value, and the carry signal output by the bit counter of the lower bit.