Patent ID: 11901035
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 3:
4. The system of claim 3, wherein:
the first set of one or more of the memory cells is contained within at least a first lot of one or more of the banks;
the second set of one or more of the memory cells is contained within at least a second lot of one of the banks;
in terms of membership, the first and second lots are non-overlapping of each other; and
the DDVFS device is further configured to perform the following:
adjusting the first clock or the first PS voltage of the first lot resulting in first bank-wide adjustment of corresponding temperatures amongst the memory cells of the banks of the first lot; and
adjusting the second clock or the second PS voltage of the second lot resulting in second bank-wide adjustment of corresponding temperatures amongst the memory cells of the banks of the second lot.