Patent ID: 11895851
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 20:
21. A method, comprising:
identifying at least one cell of a memory array, the memory array having a plurality of decks, a plurality of word lines, a plurality of word line decoders, a plurality of bit lines, and a plurality of bit line decoders positioned beneath the memory array, each of the plurality of bit lines coupled with a respective one or more decks of the plurality of decks, the plurality of bit lines comprising a first bit line, a second bit line, and a third bit line; and
accessing the at least one cell of the memory array using one of the plurality of word line decoders and one of the plurality of bit line decoders, wherein the each of the plurality of bit lines are coupled with a respective bit line decoder using a plurality of bit line sockets, wherein the plurality of bit line sockets comprises a first subset of bit line sockets that are arranged according to a first periodicity and couple respective segments of the first bit line with respective bit line decoders of the plurality of bit line decoders, a second subset of bit line sockets that are arranged according to a second periodicity and couple respective segments of the second bit line with respective bit line decoders of the plurality of bit line decoders, and a third subset of bit line sockets that are arranged according to the second periodicity and couple respective segments of the third bit line with respective bit line decoders of the plurality of bit line decoders.