Patent ID: 11894373
Assignee: WINBOND ELECTRONICS CORP.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor device, comprising:
a substrate;
a first transistor disposed on the substrate, wherein the first transistor comprises:
first semiconductor channel layers stacked in a vertical direction and separated from one another; and
a first source/drain structure and a second source/drain structure disposed at two opposite sides of each of the first semiconductor channel layers in a horizontal direction respectively, wherein the first source/drain structure and the second source/drain structure are connected with the first semiconductor channel layers respectively;

a second transistor disposed on the substrate, wherein the second transistor comprises:
second semiconductor channel layers disposed above the first semiconductor channel layers, wherein the second semiconductor channel layers are stacked in the vertical direction and separated from one another; and
a third source/drain structure and a fourth source/drain structure disposed at two opposite sides of each of the second semiconductor channel layers in the horizontal direction respectively, wherein the third source/drain structure and the fourth source/drain structure are connected with the second semiconductor channel layers respectively;

a first contact structure penetrating through the third source/drain structure in the vertical direction, wherein the first source/drain structure is electrically connected with the third source/drain structure via the first contact structure, and a part of the first source/drain structure is disposed between the substrate and the first contact structure in the vertical direction;
a dielectric layer disposed between the first source/drain structure and the third source/drain structure in the vertical direction, wherein the first contact structure further penetrates through the dielectric layer in the vertical direction;
a second contact structure disposed on and electrically connected with the second source/drain structure;
a third contact structure disposed on and electrically connected with the fourth source/drain structure, wherein the second contact structure and the third contact structure are electrically separated from each other, the fourth source/drain structure overlaps a portion of the second source/drain structure in the vertical direction, and the second contact structure is disposed on another portion of the second source/drain structure without overlapping the fourth source/drain structure in the vertical direction;
a first metal silicide layer disposed between the dielectric layer and the first source/drain structure in the vertical direction, wherein the first contact structure directly contacts the first metal silicide layer for being electrically connected with the first source/drain structure via the first metal silicide layer;
a second metal silicide layer disposed on the third source/drain structure and the fourth source/drain structure; and
an etching stop layer disposed on and directly contacting the second metal silicide layer, a sidewall of the fourth source/drain structure, and the dielectric layer, wherein the third contact structure penetrates through the etching stop layer on the second metal silicide layer, and the second contact structure penetrates through the etching stop layer on the dielectric layer.