Patent ID: 11900994
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 18:
19. The method of claim 18, wherein:
the power header edge cell and the power footer edge cell are arranged respectively at two opposite sides of the array of memory cells;
gates of the pair of first transistors are coupled to each other and coupled to the word line;
sources of the pair of first transistors are coupled to a positive power supply voltage;
drains of the pair of first transistors are coupled to a power supply to the array of memory cells;
gates of the pair of second transistors are coupled to each other and coupled to the word line;
sources of the pair of second transistors are coupled to a power supply to the array of memory cells; and
drains of the pair of second transistors are coupled to a negative power supply voltage.