Patent ID: 11869617
Assignee: META PLATFORMS TECHNOLOGIES, LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 9:
10. A system, comprising:
a static random access memory (SRAM) device comprising:
a bit cell array comprising a plurality of bit cells, the plurality of bit cells arranged in a plurality of rows and a plurality of columns, each column of the plurality of columns operatively coupled to a pair of bit lines, wherein the plurality of columns is arranged as a plurality of column groups each comprising a plurality of local columns, and wherein the plurality of columns includes one or more redundant columns;
a row decoder that is configured to operatively couple a word line to a row of the plurality of rows of bit cells based at least in part on a row address provided to the row decoder; and
a plurality of column decoders, each associated with a column group of the plurality of column groups, wherein each column decoder is configured to operatively couple a data line to a local column of the plurality of local columns corresponding to a column group of the plurality of column groups associated with said column decoder; and

a controller configured to:
obtain an address of a bit cell in the bit cell array for which a sequential memory access operation is to be performed, wherein the address comprises a row address, a column group identifier, and a local column address;
map the row address, the column group identifier, and the local column address to a repaired address corresponding to a repaired bit cell, wherein the repaired address corresponds to a redundant column of the one or more redundant columns, wherein a first bit cell of the redundant column corresponds to a faulty bit cell of a first local column and a second bit cell of the redundant column corresponds to a faulty bit cell of a second local column that is different than the first local column;
provide the row address to the row decoder that causes the word line corresponding to a row of the plurality of rows associated with the row address to be asserted;
perform the sequential memory access operation at the repaired address by selecting the redundant column corresponding to the repaired address; and
perform at least one other sequential memory access operation by selecting at least one other local column prior to de-asserting the word line.