Patent ID: 11880597
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A semiconductor memory, comprising a Data Queue (DQ) port, a memory bank, and a read operation circuit, wherein the read operation circuit comprising:
a data determination module connected to the memory bank, wherein the data determination module is configured to read read data from the memory bank, and determine, according to number of bits of a data change between previous read data and current read data, whether to invert the current read data to output global bus data for transmission through a global bus and inversion flag data for transmission through an inversion flag signal line;
a data receiving module connected to the global bus and the inversion flag signal line and configured to determine whether to invert the global bus data according to the inversion flag data to output cache data;
a parallel-to-serial conversion circuit connected between the data receiving module and the DQ port and configured to perform parallel-to-serial conversion on the cache data to generate output data of the DQ port; and
a data buffer module connected to the memory bank through the global bus, wherein the data buffer module is configured to receive an enable signal to determine an initial state of the global bus according to the enable signal and the current read data;
wherein the data determination module is configured to determine change flag data according to the change between the current read data and the previous read data, output inverted data of the current read data as the global bus data and set the inversion flag data to High if number of bits of high data in the change flag data is greater than a preset value, and output original current read data as the global bus data and set the inversion flag data to Low if the number of bits of the high data in the change flag data is less than or equal to the preset value;
wherein the change flag data and the global bus data are both divided into M groups, the inversion flag data having M bits, the M-bit inversion flag data being corresponding to the M groups of change flag data one to one, and the M-bit inversion flag data being corresponding to the M groups of global bus data one to one, wherein the M is an integer greater than 1.