Patent ID: 11942141
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. A method comprising:
providing activation signals in a first voltage domain;
providing an output signal in a second voltage domain based on the activation signals in the first domain;
providing a latched control signal to a power-gate based on the activation signals so as to provide the output signal in the second voltage domain; and
providing logic that provides a first power-gated switch as a power-gate and first inversion logic coupled in series between a source voltage supply in the second domain and ground, and wherein the logic circuitry provides a second power-gated switch and second inversion logic coupled in series between the source voltage supply in the second domain and ground, and
wherein the second inversion logic provides a buffered activation signal to the latch circuitry, and wherein the latch circuitry operates as a half-latch that receives the buffered activation signal and provides the latched control signal to the logic circuitry to activate the first power-gated switch.