Patent ID: 11869811
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 4:
5. The semiconductor device of claim 1, further comprising:
a first source/drain region on the first sub-active pattern being between the first gate electrode and the isolation pattern;
a second source/drain region on the second sub-active pattern being between the second gate electrode and the isolation pattern;
contacts connected to the first and second source/drain regions respectively; and
a first gate spacer on a sidewall of the first gate electrode; and
a second gate spacer on a sidewall of the second gate electrode
wherein a level of the bottommost surface of the each of the contacts is higher than the level of the bottommost surface of the first gate spacer and the level of the bottommost surface of the second gate spacer.