Patent ID: 11917603
Assignee: QUALCOMM INCORPORATED
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 17:
18. The apparatus of claim 15, wherein the at least one processor configured to perform the one or more actions is further configured to:
determine a first number of resource blocks (RBs) for the first PUCCH repetition and a second number of RBs for the second PUCCH repetition;
perform rate matching for the first PUCCH repetition and rate matching for the second PUCCH repetition respectively based on the first number of RBs and the second number of RBs;
determine a first number of coded bits after rate matching for the first PUCCH repetition based on the first number of RBs and allocated resources for the first PUCCH repetition, and a second number of coded bits after rate matching for the second PUCCH repetition based on the second number of RBs and allocated resources for the second PUCCH repetition; and
determine whether the first number of coded bits and the second number of coded bits would result in the same mother polar code length for both the first and the second PUCCH repetitions.