Patent ID: 11869610
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. The storage device according to claim 4, wherein the amplifying circuit comprises:
a first transistor, configured with a source to be electrically connected to a first voltage, and a gate to be electrically connected to the second input end of the amplifying circuit;
a second transistor, configured with a source to be electrically connected to a second voltage, and a drain to be electrically connected to both a drain of the first transistor and the first input end of the amplifying circuit;
a third transistor, configured with a source to be electrically connected to the first voltage, a drain to be electrically connected to both the gate of the first transistor and the second input end of the amplifying circuit, and a gate to be electrically connected to the first input end of the amplifying circuit; and
a fourth transistor, configured with a source to be electrically connected to the second voltage, a drain to be electrically connected to both the drain of the third transistor and the gate of the second transistor, and a gate to be electrically connected to the first input end of the amplifying circuit.