Patent ID: 11967269
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A scan stage comprising:
a first transistor having a first electrode coupled to an output scan line, a second electrode coupled to a first power line, and a gate electrode coupled to a first node;
a second transistor having a first electrode coupled to a first clock line, a second electrode coupled to the output scan line, and a gate electrode coupled to a second node;
a third transistor having a first electrode coupled to the first node, a second electrode coupled to a first input scan line, and a gate electrode coupled to a second clock line;
a fourth transistor having a first electrode, a second electrode, and a gate electrode, the second electrode and the gate electrode coupled to a second input scan line; and
fifth transistor having a first electrode coupled to the second node, a second electrode coupled to the first electrode of the fourth transistor, and a gate electrode coupled to a control line,
wherein the first input scan line and the second input scan line are different from each other.