Patent ID: 11935611
Assignee: REALTEK SEMICONDUCTOR CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A memory test method having a repair information maintaining mechanism, comprising:
controlling a memory built-in self repair circuit to perform a built-in self-repair procedure on a memory circuit having a redundant structure by a repairing control circuit;
receiving and storing repairing information generated by the memory built-in self repair circuit by a remapping storage circuit of the repairing control circuit after the built-in self-repair procedure is finished, wherein the remapping storage circuit is disposed in a scan chain;
receiving and storing the repairing information from the remapping storage circuit by a latch storage circuit of the repairing control circuit, wherein the latch storage circuit is electrically coupled between the remapping storage circuit and a remapping circuit corresponding to the memory circuit; and
accessing the repairing information by a remapping circuit of the memory circuit under the control of the latch storage circuit when the remapping storage circuit performs a scan test based on the scan chain to perform remapping and repairing on the memory circuit based on the repairing information and the redundant structure.