Patent ID: 11947887
Assignee: CADENCE DESIGN SYSTEMS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A non-transitory computer readable medium comprising machine-readable instructions, the machine-readable instructions being executed to:
receive, at a circuit design tool executing on a computing platform, a circuit netlist associated with a circuit design, the circuit netlist comprising functional logic, test-point nodes interconnecting portions of the functional logic, and test-point flops associated with scan-chains;
evaluate the circuit netlist to determine compatibility of the test-point nodes in the circuit netlist via a test-point flop allocation module executing on the computing platform;
allocate each of the test-point flops to one of a plurality test-point sharing groups comprising a plurality of compatible test-point nodes via the test-point flop allocation module; and
generate a circuit layout associated with the circuit design, the circuit layout comprising the functional logic and scan-chains comprising the test-point flops allocated to the test-point sharing groups in response to the circuit netlist via a circuit layout module executing on the computing platform.