Patent ID: 11862292
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A system comprising:
a plurality of memory banks;
a plurality of buffers, wherein each of the plurality of buffers is to perform a write process to write data to a corresponding one of the plurality of memory banks; and
a buffer controller including:
a first register to store an address of a corresponding memory bank of the plurality of memory banks,
a second register indicating a first entry storing an address of a memory bank on which the write process is predicted to be completed next among the plurality of memory banks,
a third register indicating a second entry to be updated, and
a controller to configure one or more buffers of the plurality of buffers to perform the write process, according to the first and second entries.