Patent ID: 11881860
Assignee: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A phase mixing circuit comprising:
a jitter cancellation circuit configured to mix phases of a first signal input to a first node and a second signal input to a second node to produce a third signal at a third node and a fourth signal at a fourth node; and
a delay adjustment circuit configured to adjust respective delays of the third signal and the fourth signal to produce a fifth signal at a fifth node and a sixth signal at a sixth node,
wherein the jitter cancellation circuit comprises:
N+2n inverters connected in series between the first node and the third node;
N+2n+1 inverters connected in series between the first node and the fourth node;
N+2n−1 inverters connected in series between the second node and the third node; and
N+2n inverters connected in series between the second node and the fourth node,
wherein N is an integer greater than or equal to 0 and n is a natural number.