Patent ID: 11882708
Assignee: SK HYNIX INC.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 4:
5. A method of manufacturing an electronic device, the method comprising:
forming a first conductive layer over a substrate;
forming a memory layer over the first conductive layer;
patterning the memory layer and the first conductive layer to define a first conductive line pattern and a preliminary memory pattern that extend to a first direction;
forming a first liner layer on sidewalls of the first conductive line pattern and sidewalls of the preliminary memory pattern, which is in parallel with the first direction, and a first potential well in the first liner layer;
forming a second conductive layer over the preliminary memory pattern;
patterning the second conductive layer and the preliminary memory pattern to define a second conductive line pattern that extends to a second direction intersecting with the first direction and a memory pattern positioned at an intersection of the first conductive line pattern and the second conductive line pattern;
forming a second liner layer on sidewalls of the second conductive line pattern and sidewalls of the memory pattern, which is in parallel with the second direction.