Patent ID: 11936383
Assignee: TAGORE TECHNOLOGY, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An electronic circuit, comprising:
a GaN semiconductor switch device including a drain node, a source node, and a gate, the gate for receiving an input signal that
in a first range of signal level, controls an on state of the semiconductor switch device in which a direct electrical connection path in the GaN semiconductor switch device is established between the drain node and the source node, or
in a second range of signal level, different from the first range, controls an off state of the GaN semiconductor switch device in which the electrical connection path has an impedance approaching an open circuit;

a driver circuit, having an output that is electrically coupled to the gate of the GaN semiconductor switch device, for providing the input signal to the gate; and
a bias-less Miller clamp protection circuit, electrically coupled to the output of the driver circuit and to the gate of the GaN semiconductor switch device, for protecting the semiconductor switch device from turning from an off state to an on state in response to a parasitic Miller turn-on signal at the gate while a supply voltage for the driver circuit and for the protection circuit is absent, and wherein the bias-less Miller clamp protection circuit includes:
a HEMT switch having a drain connected to the gate of the GaN semiconductor switch device, a source connected to the source node of the GaN semiconductor switch device, and having a gate, and
a first GaN FET having a drain connected to the drain node of the GaN semiconductor switch device and having a gate electrically coupled to the gate of the HEMT switch,

wherein the GaN semiconductor switch device, the HEMT switch and the first GaN FET are monolithically integrated on a single chip.