Patent ID: 11861236
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A memory device comprising:
a memory array comprising a plurality of planes;
a primary plane driver circuit;
a plurality of secondary plane driver circuits, wherein each of the plurality of secondary plane driver circuits occupies a smaller footprint area than the primary plane driver circuit;
routing circuitry to selectively couple the primary plane driver circuit and the plurality of secondary plane driver circuits to the memory array; and
control logic configured to perform operations comprising:
receiving a request to perform a first memory access operation associated with a first plane of the plurality of planes;
receiving a request to perform a second memory access operation associated with a second plane of the plurality of planes; and
configuring the routing circuitry to operatively couple the primary plane driver circuit to the first plane and one of the secondary plane driver circuits to the second plane to concurrently perform the first memory access operation and the second memory access operation.