Patent ID: 11967362
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. A method comprising:
configuring a first transistor of a sense amplifier for a memory device in a first diode configuration using a first compensation transistor to couple gate and source terminals of the first transistor together to charge a first gut node with a first voltage proportional to a first threshold voltage of the first transistor;
configuring a second transistor of the sense amplifier in a second diode configuration using a second compensation transistor to couple gate and source terminals of the second transistor together to charge a second gut node with a second voltage proportional to a second threshold voltage of the second transistor;
disconnecting the gate terminal from the source terminal of the first transistor using the first compensation transistor;
disconnecting the gate terminal from the source terminal of the second transistor using the second compensation transistor;
using the sense amplifier, amplifying a difference in voltages between the first and second gut nodes by:
charging a first digit line with a logic high value from a memory cell, wherein the first digit line is configured to send and receive data to and from the sense amplifier via the first gut node;
discharging the second gut node using the charging of the first digit line; and
charging the first gut node using the discharging of the second gut node; and

transmitting the amplified difference in voltages between the first and second gut nodes as a differential signal over the digit lines.