Patent ID: 11894263
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. A method, comprising:
providing a workpiece comprising a substrate, a dielectric layer over the substrate, a gate contact via, a first source/drain contact via and a second source/drain contact via disposed in the dielectric layer, and a silicon layer over the dielectric layer;
performing a first patterning process to form a first trench and a second trench in the silicon layer, wherein the first trench is disposed over the first source/drain contact via and the second trench is disposed over the second source/drain contact via;
performing a second patterning process to form a branch opening in the silicon layer, wherein the branch opening is in fluid communication with the second trench and the branch opening is disposed over the gate contact via;
conformally depositing a spacer material layer over the first trench, the second trench, and the branch opening;
etching back the spacer material layer to form a spacer along sidewalls of the first trench, the second trench and the branch opening;
after the etching back, selectively removing the silicon layer between the first trench and the second trench without substantially removing the spacer and the silicon layer between the branch opening and the first trench;
after the selectively removing, transferring a pattern of the silicon layer and the spacer to the dielectric layer; and
depositing a metal layer over the dielectric layer.