Patent ID: 11963350
Assignee: SK HYNIX INC.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor memory device comprising:
a plurality of gate stacks separated by a plurality of slit structures,
wherein each of the gate stacks comprises:
a first stack including three or more first conductive patterns spaced apart from one another in a horizontal direction;
a second stack formed over the first stack in a vertical direction and including second conductive patterns and interlayer dielectric layers alternately stacked;
a third stack formed over the second stack in the vertical direction and including a plurality of third conductive patterns spaced apart from one another; and
a plurality of channel structures formed in the first stack to the third stack,
wherein the first stack comprises:
a first lower insulating layer formed under the first conductive patterns;
a gap-fill insulating layer formed along a sidewall of each of the first conductive patterns to gap-fill between the first conductive patterns; and
a first upper insulating layer formed over the gap-fill insulating layer and the first conductive patterns.