Patent ID: 11908697
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. A method of forming an interconnect structure, the method comprising:
depositing a lower dielectric layer over a substrate;
forming a first recess in the lower dielectric layer;
forming a first conductive feature in the first recess, the first conductive feature having a first void;
depositing an upper dielectric layer over the lower dielectric layer and the first conductive feature;
forming a second recess in the upper dielectric layer, wherein the second recess exposes the first conductive feature, the second recess extending into the lower dielectric layer, wherein forming the second recess comprises removing a portion of the first conductive feature to expose the first void;
forming a carbon-containing layer along sidewalls of the second recess and the sidewalls of the first void; and
forming a second conductive layer over the carbon-containing layer.