Patent ID: 11961558
Assignee: NXP USA, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. An integrated circuit (IC) device comprising:
an input/output (I/O) pad configured to conduct voltage from a supply voltage;
a memory circuit including:
an array of non-volatile memory (NVM) cells including rows and columns of memory cells, a particular memory cell is accessed using a word line of a selected row, and a bit line and a source line of a selected column;
an internal supply voltage with a current profile that is not measurable outside the integrated circuit device or the memory circuit;
an isolation circuit controlled by a write type indicator, wherein, when the write type indicator indicates a hidden write operation, the isolation circuit isolates the internal supply voltage from the supply voltage, and the internal supply voltage is selected by the isolation circuit to perform the hidden write operation along a bit line in a selected column of the array of NVM cells;
a voltage control source follower circuit coupled to each of the memory cells;
a coupling switch configured to couple the supply voltage terminal to the voltage source follower circuit when the write type indicator indicates a hidden write is to be performed;
source line driver circuits; and
protection circuits, each of the protection circuits are coupled to a respective one of the source line driver circuits, and a portion of each of the protection circuits includes a source line voltage detector, a delay circuit coupled to output of the source line voltage detector, and a logic circuit coupled to output of the delay circuit, and output of the logic circuit is coupled to the gate electrode of the coupling switch;

a supply voltage terminal coupled to an output of the isolation circuit; and
a voltage regulator including an input coupled to the supply voltage terminal and an output that provides a bit line select voltage, wherein the voltage control source follower circuit is implemented using an NMOS transistor including a first current electrode coupled to the supply voltage terminal, a second current electrode coupled to a corresponding one of the memory cells, and a gate electrode coupled to the bit line select voltage.