Patent ID: 11935611
Assignee: REALTEK SEMICONDUCTOR CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. The memory test method of claim 8, wherein the repairing control circuit further comprises a multiplexer having a first input terminal, a second input terminal and an output terminal, the first input terminal being electrically coupled to the memory built-in self repair circuit to receive the repairing information, and the second input terminal and the output terminal being electrically coupled to the remapping storage circuit, the memory test method further comprises:
receiving a selection signal by the multiplexer such that the first input terminal is selected to receive the repairing information from the memory built-in self repair circuit in a receiving mode and the second input terminal is selected to receive the repairing information stored by the remapping storage circuit in a latch mode.