Patent ID: 11880607
Assignee: MEDIATEK SINGAPORE PTE. LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory circuit operative to perform self-repair, comprising:
a cell array including a plurality of rows and a plurality of columns of memory cells;
a controller to receive an input of a fuse signal that indicates a repair address shared by row repair and column repair of the cell array, the fuse signal including an enable signal that indicates whether the repair address is for the row repair or the column repair;
a row repair decoder to receive the repair address of a defective row from the controller when the enable signal indicates the row repair, and to map the repair address to a redundant row of the cell array; and
a column repair decoder to receive the repair address of a defective column from the controller when the enable signal indicates the column repair, and to map the repair address to another column of the cell array,
wherein the memory circuit is part of a chip and is to receive the fuse signal from a fuse memory through a plurality of fuse pins of the chip.