Patent ID: 11894446
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A semiconductor device, comprising:
a plurality of semiconductor wires;
a gate dielectric layer wrapping around each of the plurality of semiconductor wires;
a gate electrode layer disposed over the gate dielectric layer;
an isolation insulating layer from which a source/drain semiconductor fin structure protrudes;
sidewall spacers disposed on opposite side faces of the gate electrode layer; and
a dielectric layer, made of a different material than the gate dielectric layer and the sidewall spacers, disposed between the gate electrode layer and the isolation insulating layer,
wherein the dielectric layer includes SiON or SiOC, and
wherein a cross sectional shape of an uppermost one of the plurality of semiconductor wires has a tear-drop shape and has a largest area among the plurality of semiconductor wires.