Patent ID: 11935871
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor package, comprising:
a first semiconductor die comprising a first semiconductor substrate and a through silicon via, the through silicon via extending from a first side of the semiconductor substrate to a second, opposite side of the semiconductor substrate;
a second semiconductor die disposed on the first side of the semiconductor substrate;
a first insulating encapsulation disposed on the second semiconductor die and encapsulating the first semiconductor die, a terminal of the through silicon via being coplanar with a surface of the first insulating encapsulation;
a dielectric layer structure covering the first semiconductor die and the first insulating encapsulation;
an isolation layer disposed between the first semiconductor substrate and the dielectric layer structure and between the through silicon via and the first insulating encapsulation;
a conductor structure extending through the dielectric layer structure and in contact with the through silicon via; and
a second insulating encapsulation laterally encapsulating and laterally in contact with the second semiconductor die, the first insulating encapsulation, and the dielectric layer structure.