Patent ID: 11901021
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 19:
20. A non-volatile memory device comprising:
a substrate;
a memory cell region comprising a first metal pad, a memory cell array comprising a plurality of cell strings comprising a plurality of memory cells formed perpendicularly to the substrate, a plurality of string select lines respectively connected to the plurality of memory cells, and a plurality of word lines respectively connected to the plurality of memory cells; and
a peripheral circuit region comprising:
a second metal pad;
a control logic configured to control a first program operation and a second program operation for the memory cell array by providing a control signal and an address signal;
a voltage generator configured to generate at least one voltage based on the control signal;
a row decoder configured to provide the at least one voltage to the memory cell array during the first program operation and the second program operation via at least one of the plurality of string select lines and the plurality of word lines based on the address signal; and
a program logic circuit configured to adjust at least one of a voltage level and an application time of the at least one voltage for the second program operation based on a result of the first program operation,

wherein the peripheral region is connected to the memory cell region through the first metal pad and the second metal pad.