Patent ID: 11901821
Assignee: M3 TECHNOLOGY INC.
Field: Electrical machinery, apparatus, energy (Electrical engineering)
Classification: CPC H  Y | IPC H

Claim 10:
11. The apparatus of claim 10, wherein:
the gate drive signal conversion circuit comprises a first latch circuit and a second latch circuit, and wherein:
a data input of the first latch circuit and a data input of the second latch circuit are connected together and further connected to a Q-bar output of the first latch circuit;
a clock input of the first latch circuit is configured to receive a gate drive signal of the high-side switch of the first phase of the power converter; and
a clock input of the second latch circuit is configured to receive a gate drive signal of the high-side switch of the second phase of the power converter;

the current information storage circuit comprises:
a first AND gate having a first input connected to the Q-bar output of the first latch circuit, and a second input configured to receive the gate drive signal of the high-side switch of the first phase of the power converter;
a second AND gate having a first input connected to a Q output of the first latch circuit, and a second input configured to receive an inverse signal of the gate drive signal of the high-side switch of the first phase of the power converter;
a third AND gate having a first input connected to the Q output of the first latch circuit, and a second input configured to receive the gate drive signal of the high-side switch of the first phase of the power converter;
a fourth AND gate having a first input connected to the Q-bar output of the first latch circuit, and a second input configured to receive the inverse signal of the gate drive signal of the high-side switch of the first phase of the power converter;
a first sensed current source, a first control switch and a second control switch connected in series between a bias voltage source and ground, and wherein a gate of the first control switch is connected to an output of the first AND gate, and a gate of the second control switch is connected to an output of the second AND gate;
a first capacitor connected in parallel with the second control switch, and wherein the first capacitor is configured to store the signal representative of the current flowing through the high-side switch of the first phase of the power converter in a first cycle;
a third control switch and a fourth control switch connected in series between a common node of the first sensed current source and the first control switch, and ground, and wherein a gate of the third control switch is connected to an output of the third AND gate, and a gate of the fourth control switch is connected to an output of the fourth AND gate; and
a second capacitor connected in parallel with the fourth control switch, and wherein the second capacitor is configured to store the signal representative of the current flowing through the high-side switch of the first phase of the power converter in a second cycle immediately adjacent to the first cycle;

the current sensing circuit comprises:
a second sensed current source and a fifth control switch connected in series between the bias voltage source and ground, and wherein a gate of the fifth control switch is configured to receive an inverse signal of the gate drive signal of the high-side switch of the second phase of the power converter; and
a third capacitor connected in parallel with the fifth control switch, and wherein the third capacitor is configured to store the signal representative of the current flowing through the high-side switch of the second phase of the power converter; and

the reset signal circuit comprises:
a first comparator having an inverting input configured to receive the signal representative of the current flowing through the high-side switch of the first phase of the power converter in the second cycle, and a non-inverting input configured to receive the signal representative of the current flowing through the high-side switch of the second phase of the power converter;
a second comparator having an inverting input configured to receive the signal representative of the current flowing through the high-side switch of the first phase of the power converter in the first cycle, and a non-inverting input configured to receive the signal representative of the current flowing through the high-side switch of the second phase of the power converter;
a fifth AND gate having a first input connected to an output of the first comparator, and a second input connected to a Q-bar output of the second latch circuit;
a sixth AND gate having a first input connected to an output of the second comparator, and a second input connected to a Q output of the second latch circuit; and
an OR gate having a first input connected to an output of the fifth AND gate, and a second input connected to an output of the sixth AND gate, wherein the OR gate is configured to generate the second reset signal.