Patent ID: 11902297
Assignee: INTEL CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC H  B  G | IPC B  G  H

Claim 0:
1. A computing apparatus comprising:
a processor coupled to a communication bus; and
memory storing instructions, which when executed by the processor configure the apparatus to:
identify a first message from a plurality of messages transmitted on the communication bus as a low priority message;
cause overlap in arrival time between the low priority message and a second message from the plurality of messages;
determine whether the low priority message and the second message from the plurality of messages originated from a first electronic control unit (ECU) coupled to the communication bus, the second message a higher priority message than the low priority message, responsive to the overlap in arrival time; and
associate a message identification (MID) of the low priority message and an MID of the higher priority message to the first ECU.