Patent ID: 11923430
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. The device structure of claim 9, further comprising:
a second transistor disposed over a second region of the substrate, the second transistor comprising:
a second fin;
a second gate structure comprising:
the interfacial layer over a channel region of the second fin,
a third high-k dielectric layer disposed on the interfacial layer
a first high-k dielectric layer disposed on the third high-k dielectric layer,
the second high-k dielectric layer disposed on the first high-k dielectric layer, and
the capping layer disposed on the second high-k dielectric layer,

wherein the third high-k dielectric layer comprises hafnium oxide,
wherein the third high-k dielectric layer is doped with aluminum.