Patent ID: 11894378
Assignee: TOKYO ELECTRON LIMITED
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of forming a semiconductor device, the method comprising:
forming nano-sheet structures each having stacked layers of different materials including at least two layers of channel material suitable for use as a channel of a field-effect transistor (FET);
selectively masking a second portion of the nano-sheet structures while leaving a first portion including a first nano-sheet structure unmasked;
forming a first doped source/drain region in uncovered openings at a first layer of channel material in the first nano-sheet structure while a second layer of channel material in the first nano-sheet structure is covered, and forming a second doped source/drain region in the uncovered openings at the second layer of channel material in the first nano-sheet structure, the second doped source/drain region positioned vertically above the first doped source/drain region;
selectively masking the first portion of the nano-sheet structures while leaving the second portion including a second nano-sheet structure unmasked:
forming a third doped source/drain region in uncovered openings at a first layer of channel material in the second nano-sheet structure while a second layer of channel material in the second nano-sheet structure is covered, and forming a fourth doped source/drain region in the uncovered openings at the second layer of channel material in the first nano-sheet structure, the fourth doped source/drain region positioned vertically above the third doped source/drain region, wherein the first doped source/drain region shares the first channel with the third source/drain region, and wherein the second doped source/drain region shares the second channel with the fourth source/drain region.