Patent ID: 11916012
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A manufacturing method for a semiconductor structure, wherein the manufacturing method comprises:
forming a die stack comprising:
bonding a top bonding structure of a top semiconductor die to a back side of a bottom semiconductor die, wherein a top bonding conductor of the top bonding structure is bonded to a through semiconductor via of the bottom semiconductor die, and a surface area of the through semiconductor via of the bottom semiconductor die is greater than a surface area of the top bonding conductor of the top bonding structure of the top semiconductor die; and

bonding a front side of the bottom semiconductor die of the die stack to a back side of a carrier die comprising:
bonding a bottom bonding structure of the bottom semiconductor die to a through carrier via of the carrier die, wherein a surface area of the front side of the bottom semiconductor die is less than a surface area of the back side of the carrier die.