Patent ID: 11923370
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 0:
1. An integrated circuit structure, comprising:
a dielectric spine;
a first transistor device comprising a first vertical stack of semiconductor channels spaced apart from a first edge of the dielectric spine;
a second transistor device comprising a second vertical stack of semiconductor channels spaced apart from a second edge of the dielectric spine;
an N-type gate structure on the first vertical stack of semiconductor channels, a portion of the N-type gate structure laterally between and in contact with the first edge of the dielectric spine and the semiconductor channels of the first vertical stack of semiconductor channels; and
a P-type gate structure on the second vertical stack of semiconductor channels, a portion of the P-type gate structure laterally between and in contact with the second edge of the dielectric spine and the semiconductor channels of the second vertical stack of semiconductor channels.