Patent ID: 11967952
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 13:
14. An electronic system comprising:
processing circuitry configured to synthesize code of a high level language into code of a hardware description language; and
a field programmable gate array comprising a plurality of intellectual property blocks having a circuit configuration designed according to an access result of executing the code of the high level language,
wherein the processing circuitry is configured to select first code and second code from among code corresponding to a plurality of tasks to be processed, and convert the first code and the second code into code of hardware description languages, respectively,
wherein the processing circuitry is configured to load a first intellectual property block in a first sub-array of the field programmable gate array based on the code of the hardware description language into which the first code is converted, and load a second intellectual property block in a second sub-array of the field programmable gate array based on the code of the hardware description language into which the second code is converted, and
wherein the processing circuitry is further configured to design a circuit of at least one intellectual property block of the plurality of intellectual property blocks.