Patent ID: 11901012
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 13:
14. The non-volatile memory device of claim 13, further comprising:
a page buffer unit including page buffers respectively connected to the bit lines,
wherein a first page buffer from among the page buffers comprises:
a first transistor connected to a first sensing node that is connected to a first bit line from among the bit lines, and driven by a bit line setup signal; and
a second transistor connected between the first bit line and the first sensing node and driven by a bit line connection control signal, and
each of the initial develop time and the normal develop time corresponds to a time section from a time point when the bit line setup signal is deactivated to a time point when the bit line connection control signal is deactivated.