Patent ID: 11936388
Assignee: M31 TECHNOLOGY CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A clock signal generating circuit, comprising:
an oscillator, configured to generate an output clock according to a first control signal, a second control signal and a third control signal, wherein a frequency of the output clock is controlled by the first control signal and the second control signal, and a phase of the output clock is controlled by the third control signal;
a processing circuit, configured to accumulate a portion of a first digital code to generate a second digital code, a rate of change of a code value of the second digital code being slower than a rate of change of a code value of the first digital code; and
a control circuit, coupled to the oscillator and the processing circuit, the control circuit being configured to generate the first control signal at least according to the first digital code, generate the second control signal according to the second digital code, generate the third control signal at least according to a third digital code, and output the first control signal, the second control signal and the third control signal to the oscillator to lock the output clock.