Patent ID: 11880306
Assignee: AMPERE COMPUTING LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A processor-based system comprising:
a configurable combined private and shared cache, the configurable combined private and shared cache comprising a plurality of ways and configured to include a shared portion and a private portion, and to be responsive to a dynamic cache configuration determining a size of each of the shared portion and the private portion; and
a processor core associated with a corresponding configuration register (CR);
wherein:
the dynamic cache configuration is configured to allocate the shared portion and the private portion to include at least a respective shared portion and a respective private portion of the plurality of ways;
a value stored by the CR indicates a count of the plurality of ways assigned as the shared portion; and
a remainder of the plurality of ways is assigned as the private portion.