Patent ID: 11961559
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. An operating method of a storage device which includes a nonvolatile memory device, including a plurality of memory cells arranged on a substrate in rows and columns and stacked in a direction perpendicular to the substrate, and a memory controller, the method comprising:
receiving, at the memory controller, a read request from an external host device;
performing, at the storage device, a read operation on selected memory cells of the nonvolatile memory device in response to the read request;
performing, at the storage device, a first check read operation on first neighbor memory cells of the selected memory cells of the nonvolatile memory device while sequentially selecting sets of read voltages; and
performing, at the storage device, a second check read operation on second neighbor memory cells of the selected memory cells of the nonvolatile memory device while sequentially selecting the sets of read voltages, wherein:
in the second check read operation, the storage device first selects a set of read voltages that are used in the first check read operation and for which error correction succeeds, from among the sets of read voltages,
the performing of the read operation includes:
transmitting, at the memory controller, a first read command to the nonvolatile memory device;
performing, at the nonvolatile memory device, the read operation by using first read voltages in response to the first read command, such that first data read through the read operation are transmitted to the memory controller;
performing, at the memory controller, error correction decoding on the first data;
transmitting, at the memory controller, the error correction decoded first data to the external host device in response to determining that the error correction decoding succeeds; and
transmitting, at the memory controller, the first read command and first voltage information to the nonvolatile memory device in response to determining that the error correction decoding fails, the performing of the first check read operation includes:
transmitting, at the memory controller, a second read command to the nonvolatile memory device;
performing, at the nonvolatile memory device, a read operation by using one set of read voltages among the sets of read voltages in response to the second read command, such that second data read through the read operation are transmitted to the memory controller;
performing, at the memory controller, the error correction decoding on the second data;
terminating, at the memory controller, the first check read operation in response to determining that the error correction decoding succeeds; and
transmitting, at the memory controller, the second read command and second voltage information indicating a next set of read voltages among the sets of read voltages to the nonvolatile memory device in response to determining that the error correction decoding fails, and the performing of the second check read operation includes:
transmitting, at the memory controller and to the nonvolatile memory device, a third read command and third voltage information that indicates a set of read voltages used in the first check read operation and for which the error correction succeeds;
performing, at the nonvolatile memory device, a read operation by using the set of read voltages that are used in the first check read operation and for which the error correction succeeds, from among the sets of read voltages, in response to the third read command, such that third data read through the read operation are transmitted to the memory controller;
performing, at the memory controller, the error correction decoding on the third data; and
terminating, at the memory controller, the second check read operation in response to determining that the error correction decoding succeeds.