Patent ID: 11928362
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 1:
2. The fuse latch of the semiconductor device according to claim 1, wherein:
at least some parts of the second and fourth NMOS transistors are disposed in the first active region;
at least some parts of the second PMOS transistor are disposed in the second active region arranged at one side of the first active region in the first direction;
at least some parts of the first PMOS transistor are disposed in the third active region arranged at one side of the second active region in the first direction;
at least some parts of the first and third NMOS transistors are disposed in the fourth active region arranged at one side of the third active region in the first direction; and
at least some parts of the fifth and sixth NMOS transistors are disposed in the fifth active region arranged at one side of the fourth active region in the first direction.