Patent ID: 11928067
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 3:
4. The read operation circuit according to claim 3, wherein each group of read data has N bits, the N being an integer greater than 1, and the data determination module being configured to output inverted data of a group of read data inputted as a corresponding group of global bus data and set 1-bit inversion flag data corresponding to the group of read data inputted to High if the number of bits of low data in the group of read data inputted is greater than N/2, and output a group of read data inputted as a corresponding group of global bus data and set 1-bit inversion flag data corresponding to the group of read data inputted to Low if the number of bits of low data in the group of read data inputted is less than or equal to N/2.