Patent ID: 11875858
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. A non-transitory computer-readable medium storing instructions, which when executed by control logic that is operatively coupled with a memory array of a memory device, the control logic performs a plurality of memory erase operations comprising:
performing a true erase sub-operation by causing multiple pulse steps to be applied sequentially to a group of memory cells of the memory array, wherein each sequential pulse step of the multiple pulse steps occurs during a pulse-step period and at a higher voltage compared to an immediately-preceding pulse-step;
in response to receiving no erase suspend command during the true erase sub-operation, causing a true erase verify sub-operation to be performed; and
in response to detecting an erase suspend command during a pulse step, suspending the true erase sub-operation at a start of a subsequent pulse-step period after the pulse step.