Patent ID: 11869579
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A page buffer circuit comprising:
a plurality of page buffers connected to a plurality of bitlines,
wherein each of the plurality of page buffers comprises a bitline selection transistor configured to connect a corresponding bitline of the plurality of bitlines to a sensing node, a precharge circuit configured to precharge the sensing node, and a dynamic latch circuit configured to store data in a storage node,
wherein each of the plurality of page buffers is configured to refresh the data stored in the storage node through charge sharing between the storage node and the sensing node, and
wherein each of the plurality of page buffers is configured to perform a first refresh operation and a second refresh operation to refresh the data stored in the storage node,
the first refresh operation stores inverted data that are inverted from the data in the storage node, and
the second refresh operation stores the data that are inverted from the inverted data in the storage node by using the charge sharing between the storage node and the sensing node.