Patent ID: 11870880
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 19:
20. A method for digital clock data recovery comprising:
generating, by a first deserializer connected at an output of a phase detector, even deserialized signals based on up/down signals for even pulses from the phase detector;
generating, by a first vote circuit connected at an output of the first deserializer, an even up/down signal based on the even deserialized signals from the first deserializer;
controlling, by a first digital to analog converter (DAC) connected at an output of the first vote circuit, a voltage and/or frequency of a voltage controlled oscillator (VCO) based on the even up/down signal from the first vote circuit;
generating, by a second deserializer connected at the output of the phase detector, odd deserialized signals based on up/down signals for odd pulses from the phase detector;
generating, by a second vote circuit connected at an output of the second deserializer, an odd up/down signal based on the odd deserialized signals from the second deserializer; and
controlling, by a second DAC connected at an output of the second vote circuit, the voltage and/or frequency of the VCO based on the odd up/down signal from the second vote circuit.