Patent ID: 11955446
Assignee: NANYA TECHNOLOGY CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for forming a semiconductor device structure, comprising:
forming a first semiconductor die, wherein the first semiconductor die comprises a first metal layer, a first conductive via over the first metal layer, and a first conductive polymer liner surrounding the first conductive via;
forming a second semiconductor die, wherein the second semiconductor die comprises a second metal layer, a second conductive via over the second metal layer, and a second conductive polymer liner surrounding the second conductive via; and
forming a conductive structure electrically connecting the first metal layer and the second metal layer by bonding the second semiconductor die to the first semiconductor die, wherein the conductive structure is formed by the first conductive via, the first conductive polymer liner, the second conductive via, and the second conductive polymer liner, the first conductive via is bonded with the second conductive via, and the first conductive polymer liner is bonded with the second conductive polymer liner;
wherein the forming of the first semiconductor die comprises:
forming the first metal layer over a first semiconductor substrate;
forming a first dielectric layer covering the first metal layer;
etching the first dielectric layer to form a first opening exposing a portion of the first metal layer; and
forming the first conductive via and the first conductive polymer liner in the first opening to contact the portion of the first metal layer.