Patent ID: 11875848
Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. Memory device comprising:
a non-volatile memory circuit;
a buffer memory circuit comprising a volatile memory circuit;
an input-output circuit;
a first data link coupling the non-volatile memory circuit to the buffer memory circuit;
a second data link coupling the buffer memory circuit to the input-output circuit; and
a control circuit,
wherein the buffer memory circuit is adapted to implementing calculations having as operands data stored in the volatile memory circuit, the control circuit being adapted to receiving instructions via the input-output circuit, and of accordingly controlling data transfers between the non-volatile memory circuit and the buffer memory circuit via the first data link, data transfers between the buffer memory circuit and the input-output circuit via the second data link, and the implementation of calculation operations within the buffer memory circuit,
wherein the control circuit controls the buffer memory circuit to manage the volatile memory circuit like a cache memory,
and wherein the control circuit is adapted to receiving calculation instructions via the input-output circuit, each calculation instruction comprises a first field defining a type of operation to be implemented, a second field defining operand addresses, and a third field defining an address for rewriting a result of the operation.