Patent ID: 11870441
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: nan (nan)
Classification: CPC nan | IPC G  H

Claim 1:
2. The clock gating circuit of claim 1, further comprising:
a second transistor of a second type different from the first type, the second transistor including a second gate terminal, a second drain terminal and a second source terminal, the second gate terminal being coupled to at least the second node, and configured to receive the second control signal, the second drain terminal being coupled to the output node and the first drain terminal, and the second source terminal being coupled to a third node; and
a third transistor of the second type, the third transistor including a third gate terminal, a third drain terminal and a third source terminal, the third gate terminal being configured to receive the inverted clock input signal, the third drain terminal being coupled to the second source terminal and the third node, and the third source terminal being coupled to a voltage supply, the third transistor being configured to adjust the clock output signal responsive to the inverted clock input signal.