Patent ID: 11894274
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A method comprising:
forming a gate stack;
forming a dielectric fin, wherein the dielectric fin comprises:
a first portion directly underlying the gate stack; and
a second portion laterally offset from the gate stack;

forming a semiconductor fin on a side of, and parallel to, the dielectric fin, wherein the semiconductor fin comprises:
a third portion directly underlying the gate stack; and
a fourth portion laterally offset from the gate stack;

etching the second portion of the dielectric fin, wherein when the second portion of the dielectric fin is etched, the fourth portion of the semiconductor fin is exposed to a respective etching chemical, and has a lower etching rate than the second portion of the dielectric fin; and
etching the fourth portion of the semiconductor fin, wherein when the fourth portion of the semiconductor fin is etched, the second portion of the dielectric fin is exposed to a respective etching chemical, and has a lower etching rate than the fourth portion of the semiconductor fin.