Patent ID: 11864422
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for fabricating a displaying backplane, wherein the method comprises:
forming a first active layer and a second active layer on a substrate base plate, wherein a material of the first active layer and the second active layer is an oxide semiconductor, the first active layer has a first channel region and first no-channel regions that are located on two sides of the first channel region, and the second active layer has a second channel region and second no-channel regions that are located on two sides of the second channel region;
forming a first grid insulating layer covering the first active layer and the second active layer;
forming a first grid on the first grid insulating layer, wherein an orthographic projection of the first grid on the first active layer coincides with the first channel region;
performing ion implantation to the first no-channel regions, the second no-channel regions and the second channel region, to reduce oxygen-vacancy concentrations of the first no-channel regions, the second no-channel regions and the second channel region; and
forming a second grid on the first grid insulating layer, wherein an orthographic projection of the second grid on the second active layer coincides with the second channel region.