Patent ID: 11934862
Assignee: PARALLELS INTERNATIONAL GMBH
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. A non-transitory memory storing computer instructions, the computer instructions executed by one or more processors configure the one or more processors to:
establish a first guest operating system (OS) process of a plurality of guest OS processes;
establish a virtual machine monitor (VMM); and
execute a process comprising the steps of:
generating an indication of a first fault relating to an instruction of the first guest OS process of the plurality of guest OS processes;
communicating the indication of the first fault to the VMM;
handling the first fault with a virtualization event loop forming part of the VMIM;
initiating an asynchronous memory allocation request to a host operating system (OS) from the virtualization event loop;
generating a synthetic guest hardware interrupt with the virtualization event loop;
restarting the instruction of the first guest OS process of the plurality of guest OS processes with either a pending guest hardware interrupt or an emulated switch to a synthetic hardware interrupt handler in accordance with a set of guest emulation rules associated with the first computer system;
injecting the synthetic guest hardware interrupt into a guest interrupt descriptor table;
executing a guest operating system kernel which:
establishes a synthetic driver helper;
switches execution from the first guest OS process of the plurality of guest OS processes to a second guest OS process of the plurality of guest OS processes; and
receives a hardware interrupt from the non-transitory storage memory;

adding allocated memory established by the host OS in dependence upon the memory allocation request to a virtual machine working set forming part of the VMM;
mapping that portion of the virtual machine working set related to the allocated memory to a set of cache tables forming part of the VMM; and
restarting the first guest OS process of the plurality of guest OS processes based upon a rescheduling established by a scheduling operation;
wherein the injection of the synthetic guest hardware interrupt optimizes time utilization of a virtual processor of a plurality of virtual processors across a predetermined subset of the plurality of guest OS processes associated with the virtual processor of the plurality of virtual processors.