Patent ID: 11889673
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 14:
15. An integrated circuit design method comprising:
forming a first bit cell;
forming, on the first bit cell, a first bit line pair including a first bit line and a second bit line spaced apart from each other in a first direction and extending in a second direction perpendicular to the first direction;
forming, on the first bit cell, a first complementary bit line pair including a first complementary bit line and a second complementary bit line spaced apart from each other in the first direction and extending in the second direction; and
forming, on the first bit cell, a first word line between the first bit line and the second bit line and a second word line between the first complementary bit line and the second complementary bit line.