Patent ID: 11943925
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 17:
18. The semiconductor memory device of claim 15, further comprising:
a plurality of interlayer insulating layers, each being provided between a corresponding pair of two first semiconductor patterns, adjacent to each other in the second direction, among the plurality of first semiconductor patterns and between a pair of second semiconductor patterns, adjacent to each other in the second direction, among the plurality of second semiconductor patterns,
wherein each of the plurality of first bit lines is disposed between a pair of two interlayer insulating layers, adjacent to each other in the second direction, among the plurality of interlayer insulating layers, and
wherein each of the plurality of second bit lines is disposed between a pair of two interlayer insulating layers, adjacent to each other in the second direction, among the plurality of interlayer insulating layers.