Patent ID: 11950425
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A semiconductor memory device comprising:
a first mold structure stacked on a first substrate;
an upper metal line disposed on the first mold structure;
a second substrate disposed under the first substrate and including peripheral circuit elements; and
a lower metal line disposed on the peripheral circuit elements,
wherein the first mold structure includes first memory cell blocks and a first dummy block, the first dummy block includes a cell region and an extension region including a contact region and an extension through region arranged in a first direction, and a first extension through via penetrating the extension through region to connect the upper metal line and the lower metal line, whereby a target signal from one of the peripheral circuit elements is transmitted to the upper metal line.