Patent ID: 11966843
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 7:
8. A plurality of nodes comprising:
a first compute node including first instructions and first programmable circuitry to utilize the first instructions to:
construct a first batch of training data items, the first batch to include at least one data item from a first group of data items of a training data set and at least one data item from a second group of data items of the training data set, the first group of data items and the second group of data items sorted by toggle rate, the first batch of training data items having a first average toggle rate; and
train a first copy of a neural network based on the first batch;

a second compute node including second programmable circuitry to:
construct a second batch of training data items, the second batch to include at least one data item from the first group of data items of the training data set and at least one data item from the second group of data items of the training data set, the second batch having a second average toggle rate that is balanced with the first average toggle rate; and
train a second copy of the neural network based on the second batch; and

a third compute node including second instructions and third programmable circuitry to utilize the second instructions to combine a first result from the first compute node and a second result from the second compute node to update the neural network.