Patent ID: 11916042
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A semiconductor package, comprising:
a substrate;
a solder terminal on a bottom surface of the substrate;
a first semiconductor chip on a top surface of the substrate, the first semiconductor chip having a first region and a second region in a plan view;
a second semiconductor chip on a top surface of the second region of the first semiconductor chip, the second semiconductor chip exposing a top surface of the first region of the first semiconductor chip;
a third semiconductor chip on the second semiconductor chip;
a fourth semiconductor chip on the third semiconductor chip; and
a molding layer on the substrate and covering the first and fourth semiconductor chips, wherein:
the first semiconductor chip includes:
a first pad on the top surface of the first region of the first semiconductor chip and electrically connected to the substrate;
a second pad on the top surface of the first region of the first semiconductor chip and electrically connected to the second semiconductor chip;
a third pad on the top surface of the first region of the first semiconductor chip and electrically connected to the third semiconductor chip; and
a fourth pad on the top surface of the first region of the first semiconductor chip and electrically connected to the fourth semiconductor chip,

the first region of the first semiconductor chip is adjacent to a first sidewall of the first semiconductor chip,
the first pad is between the second pad and the first sidewall of the first semiconductor chip in a plan view,
the third pad is between the first pad and the second pad, and
the fourth chip pad is between the first pad and the third pad.