Patent ID: 11889096
Assignee: INTEL CORPORATION
Field: Audio-visual technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 10:
11. The system of claim 2, the one or more processors to:
decode the bitstream to generate third and fourth blocks of the video frame, wherein the third and fourth blocks comprise the first and second video coding modes, respectively, and wherein the first and second blocks comprise region of interest blocks and the third and fourth blocks comprises non-region of interest blocks;
apply the deep learning network to the third block in response to the first coding mode to generate a third output block at the second resolution; and
bypass application of the deep learning super-resolution network to the fourth block and retrieve a prior fourth output block at the second resolution for the fourth block in response to the second coding mode, wherein the one or more processors to generate the output video frame comprises the one or more processors to merge the third and fourth output blocks into the output video frame.