Patent ID: 11929927
Assignee: INTEL CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 5:
6. A method comprising:
at a network interface device in a data center:
based on receipt of a packet:
copying a portion of the received packet via a first interface to a central processing unit (CPU) interconnect to forward to a first memory buffer accessible by a CPU connected to the CPU interconnect and

based on receipt of a second packet:
copying, by a direct memory access (DMA) circuitry, a portion of the second received packet via a second interface to an accelerator fabric to forward to a second memory buffer accessible by an accelerator device connected to the accelerator fabric, wherein the accelerator device comprises a field programmable gate array (FPGA) and an application specific integrated circuit (ASIC) and
based on a request to transmit a third packet that comprises data generated by the accelerator device, copying the data via the second interface and the accelerator fabric and cause transmission of the third packet by the network interface device.