Patent ID: 11948624
Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A memory array circuit comprising:
a column circuit comprising:
a plurality of bit cell circuits;
a bit line;
a complement bit line;
a first voltage supply line;
a first voltage supply circuit coupled to the first voltage supply line and a first voltage rail;
a second voltage supply line; and
a second voltage supply circuit coupled to the second voltage supply line and the first voltage rail;
wherein:
each of the plurality of bit cell circuits coupled to the first voltage supply line, the second voltage supply line, and a second voltage rail, and comprising:
a cross-coupled inverter circuit comprising:
 a data node; and
 a complement data node;
a first pass-gate coupled to the data node and the bit line; and
a second pass-gate coupled to the complement data node and the complement bit line; and

a column set input coupled to the first voltage supply circuit includes a column set signal to control the first voltage supply circuit to decouple the first voltage supply line from the first voltage rail,
wherein the second voltage supply circuit comprises a transistor comprising a first terminal coupled to the first voltage rail, a second terminal coupled to the second voltage supply line, and a gate coupled directly to the second voltage rail.