Patent ID: 11881402
Assignee: APPLIED MATERIALS, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for forming a nanostructure on a substrate, the method comprising:
performing a first lithography-and-etch process, comprising patterning a mandrel layer disposed on a first dielectric layer;
performing a spacer patterning process, comprising forming a spacer layer on sidewalls of the patterned mandrel layer;
performing a first gap-filling process, comprising forming a gap-filling layer in openings of the spacer layer on the first dielectric layer and over the patterned mandrel layer;
performing a second lithography-and-etch process, comprising patterning the gap-filling layer and further patterning the patterned mandrel layer;
performing a second gap-filling process, comprising further forming the gap-filling layer in openings of the twice patterned mandrel layer; and
performing a spacer removing process, comprising removing the patterned spacer layer and the twice patterned mandrel layer.