Patent ID: 11961769
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 17:
18. A method of forming an integrated circuit, the method comprising:
receiving a design layout of the integrated circuit having an inverter that includes a n-type field effect transistor and a p-type field effect transistor sharing a gate;
modifying the design layout such that the gate of the inverter has an end aligned to a common edge of a n-type doped well (N-well) and a p-type doped well (P-well); and
fabricating the integrated circuit according to the modified design layout, wherein fabricating of the integrated circuit includes:
forming the N-well and P-well in a semiconductor substrate;
forming a deep trench isolation feature extending through the common edge of the N-well and P-well;
forming the gate over the N-well and the P-well; and
forming a gate-cut feature extends through the gate such that the gate-cut feature is vertically aligned with the common edge of the N-well and P-well.