Patent ID: 11917053
Assignee: INTEL CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. An apparatus, comprising:
a secure hash algorithm-2 (SHA2) accelerator;
a secure hash algorithm-3 (SHA3) accelerator configurable to perform at least one of a SHAKE-128 function or to perform a SHAKE-256 operation and comprising:
a bit state register to receive a first set of inputs for a plurality of chain functions, a second set of inputs for hashes involved in an L-Tree computation, and a third set of inputs for a Merkle tree root node computation;
a processor to:
receive a 256 bit message input;
perform a set of 24 SHA3 rounds; and
generate a 128 bit output; and

a register bank shared between the SHA2 accelerator and the SHA3 accelerator.