Patent ID: 11934867
Assignee: NVIDIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. A system comprising:
a memory;
a processing cluster comprising a plurality of hardware units; and
a graphics processing unit to:
execute an application stored in the memory in parallel on the plurality of hardware units, wherein on each of the hardware units the application is executed in a single instruction multi-threaded (SIMT) manner as a plurality of threads;
on each of the hardware units, split the execution of the plurality of threads into sequentially executed groups of threads upon the occurrence of thread divergence, each of the groups being a shard;
detect a long stall in any one of the shards as a result of encountering a long stall hint instruction in the any one of the shards;
in response to detecting the long stall in any one of the shards, switch execution to a different one of the shards on a same hardware unit of the plurality of hardware units;
wherein the long stall hint instruction is encountered between a long-latency producer instruction and a consumer instruction that utilizes a result of the long-latency producer instruction.