Patent ID: 11901227
Assignee: LAM RESEARCH CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H  C | IPC C  H

Claim 17:
18. A method comprising:
providing a 3-D structure of a partially manufactured semiconductor substrate, the 3-D structure comprising sidewalls, a plurality of openings in the sidewalls leading to a plurality of features having a plurality of interior regions fluidically accessible through the openings, wherein the plurality of features each comprise a constriction formed by a pillar of the 3-D structure, the plurality of interior regions comprising a tungsten layer deposited on a nucleation layer;
exposing the tungsten layer of the 3-D structure to diborane;
after exposing the tungsten layer of the 3-D structure to diborane, exposing the 3-D structure to nitrogen trifluoride (NF3) to preferentially inhibit tungsten nucleation at the constrictions; and
after exposing the 3-D structure to NF3, depositing tungsten in the plurality of features, wherein tungsten is preferentially depositing further within the plurality of features than at the constrictions.