Patent ID: 11869941
Assignee: GLOBALFOUNDRIES U.S. INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A method comprising:
forming a base layer on a semiconductor substrate, the base region including a first base portion and second base portions, wherein the first base portion is positioned laterally between the second base portions;
forming an isolation layer on the base region, the isolation layer including a first isolation portion on the first base portion and second isolation portions on the second base portions;
forming an emitter stack comprising:
a dielectric layer, wherein the dielectric layer is on the first isolation portion of the isolation layer and aligned above the first base portion;
an emitter region comprising:
a first emitter portion extending through the dielectric layer, wherein the first emitter portion extends through the dielectric layer and the first isolation portion of the isolation layer to the first base portion; and
a second emitter portion on the first emitter portion and further extending laterally onto the dielectric layer; and

an additional dielectric layer on the second emitter portion,
wherein the dielectric layer, the second emitter portion, and the additional dielectric layer are wider than the first emitter portion, and
wherein at least a section of the second emitter portion is narrower than the dielectric layer and the additional dielectric layer; and

covering the emitter stack with dielectric material.