Patent ID: 11892503
Assignee: TOSHIBA TEC KABUSHIKI KAISHA
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A semiconductor device, comprising:
a first semiconductor chip in a package;
a second semiconductor chip in the package;
a first pad on the first semiconductor chip and electrically connected to a node between a power supply pad and a ground pad on the first semiconductor chip;
a second pad on the second semiconductor chip;
a third pad on the second semiconductor chip;
an internal wiring connecting the first pad to the second pad within the package;
a power supply circuit on the second semiconductor chip configured to supply a current to the second pad;
a switch on the second semiconductor chip between the second pad and the power supply circuit to connect or disconnect the second pad from the power supply circuit; and
a control circuit on the second semiconductor chip configured to output:
a first control signal for controlling ON and OFF states of the switch in response to a test signal supplied to the third pad, and
a second control signal to the power supply circuit to cause the power supply circuit to output current.