Patent ID: 11960857
Assignee: ACHRONIX SEMICONDUCTOR CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A circuit comprising:
a first arithmetic logic unit (ALU) slice comprising:
a plurality of lookup tables (LUTs) including a first LUT and a second LUT;
input connections configured to receive as input a portion of a first operand, a portion of a second operand, a first carry-in bit from a second ALU slice, and a second carry-in bit from a third ALU slice;
a multiplexer controlled by the second carry-in bit; and
output connections configured to provide, as output, a set of sum bits and a carry-out bit, the sum bits containing the sum of the input portion of the first operand, the input portion of the second operand, and the first carry-in bit;

wherein each of the plurality of LUTs receives the portion of the first operand and portion of the second operand as inputs.