Patent ID: 11966310
Assignee: MELLANOX TECHNOLOGIES, LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. A method in an Integrated Circuit (IC) that includes one or more functional hardware circuits, the method comprising:
handling events occurring in the one or more functional hardware circuits using one or more processor cores;
delivering the events, from the one or more functional hardware circuits to the one or more processor cores, by a cause tree circuit comprising leaf nodes, middle nodes and a root node, wherein delivering the events comprises collecting the events from the one or more functional hardware circuits using storage elements in the leaf nodes of the cause-tree circuit, coalescing the collected events using coalescing circuits in the middle nodes of the cause-tree circuit, and delivering the coalesced events to the root node of the cause-tree circuit;
buffering a plurality of the events delivered to the root node in a memory buffer coupled to the root node of the cause-tree circuit, so as to trigger the processor cores to handle the buffered events; and
analyzing a performance of the cause-tree circuit based on the events buffered in the memory buffer.