Patent ID: 11961881
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A semiconductor structure, comprising:
a semiconductor substrate, wherein at least discrete conducting layers are comprised in the semiconductor substrate;
multiple discrete supporting structures, located on the semiconductor substrate; and
capacitor structures supported by the supporting structures, wherein each capacitor structure comprises:
a lower electrode, located on a sidewall of a corresponding one of the supporting structures;
a bottom conducting layer, located only between the semiconductor substrate and the supporting structure and configured to electrically connect the lower electrode and the conducting layer; wherein the supporting structure is on the bottom conducting layer;
a capacitor dielectric layer, located at a top of the supporting structure, a sidewall of the lower electrode, and a bottom of a gap between the supporting structures; and
an upper electrode, located on the capacitor dielectric layer.