Patent ID: 11960897
Assignee: ADVANCED MICRO DEVICES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. A system comprising:
a first processor; and
a second processor, operatively coupled to the first processor, comprising:
a plurality of parallel instruction pipes;
a register file comprising at least one shared register file read port configured to be shared across at least two pipes of the plurality of parallel instruction pipes, wherein at least two pipes of the plurality of parallel instruction pipes are configured to read from a plurality of non-shared register file read ports of the register file and read from the at least one shared register file read port; and
control logic, operatively coupled to the register file, and configured to control the at least two pipes of the parallel instruction pipes to read from the at least one shared register file read port and control at least one of the plurality of parallel instruction pipes to write data for the first processor.