Patent ID: 11886272
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 7:
8. A method of operating a memory device, comprising:
entering a first mode of operation;
while in the first mode of operation, transferring data from a memory array via each of a first plurality of links;
entering a second mode of operation;
while in the second mode of operation, transferring data via each of a second plurality of links, the second plurality of links being a proper subset of the first plurality of links and, using steering circuitry coupled to the memory array and to the first plurality of links, loop-back data via at least one link of the first plurality of links that is not one of the second plurality of links; and
while in the second mode of operation, updating a first timing adjustment parameter for the at least one link of the first plurality of links that is not one of the second plurality of links.