Patent ID: 11900996
Assignee: GLOBALFOUNDRIES U.S. INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. The memory structure of claim 19,
wherein, when a first wordline voltage on the wordline switches to a positive supply voltage level and the mode select signal indicates the read mode, output signals at the first output node and the third output node are high and an output signal at the second output node is low so the first voltage boost line, the second voltage boost line and the third voltage boost line are charged creating coupling capacitances between the first wordline and both the first voltage boost line and the second voltage boost line to increase the first wordline voltage on the first wordline above the positive supply voltage level and creating coupling capacitances between the cell supply line and both the second voltage boost line and the third voltage boost line to increase a cell supply voltage on the cell supply line above the positive supply voltage level, and
wherein, when the first wordline voltage on the wordline switches to the positive supply voltage level and the mode select signal indicates the write mode, an output signal at the first output node is high and output signals at the second output node and the third output node are low so the first voltage boost line is charged creating a coupling capacitance between the first wordline and the first voltage boost line to increase the first wordline voltage on the first wordline above the positive supply voltage level without increasing the cell supply voltage on the cell supply line,
wherein, when a second wordline voltage on the second wordline switches to the positive supply voltage level and the mode select signal indicates the read mode, output signals on the second output node and the third output node are high and an output signal on the first output node is low so the fourth voltage boost line, the second voltage boost line, and the third voltage boost line are charged creating coupling capacitances between the second wordline and both the fourth voltage boost line and the third voltage boost line to increase the second wordline voltage on the second wordline above the positive supply voltage level and creating coupling capacitances between the cell supply line and both the second voltage boost line and the third voltage boost line to increase the cell supply voltage on the cell supply line above the positive supply voltage level, and
wherein, when the second wordline voltage on the second wordline switches to the positive supply voltage level and the mode select signal indicates the write mode, an output signal on the second output node is high and output signals on the first output node and the third output node are low so the fourth voltage boost line is charged creating a coupling capacitance between the second wordline and the fourth voltage boost line to increase the second wordline voltage on the first wordline above the positive supply voltage level without increasing the cell supply voltage, and
wherein, when a first wordline voltage on the first wordline and a second wordline voltage on the second wordline are below the positive supply voltage level, output signals on the first output node, the second output node and the third output node are low so the first voltage boost line, the second voltage boost line, the third voltage boost line and the fourth voltage boost line are not charged by the voltage boost circuit.