Patent ID: 11955549
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. A manufacturing method of a semiconductor device, comprising:
forming a field-effect transistor over a substrate;
forming a lower interconnection structure over the field-effect transistor;
forming a first dielectric layer over the lower interconnection structure;
forming a channel layer and a high-k dielectric layer sequentially on the first dielectric layer;
patterning the channel layer and the high-k dielectric layer to form a channel pattern and a high-k dielectric pattern sequentially on the first dielectric layer;
forming a second dielectric layer over the channel pattern and the high-k dielectric pattern;
patterning the second dielectric layer to form a gate trench;
patterning the second dielectric layer and the high-k dielectric pattern to form two contact openings;
forming a gate pattern in the gate trench and forming two contacts in the contact openings;
forming a ferroelectric tunnel junction electrically connected to one of two contacts, wherein the ferroelectric tunnel junction comprises a layered structure comprising crystalline oxide layers and ferroelectric layers alternately stacked.