Patent ID: 11930631
Assignee: FUJIAN JINHUA INTEGRATED CIRCUIT CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A method of fabricating a semiconductor memory device, comprising:
providing a substrate;
forming a plurality of bit lines separately disposed on the substrate;
forming a plurality of plugs on the substrate, the bit lines and the plugs being alternately arranged with each other; and
forming a spacer structure on the substrate, between each of the bit lines and each of the plugs, wherein the spacer structure comprises a first air gap layer, a first spacer and a second air gap layer, and the first air gap layer, the first spacer and the second air gap layer are sequentially stacked between sidewalls of the bit lines and the plugs, wherein the spacer structure further comprises a second spacer, the first air gap layer is disposed between the first spacer and the second spacer, and a width of the second spacer is smaller than a width of the first spacer.