Patent ID: 11934671
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory system comprising:
a memory controller;
an interface for communication between the memory controller and a host; and
a decoder coupled to the interface, the decoder configured to perform operations comprising:
prior to providing to the memory controller a decoded message that comprises a request to write to a command register of the memory controller:
inspecting the decoded message to determine whether the request to write to the command register is associated with an operation that corresponds to an advertised status of the memory system, the inspecting of the decoded message comprising determining whether a message attribute of the decoded message is in a set of attributes that corresponds to the advertised status, and the advertised status being accessible by the host via the interface; and
modifying the advertised status of the memory system in response to determining that the message attribute is in the set of attributes; and
providing the decoded message to the memory controller for executing the request.