Patent ID: 11971470
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Measurement (Instruments)
Classification: CPC G  H | IPC G  H

Claim 7:
8. A circuit, comprising:
memory configured to store an N×M range matrix indexed by N velocity bins and M antenna combinations, and a M×S steering matrix indexed by the M antenna combinations and S hypothesis angles;
first and second buffers;
address generator circuitry operably coupled to the memory and configured to:
generate addresses for respective unique X×Y range slices to be successively accessed from the N×M range matrix and stored in the first buffer, in which X is a lesser multiple of N and Y is a lesser multiple of M; and
generate addresses for respective unique Y×Z steering vector slices to be successively accessed from the M×S steering matrix and stored in the second buffer, in which Z is a lesser multiple of S;
first selector logic circuitry configured to:
access the first and second buffers in response to one or more first selection signals to successively output first data, each including a respective unique X×Y range slice, from the first buffer, and to successively output second data, each including a respective unique Y×Z steering vector slice, from the second buffer;

multiplier and accumulator (MAC) circuitry coupled to the selector logic circuitry and configured to:
multiply respective pairs of first and second data to generate respective multiplication results, and
generate respective summation results;

second selector logic circuitry coupled to the first selector logic circuitry and the MAC circuitry and configured to successively output at each processing iteration one of the first data, the multiplication result, and the summation result; and
a processing circuit to process the successive outputs of the second selector logic circuit.