Patent ID: 11907635
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 19:
20. A modeling circuit of a field effect transistor comprising:
a first n-type metal oxide semiconductor field effect transistor (NMOSFET) having a drain electrode, a source electrode, a gate electrode, and a bulk electrode;
a first resistor connected between the drain electrode of the first NMOSFET and a first node;
a second resistor connected between the source electrode of the first NMOSFET and a second node;
a third resistor connected between the first node and a drain terminal for external connection;
a fourth resistor connected between the second node and a source terminal for external connection;
a first most exquisite transistor model-bipolar junction transistor (MEXTRAM-BJT) having a first collector electrode connected to the first node, a first emitter electrode connected to the second node, and a first base electrode;
a second MEXTRAM-BJT having a second collector electrode connected to the second node, a second emitter electrode connected to the first node, and a second base electrode connected to the bulk electrode of the first NMOSFET and the first base electrode of the first MEXTRAM-BJT;
a substrate resistor connected between the first and second base electrodes and a bulk external connection terminal;
a first diode and a fifth resistor connected in series between the first node and the bulk external connection terminal; and
a second diode and a sixth resistor connected in series between the second node and the bulk external connection terminal,
wherein the first and second resistors correspond to MOSFET active resistances of the first NMOSFET, and
the third and fourth resistors correspond to parasitic BJT active resistances of the first and second MEXTRAM-BJTs.