Patent ID: 11916550
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An integrated circuit, comprising:
a clock generator comprising a first NAND gate configured to generate a first latching clock signal and a second NAND gate configured to generate a second latching clock signal, each in response to a select signal and a clock signal having a clock signal waveform, wherein the clock generator is configured to generate each of the first latching clock signal and the second latching clock signal having the clock signal waveform; and
a multiplexing latch circuit configured to select either first data on a first data line or second data on a second data line based on the first latching clock signal and the second latching clock signal, and to store and output the selected data.