Patent ID: 11961567
Assignee: PUFSECURITY CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. The key storage device of claim 1,
wherein the first output transistor and the second output transistor are NMOS transistors, the first inverter further comprises a first PMOS transistor having a third threshold voltage, the second inverter comprises a second PMOS transistor having a fourth threshold voltage;
wherein the first setting circuit comprises:
a third NMOS transistor, having the second threshold voltage, comprising a drain for outputting the first setting voltage; and
a third PMOS transistor, having the fourth threshold voltage;
wherein the drain and a gate of the third NMOS are shorted with a drain and a gate of the third PMOS transistor;
wherein the second setting circuit comprises:
a fourth NMOS transistor, having the first threshold voltage, comprising a drain for outputting the second setting voltage; and
a fourth PMOS transistor, having the third threshold voltage;
wherein the drain and a gate of the fourth NMOS transistor are shorted with a drain and a gate of the fourth PMOS transistor;
wherein an absolute value of the fourth threshold voltage is lower than an absolute value of the third threshold voltage.