Patent ID: 11949416
Assignee: SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 3:
4. The composite logic gate circuit according to claim 1, wherein the first logic gate circuit is a NAND gate circuit, the NAND gate circuit comprises:
a fifth PMOS transistor, a fifth NMOS transistor, a sixth PMOS transistor, and a sixth NMOS transistor,
wherein a source of the fifth PMOS transistor is coupled to the power input terminal, a drain of the fifth PMOS transistor is coupled to drains of the sixth PMOS transistor and the fifth NMOS, and a gate of the fifth PMOS transistor is configured to receive the first input signal,
wherein a source of the sixth PMOS transistor is coupled to the power input terminal, the drain of the sixth PMOS transistor is coupled to the drains of the fifth PMOS transistor and the fifth NMOS transistor, and a gate of the sixth PMOS transistor is configured to receive the second input signal,
wherein a source of the fifth NMOS transistor is coupled to a drain of the sixth NMOS transistor, the drain of the fifth NMOS transistor is coupled to the drains of the fifth PMOS transistor and the sixth PMOS transistor, and a gate of the fifth NMOS transistor is configured to receive the first input signal,
wherein a source of the sixth NMOS transistor is coupled to the ground terminal, the drain of the sixth NMOS transistor is coupled to the source of the fifth NMOS transistor, and a gate of the sixth NMOS transistor is configured to receive the second input signal,
wherein a node where the drains of the fifth PMOS transistor, the sixth PMOS transistor, and the fifth NMOS transistor are coupled to each other is configured to output the first output signal.