Patent ID: 11862273
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. A storage device comprising:
a nonvolatile memory device including:
a memory cell array including a normal cell region, a parity cell region and a redundancy cell region associated with repairing defective columns of the normal cell region and the parity cell region, the memory cell array including a plurality of nonvolatile memory cells coupled to first bit-lines and second bit-lines, the first bit-lines connected to the normal cell region and the parity cell region, the second bit-lines connected to the redundancy cell region;
a page buffer circuit connected to the memory cell array through the first bit-lines and the second bit-lines; and
an address decoder connected to the memory cell array through a plurality of word-lines, and

a memory controller configured to control the nonvolatile memory device,
wherein the memory controller includes an error correction code (ECC) engine configured to generate parity data by performing an ECC encoding on user data to be stored in the normal cell region,
wherein the memory controller is configured to:
store the user data in the normal cell region,
assign additional column addresses to the second bit-lines, and
store the parity data in a region corresponding to the second bit-lines.