Patent ID: 11949793
Assignee: INTEL CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. At least one non-transitory machine-readable storage medium comprising instructions that, when executed by at least one processor, causes the at least one processor to:
receive a control bit sequence for scrambling a message at a single transceiver, the control bit sequence including at least a control bit corresponding to a message bit of the message, wherein the control bit has a first bit value or a second bit value different from the first value;
determine whether the control bit has the first bit value or the second bit value;
transmit the message bit at a first voltage level when the control bit has the first bit value from the single transceiver, wherein the first voltage level is a normal or standard voltage level to transmit the message bit over a high Controller Area Network (CAN) line or a low CAN line of a CAN bus; and
transmit the message bit at a second voltage level different from the first voltage level when the control bit has the second bit value from the single transceiver, wherein the second voltage level is an inverted or flipped voltage level relative to the normal or standard voltage level to transmit the message bit.