Patent ID: 11966582
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 2:
3. A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, wherein the controller is configured to:
receive a read command to read data from the memory device or a write command to write data to the memory device from a host device;
determine whether a bottleneck exists in a data/control path between the host device and the memory device, wherein the bottleneck exists either in an input queue corresponding to a hardware module of a plurality of hardware modules or in the hardware module of the plurality of hardware modules, wherein the plurality of hardware modules in the data/control path between the host device and the memory device comprises a plurality of random access memories (RAMs);
determine a fullness of a RAM of the plurality of RAMs in the data/control path between the host device and the memory device, wherein the fullness is a percentage of a capacity of the RAM of the plurality of RAMs that is utilized, wherein each RAM of the plurality of RAMs is configured for a single purpose;
execute a bottleneck release operation when the bottleneck exists in the data/control path between the host device and the memory device, wherein the bottleneck release operation is dependent on whether the bottleneck exists in the input queue or in the hardware module; and
reconfigure another RAM of the plurality of RAMs to a different purpose other than the single purpose when the fullness of the RAM of the plurality of RAMs is greater than a threshold fullness.