Patent ID: 11963411
Assignee: JAPAN DISPLAY INC.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 0:
1. A TFT array substrate comprising:
a plurality of first wirings which are provided on a first layer and each of which is arranged parallel to a first direction in a first area, and which are arranged on a second layer in a second area adjacent to the first area;
a second wiring which is provided in the first layer and is arranged between the plurality of first wirings in the first area and which is provided on a layer different from the second layer in the second area; and
a third wiring which is provided on the first layer and arranged between the plurality of first wirings in the first area and which is provided on a layer different from the second layer and arranged to intersect with at least a portion of the plurality of first wirings in a plan view, in the second area, wherein
a portion of the plurality of first wirings is arranged to be inclined to the same side in the first direction in the second area,
the second wiring is arranged to intersect with a portion of the plurality of first wirings in a plan view, in the second area, and
a width of one of the plurality of second wirings in the first area is smaller than that in the second area.