Patent ID: 11934320
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. An apparatus comprising:
processing circuitry to perform data processing in response to instructions; and
address translation circuitry to perform two-stage address translation to translate a virtual address to a physical address, where a mapping of the virtual address to the physical address depends on stage 1 translation data for mapping the virtual address to an intermediate address and stage 2 translation data for mapping the intermediate address to the physical address; in which:
in response to a first type of translation lookaside buffer (TLB) invalidation instruction specifying a target intermediate address, the processing circuitry is configured to issue a first TLB invalidation command to at least one TLB for storing translation entries derived from at least one of the stage 1 translation data and the stage 2 translation data, the first TLB invalidation command requesting that said at least one TLB invalidates a translation entry stored in said at least one TLB, wherein the translation entry satisfies a first set of one or more invalidation conditions, the first set including an intermediate-address-based condition which is satisfied when the translation entry corresponds to the target intermediate address; and,
in response to a second type of TLB invalidation instruction, the processing circuitry is configured to issue a second TLB invalidation command requesting that:
if said at least one TLB includes a first type of TLB, the first type of TLB should invalidate one or more translation entries included in the first type of TLB which satisfy a second set of one or more invalidation conditions, where said first type of TLB is a type of TLB which is configured to ignore the first TLB invalidation command and which is configured to store combined stage-1-and-2 entries specifying virtual-to-physical address translation mappings which depend on both the stage 1 translation data and the stage 2 translation data; and,
if said at least one TLB includes a second type of TLB other than said first type of TLB, the second type of TLB should retain one or more translation entries included in the second type of TLB which satisfy the second set of one or more invalidation conditions, where the second type of TLB is configured to store translation entries specifying at least one of: virtual-to-physical address translation mappings, virtual-to-intermediate address translation mappings, or intermediate-to-physical address translation mappings.