Patent ID: 11966604
Assignee: SILICON MOTION, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 10:
11. An apparatus for programming data into flash memory, comprising:
a processing unit;
a routing engine, coupled to the processing unit;
an accelerator, coupled to the processing unit and the routing engine,
wherein the accelerator is arranged operably to: obtain an execution table, a first mid-end parameter set, a first back-end parameter set, a second mid-end parameter and a second back-end parameter set from the processing unit, wherein the execution table comprises a first virtual carrier and a second virtual carrier, the first virtual carrier comprises first cargo flags, the first mid-end parameter set and the first back-end parameter set are associated with the first virtual carrier, the first cargo flags indicate data of which cargos in the first virtual carrier needs to be prepared in a front-end processing stage, the second virtual carrier comprises second cargo flags, the second mid-end parameter set and the second back-end parameter set are associated with the second virtual carrier, the second cargo flags indicate data of which cargos in the second virtual carrier needs to be prepared in the front-end processing stage, and the execution table indicates that data related to the first virtual carrier need to go through a mid-end processing stage and a back-end processing stage earlier than data related to other virtual carriers in the execution table,
wherein the routing engine is arranged operably to: obtain the first virtual carrier, a first front-end parameter set associated with the first virtual carrier, the second virtual carrier, a second front-end parameter set associated with the second virtual carrier from the processing unit;
drive a host interface (I/F) to obtain data associated with all cargos in the second virtual carrier and store obtained data in a designated address of a random access memory (RAM) according to the second front-end parameter set; and update the second cargo flags with third cargo flags to indicate that data associated with all the cargos in the second virtual carrier are prepared in the front-end processing stage,
wherein the accelerator is arranged operably to: determine that data associated with any cargo in the first virtual carrier hasn't been prepared according to information of the first cargo flags, and disallow the second virtual carrier to proceed to the mid-end processing stage and/or the back-end processing stage after obtaining the third cargo flags of the second virtual carrier from the routing engine.