Patent ID: 11923205
Assignee: WINBOND ELECTRONICS CORP.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for manufacturing a semiconductor device, comprising:
providing a wafer-bonding stack structure comprising a sidewall layer and an exposed first component layer;
forming a photoresist layer on the first component layer;
performing an edge trimming process to at least remove the sidewall layer; and
removing the photoresist layer,
wherein a method for manufacturing the wafer-bonding stack structure comprises:
providing a first wafer structure and a second wafer structure, wherein the first wafer structure comprises a first substrate and the first component layer formed on the first substrate, and the second wafer structure comprises a second substrate and a second component layer formed on the second substrate;
bonding the first wafer structure and the second wafer structure, wherein the first component layer and the second component layer face each other, and at least one interconnection layer is used to bond the first component layer and the second component layer;
performing a thinning process to thin the first substrate;
trimming the periphery of the stacked thinned first substrate, first component layer, interconnection layer, second component layer, to obtain a trimmed peripheral wall;
depositing a protective layer to at least cover the thinned first substrate and the trimming peripheral wall, wherein the protective layer comprises a top layer and the sidewall layer, the top layer is arranged on the thinned first substrate, and the sidewall layer is arranged around the trimming peripheral wall; and
removing the top layer and the thinned first substrate to expose the first component layer.