Patent ID: 11917809
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 11:
12. The apparatus of claim 10, further comprising:
a plurality of first word line conductors, each first word line conductor of the plurality of first word line conductors operable to activate the respective fifth transistors of a row of first memory cells of the set of first memory cells;
a plurality of second word line conductors, each second word line conductor of the plurality of second word line conductors operable to activate the respective sixth transistors of a row of second memory cells of the set of second memory cells;
a plurality of third word line conductors, each third word line conductor of the plurality of third word line conductors operable to activate the respective seventh transistors of a row of third memory cells of the set of third memory cells; and
a plurality of fourth word line conductors, each fourth word line conductor of the plurality of fourth word line conductors operable to activate the respective eighth transistors of a row of fourth memory cells of the set of fourth memory cells.