Patent ID: 11921660
Assignee: HUAWEI TECHNOLOGIES CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 14:
15. The equalization time configuration apparatus of claim 12, wherein the processor is further configured to:
configure both the first equalization time and the second equalization time as a default value when both the first working PHY type and the second working PHY type are the SR; and
when both the first working PHY type and the second working PHY type are the LR:
read a third equalization time of the slave chip in the third phase;
write the third equalization time into the master chip to set the third equalization time as the first equalization time;
read a fourth equalization time of the master chip in the fourth phase; and
write the fourth equalization time into the slave chip to set the fourth equalization time as the second equalization time.