Patent ID: 11937435
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Field: nan (nan)
Classification: CPC H | IPC H

Claim 8:
9. A method of fabricating a semiconductor structure, comprising:
forming a lower tier of magnetic random access memory (MRAM) cells above a first set of landing pads of a bottom metal level;
forming lower vias through a first interlayer dielectric (ILD) covering the first tier of MRAM cells, wherein the lower vias contact a second set of landing pads of the bottom metal level;
forming an upper tier of MRAM cells on the lower vias;
covering the upper tier of MRAM cells with a second ILD;
forming upper vias through the second ILD and the first ILD, wherein the upper vias contact the lower tier of MRAM cells;
forming a top metal level above the second set of vias and the second tier of MRAM cells.