Patent ID: 11924319
Assignee: NEC PLATFORMS, LTD.
Field: Telecommunications (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 8:
9. A time synchronization method comprising:
generating, by a first digital controlled oscillator included in a frequency synchronizing PLL (Phase Locked Loop), control information synchronized with a frequency of a synchronous Ethernet (registered trademark) signal received from a time master device;
generating, by a second digital controlled oscillator included in a time synchronizing PLL, time control information synchronized with a time based on a time packet received from the time master device; and
generating a time synchronization signal based on the generated frequency control information and the generated time control information, wherein
the first digital controlled oscillator and the second digital controlled oscillator perform numerical calculation processing to generate the frequency control information that is numerical information and the time control information that is numerical information, respectively,
in the generating of the time synchronization signal, the time synchronization signal is generated based on an addition value obtained by adding the frequency control information and the time control information,
the frequency synchronizing PLL and the time synchronizing PLL constitute a high-pass filter for removing a low frequency component of the synchronous Ethernet signal.