Patent ID: 11973082
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 0:
1. An integrated circuit device comprising:
a first region comprising a semiconductor on insulator (SOI) substrate layer comprising a base substrate layer, an insulating substrate layer, and a cover substrate layer;
a second region comprising a semiconductor substrate layer;
a plurality of first fin-type active areas in defined by a first plurality of trenches in the first region, the first fin-type active areas protruding from a main surface of the SOI substrate layer and extending in a first horizontal direction;
a plurality of second fin-type active areas defined by a second plurality of trenches in the second region, the second fin-type active areas protruding from a main surface of the semiconductor substrate layer and extending in the first horizontal direction;
a plurality of nanosheet stacked structures above the plurality of first fin-type active areas and the plurality of second fin-type active areas, each of the plurality of nanosheet stacked structures comprising a plurality of nanosheets extending in parallel with each other and spaced apart from upper surfaces of the plurality of first fin-type active areas and the plurality of second fin-type active areas;
a plurality of first source/drain regions between adjacent nanosheet stacked structures in the first region, each of the first source/drain regions extending into the SOI substrate layer and in contact with the insulating substrate layer and having a lower surface at a first vertical level; and
a plurality of second source/drain regions in the second region, each of the plurality of second source/drain regions extending into the semiconductor substrate layer and having a lower surface at a second vertical level that is farther from the main surface of the SOI substrate layer and the main surface of the semiconductor substrate layer than the first vertical level.