Patent ID: 11942985
Assignee: nan
Field: Telecommunications (Electrical engineering)
Classification: CPC H | IPC H

Claim 2:
3. The 10G rate OLT terminal transceiver integrated chip based on XGSPON and DFB laser according to claim 2, wherein the fast recovery module is built-in or external to the burst mode receiver RX, and the fast recovery module includes resistors R7, R8, R9, R10, and switches S1 and S2,
when the fast recovery module is external to the burst mode receiver RX, a non-inverting output terminal of the burst transimpedance amplifier TIA is connected to one end of the resistor R10 of the fast recovery module, one end of the resistor R8 and a non-inverting input pin RX_INP of the chip through an AC coupling capacitor C9;
an inverting output terminal of the burst transimpedance amplifier TIA is connected to one end of the resistor R9 and one end of the resistor R7 of the fast recovery module, and an inverting input pin RX_INN of the chip through the AC coupling capacitor C8;
a non-inverting input pin RX_INP of the chip and an inverting input pin RX_INN of the chip are connected to a non-inverting input terminal and an inverting input terminal of the pre-amplifier Pre_Amplifier respectively;
another end of the resistor R10 is connected to one end of the switch S1;
another end of the resistor R9 is connected to one end of the switch S2;
control ends of the switches S1 and S2 are connected to a reset signal line LA_RESET simultaneously; and
a reference voltage pin Vref of the burst mode receiver RX is simultaneously connected to another end of the resistor R7, another end of the R8, another end of the switch S1 and another end of the switch S2,
when the fast recovery module is built in the burst mode receiver RX, a non-inverting output terminal and an inverting output terminal of the burst transimpedance amplifier TIA are connected to a non-inverting input pin RX_INP and an inverting input pin RX_INN of the chip through AC coupling capacitors C9 and C8;
inside the chip, the non-inverting input pin RX_INP of the chip is connected to one end of the resistor R10, one end of the resistor R8 and a non-inverting input terminal of the pre-amplifier Pre_Amplifier;
the inverting input pin RX_INN of the chip is connected to one end of the resistor R9, one end of the resistor R7 and an inverting input of the pre-amplifier Pre_Amplifier;
another end of the resistor R10 is connected to one end of the switch S1;
another end of the resistor R9 is connected to one end of the switch S2;
control ends of the switches S1 and S2 are connected to a reset signal line LA_RESET of the chip simultaneously; and
a reference voltage Vref of the burst mode receiver RX is simultaneously connected to another end of the resistor R7, another end of the R8, another end of the switch S1 and another end of the switch S2.