Patent ID: 11862735
Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. The ESD protection device of claim 6, further comprising:
another bi-polar junction transistor arranged in the substrate, including another first doped region, another second doped region, and another third doped region, the another second doped region disposed between the another first and another third doped region, wherein the another second doped region is of the first conductivity type and the first doping concentration and the another first and third doped regions are of the second conductivity type and the second doping concentration;
another first doped terminal region disposed within the another first doped region;
another second doped terminal region disposed within the another third doped region;
another doped island region disposed within the another second doped region, wherein the another first doped terminal region, another second doped terminal region and another doped island region are of the second conductivity type and the third doping concentration; and
another first conductive terminal coupled to the another first doped terminal region;
another second conductive terminal coupled to the another second doped terminal region; and
another insulating layer arranged on the substrate between the another first and second conductive terminals, the another insulating layer covering at least the another second doped region,
wherein the another first doped region and the another third doped region are spaced apart from each other,
wherein a depth of the another first doped region is substantially the same as a depth of the another third doped region, and a depth of the another second doped region is less than the depth of the another first and third doped regions,
wherein a first sidewall of the another second doped region abuts the another first doped region and a second sidewall of the another second doped region abuts the another third doped region and,
wherein the another second doped region overlaps at least a portion of the another first doped region and overlaps at least a portion of the another third doped region,
wherein the second conductive terminal is connected to the another first conductive terminal.