Patent ID: 11942452
Assignee: INFINEON TECHNOLOGIES AG
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. The semiconductor module arrangement of claim 1,
wherein the first semiconductor substrate comprises a dielectrically insulating layer and a second metallization layer arranged on a rear surface of the dielectrically insulating layer, and the second semiconductor substrate comprises a dielectrically insulating layer and a second metallization layer arranged on a rear surface of the dielectrically insulating layer, and
wherein (a) the dielectrically insulating layer of the first semiconductor substrate has a first thickness in a vertical direction that is different from a second thickness of the dielectrically insulating layer of the second semiconductor substrate, the vertical direction being perpendicular to the rear surface of the first semiconductor substrate and the rear surface of the second semiconductor substrate, or (b) the second metallization layer of the first semiconductor substrate is a structured layer including recesses between different sections of the layer, the different sections of the second metallization layer of the first semiconductor substrate being arranged in a first pattern, the second metallization layer of the second semiconductor substrate being a structured layer including recesses between different sections of the layer, the different sections of the second metallization layer of the second semiconductor substrate being arranged in a second pattern that is different from the first pattern, or both (a) and (b).