Patent ID: 11960755
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. An operation method of a semiconductor memory device, the operation method comprising:
generating a reference signal having enable periods, wherein a number of the enable periods and length of each enable period are randomly determined based on operation time;
storing, as first addresses, maximum ‘K’ addresses having different values among input addresses applied during the enable period of the reference signal;
storing, as second addresses, ‘L’ addresses corresponding to a time point at which the enable period of the reference signal is ended, among the input addresses applied during the enable period of the reference signal;
determining output or non-output and a first output order of each of the first addresses based on a number of times each of the first addresses is repeatedly input, determining a second output order for outputting mixed addresses obtained by mixing the first addresses based on the first output order and the second addresses together; and
applying the mixed addresses, which are output according to the second output order, to a target refresh operation,
wherein ‘K’ is a natural number equal to or greater than 2, and ‘L’ is a natural number equal to or greater than 1.