Patent ID: 11954355
Assignee: ATLAS POWER TECHNOLOGIES INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A tristate bidirectional memory apparatus comprising a plurality of tristate bidirectional memory cells for storing information bidirectionally during write operations, and for reading the information from the tristate bidirectional memory cells during read operations, the apparatus comprising:
a device selected from a group consisting of a first device, a second device, and a third device;, wherein the first device comprises:
in each tristate bidirectional memory cell:
at least one first transistor, each first transistor having a gate electrode operable to receive a signal, and two terminals whose conduction path is controlled by the gate electrode; and
an electrostatic storage device or capacitor comprised of two electrodes, one of each first transistor's terminals being connected to one of said electrodes of said electrostatic storage device or capacitor, the other electrode of said electrostatic storage device or capacitor being connected to one of two first bit lines of the tristate bidirectional memory cell, each first transistor's gate electrode being connected to a first word line, the other first bit line connected to the other terminal of each first transistor; and

a first circuit for writing the information to the plurality of tristate bidirectional memory cells bidirectionally by applying a specific positive or negative first signal to said first word line of each tristate bidirectional memory cell, and a specific interchangeable voltage differential between said two first bit lines of each tristate bidirectional memory cell, the first circuit configured to:
charge each tristate bidirectional memory cell through each first transistor in a first specific bias and polarity, to cause each tristate bidirectional memory cell to assume a first information-representing state, when charged with positive polarity or forward bias, and
maintain no charge on each tristate bidirectional memory cell to cause each tristate bidirectional memory cell to assume a second information-representing state, and
cause, when each tristate bidirectional memory cell is charged with negative polarity or inverse bias, each tristate bidirectional memory cell to assume a third information-representing state;, the second device comprises:
in each tristate bidirectional memory cell, a configuration of second transistors able to store the information using one of three states: a first current flow state of forward bias or positive polarity, a second current flow state of no bias or neutral polarity, a third current flow state of reverse bias or negative polarity;
a second bit line and a bit line driver;
a second word line and a word line driver;
an encoding line and an encoding line driver;
a second circuit for writing the information to the plurality of tristate bidirectional memory cells bidirectionally, by applying a specific second signal to said encoding line to encode one or more of the second transistors of each tristate bidirectional memory cell, the second circuit configured to:
encode one or more of the second transistors in a second specific bias and polarity by allowing a current signal to cause each tristate bidirectional memory cell to assume the first information-representing state, with positive polarity or forward bias, and
maintain no charge on each tristate bidirectional memory cell to cause each tristate bidirectional memory cell to assume the second information-representing state, and
charge one or more of the second transistors by reversing said current signal to cause each tristate bidirectional memory cell to assume the third information-representing state, with negative polarity or reverse bias;

a circuit for reading and interpreting charge state and polarity of the plurality of tristate bidirectional memory cells by utilizing at least one of a voltage comparison, a resistance comparison, a polarity comparison, and a logic circuit; and
a circuit for reading the information stored on the plurality of tristate bidirectional memory cells by applying a read signal to said second word line and by interpreting a voltage state or a voltage state change on said second bit line;, and the third device comprises:
an electromagnetic storage device or medium, comprised of electromagnetic material forming the plurality of tristate bidirectional memory cells;
an information writing and reading circuit connected to said electromagnetic storage device or medium;
a third circuit for writing the information to said electromagnetic storage device or medium bidirectionally, by applying a specific positive or negative third signal, relative to a reference voltage, to said electromagnetic storage device or medium, by applying another specific interchangeable voltage differential between an upper surface and a lower surface of the electromagnetic material, the third circuit configured to:
charge each tristate bidirectional memory cell through said electromagnetic material in a third specific bias and polarity, by allowing another current signal to cause each tristate bidirectional memory cell to assume the first information-representing state, when charged with positive polarity or forward bias, and
maintain no charge on each tristate bidirectional memory cell to cause each tristate bidirectional memory cell to assume the second information-representing state, and
reverse said other current signal to allow the other current signal to charge each tristate bidirectional memory cell through said electromagnetic material in an alternate bias and polarity, to cause each tristate bidirectional memory cell to assume the third-information representing state, when charged with negative polarity or reverse bias;

another circuit, for reading the information stored on the plurality of tristate bidirectional memory cells by measuring electrical resistance or electrical current; and
a further circuit, for interpreting charge state and polarity of said tristate bidirectional memory cell by utilizing at least one of a further voltage comparison,
a further resistance comparison, a further polarity comparison, and a further logic circuit;, the apparatus further comprising a definable translation circuit connected to one or more sense amplifiers to receive a negative output signal from each tristate bidirectional memory cell, wherein the definable translation circuit is configured to modify or control the negative output signal of each tristate bidirectional memory cell only when the corresponding tristate bidirectional memory cell provides the negative output signal to the definable translation circuit, the definable translation circuit configured to translate the negative output signal into a predetermined signal comprising one or more binary bits.