Patent ID: 11892957
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 3:
4. The system according to claim 3, wherein:
the first interface includes an FPGA endpoint;
the second interface includes a FPGA root port, the FPGA root port supporting a configuration space;
the accelerator includes a first physical function (PF), a second PF, and a filter associated with the FPGA root port, the filter configured to intercept a first acceleration instruction received from the SSD and deliver the first acceleration instruction to the accelerator;
the accelerator is configured to request a first block of host system addresses from the processor for the first PF and to request a second block of host system addresses from the processor for the second PF; and
the accelerator is configured to forward a first transaction received from the processor to the SSD and to forward a second acceleration instruction received from the processor to the accelerator, the first transaction being associated with a first identifier of the first PF and the second acceleration instruction being associated with a second identifier of the second PF.