Patent ID: 11893243
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A storage system comprising:
a memory comprising memory cells configured to store X number of bits per memory cell, wherein X is a positive integer and wherein the memory is organized into a plurality of wordlines, wherein each wordline comprises a plurality of programming segments; and
a controller configured to:
for each of a plurality of program cycles, change, in each of the plurality of wordlines and with respect to a prior wordline, which of the plurality of programming segments is a last programming segment programmed;
after the plurality of program cycles, observe a pattern showing that an error repeatedly occurred on a certain programming segment of the plurality of programming segments;
based on the observed pattern, select the certain programming segment to be the last programming segment programmed;
detect a number of program disturb errors in the memory; and
correct the program disturb errors using the error correction operation.