Patent ID: 11948946
Assignee: HKC CORPORATION LIMITED
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A method for manufacturing an array substrate, comprising:
forming on a substrate a gate and a signal trace spaced apart from the gate;
forming on the substrate a gate insulation layer, the gate insulation layer covering the gate and the signal trace;
forming on the gate insulation layer an active layer to-be-processed;
forming on the active layer to-be-processed a first photoresist layer to-be-processed, and exposing and developing the first photoresist layer to-be-processed to form a first photoresist layer;
etching the active layer to-be-processed to form an active layer, the first photoresist layer being on a side surface of the active layer away from the gate insulation layer;
forming on the gate insulation layer a second photoresist layer to-be-processed, the second photoresist layer to-be-processed being connected with the first photoresist layer;
exposing and developing the second photoresist layer to-be-processed to form a second photoresist layer;
etching the gate insulation layer to define a through hole, the through hole facing the signal trace;
removing the first photoresist layer and the second photoresist layer; and
forming on the gate insulation layer a source and a drain, one of the source or the drain being connected with the signal trace through the through hole.