Patent ID: 11868653
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 6:
7. The memory system of claim 1, wherein
the nonvolatile memory further includes a plurality of blocks, each of the plurality of blocks being a unit of a data erase operation, the plurality of blocks including at least a first block and a second block, the first block including the first word line, the second block including the second word line,
the data buffer of the host includes a plurality of regions respectively corresponding to the plurality of blocks, the plurality of regions including at least a first region and a second region, and
the controller is further configured to:
transfer the first data from the first region of the data buffer to the write buffer by transmitting a request to the host, the first region corresponding to the first block; and
transfer the second data from the second region of the data buffer to the write buffer by transmitting another request to the host, the second region corresponding to the second block.