Patent ID: 11934330
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 10:
11. The apparatus of claim 10, wherein the determine whether to store the processed data in the buffer of the offload processor or the system memory is based on one or more of: available buffer space, latency limit associated with the processed data, priority associated with the processed data, or available bandwidth through an interface between the buffer and the system memory and wherein the determine whether to store the processed second data in the buffer of the at least one of the multiple tiles that comprises the offload processor and the buffer or the system memory after processing by the offload processor is based on one or more of: available buffer space, latency limit associated with the processed second data, priority associated with the processed second data, or available bandwidth through an interface between the buffer and the system memory.