Patent ID: 11923234
Assignee: STMICROELECTRONICS (TOURS) SAS
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A method, comprising:
attaching a support film to an interconnection layer, the interconnection layer being on a first side of a semiconductor substrate, the semiconductor substrate having a plurality of integrated circuits at the first side;
forming a plurality of trenches extending through the semiconductor substrate and the interconnection layer and to the support film, the plurality of trenches laterally delimiting a plurality of chips, each of the plurality of chips including at least one of the plurality of integrated circuits, the interconnection layer including at least one metal connection pad for each of the plurality of chips; and
forming an electrically isolating layer on a second side of the semiconductor substrate that is opposite to the first side, on lateral surfaces of the semiconductor substrate exposed by the plurality of trenches, on portions of the support film exposed by the plurality of trenches, and on lateral surfaces of the interconnection layer exposed by the plurality of trenches, the electrically isolating layer being a dielectric oxide layer.