Patent ID: 11929419
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A device, comprising:
a semiconductive fin having source and drain regions and a channel region between the source and drain regions;
an isolation dielectric layer surrounding a bottom of the semiconductive fin;
a gate feature over the channel region of the semiconductive fin;
a first spacer around the gate feature;
a second spacer around the first spacer;
an interlayer dielectric layer around the second spacer;
a void between the second spacer and the interlayer dielectric layer;
source and drain features respectively in the source and drain regions of the semiconductive fin; and
a contact etch stop layer between the second spacer and the interlayer dielectric layer, wherein a top surface of the contact etch stop layer is lower than a top surface of the interlayer dielectric layer.