Patent ID: 11881246
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. The electronic device according to claim 4, wherein the memory region comprises:
a first memory region with a plurality of row hammering word lines and a plurality of row hammering cells that are coupled to the plurality of row hammering word lines, and configured to output, during the internal read operation, the read counting signal that is stored in row hammering cells that are coupled to a row hammering word line that is selected by an internal address among the plurality of row hammering word lines, and store, in the internal write operation, the write counting signal in row hammering cells that are coupled to a row hammering word line that is selected by the internal address among the plurality of row hammering word lines; and
a second memory region including a plurality of word lines and a plurality of memory cells which are coupled to the plurality of word lines, and configured to refresh, in the smart refresh operation, word lines that are adjacent to a word line that is selected by the target address, output, in a read operation, first data that is stored in memory cells that are coupled to a word line, among the plurality of word lines, selected by the internal address, and store, in a write operation, second data in memory cells that are coupled to a word line, among the plurality of word lines, selected by the internal address.