Patent ID: 11894465
Assignee: GOOGLE LLC
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A non-planar semiconductor device, comprising:
a hetero-structure disposed above a substrate, the hetero-structure comprising a hetero junction between an upper layer and a lower layer of differing composition;
an active layer disposed above the hetero-structure and having a composition different from the upper and lower layers of the hetero-structure;
a gate structure disposed on and surrounding a channel region of the active layer, and disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure;
one or more nanowires disposed in a vertical arrangement above the active layer, wherein the gate structure is disposed on and surrounds each of the nanowires;
source and drain regions disposed on the substrate and in the upper layer on either side of the gate structure; and
isolation regions adjacent the source and drain regions and disposed at least partially into the hetero-structure.