Patent ID: 11935574
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 12:
13. A method of forming an array of capacitors, comprising:
forming a conductive lining in individual capacitor openings in insulative-comprising material in first and second areas of a substrate to comprise first capacitor electrodes of capacitors being formed in the capacitor openings and forming sacrificial material laterally-inward of the conductive linings;
vertically recessing the conductive linings and the sacrificial material in the capacitor openings in the first and second areas relative to respective top surfaces of the insulative-comprising material immediately-laterally-adjacent the capacitor openings;
forming a leaker-material lining in the capacitor openings in the first and second areas atop the conductive linings;
removing the leaker-material linings from the capacitor openings in the second area to leave the leaker-material linings in the capacitor openings in the first area;
after removing the leaker-material linings from the second area, removing remaining of the sacrificial material from being laterally-inward of the conductive linings in the capacitor openings in the first and second areas;
after removing the sacrificial material, forming capacitor insulator material in the capacitor openings in the first and second areas aside the conductive linings and the leaker-material linings;
forming conductive material in the capacitor openings in the first and second areas to comprise second capacitor electrodes of the capacitors; and
the capacitors individually comprising an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the capacitor insulator material, individual of the leaker-material linings forming a parallel current leakage path that is circuit-parallel with the intrinsic current leakage path and of lower total resistance than the intrinsic current leakage path.