Patent ID: 11915758
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A memory device comprising:
an array of memory cells comprising a plurality of strings of series-connected memory cells;
a plurality of data lines, wherein each string of series-connected memory cells of the plurality of strings of series-connected memory cells is selectively electrically connected to a respective data line of the plurality of data lines;
a plurality of access lines, each access line of the plurality of access lines connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells;
a page buffer connected to the plurality of data lines, wherein for each data line of the plurality of data lines the page buffer comprises:
a respective first storage element to store a respective first data bit; and
a respective second storage element to store a respective second data bit; and

a controller configured to apply one of four voltage levels based on the respective first data bit and the respective second data bit to each respective data line of the plurality of data lines during a programing operation of respective memory cells connected to a selected access line of the plurality of access lines.