Patent ID: 11875852
Assignee: SILICON STORAGE TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A non-volatile memory system, comprising:
an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell comprising a source and a drain;
a plurality of bit lines, each of the plurality of bit lines coupled to the drain of each non-volatile memory cell in a column of non-volatile memory cells;
a plurality of pull down bit lines, each of the plurality of pull down bit lines coupling a row of non-volatile memory cells to a reference node;
a source line coupled to the source of each non-volatile memory cell; and
an adaptive bias decoder to receive a row address and provide an adjusted voltage to a control gate line of a row in the array corresponding to the row address during an operation, wherein the adaptive bias decoder adjusts the adjusted voltage provided to the control gate line in response to a change in voltage of the reference node.