Patent ID: 11937416
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 13:
14. The method of claim 10, wherein the processing the semiconductor layer stack to form the first transistor having the first number of the first semiconductor layers in the first transistor region and the second transistor having the second number of the first semiconductor layers in the second transistor region includes:
patterning the semiconductor layer stack to from a first fin structure from the first portion of the semiconductor layer stack in the first transistor region and a second fin structure from the third semiconductor layer and the recessed second portion of the semiconductor layer stack in the second transistor region, wherein the first fin structure and the second fin structure extend lengthwise along a first direction;
forming a first dummy gate over a first channel region of the first fin structure and a second dummy gate over a second channel region of the second fin structure, wherein the first dummy gate and the second dummy gate extend lengthwise along a second direction that is different than the first direction;
forming first recesses in first source/drain regions of the first fin structure and second recesses in second source/drain regions of the second fin structure;
forming first epitaxial source/drains in the first recesses and second epitaxial source/drains in the second recesses;
removing the first dummy gate and the second dummy gate to provide a first gate opening that exposes the first channel region of the first fin structure and a second gate opening that expose the second channel region of the second fin structure;
selectively removing the second semiconductor layers exposed by the first gate opening, the second semiconductor layers exposed by the second gate opening, and the third semiconductor layer exposed by the second gate opening, such that the first number of the first semiconductor layers are suspended over the semiconductor substrate in the first transistor region and the second number of the first semiconductor layers are suspended over the semiconductor substrate in the second transistor region; and
forming a first metal gate in the first gate opening and a second metal gate in the second gate opening, wherein the first metal gate surrounds the first number of the first semiconductor layers in the first transistor region and the second metal gate surrounds the second number of the first semiconductor layers in the second transistor region.