Patent ID: 11881131
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: nan (nan)
Classification: CPC nan | IPC G

Claim 10:
11. A method for manufacturing a display device, comprising:
manufacturing a display panel;
testing for a crack in the display panel using a first set of pads before mounting a driving integrated circuit (IC) to the display panel;
mounting the driving IC to the display panel using a second set of pads spaced apart from the first set of pads in plan view; and
testing for a crack in the display panel again, after mounting the driving IC to the display panel, using the driving IC and the second set of pads,
wherein manufacturing the display panel comprises:
forming a plurality of pixels in a display area of a substrate, wherein the substrate comprises the display area and a non-display area disposed near the display area;
forming a plurality of signal lines on the substrate, wherein the signal lines are electrically connected to the pixels; and
forming a pad portion in the non-display area, wherein the pad portion comprises a plurality of pads including the first set of pads and the second set of pads,
wherein the signal lines comprise:
a first crack detecting line disposed in the non-display area to detect a crack in the display panel, the first crack detecting line directly electrically connected to a first test voltage pad and a first pad at a first node, directly electrically connected to a second pad at a second node, and extending directly across from at least a majority of one side of the display area between the first node and the second node;
a first data line comprising a first end electrically connected to a first transistor electrically connected to the first crack detecting line at the second node, and a second end electrically connected to corresponding pixels from among the plurality of pixels;
a plurality of second data lines, each comprising a first end electrically connected to the first crack detecting line through a corresponding one of a plurality of second transistors and a second end electrically connected to corresponding pixels from among the plurality of pixels; and
a control line electrically connected to gates of the first transistor and the second transistors.