Patent ID: 11941281
Assignee: NXP B.V.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. The system of claim 7, wherein the memory controller is configured to perform the margin read operation on the first memory cell and the second memory cell by performing steps including:
applying a first margin read signal to the first memory cell;
reading a fifth value of the first memory cell;
determining that the fifth value indicates the first memory cell is in a cleared condition;
applying the first margin read signal to the second memory cell;
reading a sixth value of the second memory cell;
determining that the sixth value indicates the second memory cell is in the cleared condition; and
applying a second margin read signal to the first memory cell, wherein the second margin read signal is different from the first margin read signal;
reading a seventh value of the first memory cell;
determining that the seventh value indicates the first memory cell is in a set condition;
applying the second margin read signal to the second memory cell;
reading an eighth value of the second memory cell; and
determining that the eighth value indicates the second memory cell is in the cleared condition.