Patent ID: 11961583
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 0:
1. A NAND memory device comprising:
a bus; and
a group of NAND dies, each of the group of NAND dies coupled to the bus, the group of NAND dies including:
a first NAND die configured to:
transmit through the bus, at a first time, a first set of bits related to a first peak current, the first peak current associated with a first operation on the first NAND die, and

a second NAND die configured to:
transmit through the bus, at a second time after the first time, a second set of bits related to a second peak current, the second peak current associated with a second operation on the second NAND die, and
pause, at a third time after the second time, executing the second operation on the second NAND die, based on an indication that the second peak current cannot be provided,

wherein the indication is based on the transmission of the first set of bits and the second set of bits.