Patent ID: 11972144
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. An apparatus, comprising:
a plurality of memory dice;
a data bus coupled with each of the plurality of memory dice; and
a controller coupled with each of the plurality of via the data bus, the controller configured to:
transmit a first command associated with a first operation to a first memory die of the plurality of memory dice, wherein the first command comprises an assignment of the first operation to a queue slot of a status bank;
transmit a second command to the first memory die based at least in part on transmitting the first command, wherein the second command requests a status associated with the status bank;
transmit a third command associated with a second operation to a second memory die of the plurality of memory dice subsequent to transmitting the first command, wherein the third command comprises a second assignment of the second operation to a second queue slot of the status bank;
transmit the second command concurrently to the first memory die and the second memory die based at least in part on transmitting the first command and the third command, wherein the second command is further configured to request the status associated with the status bank from the second memory die;
receive, via a first channel of the data bus determined based at least in part on the assigned queue slot of the status bank, the status of the first operation based at least in part on transmitting the second command to the first memory die; and
receive, via a second channel of the data bus determined based at least in part on the assigned second queue slot of the status bank, the status of the second operation based at least in part on transmitting the second command concurrently to the first memory die and the second memory die.