Patent ID: 11942137
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 18:
19. The semiconductor memory device of claim 11, wherein the refresh control circuit includes:
a refresh control logic configured to generate a hammer refresh signal and a target refresh signal in response to the alert signal,
a refresh clock generator configured to generate a refresh clock signal in response to a refresh signal,
a refresh counter configured to generate a count refresh address associated with a normal refresh operation on the plurality of memory cell rows,
a hammer address storage configured to store the hammer address and configured to output the hammer address in response to the hammer refresh signal,
a mapper configured to generate hammer refresh addresses designating addresses of the one or more victim memory cell rows based on the hammer address output from the hammer address storage, and
a target address storage configured to store the outcast row list and configured to output target refresh addresses indicating row addresses of the outcast memory cell rows in response to the target refresh signal.