Patent ID: 11863164
Assignee: KYOTO UNIVERSITY
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A quantum circuit learning device, comprising:
a memory; and
a processor coupled to the memory, the processor being configured to perform a process comprising:
providing a quantum circuit U({θk}), which includes a plurality of quantum bits, with an input signal x(j), wherein θk is a circuit parameter that defines a circuit configuration of the quantum circuit U({θk}), k is an index of the circuit parameter, and j is an index of the signal;
observing states of the quantum bits included in the quantum circuit U({θk}) and acquiring a value <A(x(j), {θk})> that is calculated from an output of the quantum circuit U({θk}) based on the observed states;
adjusting the circuit parameter θk, using the acquired value <A(x(j), {θk})> and using a cost function that is set based on a teacher signal y(j) corresponding to the value <A(x(j), {θk})>; and
at a time of adjusting an l-th circuit parameter θl in the circuit parameter θ, calculating a gradient in accordance with the following Formula (1), the gradient being calculated from a difference between a value <A(x(j), {θl, . . . , θ1+ε, θ1+l, . . . })> calculated from an output of the quantum circuit U({θk}) in a case in which the l-th circuit parameter θl is increased by a set value ε, and a value <A(x(j), {θl, . . . , θ1−ε, θ1+l, . . . })> calculated from an output of the quantum circuit U({θk}) in a case in which the l-th circuit parameter θl is decreased by the set value ε, and adjusting the circuit parameter θl in such a way as to minimize the cost function by means of a gradient method, using the calculated gradient value:, ∂
       
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     [
     
      Formula
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      1
     
     ]