Patent ID: 11893476
Assignee: KABUSHIKI KAISHA TOSHIBA
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. The inference system according to claim 7, wherein
the M input signals each represent a binary value,
the N intermediate signals each represent a binary value,
the L output signals each represent a binary value,
the recurrent neural network circuit includes N product-sum operation circuits corresponding to the N intermediate signals,
with respect to each of the N product-sum operation circuits, M coefficients corresponding to the M input signals are set,
if an ith input signal, for which i is an integer of 1 or more and M or less, among the M input signals is applied to the recurrent neural network circuit, the control circuit adjusts, according to the delay time period, a relative relationship between an input coefficient group set to the recurrent neural network circuit and a coefficient group other than the input coefficient group set to the recurrent neural network circuit, and
the input coefficient group is a coefficient group that is multiplied by the ith input signal among the plurality of coefficients set to the recurrent neural network circuit.