Patent ID: 11894061
Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A non-volatile memory device comprising a memory programming circuit for programming said non-volatile memory device, said non-volatile memory device having an array structure comprising a plurality of rows of a given number, each row having a row index varying from one to said given number and comprising one or more memory units, each memory unit being configured to receive one or more input signals and to deliver one or more output signals, wherein the memory programming circuit comprises:
a plurality of first source lines connected to the top electrode of the memory units comprised at rows of odd row indices, and;
a plurality of second source lines connected to the top electrodes of the memory units comprised at rows of even row indices;
an analog circuit configured to receive the output signals delivered by said one or more memory units and to deliver to at least one memory unit a programming signal as an input signal, said analog circuit being configured to perform a programming operation for each pair of successive rows in said plurality of rows, a pair of successive rows comprising a first row and a second row, the first row being connected to a first line selected among said plurality of first source lines and said plurality of second source lines depending on whether the row index of said first row is odd or even, the second row being connected to a second line selected among said plurality of first source lines and said plurality of second source lines depending on whether the row index of said second row is odd or even, the analog circuit being configured to perform said programming operation by:
reading the output signal or signals delivered by the memory units comprised in said first row;
applying a read voltage to said first line;
determining a programming signal by applying a signal transformation function to said output signals;
applying a programming voltage to said second line, and
feeding the memory units comprised in said second row by said programming signal as the input signal of each of said memory units.