Patent ID: 11894278
Assignee: nan
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 2:
3. The method of claim 1, comprising, after step (f4),
step of (f5) defining a dummy cell area, a main cell area, and a redundant cell area included in one of the cells;
step of (f6) producing a plurality of dummy cells based on a gap between cells in the dummy cell area;
step of (f7) producing a plurality of main cells based on the number of main cells and a gap between main cells in the main cell area;
step of (f8) producing a plurality of redundant cells based on the number of redundant cells and a gap between redundant cells in the redundant cell area; and
step of (f9) producing a cell layer by dividing the dummy cell area, the main cell area, and the redundant cell area, respectively.