Patent ID: 11899829
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 7:
8. An apparatus comprising:
a memory device comprising a plurality of memory regions;
a memory controller configured to control the memory device, the memory controller comprising:
a processor comprising authentication logic configured to generate a plurality of access codes, each access code of the plurality of access codes for at least a respective memory region of the plurality of memory regions, wherein the processor further comprises translation logic configured to translate a memory address of memory access request to a physical memory address associated with at least one memory region of the plurality of memory regions; and
a cache register configured to store the plurality of access codes, each access code associated with a corresponding memory region of the plurality of memory regions of the memory device; and

a memory bus coupling the memory controller to the memory device, wherein the memory controller is further configured to provide, via the memory bus, memory access requests including at least one access code of the plurality of access codes.