Patent ID: 11929292
Assignee: KIOXIA CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor memory device comprising:
a substrate including an active block area and a dummy block area arranged in a first direction;
a plurality of first conductive layers stacked above the substrate and spaced apart from each other, the first conductive layers being disposed in the active block area and in the dummy block area;
a plurality of insulating members extending in a second direction intersecting both the first direction and a stacking direction of the first conductive layers on both sides of the dummy block area in the first direction, the insulating members being arranged above the substrate and partitioning the first conductive layers in the first direction;
a plurality of first pillars extending in the stacking direction through the first conductive layers in the active block area, intersections of the first pillars with at least one of the first conductive layers functioning as memory cells; and
a plurality of second pillars extending in the stacking direction through the first conductive layers in the dummy block area, wherein
the substrate further includes an interconnect connection area in which a first contact electrically connecting an upper interconnect above the first conductive layers and a circuit disposed under the first conductive layers is provided, the dummy block area being disposed between the active block area and the interconnect connection area,
the insulating members include a first insulating member on a first side of the dummy block area facing the active block area and a second insulating member on a second side of the dummy block area facing the interconnect connection area, the first conductive layers being further disposed in an adjacent area close to the second insulating member on an opposite side of the dummy block area,
the dummy block area is sandwiched in the first direction by the first insulating member and the second insulating member,
the first conductive layers are stacked with a plurality of first insulating layers alternately in the stacking direction in the active block area, in the dummy block area, and in the adjacent area, the first insulating layers being partitioned by the insulating members in the first direction, and
the first insulating layers and a plurality of second insulating layers are alternately stacked in the stacking direction in the interconnect connection area, the first contact extending in the stacking direction through the first insulating layers and the second insulating layers in the interconnect connection area.