Patent ID: 11925030
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A method for forming a memory device, the method comprising:
forming a pair of source/drain layers and a dielectric layer vertically stacked with the dielectric layer between the source/drain layers, wherein the source/drain layers and the dielectric layer have individual sidewalls forming a common sidewall;
performing an etch into the individual sidewall of the dielectric layer to laterally offset the individual sidewall relative to the individual sidewalls of the source/drain layers, wherein the etch forms a recess at the individual sidewall of the dielectric layer;
forming a conductor-insulator-semiconductor (CIS) structure on the individual sidewall of the dielectric layer, wherein the CIS structure comprises an internal gate electrode that is continuous and in the recess;
depositing a ferroelectric layer and a conductive layer lining the individual sidewalls of the source/drain layers and an individual sidewall of the CIS structure; and
after the depositing of the ferroelectric layer and the conductive layer, forming a dielectric wall dividing the internal gate electrode into discrete segments spaced from each other in the recess, wherein the dielectric wall is spaced from the conductive layer.