Patent ID: 11907144
Assignee: AMAZON TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. A direct memory access (DMA) engine comprising:
a read descriptor queue operable to store read descriptors;
a write descriptor queue operable to store write descriptors;
an input interface operable to read data based on the read descriptors;
an output interface operable to write data based on the write descriptors; and
a controller operable to:
process the read descriptors to obtain a set of data from an on-chip memory of an integrated circuit device;
insert a first semaphore update in a processing flow of the DMA engine to indicate that the on-chip memory is free to store a new set of data;
process the write descriptors to write the set of data read from the on-chip memory to system memory;
receive an acknowledgement from the system memory that the set of data has been stored in the system memory; and
perform a second semaphore update to indicate that the set of data is available in the system memory in response to the acknowledgement.