Patent ID: 11948621
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. A memory system comprising:
a memory device configured to adjust first quad skew of a 4-phase clock; and
a controller configured to control the memory device, and to control second quad skew of the 4-phase clock,
wherein the memory device includes:
a first rank configured to receive the 4-phase clock from the controller through first channels, to detect first internal quad skew of the 4-phase clock, to store first mode register information corresponding to the first internal quad skew, and to output the first mode register information to the controller through a second channel; and
a second rank configured to receive the 4-phase clock through the first channels, to detect second internal quad skew of the 4-phase clock, to store second mode register information corresponding to the second internal quad skew, and to output the second mode register information to the controller through the second channel.