Patent ID: 11972294
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. The memory system of claim 5, wherein the hardware accelerator includes, for a current bit of interest being a test bit:
a test_bit_pos register in which contents of the test_bit_pos register indicate on which bit, inside the memory range, the counting is to be truncated;
a bits_count register to hold a result of the count of bits asserted;
a test_bit_state register to hold a result on a check of the test bit as asserted or not asserted;
an enable_check register holds an indicator that, when asserted, starts the bits counting and checks whether the test bit is asserted; and
a check_complete register in which contents of the check_complete register indicate when the counting is complete.