Patent ID: 11946972
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Field: Measurement (Instruments)
Classification: CPC G  B  H | IPC B  G  H

Claim 16:
17. A system, for monitoring of interconnect lines, comprising:
a transmit block including a first transmit logic and a second transmit logic;
a receive block including a receive logic; and
an interconnect bus coupling the transmit block with the receive block and including:
a first interconnect line; and
a second interconnect line,

the second transmit logic configured to detect a fault on the first interconnect line by comparing a transmit signal with a receive signal,
the transmit signal is generated by the transmit block using the first transmit logic,
the receive signal is generated by the receive block using the receive logic, and
the fault is detected by the second transmit logic when, for a given clock period, the transmit signal and the receive signal do not correspond.