Patent ID: 11876045
Assignee: NANYA TECHNOLOGY CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for preparing a semiconductor device, comprising:
forming an opening structure in a first dielectric layer, wherein the opening structure has a first portion, a second portion and a third portion disposed between and physically connecting the first portion and the second portion;
forming a lining material lining the first portion and the second portion of the opening structure and completely filling the third portion of the opening structure, wherein the lining material includes copper-manganese (CuMn);
filling the first portion and the second portion of the opening structure with a conductive material after the lining material is formed; and
performing a planarization process on the lining material and the conductive material, wherein forming the opening structure in the first dielectric layer comprises using a patterned mask as an etching mask, and wherein the planarization process is performed until the patterned mask is exposed.