Patent ID: 11967983
Assignee: QUALCOMM INCORPORATED
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 23:
24. The method of claim 23, wherein the associated gates comprise:
a first switching transistor coupled between the biased current source and the positive amplitude current output, the first switching transistor configured to switch the PA cell between the on state and the off state by the first clocked positive data output;
a second switching transistor coupled between the biased current source and the positive amplitude current output, the second switching transistor configured to switch the PA cell between the on state and the off state by the second clocked positive data output;
a third switching transistor coupled between the biased current source and the negative amplitude current output, the third switching transistor configured to switch the PA cell between the on state and the off state by the first clocked negative data output; and
a fourth switching transistor coupled between the biased current source and the negative amplitude current output, the fourth switching transistor configured to switch the PA cell between the on state and the off state by the second clocked negative data output.