Patent ID: 11942945
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 19:
20. The method of forming the semiconductor device of claim 19, wherein the forming the active regions, the forming the S/D regions, the forming the MD contact structures and the forming the gate lines further result in:
a fourth set of the first to fourth transistor-components connected as corresponding transistors that define a third time delay circuit having a third input configured to receive the third clock signal and having a third output configured to generate a fourth clock signal from the third clock signal; and
a fifth set of the first to fourth transistor-components connected as corresponding transistors that define a gated input circuit in the master-slave flip-flop configured to receive the third clock signal and the fourth clock signal to control an input transmission state of the gated input circuit.