Patent ID: 11910617
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A method of forming a ferroelectric memory device, comprising:
forming a multi-layer stack over a substrate, the multi-layer stack comprising a plurality of dielectric layers interleaved between a plurality of conductive layers, wherein sidewalls of the plurality of dielectric layers and the plurality of conductive layers define a trench penetrating therethrough;
forming a plurality of ferroelectric portions on the sidewalls of the plurality of conductive layers;
forming a channel layer on the plurality of ferroelectric portions and the sidewalls of the plurality of dielectric layers, wherein the channel layer is formed to have a sidewall that contacts the sidewalls of the plurality of dielectric layers and an adjoining upper surface that contacts a lower surface of the plurality of ferroelectric portions, the lower surface of the plurality of ferroelectric portions facing the substrate; and
forming a conductive pillar along sidewalls of the channel layer, wherein the conductive pillar is formed to have a wavy sidewall profile.