Patent ID: 11935613
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A device, comprising:
a memory storing instructions; and
a processor adapted to be coupled to a Double Data Rate (DDR) flash memory by way of a Serial Peripheral Interface (SPI), the processor configured to execute the instructions stored in the memory to:
determine a first set of parameters for the SPI that is usable by the processor to read successfully from the DDR flash memory, the first set of parameters comprising a largest successful value of a transmit clock delay, a largest successful value of a receive clock delay, and a first value of a reference clock delay (RD) cycle;
determine a second set of parameters for the SPI that is usable by the processor to read successfully from the DDR flash memory, the second set of parameters comprising a smallest successful value of the transmit clock delay, a smallest successful value of the receive clock delay, and a second value of the RD cycle;
select one of the first and second sets of parameters based on a determination of whether the first set of parameters is usable by the processor to read successfully from the DDR flash memory over a larger range of operating temperatures of the device than the second set of parameters;
program the SPI using the selected one of the first and second sets of parameters;
based on a determination that the first value of the RD cycle is equal to the second value of the RD cycle:
program the SPI to the first value of the RD cycle; and
program the SPI to a selected value of the transmit clock delay between the smallest successful value of the transmit clock delay and the largest successful value of the transmit clock delay, and a selected value of the receive clock delay between the smallest successful value of the receive clock delay and the largest successful value of the receive clock delay,
wherein the selected value of the transmit clock delay and the selected value of the receive clock delay are selected based on an expected operating temperature of the device.