Patent ID: 11925011
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 4:
5. The memory structure of claim 1, wherein:
the pass-gate FinFET further includes a first gate that wraps a first portion of the first p-type semiconductor fin having the first width, wherein the first gate extends lengthwise along the first direction and the first gate is disposed between respective n-type epitaxial source/drains along the second direction;
the pull-down FinFET further includes a second gate that wraps a second portion of the first p-type semiconductor fin having the first width, wherein the second gate extends lengthwise along the first direction and the second gate is disposed between respective n-type epitaxial source/drains along the second direction; and
the dummy FinFET further includes a third gate that wraps a portion of the second p-type semiconductor fin having the second width, wherein the third gate extends lengthwise along the first direction and the third gate is disposed between respective p-type epitaxial source/drains along the second direction.