Patent ID: 11870452
Assignee: NXP USA, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 17:
18. The apparatus of claim 15, further comprising
a sign detector module configured to detect signs of the first input value and the second input value; and
a calibration module configured to adjust the phase signal such that the phase value is:
provided as a first quadrant phase value in response to both the first input value and the second input value being positive;
provided as a second quadrant phase value in response to the first input value being negative and the second input value being positive, by subtracting the phase value from π;
provided as a third quadrant phase value in response to both the first input value and the second input value being negative, by adding π to the phase value; and
provided as a fourth quadrant phase value in response to the first input value being positive and the second input value being negative, subtracting the phase value from 2 π.