Patent ID: 11914481
Assignee: NETLIST, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 4:
5. The memory system of claim 4, wherein the set of parameters includes a voltage of the NVM subsystem, a current of the NVM subsystem, a temperature of the NVM subsystem, a number of errors per segment of the NVM subsystem, a number of errors per page of the NVM subsystem, a number of errors per block of the NVM subsystem, a number of errors per slice of the NVM subsystem, a number of detectable errors per segment, a number of detectable errors per page, a number of detectable errors per block, a number of detectable errors per slice, a number of correctable errors per segment, a number of correctable errors per page, a number of correctable errors per block, a number of correctable errors per slice, a number of time out errors, and a number of read and write operations,
wherein a slice of the NVM subsystem includes a plurality of blocks of the NVM subsystem, and
wherein a page of the NVM subsystem includes a plurality of segments of the NVM subsystem.