Patent ID: 11907680
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A multiplication-accumulation (MAC) operator, the MAC operator being a device comprising:
a multiplication circuit configured to perform a multiplication operation on a plurality of weight data and a plurality of vector data having a floating-point format to output a plurality of multiplication data, each of which comprise a plurality of elements;
a bit separation circuit configured to receive a plurality of exponent data of the plurality of multiplication data to generate and output exponent upper bits and exponent lower bits;
an exponent pre-processing circuit configured to receive the exponent upper bits to generate and output first maximum exponent upper data and a plurality of shift data;
a mantissa pre-processing circuit configured to perform pre-processing on a plurality of mantissa data of the plurality of multiplication data using the exponent lower bits and the plurality of shift data to generate and output a plurality of pre-processed mantissa data; and
an adder tree configured to add the plurality of pre-processed mantissa data to generate and output mantissa data of multiplication addition data,
wherein each of the plurality of weight data and each of the plurality of vector data include mantissa data of “M” bits,
wherein the multiplication circuit includes multipliers, each of the mutipliers outputting at least one of the plurality of multiplication data,
wherein the one of the plurality of multiplication data includes mantissa data having a most significant bit (MSB) of a “2×(M+1)”th bit, and a floating point in the mantissa data is positioned between a “2×M”th bit and the “(2×M)+1”th bit, and
wherein “M” is a natural number.