Patent ID: 11943918
Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A memory structure, comprising:
a substrate;
a plurality of discrete memory gate structures on the substrate, wherein each of the plurality of discrete memory gate structures includes a floating gate layer and a control gate layer on the floating gate layer;
an isolation layer formed between adjacent memory gate structures, wherein:
a top surface of the isolation layer is lower than a top surface of the control gate layer and higher than a bottom surface of the control gate layer, an opening is formed on an exposed sidewall of the control gate layer, and a bottom of the opening is lower than or coplanar with the top surface of the isolation layer; and

a metal silicide layer formed on an exposed surface of the control gate layer and the top surface of the isolation layer.