Patent ID: 11914439
Assignee: ROHM CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 11:
12. The digital processing device according to claim 11,
wherein the first and second frequency dividers are each composed of a plurality of stages of frequency-division flip-flops each having a data input terminal, a data output terminal, and a clock input terminal,
in each frequency-division flip-flop in each frequency divider, a logically inverted signal of an output signal from the data output terminal becomes an input signal to the data input terminal, and
among the plurality of stages of frequency-division flip-flops in the first frequency divider,
the first clock signal is input to the clock input terminal of an initial-stage frequency-division flip-flop,
to the clock input terminal of each frequency-division flip-flop except the initial-stage frequency-division flip-flop, an output signal from the data output terminal of a frequency-division flip-flop in a preceding stage is input, and
the first frequency-divided clock signal is output from the data output terminal of a final-stage frequency-division flip-flop in the first frequency divider, and

among the plurality of stages of frequency-division flip-flops in the second frequency divider,
the second clock signal is input to the clock input terminal of an initial-stage frequency-division flip-flop,
to the clock input terminal of each frequency-division flip-flop except the initial-stage frequency-division flip-flop, an output signal from the data output terminal of a frequency-division flip-flop in a preceding stage is input, and

the second frequency-divided clock signal is output from the data output terminal of a final-stage frequency-division flip-flop in the second frequency divider.