Patent ID: 11972347
Assignee: TECHNION RESEARCH & DEVELOPMENT FOUNDATION LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A system for training a classification system's quantized neural network dataset, comprising at least one hardware processor adapted to:
receive digital input data comprising a plurality of training input value sets and a plurality of target value sets;
in each training iteration of a plurality of training iterations:
for each layer, comprising a plurality of weight values, of one or more layers of a plurality of layers of a neural network:
compute a set of transformed values by applying to a plurality of layer values, comprising a plurality of previous layer output values of a previous layer and the layer's plurality of weight values, one or more emulated non-uniformly quantized transformations by adding to each value of the plurality of layer values one or more uniformly distributed random noise values; and
compute a plurality of layer output values by applying to the set of transformed values one or more arithmetic operations;
compute a plurality of training output values from a combination of the plurality of layer output values of a last layer of the plurality of layers; and
update one or more of the plurality of weight values of the one or more layers to decrease a value of a loss function computed using the plurality of target value sets and plurality of training output values; and
output the updated plurality of weight values of the plurality of layers,
wherein the at least one hardware processor is adapted to receive the digital data by one of the following:
via at least one data communication network interface connected to the at least one hardware processor,
reading the digital data from a digital storage electrically connected to the at least one hardware processor, and
reading the digital data from a digital storage connected to the at least one hardware processor via at least one data communication network interface connected to the at least one hardware processor.