Patent ID: 11880265
Assignee: NVIDIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A receiver device comprising:
detection logic to receive a first set of data frames using a first clock and detect one or more frame errors in the first set of data frames;
error counter logic comprising subtraction logic, addition logic, and a latch to store a count of the one or more frame errors detected in the first set of data frames, wherein the latch is clocked by the first clock, wherein the addition logic is to increment a first count for each error indication received from the detection logic, wherein the subtraction logic is to reset the first count to zero responsive to receiving a period marker signal corresponding to a programmable period and a decrement signal having a zero value, wherein the subtraction logic is to reduce the first count by a non-zero value to obtain a second count responsive to receiving the period marker signal and the decrement signal having the non-zero value, wherein the first count or second count is reset to zero responsive to receiving a reset signal;
time period logic coupled to the error counter logic, the time period logic to receive a second clock and an indication of the programmable period, the time period logic to output the period marker signal at an end of each programmable period; and
threshold logic coupled to the error counter logic, the threshold logic to compare the count stored at the error counter logic with a threshold number of frame errors and output an interrupt responsive to the count satisfying the threshold number of frame errors.