Patent ID: 11907547
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G  H

Claim 7:
8. A memory device, comprising:
an array of memory cells; and
a controller for access of the array of memory cells, wherein the controller is configured to cause the memory device to:
determine whether the memory device is waiting to initiate a next phase of an access operation on the array of memory cells;
in response to determining that the memory device is waiting to initiate the next phase of the access operation:
determine a value of a current budget reserve corresponding to the memory device;
determine an available current budget to be equal to a total current budget available to a plurality of memory devices minus the current budget reserve corresponding to the memory device, wherein the plurality of memory devices includes the memory device and one or more other memory devices in communication with the memory device;
determine whether there is sufficient available current budget to initiate the next phase of the access operation in a selected operating mode;
in response to determining that there is sufficient available current budget to initiate the next phase of the access operation in the selected operating mode, broadcast an expected peak current magnitude for the selected operating mode to remaining memory devices of the plurality of memory devices; and
in response to determining that there is insufficient available current budget to initiate the next phase of the access operation in the selected operating mode, broadcast an expected peak current magnitude for a paused memory device to the remaining memory devices of the plurality of memory devices.