Patent ID: 11961552
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device comprising:
a first wafer including a logic structure disposed on a top surface of the first wafer and a cell structure disposed on the bottom surface of the first wafer, wherein a cell region is disposed in the cell structure and a pass transistor circuit is disposed in the logic structure,
a second wafer including a page buffer circuit, a peripheral circuit and a block switch circuit, and
a plurality of bit lines extending in a first direction and arranged in a second direction,
wherein the cell region includes a plane and is coupled to the plurality of bit lines,
wherein the plane is divided into a plurality of memory groups, each including a plurality of partial pages, that are disposed in a plurality of rows arranged in the first direction.