Patent ID: 11870398
Assignee: PSEMI CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A circuital arrangement comprising:
an amplifier comprising an input transistor and a plurality of cascode transistors comprising a first cascode transistor coupled to the input transistor and remaining one or more cascode transistors;
a biasing circuit comprising:
a first plurality of series-connected resistors coupled between a substantially fixed reference voltage and a reference ground, the first plurality of series-connected resistors coupled to one another through one or more first nodes;
a second plurality of series-connected resistors coupled between a varying supply voltage to the amplifier and a reference ground, the second plurality of series-connected resistors coupled to one another through one or more second nodes;

wherein:
a gate of the first cascode transistor is coupled to a respective node of the one or more first nodes, and
gates of the remaining one or more cascode transistors are coupled to respective nodes of the one or more second nodes.