Patent ID: 11971821
Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 22:
23. A method for write-back and invalidation in a hierarchical cache structure based on one single designated key identification code, comprising:
in response to a first instruction of an instruction set architecture that is fetched by a first core for write-back and invalidation in a hierarchical cache structure based on one single designated key identification code, operating a decoder of the first core to output at least one microinstruction, wherein the first core is provided within a first processor that is fabricated on a first die;
based on the at least one microinstruction, a write-back and invalidation request is provided to a first in-core cache module of the first core through a memory ordering buffer of the first core, and then passed to a first last-level cache by the first in-core cache module, wherein the first last-level cache is fabricated outside of the first core within the first processor; and
in response to the write-back and invalidation request, operating the first last-level cache to search itself to determine which cache lines within the first last-level cache match the designated key identification code, wherein: if a matched cache line has been modified and does not exist in any upper-level cache, the first last-level cache writes back the matched cache line to a system memory; and, whether modified or not, all matched cache lines within the first last-level cache are invalidated.