Patent ID: 11928025
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. An apparatus, comprising:
a plurality of memory devices; and
a controller coupled to the plurality of memory devices via a plurality of respective channels, the controller configured to:
read, from at least a first portion of a first group of memory devices of the plurality of memory devices, host data and first error correction code (ECC) data;
perform an error detection operation using the first ECC data to indicate whether the host data includes an amount of errors; and
responsive to the error detection operation indicating the amount of errors in the host data;
read, from a second group of the memory device of the plurality of memory devices, second ECC data different than the first ECC data; and
to perform an error correction operation to correct the amount of errors using the second ECC data:
read other host data from a second portion of the first group of memory devices; and
perform an XOR operation among the other host data and the second ECC data to recover the host data.