Patent ID: 11948656
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. The method of claim 7, further comprising:
initiating a third testing operation on a third subset of the set of memory cells;
activating the first row of memory cells a second quantity of times based at least in part on initiating the third testing operation;
outputting, by the circuitry, at least one bit of the third subset from a third multiplexer of the plurality of multiplexers to a fourth multiplexer of the plurality of multiplexers based at least in part on activating the first row of memory cells the second quantity of times; and
generating, by the circuitry, a third flag indicating an error condition of the third subset based at least in part on outputting the at least one bit of the third subset from the third multiplexer to the fourth multiplexer.