Patent ID: 11888332
Assignee: NAVITAS SEMICONDUCTOR LIMITED
Field: Semiconductors (Electrical engineering)
Classification: CPC H  Y | IPC H

Claim 6:
7. An electronic device comprising:
a gallium-nitride based monolithic semiconductor substrate;
a plurality of flip-chip bumps coupled to the monolithic semiconductor substrate;
an under-voltage lock-out circuit formed on the monolithic semiconductor substrate;
a low-side transistor disposed on the monolithic semiconductor substrate, the low-side transistor including a low-side transistor control gate, a low-side source, and a low-side drain wherein the low-side transistor is controlled by a low-side transistor driver circuit arranged to control a conductivity state of the low-side transistor in response to receiving a first input signal; and
a high-side transistor disposed on the monolithic semiconductor substrate, the high-side transistor including a high-side transistor control gate, a high-side source, and a high-side drain wherein the high-side transistor is controlled by a high-side transistor driver circuit arranged to control a conductivity state of the high-side transistor in response to receiving a second input signal;
wherein the low-side drain is electrically connected to the high-side source forming a switch-node of a half-bridge circuit.