Patent ID: 11928063
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A system comprising:
a memory device comprising multiple dice; and
a processing device coupled to the memory device, the processing device to perform operations comprising:
causing programming of virtual blocks across planes of the multiple dice;
creating logical-to-physical address translation (L2P) tables to track physical address locations to which logical addresses are mapped;
creating an L2P bitmap for a respective virtual block, the L2P bitmap identifying logical addresses, within each respective L2P table, that belong to the respective virtual block;
creating a virtual block (VB) bitmap for each respective L2P table, the VB bitmap identifying virtual blocks to which the respective L2P table points;
creating an updated VB bitmap for a first L2P table based on changes to the first L2P table due to programming the virtual blocks after closing the first L2P table;
determining that an entry in the VB bitmap is different than the entry in the updated VB bitmap, the entry corresponding to a particular virtual block;
identifying an L2P bitmap corresponding to the particular virtual block;
changing a bit within the identified L2P bitmap for an L2P mapping corresponding to the entry; and
determining, based on the identified L2P bitmap, one or more L2P tables of the respective L2P tables that contain valid logical addresses for the particular virtual block.