Patent ID: 11881254
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 13:
14. The enable control circuit according to claim 13, wherein
the selection circuit is configured to: responsive the first config signal indicating that neither an Additive Latency (AL) nor a Parity Latency (PL) is turned on, select a first indication signal as the target achievement signal and determine that the target clock cycle count value is a first value, wherein the first value is greater than or equal to a value obtained by subtracting 2 from a column address write latency (CWL);
the selection circuit is configured to: responsive to the first config signal indicating that both the AL and the PL are turned on, select a second indication signal as the target achievement signal and determine that the target clock cycle count value is a second value, wherein the second value is greater than or equal to a value obtained by subtracting 2 from a sum of the CWL, the AL, and the PL;
the selection circuit is configured to: responsive to the first config signal indicating that the AL is turned on and the PL is not turned on, select a third indication signal as the target achievement signal and determine that the target clock cycle count value is a third value, wherein the third value is greater than or equal to a value obtained by subtracting 2 from a sum of the CWL and the AL; or
the selection circuit is configured to: responsive to the first config signal indicating that the PL is turned on and the AL is not turned on, select a fourth indication signal as the target achievement signal and determine that the target clock cycle count value is a fourth value, wherein the fourth value is greater than or equal to a value obtained by subtracting 2 from a sum of the CWL and the PL,
wherein the first indication signal indicates that the clock cycle count value reaches the first value, the second indication signal indicates that the clock cycle count value reaches the second value, the third indication signal indicates that the clock cycle count value reaches the third value, and the fourth indication signal indicates that the clock cycle count value reaches the fourth value.