Patent ID: 11923846
Assignee: UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A ternary logic circuit comprising:
a first inverter unit electrically connected to an input terminal and an output terminal;
a second inverter unit electrically connected to the input terminal and the output terminal and arranged in parallel with the first inverter unit;
a first junction unit arranged between the first inverter unit and the output terminal and including a tunnel PN junction; and
a second junction unit arranged between the second inverter unit and the output terminal and including a tunnel PN junction,
wherein, the first inverter unit includes a first transistor having a first threshold voltage and a second transistor that is arranged in series with the first transistor and has a second threshold voltage,
the second inverter unit includes a third transistor having a third threshold voltage and a fourth transistor that is arranged in series with the third transistor and has a fourth threshold voltage,
the first transistor and the third transistor include a p-type channel, and the second transistor and the fourth transistor include an n-type channel, and
when an absolute value of an input voltage applied to the input terminal is less than a first input voltage, the output terminal outputs a first output voltage, and when the absolute value of the input voltage is greater than the first input voltage and less than a second input voltage, the output terminal outputs a second output voltage, and when the absolute value of the input terminal is greater than the second input voltage, the output terminal outputs a third output voltage.