Patent ID: 11935950
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor device comprising:
an n-type buried layer over a substrate;
a p-type buried layer over the n-type buried layer;
a first well over the p-type buried layer, wherein sidewalls of the p-type buried layer are surrounded by the first well;
a first high voltage n-type well extending through the first well;
a second high voltage n-type well extending through the first well;
a third high voltage n-type well extending through the first well, wherein the second high voltage n-type well is interposed between the first high voltage n-type well and the third high voltage n-type well;
a first drain/source region in the first high voltage n-type well;
a first gate electrode over the first well; and
a second drain/source region in the second high voltage n-type well.