Patent ID: 11894456
Assignee: NUVOTON TECHNOLOGY CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H  Y | IPC H

Claim 0:
1. A semiconductor device of chip-size package type that is face-down mountable, the semiconductor device comprising:
a semiconductor layer; and
N vertical MOS transistors in the semiconductor layer, where N is an integer greater than or equal to three, the N vertical MOS transistors including a first vertical MOS transistor, a second vertical MOS transistor, and a third vertical MOS transistor, wherein
each of the N vertical MOS transistors includes, on an upper surface of the semiconductor layer, a gate pad electrically connected to a gate electrode of the vertical MOS transistor and a source pad electrically connected to a source electrode of the vertical MOS transistor,
the semiconductor layer includes a semiconductor substrate,
the semiconductor substrate functions as a common drain region for the N vertical MOS transistors,
in a plan view of the semiconductor layer, the semiconductor device has a rectangular shape including a first outer peripheral side, a second outer peripheral side adjacent to the first outer peripheral side, a third outer peripheral side adjacent to the first outer peripheral side, and a fourth outer peripheral side opposing the first outer peripheral side,
in a plan view of the semiconductor layer, the first vertical MOS transistor:
has a polygonal shape including a first side whose entire length faces the first outer peripheral side, a second side whose entire length faces the second outer peripheral side and that is adjacent to the first side, and a third side whose entire length faces the third outer peripheral side and that is adjacent to the first side; and
is arranged such that no other vertical MOS transistor among the N vertical MOS transistors is provided between the first outer peripheral side and the first side, between the second outer peripheral side and the second side, or between the third outer peripheral side and the third side,

in a plan view of the semiconductor layer, the second vertical MOS transistor:
has a polygonal shape including a fourth side whose entire length faces the second outer peripheral side, and a fifth side whose entire length faces the fourth outer peripheral side and that is adjacent to the fourth side; and
is arranged such that no other vertical MOS transistor among the N vertical MOS transistors is provided between the second outer peripheral side and the fourth side or between the fourth outer peripheral side and the fifth side,

in a plan view of the semiconductor layer, the third vertical MOS transistor:
has a polygonal shape including a sixth side whose entire length faces the third outer peripheral side, and a seventh side whose entire length faces the fourth outer peripheral side and that is adjacent to the sixth side; and
is arranged such that no other vertical MOS transistor among the N vertical MOS transistors is provided between the third outer peripheral side and the sixth side or between the fourth outer peripheral side and the seventh side,

for each of the N vertical MOS transistors, a surface area of the vertical MOS transistor in a plan view of the semiconductor layer increases with an increase in a maximum specified current of the vertical MOS transistor, and
S1>S2=S3 or S1<S2=S3, where S1 is the surface area of the first vertical MOS transistor in a plan view of the semiconductor layer, S2 is the surface area of the second vertical MOS transistor in a plan view of the semiconductor layer, and S3 is the surface area of the third vertical MOS transistor in a plan view of the semiconductor layer.