Patent ID: 11934843
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 10:
11. A system comprising:
a system memory; and
a processor coupled with the system memory, the processor comprising:
decode circuitry to decode a SEAMCALL instruction for a virtual machine monitor (VMM) in legacy virtual machine extensions (VMX) root operation mode; and
execution circuitry to perform operations corresponding to the SEAMCALL instruction, including to:
cause a virtual machine (VM) exit;
transition the processor from the legacy VMX root operation mode to a secure arbitration mode (SEAM) VMX root operation mode, wherein a SEAM module is to be hosted in the SEAM VMX root operation mode;
store a VMM state of the processor to a virtual machine control structure (VMCS);
load a SEAM module state of the processor from the VMCS;
inhibit system management interrupts (SMI) and non-maskable interrupts (NMI) in the SEAM VMX root operation mode; and
invoke the SEAM module.