Patent ID: 11923358
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A device, comprising:
a first transistor on a substrate, the first transistor comprising a first gate structure, first source/drain regions on opposite sides of the first gate structure, and first gate spacers spacing the first gate structure apart from the first source/drain regions;
a second transistor on the substrate, the second transistor comprising a second gate structure, second source/drain regions on opposite sides of the second gate structure, and second gate spacers spacing the second gate structure apart from the second source/drain regions;
a first contact forming a first contact interface with a first one of the first source/drain regions; and
a second contact forming a second contact interface with a first one of the second source/drain regions,
wherein an area ratio of the first contact interface to a top surface of the first one of the first source/drain regions is greater than an area ratio of the second contact interface to a top surface of the first one of the second source/drain regions, the top surface of the first one of the first source/drain regions is partially covered by one of the first gate spacers, but the top surface of the first one of the second source/drain regions is not covered by the second gate spacers.