Patent ID: 11903220
Assignee: SK HYNIX INC.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 0:
1. An electronic device comprising a semiconductor memory, the semiconductor memory comprising:
a substrate including a cell region, a first peripheral circuit region disposed at a first side of the cell region in a first direction, and a second peripheral circuit region disposed at a second side of the cell region in a second direction crossing the first direction;
a plurality of first lines disposed over the substrate and extending in the first direction across the cell region and the first peripheral circuit region;
a plurality of second lines disposed over the first lines and extending in the second direction across the cell region and the second peripheral circuit region;
a contact plug disposed in the second peripheral circuit region and having an upper surface coupled to a second line of the second lines;
a plurality of third lines disposed over the second lines and respectively overlapping the second lines;
a plurality of fourth lines disposed over the third lines and respectively overlapping the first lines;
a plurality of first memory cells disposed in the cell region and located at intersections of the first lines and the second lines between the first lines and the second lines; and
a plurality of second memory cells disposed in the cell region and located at intersections of the third lines and the fourth lines between the third lines and the fourth lines,
wherein a first portion of a third line of the third lines located in the cell region and a second portion of the third line located over the contact plug contact the second line, and
at least a part of a remainder of the third line is spaced apart from the second line.