Patent ID: 11860550
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A method, comprising:
forming a first sacrificial structure with a first spacer and a second sacrificial structure with a second spacer on a substrate;
forming an opening in a photoresist layer on the first and second sacrificial structures, wherein the opening is above the first and second spacers, and wherein a width of the opening is greater than a width between the first and second spacers;
removing a portion of the substrate between the first and second spacers to form a via opening;
forming a via structure in the via opening;
removing the first sacrificial structure to form a metal line opening;
forming a metal line in the metal line opening; and
forming, on the metal line, a capping layer with a bottom surface coplanar with a top surface of the first spacer.