Patent ID: 11868645
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 16:
17. A controller for a storage device, the controller comprising:
at least one processor configured to,
generate a patrol read command in response to a patrol read instruction, and
generate block address information based on reliability information for each of a plurality of memory cell blocks included in the storage device the reliability information generated based on weighted retention times and weighted program-erase counts; and

a memory interface configured to provide the patrol read command and the block address information to the storage device,
wherein the block address information comprises an order of a patrol read operation for the memory cell blocks based on the reliability information,
the at least one processor is further configured to perform the patrol read operation in response to the patrol read command such that the patrol read operation is performed in an ascending order of reliabilities of the memory cell blocks based on the reliability information, and
the order of the patrol read operation indicates a first memory cell block having a highest priority, a second memory cell block having a lowest priority and a third memory cell block having a priority between the highest priority and the lowest priority.