Patent ID: 11935783
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A structure, comprising:
a first conductive line and a second conductive line;
a first dielectric layer sandwiched between the first conductive line and the second conductive line;
a catalyst layer disposed on the first dielectric layer;
a dielectric alignment feature disposed directly on the catalyst layer;
an etch stop layer conformally extending along a top surface of the first conductive line, a sidewall of the catalyst layer, a sidewall of the dielectric alignment feature, and a top surface of the dielectric alignment feature;
a second dielectric layer over the etch stop layer;
a contact via disposed directly over the first conductive line and a portion of the dielectric alignment feature; and
a third conductive line disposed on the contact via,
wherein the contact via and the third conductive line are embedded in the second dielectric layer.