Patent ID: 11868266
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 8:
9. An apparatus, comprising:
a memory die, comprising:
an interface; and
a plurality of banks of memory, each coupled to the interface; and

control circuitry coupled to the memory die, wherein the control circuitry is configured to:
receive, and store in a register, an indication of a memory operation load from an application to be executed for at least one of a plurality of logical addresses;
wherein the plurality of logical addresses correspond to the plurality of banks; and
wherein the indication is of a particular logical address that will have a greatest memory operation load from the application; and

remap a logical to physical addressing of at least one of the plurality of banks based on the indication; and
remap a physical address of a particular memory bank closest to the interface to the particular logical address according to the indication stored in the register.