Patent ID: 11875851
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A semiconductor memory device, comprising:
a bit line;
a source line;
a first memory string including:
a first select transistor having one end coupled to the bit line;
a first memory cell transistor having one end coupled to the other end of the first select transistor;
a second memory cell transistor having one end coupled to the other end of the first memory cell transistor; and
a second select transistor having one end coupled to the other end of the second memory cell transistor and the other end coupled to the source line;

a second memory string including:
a third select transistor having one end coupled to the bit line;
a third memory cell transistor having one end coupled to the other end of the third select transistor;
a fourth memory cell transistor having one end coupled to the other end of the third memory cell transistor; and
a fourth select transistor having one end coupled to the other end of the fourth memory cell transistor and the other end coupled to the source line;

a first select gate line coupled to a gate of the first select transistor;
a second select gate line coupled to a gate of the third select transistor;
a first word line coupled to a gate of the first memory cell transistor and a gate of the third memory cell transistor;
a second word line coupled to a gate of the second memory cell transistor and a gate of the fourth memory cell transistor; and
a voltage generation circuit, wherein
during a first period of a read operation to read data from the first memory cell transistor, the voltage generation circuit:
applies a first voltage greater than a ground voltage to the first selection gate line,
applies a second voltage greater than the ground voltage to the second selection gate line,
applies a third voltage greater than the ground voltage to the first word line, and
applies a fourth voltage greater than the ground voltage to the second word line, and, during a second period of the read operation to read data from the first memory cell transistor after the first period, the voltage generation circuit:
applies a fifth voltage greater than the ground voltage to the first selection gate line,
applies a sixth voltage smaller than the fifth voltage and greater than the ground voltage to the second selection gate line,
applies a seventh voltage to the first word line, and
applies an eighth voltage greater than the seventh voltage to the second word line.