Patent ID: 11968289
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 16:
17. The clock data recovery circuit of claim 12, wherein the phase detector includes:
a second flip-flop, wherein an input terminal of the second flip-flop is configured to receive the input signal, a control terminal of the second flip-flop is configured to receive the clock signal, and an output terminal of the second flip-flop is electrically connected to the fourth node;
a third flip-flop, wherein an input terminal of the third flip-flop is electrically connected to the output terminal of the second flip-flop, and a control terminal of the third flip-flop is configured to receive the clock signal; and
a first XOR gate, wherein a first input terminal of the first XOR gate is electrically connected to the fourth node, a second input terminal of the first XOR gate is electrically connected to an output terminal of the third flip-flop, and an output terminal of the first XOR gate is configured to output a first portion of the phase adjustment signal.