Patent ID: 11922069
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. An apparatus, comprising:
a memory comprising a plurality of planes that each comprise a plurality of blocks, wherein each block of the plurality of blocks includes a plurality of non-volatile memory cells; and
a controller coupled with the memory and operable to:
receive, from a host device, a first command for writing first data to the memory in a first mode;
write, in the first mode, a first portion of the first data to at least a first block of a first set of blocks of the memory based at least in part on receiving the first command from the host device and a first cursor value associated with the first mode indicating the first set of blocks, wherein the first mode comprises writing a plurality of bits of data per memory cell;
write, in a second mode, a second portion of the first data to at least a second block of the first set of blocks based at least in part on receiving the first command from the host device, wherein the second mode comprises writing one bit of data per memory cell;
receive, from the host device, a second command for writing second data to the memory in the second mode, wherein upon receiving the second command a second cursor value associated with the second mode indicates the first set of blocks; and
write, in the second mode, the second data to one or more blocks of a second set of blocks of the memory based at least in part on receiving the second command from the host device and the second cursor value associated with the second mode indicating the first set of blocks.