Patent ID: 11973041
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A multi-die electronic package, comprising:
a first die in a first mold layer, the first die comprising interconnections;
a first plurality of vias in the first mold layer, the first plurality of vias laterally adjacent to a first side of the first die, each of the first plurality of vias extending from a top surface of the first mold layer to a bottom surface of the first mold layer;
a second plurality of vias in the first mold layer, the second plurality of vias laterally adjacent to a second side of the first die, each of the second plurality of vias extending from the top surface of the first mold layer to the bottom surface of the first mold layer;
a second die electrically coupled to the first die, and the second die electrically coupled to the first plurality of vias;
a third die electrically coupled to the first die, the third die electrically coupled to the second die by the interconnections of the first die, wherein the first mold layer is not vertically between the first die and the second die, and the first mold layer is not vertically between the first die and the third die;
a second mold layer between and in contact with the second die and the third die, the second mold layer having an upper surface co-planar with an upper surface of the second die, the second mold layer between the second die and the first die, the second mold layer between the third die and the first die, and the second mold layer in contact with the interconnections of the first die; and
a solder resist beneath the first die, wherein the plurality of mid-level interconnects is in the solder resist.