Patent ID: 11893281
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A storage device, comprising:
a non-volatile memory (NVM); and
a storage device controller, comprising:
a NVM interface coupled to the NVM, and
a universal flash storage interconnect;

the storage device controller configured to:
receive a first write-verify thread as a first simple write command Universal Flash Storage protocol information unit (UPIU) and as a first simple read command UPIU with a first extra header segment with a first execution condition whether a first write command of the first simple write command UPIU has completed;
receive a second write-verify thread as a second simple write command UPIU and as a second simple read command UPIU with a second extra header segment with a second execution condition whether a second write command of the second simple write command UPIU is completed; and
execute the first write-verify thread and the second write-verify thread in parallel.