Patent ID: 11956134
Assignee: UFI SPACE CO., LTD.
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. The multi-link receiver as described in claim 5, wherein the processing circuit comprises:
a second range determination circuit, coupled to the N number of indicator generators, and being configured to:
take the reference delay range of the j-th data section of the i-th data frame as the designated delay range corresponding to the i-th data frame; and
in response to determining that the receiving time points of the data sections of the i-th data frame are each within the designated delay range corresponding to the i-th data frame, provide a first command; and

a restoring circuit, coupled to the second range determination circuit and the N number of indicator generators, and in response to the first command, restoring the i-th data frame based on the N number of data sections of the i-th data frame.