Patent ID: 11967547
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. The semiconductor structure of claim 1, wherein the multi-tiered solder-resist structure comprises:
a first tier comprising a first dielectric material and including first conductive bump openings defined by inner sidewalls of the first tier, the first tier having a first width measured through the first dielectric material between the inner sidewalls of the first tier;
a second tier comprising a second dielectric material and including second conductive bump openings defined by inner sidewalls of the second tier, the second tier having a second width measured through the second dielectric material between the inner sidewalls of the second tier; and
a third tier comprising a third dielectric material and including third conductive bump openings defined by inner sidewalls of the third tier, the third tier having a third width measured through the third dielectric material between the inner sidewalls of the third tier;
wherein the first width is greater than the second width, and wherein the second width is greater than third width.