Patent ID: 11942177
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. A memory system comprising:
a memory array including:
a set of switches coupled to a global bit line;
a first set of memory cells coupled in parallel between a first local select line and a first local bit line that is further coupled to the set of switches, such that the set of switches is coupled between the first set of memory cells and the global bit line; and
a second set of memory cells coupled in parallel between a second local select line and a second local bit line that is further coupled to the set of switches, such that the set of switches is coupled between the second set of memory cells and the global bit line; and

a controller connected to the memory array, wherein the controller is configured to select at least one switch of the set of switches.