Patent ID: 11862286
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 6:
7. The data transmission circuit of claim 6, wherein the write enable circuit comprises:
a first inverter, having an input terminal configured to be electrically connected to the initial write enable signal, and an output terminal configured to output a first inverted write enable signal;
a first NOR gate, having input terminals configured to be electrically connected to the data polarity identification signal and the output terminal of the first inverter, and an output terminal configured to output the write enable signal;
a second inverter, having an input terminal configured to be electrically connected to the data polarity identification signal, and an output terminal configured to output an inverted data polarity identification signal; and
a second NOR gate, having input terminals configured to be electrically connected to the output terminal of the second inverter and the output terminal of the first inverter, and having an output terminal configured to output the inverted write enable signal.