Patent ID: 11893240
Assignee: QUALCOMM INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A method for reducing latency in a pseudo channel based memory system, comprising:
receiving a mode register write command configured to cause the pseudo channel based memory system to handle a successive memory access command as a low latency type memory access command;
receiving a successive memory access command targeting the first pseudo channel;
communicatively connecting a first pseudo channel of a plurality of pseudo channels to a first input/output (IO) of a plurality of IOs by a first pseudo channel selection device configured to selectively communicatively connect one of the plurality of pseudo channels to the first IO; and
communicatively connecting the first pseudo channel to a second IO of the plurality of IOs by a second pseudo channel selection device concurrently with communicatively connecting the first pseudo channel to the first IO by the first pseudo channel selection device in a first operation mode, wherein the second pseudo channel selection device is configured to selectively communicatively connect one of the plurality of pseudo channels to the second IO; wherein communicatively connecting the first pseudo channel to the second IO by the second pseudo channel selection device concurrently with communicatively connecting the first pseudo channel to the first IO by the first pseudo channel selection device occurs in response to receiving the mode register write command and in response to receiving the successive memory access command.