Patent ID: 11943130
Assignee: VIAVI SOLUTIONS INC.
Field: Digital communication (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 5:
6. An apparatus comprising:
at least one hardware processor; and
a memory having stored thereon machine readable instructions, the machine readable instructions, when executed by the at least one hardware processor, cause the at least one hardware processor to:
ascertain a test speed that corresponds to a maximum specified data transfer rate for a data transmission link that is to be tested;
determine a maximum specified processing speed of at least one test processor of a test instrument;
determine whether the maximum specified processing speed of the at least one test processor of the test instrument is less than the test speed;
based on a determination that the maximum specified processing speed of the at least one test processor of the test instrument is less than the test speed, divide the test speed into a plurality of test ranges corresponding to the at least one test processor, wherein a total value of the plurality of test ranges is at least equal to the test speed;
perform, for the at least one test processor, a test corresponding to each test range of the plurality of test ranges;
obtain a test result for each test range of the plurality of test ranges; and
generate, based on aggregation of the test results for the plurality of test ranges, an aggregated test result that represents an actual speed associated with the data transmission link.