Patent ID: 11894042
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 19:
20. The semiconductor memory of claim 19, wherein the first clock circuit comprises a first two-input NAND gate, a second two-input NAND gate and a first NOT gate,
wherein input ends of the first two-input NAND gate are respectively connected with the first refresh state signal and the initial refresh execution signal;
wherein input ends of the second two-input NAND gate are respectively connected with an output end of the first two-input NAND gate and the refresh pulse signal, and an output end of the second two-input NAND gate is configured to output the first inverted clock signal;
wherein an input end of the first NOT gate is connected with the first inverted clock signal, and an output end of the first NOT gate is configured to output the first clock signal.