Patent ID: 11916102
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  Y | IPC H

Claim 3:
4. The method according to claim 1, wherein the stack structure comprises a first support layer, a first sacrificial layer, a second support layer, a second sacrificial layer and a third support layer successively stacked along a direction perpendicular to the substrate; and, the removing a part of the auxiliary layer and several of the support layers and the sacrificial layers comprises:
forming a photoresist layer covering the auxiliary layer, the photoresist layer having an etching window for exposing the auxiliary layer; and
successively etching the auxiliary layer, the third support layer, the second sacrificial layer, the second support layer and the first sacrificial layer along the etching window, so that a remaining of the auxiliary layer is divided into a plurality of sub-auxiliary layers, each of the sub-auxiliary layers being overlapped with two capacitor holes.