Patent ID: 11921623
Assignee: SECURED-IC SAS
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 3:
4. The device of claim 1, wherein the statistical tests comprise the AIS Monobit Test which provides a sum value T1, the corresponding lower threshold L1 and the higher threshold H1 being equal to:, L
       1
      
      =
      
       
        N
        2
       
       -
       
        
         
          N
          2
         
        
        ×
        
         
          erfc
          
           -
           1
          
         
         (
         α
         )
        
       
      
     
     ,
        
     and
    
   
  
  
   
    
     
      
       H
       1
      
      =
      
       
        N
        2
       
       +
       
        
         
          N
          2
         
        
        ×
        
         
          erfc
          
           -
           1
          
         
         (
         α
         )
        
       
      
     
     ,
    
   
  
 

with α representing the target error probability.