Patent ID: 11967535
Assignee: KLA CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 8:
9. A method for measuring an overlay error, comprising:
depositing and patterning at least first and second thin-film layers on a semiconductor substrate to define a matrix of dies, which are separated by scribe lines and contain active areas circumscribed by the scribe lines;
forming a plurality of overlay targets in the first and second thin-film layers within each of the active areas, each overlay target having dimensions no greater than 10 μm×10 μm in a plane parallel to the substrate and comprising a first linear grating formed in the first thin-film layer and having a first grating vector and a second linear grating formed in the second thin-film layer, in proximity to the first linear grating, and having a second grating vector parallel to the first grating vector;
capturing images of the plurality of overlay targets;
processing the images to find a displacement between the first and second linear gratings; and
measuring an overlay error between the first and second thin-film layers responsively to the displacement.