Patent ID: 11967615
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. A method of forming semiconductor device comprising:
forming a first gate stack on a semiconductor substrate having a first lattice constant, the gate stack having a gate electrode;
forming a first recess on a source side of the gate stack to a first depth and forming a second recess on the drain side of the gate stack to a second depth, wherein the first depth is greater than the second depth, wherein a portion of the first recess is beneath the gate electrode of the gate stack, and a portion of the second recess is beneath the gate electrode of the gate stack, wherein the portion of the first recess extends laterally further beneath the gate electrode than the portion of the second recess, and wherein the portion of the first recess does not vertically overlap the portion of the second recess;
forming a semiconductor material in the first recess to form a source region and forming the semiconductor material in the second recess to form a drain region, wherein semiconductor material has a second lattice constant, wherein the second lattice constant is different than the first lattice constant; and
forming a second gate stack on the source side of the first gate stack and forming a third gate stack on the drain side of the first gate stack, wherein the second gate stack is separated from the first gate stack by a first distance and wherein the third gate stack is separated from the first gate stack by a second distance, wherein the first distance is greater than the second distance, wherein forming the first recess and forming the second recess comprise simultaneously etching the semiconductor substrate between the first and second gate stacks and the semiconductor substrate between the first and third gate stacks.