Patent ID: 11950407
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A memory device, comprising:
a first memory cell including a first storage cell and a first transistor to control access to the first storage cell;
a second memory cell including a second storage cell and a second transistor to control access to the second storage cell; and
a shared contact electrode that is shared between the first transistor and the second transistor, the shared contact electrode being coupled to a source area or a drain area of the first transistor, and coupled to a source area or a drain area of the second transistor, and further being coupled to a bit line of the memory device, wherein the shared contact is on a side of a first channel area and a second channel area opposite a first gate electrode and a second gate electrode of the first and second transistors, respectively, and wherein the first transistor further includes the first gate electrode coupled to a first word line, and the second transistor further includes the second gate electrode coupled to a second word line.