Patent ID: 11880706
Assignee: NANJING QINHENG MICROELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 2:
3. The interrupt control method based on RISC-V according to claim 2, wherein the step (a3) further comprises a nested interrupt, and the nested interrupt comprises the steps of:
(c1) when the processor is handling the first interrupt event, receiving and responding to a second interrupt request, and stopping handling the first interrupt event;
(c2) jumping, by the processor, to a second interrupt entry; meanwhile, updating the value of the control and status register set, storing the content of the Caller-save type general-purpose register before handling the second interrupt event into the level 2 sub-memory area of the second-type memory area, and/or storing the content of the control and status register set into the level 2 sub-memory area of the first-type memory area;
(c3) handling, by the processor, a second interrupt event; and
(c4) once the second interrupt event is completed, returning to continue handling the first interrupt event; and meanwhile, loading back the content from the level 2 sub-memory area of the second-type memory area into the Caller-save type general-purpose register and/or loading back the content from the level 2 sub-memory area of the first-type memory area into the control and status register set.