Patent ID: 11928329
Assignee: NXP B.V.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 3:
4. The IC of claim 2, wherein the register management system comprises:
an address decoder configured to (i) receive the write address, (ii) select, based on the write address, the set of storage elements from the plurality of storage elements to perform the write operation, and (iii) generate control data indicative of the selected set of storage elements; and
a controller that is coupled to the address decoder and the register, and configured to receive the functional data, the control data, and the set of register bits, wherein, based on the control data, the controller is further configured to (i) write the one or more write bits associated with the one or more mask bits having the first logic state to the one or more storage elements of the set of storage elements, respectively, and (ii) write the one or more register bits associated with the one or more mask bits having the second logic state, respectively, to the remaining storage elements of the selected set of storage elements.