Patent ID: 11916105
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 0:
1. A semiconductor device comprising:
a semiconductor stack including semiconductor layers over a substrate, wherein the semiconductor layers are separated from each other and are stacked up along a direction substantially perpendicular to a top surface of the substrate;
an isolation structure around a bottom portion of the semiconductor stack and separating active regions;
a metal gate structure over a channel region of the semiconductor stack and wrapping each of the semiconductor layers;
a gate spacer over a source/drain (S/D) region of the semiconductor stack and along sidewalls of a top portion of the metal gate structure; and
an inner spacer over the S/D region of the semiconductor stack and along sidewalls of lower portions of the metal gate structure and wrapping edge portions of each of the semiconductor layers,
wherein a side portion of the inner spacer includes a bump contacting the isolation structure.