Patent ID: 11892506
Assignee: MEDIATEK SINGAPORE PTE. LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 2:
3. A multicycle path circuit comprising:
a logic circuit configured to operate with a first clock signal of a first time period;
a memory coupled to the logic circuit and configured to operate with a second clock signal of a second time period that is a multiple of the first time period; and
an on-chip clock controller coupled to the logic circuit and the memory and configured to provide the first clock signal to the logic circuit and the second clock signal to the memory,
wherein the multicycle path circuit is configured to operate in a functional mode in which the logic circuit controls read and/or write of the memory, and
wherein the multicycle path circuit is configured to operate in an at-speed test mode in which the logic circuit controls read and/or write of the memory to test a transition, over a plurality of clock cycles of the first clock signal, of a value output from the memory,
wherein the on-chip clock controller receives an on-chip clock signal and modulates the on-chip clock signal to generate the first and second clock signals,
wherein the on-chip clock controller comprises:
a first pulse shaper that receives the on-chip clock signal and outputs a first test clock enable signal, and
a second pulse shaper that receives the on-chip clock signal and outputs a second test clock enable signal.