Patent ID: 11971823
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 22:
23. The device of claim 22, wherein the plurality of senders comprises a first sender and a second sender,
in the previous clock:
the first sender corresponds to first output data;
the second sender corresponds to second output data adjacent to the first output data; and
loaded first input data, second input data, third input data, fourth input data, fifth input data, and sixth input data are stored in a first address, a second address, a third address, a fourth address, a fifth address, and a sixth address of the reuse buffer, respectively,
in a current clock:
the first sender corresponds to third output data and the second sender corresponds to fourth output data adjacent to the third output data; and
the loader is configured to flush addresses allocated to the first input data, the second input data, the third input data, and the fourth input data, as the remaining input data, other than the fifth input data and the sixth input data overlapping input data corresponding to the third output data and the fourth output data on which a convolution operation is to be performed among input data loaded in the previous clock.