Patent ID: 11961840
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 9:
10. A semiconductor device structure, comprising:
a first gate electrode layer;
a second gate electrode layer disposed below and in contact with the first gate electrode, the second gate electrode layer comprising a material chemically different than the first gate electrode layer;
a first intermixed layer in contact with a portion of the first gate electrode layer, the first intermixed layer comprising a first material having a first polarity;
a second intermixed layer in contact with a portion of the second gate electrode layer and the first intermixed layer, the second intermixed layer comprising a second material having a second polarity opposite of the first polarity;
a high-K (HK) dielectric layer in contact with a portion of the first intermixed layer; and
a third intermixed layer in contact with a portion of the second intermixed layer and the HK dielectric layer, the third intermixed layer comprising a third material having the first polarity.