Patent ID: 11923292
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor package comprising:
a package substrate including a metal pad;
a semiconductor substrate vertically spaced apart from on an upper surface of the package substrate;
a conductive pad disposed on a lower surface of on the semiconductor substrate;
a protective layer disposed on the lower surface of on the semiconductor substrate and covering a side surface of the conductive pad and a first portion of a lower surface of the conductive pad, the protective layer having a pad opening exposing a second portion of the lower surface of the conductive pad;
a pillar pattern disposed in the pad opening and being in contact with the second portion of the lower surface the conductive pad;
a solder pattern disposed between the pillar pattern and the metal pad and electrically connected to the metal pad, the solder pattern comprising a solder seed pattern and a solder portion; and
a polymer layer being in physical contact with the upper surface of the package substrate, a lower sidewall of the pillar pattern, the protective layer, and at least a portion of a side surface of the semiconductor substrate,
wherein the lower sidewall of the pillar pattern is inclined to a top surface of the pillar pattern,
wherein a first lower surface of the protective layer on the lower surface of the semiconductor substrate is at a level different from a second lower surface of the protective layer on the first portion of a lower surface of the conductive pad, and
wherein the solder pattern comprises:
a metal material including at least one of copper and titanium and spaced apart from an edge portion of the pillar pattern; and
a solder material including at least one of tin, bismuth, lead, and silver, and in contact with the edge portion of the pillar pattern.