Patent ID: 11894263
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method, comprising:
providing a workpiece comprising a substrate, an etch stop layer (ESL) over the substrate, a dielectric layer over the ESL, and a silicon layer over the dielectric layer;
performing a first patterning process of the silicon layer to form a first trench and a second trench;
performing a second patterning process of the silicon layer to form a branch opening in fluid communication with the second trench but is spaced apart from the first trench;
forming a spacer along sidewalls of the first trench, the second trench and the branch opening;
after the forming of the spacer, performing a third patterning process of the silicon layer to form a gate signal line trench between the first trench and the second trench;
after the third patterning process of the silicon layer, etching the dielectric layer and the ESL using the silicon layer and the spacer as an etch mask; and
depositing a metal layer over the dielectric layer and the ESL.