Patent ID: 11917831
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An integrated chip comprising:
a first memory cell comprising:
a first conductive structure arranged over a substrate;
a memory layer arranged over the first conductive structure and comprising a ferroelectric material;
a second conductive structure arranged over the memory layer; and
an annealed seed layer arranged between and directly contacting the first conductive structure and the memory layer, wherein greater than 35 percent of the annealed seed layer is in an orthorhombic phase; and

a second memory cell that is level with the first memory cell and that comprises an additional annealed seed layer, wherein the additional annealed seed layer has a top surface recessed relative to a top surface of the annealed seed layer.