Patent ID: 11887931
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A semiconductor package, comprising:
a first semiconductor device on a first redistribution substrate;
a first mold layer that covers the first semiconductor device and the first redistribution substrate;
a second redistribution substrate on the first mold layer, the second redistribution substrate including:
a first opening that exposes a top surface of the first mold layer, and the second redistribution substrate having a thickness of about 20 μm to about 30 μm; and

a conductive pillar that penetrates the first mold layer and electrically connects the first redistribution substrate to the second redistribution substrate,
wherein the second redistribution substrate includes:
a first redistribution dielectric layer that contacts the first mold layer and has a first sidewall,
a second redistribution dielectric layer on the first redistribution dielectric layer, the second redistribution dielectric layer having a second sidewall spaced apart from the first sidewall, the second redistribution dielectric layer partially exposing a top surface of the first redistribution dielectric layer, and a distance between the first sidewall and the second sidewall being smaller than a first thickness of the first redistribution dielectric layer and smaller than a second thickness of the second redistribution dielectric layer, and
a first redistribution pattern between the first redistribution dielectric layer and the second redistribution dielectric layer, the first redistribution pattern penetrating the first redistribution dielectric layer and contacting the conductive pillar, and

wherein the first mold layer includes grooves on the top surface of the first mold layer, the grooves being spaced apart from a top surface of the first semiconductor device.