Patent ID: 11942522
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. The method for manufacturing the semiconductor structure according to claim 1, further comprising: before the removing the part of the protection layer, the part of the third conductive layer and the part the remaining portion of the second conductive layer to form the bit lines arranged at intervals,
forming a second laminated structure on the protection layer;
forming a second photoresist layer on the second laminated structure, and performing positive developing on the second photoresist layer by taking a second mask plate as a mask, to form a third pattern;
etching the second laminated structure along the third pattern, to form a fourth pattern in the second laminated structure; and
etching the protection layer, the third conductive layer and the second conductive layer by taking the second laminated structure having the fourth pattern as a mask, wherein a remaining portion of the protection layer, a remaining portion of the third conductive layer and the remaining portion of the second conductive layer forms the bit lines.