Patent ID: 11914941
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A computer-implemented method comprising:
generating, by a machine learning model, a prediction model for validating IC layouts;
receiving, by the prediction model, data comprising a set of test patterns comprising scanning electron microscope (SEM) images of IC patterns;
determining, by the prediction model, design violations associated with an IC layout based on the SEM images and the plurality of IC patterns by:
generating a compilation of pixel patterns including a first set of pixel patterns capable of being manufactured and a second set of pixel patterns incapable of being manufactured; and
identifying differences between the IC layout with the first set of pixel patterns and the second set of pixel patterns, wherein the design violations comprise the differences; and

providing a summary of the design violations for further characterization of the IC layout.