Patent ID: 11955515
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 0:
1. A semiconductor device, comprising:
a substrate;
first and second nanostructured channel regions disposed on the substrate;
first and second gate-all-around (GAA) structures surrounding the first and second nanostructured channel regions, respectively;
first and second source/drain (S/D) regions disposed on the substrate;
first and second contact structures disposed on first surfaces of the first and second S/D regions, respectively;
a third contact structure comprising an n-type work function metal (nWFM) silicide layer disposed on a second surface of the first S/D region and a dual metal liner disposed on the nWFM silicide layer; and
a fourth contact structure comprising a p-type WFM (pWFM) silicide layer disposed on a second surface of the second S/D region.