Patent ID: 11892502
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 2:
3. The integrated circuit of claim 1, wherein each of the first transistor and the second transistor comprises a control terminal, a first terminal and a second terminal, and the first inverter comprises a first terminal and a second terminal,
the control terminal of the first transistor is coupled to an output of the decoder, the first terminal of the first transistor is configured to receive a signal intended to be input to the operational TSV, the second terminal of the first transistor is coupled to an input of the operational TSV,
the first terminal of the first inverter is coupled to the output of the decoder, the second terminal of the first inverter is coupled to the control terminal of the second transistor,
the first terminal of the second transistor is configured to receive the signal intended to be input to the operational TSV, the second terminal of the second transistor is coupled to the input of the spare TSV.