Patent ID: 11875841
Assignee: POWERCHIP SEMICONDUCTOR MANUFACTURING CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 12:
13. A memory device, comprising:
at least one memory chip, each comprising:
a substrate;
a memory array, disposed on the substrate;
a plurality of bit lines, disposed on the substrate and coupled to the memory array;
a plurality of data paths, disposed on the substrate and corresponding to the bit lines, respectively, wherein the number of the data paths is equal to or less than the number of the bit lines; and
a sensing amplifier array, comprising a plurality of sensing amplifiers; and

a logic chip, comprising:
a plurality of data transmission ports, wherein the number of the data transmission ports is equal to a sum of the data paths of the at least one memory chip,

wherein at least parts of the data paths respectively pass through the substrate and are connected to the data transmission ports in a one-to-one manner,
wherein each of the data paths comprises:
a first through hole, a first terminal of the first through hole being coupled to an output terminal of a corresponding sensing amplifier of the sensing amplifiers;
a connection wire, a first terminal of the connection wire being coupled to a second terminal of the first through hole; and
a second through hole, disposed between a second terminal of the connection wire and a second surface of the substrate, wherein the second surface contacts the logic chip.