Patent ID: 11950432
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 7:
8. A semiconductor package, comprising:
a first die, comprising:
a memory cell;
a first bonding structure disposed over and electrically connected to the memory cell; and
a first capacitor structure disposed aside the first bonding structure, comprising a plurality of first conductive layers and a plurality of first dielectric layers, wherein the first bonding structure is electrically connected to at least one of the first conductive layers, and the at least one of the first conductive layers comprises ferromagnetic material;

a second die bonded to the first die, comprising:
a peripheral circuit; and
a second bonding structure bonded to the first bonding structure, wherein the memory cell is electrically connected to the peripheral circuit through the first bonding structure and the second bonding structure.