Patent ID: 11903034
Assignee: INTEL CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A non-transitory computer-readable storage medium that stores instructions for execution by processing circuitry of gNodeB (gNB), wherein to perform a random access procedure with a user equipment (UE), the processing circuitry is configured to:
decode random access preamble (Msg1) in a physical random access channel (PRACH) from the UE;
encode a random access response (RAR) message (Msg2) in response to the random access preamble (Msg1), the RAR message (Msg2) including an RAR uplink (UL) grant; and
decode an initial transmission of a physical uplink shared channel (PUSCH) scheduled by the RAR UL grant,
wherein for PUSCH repetition Type A that is scheduled by the RAR UL grant, the processing circuitry is decode repetitions of the initial transmission of the PUSCH over a number of slots based on a Msg3 PUSCH repetition number, and
wherein when the PUSCH repetition Type A that is scheduled by the RAR UL grant, the processing circuitry is configured to indicate to the UE the Msg3 PUSCH repetition number in two most significant bits in a modulation and coding scheme (MCS) field of the RAR UL grant, the MCS for the PUSCH determined from the least-significant bits in the MCS field,
wherein for PUSCH repetition Type A that is scheduled by a downlink control information (DCI) format 0_1, the processing circuitry is to encode radio resource control (RRC) signalling with a PUSCH aggregation factor for transmission to the UE to configure the UE to repeat the initial transmission of the PUSCH, and
wherein memory is configured to store the random access preamble.