Patent ID: 11925011
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. The memory structure of claim 13, wherein:
a first spacing is along the second direction between a first one of the first p-type fin channels and a first one of the first n-type fin channels, wherein the first one of the first p-type fin channels is adjacent to the first one of the first n-type fin channels;
a second spacing is along the second direction between the first one of the first p-type fin channels and a second one of the first p-type fin channels, wherein the first one of the first p-type fin channels is adjacent to the second one of the first p-type fin channels;
a third spacing is along the second direction between a first one of the second p-type fin channels and a second one of the second p-type fin channels, wherein the first one of the second p-type fin channels is adjacent to the second one of the second p-type fin channels;
a fourth spacing is along the second direction between a first one of the second n-type fin channels and a second one of the second n-type fin channels, wherein the first one of the second n-type fin channels is adjacent to the second one of the second n-type fin channels; and
wherein the third spacing is greater than the first spacing and the fourth spacing is greater than the first spacing.