Patent ID: 11967575
Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An apparatus, comprising:
a first bonding surface of a microelectronic component, the first bonding surface including a first dielectric material;
a second bonding surface directly bonded with the first bonding surface, the second bonding surface including a second dielectric material;
at least one recessed non-bonded area containing no electrically operational elements, the at least one recessed non-bonded area being disposed in, and bounded by, either the first dielectric material of the first bonding surface or second dielectric material of the second bonding surface, the at least one recessed non-bonded area comprising a first recess surrounding a central portion of the first bonding surface, and the first bonding surface further comprising a peripheral portion of the first bonding surface.