Patent ID: 11901277
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A method of manufacturing a semiconductor package, comprising:
forming a first redistribution structure;
mounting a semiconductor die on a first surface of the first redistribution structure;
laterally encapsulating the semiconductor die by an encapsulant; and
forming a second redistribution structure on a second surface of the first redistribution structure, wherein the second surface is opposite to the first surface, and wherein the first redistribution structure comprises a first conductive via and the second redistribution structure comprises a second conductive via disposed over the first conductive via, a cross-sectional shape of the first conductive via is trapezoid, a cross-sectional shape of the second conductive via is inverted trapezoid, wherein the encapsulant is not on sidewalls of the first redistribution structure, and wherein the first redistribution structure further comprises first conductive wires and second conductive wires, the second redistribution structure further comprises third conductive wires and fourth conductive wires, the first conductive via is located between and in direct contact with the first conductive wires and the second conductive wires, the second conductive via is located between and in direct contact with the third conductive wires and the fourth conductive wires, and the first conductive wires, the first conductive via, the second conductive wires, the third conductive wires, the second conductive via and the fourth conductive wires are sequentially disposed over the semiconductor die, a first contact area between the first conductive via and the first conductive wires is greater than a second contact area between the first conductive via and the second conductive wires, and a third contact area between the second conductive via and the third conductive wires is smaller than a fourth contact area between the second conductive via and the fourth conductive wires.