Patent ID: 11955556
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 16:
17. A method of manufacturing a semiconductor device, the method comprising:
forming a fin structure, the fin structure including sacrificial lines and semiconductor lines that are alternately and repeatedly stacked in a vertical direction, the vertical direction perpendicular to an upper surface of a substrate;
forming dummy gate structures on the substrate, each of the dummy gate structures covering a portion of the fin structure;
removing a portion of the fin structure between the dummy gate structures to form a first opening;
forming a source/drain layer in the first opening;
forming an insulating interlayer on the substrate covering the dummy gate structures and the source/drain layer;
removing the dummy gate structures and the sacrificial lines to form second and third openings, respectively, the third opening exposing a portion of a sidewall of the source/drain layer;
enlarging the third opening in a horizontal direction that is parallel to the upper surface of the substrate to form a fourth opening; and
forming a gate structure in the second and fourth openings,
wherein:
forming the source/drain layer includes:
forming a first epitaxial layer on an inner wall of the first opening by a first selective epitaxial growth (SEG) process, the SEG process using a sidewall of the fin structure along with an upper surface of the substrate exposed by the first opening as seeding layers, the first epitaxial layer including a semiconductor material doped with first impurities; and
forming a second epitaxial layer in a remaining portion of the first opening by a second SEG process, the second epitaxial layer including a semiconductor material doped with second impurities, and
the fourth opening does not expose the second epitaxial layer.