Patent ID: 11900148
Assignee: INTEL CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 21:
22. An apparatus comprising:
memory including a data buffer, the memory to store first sensor data in the data buffer at a first point in time, and to store second sensor data in the data buffer at a second point in time after the first point in time, the second sensor data including additional sensor data not included in the first sensor data; instructions; and
processor circuitry to execute the instructions to:
generate a packet descriptor for sensor data, the packet descriptor to be stored separate from the data buffer, the packet descriptor including packet header information and a pointer, the pointer to indicate a location in the data buffer where the first sensor data is stored, the second sensor data stored at the location in the data buffer identified by the pointer of the packet descriptor;
generate a first network packet, the first network packet including a packet header and the first sensor data from the data buffer, the packet header including the packet header information;
cause transmission of the first network packet to a target computing device;
generate a second network packet, the second network packet including the second sensor data from the data buffer and the packet header from the packet descriptor; and
cause transmission of the second network packet after the transmission of the first network packet.