Patent ID: 11924352
Assignee: EYGS LLP
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 12:
13. An apparatus, comprising:
a processor; and
a memory coupled to the processor, the memory storing instructions, that when executed by the processor, cause the processor:
receive, at a computing node of a distributed ledger-based network (DLN), a request to evaluate an account on the DLN and/or a behavior of a self-executing code segment of the DLN;
fork the DLN to form a forked DLN that includes a ledger onto which are recorded prior transactions executed on the DLN;
generate, at the computing node and in response to the request, a test transaction to evaluate the behavior of the self-executing code segment and/or the account;
submit, via the computing node, the test transaction to the self-executing code segment on the forked DLN for execution, the test transaction configured such that no output of the execution of the test transaction is recorded on the ledger; and
analyze an output of the execution to generate a report evaluating the account and/or the behavior of the self-executing code segment.