Patent ID: 11967959
Assignee: REALTEK SEMICONDUCTOR CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 5:
6. A clock and data recovery (CDR) method having quick locking and bandwidth stabilizing mechanism used in a CDR circuit, the CDR method comprising:
receiving a serial data and a sampling clock by a phase detection circuit to detect a position relation of two clock edges of each of a plurality of clock periods in an adaptive control period of the sampling clock and a data edge of the serial data, and to generate a tracking direction according to the position relation;
receiving the tracking direction of each of the clock periods in series by an adaptive tracking circuit;
directly outputting the tracking direction that a first clock period of the clock periods corresponds to an adaptive tracking direction by the adaptive tracking circuit;
for each of the other clock periods behind the first clock period in turn being a current clock period and one of the clock periods pervious to the current clock period being a previous clock period, replacing a previous tracking direction that the previous clock period corresponds to by a current tracking direction that the current clock period corresponds to the adaptive tracking direction by the adaptive tracking circuit only when the current tracking direction exists and when the current tracking direction is different from the previous tracking direction; and
when the adaptive tracking direction varies in the adaptive control period, generating an actual tracking direction according to the varied adaptive tracking direction; and
adjusting a phase of the sampling clock by a clock control circuit according to the actual tracking direction.