Patent ID: 11901458
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 20:
21. An integrated circuit device comprising:
a nanowire over a substrate, the nanowire comprising a first semiconductor material;
a first dielectric layer between the substrate and the nanowire, the first dielectric layer comprising a first dielectric material having a first dielectric constant, and the first dielectric layer having an uppermost surface;
a second dielectric layer completely surrounding a channel region of the nanowire, the second dielectric layer comprising a second dielectric material having a dielectric constant greater than the first dielectric constant, a portion of the second dielectric layer in contact with the first dielectric layer;
a gate electrode completely surrounding the channel region of the nanowire and in contact with the second dielectric layer;
a source region and a drain region comprising a second semiconductor material, the source region and the drain region on opposing sides of the nanowire, wherein first portions of the source region and the drain region are in direct contact with the substrate, and the first dielectric layer is on the substrate between second portions of the source region and the drain region; and
first and second gate spacers, wherein the first gate spacer is between the second dielectric material and one of the source region or drain region, and the second gate spacer is between the second dielectric material and the other of the source region or drain region.