Patent ID: 11869951
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A method comprising:
depositing a first conductive layer and a hard mask layer stacked over a substrate;
performing a first etch selectively into the first conductive layer and the hard mask layer to form a pair of control gate stacks elongated in parallel in a first dimension and laterally offset in a second dimension orthogonal to the first dimension, wherein the control gate stacks respectively comprise a first pad and a second pad laterally offset in the first dimension;
depositing a second conductive layer covering the control gate stacks;
recessing a top surface of the second conductive layer until recessed relative to a top surface of the control gate stacks to form a pair of erase gates, including a first erase gate, between which the control gate stacks are arranged, wherein the erase gates have individual sidewalls into which the first and second pads respectively protrude, and wherein the first and second pads are completely between the erase gates in the second dimension; and
performing a second etch selectively into the second conductive layer to form a pair of word lines, including a first word line, between and respectively bordering the control gate stacks, wherein the word lines have individual sidewalls into which the first and second pads respectively protrude;
wherein the first word line has a first sidewall and a second sidewall respectively on opposite sides of the first pad and respectively facing and bordering a first pair of sidewalls of the first pad in the first dimension, wherein the first erase gate has a first sidewall and a second sidewall respectively on the opposite sides of the first pad and respectively facing and bordering a second pair of sidewalls of the first pad in the first dimension, and wherein a separation between the first and second sidewalls of the first word line is a same as a separation between the first and second sidewalls of the first erase gate.