Patent ID: 11961804
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 5:
6. A method of fabricating an integrated circuit package, the method comprising:
embedding an interconnect bridge within an organic substrate, the interconnect bridge comprising:
a first termination resistor therein;
a second termination resistor therein;
a decoupling capacitor therein; and
a communication pathway therein, the communication pathway directly coupling the first termination resistor and the second termination resistor;

connecting a first integrated circuit die to the organic substrate and to the interconnect bridge, wherein a first input output buffer circuit in the first integrated circuit die is associated with the first termination resistor and the decoupling capacitor of the interconnect bridge; and
connecting a second integrated circuit die to the organic substrate and to the interconnect bridge, wherein a second input output buffer circuit in the second integrated circuit die is associated with the second termination resistor and the decoupling capacitor of the interconnect bridge, and wherein the second integrated circuit die is electrically coupled to the first integrated circuit die by the interconnect bridge.