Patent ID: 11963468
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 5:
6. An integrated chip, comprising:
a lower electrode disposed on a first interconnect within a lower inter-level dielectric (ILD) layer over a substrate;
a data storage structure over the lower electrode;
a metal diffusion barrier separating the lower electrode from the data storage structure;
an upper electrode on the data storage structure;
a dielectric spacer disposed along an upper surface of the upper electrode and along sidewalls of the upper electrode and the data storage structure;
an insulating layer disposed along sidewalls and an upper surface of the dielectric spacer, the insulating layer vertically extending from below a bottom of the dielectric spacer to over a top of the dielectric spacer;
a second ILD layer laterally surrounding the insulating layer; and
a second interconnect contacting the upper electrode.