Patent ID: 11948890
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A device comprising:
an encapsulant;
an integrated circuit die in the encapsulant;
a first dielectric layer on the integrated circuit die and the encapsulant;
a first conductive via extending through the first dielectric layer, the first conductive via connected to a die connector of the integrated circuit die, a top surface of the first conductive via disposed further from the encapsulant than a top surface of the first dielectric layer;
a first conductive line on the top surface of the first conductive via, a sidewall of the first conductive via, and the top surface of the first dielectric layer;
a second dielectric layer on the first conductive line and the first dielectric layer;
a through via extending through the encapsulant;
a second conductive via extending through the first dielectric layer, the second conductive via connected to the through via, a top surface of the second conductive via disposed further from the encapsulant than the top surface of the first dielectric layer; and
a second conductive line on the top surface of the second conductive via, a sidewall of the second conductive via, and the top surface of the first dielectric layer, the second dielectric layer disposed on the second conductive line.