Patent ID: 11972789
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 3:
4. The circuit according to claim 2, wherein the count value is a number of row errors, and the historical maximum decoding information is decoding information corresponding to a historical maximum number of row errors; wherein the decoding information is a six-bit binary number;
the circuit further comprising an address circuit, wherein the comparison circuit further comprises a second latch sub-circuit;
the address circuit is configured to output address information corresponding to the count value; and
the second latch sub-circuit has an input terminal connected to the address circuit and an enable terminal connected to the output terminal of the comparison sub-circuit, and the second latch sub-circuit is configured to output, in response to a valid enable signal, the address information outputted by the address circuit, and maintain, in response to an invalid enable signal, the address information corresponding to the historical maximum number of row errors; wherein the address information comprises a bank group address, a bank address, and a row address.