Patent ID: 11907154
Assignee: QUALCOMM INCORPORATED
Field: Digital communication (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 29:
30. The non-transitory processor-readable storage medium of claim 28, wherein the code further causes the processing circuit to:
configure a second counter to drive a control input of the clock gating circuit, the second counter being clocked by the signal received from the one-wire bus,
wherein the second counter is held in a reset state when the one-wire bus is idle and until a sequence start condition (SSC) is detected in the signal received from the one-wire bus,
wherein the second counter is configured to halt counting when an expected number of synchronization pulses have been counted in the signal received from the one-wire bus, and
wherein the clock gating circuit is disabled until the second counter halts counting.