Patent ID: 11869568
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A memory system comprising:
a memory device comprising a first memory bank including a first cell mat used as a first normal area and a second cell mat used as a row hammer area and a first redundancy area, and a second memory bank including a third cell mat used as a second normal area and a fourth cell mat used as a second redundancy area, each of the areas being an array of memory cells; and
a memory controller suitable for storing important data in the first memory bank, and storing normal data in the second memory bank, the normal data having lower reliability than the important data,
wherein the memory device comprises:
a target address generation circuit suitable for saving, in the row hammer area, a count of a received address for an active operation on the first memory bank by performing an internal access operation on the row hammer area during the active operation, and setting, a particular count which satisfies a preset condition, an address corresponding to the particular count as a target address;
a refresh control circuit suitable for controlling a smart refresh operation on the target address; and
a column repair circuit suitable for repairing, when a bit line of the first normal area has a defect, the bit line of the first normal area with a bit line of the first redundancy area, and repairing, when a bit line of the second normal area has a defect, the bit line of the second normal area with a bit line of the second redundancy area.