Patent ID: 11934685
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
responsive to allocating a quad-level cell (QLC) block stripe of a non-volatile memory device, updating an entry of a logical-to-physical (L2P) data structure with a physical address of the QLC block stripe;
responsive to allocating a plurality of single-level cell (SLC) block stripes of the non-volatile memory device for programming of data to be programmed to the QLC block stripe, initializing a linked list associated with the entry of the L2P data structure with the physical address of the QLC block stripe;
programming at least one single-level cell (SLC) block stripe of the plurality of SLC block stripes with data to be programmed to the QLC block stripe;
identifying an entry of a quad-to-single (Q2S) mapping table, on a volatile memory device, based on the entry of the L2P data structure with the physical address of the QLC block stripe, wherein each entry of the Q2S mapping table comprises a pointer to the linked list on the volatile memory device and a bit flag;
setting the bit flag of the entry of the Q2S mapping table indicating that the QLC block stripe to be programmed is not programmed;
updating the pointer of the entry of the Q2S mapping table to point to the linked list, wherein the linked list includes a first entry comprising an identification of the QLC block stripe to be programmed and an entry for each physical address of the plurality of SLC block stripes programmed with the data to be programmed to the QLC block stripe; and
copying the data of the plurality of programmed SLC block stripes to the QLC block stripe to be programmed.