Patent ID: 11893271
Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 4:
5. The computing-in-memory circuit according to claim 3, wherein the bit line module comprises a first gating circuit, a second gating circuit, a first voltage supply circuit, a second voltage supply circuit, and a readout circuit;
the first gating circuit is configured to, in the storage mode, connect a first bit line that a selected memory cell connects with an output terminal of the first voltage supply circuit, and in the computation mode, connect the first bit line that the selected memory cell connects with a first input terminal of the readout circuit;
the second gating circuit is configured to, in the storage mode, connect a second bit line that the selected memory cell connects with an output terminal of the second voltage supply circuit, and in the computation mode, connect the second bit line that the selected memory cell connects with a second input terminal of the readout circuit;
the first voltage supply circuit is configured to supply a set voltage to the first bit line that the selected memory cell connects in the storage mode, and the second voltage supply circuit is configured to supply the set voltage to the second bit line that the selected memory cell connects in the storage mode; and
the readout circuit is configured to read out a current of each memory cell located in a same column in the computation mode, and accumulate the current of each memory cell located in the same column together.