Patent ID: 11960395
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A data storage device, comprising:
one or more memory devices; and
a controller coupled to the one or more memory devices, wherein the controller is configured to:
encode a first delta logical to physical (L2P) entry;
determine that the first delta L2P entry is an absolute entry, wherein the first delta L2P entry is an absolute delta L2P entry, wherein the absolute delta L2P entry comprises a type field, a L2P table part index field, an offset in L2P table part field, and a PBA field;
enter the first delta L2P entry into a delta buffer, wherein the first delta L2P entry has a delta entry physical block address (PBA) equal to a PBA, wherein the delta buffer is a buffer where L2P updates are queued prior to updating an L2P table in the one or more memory devices;
encode a second delta L2P entry;
determine that the second delta L2P entry is a relative entry; and
enter the second delta L2P entry into the delta buffer wherein the second delta L2P entry has a delta entry PBA offset equal to an offset from the PBA.