Patent ID: 11900996
Assignee: GLOBALFOUNDRIES U.S. INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. The memory structure of claim 11,
wherein the voltage boost circuit is configured so that, when a second wordline voltage on the second wordline switches to a positive supply voltage level and the mode select signal indicates the read mode, the fourth voltage boost line, the second voltage boost line, and the third voltage boost line are charged creating coupling capacitances between the second wordline and both the fourth voltage boost line and the third voltage boost line to increase the second wordline voltage on the second wordline above the positive supply voltage level and creating coupling capacitances between the cell supply line and both the second voltage boost line and the third voltage boost line to increase a cell supply voltage on the cell supply line above the positive supply voltage level, and
wherein the voltage boost circuit is configured so that, when the second wordline voltage on the second wordline switches to the positive supply voltage level and the mode select signal indicates the write mode, the fourth voltage boost line is charged creating a coupling capacitance between the second wordline and the fourth voltage boost line to increase the second wordline voltage on the first wordline above the positive supply voltage level without increasing the cell supply voltage.