Patent ID: 11868288
Assignee: SUZHOU CENTEC COMMUNICATIONS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G  H

Claim 0:
1. A verification system for an Ethernet interface chip, wherein the verification system comprises a Reconciliation Sublayer (RS), a Physical Coding Sublayer (PCS), a Physical Medium Attachment (PMA) layer, and a flow control unit connecting the RS and the PMA layer, wherein
the PMA layer is provided with a PMA clock and a buffer, wherein the buffer is configured to store data transferred from the PCS, and the PMA clock is configured to control the PMA layer to send the data in the buffer to an Ethernet interface chip to be tested;
the flow control unit is configured to control sending of data in the RS based on determination concerning whether an amount of the data in the buffer is sufficient;
the RS is configured to send data to the PCS under control of the flow control unit; and
the PCS is configured to send the data sent by the RS to the PMA layer.