Patent ID: 11907036
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 12:
13. A computing system comprising:
a plurality of sub circuits each configured to process an instruction according to an operating condition;
active counters respectively corresponding to the plurality of sub circuits and configured to count a sub active time, which is an active time of each corresponding sub circuit;
a total counter configured to count a total active time during which at least one sub block of the plurality of sub circuits is active;
a clock management circuit configured to determine a clock signal applied to the plurality of sub circuits;
a power management circuit configured to determine a power voltage applied to the plurality of sub circuits; and
a Dynamic Voltage and Frequency Scaling (DVFS) circuit configured to derive a workload of the plurality of sub circuits,
derive energy consumed by each sub circuit of the plurality of sub circuits during a sample period based on a product of an individual active time of each sub circuit and individual power consumption of each sub circuit,
derive a total power consumption consumed by the plurality of sub circuits during the sample period based on a ratio of a sum of the energy consumed by each sub circuit of the plurality of sub circuits to the total active time,
derive a power usage rate based on the total power consumption of the plurality of sub circuits, and
control the clock management circuit or the power management circuit to adjust a frequency of the clock signal or a magnitude of the power voltage based on the ratio of the workload to the power usage rate.