Patent ID: 11928441
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 17:
18. The semiconductor memory device of claim 17, wherein:
the first state signal is an even-numbered state signal among the plurality of state signals,
the second state signal is an odd-numbered state signal among the plurality of state signals,
the logical sum calculator includes a first logical sum calculator which performs a logical sum calculation on the first state signal, and a second logical sum calculator which performs a logical sum calculation on the second state signal,
the accumulation circuit includes a first accumulation circuit which receives output of the first logical sum calculator as a first clock signal and outputs a first toggle signal to a first probing pad in response to the first clock signal, and a second accumulation circuit which receives output of the second logical sum calculator as a second clock signal and outputs a second toggle signal to a second probing pad in response to the second clock signal.