Patent ID: 11921656
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 8:
9. An apparatus, comprising:
a first processing unit configured to assign a first portion of a computational task to a second processing unit, and a second portion of the computational task to a third processing unit, wherein the second processing unit is configured to execute instructions and the third processing unit is configured to execute instructions to control processing-in-memory functionality;
a first memory configured to provide processing-in-memory functionality controllable by the third processing unit; and
a second memory comprising a first buffer portion for the second processing unit, and a second buffer portion for the third processing unit;
wherein the third processing unit is configured to copy data from the second memory to the first memory to execute the second portion of the computational task using the data; and
wherein the third processing unit is further configured to determine a trigger and copy data for the second portion of the computational task, based on the trigger, from the second memory to the first memory, wherein the trigger is based on the first portion of the computational task.