Patent ID: 11972128
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. A memory system comprising:
a memory device including a first memory block, a second memory block having a larger storage unit per a memory cell than the first memory block, and a third memory block having a same storage unit as the first memory block; and
a memory controller configured to:
when data is received from a host, control the memory device to store the data in the first memory block,
when an attribute of the data is cold data after a preset event occurs, control the memory device to store the data stored in the first memory block in the second memory block,
control the memory device to store valid data stored in the first memory block in the third memory block, and
control the memory device to erase the first memory block.