Patent ID: 11907630
Assignee: SYNOPSYS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 4:
5. The method of claim 1, further comprising:
calculating a toggle rate of signals in the subset of design signals during said executing simulation, using the output waveforms for the subset of design signals, for a subset of the power assertions specified in the power assertion specification for the signals in the subset of design signals; and
comparing the calculated toggle rate of the signals in the subset of design signals against a predicted toggle rate of the signals in the subset of design signals for the subset of the power assertions specified during said executing simulation;
determining that the IC design is associated with a third power assertion failure based on results of the comparing the calculated toggle rate of the signals in the subset of design signals against a predicted toggle rate of the signals in the subset of design signals.