Patent ID: 11862566
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 18:
19. A semiconductor device, comprising:
a cell array region and an extension region arranged along a first direction, wherein contact regions and through regions are alternately arranged along the first direction in the extension region;
a mold structure including a ground selection line on a substrate, and a plurality of wordlines stacked on the ground selection line;
a channel structure that intersects the ground selection line and the plurality of wordlines through the mold structure in the cell array region;
a gate contact in one of the contact regions, wherein the gate contact is on the mold structure and is connected to a wordline of the plurality of wordlines;
an extension gate cutting region that extends in the first direction to cut the ground selection line and the plurality of wordlines in the mold structure in the contact regions; and
a plurality of insulating patterns, stacked on same levels as the plurality of wordlines, in the mold structure in the through regions, the ground selection line partially overlapping with the plurality of insulating patterns in a direction that is perpendicular to a top surface of the substrate.