Patent ID: 11908505
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 3:
4. The data processing device of claim 3, wherein the plurality of memory cells are logically arranged in a plurality of rows and columns, wherein:
the gates of the ML switching transistors in each row of the memory cells are connected to each other;
the drains of the FeFETs in the first data storage units in each column of the memory cells are connected to each other;
the drains of the FeFETs in the second data storage units in each column of the memory cells are connected to each other;
the sources of the FeFETs in the first data storage units in each column of the memory cells are connected to each other; and
the sources of the FeFETs in the second data storage units in each column of the memory cells are connected to each other.