Patent ID: 11880591
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 12:
13. A method, comprising:
reducing, using an amplifier, inter-symbol interference between a first clock phase of a signal a second clock phase of the signal, and a third clock phase of the signal;
determining, by a first circuit, a voltage level of the signal that occurs at the first clock phase based at least in part on reducing the inter-symbol interference;
modifying, by a first feedback circuit, a first feedback signal sent to a second circuit based at least in part on the voltage level of the signal that occurs at the first clock phase;
determining, by the second circuit, a voltage level of the signal that occurs at the second clock phase based at least in part on the first feedback signal;
modifying, by a second feedback circuit, a second feedback signal sent to a third circuit based at least in part on the voltage level at the signal that occurs at the second clock phase; and
determining, by the third circuit, a voltage level of the signal that occurs at a third clock phase based at least in part on the second feedback signal, wherein the first circuit, the second circuit, and the third circuit are operated in parallel.