Patent ID: 11934527
Assignee: GENERAL ELECTRIC COMPANY
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 3:
4. The method of claim 1, further comprising:
executing, by the one or more processors, the first set of machine-readable instructions within a predetermined period of time;
loading, by the one or more processors, a second set of machine-readable instructions and second configuration information associated with the second set of machine-readable instructions onto the non-transitory computer-readable medium in response to the predetermined period of time elapsing, wherein the second set of machine-readable instructions and the second configuration information are associated with one or more non-priority partitions;
authenticating, by the one or more processors, the second set of machine-readable instructions; and
executing, by the one or more processors, the second set of machine-readable instructions in response to authentication of the second set of machine-readable instructions.