Patent ID: 11961568
Assignee: WINBOND ELECTRONICS CORP.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A semiconductor device, comprising:
a NAND memory cell array;
a reading component reading data from a selected page of the memory cell array; and
an output component outputting the data read by the reading component to outside,
wherein the reading component comprises a bit line selection circuit selecting an even-numbered bit line or an odd-numbered bit line, and a page buffer/reading circuit connected to the bit line selection circuit,
the reading component precharges a selected bit line with a supply voltage of a first voltage supply source connected to the bit line selection circuit, and initializes a latch of the page buffer/reading circuit with a supply voltage of a second voltage supply source connected to the page buffer/reading circuit in parallel with precharging of the selected bit line.