Patent ID: 11948995
Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A method for producing a capacitor, the method comprising:
providing a masking layer on a non-capacitance generation region of a silicon substrate having a principal surface including a capacitance generation region and the non-capacitance generation region;
forming, by an anode oxidation process, a macroporous part in the capacitance generation region in a thickness direction defined with respect to the silicon substrate by forming macro pores in the capacitance generation region which is not covered with the masking layer;
forming a nanoporous part in inner surfaces of the macro pores of the macroporous part, the nanoporous part having nano pores smaller than the macro pores;
forming a dielectric layer on the inner surfaces of the macro pores and inner surfaces of the nano pores;
forming a conductor layer including a filling part filled in at least part of the macro pores and the nano pores and a surface layer part at least covering part of a surface of the capacitance generation region; and
after forming fine nanoporous parts in the macro pores, removing at least part of the fine nanoporous parts, the fine nanoporous parts having fine nano pores smaller than the nano pores.