Patent ID: 11860762
Assignee: NEC CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. The semiconductor device according to claim 1, wherein
the semiconductor device includes a secure area and a non-secure area,
the secure area includes the at least one memory, the first storage apparatus, the second storage apparatus, a prediction circuitry, an inspection circuitry, and
the non-secure area includes the at least one processor,
the prediction circuitry configured to predict, in accordance with the execution of the inspection instruction by the at least one processor, the prefetch target in accordance with a fourth code block in which the inspection instruction is set, prefetch the prefetch target, determine an access destination to be one of the first storage apparatus and the second storage apparatus based on the prediction auxiliary information in the fourth code block, and acquire third execution order inspection information that corresponds to the current execution order of the fourth code block from the determined access destination, and
the inspection circuitry configured to inspect whether it is possible to execute a code block executed after the code block in which the inspection instruction is set in accordance with the execution of the inspection instruction by the at least one processor.