Patent ID: 11925020
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 9:
10. A vertical semiconductor device, comprising:
a first stacked structure on a substrate, the first stacked structure including first gate patterns being spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, the first gate patterns extending in a first direction parallel to the upper surface of the substrate;
a second stacked structure on the first stacked structure, the second stacked structure including at least three upper lines at the same level, wherein the upper lines are separated by a first trench between the upper lines; and
channel structures passing through the first gate patterns and the upper lines, each of the channel structures extending to the upper surface of the substrate, and each of the channel structures including a charge storage structure and a channel,
wherein, in a plan view of upper lines cut along a horizontal direction, one sidewall of each of the first trenches overlaps sidewalls of the channel structures,
wherein second trenches extending in the first direction and exposing the upper surface of the substrate are disposed at both sides of a structure including the first and second stacked structures, respectively, and
wherein a plurality of the first trenches are disposed between the second trenches.