Patent ID: 11899567
Assignee: CIRRUS LOGIC INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A system comprising:
a memory programmed with multiple firmware images, wherein each firmware image of the multiple firmware images has an associated entry point that is distinct from the entry point of the other firmware images;
a processor that fetches instructions of the multiple firmware images from the memory and executes the fetched instructions;
a hardware register writable with an address, wherein the hardware register is initially seeded with an address that is an initial entry point of an initial firmware image among the multiple firmware images; and
a controller that is external to the processor and that is configured to:
hold the processor in an initial reset, read the initial entry point from the hardware register, write the initial entry point to the processor, and release the processor from the initial reset to cause the processor to fetch its first instruction out of the initial reset from the memory at the initial entry point read from the hardware register;

wherein, after the external controller reads the initial entry point, the hardware register is writable with a second entry point of a second firmware image among the multiple firmware images other than the initial firmware image;
wherein to facilitate a transition from running the initial firmware image to the second firmware image, the external controller is further configured to:
hold the processor in a second reset subsequent to the initial reset, read the second entry point from the hardware register, write the second entry point to the processor, and release the processor from the second reset to cause the processor to fetch its first instruction out of the second reset from the memory at the second entry point read from the hardware register.