Patent ID: 11894850
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 1:
2. The delay circuit according to claim 1, wherein the inverting unit comprises a first transistor, a second transistor, and a first capacitor, and wherein a channel type of the first transistor and a channel type of he second transistor are different;
wherein a gate of the first transistor is connected to a gate of the second transistor and receives the input signal, wherein a drain of the first transistor is connected to a drain of the second transistor and serves as an output terminal of the delay unit, wherein a source of the first transistor and/or a source of the second transistor receive the voltage; wherein one terminal of the first capacitor is connected to the output terminal of the delay unit, wherein the first capacitor is connected to the output terminal of the delay unit, and wherein another terminal of the first capacitor is grounded.