Patent ID: 11907633
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. A layout method, comprising:
selecting a first layout device in a layout of an integrated circuit;
selecting a second layout device abutting the first layout device at a boundary between the first layout device and the second layout device,
disposing a first conductive path and a second conductive path across a boundary between a first layout device and a second layout device abutting the first layout device, and
disposing a first cut layer on the first conductive path on the boundary;
disposing a second cut layer on the second conductive path nearby the boundary;
moving the first cut layer to align and be in contact with the second cut layer; and
disposing a third cut layer and a fourth cut layer on first edges of the first conductive path and the second conductive path respectively.