Patent ID: 11947254
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Optics (Instruments)
Classification: CPC G | IPC G

Claim 11:
12. The system of claim 8, wherein, for calibrating the OPC model, the processor is further configured to:
form a test mask with test structures based on a test layout different from the device layout;
form a patterned layer on a substrate by using the test mask in a lithography process;
control the testing tool to measure a contour or a critical dimension (CD) of the patterned layer;
generate a second grid pattern density map of the test layout;
receive first values of the first set of parameters indicative of the long-range effect, and values of the second set of parameters indicative of the geometric feature of the structure or the manufacturing process;
control the testing tool to measure a contour or CD of the patterned layer of the test layout; and
iterating: adjusting the values of the second set of parameters indicative of the geometric feature of the structure or the manufacturing process to second values, control the testing tool to measure a mask pattern shape using a mask model including the first values and the second values respectively indicative of the long-range effect and the geometric feature, and controlling the testing tool to measure a new calculated contour or a new calculated CD of the test layout at least based on the calculated mask pattern shape, until a difference between the new calculated contour or the new calculated CD of the test layout and the measured contour or the measured CD of the patterned layer is within a predetermined range,
wherein the calibrated OPC model includes the received first values of the first set of parameters indicative of the long-range effect and the last adjusted second values of the second set of parameters indicative of the geometric feature of the structure or the manufacturing process among the adjusted second values during the iteration.