Patent ID: 11916127
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A method for forming a memory device, comprising:
depositing a lower insulating structure over a lower interconnect;
patterning the lower insulating structure to form an opening over the lower interconnect;
forming a multi-layer bottom electrode over the lower insulating structure and lining the opening, wherein the multi-layer bottom electrode comprises a middle region contacting the lower interconnect and a peripheral region disposed on a top surface of the lower insulating structure;
depositing a ferroelectric layer on the multi-layer bottom electrode; and
forming a multi-layer top electrode over the ferroelectric layer, wherein the multi-layer top electrode comprises a first top electrode layer and a second top electrode layer disposed between the first top electrode layer and the ferroelectric layer, wherein the second top electrode layer has a greater Gibbs free energy to form oxide than the first top electrode layer, wherein the second top electrode layer directly contacts the first top electrode layer and the ferroelectric layer.