Patent ID: 11868469
Assignee: VENTANA MICRO SYSTEMS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. A method for mitigating side channel attacks, comprising:
in a microprocessor that comprises a front end that processes instructions in program order and a back end that is configured to perform speculative execution of instructions out of program order in a superscalar fashion, wherein the back end comprises a plurality of execution units comprising one or more producing execution units configured to produce architectural register results during execution of instructions and one or more consuming execution units configured to consume the produced architectural register results during execution of instructions, wherein the producing and consuming execution units are same execution unit or different execution units:
making a detection that, during execution by a producing execution unit, an architectural register result producing instruction causes a need for an architectural exception and consequent flush of all instructions younger in program order than the producing instruction; and
in response to the detection, preventing all load/store instructions within the back end that are dependent upon the producing instruction from updating a data cache of the microprocessor based on the architectural register result produced by the producing instruction by preventing issuance of the dependent load/store instructions to a consuming execution unit for execution or by canceling execution of the dependent load/store instructions before the dependent load/store instructions update the data cache.