Patent ID: 11954487
Assignee: NVIDIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. An accelerator circuit comprising:
a first register to store a first number, wherein the first number represents an input into a modular computational operation;
a second register to store a second number;
a third register to store a third number, wherein the third number is triple the first number;
a decode unit to:
receive an instruction to perform the modular computational operation, the instruction identifying a first operand stored in the first register, a second operand stored in the second register, and a third operand stored in the third register; and
select a conditional operation (CO) from a plurality of COs, wherein each of the plurality of COs updates or maintains the second operand, wherein a first CO of the plurality of COs is selected contingent upon:
a subset of bits of the second operand and the subset of bits of the first operand having a first value, or
the subset of bits of the second operand having a second value and the subset of bits of a third operand having the first value; and

an execution unit to:
perform the selected CO to update the second operand; and
generate an output of the modular computational operation using the updated second operand.