Patent ID: 11928045
Assignee: CADENCE DESIGN SYSTEMS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A system comprising:
a memory storing machine-readable instructions comprising a plurality of component models including a processor model representative of a processor and a hardware model representative of a hardware element, and embedded software for execution using the processor model during a simulation of the plurality of component models; and
a processor configured to access the memory and execute the machine-readable instructions, the machine-readable instructions causing the processor to:
simulate the processor model representative of the processor and the hardware model representative of the hardware element, wherein each of the processor model and the hardware model are executed by the processor with a corresponding simulator thread;
simulate the embedded software using the processor model;
set a software breakpoint at a function that switches between processes within the embedded software; and
enable debugging of both non-virtual and virtual addresses at the software breakpoint without leaving the software breakpoint, wherein the non-virtual addresses are associated with a register transfer level model written in a first hardware description language and the virtual addresses are associated with a transaction level model written in a system level modeling language.