Patent ID: 11928329
Assignee: NXP B.V.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. The IC of claim 7, wherein the controller comprises a second set of logic circuits that is coupled to the second half of the register and the address decoder, and configured to:
receive the functional data, the first control bit, the third control bit, and the set of register bits, wherein the third control bit has the first logic state and the first control bit has the second logic state to indicate that the selected set of storage elements corresponds to the second half of the register; and
write, based on the first and third control bits, the one or more write bits associated with the one or more mask bits having the first logic state, respectively, and the one or more register bits associated with the one or more mask bits having the second logic state, respectively, to the second half of the register.