Patent ID: 11876063
Assignee: NANYA TECHNOLOGY CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A method for preparing a semiconductor package structure, comprising:
forming a first semiconductor wafer including a first bonding pad;
forming a second semiconductor wafer including a second bonding pad and a third bonding pad;
bonding the second semiconductor wafer onto the first semiconductor wafer using a hybrid bonding process such that the second bonding pad and the third bonding pad are bonded to the first bonding pad;
forming a first opening and a second opening in the second semiconductor wafer by performing a first etching process, wherein the first bonding pad is exposed by the first opening, and wherein a first conductive line in the second semiconductor wafer away from an interface between the first semiconductor wafer and the second semiconductor wafer is exposed by the second opening; and
forming a first via in the first opening and a second via in the second opening.