Patent ID: 11869951
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A method comprising:
forming a floating gate layer overlying a substrate;
depositing a control gate layer overlying the floating gate layer;
patterning the control and floating gate layers to form a control gate stack elongated along a first axis and comprising a first pad and a second pad that are both on the first axis;
depositing a gate layer covering the control gate stack; and
patterning the gate layer to form an erase gate and a word line respectively on opposite sides of and elongated in parallel with the control gate stack, wherein the erase gate and the word line each extends along multiple sidewalls of the first pad and each extends along multiple sidewalls of the second pad, wherein the multiple sidewalls of the first pad along which the erase gate extends comprise a first sidewall facing away from the second pad and a second sidewall facing the second pad, wherein the multiple sidewalls of the second pad along which the word line extends comprise a third sidewall facing away from the first pad and a fourth sidewall facing the first pad, wherein the first and third sidewalls extend respectively along a second axis and a third axis, wherein the erase gate is continuous from the second axis to the third axis, wherein the first and second sidewalls share a first common length in a direction orthogonal to the first axis, and wherein the third and fourth sidewalls share a second common length in the direction.