Patent ID: 11900523
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus comprising:
a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes;
traversal hardware logic to traverse one or more rays through the hierarchical acceleration data structure;
intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; and
a node refit unit comprising circuitry and/or logic to perform refit operations on nodes of the hierarchical acceleration data structure to adjust spatial dimensions of one or more of the nodes,
wherein the node refit unit is to receive refit data associated with refitting one or more child nodes of a current node and to skip refitting the current node responsive to that the refit data indicates that space occupancy of the one or more child nodes has shrunk but the one or more child nodes are still bounded by the current node.