Patent ID: 11862724
Assignee: APOGEE SEMICONDUCTOR, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of fabricating a radiation-hardened NMOS device, comprising the steps of:
providing a silicon substrate having a surface that is lightly doped p-type;
forming a field oxide in the surface of the substrate, patterned to define an active region having a boundary within which the field oxide is absent, the boundary having a first edge and a second edge opposite the first edge;
growing a gate oxide in the active region;
depositing a polysilicon gate layer;
redoping the polysilicon gate layer N+ using a redope pattern that extends over at least one region from which silicide formation will be excluded using a silicide block pattern;
patterning and etching the polysilicon gate layer to form a gate crossing the active region in a width direction from the first edge to the second edge, the gate having two sides and having a gate length between the two sides in a length direction orthogonal to the width direction;
forming an n-type lightly-doped drain structure along at least one side of the gate using an LDD pattern that excludes n-type doping from a gap region, the gap region adjacent the at least one side of the gate and adjacent at least one of the first and second edges and having a gap width g in the width direction;
patterning and doping n-type source/drain diffusion regions using an NSD pattern that excludes the n-type dopant from the gap region;
forming a metal silicide on the diffusion regions and the polysilicon gate layer using a silicide block pattern that is shaped in a way that excludes metal silicide from formation in the gap region and on a portion of the gate that was redoped; and
completing fabrication of the radiation-hardened NMOS device.