Patent ID: 11935609
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 13:
14. The method of claim 10, further comprising:
generating a plurality of reduced XOR parity buffers, each reduced XOR parity buffer of the plurality of reduced XOR parity buffers is based on the first full XOR parity buffer, the first reduced XOR parity buffer, and third flash data associated with a third one or more XOR parity bin groups and across a third one or more of the plurality of wordlines;
generating a second full XOR parity buffer based on the first full XOR parity buffer, the first reduced XOR parity buffer, the plurality of reduced XOR parity buffers, and fourth flash data associated with a fourth one or more XOR parity bin groups and across a fourth one or more of the plurality of wordlines;
generating a second plurality of reduced XOR parity buffers, each reduced XOR parity buffer of the second plurality of reduced XOR parity buffers is based on the second full XOR parity buffer and fifth flash data associated with a fifth one or more XOR parity bin groups and across a fifth one or more of the plurality of wordlines; and
generating a third full XOR parity buffer based on the second full XOR parity buffer, the second plurality of reduced XOR parity buffers, and sixth flash data associated with a sixth one or more XOR parity bin groups and across a sixth one or more of the plurality of wordlines.