Patent ID: 11862701
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor device, comprising:
a stack of first channel layers;
first and second source/drain (S/D) epitaxial features adjacent to opposite sides of at least a portion of the first channel layers, respectively, wherein the first and second S/D epitaxial features have a first conductivity type;
a stack of second channel layers stacked over the first channel layers;
third and fourth source/drain (S/D) epitaxial features adjacent to opposite sides of at least a portion of the second channel layers, respectively, wherein the third and fourth S/D epitaxial features have a second conductivity type; and
a dielectric isolation layer disposed vertically between the first and second S/D epitaxial features and the third and fourth S/D epitaxial layers,
wherein a total active channel layer number of the first channel layers is different from a total active channel layer number of the second channel layers, and wherein the dielectric isolation layer is in physical contact with at least one of the first and second channel layers and separates the at least one of the first and second channel layers from physically contacting any of the first, second, third, and fourth S/D epitaxial features.