Patent ID: 11862645
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 8:
9. A display device comprising:
a substrate;
a first connection wire which extends according to a first direction on the substrate;
a second connection wire disposed on the substrate and disposed on a layer different from the first connection wire, and disposed alternately with the first connection wire on a plane;
an insulating layer between the first connection wire and the second connection wire;
a plurality of pads disposed according to the first direction and the second direction,
a semiconductor layer disposed on the substrate;
a first gate electrode disposed on the semiconductor layer;
a first gate insulating layer between the semiconductor layer and the first gate electrode;
a second gate electrode disposed on the first gate electrode; and
a second gate insulating layer between the first gate electrode and the second gate electrode,
wherein
a first plurality of pads of the plurality of pads adjacent according to the first direction are disposed in different layers, and
a second plurality of pads of the plurality of pads adjacent according to the second direction are disposed in a same layer
wherein the plurality of pads comprising:
a first pad;
a second pad disposed adjacent to the first pad along the first direction;
a third pad disposed adjacent to the first pad along the second direction, such that there is no pad between the first pad and the third pad; and
a fourth pad disposed adjacent to the second pad along the second direction, such that there is no pad between the second pad and the fourth pad,
wherein the first pad and the second pad are disposed in different layers,
the third pad and the fourth pad are disposed in different layers,
the first pad and the third pad are disposed in a first layer, and
the second pad and the fourth pad are disposed in a second layer, and
wherein the first gate electrode is disposed in the first layer, and the second gate electrode is disposed in the second layer.