Patent ID: 11862623
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 4:
5. The method of claim 1, further comprising:
arranging a second gate structure extending continuously above the first active region and the second active region;
arranging a third gate via and a fourth gate via that are disposed on the second gate structure; and
when a guideline is followed, arranging the first local interconnect adjacent to the first gate structure or the second gate structure, wherein the guideline indicates that the first gate via and the second gate via are coupled with the first gate structure, the third gate via and the fourth gate via are coupled with the second gate structure, at least one of the first to fourth gate via is arranged above the first active region or the second active region, and a first pitch between the first gate via and the second gate via is substantially equal to a second pitch between the third gate via and the fourth gate via.