Patent ID: 11880308
Assignee: APPLE INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 10:
11. A method comprising:
storing, in a tag array circuit, tags corresponding to cache lines arranged in a plurality of ways of a cache memory circuit;
predicting, using a prediction circuit, a particular one of a plurality of ways in which a particular cache line is stored in response to a request for access to the tag array circuit;
verifying, using a comparison circuit, whether the prediction is correct, wherein the verifying comprises the comparison circuit performing a comparison to determine whether a tag associated with the particular cache line matches a tag associated with the particular one of the plurality of ways;
storing, in a confirmation bit memory by the prediction circuit and in response to determining that the prediction was correct, a confirmation bit indicating that the predicting was correct; and
indicating a match, for a subsequent request for access to the particular cache line, without reading the tag array circuit and without performing the comparison.