Patent ID: 11972340
Assignee: KWANGWOON UNIV INDUSTRY-ACADEMIC COLLABORATION FDN
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 15:
16. The weight memory system of claim 13, further comprising:
a second memory cell connected to the first electrode via a second common output terminal thereof;
a third electrode connected to a second input terminal of the second memory cell, and arranged in the second direction; and
a second driving circuit configured to drive and control a voltage of the third electrode;
wherein the second memory cell is disposed to correspond to a location at which the first electrode and the third electrode intersect each other, and is specified by intersection of the first electrode and the third electrode;
wherein a second capacitance of the second memory cell is quantified based on second data given to the second memory cell to be stored in the second memory cell;
wherein when a second input signal is applied to the second input terminal via the third electrode by the second driving circuit, a second output signal component based on the second input signal and the second capacitance is output to the first electrode via the common output terminal; and
wherein a sum output signal in which the first output signal component and the second output signal component are summed is output to the first electrode, and the first interface circuit detects the sum output signal and generates the output transfer signal.