Patent ID: 11901028
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 8:
9. The data transmission circuit according to claim 8, wherein the write enable circuit comprises:
a first inverter, an input terminal of the first inverter being electrically connected to the initial write enable signal, and an output terminal of the first inverter being configured to output a first write enable inverted signal;
a first NOR gate, an input terminal of the first NOR gate being electrically connected to the data polarity identification signal and the output terminal of the first inverter, and an output terminal of the first NOR gate being configured to output a write enable signal;
a second inverter, an input terminal of the second inverter being electrically connected to the data polarity identification signal, and an output terminal of the second inverter being configured to output a data polarity identification inverted signal; and
a second NOR gate, an input terminal of the second NOR gate being electrically connected to the output terminal of the second inverter and the output terminal of the first inverter, and an output terminal of the second NOR gate being configured to output the write enable inverted signal.