Patent ID: 11862723
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. The integrated circuit memory of claim 12, wherein the vertical storage transistor comprises:
an annular gate dielectric layer located on a sidewall of the through hole; and
the active pillar located in the through hole, with a first doped region being formed in a lower end portion of the active pillar and connected to the bit line, a second doped region being formed in an upper end portion of the active pillar and being configured to connect a storage element, a third doped region being formed between the lower end portion and the upper end portion of the active pillar, and the first doped region, the second doped region and the third doped region being respectively constructed to a drain region, a source region and a channel region of the vertical storage transistor.