Patent ID: 11915775
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. A system comprising:
a memory comprising:
a repair circuit configured to remap a plurality of repaired addresses to a respective one of a plurality of redundant word lines;
a disable control circuit configured to prevent read operations to a word line associated with a selected address when the memory is in a bad row mode to disable the word line and test a repair logic configured to detect defective rows of the memory, wherein the disable control circuit is configured to cause failure of an access operation on the word line associated with the selected address to cause the word line to temporarily appear to be a defective row by changing a value of at least one data bit in the selected word line; and
a controller comprising:
a repair test circuit configured to enter the memory into the bad row mode, and
a bad row identification circuit configured to test the memory to identify the word line as the defective row based on the failure of the access operation and perform a post package repair (PPR) operation on the selected address,

wherein after the PPR operation the selected address is one of the plurality of repaired addresses,
wherein the word line associated with the selected address is disabled when the memory is in the bad row mode, and
wherein the word line associated with the selected address is not disabled when the memory is exited from the bad row mode.