Patent ID: 11973111
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A semiconductor device, comprising:
a substrate;
an active pattern extending in a first horizontal direction on the substrate;
a plurality of nanosheets stacked to be spaced apart from each other in a vertical direction on the active pattern;
a gate electrode extending in a second horizontal direction different from the first horizontal direction on the active pattern and surrounding the plurality of nanosheets;
a source/drain region on at least one side of the gate electrode;
a source/drain contact extending into the source/drain region and including a filling layer and a barrier layer along a sidewall of the filling layer;
a silicide layer between the source/drain region and the filling layer, including a first sidewall in contact with the filling layer and a second sidewall in contact with the source/drain region, and having an uppermost surface in contact with the barrier layer;
an interlayer insulating layer on a sidewall of the source/drain contact; and
a liner layer between the source/drain contact and the gate electrode and between the source/drain contact and the interlayer insulating layer,
wherein the barrier layer includes a first sidewall in contact with the filling layer and a second sidewall opposite to the first sidewall,
wherein the first sidewall of the barrier layer extends from the first sidewall of the silicide layer, and
wherein the filling layer is formed as a single film.