Patent ID: 11967391
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A method for testing a storage device including a plurality of flash translation layer (FTL) cores, each FTL core associated with multiple memory blocks, the method comprising:
generating, by a test device, test preconditions for the plurality of FTL cores;
providing, by the test device, the test preconditions to the plurality of FTL cores, the test preconditions being different from each other; and
controlling the plurality of FTL cores to perform one or more test operations based on the test preconditions,
wherein the test preconditions include differing conditions,
wherein each of the plurality of FTL cores performs the one or more test operations based on a corresponding test precondition of the test preconditions,
wherein the test preconditions include erase and read operation parameter values for each of the multiple memory blocks, and
wherein each FTL core selectively performs the one or more test operations on the multiple memory blocks based on the erase and read operation parameter values.