Patent ID: 11967356
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 9:
10. An apparatus comprising:
a first plurality of fuse latch and comparator circuits each associated with a particular row section of a first plurality of row sections and configured to store a respective defective row address, wherein a first fuse latch and comparator circuit of the first plurality of fuse latch and comparator circuits is configured to, in response to a determination that a received prime row address matches the respective defective row address, provide a first match signal;
a second plurality of fuse latch and comparator circuits each associated with a particular row section of a second plurality of row sections and configured to store a respective defective row address, wherein a second fuse latch and comparator circuit of the second plurality of fuse latch and comparator circuits is configured to, in response to a determination that the received prime row address matches the respective defective row address, provide a second match signal;
a first predecoder coupled to the first plurality of fuse latch and comparator circuits and configured to receive the first match signal and to receive the prime row address, wherein, in response to the first match signal, cause a first threshold voltage compensation to be initiated on a first redundant row associated with the first fuse latch and comparator circuit, wherein, in response to a determination that the decoded prime row address targets a first prime row of the first plurality of row sections, cause a second threshold voltage compensation operation to be initiated on the first prime row; and
a second predecoder coupled to the second plurality of fuse latch and comparator circuits and configured to receive the second match signal and to receive the prime row address, wherein, in response to the first match signal, cause a third threshold voltage compensation to be initiated on a second redundant row associated with the second fuse latch and comparator circuit, wherein, in response to a determination that the decoded prime row address targets a second prime row of the second plurality of row sections, cause a fourth threshold voltage compensation operation to be initiated on the second prime row, wherein at least one of the first or third threshold voltage compensation operations is at least partially concurrent with at least one of the second or fourth threshold voltage compensation operations.