Patent ID: 11887964
Assignee: ZHEJIANG LAB
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 3:
4. A wafer-level heterogeneous dies integration method, comprising:
preparing a wafer substrate, comprising:
disposing a Through Silicon Via array on a wafer by a standard semiconductor process,
constructing a micro bump array on an upper surface of the wafer based on the Through Silicon Via array, and
repeating a patterning process to form repeating standard integration zones on the wafer, to obtain the wafer substrate, wherein a size of the wafer substrate is greater than or equal to 8-inch;

preparing a silicon interposer, comprising:
disposing heterogeneous micro bumps of the interposer on an upper surface of the silicon interposer by a silicon interposer preparation process, wherein the micro bumps of the interposer are configured for bonding heterogeneous dies; and

disposing standardized micro pads of the interposer on a lower surface of the silicon interposer, wherein the micro pads of the interposer are coordinated with the standard integration zones of the wafer substrate, and configured for bonding the wafer substrate; and the micro bumps of the interposer and the micro pads of the interposer are cooperatively connected with each other within the silicon interposer; and
when designing a wiring line according to chip functions in the silicon interposer, applying a direct connection to a single signal transmission, or combining a power signal transmission with the single signal transmission;
wherein the silicon interposer has different types, the silicon interposer is further provided with heterogeneous preforms in different types according to different types of the heterogeneous dies:

bonding a set of the heterogeneous dies to the upper surface of the silicon interposer to form a standard integration module, wherein a first heterogeneous die and a second heterogeneous die are bonded to a first silicon interposer, which is grinded for thinning after molding to obtain a first standard integration module; a third heterogeneous die and a fourth heterogeneous die are bonded to a second silicon interposer, which is grinded for thinning after molding to obtain a second standard integration module;
integrating a set of standard integration modules with the wafer substrate by Die to Wafer bonding to obtain a heterogeneous integration wafer; and
attaching the heterogeneous integration wafer to a configuration substrate.