Patent ID: 11948968
Assignee: NANYA TECHNOLOGY CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for preparing a semiconductor device structure, comprising:
forming a capacitor contact over a semiconductor substrate;
forming a base layer over the capacitor contact;
forming a dielectric layer over the base layer;
performing a first doping process to form a first doped region in the dielectric layer;
etching the dielectric layer such that a sidewall of the dielectric layer is aligned with a sidewall of the first doped region;
removing the first doped region to form a first gap structure in the dielectric layer after the dielectric layer is etched; and
forming a surrounding portion along sidewalls of the dielectric layer and a first interconnect portion in the first gap structure by a deposition process, wherein the base layer, the surrounding portion and the first interconnect portion collectively form a bottom capacitor electrode.