Patent ID: 11860795
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. A system comprising:
a Memory Protection Unit (MPU) associated with a Random Access Memory (RAM) memory unit; an MPU configuration unit, to indicate to said MPU a limited size of a part of the RAM memory unit that would be available to a particular executable code during its runtime; wherein the MPU is (i) to allow access of said particular executable code, during its runtime, to said limited size of RAM in said part of the RAM memory unit, and (11) to block any access of said particular executable code, during its runtime, to a forbidden memory region of the RAM memory unit which includes any other region of said RAM memory unit that is beyond said part of the RAM memory unit having the limited size; and an Iterative Memory-Boundaries Configurator unit, to iteratively modify a configuration of said MPU, by modifying in each iteration the size of the allowed portion of RAM that would be available to said executable code during runtime such that the blocked part of the RAM memory unit of the forbidden portion changes in size for each iteration.