Patent ID: 11894038
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A memory device comprising:
a memory cell array including a first region and a second region, the second region configured to store a value of a write voltage, the write voltage based on a value of a reference resistor for determining whether a programmed memory cell is in a parallel state or anti-parallel state;
a voltage generator configured to generate a code value based on the value of the write voltage;
a write driver configured to drive a write current based on the code value, the write current being a current for storing data in the first region;
a current source configured to generate a first read current and a second read current; and
a sensing circuitry including a sense amplifier configured to amplify a difference between a first voltage drop and a second voltage drop, the first voltage drop being at a first node according to an application of the first read current to a first bit line, the first bit line connected with a selected memory cell, the second voltage drop at a second node according to an application of the second read current to a reference bit line.