Patent ID: 11967955
Assignee: SAMBANOVA SYSTEMS, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A clocked storage element comprising:
a first latch having a first latch input data node, a first clock input node and a first latch output data node, the first latch comprising a first transistor directly connected to the first latch output data node with a first gate of the first transistor directly driven by the first latch input data node; and
a second latch having a second latch input data node connected to the first latch output data node, a second clock input node and a second latch output data node, the second latch comprising a second transistor directly connected to the second latch output data node with a second gate of the second transistor directly driven by the second latch input data node;
wherein (the first latch comprises a merged AND-NOR configured transistor stack with a NOR transistor stack configured as feedback, and the second latch comprises a merged OR-NAND configured transistor stack with a NAND transistor stack configured as feedback) or
(the first latch comprises the merged OR-NAND configured transistor stack with the NAND transistor stack configured as feedback, and the second latch comprises the merged AND-NOR configured transistor stack with the NOR transistor stack configured as feedback).