Patent ID: 11954358
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. An apparatus, comprising:
a non-volatile memory;
a volatile memory comprising a plurality of banks; and
an interface controller comprising:
a plurality of first buffers each having a capacity that is equal to a pane size of the volatile memory, wherein each first buffer of the plurality of first buffers is coupled with a respective bank of the plurality of banks of the volatile memory, assigned to the respective bank, configured for data transfers involving the respective bank, and configured to store data indicated by access commands for the respective bank; and
a plurality of second buffers each having a capacity that is equal to the pane size of the volatile memory, wherein each second buffer in the plurality of second buffers is coupled with a respective bank of the plurality of banks of the volatile memory, assigned to the respective bank, configured for data transfers involving the respective bank, and configured to store data for transfer between the respective bank of the volatile memory and the non-volatile memory.