Patent ID: 11916558
Assignee: QUALCOMM INCORPORATED
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 14:
15. The system of claim 1, further comprising:
a first clock source;
a second clock source;
a third clock source;
a third multiplexer having a first input, a second input, and an output, wherein the first input of the third multiplexer is coupled to the first clock source, the second input of the third multiplexer is coupled to the third clock source, and the first clock path is coupled between the output of the third multiplexer and the first input of the first multiplexer; and
a fourth multiplexer having a first input, a second input, and an output, wherein the first input of the fourth multiplexer is coupled to the second clock source, the second input of the fourth multiplexer is coupled to the third clock source, and the second clock path is coupled between the output of the fourth multiplexer and the second input of the first multiplexer.