Patent ID: 11935951
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A device comprising:
a first gate stack disposed over a substrate;
a first source/drain feature disposed on the substrate and formed of a first semiconductor material, the first source/drain feature having a first sidewall;
a passivation material layer disposed within the substrate and interfacing with a first portion of the first sidewall of the first source/drain feature such that the passivation material layer prevents the first portion of the first sidewall of the first source/drain feature from interfacing with the substrate, the passivation material layer formed of a second semiconductor material that is different than the first semiconductor material, wherein a second portion of the first sidewall is free of the passivation layer; and
a second source/drain feature disposed in the substrate and extending from the passivation material layer that is interfacing with the first sidewall of the first source/drain feature to under the first gate stack, and
wherein the passivation material layer includes a first dopant having a first-type of conductivity and the first source/drain feature includes a second dopant having a second-type of conductivity that is opposite the first-type of conductivity.