Patent ID: 11955551
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC B  H

Claim 13:
14. A method of manufacturing a semiconductor device, comprising:
forming a multi-layer structure of first semiconductor layers and second semiconductor layers alternately stacked in a vertical direction over a substrate;
patterning the multi-layer structure into a first fin structure and a second fin structure, the first and second find structures each including the first semiconductor layers and the second semiconductor layers alternately stacked over a bottom fin structure;
forming a sacrificial gate structure over the first and second fin structures;
forming a first source/drain epitaxial layer in a first source/drain region of the first fin structure;
forming a second source/drain epitaxial layer in a second source/drain region of the second fin structure;
removing the sacrificial gate structure to expose channel regions of the first and second fin structures;
removing the second semiconductor layers in the channel regions, thereby exposing the first semiconductor layers in the channel regions; and
forming a gate dielectric layer and a gate electrode layer around the first semiconductor layers in the channel region, wherein:
the first semiconductor layers are made of Si1-xGex, where 0.9≤x≤1.0,
the bottom fin structure is made of Si1-y1Gey1, where y1<x and 0.3≤y1≤0.7,
the second semiconductor layers are made of Si1-y2Gey2, where y2<x and 0.3≤y2≤0.7,
the first source/drain epitaxial layer is made of GeSn or Si1-wGew, where x≤w and 0.9≤w≤1.0, and
the second source/drain epitaxial layer is made of SiC or Si1-zGez, where 0≤z≤0.3.