Patent ID: 11899953
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A memory device comprising:
a memory array including memory cells;
a memory controller operatively coupled to the memory array and including a processor, the processor configured to:
initiate an enhanced memory operation to the memory array;
identify memory extents of the memory array affected by the enhanced memory operation;
allocate a list of unmarked extents in the memory array, wherein the list has a predetermined size, and an extent is marked if a meta state associated with the extent indicates that the extent is included in the enhanced memory operation;
receive a request for a primitive memory operation, wherein the primitive memory operation includes a memory address;
compare the memory address to the unmarked extents in the list; and
perform the primitive memory operation and the enhanced memory operation on the memory address when the memory address is included in an unmarked extent or a meta state of the memory line of the memory address is marked.