Patent ID: 11967271
Assignee: SHANGHAI TIANMA MICRO-ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 34:
35. The method according to claim 34,
wherein the pixel driving circuit is electrically connected to a first light-emitting control signal line, the first light-emitting control signal line is configured to output a first disable level and a first enable level for controlling a light-emitting state of the primary light-emitting element, the mode controlling module is electrically connected to a second light-emitting control signal line, and the second light-emitting control signal line is configured to output a second disable level and a second enable level for controlling the light-emitting state of the auxiliary light-emitting element;
wherein the display panel further comprises a regulating module, the regulating module comprises a NOR gate and an inverter, a first input terminal of the NOR gate is electrically connected to the first light-emitting signal line, a second input terminal of the NOR gate is electrically connected to a regulating signal line, an input terminal of the inverter is electrically connected to an output terminal of the NOR gate, and an output terminal of the inverter is electrically connected to the second light-emitting control signal line,
wherein the process of the second light-emitting control signal line outputting the second enable signal in the sharing mode comprises: outputting, by the regulating signal line, a low level; outputting, by the NOR gate, a high level according to the low level outputted by the regulating signal line and the low level outputted by the first light-emitting control signal line; and outputting, by the inverter, a low level according to the high level outputted by the inverter; and
wherein the process of the second light-emitting control signal line outputting the second disable signal in the anti-peeping mode comprises: outputting, by the regulating signal line, a high level; outputting, by the NOR gate, a low level; and
outputting, by the inverter, a high level according to the low level outputted by the NOR gate.