Patent ID: 11915755
Assignee: WINBOND ELECTRONICS CORP.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 3:
4. The layout of the semiconductor memory device of claim 1, wherein each of the storage units comprises:
a first inverter, comprising an input terminal and an output terminal;
a second inverter, comprising an input terminal and an output terminal, wherein the output terminal of the second inverter is electrically connected to the input terminal of the first inverter;
a first transistor, comprising a gate and two source and drain regions, wherein the two source and drain regions of the first transistor are electrically connected to the output terminal of the second inverter and a first bit line, respectively; and
a second transistor, comprising a gate and two source and drain regions, wherein the two source and drain regions of the second transistor are electrically connected to the input terminal of the second inverter and a second bit line, respectively, and the gate of the second transistor and the gate of the first transistor are electrically connected to one of the word lines.