Patent ID: 11892927
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A method for error handling of an interconnection protocol, for use in a first device that is linkable to a second device according to the interconnection protocol, the method comprising:
in processing of frames from the second device received by the first device with multiple frames being allowed to be received in each clock cycle:
a) receiving a frame error position indication signal to indicate whether an error occurs in a frame in each clock cycle and a symbol position corresponding to the error, and receiving a frame correction position indication signal to indicate whether the frame in each clock cycle is correct and a symbol position corresponding to the frame that is correct;
b) according to the frame error position indication signal and the frame correction position indication signal, and in a state of allowing Negative Acknowledgment Control (NAC) frame transmission, determining that a frame error occurs in a first clock cycle, and after requesting for NAC frame transmission, sending a request to enter into a state of disabling the NAC frame transmission; and
c) after the first clock cycle, comparing the frame error position indication signal and the frame correction position indication signal, wherein
when there is a correct frame and an error frame in a second clock cycle after the first clock cycle, if a value corresponding to the frame correction position indication signal is less than a value corresponding to the frame error position indication signal, then sending a request to enter into the state of allowing NAC frame transmission and the request for NAC frame transmission until the state of allowing NAC frame transmission is established.