Patent ID: 11942409
Assignee: MARVELL ASIA PTE LTD
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. The integrated circuit of claim 1 wherein the first set of dies comprises four dies arranged in a 2×2 array and the second set of interposer dies comprises four interposer dies, the integrated circuit further comprising:
a substrate having a perimeter aligned with a collective perimeter of the four dies; and
a filler material disposed on the substrate, the filler material having four slots such that the filler material covers the substrate at a center and four corners of the substrate and at the perimeter of the substrate;
wherein the four interposer dies are disposed in the four slots;
wherein each of the four dies includes connections on edges adjacent to a neighboring one of the four dies; and
wherein the four interposer dies include connections to interconnect different pairs of the four dies.