Patent ID: 11967286
Assignee: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 6:
7. The display substrate according to claim 6, further comprising a second connection wire in a substantially “Y” shape,
wherein the second connection wire is connected to and integrally formed with a gate electrode of the input transistor and a gate electrode of the second control transistor,
a first terminal of the second connection wire is connected to the gate electrode of the input transistor, a second terminal of the second connection wire is connected to the gate electrode of the second control transistor, and a third terminal of the second connection wire is connected to the first clock signal line or the second clock signal line through a via hole penetrating through an insulating layer to receive the first clock signal.