Patent ID: 11862251
Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An erase method for a memory device, comprising:
applying, during a time period T, a first positive voltage to a body portion of a memory cell string of the memory device, the memory cell string including memory cell transistors and select transistors connected in series;
applying, during the time period T, a second positive voltage to a bit line (BL) signal that is applied to a drain side of the memory cell string;
applying, during the time period T, a third positive voltage to a first top select gate (TSG) signal to turn on a first top select transistor of the select transistors so that the memory cell transistors are coupled to the BL signal through the first top select transistor, the first top select transistor being a closest select transistor to the drain side of the memory cell string, and the third positive voltage being less than the second positive voltage applied to the BL signal;
applying, during the time period T, a ground level voltage or a fourth positive voltage to a word line (WL) signal that is applied to gates of the memory cell transistors, the fourth positive voltage being less than the second positive voltage applied to the BL signal; and
applying, during the time period T, a fifth positive voltage to a second TSG signal to turn on a second top select transistor of the select transistors, the second top select transistor being disposed next to the first top select transistor, and the fifth positive voltage being less than the third positive voltage.