Patent ID: 11929123
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 10:
11. A semiconductor memory device comprising:
a plurality of first conductive layers arranged in a first direction;
a plurality of second conductive layers disposed to be spaced from the plurality of first conductive layers in a second direction intersecting with the first direction, the plurality of second conductive layers being arranged in the first direction;
a first semiconductor layer disposed between the plurality of first conductive layers and the plurality of second conductive layers, the first semiconductor layer extending in the first direction and being opposed to the plurality of first conductive layers and the plurality of second conductive layers;
a charge storage layer including a first part disposed between the plurality of first conductive layers and the first semiconductor layer and a second pail disposed between the plurality of second conductive layers and the first semiconductor layer;
a first wiring electrically connected to the first semiconductor layer;
a plurality of voltage supply lines applying a voltage to at least one of the plurality of first conductive layers or the plurality of second conductive layers;
a plurality of first current paths disposed between the plurality of first conductive layers and the plurality of voltage supply lines, the plurality of first current paths each including a first transistor; and
a plurality of second current paths disposed between the plurality of second conductive layers and the plurality of voltage supply lines, the plurality of second current paths each including a second transistor, wherein
the semiconductor memory device is configured to be able to execute an erase operation that includes a first erase loop and a second erase loop,
in the first erase loop, the semiconductor memory device applies a first voltage to at least a part of the plurality of first conductive layers, applies the first voltage to at least a part of the plurality of second conductive layers, and applies an erase voltage larger than the first voltage to the first wiring, and
in the second erase loop, the semiconductor memory device applies the first voltage to at least a part of the plurality of first conductive layers, applies a first signal voltage for setting the second transistor to an OFF state to a gate electrode of at least one of the second transistors in the second current paths corresponding to at least a part of the plurality of second conductive layers, and applies the erase voltage to the first wiring.