Patent ID: 11860800
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A method comprising:
receiving a compute kernel for execution using a compute-near-memory system that comprises memory-compute tiles having respective functional units and respective memory circuits;
parsing the compute kernel to provide an acyclic graph that represents multiple operations;
performing a resource search to identify candidate tiles in the compute-near-memory system to perform respective ones of the multiple operations using their respective functional units; and
assigning the multiple operations to respective ones of the identified candidate tiles based on results of the resource search and timing information from the acyclic graph;
wherein each tile in the compute-near-memory system is coupled to one or more adjacent tiles using a synchronous compute fabric and is coupled to one or more non-adjacent tiles using an asynchronous compute fabric, and wherein at least one of the multiple operations depends on an intermediate compute result communicated between adjacent tiles using the synchronous compute fabric or the asynchronous compute fabric.