Patent ID: 11882535
Assignee: APPLE INC.
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An apparatus comprising:
memory; and
processing circuitry in communication with the memory, wherein the processing circuitry is configured to:
decode one or more sidelink synchronization signals (SLSSs) received on one or more carriers;
for each of the one or more carriers on which the one or more SLSSs are decoded, determine a priority level for a carrier based on an indicator in one or more respective SLSSs received on the carrier;
select, from the one or more carriers on which one or more SLSSs are decoded, the carrier for which the determined priority level is highest; and
determine a reference timing for sidelink communication based on the one or more SLSSs received on the selected carrier.