Patent ID: 11922108
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 10:
11. The method of claim 8, wherein the placing the first set of memory cell layout patterns or the second set of memory cell layout patterns comprises:
placing a first selector element layout pattern in the first column or the second column, the first selector element layout pattern corresponding to fabricating a first selector element, the first selector element layout pattern being located on a first set of layout levels;
placing a first electrode element layout pattern on a third layout level different from the first layout level and the second layout level, the first electrode element layout pattern corresponding to fabricating a bottom electrode element of a resistive switching element, the resistive switching element being coupled to the first selector element;
placing a second electrode element layout pattern on a fourth layout level different from the first layout level, the second layout level and the third layout level, the second electrode element layout pattern corresponding to fabricating a top electrode element of the resistive switching element; and
placing a resistive switching material layout pattern between the third layout level and the fourth layout level, the resistive switching material layout pattern corresponding to fabricating a resistive switching material of the resistive switching element.