Patent ID: 11936861
Assignee: TSINGHUA UNIVERSITY
Field: Audio-visual technology (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A decoding apparatus, comprising:
a memory; and
one or more processors coupled to the memory, wherein the one or more processors are configured to:
parse a bitstream to determine a basic split mode for a current to-be-decoded picture block and a target derivation mode for a subpicture block of the current to-be-decoded picture block, wherein the target derivation mode is one derivation mode in a candidate derivation mode set, the candidate derivation mode set comprises M preset derivation modes, the preset derivation mode is used to indicate a derivation manner, the derivation manner is used for deriving one derived picture block from any two adjacent subpicture blocks of the current to-be-decoded picture block, and M is an integer greater than or equal to 0;
split the current to-be-decoded picture block into N subpicture blocks in the basic split mode, wherein N is an integer greater than or equal to 2;
derive, in a derivation manner indicated by the target derivation mode, a first derived picture block from at least two adjacent subpicture blocks in the N subpicture blocks; and
decode the first derived picture block,
wherein responsive to determining that the basic split mode is a horizontal N-way split mode or a vertical N-way split mode, 0≤M≤2N-1; or
wherein responsive to determining that the basic split mode is a horizontal and vertical N-way split mode, 0≤M≤22√{square root over (N)}x(√{square root over (N)}−1), and √{square root over (N)} is an integer.