Patent ID: 11869589
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus, comprising:
a controller;
a first content addressable memory coupled to the controller; and
a second content addressable memory coupled to the controller;
wherein the controller is configured to:
determine whether first data stored in the first content addressable memory is invalid for comparison to input data by determining whether an elapsed time from a time when the first data is written to the first content addressable memory to a time when the input data is compared to the first data is less than a threshold length of time; and

wherein the first data is concurrently written to the first content addressable memory and to the second content addressable memory such that the time when the first data is written to the first content addressable memory is the time when the first data is written to the second content addressable memory.