Patent ID: 11967631
Assignee: JSAB TECHNOLOGIES (SHENZHEN) LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A method for manufacturing the power semiconductor device according to claim 1, wherein the method comprises the steps of:
first, forming a lightly-doped semiconductor region of the second conductivity type;
second, forming a gate trench, a dummy gate trench, a fourth semiconductor region of a first conductivity type and a seventh semiconductor region of a first conductivity type on an upper surface of the lightly-doped semiconductor region of the second conductivity type;
third, forming a heavily-doped fifth semiconductor region of the second conductivity type on an upper surface of the fourth semiconductor region of a first conductivity type by ion implantation and annealing, and depositing an insulating dielectric layer on the upper surface;
fourth, performing mask etching on the insulating dielectric layer, respectively forming a first etched hole located between two adjacent gate trenches and a second etched hole located between the adjacent gate trench and dummy gate trench, wherein the first etched hole and the second etched hole are in contact with the upper surface of the heavily-doped fifth semiconductor region of the second conductivity type, the width of the second etched hole is greater than the width of the first etched hole, and the horizontal spacing between the second etched hole and the adjacent dummy gate trench is less than the horizontal spacing between same and the adjacent gate trench;
fifth, using the remaining insulating dielectric layer as a mask, implanting ions of the first conductivity type below the first etched hole and the second etched hole, and forming a heavily-doped sixth semiconductor region of a first conductivity type by annealing;
sixth, performing trench etching with the remaining insulating dielectric layer as a mask, and synchronously forming a first contact trench and a second contact trench;
seventh, performing surface metal deposition to form an emitter;
eighth, moderately thinning the lightly-doped semiconductor region of the second conductivity type from its lower surface to reach a target thickness determined by a device withstand voltage value, and then forming a second semiconductor layer and a first semiconductor layer at the bottom of the thinned lightly-doped semiconductor region of the second conductivity type through an ion implantation and activation process; and
ninth, metalizing at the bottom of the device to form a collector.