Patent ID: 11968843
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 14:
15. A method of manufacturing an integrated circuit, comprising:
forming one or more processing cores of an integrated circuit chip in a substrate; and
forming one or more magnetoresistive random access memory (MRAM) arrays of the integrated circuit chip in the substrate, the one or more MRAM arrays being organized into a plurality of memories including at least one cache memory and at least one main memory;
forming a first addressing circuit positioned in close proximity to a first region of the one or more MRAM arrays and coupled to the first region of the one or more MRAM arrays via a first set of memory control lines, the first region of the one or more MRAM arrays implementing the at least one cache memory, the first addressing circuit corresponding to a second region of the one or more of MRAM arrays; and
forming a second different addressing circuit positioned in close proximity to the second region of the one or more MRAM arrays and coupled to the second region of the one or more MRAM arrays via a second set of memory control lines, the second region of the one or more MRAM arrays implementing the at least one main memory, the second addressing circuit corresponding to the second region of the one or more of MRAM arrays, and the second addressing circuit different from the first addressing circuit,
wherein a MRAM cell of the plurality of MRAM cells includes a fixed layer, a free layer and a tunnel barrier layer between the fixed layer and the free layer, the free layer coupled to a first source or drain terminal of a control transistor through a metal layer, the fixed layer coupled to a bit line; and

wherein a second source or drain terminal of the control transistor is coupled to a sense line and a gate of the control transistor is coupled to a write line.