Patent ID: 11876032
Assignee: MURATA MANUFACTURING CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. The semiconductor device according to claim 1, further comprising:
a foundation semiconductor layer disposed between the bond layer and the semiconductor element, wherein
the foundation semiconductor layer includes, in the plan view, a plurality of conducting regions and an element isolating region other than the conducting regions,
the collector layer of the first transistor is electrically coupled to the metal region of the bond layer by using one of the conducting regions of the foundation semiconductor layer,
the bond layer includes, in the plan view, an insulating region disposed in an outer side portion of the metal region,
the foundation semiconductor layer further includes a third conducting region disposed above the insulating region of the bond layer,
the semiconductor element further includes a third transistor disposed on the third conducting region, and
the third transistor includes a collector layer electrically coupled to the third conducting region, a base layer disposed on the collector layer, and an emitter layer disposed on the base layer,

a third emitter electrode disposed on the emitter layer of the third transistor and electrically coupled to the emitter layer of the third transistor; and
a third collector electrode disposed, in the plan view, in an inner side portion of the third conducting region and in an outer side portion of the third transistor and electrically coupled to the third conducting region.