Patent ID: 11868265
Assignee: ORACLE INTERNATIONAL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A method comprising:
proxying a source of a reset or power transition event in a computing system to system logic configured to (a) generate an interrupt signal, on a first pin of a chipset, that triggers a persistent cache flushing operation and delays a reset or power transition when in a first mode and (b) directly route a request to perform the reset or power transition on a second pin of the chipset without invoking the persistent cache flush handler when operating in a second mode;
responsive to detecting the reset or power transition event, determining by the system logic whether to generate the interrupt signal on the first pin or directly route the request on the second pin based on whether the first mode is enabled in the computing system;
responsive to determining that the first mode is enabled, generating, by the system logic, the interrupt signal, on the first pin of the chipset, that triggers the persistent cache flushing operation; and
delaying the reset or power transition until the persistent cache flushing operation has completed or a timeout has expired;
wherein the chipset halts task execution on a hardware processor and invokes a persistent cache flush handler responsive to detecting the interrupt on the first pin.