Patent ID: 11972188
Assignee: NVIDIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 19:
20. A non-transitory computer-readable media storing computer instructions for producing an integrated circuit layout that, when executed by one or more processors, cause the one or more processors to perform the steps of:
obtaining power density values for a plurality of cells in an initial cell placement for an integrated circuit layout, wherein the initial cell placement is subdivided into multiple regions, and wherein at least a first region of the multiple regions includes multiple power supply rails and a first portion of the cells of the plurality of cells in the initial cell placement;
computing a per-rail power density value for each power supply rail within the first region by,
for each time slice within a timing window, computing a per-time slice power density as a sum of the power density value for the cells in the first portion of the cells that are active during the time slice; and
selecting the per-rail power density value as a maximum value of the per-time slice power density values;

for each of a plurality of cell placements of the first portion of the cells, evaluating an objective function based on the per-rail power density values to generate a result value; and
selecting a cell placement of the plurality of cell placements, in response to the result values.