Patent ID: 11909388
Assignee: SHENZHEN PANGO MICROSYSTEMS CO., LTD
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 15:
16. A chip communication device, comprising: a first FPGA chip, a second FPGA chip, a first transmission line, a second transmission line and three terminal resistance circuits;
wherein the three terminal resistance circuits comprise a first terminal resistance circuit, a second terminal resistance circuit and a third terminal resistance circuit; a high-speed differential I/O pair of the first FPGA chip comprises a first port and a second port, and a high-speed differential I/O pair of the second FPGA chip comprises a third port and a fourth port;
wherein the first port of the first FPGA chip is electrically connected to the third port of the second FPGA chip through the first transmission line, and the second port of the first FPGA chip is electrically connected to the fourth port of the second FPGA chip through the second transmission line;
wherein the first terminal resistance circuit is integrated in the first FPGA chip;
wherein the second terminal resistance circuit is arranged outside the second FPGA chip;
wherein the third terminal resistance circuit is integrated in the second FPGA chip;
wherein each of the first through third terminal resistance circuits comprises:
resistance circuits connected in series, wherein a wire connected between the resistance circuits has a target node thereon; and
a control circuit, electrically connected to the resistance circuits and configured to control the resistance circuits each to be in a turn-off state during powering-on of the chip;

wherein an end of the series-connected resistance circuits of the first terminal resistance circuit is electrically connected to the first port, another end of the series-connected resistance circuits of the first terminal resistance circuit is electrically connected to the second port, and
wherein an end of the series-connected resistance circuits of the second terminal resistance circuit is electrically connected to the third port, another end of the series-connected resistance circuits of the second terminal resistance circuit is electrically connected to the fourth port; and
wherein an end of the series-connected resistance circuits of the third terminal resistance circuit is electrically connected to the third port, another end of the series-connected resistance circuits of the third terminal resistance circuit is electrically connected to the fourth port.