Patent ID: 11935828
Assignee: STMICROELECTRONICS (ROUSSET) SAS
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 17:
18. An integrated circuit, comprising:
a semiconductor substrate;
an isolating region delimiting a working area of the semiconductor substrate;
a plurality of strips overlying the semiconductor substrate, wherein each strip includes an electrically conductive layer insulated from the semiconductor substrate by a dielectric layer and a sidewall spacer;
a plurality of trenches in the semiconductor substrate, wherein each trench is centered underneath a corresponding one of the strips of said plurality of strips, and wherein each trench is filled by an electrically conductive central portion enclosed in an isolating enclosure;
wherein the sidewall spacers of an adjacent pair of strips of said plurality of strips extend over side parts of a portion of the semiconductor substrate located between the adjacent pair of strips;
a plurality of first doped regions in the portions of the semiconductor substrate located between the adjacent pairs of strips;
a first metal silicide located on a part of each first doped region not covered by the sidewall spacers of the strips;
a second metal silicide located on the electrically conductive layer of each strip;
a first electrical contact to the first metal silicide forming a first electrode of a filler capacitor cell device; and
a second electrical contact to the second metal silicide forming a second electrode of the filler capacitor cell device.