Patent ID: 11968828
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. A method, comprising:
forming an isolation region in a semiconductor substrate to define a cell region and a peripheral region in the semiconductor substrate, and an isolation feature in the peripheral region;
forming a gate stack of a memory cell over the cell region of the semiconductor substrate;
after forming the gate stack of the memory cell, forming a concave dielectric layer over the peripheral region of the semiconductor substrate, wherein a thickness of an edge portion of the concave dielectric layer is greater than a thickness of a middle portion of the concave dielectric layer, wherein a top surface of the edge portion of the concave dielectric layer is higher than a top surface of a tunneling layer of the gate stack of the memory cell, wherein forming the concave dielectric layer comprises:
forming a first dielectric layer over the semiconductor substrate;
patterning the first dielectric layer, such that an opening is formed in the first dielectric layer, and a first portion and a second portion of the first dielectric layer adjacent to the isolation feature remain, the first and second portions are at a first region of the peripheral region at a first side of the isolation feature, and a second region of the peripheral region at a second side of the isolation feature opposite to the first side is exposed from the first dielectric layer;
forming a second dielectric layer over the first and second regions of the peripheral region to cover the first and second portions of the first dielectric layer and in the opening; and
patterning the second dielectric layer, such that the first and second portions of the first dielectric layer and the patterned second dielectric layer are defined as the concave dielectric layer, and the second region of the peripheral region is exposed from the second dielectric layer;

after forming the concave dielectric layer, forming an interfacial layer over the second region of the peripheral region of the semiconductor substrate;
after forming the interfacial layer, forming a high-k dielectric layer over the interfacial layer, wherein the high-k dielectric layer is in contact with the interfacial layer;
forming a dummy gate layer over the high-k dielectric layer;
patterning the dummy gate layer, the high-k dielectric layer, the interfacial layer, and the concave dielectric layer to form a first gate stack over the first region of the peripheral region and a second gate stack over the second region of the peripheral region; and
replacing the patterned dummy gate layer with a conductive layer.