Patent ID: 11955531
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A method of forming an integrated circuit device comprising:
forming a gate structure and a source/drain region on a substrate, wherein the source/drain region is on a first side of the gate structure;
forming an interlayer dielectric on the substrate to overlap the gate structure and the source/drain region;
forming a first contact hole that penetrates the interlayer dielectric to expose an upper surface of the source/drain region;
forming a first contact in a lower portion of the first contact hole, wherein the first contact is in contact with the upper surface of the source/drain region;
forming a first capping layer on an inner wall of an upper portion of the first contact hole;
forming a second capping layer on the first capping layer to at least partially fill an inside of the upper portion of the first contact hole;
forming a second contact hole that penetrates the interlayer dielectric to expose an upper surface of the gate structure, wherein a sidewall of the first capping layer is exposed to an inner wall of the second contact hole; and
forming a second contact in the second contact hole, wherein the second contact is in contact with the upper surface of the gate structure,
wherein the first capping layer includes a material having higher etch selectivity with respect to the interlayer dielectric than a material included in the second capping layer.