Patent ID: 11925021
Assignee: SK HYNIX INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of manufacturing a semiconductor device, the method comprising:
forming a first stack structure including first interlayer insulating layers and first conductive patterns which are alternately stacked on each other, and penetrated by first channel structures;
forming a second stack structure including second interlayer insulating layers and sacrificial layers which enclose second channel structures coupled to the first channel structures and which are alternately stacked on each other, on the first stack structure;
forming at least one first opening and at least one second opening which expose the sacrificial layers by etching the second stack structure;
replacing each of the sacrificial layers with a conductive material through the first opening and the second opening; and
forming second conductive patterns separated from each other through the first opening by etching the conductive material to expose a bottom surface of the first opening such that the second opening is filled with one second conductive pattern among the second conductive patterns.