Patent ID: 11886744
Assignee: NVIDIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. A system comprising:
a requester having a first processor and a first memory including first computer program code, the first memory and the first computer program code configured to, with the first processor, cause the requester to:
transmit a request to make one or more writes associated with an identification tag, the request comprising:
the identification tag,
the one or more writes,
a first instruction to make the one or more writes to one of a plurality of persistence levels of a second memory,
a second instruction to respond with at least one first indication that at least one of the one or more writes associated with the identification tag have been written to the one of the plurality of persistence levels of the second memory,
a third instruction to make the one or more writes associated with the identification tag visible, and
a fourth instruction to respond with at least one second indication that at least one of the one or more writes associated with the identification tag have reached a point of visibility; and

receive the at least one first indication that at least one of the one or more writes associated with the identification tag have been written to the one of the plurality of persistence levels of the second memory; and

a completer having a second processor and the second memory including second computer program code, the second memory and the second computer program code configured to, with the second processor, cause the completer to:
receive the request to make the one or more writes associated with the identification tag;
write the one or more writes associated with the identification tag to the one of the plurality of persistence levels of the second memory; and
transmit the at least one first indication to the requester that at least one of the one or more writes associated with the identification tag have been written to the one of the plurality of persistence levels of the second memory.