Patent ID: 11971826
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 5:
6. The non-volatile memory device of claim 5, wherein:
the first internal data bus is configured to transfer data from the first cache buffer to the input-output interface in a parallel format; and
the second internal data bus is configured to transfer data from the second cache buffer to the input-output interface in the parallel format, and
input-output interface comprises:
a set of input-output pads;
a first parallel format to a serial format converter configured to convert received data from the first internal data bus in the parallel format into a series format and provide the received data from the first internal data bus in the series format to the set of input-output pads; and
a second parallel format to a serial format converter configured to convert received data from the second internal data bus in the parallel format into the series format and provide the received data from the second internal data bus in the series format to the set of input-output pads.