Patent ID: 11887674
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 2:
3. The memory apparatus as set forth in claim 1, wherein each of the plurality of data states is grouped into one of a plurality of probability pattern groups according to the probability of the at least one neighboring one of the plurality of bit lines being coupled to the memory cells retaining the threshold voltage corresponding to the different one of the plurality of data states than the one of the memory cells and the control means is further configured to offset the at least one of the bit line settling time and the kick voltage applied to the one of the plurality of bit lines coupled to the one of the memory cells during the read operation according to which of the plurality of probability pattern groups is associated with the one of the plurality of data states to which each of the memory cells is being read during the read operation.