Patent ID: 11871626
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 7:
8. The display panel according to claim 7, wherein:
the gate driving circuit comprises a first clock signal line and a second clock signal line located on one side of the first clock signal line away from the display area;
the first planarization portion comprises a third opening located above the first clock signal line and a fourth opening located above the second clock signal line; and
the display panel further comprises:
a second conductive portion located in the third opening and in contact with the first clock signal line,
a third conductive portion located in the fourth opening and in contact with the second clock signal line,
a second planarization layer located on one side of the first planarization layer away from the base substrate, and comprising:
a second planarization portion located between the first planarization portion and the connection layer, and covering the second conductive portion and the third conductive portion, and
a third planarization portion spaced apart from the second planarization portion, located on one side of the light-emitting control driving circuit away from the display area, and comprising a fifth opening located above the first conductive portion, wherein the connection layer is partially located in the fifth opening, and a portion of the connection layer located between the third planarization portion and the second planarization portion is at least partially in contact with the first planarization layer.