Patent ID: 11915740
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 20:
21. An apparatus, comprising:
a memory array comprising a plurality of pillars arranged in a two-dimensional array of a first quantity of pillars along a first direction and a second quantity of pillars along a second direction, each pillar of the plurality of pillars coupled with a respective plurality of memory cells;
a first word line driver;
a second word line driver; and
circuitry coupled with memory array, wherein, to access the memory array, the circuitry is operable to:
couple each pillar of a set of pillars along the second direction, having the second quantity of pillars, with a respective sensing line;
bias, with the first word line driver and during the coupling of each pillar of the set with the respective sensing line, a first word line coupled with a respective memory cell of each pillar of a first subset of the set of pillars, the first subset associated with a third quantity of pillars along the second direction that is less than the second quantity of pillars; and
bias, with the second word line driver and during the coupling of each pillar of the set with the respective sensing line, a second word line coupled with a respective memory cell of each pillar of a second subset of the set of pillars, the second subset associated with the third quantity of pillars along the second direction.