Patent ID: 11862535
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 17:
18. A method of forming an integrated chip, comprising:
forming a plurality of interconnects within an inter-level dielectric (ILD) structure along a first side of a substrate;
forming a masking layer on a second side of the substrate opposing the first side;
performing a first etching process to etch the substrate according to the masking layer and to form sidewalls of the substrate that define a first through-substrate-via (TSV) opening extending through the substrate, wherein the first TSV opening has a width that increases as a distance from the masking layer increases;
forming a dielectric liner along the sidewalls of the substrate and on the ILD structure;
performing a second etching process on the dielectric liner and the ILD structure to form a second TSV opening exposing one of the plurality of interconnects, wherein the second TSV opening is separated from a sidewall of the dielectric liner by a non-zero distance; and
forming a through-substrate-via (TSV) within the first TSV opening and the second TSV opening, wherein the dielectric liner has sidewalls that slope inward towards one another from an upper surface of the dielectric liner arranged directly below the TSV to a topmost surface of the dielectric liner over the sidewalls of the substrate, as viewed in a cross-sectional view.