Patent ID: 11960853
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 17:
18. A field-programmable gate array (FPGA) comprising:
a multiplier configurable to perform multiplication;
a first addition/subtraction unit and a second addition/subtraction unit, both configurable to perform addition and subtraction;
a first set of registers configurable to store one or more products generated by the multiplier;
a second set of registers configurable to store one or more first values generated by the first addition/subtraction unit;
a third set of registers configurable to store one or more second values generated by the second addition/subtraction unit;
a first multiplexer communicatively coupled to the multiplier, wherein the first multiplexer is configurable to select a first received value as a first operand to provide to the multiplier based on a first control signal of a plurality of control signals;
a second multiplexer communicatively coupled to the multiplier, wherein the first multiplexer is configurable to select a second received value as a second operand to provide to the multiplier based on a second control signal of the plurality of control signals; and
control circuitry communicatively coupled to the first and second multiplexers, wherein the control circuitry is configurable to output the plurality of control signals to cause the FPGA to determine a plurality of products for a plurality of pairs of input values having a first number of bits, wherein the FPGA is configurable to determine each product of the plurality of products by:
performing, using the multiplier and based on the plurality of control signals, a plurality of multiplication operations involving values having fewer bits than the first number of bits, wherein the plurality of multiplication operations comprises a first number of multiplication operations and the multiplier is configurable to begin performing each multiplication operation of the plurality of multiplication operations in a sequence of consecutive clock cycles; and
performing, using the first and second addition/subtraction units, a plurality of operations involving addition or subtraction.