Patent ID: 11888496
Assignee: KIOXIA CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A semiconductor integrated circuit comprising:
an A/D converter configured to convert an analog signal into a digital signal based on a clock signal;
a first equalizer circuit includes a plurality of taps including a first tap that is one tap after a center tap, the first equalizer circuit receiving a signal based on the digital signal and outputting a first signal;
a first data comparator circuit configured to determine data based on the first signal and output the determined data as first data;
a second equalizer circuit includes a plurality of taps, the second equalizer circuit receiving a signal based on the digital signal and outputting a second signal;
a second data comparator circuit configured to determine data based on the second signal and output the determined data to an outside;
a first control circuit configured to adjust a phase of the clock signal based on the first signal and the first data, and input the adjusted clock signal to the A/D converter; and
a second control circuit configured to control each of the first equalizer circuit and the second equalizer circuit, and execute an operation of adjusting a control parameter including a tap coefficient, wherein
in the operation, the second control circuit is configured to adjust a tap coefficient of each of the taps of the second equalizer circuit, and adjust a tap coefficient of the first tap based on an adjustment result of each tap coefficient of the second equalizer circuit.