Patent ID: 11947409
Assignee: XILINX, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A method comprising:
determining, by a first parity circuit of parity checking circuitry of an integrated circuit (IC) device, a first value from first register values of a plurality of registers of the IC device, wherein the first register values correspond to first bits of two or more of the plurality of registers, and wherein the first register values have fewer bits than the plurality of registers;
determining, by a second parity circuit of the parity checking circuitry, a second value from second register values of the plurality of registers, wherein the second register values correspond to second bits of the two or more of the plurality of registers;
comparing the first and second values to determine a first error within the plurality of registers; and
outputting an error signal indicative of the first error.