Patent ID: 11893438
Assignee: EXCELIO TECHNOLOGY (SHENZHEN) CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A method of using the above disclosed positive feedback latch amplitude limiting control circuit in claim 6 to perform a graded amplitude limiting control, the method comprising following steps:
S1: a resonance circuit is coupled with an external magnetic field to generate an alternating current and inputs the alternating current to the rectifier circuit, and the rectifier circuit rectifies the alternating current into a direct current and outputs the direct current to each circuit module including the signal generating circuit, the first signal processing circuit, the first discharge circuit, the second signal processing circuit, the second signal control circuit and the second discharge circuit;
S2: the signal generating circuit generates the first control signal S1 that varies with the change of the strength of the magnetic field coupled to the coil of the passive RFID tag, and inputs the first control signal S1 to the first signal processing circuit and the second signal processing circuit, wherein: when the voltage value of the first control signal S1 is too low to drive the inverting sub-module in the first signal processing circuit to be turned on, the logic signal S2 outputted by the first signal processing circuit is a high level “1”; when the voltage value of the first control signal S1 gradually increases to the turn-on voltage of the inverting sub-module, the logic signal S2 outputted by the first signal processing circuit is a low level “0”; the first signal processing circuit returns the logic signal S2 of the high level “1” or the low level “0” to the signal generating circuit; and when the voltage value of the first control signal S1 is lower than the sum of the threshold voltage of the unidirectional conduction threshold device and the turn-on voltage of the inverting sub-module in the second signal processing circuit, the logic signal S2′ outputted by the second signal processing circuit is the high level “1”; when the voltage value of the first control signal S1 gradually increases to the sum of the threshold voltage of the threshold device and the turn-on voltage of the inverting sub-module in the second signal processing circuit, the logic signal S2′ outputted by the second signal processing circuit is the low level “0”; and the second signal processing circuit inputs the above logic signal S2′ of the high level “1” or the low level “0” to the second signal control circuit; and
S3: when the inputted logic signal S2 is the high level “1”, the first N-type MOS transistor in the signal generating circuit is turned on, and the second resistive device is short-circuited; because the resistance value of the first resistive device is far smaller than the resistance value of the second resistive device, the first control signal S1 is rapidly pulled down to a low level signal, such that the second N-type MOS transistor in the first discharge circuit is turned off, and the first discharge path maintains the turned-off state; when the inputted logic signal S2 is the low level “0”, the first N-type MOS transistor is turned off, and the first control signal S1 maintains a high-level signal, such that the second N-type MOS transistor is turned on, the first discharge path is switched from the turned-off state to the turned-on state, and the charges at an antenna terminal are outputted to the ground; when the inputted logic signal S2′ is the high level “1”, the third N-type MOS transistor in the second signal control circuit is turned on, and the fourth resistive device is short-circuited; because the resistance value of the third resistive device is far smaller than the resistance value of the fourth resistive device, the second control signal S3 is rapidly pulled down to a low level signal, such that the fourth N-type MOS transistor in the second discharge circuit is turned off, and the second discharge path maintains the turned-off state; when the inputted logic signal S2′ is the low level “0”, the third N-type MOS transistor is turned off, and the third control signal S3 maintains a high-level signal, such that the fourth N-type MOS transistor is turned on, the second discharge path is switched from the turned-off state to the turned-on state, and the charges at the antenna terminal are outputted to the ground.