Patent ID: 11936927
Assignee: REALTEK SEMICONDUCTOR CORPORATION
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 13:
14. The receiver control circuit of claim 11, wherein the receiver control circuit receives a pixel clock signal from the transmitter control circuit, and provides the pixel clock signal to the display module, wherein each pulse of the pixel clock signal is configured to control the display module to update a corresponding pixel of the display module,
wherein the receiver control circuit is configured to receive a data enable signal, when the data enable signal provides a pulse, the receiver control circuit generates the control signal according to information in the plurality of first hybrid data packets, and each pulse of the data enable signal is configured to control the display module to update a corresponding row of pixels of the display module,
wherein a width of the pulse of the data enable signal corresponds to a width of K pulses of the pixel clock signal, K is a positive integer and greater than a horizontal resolution of a pixel array of the display module.