Patent ID: 11966741
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 19:
20. An apparatus, comprising:
a processor core configured to execute a plurality of instructions;
an interconnection network interface coupleable to an interconnection network to receive a call work descriptor data packet and to receive one or more load response data packets, the interconnection network interface configured to decode the call work descriptor data packet into an initial program count and a received argument for a corresponding execution thread;
a thread control memory coupled to the interconnection network interface, the thread control memory comprising a thread identifier pool register configured to store a plurality of thread identifiers, a program count register configured to store the initial program count, a data cache configured to store cached data, and a general-purpose register configured to store the received argument and non-cached data;
an execution queue coupled to the thread control memory, the execution queue configured to store one or more thread identifiers of the plurality of thread identifiers;
a control logic and thread selection circuit coupled to the execution queue and to the thread control memory, the control logic and thread selection circuit configured, in response to the call work descriptor data packet, to assign a thread identifier to the corresponding execution thread and to place the thread identifier in the execution queue, to periodically select the thread identifier for execution by the processor core of a single instruction of the corresponding execution thread, with the processor core automatically commencing execution of the single instruction corresponding to the initial program count using the received argument;
an instruction cache coupled to the control logic and thread selection circuit to receive the initial program count and provide the single instruction for execution by the processor core;
a network response memory coupled to the interconnection network interface, the network response memory comprising one or more memory request registers and one or more transaction identifier registers storing a plurality of transaction identifiers, each transaction identifier of the plurality of transaction identifiers associated with a selected thread identifier, of the plurality of thread identifiers, of a corresponding execution thread which generated a memory request; and
data path control circuitry configured to increase or decrease an amount of data transferred, in the one or more data packets to or from a memory circuit coupled to the interconnection network, in response to a time-averaged usage level of the interconnection network or the memory circuit.