Patent ID: 11894345
Assignee: ADEIA SEMICONDUCTOR INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A method comprising:
forming a package substrate comprising a first side and a second side opposite the first side;
coupling a first side of a first semiconductor die to the second side of the package substrate;
coupling a first bonding layer to a second side of the first semiconductor die opposite the first side of the first semiconductor die;
coupling a second bonding layer to a first side of a second semiconductor die;
forming a circuit comprising at least one active component on the first semiconductor die or the second semiconductor die;
integrating a first portion of a first passive component into the first semiconductor die;
integrating a second portion of the first passive component into the second semiconductor die;
electrically coupling the first portion or the second portion of the first passive component to the circuit; and
completing the first passive component by coupling the second side of the first semiconductor die to the first side of the second semiconductor die.