Patent ID: 11869582
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 15:
16. A memory device comprising:
a memory cell region comprising a first metal pad;
a peripheral circuit region comprising a second metal pad and configured to be connected in a vertical direction to the memory cell region through the first metal pad and the second metal pad;
a memory cell array including a plurality of memory cells including a plurality of strings extending in the vertical direction with respect to a substrate in the memory cell region; and
a control logic circuit configured to apply a first program pulse and a first verify pulse in a first program loop of a plurality of program loops in the peripheral circuit region, count a number of first off cells by using an output based on the first verify pulse, determine a first verify skip period based on the number of first off cells, apply an N-th program pulse and a plurality of verify pulses in response to termination of the first verify skip period, count a number of second off cells by using an output based on the plurality of verify pulses, and determine a second verify skip period based on the number of second off cells, wherein N is a positive integer.