Patent ID: 11961795
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A method of manufacturing a semiconductor package, the method comprising:
attaching a plurality of semiconductor chips and a plurality of lower conductive solders onto a support wiring structure array;
forming a preliminary filling member surrounding the plurality of semiconductor chips and the plurality of lower conductive solders on the support wiring structure array and including a plurality of fillers;
forming a lower filling unit and a plurality of lower connection units by removing an upper portion of the preliminary filling member, upper portions of the plurality of lower conductive solders, and upper portions of the plurality of semiconductor chips;
attaching a plurality of upper conductive solders under a cover wiring structure array;
arranging the cover wiring structure array on the support wiring structure array so that the plurality of lower connection units and the plurality of upper conductive solders correspond to each other;
forming a plurality of connection structures that are one body by soldering the plurality of lower connection units and the plurality of upper conductive solders corresponding to each other by performing a reflow process, each of the plurality of connection structures including the lower connection unit and an upper connection unit;
forming a filling member including the lower filling unit and an upper filling unit, the upper filling unit is formed by filling a gap between the lower filling unit and the cover wiring structure array; and
individualizing the support wiring structure array and the cover wiring structure array into support wiring structures and cover wiring structures corresponding to each other,
wherein a partial portion of the plurality of fillers includes cutting fillers, and
wherein each of upper surfaces of the cutting fillers is a flat surface as seen in a cross-sectional view.