Patent ID: 11907062
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. The semiconductor system of claim 11, wherein the memory apparatus comprises:
an ECS engine configured to generate an ECS control signal by decoding a command that is received from the controller;
an ECS address generation circuit configured to:
sequentially increase and store an ECS address based on the ECS control signal,
transmit, to the controller, the ECS information that is generated from the ECS address in response to the count request signal,
generate an ECS address for the ECS operation based on the ECS control signal and the ECS resume information after the start of the boot-up operation, and
sequentially increase the ECS address by receiving the ECS control signal; and

a core circuit comprising multiple banks each comprising a selected region, and configured to perform the ECS operation on the selected region of a selected bank, among the multiple banks, based on the ECS control signal and the ECS address.