Patent ID: 11967578
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 19:
20. A semiconductor package comprising:
a semiconductor chip;
a base layer disposed outside the semiconductor chip;
a mold layer interposed between the semiconductor chip and the base layer, the mold layer covering upper surfaces of the semiconductor chip and the base layer;
a lower redistribution layer on a lower surface of the semiconductor chip;
an upper redistribution layer on the mold layer;
a conductive via electrically interconnecting the lower redistribution layer and the upper redistribution layer, the conductive via extending through the base layer in a vertical direction; and
a connecting terminal on a lower surface of the lower redistribution layer,
wherein the lower redistribution layer comprises an insulating layer, a redistribution pattern on the insulating layer, a via connected to an upper surface of the redistribution pattern and extending through the insulating layer in a vertical direction, an under bump metal (UBM) connected to a lower surface of the redistribution pattern, and a post connected to the upper surface of the redistribution pattern while vertically overlapping with the UBM,
wherein the UBM comprises a first section having an upper surface directly contacting the redistribution pattern, and a second section having an upper surface directly contacting the insulating layer,
wherein the post has a ring shape having an inner surface and an outer surface when viewed in a top view,
wherein, when viewed in a top view, a maximum width of the inner surface is in a range of about 0.2 to 0.8 times a maximum width of an upper surface of the first section, and a maximum width of the outer surface is about 1.2 times or more the maximum width of the upper surface of the first section,
wherein a lateral edge of the upper surface of the first section vertically overlaps with the post.