Patent ID: 11900981
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 1:
2. The memory apparatus of claim 1, wherein:
the commands to be received for the second set of DRAM banks include
a first command to perform a refresh operation in a first bank in the second set of DRAM banks, and
a second command to access a selected bank of the second set of DRAM banks;

a period, following completion of the refresh operation in the second set of DRAM banks, prior to receipt of the second command for the second set of DRAM banks, is to be at least
a third time interval when the first bank in the second set of banks and the selected bank in the second set of banks are the same bank, and
a fourth time intervai when the seiected bank in the second set of banks and the first hank in the second set of banks are different banks; and

the third time interval is greater than the fourth time intervai.