Patent ID: 11935604
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A memory device comprising:
a memory array having strings of cells, each string including a selector device coupling the string to a data line to the memory array and including multiple memory cells, with the selector device coupled to a select line, each of the multiple memory cells coupled to a respective different access line;
multiple drivers coupled to the select lines and the access lines; and
a memory controller to selectively direct one or more drivers of the multiple drivers to generate a selector signal simultaneously both to a first driver coupled to a first select line of a first string of the strings of the memory array and to a dummy memory cell directly adjacent to the first selector device in the first string with data memory cells of the first string maintained unselected, in response to a determination of completion of a selected erase operation to at least one data memory cell of the first string, the selected erase operation including an erase verify procedure, the completion completing erasure of the at least one data memory cell of the first string.