Patent ID: 11949629
Assignee: ASTERA LABS, INC.
Field: Digital communication (Electrical engineering)
Classification: CPC G  H | IPC H

Claim 17:
18. A method of operation within an integrated circuit component, the method comprising:
receiving a first stream of fixed-length blocks of symbols having first length-modifiable blocks of symbols spaced from one another at first intervals within the first stream;
generating a second stream of fixed-length blocks of symbols throughout a first time period in which reception of the first stream of fixed-length blocks of symbols temporarily ceases, including embedding second length-modifiable blocks of symbols at second intervals within the second stream of fixed-length blocks of symbols; and
adjusting lengths of successive ones of the second length-modifiable blocks relative to counterpart ones of the first length-modifiable blocks to reduce a temporal misalignment between the first and second intervals; and
outputting from the integrated circuit component:
the first stream of fixed-length blocks of symbols prior to the first time period;
the second stream of fixed-length blocks of symbols instead of the first stream of fixed-length blocks of symbols during the first time period; and
the first stream of fixed-length blocks of symbols following a second time period that transpires after the first time period and during which (i) reception of the first stream of fixed-length blocks of symbols restarts and (ii) the lengths of the successive ones of the second length-modifiable blocks are adjusted relative to the counterpart ones of the first length-modifiable blocks to reduce the temporal misalignment between the first and second intervals.