Patent ID: 11907369
Assignee: VENTANA MICRO SYSTEMS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A microprocessor that mitigates side channel attacks,
comprising:
a cache memory;
fill request generation logic configured to generate a request to fill the cache memory with a cache line implicated by a memory address that misses in the cache memory;
wherein the processor is configured to perform speculative execution of instructions;
wherein the processor is configured to execute instructions out of program order; and
at least one execution pipeline configured to:
receive first and second load operations;
detect a condition in which the first load operation generates a need for an architectural exception, the second load operation misses in the cache memory, and the second load operation is newer in program order than the first load operation; and
prevent state of the cache memory from being affected by the miss of the second load operation by inhibiting the fill request generation logic from generating a fill request for the second load operation or by canceling the fill request for the second load operation if the fill request generation logic has already generated the fill request for the second load operation;

wherein to prevent the state of the cache memory from being affected by the miss of the second load operation means there are no side effects on the cache memory as a result of the miss of the second load operation in the cache memory.