Patent ID: 11862282
Assignee: CEREMORPHIC, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 14:
15. A memory performing a logical exclusive or (XOR) operation, the memory comprising:
a first Single Transistor Static Random Access Memory (STSRAM) having a source, drain, and gate, and storing a charge value which influences a conductivity from the drain to the source when the gate is enabled;
a second STSRAM having a source, drain, and gate, and storing a charge value which influences a conductivity from the drain to the source when the gate is enabled;
a select line (SL) coupled to the first STSRAM drain and also to the second STSRAM drain;
a first current comparator amplifier (CCA) having an inverting input and a noninverting input, the first CCA generating a binary output by comparison of a current applied to the inverting input and a current applied to the noninverting input;
a second current comparator amplifier (CCA) having an inverting input and a noninverting input, the second CCA generating a binary output by comparison of a current applied to the inverting input and a current applied to the noninverting input;
a Bit Line (BL) node coupled to the first STSRAM source, the second STSRAM source, and to the noninverting input of the first CCA and also to the inverting input of the second CCA;
the first CCA inverting input coupled to a first current source Iref1, the second CCA noninverting input coupled to a second current source Iref2;
the first CCA output and second CCA output coupled to an AND gate forming an exclusive OR logical output.