Patent ID: 11936392
Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. A method for controlling a phase locked loop, comprising:
a multi-phase clock generation procedure for generating a plurality of feedback clock signals having different phases;
a feedback side frequency dividing procedure for dividing frequencies of the plurality of feedback clock signals and outputting the plurality of feedback clock signals as frequency-divided clock signals;
a reference clock latching procedure comprising:
holding the frequency-divided clock signals in synchronization with a predetermined reference clock signal and outputting a held value, and
outputting the held value as a fractional part code representing a fractional part of a phase difference between the reference clock signal and any of the plurality of feedback clock signals; and

a control procedure for controlling the frequencies of the plurality of feedback clock signals based on the held value, wherein the control procedure includes:
integrating a predetermined value in synchronization with any of the frequency-divided clock signals and to output an integrated value,
holding the reference clock signal in synchronization with any of the plurality of feedback clock signals and to output the reference clock signal as a retiming clock signal,
holding the integrated value in synchronization with the retiming clock signal and to output the held value as an integral part code representing an integral part of the phase difference,
obtaining a correction value for the phase difference representing the integral part code and the fractional part code, and
correcting the phase difference according to the correction value and to output phase difference information representing the corrected phase difference.