Patent ID: 11967389
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. A semiconductor apparatus comprising:
a plurality of memory banks divided into a plurality of bank groups, the plurality of bank groups including at least a first bank group and a second bank group;
a plurality of sense amplifiers configured to sense and amplify data output from memory banks connected to the plurality of sense amplifiers among the plurality of memory banks, and to transmit the amplified data;
a first storage circuit located outside the plurality of memory banks and directly connected to the plurality of sense amplifiers and configured to store data output from the plurality of sense amplifiers;
an error correction circuit configured to correct an error bit of data output from the plurality of memory banks;
a first sub-read path, one side terminals of the first sub-read path are connected to the first bank group and the first storage circuit in common and other side terminals of the first sub-read path are connected to the error correction circuit and activated in response to activation of one of a first control signal set and activation of a second control signal;
a second sub-read path, one side terminals of the second sub-read path are connected to the second bank group and the first storage circuit in common and other side terminals of the second sub-read path are connected to the error correction circuit and activated in response to activation of a remaining one of the first control signal set and the activation of the second control signal;
a second storage circuit connected to an output terminal of the error correction circuit and configured to store test data output from the error correction circuit by being activated in response to activation of a third control signal set; and
a control circuit configured to deactivate the first control signal set and the second control signal during a first sub-test section, and to sequentially activate the one of the first control signal set and the remaining one of the first control signal set during a second sub-test section.