Patent ID: 11869932
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. The manufacturing method according to claim 3, wherein depositing the lower electrode layer, the dielectric layer and the upper electrode layer in the capacitive holes to form the capacitive structure comprises:
forming the lower electrode layer on an inner surface of a side circumferential wall of each capacitive hole and a bottom surface of the capacitive hole, the lower electrode layer being connected to the bonding pad;
forming a third mask layer on a top of the capacitive hole, and forming third round hole patterns on the third mask layer;
removing a supporting layer on a top of part of side circumferential wall of the capacitive hole based on the third round hole patterns; and
etching the capacitive hole to remove a sacrificial layer between the lower electrode layers.