Patent ID: 11888486
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 13:
14. A phase interpolating device, comprising:
a decoder configured to generate a first control signal and a second control signal based on a phase difference of a clock signal and a reference signal;
a phase shift unit including a plurality of phase correction circuits connected in series; and
a phase select unit;
wherein each of the plurality of phase correction circuits includes:
a delay circuit configured to receive an input clock signal and to delay the input clock signal as much as a first delay time to output an output clock signal to an output node;
a first fine tuning circuit including a first terminal connected with the output node, a second terminal receiving the first control signal, and a third terminal; and
a second fine tuning circuit including a fourth terminal connected with the third terminal, a fifth terminal receiving the second control signal, and a sixth terminal connected with a load capacitor;

wherein, in response to the first control signal, the output clock signal is further delayed as much as a second delay time shorter than the first delay time;
wherein, in response to the second control signal, the output clock signal is advanced as much as a third delay time shorter than the first delay time; and
wherein the phase select unit is configured to determine whether to select, as a corrected clock signal, an output clock signal output from the delay circuit of each of the plurality of phase correction circuits, based on the phase difference.