Patent ID: 11972800
Assignee: EMEMORY TECHNOLOGY INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A non-volatile memory cell array comprising a first non-volatile memory cell, the first non-volatile memory cell comprising:
a first select transistor, wherein a first source/drain terminal of the first select transistor is connected with a program source line, and a gate terminal of the first select transistor is connected with a first program word line;
a first floating gate transistor, wherein a first source/drain terminal of the first floating gate transistor is connected with a second source/drain terminal of the first select transistor, and a second source/drain terminal of the first floating gate transistor is connected with a first program bit line;
a second floating gate transistor, wherein a first source/drain terminal of the second floating gate transistor is connected with a read source line, and a floating gate of the second floating gate transistor is connected with a floating gate of the first floating gate transistor; and
a second select transistor, wherein a first drain/source terminal of the second select transistor is connected with a second source/drain terminal of the second floating gate transistor, a gate terminal of the second select transistor is connected with a first read word line, and a second source/drain terminal of the second select transistor is connected with a first read bit line.