Patent ID: 11901019
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A non-volatile memory device, comprising:
a control circuit configured to connect to a plurality of bit lines each connected to a corresponding plurality of memory cells, the control circuit comprising:
a plurality of sense amplifiers each configured to read data from the memory cells connected to a corresponding one or more bit lines;
a plurality of sets of internal data latches, each set of internal data latches configured to store data associated with a corresponding one of the sense amplifiers;
a cache buffer comprising a plurality of sets of transfer data latches each corresponding to one of the sets of internal data latches; and
an input-output interface configured to provide data to an external data bus, the control circuit configured to:
perform a read operation by each of the sense amplifiers on a plurality of memory cells;
store results of the read operation by each of the sense amplifiers in the corresponding set of internal data latches;
compress the results of the read operation by each of the sense amplifiers within the corresponding set of internal data latches;
transfer the compressed results of the read operation from each of the set of internal data latches to a corresponding set of transfer data latches;
compact the compressed results of the read operation from the sets of transfer data latches into a smaller number of the sets of transfer latches; and
transfer the compacted compressed results of the read operation over the input-output interface to the external data bus.