Patent ID: 11860751
Assignee: SYNOPSYS, INC.
Field: Measurement (Instruments)
Classification: CPC G | IPC G

Claim 8:
9. A circuit, comprising:
a first circuit to receive, from an automated test equipment (ATE), test packets comprising test pattern data to test a design under test (DUT), wherein the test packets are received over a serializer/deserializer (SERDES) connection between the ATE and the DUT;
a second circuit to apply the test pattern data to the DUT using a set of scan chains and obtain test response data corresponding to the test pattern data;
a third circuit to receive the test response data at irregular time intervals; and
a fourth circuit to send response packets comprising a portion of the test response data to the ATE at regular time intervals, wherein the response packets are sent to the ATE over the SERDES connection.