Patent ID: 11955548
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 18:
19. A method of forming a FeFET device, comprising:
forming a lower metal layer of an interconnect structure over a substrate;
forming a stack of a gate electrode, a ferroelectric layer, and an oxide semiconductor (OS) channel layer one stacked over another over the lower metal layer, the OS channel layer having a first doping type;
forming a two-dimensional (2D) contacting layer along the OS channel layer, the 2D contacting layer having a second doping type different than the first doping type;
forming a pair of source/drain regions at one side of the 2D contacting layer opposite to the OS channel layer; and
forming an upper metal layer of the interconnect structure having metal vias contacting the pair of source/drain regions;
wherein the pair of source/drain regions has a bottom surface disposed on the 2D contacting layer.