Patent ID: 11869819
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A package structure, comprising:
a carrier substrate;
an integrated circuit component, disposed on the carrier substrate, wherein the integrated circuit component comprises:
a semiconductor substrate;
conductive pads, disposed on and electrically coupled to the semiconductor substrate, and each having a contact region and a testing region next to the contact region, wherein a surface roughness of a surface of the testing region of the at least one of the conductive pads is greater than a surface roughness of a surface of a respective one of the contact regions;
a passivation layer, disposed on the semiconductor substrate, wherein the testing regions and the contact regions of the conductive pads are exposed by the passivation layer; and
a post-passivation layer, disposed on the semiconductor substrate, wherein the testing regions of the conductive pads exposed by the passivation layer are covered by the post-passivation layer, and the contact regions of the conductive pads exposed by the passivation layer are exposed by the post-passivation layer; and

conductive vias, respectively disposed on the contact regions of the conductive pads, wherein the integrated circuit component is electrically connected to the carrier substrate through the conductive vias.