Patent ID: 11929419
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A device, comprising:
a semiconductive fin having source and drain regions and a channel region between the source and drain regions;
a gate feature over the channel region of the semiconductive fin;
a first spacer around and in contact with the gate feature;
source and drain features respectively in the source and drain regions of the semiconductive fin;
an interlayer dielectric layer around the first spacer;
a void between the first spacer and the interlayer dielectric layer; and
a contact stop layer having a first portion directly over the gate feature, a second portion directly over the first spacer, and a third portion directly over the void, wherein a bottom surface of the third portion of the contact stop layer is lower than a top surface of the first spacer; and
a contact etch stop layer between the first spacer and the interlayer dielectric layer, wherein a top surface of the contact etch stop layer is lower than a top surface of the interlayer dielectric layer.