Patent ID: 11894052
Assignee: STMICROELECTRONICS S.R.L.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An in-memory computation circuit, comprising:
a memory array including a plurality of memory cells arranged in a matrix with plural rows and plural columns, the memory cells storing computational weights for an in-memory compute operation, each row including a word line connected to the memory cells of the row, and each column including a bit line connected to the memory cells of the column;
a biasing circuit for each bit line comprising:
a first transistor and second transistor having source-drain paths connected in series between the bit line and a column output;
wherein said first transistor is configured to apply a fixed reference voltage level to said bit line;
wherein said second transistor is configured as a switching circuit and controlled to turn on for a time duration corresponding to coefficient data for said in-memory compute operation; and
wherein an analog signal at the column output is dependent on the coefficient data and computational weight; and

a column combining circuit configured to combine and integrate the analog signals generated at the column outputs of the biasing circuits.