Patent ID: 11875248
Assignee: IMAGINATION TECHNOLOGIES LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. A hardware implementation of a deep neural network comprising a plurality of layers arranged in a plurality of layer groups, the plurality of layer groups including at least a first layer group and a second layer group, each layer group comprising one or more consecutive layers of the neural network, wherein output data of the first layer group comprises input data for the second layer group, the hardware implementation comprising:
one or more first memory devices, configured to store input data for the first layer group, the input data comprising a multidimensional tensor including one or more traversed dimensions, being dimensions that are traversed by strides in at least one layer of the first layer group, and one or more non-traversed dimensions;
one or more second memory devices, configured to store the output data of at least the first layer group;
a plurality of cores, comprising at least a first core and a second core; and
a splitter unit,
wherein the splitter unit is configured to determine a size of the input data in a first dimension among the one or more traversed dimensions, and
if the size in the first dimension is greater than a threshold,
the splitter unit is configured to split the input data for the first layer group into at least a first tile and a second tile, along the first dimension, each tile comprising a plurality of data elements in each of the one or more traversed dimensions,
the first core is configured to evaluate the first layer group based on the first tile, to generate a first output tile of the first layer group,
the second core is configured to evaluate the first layer group based on the second tile, to generate a second output tile of the first layer group,
the first core and the second core are configured to store said first output tile and said second output tile of the first layer group in the one or more second memory devices, as input data for the second layer group,
the first core is configured to evaluate the second layer group based on the first output tile of the first layer group, to generate a first output tile of the second layer group, and
the second core is configured to evaluate the second layer group based on the second output tile of the first layer group, to generate a second output tile of the second layer group,

and, if the size in the first dimension is not greater than the threshold,
the splitter unit is configured to split the evaluation of the first layer group into at least a first pass and a second pass, along a dimension other than the first dimension,
the first core is configured to evaluate the first layer group for the first pass, to generate a first portion of output data,
the second core is configured to evaluate the first layer group for the second pass, to generate a second portion of output data, each of said first portion of output data and said second portion of output data comprising a plurality of data elements,
the plurality of cores is configured to produce the output data of the first layer group, comprising combining the first portion of output data and the second portion of output data, and
the plurality of cores is configured to store the output data of the first layer group in the one or more second memory devices, as input data for the second layer group.