Patent ID: 11899584
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 1:
2. The system of claim 1, wherein the processor is configured such that the cache hit ratio for the cache memory includes at least one of: during a preset time period, (1) a ratio of a size of data in the cache memory that is accessed by the processor to a total size of data in the random access memory or the cache memory that is accessed by the processor; (2) a ratio of a number of data accesses by the processor to the cache memory to a total number of data accesses by the processor to the random access memory or the cache memory; or (3) a ratio of a number of data accesses by the processor to the cache memory to a total number of data retrieves from the cache memory.