Patent ID: 11862635
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of fabricating an integrated circuit structure, the method comprising:
forming a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate, the nanowires of the second vertical arrangement of nanowires having a horizontal width greater than a horizontal width of the nanowires of the first vertical arrangement of nanowires;
forming first epitaxial source or drain structures at ends of the first vertical arrangement of nanowires, and forming second epitaxial source or drain structures at ends of the second vertical arrangement of nanowires, ones of the second epitaxial source or drain structures and corresponding ones of the first epitaxial source or drain structures having a laterally merged region there between;
removing the laterally merged region to disjoin the ones of the second epitaxial source or drain structures and the corresponding ones of the first epitaxial source or drain structures; and
forming an intervening dielectric structure between the ones of the second epitaxial source or drain structures and the corresponding ones of the first epitaxial source or drain structures.