Patent ID: 11881486
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A method of fabricating an integrated circuit structure, the method comprising:
forming a first transistor comprising:
forming a gate electrode over a three-dimensional semiconductor body, the gate electrode having a first side opposite a second side;
forming a first gate dielectric between the three-dimensional semiconductor body of the first transistor and the gate electrode of the first transistor, wherein the first gate dielectric comprises a first high-k dielectric layer, and wherein the first high-k dielectric layer is further along the first side and the second side of the gate electrode of the first transistor;
forming a first source or drain region at the first side of the gate electrode; and
forming a second source or drain region at the second side of the gate electrode; and
forming a second transistor, the forming comprising:
forming a gate electrode over a three-dimensional semiconductor body, the gate electrode having a first side opposite a second side;
forming a second gate dielectric between the three-dimensional semiconductor body of the second transistor and the gate electrode of the second transistor, wherein the second gate dielectric comprises a second high-k dielectric layer, and wherein the second high-k dielectric layer is further along the first side and the second side of the gate electrode of the second transistor;
forming a first source or drain region at the first side of the gate electrode of the first transistor; and
forming a second source or drain region at the second side of the gate electrode;

forming a first dielectric spacer adjacent to and in direct contact with the first high-k dielectric layer along the first side of the gate electrode, the first dielectric spacer having a first lateral thickness;
forming a second dielectric spacer adjacent to and in direct contact with the first high-k dielectric layer along the second side of the gate electrode, the first dielectric spacer having the first lateral thickness;
forming a third dielectric spacer adjacent to and in direct contact with the second high-k dielectric layer along the first side of the gate electrode of the second transistor, the third dielectric spacer having a second lateral thickness, the second lateral thickness less than the first lateral thickness;
forming a fourth dielectric spacer adjacent to and in direct contact with the second high-k dielectric layer along the second side of the gate electrode of the second transistor, the fourth dielectric spacer having the second lateral thickness;
forming a first conductive contact on the first source or drain region of the first transistor, wherein the first conductive contact is not in contact with the first dielectric spacer;
forming a second conductive contact on the second source or drain region of the first transistor, wherein the second conductive contact is not in contact with the second dielectric spacer;
forming a third conductive contact on the first source or drain region of the second transistor, wherein the third conductive contact is in direct contact with the third dielectric spacer; and
forming a fourth conductive contact on the second source or drain region of the second transistor, wherein the fourth conductive contact is in direct contact with the fourth dielectric spacer.