Patent ID: 11954063
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 20:
21. A parallel processing unit comprising:
a first processing cluster to perform parallel processing operations, the first processing cluster including a ray tracing core to perform a ray tracing operation and a matrix processing core to perform a matrix multiply operation; and
a second processing cluster coupled to the first processing cluster, the second processing cluster including a processing core configured to process an instruction, wherein the instruction is a single instruction multiple data (SIMD) instruction having multiple operands and configured to use a bfloatl6 (BF16) number format, the processing core including a floating-point unit to perform floating point operations on input included in the multiple operands, the floating point unit including a multiplier to multiply second and third input while an accumulator adds a first input with output from the multiplier.