Patent ID: 11907005
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G  H

Claim 6:
7. The multi-core system of claim 4, wherein the synchronization circuit includes:
an OR gate configured to generate a busy signal by performing an OR logic operation on a plurality of core busy signals where each of the plurality of core busy signal is activated when a frequency of each of the plurality of core clock signals is changed;
a first flip-flop circuit configured to generate a first enable signal by synchronizing the busy signal with the second clock signal;
a second flip-flop circuit configured to generate a second enable signal by synchronizing the first enable signal with the first clock signal; and
a multiplexer configured to generate the clock gating signal by selecting one of the first enable signal and the second enable signal based on the busy signal.