Patent ID: 11928018
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. An apparatus, comprising:
a receiver configured to receive, from a memory device, a set of data and an indication of whether a first error management procedure performed by the memory device on the set of data detected one or more errors in the set of data;
an error management component configured to perform a second error management procedure on the set of data received from the memory device;
logic configured to receive the indication and a result of the second error management procedure and to output, based at least in part on the indication and the result of the second error management procedure, a plurality of bits indicating whether one or more errors associated with the set of data were detected at the memory device, a host device comprising the error management component, or both; and
a controller configured to validate or discard the set of data based at least in part on the plurality of bits and to perform an operation.