Patent ID: 11874793
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus, comprising:
a plurality of processing tiles, wherein individual processing tiles to comprise one or more processing units; and
an interconnect to electronically couple individual processing tiles of the plurality of processing tiles to two or more other processing tiles of the plurality of processing tiles;
wherein a particular processing tile of the plurality of processing tiles to comprise a broadcast hub, wherein the broadcast hub to:
obtain a plurality of parameters applicable to a particular operation from at least one of the plurality of processing tiles; and
initiate distribution, via broadcast communication, of the plurality of parameters applicable to the particular operation from the broadcast hub to the plurality of processing tiles, wherein routing of the plurality of parameters applicable to the particular operation as the plurality of parameters applicable to the particular operation traverse individual processing tiles is performed in accordance with a programmable vertical-first or horizontal-first rule;
wherein the plurality of processing tiles to execute the particular operation based at least in part on the plurality of distributed parameters applicable to the particular operation.