Patent ID: 11862271
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A method, comprising:
identifying memory having an array of bitcells;
selecting a row in the array of bitcells for error correction;
writing a first row data sequence to the row;
reading a second row data sequence from the row after writing the first row data sequence to the row;
checking the second row data sequence for a number of errors by comparing the first row data sequence to the second row data sequence;
accumulating a row error count by increasing a row error counter by the number of errors;
writing a third row data sequence to the row;
reading a fourth row data sequence from the row after writing the third row data sequence to the row;
checking the fourth row data sequence for the number of errors by comparing the third row data sequence to the fourth row data sequence;
accumulating the row error count by increasing the row error counter by the number of errors;
storing a row address associated with the row in a repair register for repair using row redundancy if the number of errors in the row error count is greater than a predetermined number of errors; and
relying on error correction coding (ECC) to repair the number of errors in the row if the number of errors in the row error count is less than or equal to the predetermined number of errors.