Patent ID: 11895821
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 5:
6. The method of claim 2, after etching the top of each of the first patterns, further comprising:
forming a bit line mask layer on a side surface of the protrusion;
by taking the bit line mask layer and the protrusion as a mask, etching each second main body to obtain two corresponding adjacent third main bodies, and to simultaneously obtain a gap between the two corresponding adjacent third main bodies, so as to expose a part of the substrate;
removing the bit line mask layer and the protrusion to expose upper surfaces of the third main bodies;
forming a third flank wall on each of opposite sidewalls between the two corresponding adjacent third main bodies; and
removing the filling layer to expose the second flank wall.