Patent ID: 11908790
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for forming a chip structure, comprising:
forming a conductive line over a substrate;
forming a first passivation layer over the substrate and the conductive line;
forming a first through hole and a second through hole in the first passivation layer over the conductive line to expose first portions of the conductive line;
forming a first conductive via structure, a second conductive via structure, and a conductive pad over the conductive line, wherein the first conductive via structure and the second conductive via structure are respectively in the first through hole and the second through hole, the conductive pad is over the first conductive via structure, the second conductive via structure, and the first passivation layer, the conductive pad is thicker and wider than the conductive line, and the conductive pad has a curved top surface;
forming a second passivation layer over the first passivation layer and the conductive pad, wherein the second passivation layer has an opening exposing a second portion of the conductive pad, the second passivation layer conformally and continuously covers a first top surface and a sidewall of the conductive pad, and the first top surface is higher than a second top surface of a portion of the second passivation layer covering the first passivation layer; and
forming a conductive pillar over the conductive pad, wherein the conductive pillar is over the second passivation layer and fills the opening, and the conductive pillar has a curved bottom surface facing the curved top surface of the conductive pad.