Patent ID: 11971826
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A non-volatile memory device, comprising:
a control circuit configured to connect to a plurality of planes of non-volatile memory cells, the control circuit comprising:
a plurality of cache buffers each configured to store data read from a corresponding one of the planes;
an input-output interface configured to provide data to an external data bus;
an internal data bus having a plurality segments, including a first segment configured to transfer data between a first cache buffer corresponding to a first of the planes and the input-output interface and a second segment configured to transfer data between a second cache buffer corresponding to a second of the planes and the input-output interface;
a first compression circuit configured to compress data received from the first segment and,
a second compression circuit configured to compress data received from the second segment,

the control circuit configured to:
read a first page of hard bit data and corresponding first soft bit data from the first plane and store the read first page of hard bit data and first soft bit data in the first cache buffer;
read a second page of hard bit data and corresponding second soft bit data from the second plane and store the read second page of hard bit data and second soft bit data in the second cache buffer;
transfer the first soft bit data over the first segment from the first cache buffer to the first compression circuit, compress the transferred first soft bit data in the first compression circuit, transfer the compressed first soft bit data over the first segment from the first compression circuit to the first cache buffer, and store the compressed first soft bit data in the first cache buffer; and
transfer the second soft bit data over the second segment from the second cache buffer to the second compression circuit, compress the transferred second soft bit data in the second compression circuit, transfer the compressed second soft bit data over the second segment from the second compression circuit to the second cache buffer, and store the compressed second soft bit data in the second cache buffer, where one or both of transferring the first soft bit data from the first cache buffer to the first compression circuit and transferring the compressed first soft bit data over the first segment from the first compression circuit to the first cache buffer is performed concurrently with the transferring of data from the second cache buffer over the second segment.