Patent ID: 11972832
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 12:
13. The command decoder circuit of claim 12, wherein the enable signal generation unit comprises:
an OR gate, configured to determine an OR signal of the second command signal and the timing signal;
a first AND gate, configured to determine an AND signal of the first command signal and an AND signal output by a second AND gate;
the second AND gate, configured to determine an AND signal of the OR signal and the AND signal output by the first AND gate; and
a NOT gate, configured to use a NOT signal of the AND signal output by the first AND gate as the enable signal; and wherein
the clock gate is an AND gate, configured to determine an AND signal of the system clock signal, the enable signal, and the chip select signal as the dynamic clock signal.