Patent ID: 11917831
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. An integrated chip comprising:
a substrate;
an interconnect structure overlying the substrate and comprising a plurality of wires and a plurality of vias, wherein the plurality of wires and the plurality of vias are grouped respectively into a plurality of wire levels and a plurality of via levels that are alternatingly stacked; and
a memory cell in and electrically coupled to the interconnect structure, wherein the memory cell comprises:
a first electrode;
a ferroelectric layer overlying the first electrode;
a second electrode overlying the ferroelectric layer; and
a seed layer between and directly contacting the first electrode and the ferroelectric layer;

an additional memory cell in and electrically coupled to the interconnect structure, and comprising an additional seed layer;
a first etch stop layer overlying and directly contacting the memory cell and the additional memory cell; and
a second etch stop layer spaced from and underlying the first etch stop layer, wherein the second etch stop layer is on sidewalls of the additional seed layer and comprises a same material as the first etch stop layer;
wherein the seed layer and the first electrode have a shared width, wherein the plurality of wires comprises a first wire, which underlies and directly contacts the first electrode with a width less than the shared width, wherein the plurality of vias comprises a first via, which extends from a bottom of the first wire with a width less than the width of the first wire, wherein at least 35 percent of the seed layer is in an orthorhombic phase, wherein at least 35 percent of the ferroelectric layer is in the orthorhombic phase, and wherein the plurality of wires comprises a second wire, which is level with the first wire and which underlies and directly contacts the additional seed layer.