Patent ID: 11972230
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A method comprising:
decoding an instruction having a format including an opcode field to specify an opcode, a first destination operand field to specify a destination matrix location, a first source operand field to specify a first source matrix location, and a second source operand field to specify a second source matrix location; and
executing the decoded instruction, wherein executing includes transposing a first source matrix from the first source matrix location to generate a transposed first source matrix, performing a matrix multiplication using the transposed first source matrix and a second source matrix from the second source matrix location to generate a result, and storing the result in a destination matrix location, and wherein executing is restartable at a stored start row value corresponding to a row of at least one of the destination matrix, the first source matrix, and the second source matrix.