Patent ID: 11886295
Assignee: PURE STORAGE, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A system comprising:
a plurality of storage devices; and
a storage controller comprising a processing device operatively coupled to the plurality of storage devices, the processing device configured to:
determine that two parity shards of an N+2 erasure coded stripe stored at two of the plurality of storage devices differ from expected values of the two parity shards calculated from remaining data shards of the N+2 erasure coded stripe;
determine that a stored value for a particular data shard of the remaining data shards differs from an expected value for the particular data shard calculated using erasure codes from other remaining data shards of the remaining data shards and a first parity shard of the two parity shards; and
utilize the expected value for the particular data shard calculated using the erasure code as a corrected value for the particular data shard.