Patent ID: 11948797
Assignee: MITSUBISHI ELECTRIC CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 4:
5. A method for manufacturing a semiconductor device comprising:
applying a lower resist on a semiconductor substrate;
applying an upper resist which is an image reversal resist on the lower resist;
preventing a first region of the upper resist from being exposed by covering the first region with a mask and exposing a second region of the upper resist;
after exposing the second region, applying a shrink agent on the upper resist;
performing baking to cause cross-linking reaction between free acid in a resist upper portion of the second region and the shrink agent and to cause thermal cross-linking reaction of free acid in a resist lower portion of the second region;
after the baking, exposing the first region by whole surface exposure;
after the whole surface exposure, removing the shrink agent, the resist upper portion of the second region and the first region of the upper resist by development to form a first opening and dissolving the lower resist with a developer upon the development to form a second opening having a width wider than that of the first opening below the first opening so that a resist pattern in a shape of an eave having an undercut is formed;
forming a metal film on the resist pattern and on the semiconductor substrate exposed at the second opening; and
removing the resist pattern and the metal film on the resist pattern and leaving the metal film on the semiconductor substrate as an electrode.