Patent ID: 11895224
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Digital communication (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 12:
13. A crypto processor, the crypto processor comprising:
an encryptor configured to encrypt input data to plural lattice-based texts;
a multiplexer configured to multiplex coefficients of polynomials of the plural lattice-based texts, to selectively provide the multiplexed coefficients to plural multipliers,
input registers configured to respectively store the selectively provided multiplexed coefficients;
the plural multipliers;
an adder; and
output registers configured to store a lattice-based text result for a homomorphic operation with respect to the multiplexed coefficients that is based on results of configured respective parallel operating of the plural multipliers and a result of the adder,
wherein the operating of the plural multipliers includes an operating of a first multiplier, of the plural multipliers, provided a first portion of the multiplexed coefficients, an operating of a second multiplier, of the plural multipliers, provided a second portion of the multiplexed coefficients, and a selective operating of the adder provided some results of the operated plural multipliers.