Patent ID: 11901311
Assignee: MACRONIX INTERNATIONAL CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A memory device, comprising:
a substrate comprising a first region and a second region;
a conductive layer over the substrate in the first region and the second region, wherein the conductive layer has a first slit trench along a first direction in a region between the first region and the second region;
a stacked structure on the conductive layer, wherein the stacked structure comprises a first staircase structure in the first region and a second staircase structure in the second region;
a dielectric layer overlaying the first staircase structure and the second staircase structure, and filling into the first slit trench, wherein the dielectric layer filled in the first slit trench forms a first slit along the first direction; and
multiple second slits along a second direction perpendicular to the first direction extending from a top surface of the dielectric layer through the stacked structure to a bottom surface of the conductive layer in the first region and the second region.