Patent ID: 11893243
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. In a storage system comprising a memory comprising memory cells configured to store X number of bits per memory cell, wherein X is a positive integer, wherein the memory is organized into a plurality of wordlines, wherein each wordline comprises a plurality of programming segments, and wherein the memory comprises a plurality of memory dies organized in a stripe, a method comprising:
changing, in each memory die in the stripe, which of the plurality of programming segments is a last programming segment programmed;
observing a pattern showing that an error repeatedly occurred on a certain programming segment of the plurality of programming segments;
based on the observed pattern, selecting the certain programming segment to be the last programming segment programmed;
detecting a number of program disturb errors in the memory; and
correcting the program disturb errors using the error correction operation.