Patent ID: 11886377
Assignee: CORNAMI, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G  H

Claim 35:
36. A reconfigurable arithmetic circuit comprising:
a plurality of input reordering queues;
a multiplier shifter and combiner network, the multiplier shifter and combiner network comprising:
a shifter circuit; and
a plurality of series-coupled adder circuits coupled to the shifter circuit;

a configurable multiplier having a plurality of operating modes, the configurable multiplier coupled to the plurality of input reordering queues and to the multiplier shifter and combiner network, the plurality of operating modes comprising a fixed point operating mode and a floating point operating mode, wherein the configurable multiplier has a native operating mode of a 27×27 unsigned multiplier further configurable to process signed inputs, the configurable multiplier further configurable as four 8×8 multipliers, two 16×16 single-instruction multiple-data (SIMD) multipliers, one 32×32 multiplier, and one 54×54 multiplier;
an accumulator circuit; and
at least one control logic circuit coupled to the multiplier shifter and combiner network and to the accumulator circuit.