Patent ID: 11972828
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 7:
8. A memory, comprising:
a normal memory area;
a redundant memory area, comprising a target repair unit immediately adjacent to the normal memory area;
a row address receiving end, configured to receive a row address input to the memory; and
a repair circuit, configured to control the target repair unit to repair an abnormal memory cell in the normal memory area,
wherein the repair circuit comprises:
a first control circuit, configured to receive signals at a target number of bits from low to high in a row address, process the signals at the target number of bits to obtain a control result, and output the control result, wherein the target number is associated with a number of Word Lines (WLs) in the target repair unit; and
a repair determination circuitry, connected to an output terminal of the first control circuit, and configured to receive the control result and output, in combination with the control result, a repair signal indicating whether to perform a repair operation,
wherein the target repair unit comprises a plurality of WLs, and is configured to:
replace WLs corresponding to the abnormal memory cell with remaining WLs of the plurality of WLs other than a first WL of the plurality of WLs in the target repair unit, wherein the first WL in the target repair unit is a WL adjacent to the normal memory area; and
retain a first WL of the WLs corresponding to the abnormal memory cell, the first WL of the WLs corresponding to the abnormal memory cell being a WL more adjacent to the target repair unit than remaining WLs of the WLs corresponding to the abnormal memory cell, wherein the first WL of the WLs corresponding to the abnormal memory cell is not damaged.