Patent ID: 11894066
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 9:
10. A semiconductor memory device comprising:
a plurality of memory cells connected to a selected word line;
a plurality of page buffers configured to perform a sensing operation on each of the plurality of memory cells, wherein each of the plurality of memory cells stores N bit of data; and
control logic configured to control an operation of the plurality of page buffers,
wherein each of the plurality of page buffers comprises:
at least one data latch connected to a sense out node and storing bit data; and
a sensing latch connected to the sense out node and storing bit data indicating whether a threshold voltage of a corresponding memory cell among the plurality of memory cells is greater than a selected read voltage during a sensing operation,
the at least one data latch stores bit data programmed to the corresponding memory cell, and
the control logic selects a target state, in which a threshold voltage distribution is to be detected, from among an erase state and first to (2N-1)-th program states, wherein Nis a natural number, and controls each of the plurality of page buffers to apply masking of the target state to the bit data stored in the sensing latch, based on the bit data stored in the at least one data latch.