Patent ID: 11948638
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 20:
21. The apparatus of claim 20, further comprising:
a plurality of bit line drivers coupled with the plurality of bit lines, wherein a first subset of the plurality of bit line drivers are configured to:
bias a first subset of the plurality of bit lines according to a first sequence of voltages during the first duration, the second duration, the third duration, or a combination thereof, wherein the at least one memory cell of the first subset of the first tier of memory cells thresholds and is written to the first logic state based at least in part on biasing the first subset of the plurality of bit lines according to the first sequence of voltages; and

wherein a second subset of the plurality of bit line drivers are configured to:
bias a second subset of the plurality of bit lines according to a second sequence of voltages during the first duration, the second duration, the third duration, or a combination thereof, wherein the at least one memory cell of the second subset of the first tier of memory cells thresholds and is written to the second logic state based at least in part on biasing the second subset of plurality of bit lines according to the second sequence of voltages.