Patent ID: 11956946
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 9:
10. The method of forming the semiconductor structure according to claim 1, wherein the step of forming the bit line layer on the bit line contact layer comprises:
depositing a diffusion barrier material on the surface of the bit line contact layer and the surface of the substrate isolation layer to form an initial diffusion barrier layer;
depositing a second conductive material on a surface of the initial diffusion barrier layer to form an initial bit line layer;
depositing a cap layer material on a surface of the initial bit line layer to form an initial bit line cap layer;
forming a second mask layer on the initial bit line cap layer, wherein the second mask layer comprises a second etching window for exposing the initial bit line cap layer; and
etching the initial bit line cap layer, the initial bit line layer, and the initial diffusion barrier layer along the second etching window to form a diffusion barrier layer on the bit line contact layer, a bit line layer on the diffusion barrier layer, and a bit line cap layer on the bit line layer.