Patent ID: 11942035
Assignee: WUHAN TIANMA MICROELECTRONICS CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. The method according to claim 11, wherein
the display panel further comprises a second scanning driving circuit, wherein the second scanning driving circuit comprises second scanning driving unit groups that are cascaded, wherein each second scanning driving unit group of the second scanning driving unit groups comprises B second scanning driving units that are cascaded; the B second scanning driving units in one second scanning driving unit group of the second scanning driving unit groups comprise an m-th stage second scanning driving unit and an n-th stage second scanning driving unit, where m and n are both integers, and 1≤m<n≤B, wherein an output terminal of the m-th stage second scanning driving unit is electrically connected to the data writing control terminal of the first pixel driving circuit, and an output terminal of the n-th stage second scanning driving unit is electrically connected to the data writing control terminal of the second pixel driving circuit;
wherein the B second scanning driving units comprise a clock terminal of the m-th stage second scanning driving unit and a clock terminal of the n-th stage second scanning driving unit, and the display panel further comprises B types of clock signal lines, wherein the B types of clock signal lines comprise an m-th type clock signal line and an n-th type clock signal line, wherein the m-th type clock signal line is electrically connected to the clock terminal of the m-th stage second scanning driving unit, and the n-th type clock signal line is electrically connected to the clock terminal of the n-th stage second scanning driving unit; and
wherein said controlling the turned-on duration of the data writing transistor in the first pixel driving circuit to be shorter than the turned-on duration of the data writing transistor in the second pixel driving circuit comprises:
controlling a period of an effective level transmitted by the m-th type clock signal line to be shorter than a period of an effective level transmitted by the n-th type clock signal line.