Patent ID: 11936378
Assignee: CHONGQING GIGACHIP TECHNOLOGY CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. The interface circuit according to claim 12, wherein each of the plurality of output driving modules comprises a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, and a twelfth transistor M12, wherein a gate of the seventh transistor M7 is connected to a first bias voltage Vb1, a gate of the eighth transistor Mg is connected to a second bias voltage Vb2, a source of the seventh transistor M7 is connected to a power supply, and a source of the eighth transistor M8 is grounded; gates of the ninth transistor M9 and the tenth transistor M10 are connected to a first digital input logic level D+, and gates of the eleventh transistor Mu and the twelfth transistor M11 are connected to a second digital input logic level D−; a drain of the seventh transistor M7 is connected to sources of the ninth transistor M9 and the eleventh transistor M11, respectively, and a drain of the eighth transistor M8 is connected to sources of the tenth transistor M10 and the twelfth transistor M12, respectively; a first output end Dout+ of the output driving module is connected to drains of the eleventh transistor M11 and the twelfth transistor M12, a second output end Dout− of the output driving module is connected to drains of the ninth transistor Mg and the tenth transistor M10, and a signal amplitude between the first output end Dout+ and the second output end Dout− is:

[(Dout+)−(Dout−)]=(VdH−VdL)=(VH−VL)

wherein VH is the high level voltage, VL is the low level voltage, and (VdH−VdL) is the output signal amplitude of the driving bias generation circuit.