Patent ID: 11947460
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus comprising:
a cache providing a plurality of cache lines and associated address indication entries, each cache line arranged to store a block of data and the associated address indication entry arranged, by default, to store a memory address indication for the block of data;
cache access control circuitry, responsive to an access request issued by at least one processing element and indicating a target memory address, to determine whether a hit condition is present in the cache, the hit condition being present when a given cache line is determined, with reference to the memory address indication stored in the associated address indication entry, to store data associated with the target memory address; and
cache configuration control circuitry to set, in response to detecting a merging trigger event, merge indication state to identify multiple cache lines amongst the plurality of cache lines that are to be treated as a merged cache line to store multiple blocks of data,
wherein:
when the merge indication state indicates that the given cache line is part of the merged cache line, the cache access control circuitry is responsive to detecting the hit condition to allow access to any of the data blocks stored in the multiple cache lines forming the merged cache line;
the merging trigger event comprises one of a set of merging trigger events; and
the set of merging trigger events comprises at least one of:
a request from the at least one processing element to merge the multiple cache lines to form the merged cache line;
a determination that a pattern of previous accesses to the multiple cache lines meets at least one criterion; and
a determination that the at least one processing element is of a given type.