Patent ID: 11955496
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. An integrated circuit, comprising:
an image sensing die having a plurality of pixel regions respectively comprising a photodiode configured to convert radiation that enters the image sensing die from a back-side into an electrical signal, the photodiode comprising a photodiode doping column with a first doping type surrounded by a photodiode doping layer with a second doping type that is different than the first doping type;
a back-side deep trench isolation (BDTI) structure disposed between adjacent pixel regions and extending from the back-side of the image sensing die to a position within the photodiode doping layer, wherein the BDTI structure comprises a doped liner with the second doping type and a dielectric fill layer, the doped liner lining a sidewall surface of the dielectric fill layer;
a doped isolation well with the second doping type disposed between the adjacent pixel regions and extending from a front-side of the image sensing die opposite to the back-side to a position within the photodiode doping layer;
a metallization stack arranged on the front-side and comprising a plurality of metal interconnect layers arranged within an inter-level dielectric layer; and
a logic die bonded to the front-side of the image sensing die, the logic die comprising logic devices,
wherein the doped liner is formed under a protection layer followed by removing the protection layer prior to forming the dielectric fill layer to reduce a surface concentration of the doped liner to be smaller than 1E19/cm2.