Patent ID: 11861328
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A system for performing computations by a neural network, the system comprising:
a processing circuit comprising:
a first multiplier;
a second multiplier; and
a third multiplier,

the processing circuit being configured to:
identify a first plurality of weights having a first arrangement;
generate a first set of products, each product of the first set of products being an integer product of a first activation value and a respective weight of a first plurality of weights;
generate a second set of products, each product of the second set of products being a floating-point product of a second activation value and a respective weight of a second plurality of weights; and
output at least one of the first set of products or the second set of products for use by the neural network,

each of the weights of the first plurality of weights including a least significant sub-word and a most significant sub-word,
the most significant sub-word of a first weight of the first plurality of weights being nonzero,
the most significant sub-word of a second weight of the first plurality of weights being zero,
wherein in generating the first set of products, the processing circuit is configured to:
process the first plurality of weights to have a second arrangement different from the first arrangement;
store the first plurality of weights arranged according to the second arrangement into a first memory space;
multiply, in the first multiplier, the first activation value by the least significant sub-word of the first weight stored in the first memory space to form a first partial product;
multiply, in the second multiplier, the first activation value by the least significant sub-word of the second weight stored in the first memory space;
multiply, in the third multiplier, the first activation value by the most significant sub-word of the first weight to form a second partial product; and
add the first partial product and the second partial product;

wherein in generating the second set of products, the processing circuit is configured to generate a first floating point product,
wherein in generating the first floating point product, the processing circuit is configured to multiply, in the first multiplier, a first sub-word of a mantissa of the second activation value by a first sub-word of a mantissa of a first weight of the second plurality of weights, to generate a third partial product.