Patent ID: 11967365
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A device comprising:
a memory cell having logic and passgates, wherein the logic is configured to store data, and wherein the passgates are coupled to the logic and configured to access the data stored in the logic; and
a first number of input-output ports that are time-multiplexed with wordlines and bitlines coupled to the passgates so as to increase the first number of input-output ports to a second number of input-output ports that is greater than the first number of input-output ports,
wherein the passgates include a first write passgate and a second write passgate with outputs coupled together, wherein the passgates include a third write passgate and a fourth write passgate with outputs coupled together, wherein the wordlines include first write wordlines coupled to the first write passgate, wherein the wordlines include second write wordlines coupled to the second write passgate, wherein the wordlines include third write wordlines coupled to the third write passgate, and wherein the wordlines include fourth write wordlines coupled to the fourth write passgate.