Patent ID: 11929130
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A device for testing a self refresh (SR) cycle used for a memory, comprising:
a data obtaining module configured to execute a preset number of data-retention-capacity acquisition steps, the data-retention-capacity acquisition steps including determining a preset refresh time, send an SR entry command to control the memory to enter an SR operation, send an SR exit command to control the memory to exit the SR operation after the memory executes SR for the preset refresh time, and detect a current data retention capacity of the memory; and
a data processing module configured to obtain a cycle of a function of a data retention capacity with respect to a corresponding preset refresh time, and determine the SR cycle of the memory with the cycle of the function;
wherein the data obtaining module is further configured, in response to detecting the current data retention capacity of the memory, to:
perform a data reading step, the data reading step comprising determining a preset waiting time;
wait for the preset waiting time after the memory executes the SR for the preset refresh time;
read data of the memory after waiting for the preset waiting time;
when the data is successfully read, increment the preset waiting time and proceed to the data reading step; and
when the data is not successfully read, determine a previous preset waiting time as the data retention capacity, wherein the previous preset waiting time is a previous longest preset waiting time in which the data may be read successfully.