Patent ID: 11960735
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. An apparatus, comprising:
a first memory controller coupled to a first memory device, wherein a first memory address range, reserved for a portion of a first data type, is allocated to the first memory device;
a second memory controller coupled to a second memory device, wherein a second memory address range, reserved for a portion of a second data type, is allocated among the first memory device and the second memory device; and
a memory manager configured to:
determine a data type associated with a first access request;
determine a data type associated with a second access request;
utilize the first memory controller to execute the first access request and utilize the second memory controller to execute the second access request in parallel, responsive to a determination that the first access request is associated with the first data type and responsive to a determination that the second access request is not directed to the first memory device; and
utilize the first memory controller and the second memory controller to execute the first access request responsive to a determination that the first access request is associated with the second data type.