Patent ID: 11881483
Assignee: ICOMETRUE COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 13:
14. A multi-chip package comprising:
an interconnection substrate comprising a silicon substrate and an interconnection scheme over the silicon substrate, wherein the interconnection scheme comprises a first interconnection metal layer over the silicon substrate, a second interconnection metal layer over the silicon substrate, an insulating dielectric layer between the first and second interconnection metal layers, a first silicon-oxide-containing layer over the interconnection scheme and at a top of the interconnection substrate, and first and second copper pads over the interconnection scheme and at the top of the interconnection substrate, wherein the first and second copper pads are respectively in first and second openings in the first silicon-oxide-containing layer and each of the first and second copper pads couples to the interconnection scheme, wherein each of the first and second copper pads has a top surface coplanar with a top surface of the first silicon-oxide-containing layer, wherein the first interconnection metal layer comprises a first copper layer and a first adhesion metal layer at a sidewall and bottom of the first copper layer;
a metal contact at a bottom of the multi-chip package;
a first semiconductor integrated-circuit (IC) chip over the interconnection substrate, wherein the first semiconductor integrated-circuit (IC) chip comprises a second silicon-oxide-containing layer and third copper pad both at a bottom of the first semiconductor integrated-circuit (IC) chip, wherein the third copper pad is in a third opening in the second silicon-oxide-containing layer, wherein a bottom surface of the second silicon-oxide-containing layer is bonded to and in contact with a top surface of the first silicon-oxide-containing layer, and a bottom surface of the third copper pad is bonded to and in contact with a top surface of the first copper pad, wherein the first semiconductor integrated-circuit (IC) chip couples to the interconnection substrate through the first and third copper pads; and
a second semiconductor integrated-circuit (IC) chip over the interconnection substrate and at a same horizontal level as the first semiconductor integrated-circuit (IC) chip, wherein the second semiconductor integrated-circuit (IC) chip comprises a third silicon-oxide-containing layer and fourth copper pad both at a bottom of the second semiconductor integrated-circuit (IC) chip, wherein the fourth copper pad is in a fourth opening in the third silicon-oxide-containing layer, wherein a bottom surface of the third silicon-oxide-containing layer is bonded to and in contact with a top surface of the first silicon-oxide-containing layer, and a bottom surface of the fourth copper pad is bonded to and in contact with a top surface of the second copper pad, wherein the second semiconductor integrated-circuit (IC) chip couples to the interconnection substrate through the second and fourth copper pads, wherein the first semiconductor integrated-circuit (IC) chip comprises an input/output (I/O) circuit having a driving capability smaller than 1 pF and coupling to the second semiconductor integrated-circuit (IC) chip through the interconnection substrate.