Patent ID: 11956944
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 2:
3. The semiconductor structure formation method according to claim 1, wherein the step of removing, in the dummy region, part of height of the first bitline structure, part of height of the first dielectric layer and part of height of the first sacrificial layer to form a first opening located at top of a second bitline structure, a second dielectric layer and a second sacrificial layer comprises:
forming, in the contact region, a mask layer located on top surfaces of the first bitline structure, the first dielectric layer and the first sacrificial layer; and
etching, based on the mask layer, the part of the height of the first bitline structure, the part of height of the first dielectric layer and the part of the height of the first sacrificial layer in the dummy region to form the second bitline structure, the second dielectric layer, the second sacrificial layer and the first opening.