Patent ID: 11940483
Assignee: TEKTRONIX, INC.
Field: Measurement (Instruments)
Classification: CPC G | IPC G  H

Claim 14:
15. A method for electrical margin testing a device under test (DUT), the method comprising:
coupling the DUT to a plurality of lanes of a margin tester, wherein the margin tester includes a controller and a plurality of interfaces for electrical connection to external devices, and wherein at least one interface of the margin tester is configured to connect to a removable test fixture, the test fixture being external to the margin tester and configured to couple the plurality of lanes of the margin tester to the DUT;
establishing a multi-lane high speed input/output (I/O) link with the DUT through the plurality of lanes, wherein for one or more lanes of the multi-lane high speed I/O link, said establishing includes implementing physical and logical link layers that communicatively connect the margin tester with the DUT via the at least one interface and the test fixture; and
assessing, by the margin tester via the test fixture, an electrical margin, in either or both transmit (Tx) and receive (Rx) directions, for each high-speed input/output (I/O) lane of the multi-lane high speed I/O link.