Patent ID: 11942158
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. The memory device of claim 8, wherein the controller is further configured to:
cause the first latch to store, during a second time period after the first time period, the first page of the second data that is being written in the second memory cell of the memory string through the fine write operation,
cause the second latch to store, during the second time period, the first page of the first data to be written in the first memory cell of the memory string through the fine write operation,
cause the third latch to store, during the second time period, the first page of the second data to be written in the second memory cell of the memory string through the fine write operation,
cause the fourth latch to store, during the second time period, the second page of the second data that is being written in the second memory cell of the memory string through the fine write operation,
cause the fifth latch to store, during the second time period, the second page of the first data to be written in the first memory cell of the memory string through the fine write operation, and
cause the sixth latch to store, during the second time period, the second page of the second data to be written in the second memory cell of the memory string through the fine write operation.