Patent ID: 11921630
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 22:
23. A memory system comprising:
a memory device including a plurality of blocks; and
a controller including a first memory,
wherein the controller stores data segments of user data, in response to a plurality of commands received from a host, in the first memory, controls the memory device to store the data segments in the blocks,
updates logical-to-physical (L2P) mapping entries in response to storage of the data segments in the blocks, stores the updated L2P mapping entries in the first memory, and controls the memory device to store the updated L2P mapping entries stored in the first memory, in the blocks, and
provides a response including the updated L2P mapping entries to the host in response to a read buffer command from the host,
wherein the controller updates a second L2P mapping entry group of L2P mapping entries by referencing some part of a first L2P mapping entry group of the L2P mapping entries that has already been updated.