Patent ID: 11955183
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 12:
13. The non-volatile memory of claim 11, wherein the first page buffer circuit is configured to
perform a first read on the first memory cells using a first read level voltage and store a first result of the first reading into the first latch, and
perform a second read on the first memory cells using a second read level voltage different from the first read level voltage and store a second result of the second reading into the second latch, and
wherein the second page buffer circuit is configured to
perform a third read on the second memory cells using the first read level voltage and store a third result of the third reading into the third latch, and
perform a fourth read on the second memory cells using the second read level voltage and store a fourth result of the fourth reading into the fourth latch.