Patent ID: 11876651
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 16:
17. The driving adjustment circuit of claim 16, wherein the third NOT gate comprises a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor;
a first end of the seventh transistor is connected to the ground signal, a first end of the eighth transistor is connected to the second control signal, a first end of the ninth transistor and a first end of the tenth transistor are connected to the second first adjustment signal, a first end of the eleventh transistor and a first end of the twelfth transistor are connected to the second second adjustment signal, a first end of the thirteenth transistor is connected to a third power supply signal, and a first end of the fourteenth transistor is connected to the first control signal;
a second end of the seventh transistor is connected to a fourth power supply signal, a second end of the eighth transistor is connected to a fifth power supply signal, a second end of the ninth transistor is connected to a third end of the seventh transistor, and a second end of the tenth transistor is connected to a third end of the eighth transistor;
a third end of the ninth transistor, a third end of the tenth transistor, a second end of the eleventh transistor, and a second end of the twelfth transistor are connected to the signal terminal; and
a second end of the thirteenth transistor is connected to a third end of the eleventh transistor, a second end of the fourteenth transistor is connected to a third end of the twelfth transistor, and both a third end of the thirteenth transistor and a third end of the fourteenth transistor are connected to the ground signal.