Patent ID: 11922040
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory system comprising:
a memory device comprising a plurality of memory dies, each memory die including a plurality of memory blocks; and
a memory controller which communicates with the memory device and controls the memory device,
wherein the memory controller is configured to:
group the plurality of memory dies into a plurality of memory die groups,
set a first super memory block which is a super memory block including at least one of memory blocks included in memory dies included in a first memory die group among the plurality of memory die groups, and a second super memory block which is a super memory block including at least one of memory blocks included in memory dies included in a second memory die group among the plurality of memory die groups,
determine whether to set an extended super memory block in which all or part of the memory blocks included in the first super memory block and all or part or the memory blocks included in the second super memory block are included.