Patent ID: 11889683
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A method used in forming a memory array comprising strings of memory cells, comprising:
forming a stack comprising vertically-alternating first tiers and second tiers, the first tiers being conductive and the second tiers being insulative in a finished construction, a channel-material string being in individual channel openings in the vertically-alternating first tiers and second tiers, the channel-material strings individually comprising a cylindrical shell, insulator material being radially inside the cylindrical shell, storage material being radially outside the cylindrical shell;
vertically recessing the insulator material in the individual channel openings relative to the storage material and relative to the channel material;
forming a conductor-material contact in the individual channel openings radially inside of and directly against radially-inner sides of the cylindrical shell of the channel material of individual of the channel-material strings and atop the vertically-recessed insulator material, the conductor-material contact having a bottom that is below a bottom of an uppermost of the first tiers;
vertically recessing the conductor-material contacts and the cylindrical shell of the individual channel-material strings relative to the storage material in the individual channel openings; and
forming a conductive via in the individual channel openings directly against a top of the vertically-recessed cylindrical shell of the channel-material string and directly against a top of the vertically-recessed conductor-material contact that are in that individual channel opening.