Patent ID: 11923338
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A structure comprising:
a first device comprising:
a first semiconductor substrate;
a first electric circuit at a bottom side of the first semiconductor substrate; and
a first dielectric layer underlying the first electrical circuit;
a first plurality of conductive features between the first dielectric layer and the first semiconductor substrate;

a second device bonding to the first device, the second device comprising:
a second semiconductor substrate;
a second electrical circuit on a top side of the second semiconductor substrate; and
a second dielectric layer over the second semiconductor substrate, wherein the second dielectric layer is bonded to the first dielectric layer;

a first conductive feature between the second dielectric layer and the second semiconductor substrate;
an interconnect structure penetrating through the first device and extending into the second device, wherein the interconnect structure stops on, and contacts, the first conductive feature in the second device, wherein the interconnect structure has a first width in the first device, and a second width in the second device, and the second width is smaller than the first width;
a conductive line over the first semiconductor substrate and contacting the interconnect structure; and
a bonding structure over and electrically connecting to the conductive line.