Patent ID: 11862699
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A method for manufacturing a semiconductor structure, comprising:
providing a substrate, conductive contact regions being provided in the substrate, and the substrate exposing the conductive contact regions;
forming multiple discrete bit line structures on the substrate, wherein the bit line structures are configured to expose the conductive contact regions, and a top width is smaller than a bottom width of the bit line structures in a direction parallel to an orientation of the bit line structures; and
forming isolation walls including at least one isolation layer on sidewalls of the bit line structures, wherein capacitor contact holes are constituted by regions defined by the isolation walls between adjacent bit line structures, the isolation layer comprises a first isolation part close to the bit line structures and a second isolation part deviating from the bit line structures;
wherein forming the isolation walls comprises: forming a silicon nitride layer on the sidewalls of the bit line structures; doping a second isolation part of the silicon nitride layer with oxygen ions; and forming a silicon oxide layer on a side of the silicon nitride layer deviating from the bit line structures, and doping a second isolation part of the silicon oxide layer with nitrogen ions.