Patent ID: 11928468
Assignee: ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITY
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A method, comprising:
generating a random schedule for mapping onto a coarse-grained reconfigurable architecture (CGRA) unit that schedules a node of a plurality of nodes of a data flow graph expressive of an operation of a computational loop to a random timeslot between a lower bound modulo timeslot and an upper bound modulo timeslot with respect to an initiation interval value;
evaluating a feasibility of the random schedule with respect to resource usage;
generating a new random schedule upon infeasible evaluation of the random schedule; and
increasing the initiation interval after A random schedules have been generated for a current value of the initiation interval.