Patent ID: 11862248
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. The semiconductor storage device according to claim 1, further comprising:
a third memory cell electrically connected to a third bit line and the first word line, the third bit line being adjacent to the first bit line; and
a fourth memory cell electrically connected to a fourth bit line and the first word line, the fourth bit line being adjacent to the second bit line, wherein
during the reading operation to read the page of the memory cells including the third memory cell and the fourth memory cell, while the third memory cell is selected as the read target during a third time period that is different from the first and the second time period, the first circuit supplies:
the first voltage to the first word line,
the second voltage to the first word line after supplying the first voltage,
the third voltage to the first word line directly after supplying the second voltage; and

during the reading operation to read the page of memory cells including the third memory cell and the fourth memory cell, while the fourth memory cell is selected as the read target during a fourth time period that is different from the first, second and the third time periods, the first circuit supplies:
the first voltage to the first word line,
the second voltage to the first word line after supplying the first voltage,
the fourth voltage to the first word line directly after supplying the first voltage, and
the third voltage to the first word line directly after supplying the fourth voltage.