Patent ID: 11930632
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor structure, comprising: a substrate; isolation regions formed in the substrate; active regions formed in the substrate and defined by the isolation regions; gate structures formed in the substrate and arranged alternately with the isolation regions and the active regions; wherein each of the gate structures comprises:
a gate groove formed in the substrate;
a gate dielectric layer formed on an inner surface of the gate groove;
a work function layer formed on the gate dielectric layer and in the gate groove, the work function layer comprising a first portion that is lower than a top surface of the active regions and a second portion that is distributed along a direction substantially perpendicular to a bottom of the gate groove, a first groove being formed between the first portion of the work function layer and the second portion of the work function layer;
a first gate material layer formed on an inner surface of the work function layer and filling up the first groove; and
a second gate material layer formed on a top surface of the work function layer, a top surface of the first gate material layer and a surface of the gate dielectric layer, the second gate material layer being lower than the top surface of the active regions;
a height ratio of the second portion of the work function layer to the first gate material layer to the second gate material layer being 3-8:1-1.5:1.