Patent ID: 11955377
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 11:
12. A method of fabricating an interconnect structure for an integrated circuit, the method comprising:
forming a mask above an ILD material layer, the mask having a plurality of spaced apart features each with a central portion and a pair of sidewall spacers;
forming, using the mask, a first plurality of trenches partially into the ILD material layer;
forming first hardmask portions and a first plurality of electrobuckets in the first plurality of trenches;
forming a second mask from the mask by removing the central portion of each feature of the mask;
forming, using the second mask, a second plurality of trenches partially into the ILD material layer;
forming second hardmask portions and a second plurality of electrobuckets in the second plurality of trenches, wherein the second plurality of electrobuckets has less sensitivity to e-beam or extreme ultra-violet (EUV) radiation than the first plurality of electrobuckets;
exposing, developing and removing fewer than all of the first plurality of electrobuckets by using a lithographic exposure;
forming via locations where the fewer than all of the first electrobuckets were removed; and
forming metal vias in the via locations and metal lines above the metal vias.