Patent ID: 11935826
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method comprising:
depositing a first passivation layer over a conductive feature, wherein the first passivation layer has a first dielectric constant;
forming a capacitor over the first passivation layer;
depositing a second passivation layer over the capacitor, wherein the second passivation layer has a second dielectric constant greater than the first dielectric constant, wherein the depositing the second passivation layer comprises depositing a same material as the first passivation layer, with more porogen incorporated into the first passivation layer than the second passivation layer;
forming a redistribution line over and electrically connecting to the capacitor;
depositing a third passivation layer over the redistribution line; and
forming an Under-Bump-Metallurgy (UBM) penetrating through the third passivation layer to electrically connect to the redistribution line.