Patent ID: 11956947
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 8:
9. A one-time programmable (OTP) memory array, comprising:
a plurality of OTP memory cells arranged in a plurality of columns and a plurality of rows, each OTP memory cell comprising:
an antifuse transistor, wherein a gate terminal of the antifuse transistor is connected to a first word line configured to receive a first signal, and the antifuse transistor is selectable between a first state and a second state in response to the first signal; and
a selection transistor connected between the antifuse transistor and a bit line, wherein a gate terminal of the selection transistor is connected to a second word line configured to receive a second signal, and the selection transistor is configured to provide access to the antifuse transistor in response to the second signal;
wherein a first OTP memory cell and a second OTP memory cell of the plurality of OTP memory cells are arranged in a first row of the plurality of rows, wherein the selection transistor of the first OTP memory cell is connected to the selection transistor of the second OTP memory cell;
the antifuse transistor of the first OTP memory cell has a first terminal that is a vacancy terminal and a second terminal that is connected to the selection transistor of the first OTP memory cell, and
the antifuse transistor of the second OTP memory cell has a third terminal that is a floating terminal including a contact structure and a fourth terminal that is connected to the selection transistor of the second OTP memory cell.