Patent ID: 11862286
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. A data transmission circuit, comprising:
a comparison circuit, configured to receive first data on a data bus and second data on a global data line, and compare the first data with the second data to output a comparison result of whether a number of different bits between the first data and the second data exceeds a preset threshold, wherein the first data and the second data have a same preset bit width;
a data conversion circuit, electrically connected to the data bus, the comparison circuit and the global data line, and configured to: invert the first data and transmit the inverted first data to the global data line in response to the comparison result indicating that the number of different bits exceeds the preset threshold, and transmit the first data to the global data line in response to the comparison result indicating that the number of different bits does not exceed the preset threshold; and
a read-write conversion circuit, electrically connected to the global data line, a local data line and a complementary local data line, and configured to: transmit data on the global data line to the complementary local data line in response to the comparison result indicating that the number of different bits exceeds the preset threshold, and transmit data on the global data line to the local data line in response to the comparison result indicating that the number of different bits does not exceed the preset threshold.