Patent ID: 11929324
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 18:
19. A semiconductor device, comprising:
a substrate including a first device isolation region, a second device isolation region having a first side and a second side opposite the first side, a first active region between the first device isolation region and the first side of the second device isolation region, and a second active region adjacent to the second side of the second device isolation region;
a first bit line structure on the first device isolation region;
a second bit line structure on the second active region;
a buffer pattern between the first device isolation region and the first bit line structure;
a first contact between the first bit line structure and the second bit line structure, the first contact including a first portion, a second portion that is on the first portion, and a third portion that is on the second portion;
a second contact between the second active region and the second bit line structure;
a spacer structure between the first bit line structure and the first contact, the spacer structure including a first spacer, a second spacer that is on the first spacer, and a third spacer that is on the second spacer; and
a capacitor bottom electrode on the first contact,
wherein the first portion of the first contact is in contact with the first device isolation region, the first active region and the second device isolation region,
wherein the first spacer of the spacer structure is in contact with a top surface of the buffer pattern,
wherein the second spacer of the spacer structure is in contact with the buffer pattern, the first device isolation region and the first portion of the first contact,
wherein a top surface of the third spacer of the spacer structure is lower than a top surface of one of the first spacer and the second spacer of the spacer structure, and
wherein a bottom surface of the third spacer of the spacer structure is lower than a top surface of the first device isolation region.