Patent ID: 11923395
Assignee: SONY GROUP CORPORATION
Field: Audio-visual technology (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A chip size package (CSP), comprising:
an upper structural body on which a photodiode is formed; and
a lower structural body comprising:
a multilayer wiring layer; and
a semiconductor substrate provided beneath the multilayer wiring layer,

wherein a through hole penetrates through the semiconductor substrate from a bottom surface of the semiconductor substrate towards a top surface of the semiconductor substrate,
wherein a connection conductor is embedded in an inner wall of the through hole via an insulating film and forms a through via,
wherein the connection conductor of the through via is connected to a rewiring line formed on the bottom surface of the semiconductor substrate,
wherein a protective substrate is provided on a top surface of the upper structural body,
wherein a solder resist is formed on the bottom surface of the semiconductor substrate beneath the rewiring line and the insulating film,
wherein conductive pads are provided on a bottom surface of the CSP beneath the solder resist,
wherein the rewiring line is connected to the conductive pads, and
wherein a region where the connective pads are formed on the bottom surface of the CSP is not covered by the solder resist.