Patent ID: 11972288
Assignee: AMPERE COMPUTING LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus, comprising:
a scheduler circuit comprising a scheduling group circuit, a first selection circuit, and a second selection circuit;
the scheduling group circuit comprising a plurality of groups of scheduling entries, each scheduling entry among the groups of scheduling entries each comprising an instruction portion and a ready portion, each group configured to have its scheduling entries written in-order;
the scheduling group circuit further configured to maintain group age information associated with each group of the plurality of groups;
the first selection circuit configured to select a first in-order ready entry from each group;
the second selection circuit configured to select the first in-order ready entry belonging to the oldest group based on the group age information for scheduling; and
the scheduler circuit further configured to receive new instructions and to write one or more new instruction(s) in order into a group of scheduling entries which has been indicated as available by being configured to:
write a first new instruction in-order into a first group of scheduling entries which has been indicated as available; and
write a second new instruction in-order into a second group of scheduling entries which has been indicated as available when the first group of scheduling entries which was indicated as available has been filled.