Patent ID: 11961832
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. An integrated circuit device comprising:
a substrate having a plurality of intellectual property (IP) core, each of the plurality of IP core surrounded by a separation region, having at least two first edges extending in a first horizontal direction and at least two second edges extending in a second horizontal direction that intersects the first horizontal direction, and comprising a cell region and an edge dummy region that is arranged to extend along the at least two second edges;
a plurality of dummy fin-type active regions in the edge dummy region, and spaced apart from each other by a first pitch in the edge dummy region;
a plurality of fin-type active regions in the cell region, extending in the first horizontal direction;
a plurality of nanosheet stack structures disposed on top surfaces of the plurality of fin-type active regions and spaced apart from the top surfaces of the plurality of fin-type active regions, each of the plurality of nanosheet stack structures comprising a plurality of nanosheets;
a plurality of gate lines in the cell region, extending in the second horizontal direction, which intersects the first horizontal direction;
a plurality of dummy gate lines in the edge dummy region, and spaced apart from each other by a second pitch in the edge dummy region;
a first device isolation film, which defines the plurality of fin-type active regions and fills a lower portion of a first trench disposed between two fin-type active regions, adjacent to each other, of the plurality of fin-type active regions, the first trench having a bottom surface at a first vertical level; and
a second device isolation film filling a second trench, the second trench extending through the first device isolation film and having a bottom surface at a second vertical level that is lower than the first vertical level,
wherein the edge dummy region is disposed between the separation region and the cell region, and
wherein a length, in the second horizontal direction, of the edge dummy region is the same as a length, in the second horizontal direction, of the cell region,
wherein the second device isolation film, in the separation region, is configured to enclose the each of the plurality of IP core and extend along each of at least two first edges and each of at least two second edges,
wherein a portion of the second device isolation film between respective first edges of two adjacent IP cores among the plurality of IP cores is formed in one body, and
wherein two portions of the second device isolation film, which extend to surround mutually-facing respective second edges of two adjacent IP cores among the plurality of IP core is spaced apart from each other.