Patent ID: 11942162
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. The memory device of claim 10, wherein:
the level shifter includes:
a third PMOS transistor and a fourth PMOS transistor, each connected the second voltage terminal,
a third NMOS transistor connected to the first voltage terminal and to the third PMOS transistor through a third node, and
a fourth NMOS transistor connected to the first voltage terminal and to the fourth PMOS transistor through a fourth node;

a gate terminal of the third PMOS transistor is connected to the fourth node;
a gate terminal of the fourth PMOS transistor is connected to the third node;
a gate terminal of the third NMOS transistor is connected to the second node;
the gate terminal of the third NMOS transistor is connected to the first node; and
the fourth node is connected to the third wiring.