Patent ID: 11954589
Assignee: STMICROELECTRONICS S.R.L.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 6:
7. An integrated artificial neuron device, comprising:
an integrator circuit coupled between an input node at which at least one input signal is received and an output node at which the integrator circuit delivers at least one output signal; and
a refractory circuit configured to inhibit the integrator circuit for an inhibition duration after the delivery of the at least one output signal, the refractory circuit comprising:
a first transistor comprising a first n-channel MOS transistor having a drain coupled to a supply node, a source coupled to a common node, and a gate coupled to the output node;
a second transistor comprising a second n-channel MOS transistor having a drain coupled to the input node, a source coupled to a reference node, and a gate coupled to the common node; and
a resistive-capacitive circuit coupled between the supply node and the reference node and having a tap coupled to the common node, wherein the inhibition duration is dependent upon a time constant of the resistive-capacitive circuit.