Patent ID: 11923410
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 21:
22. An integrated circuit comprising:
a body of semiconductor material, the body having a bottommost surface;
a gate structure in contact with a portion of the body, the gate structure defining a channel region in the body;
a source region in contact with the body;
a drain region in contact with the body such that the portion of the body in contact with the gate structure is between the source region and the drain region;
a first isolation region under an entirety of the source region and having a top surface in contact with a portion of a bottom surface of the source region laterally adjacent to the channel region, the first isolation region having an uppermost surface above the bottommost surface of the body;
a second isolation region under an entirety of the drain region and having a top surface in contact with a portion of a bottom surface of the drain region laterally adjacent to the channel region, the second isolation region having an uppermost surface above the bottommost surface of the body; and
a fin stub having a top surface spaced apart from a bottom surface of the body, wherein the gate structure has a gate-all-around configuration that includes a lower gate portion that is below the body, the lower gate portion in contact with: a bottom surface of the body, respective sidewalls of the first and second isolation regions, and the top surface of the fin stub.