Patent ID: 11966290
Assignee: SIFIVE, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. A method comprising:
accessing, using a checker core, a committed instruction packet output from a processor core, wherein the committed instruction packet includes an instruction that has been read from an outer memory system and committed by the processor core;
decoding, using the checker core, the instruction from the committed instruction packet;
executing, using the checker core, the instruction to obtain one or more results;
comparing, using the checker core, the one or more results to corresponding data of the committed instruction packet; and
responsive to a mismatch between the one or more results and the corresponding data of the committed instruction packet, invoking a response to a detected error, in which invoking the response comprises injecting an architectural state of the checker core into the processor core.