Patent ID: 11972815
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device, comprising:
a plurality of memory cells arranged in a plurality of word lines;
a controller in electrical communication with the plurality of memory cells, the controller being configured to:
program the memory cells of a selected word line of the plurality of word lines in a plurality of programming loops and count the number of programming loops to complete programming,
compare the number of programming loops to complete programming of the memory cells of the selected word line to at least one of a predetermined upper limit and a predetermined lower limit to determine if a plane containing the selected word line is at an elevated risk for read failure, and
in response to a determination that the plane containing the selected word line is at an elevated risk for read failure, conduct a post write read operation on at least one word line of the plurality of word lines.