Patent ID: 11973144
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of manufacturing a semiconductor device, the method comprising:
forming a fin structure over a substrate, the fin structure including a bottom fin layer, one or more body layers and epitaxial growth enhancement layers made of different material than the one or more body layers, one of the epitaxial growth enhancement layers being a top layer of the fin structure;
forming an isolation insulating layer over the substrate so that an upper portion of the fin structure protrudes from the isolation insulating layer;
forming a sacrificial gate structure over a channel region of the fin structure;
forming a source/drain space by recessing a source/drain region of the fin structure below an upper surface of the isolation insulating layer such that at least one of the epitaxial growth enhancement layers is exposed in the source/drain space below the upper surface of the isolation insulating layer; and
forming a source/drain epitaxial layer in the source/drain space,
wherein the at least one of the epitaxial growth enhancement layers is in contact with the source/drain epitaxial layer,
the fin structure includes two epitaxial growth enhancement layers separated by one body layer, and
the source/drain region of the fin structure is recessed such that one of the two epitaxial growth enhancement layers located above the upper surface of the isolation insulating layer is exposed in the source/drain space, and another of the two epitaxial growth enhancement layers located below the upper surface of the isolation insulating layer is not exposed.