Patent ID: 11894052
Assignee: STMICROELECTRONICS S.R.L.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. The in-memory computation circuit of claim 13, wherein the coefficient data comprises a coefficient sign and a coefficient value; wherein switching by the second transistor is controlled in response to the coefficient value; and wherein said column combining circuit combines and integrates a positive version of said analog signal in response to either: a) a positive value of the coefficient sign and the positive value of the sign signal or b) a negative value of the coefficient sign and the negative value of the sign signal; and combines and integrates a negative version of said analog signal in response to either: c) the negative value of the coefficient sign and the positive value of the sign signal or d) the positive value of the coefficient sign and the negative value of the sign signal.