Patent ID: 11886377
Assignee: CORNAMI, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G  H

Claim 34:
35. A reconfigurable arithmetic circuit comprising:
a plurality of data inputs, the plurality of data inputs comprising a first, X data input; a second, Y data input, and a third, Z data input;
a plurality of data outputs;
a plurality of output reorder queues coupled to the plurality of data outputs, the plurality of output reorder queues configurable to reorder output data;
a plurality of input reordering queues coupled to the plurality of data inputs and configured to store input data, the input reordering queues further comprising input reordering logic circuitry configurable to reorder a sequence of the input data;
a configurable multiplier coupled to the plurality of input reordering queues, the configurable multiplier having a plurality of operating modes, the plurality of operating modes comprising a fixed point operating mode and a floating point operating mode, wherein the configurable multiplier has a native operating mode of a 27×27 unsigned multiplier further configurable to process signed inputs, and further configurable to become four 8×8 multipliers, two 16×16 single-instruction multiple-data (SIMD) multipliers, one 32×32 multiplier and one 54×54 multiplier;
a multiplier shifter and combiner network coupled to the configurable multiplier, the multiplier shifter and combiner network comprising:
a shifter circuit;
a plurality of series-coupled adder circuits coupled to the shifter circuit; and
a plurality of direct connections coupling the multiplier shifter and combiner network to one or more adjacent reconfigurable arithmetic circuits to perform single cycle 32×32 multiplication, single cycle 54×54 multiplication, single precision/24×24 multiplication, and single-instruction multiple-data (SIMD) dot products;

a fixed and floating point carry-save accumulator circuit; and
a plurality of control logic circuits coupled to the multiplier shifter and combiner network and to the accumulator circuit, the plurality of control logic circuits comprising:
a compare circuit configurable to extract a minimum or maximum data value from an input data stream and an index from the input data stream, and is further configurable to compare two input data streams, to swap the two input data streams to put the minimum of the two input data streams on a first output and the maximum of the two input data streams on a second output, to perform data steering, to generate address sequences, and to generate comparison flags for equality, greater than and less than;
a Boolean logic circuit comprising an AND-OR-INVERT logic unit configurable to perform AND, NAND, OR, NOR, XOR, XNOR, and selector operations on 32-bit integer inputs;
a Z input shifter configurable to shift a floating point Z-input value to a radix-32 exponent value, to shift by multiples of 32-bits to match a scaling of multiplier sum outputs, and having has a plurality of integer modes wherein the Z input shifter is configurable as a shifter or rotator with 64, 32, 2×16 and 4×8 bit shift or rotate modes;
an exponent logic circuit; and
an add, saturate and round circuit.