Patent ID: 11881530
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 8:
9. A semiconductor device, comprising:
a substrate;
a stack of first nanostructured layers disposed on the substrate, wherein each of the first nanostructured layers comprises first and second regions;
a passivation layer disposed on sidewalls of the first and second regions;
a stack of second nanostructured layers disposed on the substrate, wherein each of the second nanostructured layers comprises third and fourth regions, and wherein the first and second nanostructured layers are disposed at surface planes different from each other;
a first epitaxial region surrounding each of the first regions;
a second epitaxial region surrounding each of the third regions, wherein the second epitaxial region is a conductivity type different from the first epitaxial region;
a first gate-all-around (GAA) structure disposed on the stack of first nanostructured layers and around each of the second regions;
a second GAA structure disposed on the stack of second nanostructured layers and around each of the fourth regions;
first inner spacers comprising a first material and disposed between each pair of the first nanostructured layers; and
second inner spacers comprising a second material different from the first material and disposed between each pair of the second nanostructured layers.