Patent ID: 11893477
Assignee: DEEPX CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A system on chip (SoC) comprising:
a first circuit arranged as at least one memory; and
a second circuit arranged as a plurality of processing elements (PEs) capable of performing operations for at least one of artificial neural network (ANN) models,
wherein the plurality of PEs include an adder, a multiplier, and an accumulator,
wherein the plurality of PEs include a first group of PEs configured to operate on a first portion of a clock signal and a second group of PEs configured to operate on a second portion of the clock signal, and
wherein a reference phase of the second group of PEs is based on a conversion from the first portion to the second portion of the clock signal.