Patent ID: 11909405
Assignee: INFINEON TECHNOLOGIES AG
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A digital phase-locked loop (DPLL) circuit comprising:
a coarse time-to-digital converter (TDC) and a coarse digital loop filter (DLF) that are configured to be coupled between a reference clock source and a digitally controlled oscillator (DCO), wherein the coarse TDC is configured to, during an acquisition mode of the DPLL circuit, generate a phase error by:
receiving a reference clock signal from the reference clock source;
receiving a first clock signal that is based on an output of the DCO divided by a dividing factor;
computing a phase error using the reference clock signal and the first clock signal;
comparing a magnitude of the phase error with a threshold value; and
in response to detecting that the magnitude of the phase error is equal to or larger than the threshold value, saturating the magnitude of the computed phase error to the threshold value; and
a first frequency divider circuit coupled to the DCO, wherein the first frequency divider circuit is configured to generate the first clock signal by dividing the output of the DCO by the dividing factor.