Patent ID: 11955519
Assignee: WINBOND ELECTRONICS CORP.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A normally-off transistor with a strain-relaxed layer, comprising:
an epitaxial substrate comprising:
a substrate;
a strain-relaxed layer covering and contacting the substrate, wherein the strain-relaxed layer comprises a first strain-relaxed layer, the first strain-relaxed layer comprises two different material layers, one of the two different material layers is silicon oxide and another one of the two different material layers is silicon carbide, and wherein there is no stress in the strain-relaxed layer; and
a III-V compound stacked layer covering and contacting the strain-relaxed layer, wherein the III-V compound stacked layer comprises a nucleation layer covering and contacting the strain-relaxed layer, a transition layer covering and contacting the nucleation layer, a superlattice covering and contacting the transition layer, and wherein the superlattice is formed by alternately stacking aluminum gallium nitride and aluminum nitride, and there is no carbon within aluminum gallium nitride;

a device layer contacting and covering the epitaxial substrate, wherein the device layer comprising:
a gallium nitride layer; and
an aluminum gallium nitride layer disposed on the gallium nitride layer;

a source electrode and a drain electrode disposed penetrating the aluminum gallium nitride layer;
a gate electrode disposed between the source electrode and the drain electrode, wherein a part of the gate electrode is embedded within the aluminum gallium nitride layer; and
a protective layer disposed between the part of the gate electrode and the aluminum gallium nitride layer.