Patent ID: 11876732
Assignee: STMICROELECTRONICS (ROUSSET) SAS
Field: Digital communication (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 17:
18. The system on a chip according to claim 16, comprising:
wherein at least one piece of configuration information is intended to be attached to each transaction, and the processing circuit includes a verification module configured to:
verify whether a first transaction emanating from a master piece of equipment and intended for an element coupled to the first particular slave resource is authorized to access the element, using the at least one piece of configuration information attached to the transaction as well as the configuration pieces of information assigned to the first particular slave resource; and
verify whether a second transaction emanating from the master piece of equipment and intended for the at least one same element is authorized to access the same element, using the at least one piece of configuration information attached to the transaction as well as a content of the at least one selection register.