Patent ID: 11894308
Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A substrate, comprising:
a dielectric layer
a first conductive via disposed in the dielectric layer, the first conductive via comprising a pattern exposed from the dielectric layer:
wherein the pattern comprises a first geometric center corresponding to a first geometric pattern, a second geometric center corresponding to a second geometric pattern, and a first distance between the first geometric center and the second geometric center is greater than a sum of a radius of the first geometric pattern and a radius of the second geometric pattern,
wherein the pattern further comprises a third geometric center corresponding to a third geometric pattern, a fourth geometric center corresponding to a fourth geometric pattern, and the third geometric pattern is connected to the first geometric pattern and the second geometric pattern, the fourth geometric pattern is connected to the first geometric pattern and the second geometric pattern,
wherein a second distance between the third geometric center and the fourth geometric center is greater than a sum of a radius of the third geometric pattern and a radius of the fourth geometric pattern, and
wherein a third distance between the third geometric center and the second geometric center is less than a fourth distance between the third geometric center and the first geometric center, and a first direction extending from the third geometric center to the second geometric center is substantially perpendicular to a second direction extending from the third geometric center to the first geometric center.