Patent ID: 11915757
Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 5:
6. The memory device through use of a semiconductor device according to claim 1, wherein
when in the page write operation, the memory device holds a hole group generated by an impact ionization phenomenon in the channel semiconductor layer to change a voltage of the channel semiconductor layer to a first data holding voltage which is higher than a voltage of one of or voltages of both of the first impurity layer and the second impurity layer, and
when in the page erase operation, the memory device controls voltages to be applied to the first impurity layer, the second impurity layer, the first gate conductor layer, and the second gate conductor layer to extract the hole group from one or both of the first impurity layer and the second impurity layer, and change the voltage of the channel semiconductor layer to a second data holding voltage which is lower than the first data holding voltage.