Patent ID: 11870398
Assignee: PSEMI CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A circuital arrangement comprising:
an amplifier comprising an input transistor and a plurality of cascode transistors comprising a first cascode transistor coupled to the input transistor and remaining one or more cascode transistors;
a biasing circuit comprising:
a plurality of series-connected resistors coupled between a varying supply voltage to the amplifier and a reference ground, the plurality of series-connected resistors coupled to one another through a plurality of nodes; and
a substantially fixed reference supply voltage coupled to a first node of the plurality of nodes,

wherein:
a gate of the first cascode transistor is coupled to a respective node of the plurality of nodes that is arranged between the first node and the reference ground, and
gates of the remaining one or more cascode transistors are coupled to respective nodes of the plurality of nodes that are arranged between the varying supply voltage and the first node.