Patent ID: 11881486
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of fabricating an integrated circuit structure, the method comprising:
forming a high voltage transistor, the forming comprising:
forming a gate electrode over a three-dimensional semiconductor body, the gate electrode having a first side opposite a second side;
forming a first gate dielectric between the three-dimensional semiconductor body of the high voltage transistor and the gate electrode of the high voltage transistor, wherein the first gate dielectric comprises a first high-k dielectric layer, and wherein the first high-k dielectric layer is further along sides of the gate electrode of the high voltage transistor; and
forming a first source or drain region at the first side of the gate electrode; and
forming a second source or drain region at the second side of the gate electrode; and

forming a low voltage transistor, the forming comprising:
forming a gate electrode over a three-dimensional semiconductor body, the gate electrode having a first side opposite a second side;
forming a second gate dielectric between the three-dimensional semiconductor body of the low voltage transistor and the gate electrode of the low voltage transistor, wherein the second gate dielectric comprises a second high-k dielectric layer, and wherein the second high-k dielectric layer is further along sides of the gate electrode of the low voltage transistor; and
forming a first source or drain region at the first side of the gate electrode; and
forming a second source or drain region at the second side of the gate electrode;
forming a first conductive contact on the first source or drain region of the high voltage transistor, the first conductive contact laterally spaced apart from the first side of the gate electrode of the high voltage transistor by a first distance;
forming a second conductive contact on the second source or drain region of the high voltage transistor, the second conductive contact laterally spaced apart from the second side of the gate electrode of the high voltage transistor by approximately the first distance;
forming a third conductive contact on the first source or drain region of the low voltage transistor, the third conductive contact laterally spaced apart from the first side of the gate electrode of the low voltage transistor by a second distance, the second distance less than the first distance; and
forming a fourth conductive contact on the second source or drain region of the low voltage transistor, the fourth conductive contact laterally spaced apart from the second side of the gate electrode of the low voltage transistor by approximately the second distance.