Patent ID: 11929352
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC H

Claim 14:
15. A memory chip comprising:
a set of word lines stacked along a first direction and extending along a second direction crossing the first direction;
a pillar including:
a semiconductor layer extending through the word lines along the first direction, and
an insulating layer between the semiconductor layer and the word lines;

a set of memory cells, each of the memory cells disposed at a corresponding intersection of the pillar and a corresponding one of the word lines;
a bit line connected to the semiconductor layer;
a bonding pad; and
a transistor configured to electrically connect or disconnect the bit line to or from the bonding pad,
wherein the bit line and the transistor are disposed between the bonding pad and the pillar along the first direction, and the bonding pad is configured for connection with another bonding pad of a control chip, wherein a location of the another bonding pad is between the bonding pad and the control chip along the first direction.