Patent ID: 11861487
Assignee: ZJU-HANGZHOU GLOBAL SCIENTIFIC AND TECHNOLOGICAL INNOVATION CENTER
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. A low-power and compact neuron circuit implementing a rectified linear unit (ReLU) activation function, comprising:
a first-layer synaptic array (1) having at least one voltage output end (1a);
a neuron transistor (2), which is a metal-oxide-semiconductor (MOS) transistor with a threshold voltage-adjustable property, the neuron transistor (2) having a gate electrode (g), a source electrode (s) and a drain electrode (d), and the gate electrode (g) being connected to each voltage output end (1a) of the first-layer synaptic array (1), wherein a single neuron transistor (2) acts as a neuron;
a second-layer synaptic array (3) having at least one voltage input end (3a), each voltage input (3a) being connected to the drain electrode (d) of the neuronal transistor (2);
wherein a voltage output value of the voltage output end (1a) of the first-layer synaptic array (1) is denoted as X, a threshold voltage of the neuron transistor (2) is denoted as Vth, and a gate voltage of the neuron transistor (2) is denoted as Vg, where Vg=X;
in a case where the voltage output value X is less than the threshold voltage Vth, the metal-oxide-semiconductor (MOS) transistor is not turned on, the neuron is not activated, and an output of the neuron is constant at 0;
in a case where the voltage output value X is greater than or equal to the threshold voltage Vth, the metal-oxide-semiconductor (MOS) transistor is turned on, the neuron is activated, and the output of the neuron is X-Vth;
wherein the neuron transistor (2) is a ferroelectric-polarized metal-oxide-semiconductor (MOS) transistor;
wherein the ferroelectric-polarized metal-oxide-semiconductor (MOS) transistor is prepared by:
employing a conventional front-end process for preparing a complementary-metal-oxide-semiconductor (CMOS) transistor, forming a shallow trench isolation region on a substrate, and isolating an active region by the shallow trench isolation region;
forming wells corresponding to each active region through ion implantation; wherein the N-channel-metal-oxide-semiconductor (NMOS) transistor features a P-well, and the P-channel-metal-oxide-semiconductor (PMOS) transistor features an N-well;
forming a gate pattern through photolithographic development, depositing a SiO2 layer on an upper surface of the substrate, depositing a ferroelectric material layer on an upper surface of the SiO2 layer, and then depositing a polysilicon layer on an upper surface of the ferroelectric material layer;
etching the polysilicon layer, the ferroelectric material layer, and a SiO2 layer on the basis of the gate pattern to form a gate structure; and
protecting the gate structure through sidewall masked isolation, and performing ion doping on both ends of the gate structure to form two ends of the source electrode and the drain electrode; employing a conventional complementary-metal-oxide-semiconductor (CMOS) back-end process to prepare the metal-oxide-semiconductor (MOS) transistor, wherein the metal-oxide-semiconductor (MOS) transistor, after preparation, is the ferroelectric-polarized metal-oxide-semiconductor (MOS) transistor by adjusting a doping concentration during the preparation of the drain electrode so as to adjust a resistance value of the drain electrode.