Patent ID: 11935595
Assignee: SILICON MOTION, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 10:
11. A method of a flash memory device to be used in a storage device and coupled to a flash memory controller of the storage device through a specific communication interface, the flash memory device having an input/output (I/O) control circuit, a command register, an address register, a memory cell array, a data register, at least one address decoder, and an address control circuit, the I/O control circuit coupled to the flash memory controller through the specific communication interface, the command register coupled to the I/O control circuit, the memory cell array having a first plane and a second plane, comprising:
using the command register to buffer command information sent from the flash memory controller and transmitted through the I/O control circuit;
using the address register to buffer address information sent from the flash memory controller and transmitted through the I/O control circuit;
using the address control circuit to control the at least address decoder accessing at least one data unit, indicated by the address information transmitted from the address register, for at least one plane of the memory cell array;
wherein the address information is first address information which is used for the first plane and is carried by a single command sequence; the step of using the address control circuit comprises:
controlling the address control circuit automatically generating second address information associated with the second plane according to the first address information of the first plane, and then selecting multiple data units at the first plane and the second plane based on the first address information and the second address information in response to the command information buffered in the command register so as to perform an access operation upon the multiple data units at the first plane and the second plane.