Patent ID: 11862241
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 23:
24. The memory system of claim 23, wherein the first hierarchical bit line structure further comprises a first discharge switch that is connected between the first local bit line and a discharge terminal to be driven in response to a first control signal that corresponds to the discharge control signal,
wherein the first hierarchical word line structure further comprises a second discharge switch that is connected between the first local word line and the discharge terminal to be driven along a direction opposite to the first global word line switch,
wherein the second hierarchical word line structure further comprises a third discharge switch that is connected between the second local word line and the discharge terminal to be driven in response to a second control signal, which has a level opposite to a level of the first control signal, corresponding to the discharge control signal, and
wherein the second hierarchical bit line structure further comprises a fourth discharge switch that is connected between the second local bit line and the discharge terminal to be driven along a direction opposite to the second global bit line switch.