Patent ID: 11894250
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A method comprising:
performing a plasma assisted process on a wafer within a semiconductor process chamber including a top electrode and the wafer positioned on a bottom electrode, wherein the plasma assisted process generates an anode glow region adjacent to the top electrode, a cathode glow region adjacent to the bottom electrode and a plasma region between the anode glow region and the cathode glow region;
capturing, while performing the plasma assisted process, images of plasma within the semiconductor process chamber with a plurality of groups of cameras positioned around the semiconductor process chamber from different angles and positions, each group including an infrared camera, a visible light camera, and an ultraviolet camera;
processing the images with a control system;
generating a 3D model of the plasma within the semiconductor process chamber based on the images;
detecting, during the plasma assisted process, arcing between the top electrode and the wafer through the anode glow region, the plasma region, and the cathode glow region within the semiconductor process chamber with the control system based on the 3D model;
determining a location of the arcing on the wafer within the semiconductor processing chamber based on the images and angles and positions of the plurality of groups of cameras; and
adjusting, with the control system, the plasma assisted process during the plasma assisted process responsive to detecting the arcing.