Patent ID: 11917603
Assignee: QUALCOMM INCORPORATED
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 19:
20. The apparatus of claim 18, wherein, responsive to determining that the first number of coded bits after rate matching for the first PUCCH repetition and the second number of coded bits after rate matching for the second PUCCH repetition would result in different mother polar code lengths for the first and second PUCCH repetitions, the at least one processor is configured to perform the polar encoding by:
adjusting the number of RBs for one of the first or second PUCCH repetitions; and
determining an updated first number of coded bits after performing rate matching for the first PUCCH repetition or an updated second number of coded bits after performing rate matching for the second PUCCH repetition, based on the adjusted number of RBs.