Patent ID: 11894077
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 4:
5. The memory apparatus as set forth in claim 4, wherein the plurality of word lines and a plurality of dielectric layers extend horizontally and overlay one another in an alternating fashion in a stack, the memory holes extend vertically through the stack, the plurality of strings comprise each of a plurality blocks, the plurality of blocks comprise each of a plurality of planes, and the control means is further configured to:
determine whether a leak detection operation should be triggered in response to the quantity of the plurality of smart verify loops being greater than or equal to the predetermined upper loop quantity threshold,
determine whether the leak detection operation should be triggered in response to the quantity of the plurality of smart verify loops being less than or equal to the predetermined lower loop quantity threshold, and
check for leaks involving the memory cells connected to the one of the plurality of word lines and associated with the first one of the plurality of strings in one of the plurality of planes in the leak detection operation in response to determining the leak detection operation should be triggered.