Patent ID: 11864382
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A three-dimensional semiconductor memory device, comprising:
a substrate including a cell array region and a connection region;
an electrode structure including a plurality of electrodes stacked in a first direction perpendicular to a top surface of the substrate, the electrode structure having a staircase-shape on the connection region;
a first vertical channel that penetrates the electrode structure on the cell array region, the first vertical channel including a first lower channel pattern in direct contact with the substrate and a first upper channel pattern connected to the first lower channel pattern; and
a second vertical channel that penetrates the electrode structure on the connection region, the second vertical channel including a second lower channel pattern in direct contact with the substrate and a second upper channel pattern connected to the second low pattern,
wherein a lowermost electrode of the plurality of electrodes surrounds the first lower channel pattern and the second upper channel pattern,
wherein a sidewall of the second lower channel pattern is spaced apart from the substrate,
wherein a top surface of the second lower channel pattern is positioned at a lower level than a bottom surface of the lowermost electrode, and
wherein each of the first lower channel pattern and the second lower channel pattern comprises a pillar-shaped epitaxial pattern directly contacting the substrate.