Patent ID: 11899936
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 4:
5. The data transmission circuit according to claim 4, wherein the mode register data processing unit further comprises:
a first-in-first-out pointer processing unit, connected to the delay module, wherein an output of the first-in-first-out pointer processing unit comprises a first pointer signal in response to the mode register read command, and a second pointer signal in response to the delayed read command; and
a first-in-first-out data processing unit, connected to the first-in-first-out pointer processing unit and the mode register, wherein an input of the first-in-first-out data processing unit comprises a read out of the setting parameters from the mode register in response to the first pointer signal, and wherein an output of the first-in-first-out data processing unit comprises the setting parameters in response to the second pointer signal.