Patent ID: 11901362
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 9:
10. A method comprising:
forming a first set of nanostructures on a substrate, the first set of nanostructures comprising a first channel region;
forming first source/drain regions adjacent the first channel region of the first set of nanostructures;
forming a first gate dielectric on the first channel region;
forming a first work function tuning layer on the first gate dielectric;
forming a barrier layer on the first work function tuning layer;
forming a second work function tuning layer on the barrier layer;
performing a treatment process on the second work function tuning layer to modify a second work function of the second work function tuning layer; and
depositing a fill layer on the treated second work function tuning layer.