Patent ID: 11869872
Assignee: INSTITUTE OF SEMICONDUCTORS, GUANGDONG ACADEMY OF SCIENCES
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 5:
6. A chip stack packaging method, comprising:
a step of forming a stacked chip layer, forming at least one stacked chip layer on a base chip layer, wherein the at least one stacked chip layer comprises an inter-chip insulating layer and at least one stacked chip;
a step of thinning and reducing the at least one stacked chip, thinning and reducing at least one stacked chip comprised in a stacked chip layer each time the stacked chip layer is formed, so as to expose a part of area of pins of the at least one stacked chip;
a step of forming a vertical interconnection hole, after the step of thinning and reducing the at least one stacked chip, forming the vertical interconnection hole to allow corresponding pins to be vertically communicated, wherein the corresponding pins refer to specified pins that need to be electrically connected;
a step of forming a conductive material layer, forming the conductive material layer that makes the corresponding pins electrically connected in the vertical interconnection hole; and
a step of forming a top insulating layer, forming the top insulating layer on the at least one stacked chip layer.