Patent ID: 11908825
Assignee: SK HYNIX INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor package, comprising:
a lower semiconductor die and an upper semiconductor die which are stacked in a staircase form in a first direction, wherein
the lower semiconductor die includes a plurality of lower pads arranged in a second direction, which is perpendicular to the first direction, and
the upper semiconductor die includes a plurality of upper pads arranged in the second direction;

bent wires electrically connecting at least one of the lower pads of the lower semiconductor die to at least one of upper pads of the upper semiconductor die in pairs in the first direction; and
vertical wires disposed on any ones of the lower pads and the upper pads which are electrically connected by the bent wires,
wherein a distance between the vertical wires of adjacent pairs of pads is greater than a pitch between the upper pads of adjacent pairs of pads.