Patent ID: 11862282
Assignee: CEREMORPHIC, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 4:
5. A logic memory storing two charges and performing a logic operation on the two charges, the logic memory comprising:
a first Single Transistor Static Random Access Memory (STSRAM) having a source, drain, and gate, and storing a charge value which modifies a conductivity from the drain to the source when the gate is enabled;
a second STSRAM having a source, drain, and gate, and storing a charge value which modifies a conductivity from the drain to the source when the gate is enabled;
a select line (SL) coupled to the first STSRAM drain and also to the second STSRAM drain;
a Bit Line (BL) node coupled to the first STSRAM source, the second STSRAM source, and to a noninverting input of a current comparator amplifier (CCA) generating a binary result by comparing a current IBL applied to the noninverting input of the CCA to a current Iref applied to an inverting input of the CCA, the inverting input of the CCA coupled to a current source Iref;
a current IBL through the first STSRAM and second STSRAM thereby having:
a first value when a charge is not stored in the first STSRAM and the second STSRAM;
a second value with a charge is stored in one of the first STSRAM or the second STSRAM;
a third value when a charge is stored in both the first STSRAM and the second STSRAM;
the CCA having an output performing a logic operation governed by a setting of Iref and selection of a polarity of the output.