Patent ID: 11881433
Assignee: TESSERA LLC
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A method of forming an integrated circuit, comprising:
providing, in a dielectric layer on a wafer, (i) a first narrow-line trench and (ii) a second narrow-line trench, wherein the first narrow-line trench has a depth d1, wherein the second narrow-line trench has a depth d2, and wherein d1 is less than d2;
depositing a liner material on
a bottom and sidewalls of the first narrow-line trench,
a bottom and sidewalls of the second narrow-line trench, and
the dielectric layer;
depositing copper on the liner material to fill the first and second narrow-line trenches; and
annealing the deposited copper such that (i) copper comprising bamboo microstructure extends to the liner material at the bottom of the first narrow-line trench and (ii) copper comprising bamboo microstructure extends towards the liner material at the bottom of the second narrow-line trench and ends at a depth above d2.