Patent ID: 11875844
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A memory device comprising:
a memory cell array including a plurality of static random access memory cells arranged in rows and columns;
a row decoder connected with the plurality of memory cells through a plurality of word lines;
a data input/output circuit connected with the plurality of memory cells through a plurality of bit lines; and
control logic including a clock generator configured to generate a first internal clock, a level shifter configured to generate a second internal clock by adjusting a level of the first internal clock, and a tracking circuit configured to track a number of the rows and a number of the columns based on the second internal clock,
wherein the tracking circuit includes:
a driver connected with a first wire, and configured to output a first signal based on the second internal clock, a resistance value of the first wire, and a capacitance of the first wire, the first wire having a length corresponding to a length of one of the plurality of word lines;
a first inverter including a first end connected with a second wire and a second end connected with a third wire, and configured to output a second signal based on a resistance value of the second wire, a capacitance of the third wire, and the first signal, the second wire having a length corresponding to a length of one of the plurality of bit lines, and the third wire having a length corresponding to the length of the one of the plurality of bit lines; and
a second inverter configured to output a third signal in response to the second signal,
wherein the second wire and the third wire are identical to the plurality of bit lines connected with the plurality of memory cells.