Patent ID: 11894362
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A method of forming an integrated circuit with an electrostatic discharge protection device, the method comprising:
forming an n-doped buried layer in a semiconductor substrate;
doping the semiconductor substrate to form alternating and adjacent first n-wells and first p-wells in a first region, an adjacent second n-well and second p-well in a second region, and alternating and adjacent third n-wells and third p-wells in a third region, wherein the first n-wells, the first p-wells, the second n-well, the second p-well, third n-wells, and the third p-wells extend to a depth of the n-doped buried layer;
masking every other third n-well so that a first group of third n-wells is masked and a second group of third n-wells is unmasked;
doping to form deep p-wells under the second group of third n-wells while the first group of third n-wells, the first region, and the second region are masked;
doping to form n-doped contact regions directly over the second n-well and the third n-wells;
doping to form p-doped contact regions directly over the first n-wells, the first p-wells, the second p-well and the third p-wells; and
forming a metal interconnect connecting the p-doped contact regions over the first n-wells, the n-doped contact regions over the second n-well, and the n-doped contact regions over the first group of third n-wells to a first terminal, connecting the p-doped contact regions over the first p-wells and the p-doped contact regions over the third p-wells to each other, and connecting the p-doped contact regions over the second p-well and the n-doped contact regions over the second group of the third n-wells to a second terminal.