Patent ID: 11937418
Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A semiconductor-element-including memory device, the memory device comprising a plurality of pages arranged in a column direction, each of the pages being constituted by a plurality of memory cells arranged in a row direction on a substrate,
each memory cell included in each of the pages comprising:
a semiconductor base material that stands on the substrate in a vertical direction or that extends along the substrate in a horizontal direction;
a first impurity layer and a second impurity layer that are disposed at respective ends of the semiconductor base material;
a first gate insulating layer that partially or entirely surrounds a side surface of the semiconductor base material between the first impurity layer and the second impurity layer and that is in contact with or in close vicinity to the first impurity layer;
a second gate insulating layer that surrounds the side surface of the semiconductor base material, that is connected to the first gate insulating layer, and that is in contact with or in close vicinity to the second impurity layer;
a first gate conductor layer that partially or entirely covers the first gate insulating layer;
a second gate conductor layer that covers the second gate insulating layer; and
a channel semiconductor layer that is the semiconductor base material and that is covered by the first gate insulating layer and the second gate insulating layer, wherein
voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer are controlled to perform a page write operation and a page erase operation,
the first impurity layer of the memory cell is connected to a source line, the second impurity layer thereof is connected to a bit line, one of the first gate conductor layer or the second gate conductor layer thereof is connected to a word line, and the other of the first gate conductor layer or the second gate conductor layer thereof is connected to a driving control line,
the bit lines are connected to sense amplifier circuits with a switch circuit therebetween,
in a page read operation, page data in a group of memory cells selected by the word line is read to the sense amplifier circuits, and
in a page sum-of-products read operation, a voltage is applied to the driving control line such that memory cell currents, in the group of memory cells, flowing into the bit lines multiply N-fold (N is a positive integer).