Patent ID: 11948658
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A processing-in-memory (PIM) device comprising:
a first operational logic unit configured to perform a first operation on a first set of first input data and a first set of second input data to output first operation result data;
a second operational logic unit configured to perform a second operation on a second set of the first input data and a second set of the second input data to output second operation result data; and
a buffer memory configured to provide the first set and the second set of the second input data to the first operational logic unit and the second operational logic unit, respectively,
wherein the second operational logic unit is configured to receive the first operation result data from the first operational logic unit and to perform the second operation using the first operation result data as initial latch data,
wherein the first operational logic unit comprises:
a first memory circuit configured to store the first set of the first input data; and
a first operational logic circuit configured to receive the first set of the first input data and the first set of the second input data from the first memory circuit and the buffer memory device, respectively, to perform the first operation, and

wherein the second operational logic unit comprises:
a second memory circuit configured to store the second set of the first input data; and
a second operational logic circuit configured to receive the second set of the first input data and the second set of the second input data from the second memory circuit and the buffer memory device, respectively, to perform the second operation,

wherein the first set of the first input data in the first memory circuit and the first set of the second input data of the buffer memory device are designated by the same first column address, and
wherein the second set of the first input data in the first memory circuit and the second set of the second input data of the buffer memory device are designated by the same second column address.