Patent ID: 11955190
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A memory array system comprising:
a decoder having a first input coupled to a plurality of bit address lines, a second input coupled to a plurality of word address lines, and an output coupled to a plurality of two-dimensional (2D) word lines based on the plurality of bit address lines and the plurality of word address lines; and
a plurality of memory cells, wherein each of the plurality of memory cells is coupled to a corresponding one of the plurality of 2D word lines;
wherein a first subset of the plurality of memory cells is coupled to a first bit line and a second subset of the plurality of memory cells is coupled to a second bit line, and the first subset and second subset share the plurality of 2D word lines.