Patent ID: 11966335
Assignee: GOOGLE LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. A first computing device comprising:
a first cache; and
one or more processors coupled to a first memory device shared between the first computing device and a second computing device, the one or more processors are configured to:
cache control information in the first cache, the control information comprising one or more flags indicating the status of one or more data buffers in the memory device and accessed from a second memory device connected to the second computing device; and
non-coherently read or write contents of the one or more data buffers based on the control information, and after non-coherently reading or writing the contents of the one or more buffers, coherently write updated control information to the second memory device, wherein coherently writing the updated control information causes the control information in the first or second cache to also be updated,

wherein the first computing device is configured to communicate with the second computing device over a hardware interconnect comprising a plurality of channels and configured for memory-coherent data transmission,
wherein the one or more processors are further configured to:
coherently read or write the control information over a first channel dedicated to input/output (I/O) data communication; and
non-coherently read or write the contents of the one or more data buffers over a second channel dedicated to communication between memory devices connected to the first or second computing device,

wherein to coherently write the updated control information to the second memory device, the one or more processors are configured to cause the updated control information to be sent to the second cache of the second memory device over a third channel dedicated to updating contents of the first or second cache, and
wherein the one or more processors are further configured to:
receive, over the I/O channel, a command descriptor, the command descriptor comprising respective addresses for a source data buffer and a destination data buffer in the first memory device;

cache the respective addresses for the source and destination data buffers to the first cache; and
non-coherently read or write the contents of the source and destination data buffer using the respective cached addresses.