Patent ID: 11943051
Assignee: QUALCOMM INCORPORATED
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 21:
22. The apparatus of claim 21, wherein the at least one channel interleaver includes a first channel interleaver for a plurality of parity bits and a second channel interleaver for the plurality of systematic bits,
wherein the at least one channel interleaver includes a first row-to-column interleaver and a second row-to-column interleaver, where the first row-to-column interleaver is associated with an output of a shaping encoder and the second row-to-column interleaver is associated with a low density parity check (LDPC) output of the plurality of systematic bits, or
wherein the at least one processor is further configured to: enable or disable the at least one channel interleaver based on the at least one RV.