Patent ID: 11864373
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 3:
4. The method for manufacturing a semiconductor structure of claim 1, wherein an active area is further arranged in the substrate; and
after the removing a part of the dielectric layer and a part of the first conductive layer on the first barrier layer, to reserve a part of the dielectric layer and a part of the first conductive layer on the first barrier layer closer to the peripheral region, the method for manufacturing a semiconductor structure further comprises:
forming a bit line contact hole on the first barrier layer and the substrate, a bottom of the bit line contact hole exposing the active area in the core region;
forming a second conductive layer in the bit line contact hole, the second conductive layer being flush with the first barrier layer;
forming a third conductive layer on the first barrier layer, the second conductive layer and the first conductive layer; and
forming a second barrier layer on the third conductive layer.