Patent ID: 11888403
Assignee: UNITED STATES OF AMERICA AS REPRESENTED BY THE SECRETARY OF THE AIR FORCE
Field: Electrical machinery, apparatus, energy (Electrical engineering)
Classification: CPC H  Y | IPC H

Claim 1:
2. A direct current-direct current (DC-DC) converter for galvanically isolating a load from a power source and limiting current from the power source to the load, the DC-DC converter comprising:
one of a full-bridge inverter and a half-bridge inverter having an input portion that receives a direct current (DC) input voltage and an input current from a power source and having a power stage, the one of the full-bridge inverter and the half-bridge inverter feeding a transformer that galvanically isolates the input portion from the output;
a controller having gate drives circuitry that switch the one of the full-bridge inverter and the half-bridge inverter to synthesize a first alternating voltage waveform that magnetically couples through the transformer to induce a second alternating voltage waveform with galvanic isolation from the first alternating voltage waveform, preventing a potentially-faulted load from having a direct electrical connection to the power source;
one of a full-bridge rectifier and a half-bridge rectifier having the power stage that rectifies the second alternating voltage waveform to produce a DC output voltage having output current through more than one secondary side transistors; and
a current limiter that current limits more than one primary side drive transistor to reduce or prevent brown-out, black-out, or protective race conditions in non-faulted portions of DC power generation systems and DC distribution electrical power systems, the current limiter configured to:
utilize a transistor to control a voltage or a current mode control output signal to the gate drive circuitry;
compare the output current to a programmed current limit, once per cycle;
utilize negative gate bias to rapidly disable the gate drive signal, without modifying voltage or current mode control design or operation;
shut off the more than one primary side drive transistor to limit output current in response to the output current being greater than the programmed current limit; and
supply a common collector voltage to respective gates of the more than one primary side drive transistor in response to the output current not being greater than the programmed current limit.