Patent ID: 11908528
Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 8:
9. An integrated circuit, comprising:
a memory array;
a charge pump coupled to the memory array and including a plurality of charge pump stages and configured to selectively couple all of the charge pump stages in series for a programming operation of the memory array and to couple the charge pump stages in a first number of parallel groups of series coupled charge pump stages for a read operation of the memory array, wherein each charge pump stage incudes multiple charge pump sub-stages fixedly coupled in series; and
a mode selector coupled to the charge pump and configured to output a selection code to cause the charge pump to couple the charge pump stages for either the read operation or the programming operation, wherein in a test mode of the charge pump the selection code couples the charge pump stages into multiple parallel groups of series coupled charge pump stages.