Patent ID: 11902414
Assignee: HUAWEI TECHNOLOGIES CO., LTD.
Field: Digital communication (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 10:
11. A field programmable gate array (FPGA) cluster for use in homomorphic encryption comprising:
a plurality of FPGAs to provide a configured to provide a pipeline for providing a low-latency relinearization method comprising:
receiving at the FPGA cluster a polynomial vector comprising R components;
performing modular reduction on the polynomial vector to generate a polynomial matrix comprising R+1 rows and R columns;
multiplying the polynomial matrix by a first Keyswitch matrix to generate a first intermediate polynomial matrix;
summing a last row of the first intermediate polynomial matrix to generate a first early-summation element and performing a modular reduction on the first early-summation element to generate a first early-summation vector;
summing remaining rows of the first intermediate polynomial matrix to generate a first summation vector;
subtracting the first early-summation vector from the first summation vector to generate a first subtraction-result vector;
multiplying the first subtraction-result vector by an inverse moduli vector to generate a first result vector; and
outputting from the FPGA cluster the first result vector.