Patent ID: 11966251
Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. A device for generating at least one bias voltage and at least one clock signal, configured to bias back faces of FDSOI transistors of asynchronous digital circuit and to clock the synchronous digital circuit, the device comprising:
an oscillator circuit comprising a signal propagation path, a delay whereof is representative of a delay of a critical path of the synchronous digital circuit and which varies as a function of a value of at least one back-bias voltage supplied to FDSOI transistors of the oscillator circuit, and configured to output, from an output, which is configured to be coupled to a clock input of the synchronous digital circuit, a periodic signal, a frequency whereof depending on the delay of the signal propagation path;
a resistive element of resistance R;
a switched capacitor comprising a capacitance C and which is coupled to the output of the oscillator circuit such that a switching frequency of the switched capacitor corresponds to the frequency of the periodic signal output from the output of the oscillator circuit or to a multiple or to a divisor of the frequency of the periodic signal output from the output of the oscillator circuit; and
an amplifier circuit configured to output, from an output coupled to at least one back-bias voltage input of the FDSOI transistors of the oscillator circuit, a voltage, an amplitude whereof is representative of a difference between a value of the resistance R and a value of an equivalent resistance of the switched capacitor.