Patent ID: 11946970
Assignee: TEKTRONIX, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 16:
17. The method of claim 14 wherein the assessing the electrical margin includes:
assessing, by the controller of the test device, for each respective DUT of a plurality of devices under test (DUTs), timing eye width and/or eye height margin, in either or both of the Tx and receive Rx directions, of the one or more lanes of the multi-lane high speed I/O link of the respective DUT;
detecting, based on the assessing, timing eye width and/or eye height margin measurements for each DUT of the plurality of DUTs that are consistently below a predetermined threshold for a same lane across the plurality of DUTs; and
identifying a potential DUT design issue based on the detection of the timing eye width and/or eye height margin measurements for each DUT of the plurality of DUTs that are consistently below the predetermined threshold for the same lane across the plurality of DUTs.