Patent ID: 11935784
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A method of forming a memory device, comprising:
forming a two-dimensional array of semiconductor channels and a two-dimensional array of drain regions connected to an end of a respective one of the semiconductor channels;
forming a vertical layer stack including a bit-line-level dielectric layer and an etch stop dielectric layer over the two-dimensional array of drain regions;
forming bit-line trenches through the vertical layer stack;
forming bit-line-trench fill structures in the bit-line trenches, wherein each of the bit-line-trench fill structures comprises a stack of a bit line and a capping dielectric strip within each of the bit-line trenches, wherein each of the bit lines is electrically connected to a respective subset of drain regions within the two-dimensional array of drain regions;
forming at least one via-level dielectric layer over the vertical layer stack;
forming a bit-line-contact via cavity through the at least one via-level dielectric layer and one of the capping dielectric strips, wherein the bit-line-contact via cavity comprises a stepped bottom surface including a top surface of one of the bit lines, a sidewall segment of the etch stop dielectric layer, and a segment of a top surface of the etch stop dielectric layer; and
forming a bit-line-contact via structure in the bit-line-contact via cavity.