Patent ID: 11936384
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 19:
20. A multi-bit flip-flop comprising:
a signal generation circuit configured to receive a clock signal, output the clock signal and an inverse clock signal, receive a scan enable signal, and output the scan enable signal and an inverse scan enable signal;
a first bit flip-flop; and
a second bit flip-flop,
wherein the first bit flip-flop comprises
a first input multiplexer configured to receive a first data bit as a data input, receive a second data bit as a scan input, and output one of the first data bit and the second data bit as a third data bit in response to the scan enable signal and the inverse scan enable signal,
a first transmission circuit configured to output a fourth data bit in response to the third data bit in synchronization with the clock signal and the inverse clock signal,
a first latch configured to store the fourth data bit in synchronization with the clock signal and the inverse clock signal,
a second transmission circuit configured to output a fifth data bit in response to the fourth data bit in synchronization with the clock signal and the inverse clock signal, and
a second latch configured to store the fifth data bit and output a sixth data bit as a first output data bit in response to the fifth data bit, and
wherein the second bit flip-flop comprises
a second input multiplexer configured to receive a seventh data bit as a data input, receive the sixth data bit as a scan input, and output one of the seventh data bit and the sixth data bit as an eighth data bit,
a third transmission circuit configured to output a ninth data bit in response to the eighth data bit in synchronization with the clock signal and the inverse clock signal,
a third latch configured to store the ninth data bit in synchronization with the clock signal and the inverse clock signal,
a fourth transmission circuit configured to output a tenth data bit in response to the ninth data bit in synchronization with the clock signal and the inverse clock signal, and
a fourth latch configured to store the tenth data bit and to output an eleventh data bit as a second output data bit in response to the tenth data bit,
wherein each of the first and third transmission circuits comprise a first transmission gate, the first transmission gate of the first transmission circuit configured to transfer the third data bit to be provided as the fourth data bit, and the first transmission gate of the third transmission circuit configured to transfer the eighth data bit to be provided as the ninth data bit,
wherein the first latch comprises a first inverter configured to receive the fourth data bit, and a first three-phase inverter configured to transfer an output of the first inverter to an input of the first inverter in synchronization with the clock signal and the inverse clock signal, and
wherein the third latch comprises a second inverter configured to receive the ninth data bit, and a second three-phase inverter configured to transfer an output of the second inverter to an input of the second inverter in synchronization with the clock signal and the inverse clock signal,
wherein each of the second and fourth transmission circuits comprise a third three-phase inverter,
the third three-phase inverter of the second transmission circuit configured to invert the fourth data bit to provide the fifth data bit in synchronization with the clock signal and the inverse clock signal, and the third three-phase inverter of the fourth transmission circuit configured to invert the ninth data bit to provide the tenth data bit in synchronization with the clock signal and the inverse clock signal, and
wherein the second latch comprises a third inverter configured to receive the fifth data bit, a fourth inverter configured to receive an output of the third inverter and output the sixth data bit, and a second transmission gate configured to transfer the sixth data bit to an input of the third inverter in synchronization with the clock signal and the inverse clock signal, and
wherein the fourth latch comprises a fifth inverter configured to receive the tenth data bit, a sixth inverter configured to receive an output of the fifth inverter and output the eleventh data bit, and a third transmission gate configured to transfer the eleventh data bit to an input of the fifth inverter in synchronization with the clock signal and the inverse clock signal.