Patent ID: 11900156
Assignee: SPEEDATA LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A processor, comprising:
a compute fabric, which is configured to execute specified code instructions on different data in parallel using multiple threads, each thread executing the specified code instructions on respective different data, the compute fabric comprising an array of compute nodes and interconnects that configurably connect the compute nodes; and
a controller, configured to configure at least a group of the compute nodes in the array and at least some of the interconnects in the compute fabric to execute the specified code instructions, and instruct the compute fabric to execute the multiple threads,
wherein each compute node in the group is assigned by the controller to execute a respective same code instruction for the multiple threads,
wherein each compute node in the group comprises a respective token buffer for storing tokens, each token specifying (i) a respective operand on which the compute node is to execute the code instruction assigned to the compute node, and (ii) an identity of a thread that is to use the operand, wherein the token buffer comprises multiple slots for buffering the tokens, wherein each slot (a) is assigned to a respective thread, (b) has a slot identifier derived from an identifier of the thread, and (c) is configured to store metadata of the thread,
wherein a given compute node in the group is assigned to execute a given code instruction for the multiple threads,
and wherein another compute node in the group is configured to transfer an execution result from a first thread to a second thread, different from the first thread, by storing the execution result in the token buffer of the given compute node as a token that (i) specifies the execution result as the operand for the given code instruction, and (ii) specifies the second thread as the identity of the thread that is to use the operand.