Patent ID: 11860747
Assignee: INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A method for performing a power stress test on a field programmable gate array (FPGA) acceleration card, comprising:
dividing, according to a partial reconfiguration (PR) method, the FPGA acceleration card into a static region and a dynamic PR region in advance, and burning FPGA firmware with a partial reconfiguration function to a Flash memory;
in response to receiving a request for power stress test, setting an operating mode of the dynamic PR region as a power test mode, and loading dynamic PR profiles burned in the Flash memory to the dynamic PR region; and
calling power stress test modules to perform the power stress test in the dynamic PR region, wherein
the static region is a hardware logic implementation region for a functional test other than the power stress test, the dynamic PR region comprises a blank mode occupying no hardware resource and the power test mode for performing the power stress test, and the dynamic PR region in the blank mode is used for performing a test other than the power stress test in conjunction with the static region.