Patent ID: 11971448
Assignee: CEREMORPHIC, INC.
Field: Measurement (Instruments)
Classification: CPC G  H | IPC G  H

Claim 7:
8. A process operative on:
a mode selection input Scan_test_mode selecting a functional mode or a test mode;
a multiplexer selecting between a functional logic input when in the functional mode and a test input when in the test mode according to the Scan_test_Mode input;
a master latch comprising low Threshold Voltage transistors (LTVT) forming a low threshold voltage master latch (LTVML) having an input coupled to an output of the multiplexer, the LTVML generating an output coupled to a functional logic output, the master latch clocked by a master functional clock (M_F_CLK) and a master latch test clock (M_T_CLK) which is inverted from the M_F_CLK, both the M_F_CLK and M_T_CLK running continuously in a functional mode and in a test mode;
a slave latch comprising standard Threshold Voltage transistors (STVT) forming a standard threshold voltage slave latch (STVSL) having an input coupled to the output of the LTVML and configured to provide a test output for a subsequent scan chain element;
the process comprising:
clocking the slave latch with a slave latch functional clock (S_F_CLK) and a slave test clock (S_T_CLK) which is inverted from the S_F_CLK, both the S_F_CLK and S_T_CLK enabled only when in test mode;
and where the LTVT transistors have a lower switching threshold voltage than the STVT transistors.