Patent ID: 11930665
Assignee: MIANYANG BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 8:
9. The display substrate according to claim 8, wherein
the first planarization layer includes the two first planarization layers;
the at least one conductive line layer includes three conductive line layers; a planarization layer in the plurality of planarization layers is disposed between two adjacent conductive line layers of the three conductive line layers proximate to the substrate, and is a first second planarization layer; and another planarization layer in the plurality of planarization layers is disposed between two adjacent conductive line layers of the three conductive line layers away from the substrate, and is a second second planarization layer;
the plurality of first blocking layers further include a third first blocking layer arranged in yet another same layer as the first second planarization layer, and a fourth first blocking layer arranged in yet another same layer as the second second planarization layer; and
the plurality of second blocking layers further include a third second blocking layer arranged in the yet another same layer as the first second planarization layer, and a fourth second blocking layer arranged in the yet another same layer as the second second planarization layer; wherein
the at least one connection layer further includes a third connection layer and a fourth connection layer; and the third connection layer connects the third first blocking layer and the third second blocking layer, and the fourth connection layer connects the fourth first blocking layer and the fourth second blocking layer; or
the at least one connection layer further includes a third connection layer, and the third connection layer connects the third first blocking layer and the third second blocking layer; and the fourth first blocking layer is unconnected to the fourth second blocking layer.