Patent ID: 11907043
Assignee: APPLE INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. A method implemented in a processor, the method comprising:
placing the processor into a sleep state in which a plurality of processing pipelines are in a low power state, wherein the plurality of processing pipelines includes a first pipeline having a first memory circuit and a first logic circuit configured to process a physical downlink control channel, a second pipeline having a second memory circuit and a second logic circuit configured to process a physical downlink shared channel, and a third pipeline having a third memory circuit and a third logic circuit configured to process one or more physical uplink channels;
determining when a paging interval has elapsed;
in response to determining that the paging interval has elapsed:
entering a listening state, wherein entering the listening state includes powering up the first pipeline including the first memory circuit and the first logic circuit; and
determining, based at least in part on downlink control information received using the first pipeline, whether a base station has data ready to send to the processor;

in response to determining that the base station has data ready to send, entering a data communication state, wherein entering the data communication state includes powering up the second and third memory circuits and the second and third logic circuits;
determining that the data communication state should be exited; and
in response to determining that the data communication state should be exited, returning to the sleep state, wherein returning to the sleep state includes powering down the first, second, and third memory circuits and the first, second, and third logic circuits.