Patent ID: 11908739
Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An apparatus comprising:
a first substrate comprising a first bonding surface that comprises a first conductive layer-filled cavity, the first conductive layer-filled cavity having a first width of at least 5 microns and a first depth that is less than the first width; and
a second substrate comprising a second bonding surface that comprises a second conductive layer-filled cavity, wherein the second conductive layer-filled cavity has a second width and a second depth that is less than the second width and wherein a width of a grain size of a conductor within the second conductive layer-filled cavity is more than 5% of the width of one of (i) the first conductive layer-filled cavity or (ii) the second conductive layer-filled cavity
wherein the first bonding surface is bonded to the second bonding surface.