Patent ID: 11907758
Assignee: INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. A computer device, comprising a memory, and one or more processors, wherein the memory stores a computer-readable instruction, and when the computer-readable instruction is executed by the one or more processors, the one or more processors are enabled to:
determine that whether a receiving end supports out-of-order reading of an Advance eXtensible Interface (AXI) protocol needs to be tested, and create a plurality of threads on the basis of the determination, wherein the plurality of threads correspond to a plurality of data identifiers on a one-to-one basis;
instruct all threads to acquire transmission permission in a manner of acquisition after random delay, determining, after any thread in the all threads acquires the transmission permission, the any thread as a current thread, and instruct the current thread to drive currently generated data and a corresponding data identifier to an AXI bus for reading by the receiving end, so as to implement an out-of-order reading test on the basis of the data and the corresponding data identifier that are read by the receiving end, wherein only one thread is allowed to acquire the transmission permission at the same moment;
after sending, by the current thread, of the currently generated data and the corresponding data identifier ends, recycle the transmission permission, and return to execute the step of instructing the all threads to acquire the transmission permission in the manner of acquisition after the random delay;
perform functional verification of the AXI bus, wherein, when the functional verification of the AXI bus is performed, the plurality of threads are used to simulate and generate, at a clock beat dimension, read data of multiple transactions returned to the AXI bus, so as to meet a interweaving of different supported ID data in the AXI protocol, and test a support of the receiving end to multi-transaction out-of-order reading in the AXI protocol; and
insert the random delay in each thread to simulate various interweaving situations, so as to test the support of the receiving end to multi-transaction out-of-order reading in the AXI protocol.