Patent ID: 11862668
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A method, comprising:
forming a deck of memory cells;
forming a dielectric portion including one or more dielectric materials over the deck of memory cells;
forming a plurality of cavities within the dielectric portion, wherein each of the plurality of cavities includes a taper from a first cross-sectional area toward a point;
depositing a semiconductor material in each of the plurality of cavities and above the one or more dielectric materials;
forming a plurality of single crystalline arrangements of the semiconductor material, each associated with one of the plurality of cavities, wherein forming the plurality of single crystalline arrangements comprises nucleating each of the plurality of single crystalline arrangements based at least in part on heating and cooling the semiconductor material after depositing the semiconductor material in each of the plurality of cavities; and
forming, from each of the plurality of single crystalline arrangements of the semiconductor material, a respective channel portion of a transistor based at least in part on doping the single crystalline arrangement of the semiconductor material.