Patent ID: 11874784
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. A memory system comprising:
a memory controller;
a memory module connected to the memory controller, the memory module comprising a plurality of memory devices sharing a bus, the plurality of memory devices comprising a first memory device included in a first group and a second memory device included in a second group,
wherein the first memory device comprises:
a first command/address (CA) buffer configured to receive a CA signal through a first CA pin connected to the bus;
a first mode register configured to store a first on-die termination (ODT) strap value; and
a first ODT pin connected to the first mode register and configured to receive one of a first voltage or a second voltage, and provide the one of the first voltage or the second voltage to the first mode register as the ODT strap value, the first voltage being different from the second voltage, and

wherein the second memory device comprises:
a second CA buffer configured to receive the CA signal through a second CA pin connected to the bus; and
a second mode register configured to store a second ODT strap value.