Patent ID: 11937423
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 15:
16. A memory array comprising:
a vertical stack comprising:
a conductive tier;
an insulator tier above the conductive tier;
a first stack comprising at least three select gate tiers above the insulator tier, one of the select gate tiers comprising conducting metal material, another of the select gate tiers comprising conductively-doped semiconductive material; and
a second stack comprising vertically-alternating insulative tiers and wordline tiers above the first stack, the wordline tiers comprising gate regions of individual memory cells, individual of the gate regions comprising part of a wordline in individual of the wordline tiers;
channel material extending elevationally through the insulative tiers, the wordline tiers, the one select gate tier, and the another select gate tier and is directly electrically coupled with conductive material in the conductive tier;
the individual memory cells comprising a memory structure between the individual gate regions and the channel material; the memory structure comprising a charge-blocking region laterally inward of the individual gate regions, a storage region laterally inward of individual of the charge-blocking regions, and insulative charge-passage material laterally inward of individual of the storage regions; a select gate in the one select gate tier and in the another select gate tier, the select gate comprising the conducting metal material in the one select gate tier and the conductively-doped semiconductive material in the another select gate tier; and
an insulating material vertically between and vertically separating the conducting metal material and the conductively-doped semiconductive material proximate the channel material, the conducting metal material in the one select gate tier and the conductively-doped semiconductive material in the another select gate tier being directly coupled to one another distal the channel material, and wherein the conducting metal material is below the conductively-doped semiconductive material.