Patent ID: 11869845
Assignee: GLOBAL UNICHIP CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor wiring substrate, comprising:
a first circuit layer comprising a plurality of first signal traces and a plurality of first ground traces, wherein the first signal traces and the first ground traces are alternatively arranged on the first circuit layer, and one of the first signal traces is spaced at a first spacing from adjacent one of the first ground traces;
a second circuit layer comprising a plurality of second signal traces and a plurality of second ground traces, wherein the second signal traces and the second ground traces are alternatively arranged on the second circuit layer; and
a first dielectric layer between the first circuit layer and the second circuit layer and having a first thickness in an arrangement direction of the first circuit layer, the first dielectric layer and the second circuit layer, wherein the first spacing substantially ranges from 0.78 to 1.96 times the first thickness.