Patent ID: 11941797
Assignee: BATTELLE MEMORIAL INSTITUTE
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. An apparatus for inspecting ICs, comprising:
one or more imaging devices configured to capture one or more images of a Device Under Test (DUT); and
a controller comprising a mapping and inference model (MIM) that is configured to cause the controller to:
receive one or more images of the DUT from the one or more imaging devices;
detect observed features in the one or more images of the DUT and produce a first synthetic representation of a part design of the DUT, the first synthetic representation including at least the observed features;
infer a presence of one or more first unobserved features based at least in part on the first synthetic representation; and
generate a second synthetic representation of the part design of the DUT by adding one or more second unobserved features to the first synthetic representation of the part design.