Patent ID: 11928329
Assignee: NXP B.V.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. The IC of claim 9, wherein a logic circuit of the first set of logic circuits comprises a first multiplexer that is coupled to a first storage element of the first half of the register, and configured to:
receive a first write bit of the set of write bits, a first register bit of the set of register bits that is stored in the first storage element, and a first select bit that is derived from a first mask bit of the set of mask bits;
select and output, based on the first select bit, one of a group consisting of the first write bit and the first register bit as a first output bit; and
write the first output bit to the first storage element, wherein when the first mask bit has the first logic state, the first write bit is written to the first storage element, and when the first mask bit has the second logic state, the first register bit is written to the first storage element.