Patent ID: 11966718
Assignee: RENESAS ELECTRONICS CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 1:
2. The virtual developmental environment apparatus according to claim 1,
wherein the I/O port of the virtual ECU includes an input I/O port and an output I/O port,
wherein the processing execution unit is configured to:
generate a position of the input port and the output port of the identified controller block as first result information;
generate a second model in which the bridge is arranged on the output port and the input port based on the first result information;
generate second result information in which the input port or the output port is associated with the I/O port of the virtual ECU based on the second setting information and the second model; and
generate a vHILS model in which the input port and the output I/O port and the output I/O port in the bridge are respectively connected based on the first result information and the second result information.