Patent ID: 11862591
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. A semiconductor die assembly, comprising:
a first semiconductor die including:
a first semiconductor substrate;
a first dielectric layer over the first semiconductor substrate; and
a first copper pad in the first dielectric layer, the first copper pad having a first surface opposite to the first semiconductor substrate; and

a second semiconductor die including:
a second semiconductor substrate;
a second dielectric layer over the second semiconductor substrate; and
a second copper pad in the second dielectric layer, the second copper pad having a second surface opposite to the second semiconductor substrate, wherein:

the first dielectric layer is in direct contact with the second dielectric layer at a bonding interface between the first and second semiconductor dies; and
the first and second copper pads form an interconnect between the first and second semiconductor dies, the interconnect having a conductive buffer material between the first and second copper pads, wherein the conductive buffer layer includes aggregates of conductive particles, and wherein the conductive buffer layer is less dense than the first and second copper pads.