Patent ID: 11900990
Assignee: R&D 3 LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. A method of reading a memory device, comprising:
effecting, using a read circuit, a voltage transition of a signal node of the memory device at a variable rate corresponding to a respective data value stored within a selected memory cell, wherein the selected memory cell is disposed within a memory array of the memory device, and wherein the respective data value corresponds to a plurality of bits;
measuring, using an individual tracking memory cell, a time-to-transition of a signal node coupled to the selected memory cell, wherein the individual tracking memory cell is disposed within the memory array;
determining, based on the time-to-transition of the signal node coupled to the selected memory cell, an impedance of the selected memory cell; and
determining, using a single memory read access and based on the impedance of the selected memory cell, the respective data value stored in the selected memory cell, wherein the respective data value can be any one of all possible data values corresponding to the plurality of bits.