Patent ID: 11877457
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 11:
12. A memory device, comprising:
a memory layer comprising:
a vertical three-dimensional (3D) memory array that includes a plurality of memory cells;
a plurality of word lines coupled with the plurality of memory cells; and
a digit line associated with the memory array, the digit line comprising a conductive pillar coupled with the plurality of memory cells, wherein the conductive pillar extends vertically and is orthogonal to the plurality of word lines and wherein respective storage elements of vertically adjacent memory cells are isolated from each other;

a pillar selection layer formed under the memory layer and comprising a thin film transistor (TFT) coupled with the conductive pillar for accessing the plurality of memory cells; and
a peripheral circuit layer formed under the pillar selection layer and comprising a sense amplifier and decoding circuitry coupled with the plurality of word lines and with a plurality of bit lines associated with the plurality of memory cells.