Patent ID: 11893938
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 12:
13. The display panel according to claim 12, wherein in the light-emitting stage:

Vn3′=(Vdt+Vth)+C(3/(C3+C1+Cn3-other)*ΔVSn;

Vn4′=Vinit+C4/(C4+C2+Cn4-other)*ΔVSn-1;

Vn1′=(Vdt+Vth)+Cn1-sn/(Cst+2*Cgd+Cn1-other)*ΔVSn+(Cn1-n5+Cgd)/(Cst+2*Cgd+Cn1-other)*ΔVn5;

wherein, Vdt is a data voltage, Vth is a threshold voltage of the driving transistor, C3 is a parasitic capacitance between the third node and the second scanning signal line, C4 is parasitic capacitance between the fourth node and the first scanning signal line, C1 is a capacitance value of the first compensation capacitor, C2 is a capacitance value of the second compensation capacitor, Cn3-other is a parasitic capacitance between the third node and another signal line, Cn4-other is a parasitic capacitance between the fourth node and another signal line, Cn1-other is a parasitic capacitance between the first node and another signal line, and Vinit is a resetting voltage on the resetting signal line, ΔVSn is a voltage difference on the second scanning signal line, ΔVSn-1 is a voltage difference on the first scanning signal line, Cst is a capacitance value of the storage capacitor in the pixel circuit, Cn1-sn is a parasitic capacitance between the gate of the driving transistor and the second scanning signal line, Cgd is a channel capacitance of the driving transistor, and Cn1-n5 is capacitance between the first node and the second electrode of the driving transistor, and ΔVn5 is a voltage difference between voltages of the second electrode of the driving transistor in the light-emitting stage and before the light-emitting stage.