Patent ID: 11963346
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A method for manufacturing a semiconductor structure, comprising:
providing a substrate;
forming a trench in the substrate;
forming a bit line contact structure in the trench, an upper surface of the bit line contact structure being lower than an upper surface of the substrate, the bit line contact structure extending along a first direction;
forming a bit line structure on the bit line contact structure, at least part of the bit line structure being located in the trench;
forming a top dielectric layer on the bit line structure, the top dielectric layer forming a laminated structure together with the bit line structure;
forming a sidewall structure, the sidewall structure covering part of sidewalls of the laminated structure on the substrate, the sidewall structure having a first air gap; the sidewall structure and the top dielectric layer forming a bit line protection structure; and
forming an isolation pattern structure, the isolation pattern structure having a second air gap, the isolation pattern structure extending along a second direction, the second direction intersecting with the first direction, a capacitance contact hole being formed between the adjacent bit line protection structures and the adjacent isolation pattern structures.