Patent ID: 11955535
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method, comprising:
receiving a substrate, the substrate comprising an active region including a channel region and a source/drain feature adjacent the channel region;
forming a dummy gate stack over the active region;
forming spacers along sidewalls of the dummy gate stack;
removing portions of the spacers that are directly over the active region;
forming a first dummy spacer layer over the dummy gate stack and the source/drain feature;
forming a second dummy spacer layer over the first dummy spacer layer and the source/drain feature;
recessing the second dummy spacer layer to expose top-facing surfaces of the first dummy spacer layer while sidewalls of the first dummy spacer layer remain covered by the second dummy spacer layer;
depositing an etch stop layer over the first dummy spacer layer and the second dummy spacer layer;
depositing an interlayer dielectric layer over the etch stop layer;
replacing the dummy gate stack with a gate structure;
recessing the gate structure, the first dummy spacer layer, the second dummy spacer layer, and the etch stop layer to form a self-aligned contact (SAC) opening;
forming a dielectric feature in the SAC opening;
forming a contact feature extending through the etch stop layer, the interlayer dielectric layer, and the first dummy spacer layer to be in contact with the source/drain feature;
selectively recessing the interlayer dielectric layer and the etch stop layer without substantially etching the dielectric feature and the contact feature to form an opening adjacent the contact feature and to expose a portion of the second dummy spacer layer; and
selectively removing the second dummy spacer layer to form an air gap.