Patent ID: 11973111
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A method for fabricating a semiconductor device, the method comprising:
forming a stacked structure in which a first semiconductor layer and a second semiconductor layer are alternately stacked on a substrate;
forming a dummy gate on the stacked structure;
forming a trench by etching the stacked structure using the dummy gate as a mask;
forming a source/drain region in the trench;
forming a sacrificial layer on the source/drain region in the trench;
forming a liner material layer on a sidewall of the dummy gate and on the sacrificial layer;
removing the dummy gate and the first semiconductor layer;
forming a gate electrode in regions from which the dummy gate and the first semiconductor layer are removed;
forming a liner layer on a sidewall of the gate electrode by removing a part of the liner material layer formed on the sacrificial layer;
removing the sacrificial layer to expose the source/drain region;
forming a barrier material layer along a profile of each of the source/drain region and a sidewall of the liner layer, after the removing of the sacrificial layer;
forming a silicide layer by heat-treating a part of the barrier material layer in contact with the source/drain region; and
forming a filling layer on the silicide layer.