Patent ID: 11942168
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 16:
17. A method of manufacturing an integrated circuit (IC) structure, the method comprising:
constructing a first plurality of fin structures extending in a first direction in a first active area and a second plurality of fin structures extending in the first direction in a second active area;
constructing a first plurality of gate structures extending across the first plurality of fin structures, thereby forming a first plurality of fin field-effect transistors (FinFETs);
constructing a second plurality of gate structures extending across the second plurality of fin structures, thereby forming a second plurality of FinFETs;
forming an electrical fuse (eFuse) conductive segment extending in the first direction between the first and second pluralities of FinFETs, a first signal line extending in the first direction between the first plurality of FinFETs and the eFuse conductive segment, and a second signal line extending in the first direction between the second plurality of FinFETs and the eFuse conductive segment;
forming electrical connections from the eFuse conductive segment to each of the first and second pluralities of FinFETs; and
forming electrical connections from the first signal line to the first plurality of gate structures and from the second signal line to the second plurality of gate structures.