Patent ID: 11908806
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor package, comprising:
a first substrate that includes a first insulating layer, a ground pattern in the first insulating layer, and a first conductive pattern;
a first semiconductor chip placed on an upper surface of the first substrate;
a ball array structure that is placed on the upper surface of the first substrate, is electrically connected to the ground pattern, extends along a perimeter of the first semiconductor chip and is spaced apart from side walls of the first semiconductor chip; and
a shielding structure that is in contact with an upper surface of the first semiconductor chip, is in contact with at least a part of an upper surface of the ball array structure and is not in contact with side surfaces of the ball array structure,
wherein the ball array structure has a closed loop shape, and includes a solder ball portion and a connecting portion that connects adjacent solder ball portions, and
a maximum width in a first direction parallel to the upper surface of the first substrate of the solder ball portion is greater than a width of the connecting portion in a direction perpendicular to an extension direction of the connecting portion between adjacent solder ball portions.