Patent ID: 11954493
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A system, comprising:
a first cache set;
a second cache set;
a logic circuit coupled to a processor to control the first cache set and the second cache set according;
a plurality of registers, comprising a first register associated with the first cache set and a second register associated with the second cache set; and
a connection to a speculation-status signal line from the processor identifying a status of a speculative execution of instructions by the processor,
wherein the connection to the speculation-status signal line is configured to receive the status of a speculative execution,
wherein the status of a speculative execution indicates that a result of a speculative execution is to be accepted or rejected;
wherein when an execution type changes from the speculative execution to a non-speculative execution, the logic circuit is configured to:
implement commands via the second cache set if the status of speculative execution indicates that a result of speculative execution is to be accepted; and
implement commands via the first cache set if the status of speculative execution indicates that a result of speculative execution is to be rejected;

wherein when the execution type changes from the speculative execution to a non-speculative execution, the logic circuit is configured to:
change the state of the first and second registers, if the status of speculative execution indicates that a result of speculative execution is to be accepted; and
maintain the state of the first and second registers without changes, if the status of speculative execution indicates that a result of speculative execution is to be rejected.