Patent ID: 11900118
Assignee: APPLE INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A system, comprising:
a stack memory circuit;
a rescue buffer circuit configured to retain address information related to stack push instructions;
a store-load prediction circuit configured to retain register information related to stack push instructions;
a store-load execution circuit configured to execute stack push and stack pop instructions using the stack memory circuit;
a store queue circuit configured to buffer a particular stack push instruction until the particular stack push instruction is released in response to selection by the store-load execution circuit; and
a control circuit configured to:
cause register information related to the particular stack push instruction to be written to the store-load prediction circuit;
cause address information related to the particular stack push instruction to be written to the rescue buffer circuit, wherein the rescue buffer circuit is further configured to retain the address information after the particular stack push instruction has been released from the store queue circuit;
identify, using the address information in the rescue buffer circuit, a subsequent stack pop instruction that is related to the particular stack push instruction; and
perform the subsequent stack pop instruction using the register information from the store-load prediction circuit.