Patent ID: 11923362
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 12:
13. An integrated circuit device comprising:
a fin-type active area protruding from a substrate and extending in a first horizontal direction;
a pair of source/drain regions disposed on the fin-type active area, a first level of a lower surface of each of the pair of source/drain regions being higher than a second level of an upper surface of the fin-type active area;
a nanosheet stack structure facing the upper surface of the fin-type active area with a first separation space between the nanosheet stack structure and the upper surface of the fin-type active area, the nanosheet stack structure comprising a plurality of nanosheets disposed between the pair of source/drain regions;
a gate line extending on the fin-type active area in a second horizontal direction intersecting the first horizontal direction and having a sub-gate portion disposed in a second separation space between two nanosheets from among the plurality of nanosheets;
a gate dielectric layer interposed between the plurality of nanosheets and the gate line; and
a bottom insulation structure in the first separation space,
wherein no portion of the gate line is disposed in the first separation space.