Patent ID: 11929336
Assignee: SK HYNIX INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor device comprising:
a first pad defined on one surface of a first chip, the first chip includes a memory cell array disposed in a cell region and a first peripheral circuit disposed in a peripheral region outside of the cell region;
a second pad defined on one surface of a second chip, which is stacked on the first chip in a first direction, and bonded to the first pad, the second chip includes a second peripheral circuit disposed in the peripheral region;
a first horizontal resistor pattern defined on the one surface of the first chip and coupled to the first pad; and
a second horizontal resistor pattern defined on the one surface of the second chip and coupled to the second pad,
wherein the first horizontal resistor pattern and the second horizontal resistor pattern are disposed between the first peripheral circuit and the second peripheral circuit in the peripheral region,
wherein the first horizontal resistor pattern and the second horizontal resistor pattern do not overlap with each other in the first direction.