Patent ID: 11879939
Assignee: NXP B.V.
Field: Measurement (Instruments)
Classification: CPC G  H | IPC G  H

Claim 9:
10. The IC of claim 9, wherein the reset controller comprises:
a third flip-flop configured to generate a first control signal based on (i) the first pipeline enable signal and (ii) a sixth clock signal that is generated based on the first clock enable signal and the first clock signal, wherein the first control signal is same as the first pipeline enable signal based on a transition of the sixth clock signal;
a third inverter that is coupled to the third flip-flop, and configured to generate a second control signal as an inverted version of the first control signal; and
a fourth flip-flop that is coupled to the clocking system and the third flip-flop, and configured to generate a third control signal based on the first control signal and the first clock signal, wherein the third control signal is same as the first control signal based on a transition of the first clock signal, wherein based on the assertion of the first pipeline enable signal, (i) the first control signal is asserted and the second control signal is de-asserted, and (ii) the reset signal is de-asserted based on the de-assertion of the second control signal, and wherein based on the de-assertion of the first pipeline enable signal, (i) the first control signal is de-asserted and the second control signal is asserted, (ii) the third control signal remains asserted until the transition of the first clock signal, and (iii) the reset signal is asserted based on the assertion of the second control signal and the third control signal.