Patent ID: 11935588
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device, comprising:
a memory cell array in which memory cells of a latch structure are connected in a matrix form to word lines and bit line pairs each of which comprises a bit line and an inverted bit line; and
a driving circuit configured to sequentially program or read n second memory cells among first memory cells connected to a word line through n first bit line pairs (n is a natural number equal to or greater than 2) during an on period in which the word line activates the first memory cells,
wherein the driving circuit comprises a precharging circuit to charge the bit line and the inverted bit line of a corresponding bit line pair through 2 NMOS transistors during an off period inactivating the first memory cells with a second voltage lower than a supply voltage supplied to the memory cells,
wherein the precharging circuit comprises first and second PMOS transistors, a third PMOS transistor, and first and second NMOS transistors,
wherein in the first and second PMOS transistors, input electrodes receive the supply voltage, and control electrodes are connected to each other and receive a turn-on logic level during the off period,
wherein in the third PMOS transistor, a control electrode is connected to the control electrode of the first PMOS transistor, and input and output electrodes are respectively connected to one and the other of output electrodes of first and second PMOS transistors, and
wherein in the first and second NMOS transistors, input electrodes are respectively connected to one and the other of the input and output electrodes of the third PMOS transistor, control electrodes receive the turn-on logic level during the off period, and output electrodes are respectively connected to one and the other of the bit line and the inverted bit line.