Patent ID: 11956342
Assignee: NVIDIA CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 17:
18. A system comprising:
a link comprising one or more lanes associated with transmitting data and one or more lanes associated with transmitting a clock signal;
a first device coupled with the link and comprising a transmitter, the first device to:
transmit a set of bits associated with a pattern via the one or more lanes associated with transmitting the clock signal, wherein the pattern is different than a second pattern associated with a data transmission operation; and

a second device coupled with the link and comprising a receiver, the second device to:
receive the set of bits associated with the pattern;
determine a number of pulses associated with the set of bits over a period;
determine the number of pulses associated with the set of bits fails to satisfy a predetermined condition relating to a specified number of pulses for the period; and
initiate a power-down sequence in response to determining the number of pulses fails to satisfy the predetermined condition relating to the specified number of pulses for the period.