Patent ID: 11973112
Assignee: SILANNA ASIA PTE LTD
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. A transistor tile comprising:
a first PLDD region formed as a first collector region longitudinally spanning a first side of the transistor tile;
a second PLDD region formed as a second collector region longitudinally spanning a second side of the transistor tile;
an N-well formed as a base region located laterally between the first and second PLDD regions;
a base N+ region formed in the N-well; and
an emitter P+ region formed as an emitter region located laterally between the first and second collector regions and in the N-well;
wherein:
the base region and emitter region are both centered on a longitudinally extending, laterally located midline of the transistor tile; and
the base N+ region and the emitter P+ region are separated by a portion of the N-well.