Patent ID: 11956959
Assignee: KIOXIA CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor memory device, comprising:
a semiconductor substrate;
a transistor provided on the semiconductor substrate;
a first interconnection layer provided above the transistor, the first interconnection layer including a first interconnection and a second interconnection, the first interconnection being electrically connected to the semiconductor substrate, the second interconnection being electrically connected to the transistor;
a first conductive layer provided above the first interconnection layer;
a stacked body provided above the first conductive layer and including a plurality of electrode layers stacked in a first direction;
a semiconductor member extending through the stacked body in the first direction and connected to the first conductive layer;
a charge storage member provided between the plurality of electrode layers and the semiconductor member;
a first via provided between the first conductive layer and the first interconnection and connected to the first conductive layer and the first interconnection; and
a second via extending though the stacked body and the first conductive layer and connected to the second interconnection.