Patent ID: 11882707
Assignee: STMICROELECTRONICS (ROUSSET) SAS
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A method, comprising:
forming a row of bipolar transistors, including:
a plurality of first conduction regions;
a second conduction region;
a common base between the first conduction regions and the second conduction region; and
a plurality of insulator walls extending in a first direction, the first conduction regions being separated from one another by the insulator walls;

forming an insulating trench extending in a second direction and in contact with each of the bipolar transistors of the row of bipolar transistors, the insulating trench extending entirely across the common base and at least partially into the second conduction region; and
forming a conductive layer coupled to the base, the conductive layer extending through the insulator walls and extending at least partially into the insulating trench.