Patent ID: 11967578
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. A semiconductor package comprising:
a semiconductor chip;
a lower redistribution layer on a lower surface of the semiconductor chip, the lower redistribution layer comprising an insulating layer, a redistribution pattern on the insulating layer, a via connected to an upper surface of the redistribution pattern and extending through the insulating layer in a vertical direction, an under bump metal (UBM) on a lower surface of the redistribution pattern, and a post between the redistribution pattern and the UBM;
a mold layer on the lower redistribution layer, the mold layer surrounding a lateral side surface of the semiconductor chip; and
a connecting terminal connected to the UBM,
wherein the UBM comprises a first section having an upper surface directly contacting the post and a second section having an upper surface directly contacting the insulating layer,
wherein the post has a ring shape having an inner surface and an outer surface when viewed in a top view,
wherein, when viewed in the top view, a maximum width of the inner surface is in a range of about 0.2 to about 0.8 times a maximum width of an upper surface of the first section, and a maximum width of the outer surface is in a range of about 1.2 times or more the maximum width of the upper surface of the first section.