Patent ID: 11971446
Assignee: nan
Field: Measurement (Instruments)
Classification: CPC G | IPC G

Claim 0:
1. An interface system for an interconnected die and an MPU, comprising a data interface, an interrupt interface, and a debugging interface; the data interface comprises an SPI interface, a DDR data interface, and a DMA control interface; the SPI interface is used for autonomous startup of the MPU during the startup phase, and the DMA control interface is used for DMA startup and end control; the interrupt interface is used for receiving an interrupt data packet from the network and parsing the interrupt data packet to obtain a pulse interrupt input required by the MPU, and meanwhile, the interrupt interface receives an interrupt address operation from the data interface and converts the interrupt address operation into an interrupt event to be sent out; the debugging interface comprises a JTAG-Core debugging interface, which is used for receiving a debugging data packet from the network and translating the debugging data packet into a JTAG protocol for MPU debugging.