Patent ID: 11909567
Assignee: HITACHI, LTD.
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. The equalization system according to claim 6, wherein
the CAL logic circuit
starts the calibration loop at a time point at which capacitance switching control of a zero point generation circuit of the equalizer or a source follower is executed, or at a time point of continuous operation,
sequentially outputs an instruction to apply the displacement amount stepwise to the value of the mutual conductance gm2 of the third and fourth transistors of the equalizer step by step to the gm2 adjustment unit,
obtains an evaluation value of an opening degree of the eye pattern opening portion from the EYE monitor in which an eye pattern is created based on a data signal obtained by the equalizer executing equalizing by the gm2 value, the gm2 value being variably controlled by the gm2 adjustment unit by one stage, and
compares the evaluation value of the opening degree of the eye pattern opening portion obtained at each stage in which the displacement amount is applied stepwise to the gm2 value, identifies the displacement amount applied to the gm2 value at the stage in which a maximum evaluation value is obtained, and instructs the gm2 adjustment unit to set gm2.