Patent ID: 11870441
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: nan (nan)
Classification: CPC nan | IPC G  H

Claim 7:
8. A clock gating circuit comprising:
a NOR logic gate coupled to a first node, and being configured to receive a first enable signal and a second enable signal, and to set a first control signal in response to the first enable signal or the second enable signal;
a transmission gate coupled to the NOR logic gate by the first node, and being further coupled between the first node and a second node, the transmission gate being configured to receive at least the first control signal, an inverted clock input signal or a clock output signal;
a cross-coupled pair of transistors coupled between the second node and an output node, and being configured to receive at least a second control signal or the clock output signal; and
a first pull-up transistor of a first type, the first pull-up transistor including a first gate terminal, a first drain terminal and a first source terminal, the first gate terminal being configured to receive the inverted clock input signal, the first drain terminal being coupled to at least a third node, and the first source terminal being coupled to a voltage supply, the first pull-up transistor being configured to adjust the clock output signal responsive to the inverted clock input signal.