Patent ID: 11869610
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. The storage device according to claim 15, wherein the second control unit comprises:
an eleventh transistor, configured with a source to be electrically connected to the first voltage, and a drain to be electrically connected to the first negative data wire;
a twelfth transistor, configured with a drain to be electrically connected to both the drain of the eleventh transistor and the first negative data wire, and a source to be electrically connected to the second voltage;
a third NOR gate, configured with an output end to be electrically connected to a gate of the eleventh transistor, and a first input end to be electrically connected to the output end of the second inverter;
a fourth NOR gate, configured with an output end to be electrically connected to a gate of the twelfth transistor, and a first input end to be electrically connected to the output end of the first NAND gate;
a second AND gate, configured with an output end to be electrically connected to a second input end of the third NOR gate, and a first input end to be electrically connected to the writing enable signal; and
a third inverter, configured with an output end to be electrically connected to both a second input end of the fourth NOR gate and the second input end of the second AND gate, and an input end to be electrically connected to the second data wire.