Patent ID: 11900038
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A simulation method, comprising:
generating a power wire topology network according to a power wire layout, the power wire topology network comprising a plurality of first layer of metal wires arranged in a transverse direction, a plurality of second layer of metal wires arranged in a longitudinal direction, power child nodes, and a parasitic element, the parasitic element being located between two power child nodes;
determining a minimum voltage of a power input node of each circuit module in a circuit corresponding to the power wire topology network, the power input node being one of the power child nodes in each circuit module;
performing time sequence simulation according to the minimum voltage of the power input node of each circuit module and a post-simulation circuit network list of an integrated circuit, wherein the post-stimulation circuit network list of the integrated circuit does not comprise a parasitic capacitance or a parasitic resistance; and
performing post-stimulation by using the parasitic capacitance and the parasitic resistance after the time sequence simulation is completed.