Patent ID: 11934941
Assignee: APPLE INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A method of performing neural processing operations, comprising:
storing at least one of neural output data or planar output data in a buffer circuit;
addressing data dependency between neural input data and planar input data by a data processor circuit, the addressing data dependency comprising:
selectively having the buffer circuit grant access to the planar output data in the buffer circuit by one or more neural engine circuits to read the planar output data, or
selectively having the buffer circuit grant access to the neural output data in the buffer circuit by one or more planar engine circuits to read the neural output data as the planar input data;

performing, by the one or more neural engine circuits, convolution operations on the neural input data to generate the neural output data; and
performing, by the one or more planar engine circuits, non-convolution operations in parallel with performing of the convolution operations, on the planar input data to generate the planar output data.