Patent ID: 11887975
Assignee: DAICEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 1:
2. A semiconductor device manufacturing method comprising:
a preparation step of preparing two reinforced wafers each having a laminated structure that includes a wafer including an element forming surface and a back surface opposite therefrom, a supporting substrate, and a temporary adhesive layer forming temporary adhesion, the temporary adhesive layer being provided between the supporting substrate and a side of the element forming surface of the wafer;
a thinning step of grinding the wafer of each of the reinforced wafers from a side of the back surface, forming a thinned wafer;
a bonding step that is implemented with each of the reinforced wafers, and in which a side of an element forming surface of a base wafer including the element forming surface and a back surface opposite therefrom is bonded, through an adhesive, to the side of the back surface of the thinned wafer of the reinforced wafer, whereby forming two first wafer laminates;
a removal step of removing the supporting substrate from each of the first wafer laminates; and
a multilayering step in which the sides of the element forming surface of the thinned wafers or sides of the back surface of the base wafers of two of the first wafer laminates that have been subjected to the removal step are bonded through an adhesive, forming a second wafer laminate from the two first wafer laminates, wherein
the second wafer laminate obtained through the multilayering step has a laminated configuration that is symmetrical in a thickness direction thereof.