Patent ID: 11943938
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 12:
13. A method for manufacturing a 3D vertical array of memory cells, comprising:
forming, on a substrate, a stack of dielectric material layers comprising alternating first and second dielectric material layers;
forming a trench through the stack of dielectric material layers, the trench exposing the substrate, and
filling the trench with a third dielectric material
forming holes through the stack of dielectric material layers, the holes exposing the substrate, wherein forming the holes through the stack of dielectric material layers comprises forming the holes in the third dielectric material filling the trench;
selectively removing the second dielectric material layers through the holes to form cavities between adjacent first dielectric material layers;
filling the cavities with a conductive material through the holes to form corresponding conductive material layers for forming a first access line to memory cells;
forming memory cell storage elements though recesses at the holes; and
filling the holes with conductive material to form corresponding second memory cell access lines.