Patent ID: 11937470
Assignee: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 11:
12. The array substrate according to claim 8, wherein the peripheral area further comprises a corner area adjacent to the first peripheral area, the first power bus is also located at the corner area, and the first power bus and the plurality of data signal input lines are located on different layers, and the array substrate further comprises:
a plurality of control signal connecting lines located in a different layer from the plurality of data signal input lines and located between the first power bus and the display area, wherein each of the plurality of control signal connecting lines is electrically connected to one of the plurality of control signal lines; and
a plurality of control signal input lines located in a different layer from the first power bus, wherein each of the plurality of control signal input lines is electrically connected to a control signal connecting line of the control signal connecting lines via a third via, and an orthographic projection of the third via on the base substrate is located between an orthographic projection of a portion of the first power bus line located at the corner area on the base substrate and orthographic projections of the plurality of data signal input lines on the base substrate.