Patent ID: 11869988
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. A method for building an integrated circuit (IC), comprising:
forming a first series of trenches on a first side of a semiconductor substrate, and forming a first deep trench capacitor (DTC) stack within the first series of trenches;
after the first DTC stack has been formed, bonding the first side of the semiconductor substrate to a first metal interconnect structure disposed on a carrier wafer;
thinning down a second side of the semiconductor substrate opposite the first side;
etching a second series of trenches into the second side of the semiconductor substrate, and forming a second DTC stack within the second series of trenches;
wherein the first DTC stack and the second DTC stack have an overall thickness ranging from 1 micrometer to 500 micrometers;
forming a through-substrate via (TSV) through the semiconductor substrate;
forming an inter-layer dielectric over the second side of the semiconductor substrate, wherein the inter-layer dielectric directly contacts outer sidewalls of the TSV; and
forming a first encapsulation layer directly over the inter-layer dielectric, wherein the first encapsulation layer completely overlies the semiconductor substrate.