Patent ID: 11887520
Assignee: REALTEK SEMICONDUCTOR CORPORATION
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A chipset for frame rate control (FRC), comprising:
a first FRC chip, configured to receive input image data, and perform a motion compensation on a first part of the input image data to generate a first part of an output image data, wherein a frame rate of the output image data is greater than or equal to a frame rate of the input image data; and
a second FRC chip, configured to receive a second part of the input image data, and perform the motion compensation on the second part of the input image data to generate a second part of the output image data;
wherein the first part of the output image data and the second part of the output image data are combined into complete output image data for displaying on a display panel;
wherein the first FRC chip splits the input image data into the first part of the input image data and the second part of the input image data, wherein the first part of the input image data is stored in a memory of the first FRC chip, and the second part of the input image data is sent to the second FRC chip.