Patent ID: 11921635
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A method of managing data coherency in a heterogeneous processing system, the method comprising:
performing a virtual to physical memory address translation for a memory write request to a block of memory having a virtual memory address in a unified virtual memory address space in which a complete virtual address space of a graphics processor is shared with an application processor;
concurrently with the virtual to physical memory address translation, managing cache coherency state for one or more cache lines associated with the block of memory, wherein the one or more cache lines are within a cache memory of a graphics processor of the heterogeneous processing system and a cache memory of an application processor of the heterogeneous processing system, wherein managing the cache coherency state includes:
determining coherency ownership associated with the block of memory based on cache coherency metadata stored contiguously with virtual to physical memory address translation data for the block of memory, the coherency ownership and the virtual to physical memory address translation data determined via a single read operation that is performed based on the virtual memory address of the block of memory, wherein the block of memory is accessible to the graphics processor and the application processor via the virtual memory address; and
transferring the coherency ownership associated with the block of memory between the graphics processor and the application processor, wherein address translation circuitry of each of the graphics processor and the application processor is to transfer the coherency ownership via a response sent between the graphics processor and application processor.