Patent ID: 11894846
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A memory device comprising clock distortion calibration circuitry configured to:
in response to determining that a duty cycle calibration (DCC) condition is met, execute a DCC operation to adjust a trim value associated with a duty cycle of a voltage signal, wherein the DCC condition comprises the memory device performing a data write operation and refraining from performing a data read operation based on receiving a command;
while executing the DCC operation and after determining that the DCC condition is met, determine that the DCC condition is no longer met; and
in response to the determination that the DCC condition is no longer met, interrupt the DCC operation before completing execution of the DCC operation such that the clock distortion calibration circuitry (i) does not adjust the trim value during the execution of the DCC operation or (ii) does not use an adjusted trim value, generated while executing the DCC operation, to calibrate the duty cycle of the voltage signal.