Patent ID: 11925032
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 9:
10. A method of forming a memory cell, the method comprising:
forming a bottom electrode material layer;
forming a memory element of the memory cell on the bottom electrode material layer;
forming a sidewall spacer on a sidewall of the memory element and in contact with an upper surface of the bottom electrode material layer;
forming an etch stop layer on the sidewall spacer and the bottom electrode material layer;
removing a first portion of the etch stop layer to expose a portion of the bottom electrode material layer; and
etching the exposed portion of the bottom electrode material layer to form a bottom electrode of the memory cell, such that a peripheral portion of the bottom electrode extends beyond the sidewall spacer and the etch stop layer contacts an upper surface of the bottom electrode at the peripheral portion of the bottom electrode.