Patent ID: 11971815
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 4:
5. A device, comprising:
a communication interface;
memory cells formed on an integrated circuit die; and
circuitry configured to:
receive, via the communication interface, a command that indicates a write threshold;
store, in a portion of the memory cells or in a register on the integrated circuit die, one or more bits that indicate the write threshold, the one or more bits associated with a logical partition, wherein the write threshold indicated by the one or more bits specifies a threshold quantity of program erase cycles in the memory cells utilized to host the logical partition and a threshold amount of bytes to be written to the logical partition;
determine that an accumulated amount of program erase cycles used to host the logical partition and that an accumulated amount of first data written to the memory cells according to write requests, received in the communication interface, has reached the write threshold based on the accumulated amount of program erase cycles used to host the logical partition satisfying the threshold quantity of program erase cycles and based on the accumulated amount of first data satisfying the threshold amount of bytes based on the write requests identifying the logical partition; and
avoid writing data to the logical partition after receiving a write request based at least in part on a determination that the accumulated amount of first data and the accumulated amount of program erase cycles has reached the write threshold.