Patent ID: 11869564
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. An integrated chip structure, comprising:
a first source/drain region and a second source/drain region disposed within a substrate;
a select gate disposed over the substrate between the first source/drain region and the second source/drain region;
a ferroelectric random-access memory (FeRAM) device disposed over the substrate between the select gate and the first source/drain region;
a first sidewall spacer comprising one or more dielectric materials arranged laterally between the select gate and the FeRAM device; and
an inter-level dielectric (ILD) structure laterally surrounding the FeRAM device and the select gate and vertically overlying a top surface of the first sidewall spacer.