Patent ID: 11967357
Assignee: NATIONAL TSING HUA UNIVERSITY
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 15:
16. The memory unit with time domain edge delay accumulation for computing-in-memory applications of claim 8, wherein a number of the at least one edge-delay cell multiplexor is plural, a number of the at least one edge-delay cell is plural, the edge-delay cell multiplexors are connected to the edge-delay cells, respectively, the edge-delay cell multiplexors are configured to transmit a plurality of weights to each of the edge-delay cells, one of the weights is the one of the first weight and the second weight, the edge-delay cells are configured to receive a plurality of the multi-bit analog input voltages, a plurality of the edge-input signals and the weights, the edge-delay cells are connected in series and configured to generate a plurality of the edge-output signals having a plurality of the delay times, and the delay time of a last one of the edge-output signals is positively correlated with a sum of the multi-bit analog input voltages multiplied by the weights.