Patent ID: 11914524
Assignee: QUALCOMM INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 18:
19. An apparatus for managing memory accesses at a respective processor of one or more processors that are configured to execute one or more virtual machines, the apparatus comprises:
means for receiving a request for initiating a synchronization event; and
means for in response to the request:
identifying a subset of speculative memory access requests in one or more memory access request queues;
automatically, in accordance with the identifying, purging translations associated with the subset of speculative memory access requests;
subsequent to the purging, initiating the synchronization event; and

means for receiving a barrier instruction configured to force memory access completion to initiate a data synchronization event for updating registers associated with a virtual machine implemented on the respective processor,
wherein the barrier instruction includes a data synchronization barrier that is executed on a hypervisor layer or a firmware layer to force memory access completion of the speculative memory access requests to an operating system level or an application level.