Patent ID: 11956970
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 14:
15. The apparatus of claim 14, wherein:
the first tile comprises the first plate node coupled with storage elements of the first memory cells associated with the set of first digit lines and the second plate node coupled with the storage elements of the first memory cells associated with the second set of first digit lines; and
the second tile comprises a third plate node coupled with storage elements of the second memory cells associated with the set of second digit lines and a fourth plate node coupled with the storage elements of the second memory cells associated with the second set of second digit lines,
wherein each of the first plate node, the second plate node, the third plate node, and the fourth plate node is operable for biasing independently from others of the first plate node, the second plate node, the third plate node, and the fourth plate node.