Patent ID: 11862220
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 18:
19. A memory device comprising:
a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell each comprising a ferroelectric field effect transistor and a field effect transistor, wherein the ferroelectric field effect transistor comprises a grounded first source/drain, a first gate structure, and a second source/drain, and the field effect transistor comprises a third source/drain connected to the first gate structure, a second gate structure, and a fourth source/drain;
a first selection word line connected to the second gate structure of each of the first memory cell and the second memory cell;
a second selection word line connected to the second gate structure of each of the third memory cell and the fourth memory cell;
a first bit line connected to the second source/drain of each of the first memory cell and the third memory cell;
a second bit line connected to the second source/drain of each of the second memory cell and the fourth memory cell;
a first cell word line connected to the fourth source/drain of each of the first memory cell and the third memory cell; and
a second cell word line connected to the fourth source/drain of each of the second memory cell and the fourth memory cell,
wherein, in a write operation on the fourth memory cell, a switching voltage is applied to the second selection word line, a write voltage is applied to the second cell word line, and 0 V is applied to the first bit line, the first selection word line, the first cell word line, and the second bit line.