Patent ID: 11914518
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. An apparatus as claimed in claim 11, wherein:
the allocation circuitry comprises a plurality of determination blocks forming at least one group of determination blocks, where each group comprises multiple determination blocks arranged in series;
a first determination block in each group is arranged to receive a source vector derived from the input vector, and each other determination block in any given group is arranged to receive as a source vector an updated vector generated by a preceding determination block in that given group;
each instance of the first direction analysis circuitry and the second direction analysis circuitry is formed by a group of determination blocks;
a first determination block in the first direction analysis circuitry of the first determination circuitry is arranged to receive as its source vector the input vector;
a first determination block in the second direction analysis circuitry of the first determination circuitry is arranged to receive as its source vector a bit order reversed version of the input vector;
a first determination block in the first direction analysis circuitry of the second determination circuitry is arranged to receive as its source vector an inverted version of the input vector; and
a first determination block in the second direction analysis circuitry of the second determination circuitry is arranged to receive as its source vector a bit order reversed version of the inverted version of the input vector.