Patent ID: 11972788
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. An apparatus comprising:
a memory; and
a controller configured to provide commands and addresses to the memory along a CA bus,
configured to send and receive data along a DQ bus,
configured to identify an aggressor address based, in part, on the addresses provided to the memory along the CA bus, and provide the identified aggressor address to the memory, and
configured to provide a sampling command signal to the memory, wherein the sampling command signal is different from the commands, wherein the sampling command signal causes the memory to provide a sampling signal at an active level, wherein the memory comprises a refresh control circuit separate from the controller configured to provide the sampling signal at the active level based on timing logic of the refresh control circuit, wherein the sampling signal causes detection of a row address of the addresses when the sampling signal is at the active level, and wherein the memory comprises an aggressor address storage structure configured to store first aggressor addresses identified by the refresh control circuit and further configured to store second aggressor addresses received from the controller, wherein the second aggressor addresses are identified as aggressor addresses by the controller.