Patent ID: 11923430
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A device structure, comprising:
a substrate;
a fin disposed over the substrate and extending lengthwise along a first direction;
a gate structure disposed over a channel region of the fin; and
a first gate spacer and a second gate spacer sandwiching the gate structure along a second direction perpendicular to the first direction,
wherein the gate structure comprises:
an interfacial layer disposed on the channel region of the fin,
a first high-k dielectric layer disposed on the interfacial layer, a sidewall of the first gate spacer, and a sidewall of the second gate spacer,
a second high-k dielectric layer disposed over the first high-k dielectric layer and extending along the sidewall of the first gate spacer and the sidewall of the second gate spacer, and
a third high-k dielectric layer disposed over the second high-k dielectric layer and extending along the sidewall of the first gate spacer and the sidewall of the second gate spacer,

wherein the first high-k dielectric layer, the second high-k dielectric layer, and the third high-k dielectric layer comprise hafnium oxide,
wherein the first high-k dielectric layer is doped with aluminum,
wherein the second high-k dielectric layer is substantially undoped,
wherein the third high-k dielectric layer is doped with lanthanum.