Patent ID: 11967624
Assignee: HITACHI, LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor device comprising:
a semiconductor chip having a first gate pad and a second gate pad in a main surface;
a first wiring provided outside the semiconductor chip and electrically connected to the first gate pad;
a second wiring provided outside the semiconductor chip and electrically connected to the second gate pad; and
a first voltmeter connected between the first wiring and the second wiring, wherein the semiconductor chip includes:
a substrate of a first conductivity type;
a source region of a second conductivity type different from the first conductivity type, which is formed in an upper surface of the substrate;
a drain region of the second conductivity type formed in a lower surface of the substrate;
a first gate electrode formed on the substrate and electrically connected to the first gate pad; and
a second gate electrode formed on the substrate and electrically connected to the second gate pad,
wherein the first gate electrode, the source region, and the drain region constitute a first field effect transistor,
wherein the second gate electrode, the source region, and the drain region constitute a second field effect transistor,
wherein a current measuring unit is connected in series with the source region which constitutes the second field effect transistor,
wherein the first gate pad, the second gate pad, a first source pad, and a second source pad are formed in the main surface of the semiconductor chip,
wherein the first source pad is electrically connected to the source region of the first field effect transistor,
wherein the second source pad is electrically connected to the source region of the second field effect transistor, and
wherein the area of the first source pad is larger than that of the second source pad.