Patent ID: 11862222
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A refresh circuit, comprising:
a refresh control module configured to receive a refresh command to output a row address refresh signal, the row address refresh signal being outputted a number of times of a preset value each time the refresh command is received; and further configured to receive a temperature signal to adjust the preset value, the higher a temperature represented by the temperature signal, the greater the adjusted preset value;
a row addresser configured to receive the row address refresh signal and output a to-be-refreshed single-row address; and
an array refresh device configured to perform a single-row refresh operation according to the single-row address and output a single-row refresh end signal after the end of single-row refresh;
wherein the refresh control module comprises:
a control unit configured to receive the row address refresh signal and output a reset signal; and further configured to count the row address refresh signal, and output the reset signal when a count value is equal to the adjusted preset value; and
a refresh signal generation unit configured to receive the refresh command, the reset signal and the single-row refresh end signal and output the row address refresh signal; output the row address refresh signal when receiving the refresh command; detect the reset signal when receiving the single-row refresh end signal, output the row address refresh signal when not receiving the reset signal, and suspend outputting the row address refresh signal when receiving the reset signal.