Patent ID: 11934834
Assignee: AMPERE COMPUTING LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A processor for scheduling instructions, comprising:
a scheduling entry array circuit comprising a plurality of scheduling entries, each scheduling entry configured to store first operation source parent information; and
a compare array circuit configured to:
receive the first operation source parent information from the scheduling entry array circuit; and
perform a dependency comparison with a first source parent of a plurality of source parents based on the first operation source parent information;

wherein:
each of the plurality of source parents is associated with an execution pipeline of a plurality of execution pipelines; and
the processor is configured to perform the dependency comparison by being configured to:
select, using the first operation source parent information, an associated execution pipeline from among the plurality of execution pipelines on which to perform the dependency comparison;
select, using the first operation source parent information, information from the associated execution pipeline; and
perform the dependency comparison only against the information from the associated execution pipeline.