Patent ID: 11914708
Assignee: INFINEON TECHNOLOGIES AG
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 27:
28. A method, comprising:
generating, by a first processing circuit, a first output based on an input;
generating, by a second processing circuit, a second output based on the input set, wherein the input set used by the second processing circuit is the same as the input set used by the first processing circuit;
generating, by a random sequence generator, a random bit sequence;
selecting, by a delay selector, a delay from among a plurality of selectable delays for output from the delay selector based on the random bit sequence, wherein the plurality of selectable delays include integer multiples of a clock cycle;
delaying, by a first delay circuit, the input set from being received at the first processing circuit based on the delay selected by the delay selector;
delaying, by a second delay circuit, the second output based on the delay selected by the delay selector;
generating, by a fault detection circuit, a comparison result based on comparing the first input with the delayed second output; and
detecting a fault, by the fault detection circuit, when the comparison result indicates that that a deviation between the first output and the delayed second output is present.