Patent ID: 11929110
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 11:
12. The memory circuit of claim 11, further comprising:
a second word line driver circuit comprising:
a second set of repeater circuits configured to generate the first set of local pre-decoder signals in response to the first set of global pre-decoder signals, and to generate the second set of local pre-decoder signals in response to the second set of global pre-decoder signals; and
a second set of word line post-decoder circuits coupled to the first clock pre-decoder circuit and the second set of repeater circuits, and configured to generate a second set of word line signals in response to the second set of clock signals, the first set of local pre-decoder signals and the second set of local pre-decoder signals.