Patent ID: 11921558
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 17:
18. A system comprising:
a processor comprising:
a first plurality of cores to execute instructions;
a second plurality of cores to execute instructions, the second plurality of cores heterogenous to the first plurality of cores;
a power controller to control, based at least in part on network traffic metadata, power consumption of the first plurality of cores and the second plurality of cores; and
a hardware feedback circuit coupled to at least the second plurality of cores, the hardware feedback circuit to provide, based at least in part on the network traffic metadata, hint information to a scheduler to cause the scheduler to schedule a workload on one or more of the second plurality of cores, the second plurality of cores having lower power consumption than the first plurality of cores;
a memory hierarchy coupled to the processor, the memory hierarchy comprising a system memory and a system cache coupled to the system memory; and
a memory controller coupled to the memory hierarchy, the memory controller to control, based at least in part on the network traffic metadata, a configuration of the memory hierarchy.