Patent ID: 11862435
Assignee: LAM RESEARCH CORPORATION
Field: Electrical machinery, apparatus, energy (Electrical engineering)
Classification: CPC H  C | IPC C  H

Claim 0:
1. A method for creating a high impedance path for reducing parasitic plasma in a process chamber including an electrode and a conducting structure, the method comprising:
selecting a number of a plurality of dielectric layers to arrange between the electrode and a first surface of the conducting structure;
selecting respective sizes of (i) a first gap between the electrode and a first one of the plurality of dielectric layers, (ii) a second gap between adjacent ones of the plurality of dielectric layers, and (iii) a third gap between a last one of the plurality of dielectric layers and the first surface,
wherein selecting the number of the plurality of dielectric layers and the respective sizes includes selecting the number of the plurality of dielectric layers and the respective sizes to prevent parasitic plasma between the first surface and the electrode during a semiconductor process performed in the process chamber; and
vertically arranging the selected number of the plurality of dielectric layers in a vertical stack between the electrode and the first surface of the conducting structure in accordance with the selected respective sizes of the first gap, the second gap, and the third gap.