Patent ID: 11923296
Assignee: RENESAS ELECTRONICS CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. The semiconductor device according to claim 1,
wherein the second portion has a second tapered portion and a second pad portion in plan view,
wherein the second tapered portion is connected to the first portion and arranged between the first portion and the second pad portion,
wherein the second tapered portion is configured such that a wiring width of the second tapered portion gradually increases from the first portion toward the second pad portion in plan view,
wherein the third portion has a third tapered portion and a third pad portion in plan view,
wherein the third tapered portion is connected to the first portion and arranged between the first portion and the third pad portion, and
wherein the third tapered portion is configured such that a wiring width of the third tapered portion gradually increases from the first portion toward the third pad portion in plan view.