Patent ID: 11925011
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 2:
3. The memory structure of claim 1, wherein the p-type epitaxial source/drains are first p-type epitaxial source/drains and the dummy FinFET further includes:
a third p-type semiconductor fin extending from the second p-well, wherein the third p-type semiconductor fin extends lengthwise along the second direction, the third p-type semiconductor fin has the second width along the first direction, and a spacing is along the first direction between the second p-type semiconductor fin and the third p-type semiconductor fin;
second p-type epitaxial source/drains disposed on the third p-type semiconductor fin; and
a source/drain contact disposed over one of the first p-type epitaxial source/drains and one of the second p-type epitaxial source/drains, wherein the source/drain contact extends along and spans the spacing between the second p-type semiconductor fin and the third p-type semiconductor fin along the first direction.