Patent ID: 11942282
Assignee: NATIONAL TECHNOLOGY & ENGINEERING SOLUTIONS OF SANDIA, LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 18:
19. An analog memory device comprising:
a source contact;
a drain contact;
a gate contact;
a channel layer disposed between the source contact and the drain contact, the channel layer having a variable conductance;
a reservoir layer having the gate contact deposited thereon;
an electrolyte layer positioned between the channel layer and the reservoir layer, wherein:
when a write operation is performed on the analog memory device, the analog memory device is heated to a temperature above a state transition temperature of the electrolyte layer and a write voltage is applied between the gate contact and one of the source contact or the drain contact, resulting in ions migrating between the reservoir layer and the channel layer by way if the electrolyte layer, wherein the conductance of the channel layer changes responsive to the ions migrating between the reservoir layer and the channel layer, and
when a read operation is performed on the analog memory device, the analog memory device has a temperature that is below the state transition temperature of the electrolyte layer and a read voltage is applied between the source contact and the drain contact to obtain a value of the conductance of the channel layer, where the conductance of the channel layer is substantially invariant when the analog memory device has the temperature that is below the state transition temperature of the electrolyte layer.