Patent ID: 11948939
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. An integrated circuit, comprising:
a substrate;
first and second active source/drain (S/D) regions disposed on or within the substrate;
an active gate structure with a gate fill layer disposed on the substrate;
first and second dummy S/D regions disposed on or within the substrate;
a dummy gate structure disposed on the substrate, wherein the dummy gate structure comprises:
a first gate fill layer;
a second gate fill layer that is different from the first gate fill layer;
a first gate dielectric layer surrounding the first gate fill layer; and
a second gate dielectric layer surrounding the second gate fill layer,
wherein a vertical sidewall of the first gate dielectric layer is in contact with a vertical sidewall of the second dielectric layer, and
wherein the first gate fill layer has a first top surface area and the second gate fill layer has a second top surface area that is substantially equal to the first top surface area.