Patent ID: 11864143
Assignee: REALTEK SEMICONDUCTOR CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 3:
4. The method for adjusting target clock according to claim 1, wherein when the time interval is greater than or equal to the target value, the frequency error is calculated according to, Err
    =
    
      
        
          
            P
            n
          
          -
          
            P
            
              n
              -
              1
            
          
        
        
          PKT
          target
        
      
      -
      1
    
  
  ,, and a frequency value of the target clock is decreased according to the frequency error, wherein Err represents the frequency error, Pn−Pn-1 represents the time interval, and PKTtarget represents the target value.