Patent ID: 11903210
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A semiconductor memory device, comprising:
a first chip having a first bonding surface extending in a first direction and a second direction crossing the first direction, the first chip including:
a plurality of word lines each extending in the first direction and the second direction and stacked in a third direction crossing the first direction and the second direction, one ends of the word lines in the first direction form a contact portion in which the end of each word line being exposed from the neighboring word line at one side thereof in the third direction when viewed in the third direction,
a semiconductor pillar piercing the word lines in the third direction,
a charge storage member provided between the semiconductor pillar and the word lines,
a plurality of first pads having first pad faces, respectively, aligned with the first bonding surface, and
a plurality of contact plugs each extending in the third direction to reach a corresponding one of the word lines at the contact portion and being electrically connected to a corresponding one of the first pads; and

a second chip having a second bonding surface extending in the first direction and the second direction, the second chip including:
a semiconductor substrate,
a plurality of transistors formed in the semiconductor substrate and aligned along the first direction, each of the transistors having a source, a drain, and a gate electrode, and the source, the gate electrode, and the drain of each of the transistors being aligned along the second direction, and
a plurality of second pads having second pad faces, respectively, aligned with the second bonding surface, and each being electrically connected to the source or the drain of a corresponding one of the transistors, wherein

the contact portion includes:
a first staircase portion including the exposed ends of a first part of the word lines, each of the exposed ends of the first part of the word lines having a first length in the first direction,
a second staircase portion including the exposed ends of a second part of the word lines, each of the exposed ends of the second part of the word lines having the first length in the first direction, and
a terrace portion including the exposed end of at least one of the word lines, the terrace portion being provided between the first staircase portion and the second staircase portion in the first direction, the terrace portion having a second length in the first direction, the second length being longer than the first length,

the transistors include:
a first transistor at least partially overlapping with the terrace portion when viewed in the third direction, and
a second transistor at east partially overlapping with the terrace portion when viewed in the third direction, and

a distance between a geometric center of the first transistor and a geometric center of the second transistor in the first direction is longer than the first length and shorter than the second length.