Patent ID: 11881275
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. The BIST system of claim 1, wherein:
the memory cell is a first memory cell of the memory array that further includes second through n memory cells, where n is a positive integer of 3 or more;
the processor is further configured to execute a read instruction directed to each of the second through n memory cells of the memory array, wherein each of the second through n memory cells has a nominal wordline voltage and the corresponding read instruction specifies a corresponding modulated wordline voltage that is different from the nominal wordline voltage of that memory cell;
the address/data generator is further configured to generate an expected value for each of the second through n memory cells;
the wordline margin control is further configured to provide a wordline of each of the second to nth memory cells, the corresponding modulated wordline voltage based on the corresponding read instruction;
the write/read control generator is further configured to obtain a cell value from each of the second through n memory cells using the corresponding modulated wordline voltage; and
the comparator is further configured to compare each cell value of the second to n memory cells to the corresponding expected value.