Patent ID: 11960426
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A multiprocessor computer system comprising:
a first processing drawer comprising a first processing cluster comprising a first processing chip and a second processing chip;
a second processing drawer comprising a second processing cluster comprising a third processing chip and fourth processing chip; and
a cable pair that communicatively connects the first processing cluster to the second processing cluster, the cable pair comprising:
a first cable comprising a first plurality of data lanes consisting of a first data lane group and a second data lane group, wherein the first data lane group primarily communicatively connects the first processing chip to the third processing chip and wherein the second data lane group secondarily communicatively connects the second processing chip to the fourth processing chip;
a second cable comprising a second plurality of data lanes consisting of a third data lane group and a fourth data lane group, wherein the third data lane group secondarily communicatively connects the first processing chip to the third processing chip and wherein the flan fourth data lane group primarily communicatively connects the second processing chip to the fourth processing chip;
wherein the first data lane group and the fourth data lane group have more data lanes relative to the second data lane group and the third data lane group, respectively;
one or more interfaces that prohibit communicative connection through the first cable when the first data lane group is operating in a degraded state and permit communicative connection through the second cable when the third data lane group and the fourth data lane group each comprise at least a threshold number of operational data lanes, wherein the threshold number of data lanes is the smallest majority of data lanes within the fourth data lane group.