Patent ID: 11940929
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. An apparatus comprising:
a cache memory that includes a first memory bank and a second memory bank;
an interface configured to be coupled to a central processing unit, the interface to obtain a write operation from the central processing unit that specifies to write a first set of data to the first memory bank and a second set of data to the second memory bank;
a cache controller coupled between the interface and the cache memory; and
bank processing logic coupled to the cache controller, the bank processing logic to:
determine that the first set of data corresponds to a data width of the first memory bank and that the second set of data is less than a data width of the second memory bank;
provide a first instruction to the cache controller to perform a partial read-modify-write operation to write the first set of data to the first memory bank; and
provide a second instruction to the cache controller to perform a full read-modify-write operation to write the second set of data to the second memory bank.