Patent ID: 11860680
Assignee: JFROG LTD.
Field: Digital communication (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 11:
12. A system for sharing validation information of a software release associated with multiple development stages, the system comprising:
at least one memory storing instructions; and
one or more processors coupled to the at least one memory, the one or more processors configured to execute the instructions to cause the one or more processors to:
obtain one or more files associated with the software release based on performance of at least a portion of a development process that includes the multiple development stages, where performance of at least the portion of the development process generates data components associated with general development parameters, one or more development stages of the multiple development stages, or a combination thereof;
generate, based on a master key accessible to the one or more processors and that operates as a private cryptographic key for a universal artifact repository, a private key and a public key;
for each of the data components:
generate a digital signature based at least in part on the respective data component and the private key; and
add an entry that includes the digital signature to a secure data structure accessible to one or more node devices, the entry added based on a previous entry in the secure data structure; and

initiate transmission of the data components, the public key, and the one or more files to the one or more node devices.