Patent ID: 11879917
Assignee: MITSUBISHI ELECTRIC CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 4:
5. The phase detector according to claim 2, wherein
the phase difference calculating circuit includes:
a first difference circuit to subtract a sum of the fifth multiplication signal and the seventh multiplication signal from a sum of the first multiplication signal and the third multiplication signal, and output a first difference signal indicating a result of the subtraction;
a second difference circuit to subtract a sum of the sixth multiplication signal and the eighth multiplication signal from a sum of the second multiplication signal and the fourth multiplication signal, and output a second difference signal indicating a result of the subtraction;
a third difference circuit to subtract a sum of the sixth multiplication signal and the eighth multiplication signal from a sum of the first multiplication signal and the third multiplication signal, and output a third difference signal indicating a result of the subtraction;
a fourth difference circuit to subtract a sum of the fifth multiplication signal and the seventh multiplication signal from a sum of the second multiplication signal and the fourth multiplication signal, and output a fourth difference signal indicating a result of the subtraction;
a first subtraction circuit to subtract the second difference signal from the first difference signal, and output a first subtraction signal indicating a result of the subtraction;
a second subtraction circuit to subtract the third difference signal from the fourth difference signal, and output a second subtraction signal indicating a result of the subtraction;
a filter to remove a high-frequency component included in the second subtraction signal, and output the second subtraction signal after removal of the high-frequency component; and
a calculation processing circuit to calculate a phase difference between the first differential signal and the second differential signal from the first subtraction signal output from the first subtraction circuit and the second subtraction signal after removal of the high-frequency component output from the filter.