Patent ID: 11934303
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus, comprising:
a controller coupled with a memory system, wherein the controller is configured to cause the apparatus to:
receive a sequence of data comprising a first set of data and a second set of data from a same application of a host system;
determine, based at least in part on the sequence of data, a first set of contiguous logical addresses for the first set of data and a second set of contiguous logical addresses for the second set of data; and
transmit, to the memory system based at least in part on the first set of data and the second set of data being from the same application, a write command that indicates the first set of contiguous logical addresses and the second set of contiguous logical addresses and that indicates the memory system is to track a storage status of the sequence of data, the first set of contiguous logical addresses being discontiguous with the second set of contiguous logical addresses.