Patent ID: 11907528
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 18:
19. A processing system comprising:
a plurality of processors including a first processor and a second processor, wherein the second processor includes a memory interface;
a cache memory coupled to the plurality of processors;
a bridge circuit, wherein the second processor is coupled to the cache memory by the bridge circuit; and
a shared memory controller comprising:
circuitry configured to receive a memory management command having a specification to perform a memory management operation to load data into a memory location of the cache memory before the first processor executes an input/output instruction that requests the data from the memory location;
formatting circuitry configured to format the memory management command into a formatted command; and
routing circuitry configured to route the formatted command based on the specification to the bridge circuit; and
response circuitry configured to receive a first response from the bridge circuit,

wherein the bridge circuit is configured to:
translate the formatted command into an op code;
transmit the op code to the memory interface of the second processor;
receive a second response from the second processor indicating the data was loaded into the memory location; and
send the first response to the response circuitry indicating the data was loaded into the memory location.