Patent ID: 11894043
Assignee: INTEGRATED SILICON SOLUTION INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. The management method of the power management circuit in the low-power double data rate memory of claim 15, wherein in the voltage regulating step, the control signal is configured to turn on and off the another low dropout regulator;
in response to determining that the control signal is at a high voltage level, the another low dropout regulator is turned on to enter a normal mode and adjusts the second voltage difference between the third voltage of the third transmitting terminal and the first voltage of the fourth transmitting terminal according to the another reference voltage; and
in response to determining that the control signal is at a low voltage level, the another low dropout regulator is turned off to enter a standby mode, and reduces the third voltage difference between the fourth voltage of the fifth transmitting terminal and the first voltage of the fourth transmitting terminal.