Patent ID: 11876079
Assignee: NANYA TECHNOLOGY CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for fabricating a semiconductor device, comprising:
performing a bonding process to bond a second die onto a first die comprising a pad layer;
forming a through-substrate opening along the second die and extending to the pad layer in the first die;
conformally forming an isolation layer in the through-substrate opening;
performing a punch etch process to remove a portion of the isolation layer and expose a portion of a top surface of the pad layer;
performing an isotropic etch process to form a recessed space extending from the through substrate opening and in the pad layer;
conformally forming a barrier layer in the through-substrate opening and the recessed space; and
forming a filler layer in the through-substrate opening and the recessed space.