Patent ID: 11868694
Assignee: SYNOPSYS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. The system of claim 1, wherein the processor executes the operations to further:
generate a divided clock of the clock for a second set of sequential elements of the plurality of sequential elements;
analyze each of the second set of sequential elements of the plurality of sequential elements to determine an edge of a clock signal pattern of the divided clock associated with each of the second set of sequential elements causing an output change at corresponding one or more sequential elements of the second set of sequential elements; and
emulate the one or more cycles of the clock signal pattern of the clock that are discarded upon determining that the one or more discarded cycles include the edge of the clock signal pattern of the divided clock that causes at least one sequential element of the second set of sequential elements to change the output.