Patent ID: 11860814
Assignee: KONDA TECHNOLOGIES INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A scalable distributed computing system comprising:
wherein said scalable distributed computing system further comprising an α×b processing elements arranged in a two dimensional grid with one side of said two dimensional grid having the size of α processing elements and the other side of said two dimensional grid having the size of b processing elements where α>2, b>2, and both α and b are non-negative numbers; and
Wherein said α×b processing elements are numbered with a representation in binary format having n bits, where 2n−1<α×b≤2n and where n is a positive number; and
Wherein said α×b processing elements are arranged in said two dimensional grid so that a first processing element of said α×b processing elements is placed 2k hops away either vertically or horizontally from a second processing element of said α×b processing elements when said all n bits of said representation in binary format of said first processing element and said representation in binary format of said second processing element are the same in each bit excepting in one of either (2×k+1)th least significant bit or (2×k+2)th least significant bit differ where k is a non-negative number; and
Wherein each processing element of said α×b processing elements arranged in said two dimensional grid connected to an interconnect comprising one or more switches; and
Wherein said one or more switches arranged consecutively starting from a first switch and ending with a last switch, each switch of said one or more switches having an inlet bus and an outlet bus, each switch of said one or more switches, excepting said last switch connected to its succeeding switch by a forward bus and each switch of said one or more switches, excepting said first switch connected to its preceding switch by a backward bus; and
Wherein a switch of said one or more switches of a first processing element of said α×b processing elements is connected, by a 2k hop length horizontal bus or a 2k hop length vertical bus, to a switch of said one or more switches of a second processing element of said α×b processing elements when said all n bits of said representation in binary format of said first processing element and said representation in binary format of said second processing element are the same in each bit excepting in one of either (2×k+1)th least significant bit or (2×k+2)th least significant bit differ where k is a non-negative number and also said switch of said one or more switches of said first processing element of said α×b processing elements is connected, by a 2k hop length horizontal bus or a 2k hop length vertical bus, from said switch of said one or more switches of said second processing element of said α×b processing elements when said all n bits of said representation in binary format of said first processing element and said representation in binary format of said second processing element are the same in each bit excepting in one of either (2×k+1)th least significant bit or (2×k+2)th least significant bit differ where k is a non-negative number so that said interconnect of each processing element of said α×b processing elements comprising one or more horizontal buses connecting to said interconnect of one or more processing elements of said α×b processing elements and said interconnect of each processing element of said α×b processing elements comprising one or more vertical buses connecting to said interconnect of one or more processing elements of said α×b processing elements.