Patent ID: 11909748
Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. The anti-fraud control system according to claim 7, wherein
in the first error monitoring device,
the first hardware error detector causes the first frame transmitting and receiving hardware unit to transmit a transition frame for invalidating one branch among the branches to prepare a period in which at least one of the one or more second error monitoring devices connected to the one branch shifts to the invalidation mode and others of the one or more second error monitoring devices connected to one or more of the branches other than the one branch do not shift to the invalidation mode, and detects a total number of error notification frames received from the at least one of the one or more second error monitoring devices during the period,
after a lapse of a predetermined time after the first frame transmitting and receiving hardware unit has transmitted the transition frame, the first hardware error detector causes the first frame transmitting and receiving hardware unit to transmit another transition frame for invalidating another branch among the branches to cause the first frame transmitting and receiving hardware unit to transmit transition frames for sequentially invalidating the branches, and
one of the branches detected as having a maximum number of error notification frames is determined as an unauthorized branch.