Patent ID: 11892955
Assignee: MICROCHIP TECHNOLOGY INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 18:
19. The CXL memory controller of claim 12, comprising:
the physical layer of the CXL memory controller to receive the plurality of CXL flits, to transmit the plurality of CXL flits to the read bypass detection logic and to transmit the plurality of CXL flits to the arbitration/multiplexing layer of the CXL memory controller;
the arbitration/multiplexing layer to identify one or more link layer memory read requests from the plurality of CXL flits and to transmit the one or more link layer memory read requests to the link layer; and
the link layer to perform a cyclic redundancy check (CRC) on each of the one or more link layer memory read requests, to transmit the link layer memory read requests that pass the CRC to the transaction/application layer of the CXL memory controller and to discard the link layer memory read requests that fail the CRC.