Patent ID: 11961792
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 19:
20. The method as claimed in claim 19,
wherein the second seed layer and the second conductive pattern include a pad layer and an under-bump metallurgy (UBM) layer, the pad layer being portions of the second seed layer and the second conductive pattern that are enveloped by the second insulating layer, and the UBM layer being portions of the second seed layer and the second conductive pattern that are enveloped by the first insulating layer,
wherein the UBM layer includes a body portion and a protrusion protruding from the body portion and arranged in the recess area,
wherein a side surface of the body portion extends from a lower surface of the pad layer provided on the first insulating layer and forms an obtuse angle with respect to the lower surface of the pad layer, and
wherein a horizontal width of the protrusion is less than a horizontal width of the body portion.