Patent ID: 11895831
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. A manufacturing method for memory, comprising:
providing a substrate, and forming a first isolation layer and discrete bit lines on the substrate, wherein the bit lines extend along a first direction, and the first isolation layer is located on surfaces of the bit lines away from the substrate and further located between adjacent bit lines;
removing part of the first isolation layer by a thickness to form through holes arranged in an array, wherein the through holes expose part of the surface of the bit lines, and forming an active layer filling the through holes;
removing part of the first isolation layer to form discrete first trenches, wherein the first trenches extend along a second direction, and the second direction is different from the first direction; and the first trenches expose a first side face and a second side face of the active layer, the first side face and the second side face are arranged oppositely;
forming a first dielectric layer on the first side face, and forming a second dielectric layer on the second side face, wherein a thickness of an equivalent-gate dielectric layer of the first dielectric layer is greater than a thickness of an equivalent-gate dielectric layer of the second dielectric layer; and
forming word lines filling the first trenches after the first dielectric layer and the second dielectric layer are formed.