Patent ID: 11949629
Assignee: ASTERA LABS, INC.
Field: Digital communication (Electrical engineering)
Classification: CPC G  H | IPC H

Claim 8:
9. An integrated circuit component comprising:
symbol-stream reception circuitry to receive a first stream of fixed-length blocks of symbols having first length-modifiable blocks of symbols spaced from one another at first intervals within the first stream;
symbol-stream synthesizing circuitry to (i) generate a second stream of fixed-length blocks of symbols throughout a first time period in which the symbol-stream reception circuitry is idle and receives no constituent symbols of the first stream, and (ii) embed second length-modifiable blocks of symbols at second intervals within the second stream of fixed-length blocks of symbols, the symbol-stream synthesizing circuitry including stream alignment circuitry to adjust lengths of successive ones of the second length-modifiable blocks relative to counterpart ones of the first length-modifiable blocks to reduce a temporal misalignment between the first and second intervals; and
output circuitry to output from the integrated circuit component:
the first stream of fixed-length blocks of symbols prior to the first time period;
the second stream of fixed-length blocks of symbols instead of the first stream of fixed-length blocks of symbols during the first time period; and
the first stream of fixed-length blocks of symbols following a second time period that transpires after the first time period and during which (i) the symbol-stream circuitry reverts to reception of the first stream of fixed-length blocks of symbols having the first length-modifiable blocks of symbols spaced from one another at the first intervals, and (ii) the stream alignment circuitry adjusts the lengths of the successive ones of the second length-modifiable blocks relative to the counterpart ones of the first length-modifiable blocks to reduce the temporal misalignment between the first and second intervals.