Patent ID: 11903258
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 8:
9. A preparation method of a display substrate comprising a plurality of pixel units arranged in a matrix, wherein the pixel units each comprise a plurality of sub-pixels, and the method comprises:
forming sequentially a silicon substrate, a micro-cavity modulation layer and an emitting structure layer in each of the sub-pixels, wherein the micro-cavity modulation layer has a reflective electrode formed therein, and the emitting structure layer comprises a first electrode, an emitting layer and a semi-transparent and semi-reflective second electrode which are sequentially formed on the micro-cavity modulation layer, and making a distance between the second electrode and the reflection electrode different in each sub-pixel; wherein
the pixel units each comprise a first sub-pixel, a second sub-pixel and a third sub-pixel adjacently arranged;
the first sub-pixel, the second sub-pixel and the third sub-pixel respectively comprise a first reflective electrode, a second reflective electrode and a third reflective electrode;
each of the second reflective electrode and the third reflective electrode is electrically connected to a drive transistor through a first connection electrode provided in a same layer as the first reflective electrode;
in the first sub-pixel, an orthographic projection of the drive transistor on the silicon substrate is located within an orthographic projection of the first reflective electrode on the silicon substrate;
in each of the second sub-pixel and the third sub-pixel, an orthographic projection of the drive transistor on the silicon substrate is located within an orthographic projection of the first connecting electrode on the silicon substrate;
the preparation method comprises: forming a driving circuit layer on the silicon substrate, wherein the driving circuit layer comprises the driving transistor having a drain electrode, the micro-cavity modulation layer is formed on the driving circuit layer, and the emitting structure layer is formed on the micro-cavity modulation layer;
wherein forming the micro-cavity modulation layer comprises:
forming the first reflective electrode and the first connection electrode on the driving circuit layer, wherein the first reflective electrode is formed in the first sub-pixel and is connected with a drain electrode of the driving transistor through a first via provided in the driving circuit layer, and the first connection electrode is formed in each of the second sub-pixel and the third sub-pixel and is connected with a drain electrode of the driving transistor through a first via provided in the driving circuit layer;
forming a first modulation layer covering the first reflective electrode and the first connection electrode, wherein each sub-pixel has a second via formed on the first modulation layer, a second via of the first sub-pixel exposes the first reflective electrode, and each of second vias of the second sub-pixel and the third sub-pixel exposes the first connection electrode;
forming a first connection block in each sub-pixel's second via, wherein the first reflective electrode is connected with a first connection block of the first sub-pixel, and the first connection electrode of the second sub-pixel and the first connection electrode of the third sub-pixel are connected with a first connection block of the second sub-pixel and a first connection block of the third sub-pixel respectively;
forming the second reflective electrode and a second connection electrode on the first modulation layer, wherein the second reflective electrode is formed in the second sub-pixel and connected with the first connection block of the second sub-pixel, and the second connection electrode is formed in the third sub-pixel and connected with the first connection block of the third sub-pixel;
forming a second modulation layer covering the second reflective electrode and the second connection electrode, wherein each sub-pixel has a third via formed on the second modulation layer, a third via of the first sub-pixel exposes the first connection block of the first sub-pixel, a third via of the second sub-pixel exposes the second reflective electrode, and a third via of the third sub-pixel exposes the second connection electrode;
forming a second connection block in each sub-pixel's third via, wherein the first connection block is connected with a second connection block of the first sub-pixel, the reflective electrode is connected with a second connection block of the second sub-pixel, and the second connection electrode is connected with a second connection block of the third sub-pixel;
forming the third reflective electrode on the second modulation layer, wherein the third reflective electrode is formed in the third sub-pixel and connected with the second connection block of the third sub-pixel; and
forming a third modulation layer covering the third reflective electrode, wherein each sub-pixel has a fourth via formed on the third modulation layer, a fourth via of the first sub-pixel and a fourth via of the second sub-pixel respectively expose the second connection block of the first sub-pixel and the second connection block of the second sub-pixel, and a fourth via of the third sub-pixel exposes the third reflective electrode.