Patent ID: 11889692
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A vertical memory device, comprising:
a substrate;
a plurality of channels extending in a first direction substantially vertical to a top surface of the substrate;
a plurality of gate lines arranged and spaced apart from one another along the first direction, wherein the plurality of gate lines surround the channels;
a plurality of common wirings electrically connected to the gate lines;
a plurality of first contacts extending in the first direction, wherein a first end of each first contact is connected to a corresponding common wiring from among the common wirings, and a second end of each first contact is connected to a corresponding gate line from among the gate lines,
wherein the second ends of the first contacts are disposed at different levels from one another,
wherein an uppermost gate line from among the gate lines is connected to a corresponding common wiring via a corresponding first contact;
a plurality of first signal wirings electrically connected to lower gate lines from among the gate lines via the common wirings; and
a plurality of second signal wirings electrically connected to upper gate lines from among the gate lines via the common wirings,
wherein the second signal wirings are disposed higher than the first signal wirings in the first direction, the first signal wirings are electrically connected to adjacent common wirings from among the common wirings, and the second signal wirings are electrically connected to adjacent common wirings from among the common wirings,
wherein, in a plan view, the first signal wirings are not disposed between the second signal wirings, and the second signal wirings are not disposed between the first signal wirings.