Patent ID: 11907544
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 33:
34. An apparatus comprising:
at least one memory array;
error correction code (ECC) logic configured to perform an ECC process for data stored in the at least one memory array;
a buffer memory; and
control circuitry that is configured to perform an automated error correction process with memory refresh, the automated error correction process comprising:
determining that a memory address of the at least one memory array is associated with at least one bit-error during a read operation using the ECC logic, the read operation corresponding to an external data access request;
writing the memory address to the buffer memory;
entering a self-refresh mode for the at least one memory array;
determining that a refresh address matches the memory address; and
correcting the at least one bit-error in conjunction with refreshing one or more memory cells that are represented by the refresh address.