Patent ID: 11893943
Assignee: CHONGQING BOE DISPLAY TECHNOLOGY CO.,LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. A display substrate, comprising a display region and a peripheral region on a periphery of the display region, wherein multiple sub-pixels are arranged in the display region; a gate driving circuit is arranged in the peripheral region, and the gate driving circuit comprises multiple cascaded first shift register units, the first shift register unit being the shift register unit according to claim 1;
at least one sub-pixel comprises a light emitting element and a pixel circuit configured to drive the light emitting element to emit light; and
a nth-stage first shift register unit of the gate driving circuit is configured to provide a gate driving signal to a pixel circuit of a sub-pixel of an nth row, n being an integer greater than 0;
wherein the pixel circuit configured to drive the light emitting element to emit light comprises a data writing sub-circuit, a driving sub-circuit, a storage sub-circuit, a compensation sub-circuit, a level holding sub-circuit, a light emitting control sub-circuit, a first initialization sub-circuit, and a second initialization sub-circuit;
the data writing sub-circuit is connected with a data line, a first scanning line, and a second node, and is configured to write a signal of the data line to the storage sub-circuit under control of the first scanning line; the driving sub-circuit is connected with a third power line, a first node, and a third node, and is configured to output a driving current to the light emitting control sub-circuit through the third node under control of the first node; the storage sub-circuit is connected with the first node and the second node; the level holding sub-circuit is connected with the third power line and the second node, and is configured to hold a potential of the second node; the compensation sub-circuit is connected with a second scanning line, the first node, and the third node, and is configured to compensate a threshold voltage of the driving sub-circuit under control of the second scanning line; the first initialization sub-circuit is connected with a first reset signal line, an initial voltage line, and the first node, and is configured to initialize the first node under control of the first reset signal line; the second initialization sub-circuit is connected with a second reset signal line, a reference voltage line, and the second node, and is configured to initialize the second node under control of the second reset signal line; the light emitting control sub-circuit is connected with a light emitting control line, the third node, and a first electrode of the light emitting element, and is configured to, under control of the light emitting control line, drive the light emitting element according to the driving current to emit light; a second electrode of the light emitting element is connected with a fourth power line;
writing time when the data writing sub-circuit writes the signal of the data line to the storage sub-circuit is shorter than compensation time when the compensation sub-circuit compensates the threshold voltage of the driving sub-circuit;
a third output terminal of the nth-stage first shift register unit of the gate driving circuit is connected with a second reset signal line driving the pixel circuit of the sub-pixel of the nth row; and a second output terminal of the nth-stage first shift register unit is connected with a second scanning line driving the pixel circuit of the sub-pixel of the nth row.