Patent ID: 11870429
Assignee: NAVITAS SEMICONDUCTOR LIMITED
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 16:
17. A method of forming a circuit, the method comprising:
forming a semiconductor substrate;
forming a bidirectional transistor on the semiconductor substrate, the bidirectional transistor including a first source node, a second source node and a common drain node;
forming a first transistor on the substrate, the first transistor including a first source terminal, a first drain terminal and a first gate terminal, the first source terminal connected to the substrate, the first drain terminal connected to the first source node and the first gate terminal connected to the second source node;
forming a second transistor on the substrate, the second transistor including a second source terminal, a second drain terminal and a second gate terminal, the second source terminal connected to the substrate, the second drain terminal connected to the second source node, wherein the second transistor is arranged to transition from an off state to an on state in response to the first source node at a positive voltage relative to a voltage of the semiconductor substrate;
forming a third transistor on the substrate, the third transistor including a third drain, a third source, and a third gate, the third gate connected to a voltage source, the third drain connected to the first source node and the third source connected to the second gate terminal; and
forming a fourth transistor on the substrate, the fourth transistor including a fourth drain, a fourth source, and a fourth gate, the fourth gate connected to the voltage source, the fourth drain connected to the second source node, and the fourth source connected to the first gate terminal.