Patent ID: 11961569
Assignee: WINBOND ELECTRONICS CORP.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 11:
12. The clock-generating circuit as claimed in claim 3, wherein the second clock signal is provided to a memory controller and a flash memory which are coupled to each other through a bus,
wherein when the memory controller executes a read operation of the flash memory, the memory controller switches the enable signal from the low-logic state to the high-logic state, and starts counting a number of clock cycles elapsed by the second clock signal until the memory controller receives a data signal responded by the flash memory for the read operation,
wherein when a period obtained by multiplying a clock period of the second clock signal by the number of clock cycles is greater than a predetermined period, the memory controller determines that the read operation has failed,
wherein when the period obtained by multiplying the clock period of the second clock signal by the number of clock cycles is smaller than or equal to the predetermined period, the memory controller determines that the read operation has succeeded.