Patent ID: 11943979
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 5:
6. A fabrication method of an array substrate, the array substrate comprising a display region and a bonding region outside the display region, the fabrication method comprising:
forming a bonding electrode, the bonding electrode is located in the bonding region and spaced apart from an outer edge of the bonding region; and
forming an electrostatic barrier line, the electrostatic barrier line comprises one end electrically connected with the bonding electrode, and the other end extending to the outer edge of the bonding region, and resistivity of the electrostatic barrier line is larger than resistivity of the bonding electrode,
wherein the electrostatic barrier line is located outside the display region and on a side of the bonding electrode facing away from the display region, and the electrostatic barrier line is configured to prevent static electricity from entering inside of the array substrate from an edge of the array substrate,
wherein the fabrication method further comprises:
forming a semiconductor thin film on a base substrate;
patterning the semiconductor thin film to form an active layer and the electrostatic barrier line;
performing ion implantation on a source region and a drain region of the active layer as well as the electrostatic barrier line,

wherein after the patterning the semiconductor thin film and before the performing ion implantation, the fabrication method further comprises:
forming a gate insulating layer on a side of the active layer and the electrostatic barrier line that faces away from the base substrate;
forming a gate metal layer on a side of the gate insulating layer that faces away from the base substrate;
patterning the gate metal layer to form a gate electrode, and
wherein the performing ion implantation comprises: performing ion implantation by using the gate electrode as a mask:
forming the bonding electrode at a same time of patterning the gate metal layer to form the gate electrode; and
the fabrication method further comprises: forming a first via hole in the gate insulating layer, the bonding electrode is electrically connected with the electrostatic barrier line through the first via hole.