Patent ID: 11962301
Assignee: NVIDIA CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A Serializer/Deserializer (SERDES) system comprising:
a transmitter device comprising:
a serializer;
a phase-locked loop (PLL) coupled to the serializer, the PLL to provide a first set of N phase signals to the serializer, wherein the PLL comprises:
a first ring oscillator comprising a first set of M delay stages, each stage to output a phase signal, wherein M is a positive integer greater than one; and
a first phase selector circuit coupled to the first ring oscillator, wherein the first phase selector circuit is to:
receive a first set of M phase signals from the first ring oscillator; and
generate the first set of N phase signals from the first set of M phase signals at a time, wherein N is a positive integer less than M and greater than one, wherein the first ring oscillator comprises a first oscillation frequency that is less than a second frequency of the N phase signals.