Patent ID: 11862602
Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A microelectronic assembly, comprising: a semiconductor wafer having first and second opposite surfaces, the semiconductor wafer having a grid of sixteen network nodes electrically connected to one another via local adjacent connections each extending in only one of first and second horizontal orthogonal directions, the sixteen network nodes connecting to a plurality of processor cores of a hierarchical mesh network;
an interconnection structure comprising a low-loss dielectric material and having first and second opposite surfaces, the interconnection structure having electrical connections including local oblique connections each extending in only one of third and fourth horizontal oblique directions that are each oriented at an oblique angle relative to the first and second directions; and
wherein the first surface of the semiconductor wafer is directly hybrid bonded, without using an adhesive, to the first surface of the interconnection structure such that each of the network nodes is electrically connected with at least one of the other network nodes through at least one of the local adjacent connections and at least one of the local oblique connections,
wherein, the hierarchical mesh network is configured such that a maximum of two hops is needed for an electrical signal to travel from any one of the network nodes, through the interconnection structure, to any other one of the network nodes, and
wherein the maximum of two hops is a maximum of two direct electrical signal connections extending between the any one of the network nodes to the any other one of the network nodes.