Patent ID: 11942477
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor device, comprising:
a substrate;
a first active region and a second active region on the substrate, the first active region being spaced apart from the second active region;
an isolation region on the substrate, the isolation region including a region between the first active region and the second active region;
a first gate structure overlapping the first active region and the isolation region;
a second gate structure overlapping the second active region and the isolation region; and
a gate separation region between the first gate structure and the second gate structure,
wherein:
the first gate structure includes a first gate dielectric layer and a first gate electrode on the first gate dielectric layer,
the second gate structure includes a second gate dielectric layer and a second gate electrode on the second gate dielectric layer,
each of the first gate structure and the second gate structure has a line shape or bar shape extending in a first direction,
the first gate structure and the second gate structure are spaced apart from each other in the first direction,
the first gate structure, the gate separation region, and the second gate structure are sequentially arranged in the first direction,
a lower end of the gate separation region is at a lower level than an upper surface of the isolation region,
the gate separation region includes:
a first pattern including a first portion and a second portion; and
a second pattern on side surfaces of the first pattern,

at least a portion of the first portion has a dielectric constant that is higher than a dielectric constant of at least a portion of the second portion,
the gate separation region has a first width region and a second width region below the first width region,
a width of the second width region is greater than a width of the first width region in the first direction,
the second width region is adjacent to lower surfaces of the first and second gate structures, and
a lower surface of the gate separation region has a rounded shape.