Patent ID: 11917807
Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A memory device that uses a semiconductor element, in which a page is made up of a plurality of memory cells arranged in a row direction of a substrate, and a plurality of the pages is arranged in a column direction,
wherein each of the memory cells contained in each of the pages includes:
a semiconductor base material erected on the substrate in a vertical direction of the substrate or extended on the substrate in a horizontal direction,
a first impurity layer and a second impurity layer provided on opposite ends of the semiconductor base material,
a first gate insulating layer placed in contact with, or close to, the first impurity layer, partially or entirely surrounding a lateral surface of the semiconductor base material between the first impurity layer and the second impurity layer,
a second gate insulating layer joined to the first gate insulating layer and placed in contact with, or close to, the second impurity layer, surrounding the lateral surface of the semiconductor base material,
a first gate conductor layer covering part or all of the first gate insulating layer,
a second gate conductor layer covering the second gate insulating layer, and
a channel semiconductor layer in which the semiconductor base material is covered with the first gate insulating layer and the second gate insulating layer;

a page write operation and a page erase operation are performed by controlling voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer;
the first impurity layer of the memory cell is connected with a source line, the second impurity layer is connected with a bit line, one of the first gate conductor layer and the second gate conductor layer is connected with a word line, and another is connected with a drive control line; and
during the write operation after the page erase operation, a positive hole group is formed in the channel semiconductor layer by an impact ionization phenomenon by controlling voltages applied to the word line, the drive control line, the source line, and the bit line and an applied voltage/applied voltages of one or both of the word line and the drive control line is/are lowered with drops in a first threshold voltage of the first gate conductor layer and a second threshold voltage of the second gate conductor layer.