Patent ID: 11934830
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A processor for executing an instruction, the processor comprising:
a decode circuit to decode a single instruction by a decode circuit, the single instruction comprising an opcode, at least one source memory location identifier, a destination register identifier, a data readiness indicator identifying at least one data access condition, and a data readiness mask; and
an execution circuit to execute the decoded instruction to, for each data element of the identified source memory location,
determine whether the data access condition for that data element is satisfied, and in response to a determination that the data access condition for the data element is not satisfied to:
generate a prefetch request for the data element, and
set a value in a corresponding data element position of the identified destination register, and
set a masked value in a corresponding data element position of the data readiness mask.