Patent ID: 11917811
Assignee: WINBOND ELECTRONICS CORP.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 8:
9. The memory as claimed in claim 1, wherein the bit line structures comprise:
a conductive structure on the bit line contact structures;
an insulating cap layer on the conductive structure;
an insulating spacer between the conductive structure and the capacitor contact structure, and comprising:
a first spacer layer on a sidewall of the insulating cap layer and on a sidewall of the conductive structure;
a second spacer layer on the first spacer layer, wherein a top surface of the second spacer layer is lower than a top surface of the first spacer layer; and
a third spacer layer on the second spacer layer, wherein a top surface of the third spacer layer is lower than the top surface of the first spacer layer.