Patent ID: 11869567
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. The refresh control circuit of claim 5, wherein the timeout selection sub-circuit comprises:
a timing sub-circuit, configured to receive the row activation commands and the pre-charging commands to obtain the single enabling duration, and when the single enabling duration is greater than the preset duration, output timeout signals; and
a first latch sub-circuit, connected to an output end of the timing sub-circuit, and configured to: receive each of the L single-row addresses one by one, and receive, one by one, each timeout signal outputted by the timing sub-circuit, so as to output n single-row addresses corresponding to the n timeout signals; and when the timeout signals are received, output the single-row address last received before the timeout signals arrive.