Patent ID: 11907033
Assignee: LATTICE SEMICONDUCTOR CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 5:
6. The adaptive POR signal generator of claim 5, further comprising:
an oscillator configured to receive clock control signals from the logic device and provide a clock signal to the counter based, at least in part, on the clock control signals provided by the logic device;
wherein the initiating the incrementing count by the counter comprises:
generating the counter control signals to control the counter to count incrementally; and
generating the clock control signals to enable the oscillator and control the oscillator to provide the clock signal to the counter; and

wherein the initiating the decrementing count by the counter comprises:
generating the counter control signals to control the counter to count decrementally starting at the ramp time count; and
generating the clock control signals to enable the oscillator and control the oscillator to provide a modified clock signal to the counter, wherein the modified clock signal comprises a frequency based, at least in part, on the nominal operating voltage and the amount of time between the first and second supply voltage ramp traversals.