Patent ID: 11947456
Assignee: ADVANCED MICRO DEVICES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A device, comprising:
a first level of a multi-level memory hierarchy; and
a first controller of the first level of the multi-level memory hierarchy;
wherein the first controller of the first level of the multi-level memory hierarchy is configured to:
receive a weak exclusive read request for a speculatively executing store instruction;
process, by the first controller, the weak exclusive read request, by determining whether to invalidate one or more cache lines associated with the store instruction in one or more memories of the first level of the multi-level memory hierarchy; and
issue the weak exclusive read request to a second controller of a second level of the multi-level memory hierarchy, wherein the second controller is configured to process the weak exclusive read request.