Patent ID: 11901025
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A semiconductor memory device comprising:
a memory cell array including a plurality of memory cell rows, each including a plurality of volatile memory cells;
a row hammer management circuit configured to:
count each of access addresses associated with access to each of the plurality of memory cell rows to store counting values therein; and
determine a hammer address associated with at least one of the plurality of memory cell rows, which is intensively accessed, based on the counting values;

a repair control circuit including a plurality of repair controllers, each of the plurality of repair controllers configured to store a defective address storage, the repair control circuit configured to repair a defective memory cell row among from the plurality of memory cell rows; and
a connection logic configured to connect first repair controllers to the row hammer management circuit, the first repair controllers being a portion of the plurality of repair controllers unused for storing defective addresses,
wherein the row hammer management circuit is configured to use the first repair controllers as a storage resource to store a portion of the access addresses.