Patent ID: 11934809
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A performance-enhanced computing system comprising:
a network controller to obtain an application binary file, wherein the application binary file includes first binary code corresponding to vector functions and non-vector functions and intermediate representation data corresponding to the vector functions, and wherein the application binary file further includes a vector function information table;
a processor coupled to the network controller; and
a memory including a set of executable program instructions, which when executed by the processor, cause the computing system to:
generate a first compilation output based on the application binary file;
detect a capability change in an execution environment associated with the first compilation output; and
generate, in response to the detected capability change, a second compilation output based on the first compilation output;

wherein to generate the second compilation output, the instructions, when executed, further cause the computing system to:
map the intermediate representation data to a unified interface invocation;
generate, via the unified interface invocation, second binary code based on the intermediate representation data and the detected capability change;
embed the second binary code into the second compilation output;
update the vector capability list based on the execution environment;
embed the updated vector capability list into the second compilation output; and
update one or more binary location field entries in the vector function information table.