Patent ID: 11880328
Assignee: SHANGHAI CAMBRICON INFORMATION TECHNOLOGY CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. An NoC data processing method, comprising:
obtaining first operation data by using a first NoC processing module, wherein the first NoC processing module includes a first storage device and a plurality of first computation devices, and the first operation data is stored in the first storage device;
performing an operation on the first operation data through the plurality of the first computation devices in the first NoC processing module to obtain a first operation result, wherein the performing the operation on the first operation data includes:
performing a machine learning computation by each of the plurality of the first computation devices,
wherein each of the plurality of the first computation devices includes an operation unit and a controller unit, and
wherein the operation unit includes a primary processing circuit and a plurality of secondary processing circuits,
obtaining, by the controller unit, input data and a computation instruction,
parsing, by the controller unit, the computation instruction to obtain a plurality of operation instructions,
sending, by the controller unit, the plurality of operation instructions and the input data to the primary processing circuit,
performing, by the primary processing circuit, preorder processing on the input data,
sending, by the primary processing circuit, the data and the operation instructions to the primary processing circuit and the plurality of secondary processing circuits,
performing, by the plurality of secondary processing circuits, intermediate computations in parallel according to the data and the operation instructions sent by the primary processing circuit to obtain a plurality of intermediate results,
sending, by the plurality of secondary processing circuits, the plurality of intermediate results to the primary processing circuit, and
performing, by the primary processing circuit, postorder processing on the plurality of intermediate results to obtain a computation result of the computation instruction; and

sending the first operation result to a second NoC processing module.