Patent ID: 11861234
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
receiving data to write to a memory sub-system, wherein the memory sub-system comprises a single-level cell (SLC) cache and a multiple level cell (XLC) storage, wherein the SLC cache comprises a static SLC cache having a fixed size and dynamic SLC cache, wherein the dynamic SLC cache has a default maximum size corresponding to a first mode of operation and an enhanced maximum size greater than the default maximum size corresponding to a second mode of operation;
determining whether to initiate a write operation in the second mode to write the data;
in response to determining to initiate the write operation in the second mode, initiating the write operation in the second mode to write a first portion of the data to the SLC cache;
determining whether a logical saturation of the first portion of the data satisfies a first threshold condition based on the enhanced maximum size; and
in response to determining that the logical saturation of the first portion of the data does not satisfy the first threshold condition, continuing the write operation in the second mode to write a second portion of the data to the SLC cache.