Patent ID: 11879917
Assignee: MITSUBISHI ELECTRIC CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 2:
3. The phase detector according to claim 2, wherein
the phase difference calculating circuit includes:
a first addition circuit to add the first multiplication signal, the third multiplication signal, the fifth multiplication signal, and the seventh multiplication signal, and output a first addition signal indicating a result of the addition;
a second addition circuit to add the second multiplication signal, the fourth multiplication signal, the sixth multiplication signal, and the eighth multiplication signal, and output a second addition signal indicating a result of the addition;
a third addition circuit to add the first multiplication signal, the third multiplication signal, the sixth multiplication signal, and the eighth multiplication signal, and output a third addition signal indicating a result of the addition;
a fourth addition circuit to add the second multiplication signal, the fourth multiplication signal, the fifth multiplication signal, and the seventh multiplication signal, and output a fourth addition signal indicating a result of the addition;
a first subtraction circuit to subtract the second addition signal from the first addition signal, and output a first subtraction signal indicating a result of the subtraction;
a second subtraction circuit to subtract the third addition signal from the fourth addition signal, and output a second subtraction signal indicating a result of the subtraction;
a filter to remove a high-frequency component included in the first subtraction signal, and output the first subtraction signal after removal of the high-frequency component; and
a calculation processing circuit to calculate a phase difference between the first differential signal and the second differential signal from the first subtraction signal after removal of the high-frequency component output from the filter and the second subtraction signal output from the second subtraction circuit.