Patent ID: 11929110
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 10:
11. A memory circuit comprising:
a global control circuit configured to generate a first set of global pre-decoder signals, a second set of global pre-decoder signals and a first set of local address signals in response to a memory address signal and a first clock signal;
a first local control circuit coupled to the global control circuit, the first local control circuit comprising:
a first clock pre-decoder circuit coupled to the global control circuit, and configured to generate a first set of clock signals and a second set of clock signals in response to the first set of local address signals and the first clock signal; and

a first word line driver circuit comprising:
a first set of repeater circuits configured to generate a first set of local pre-decoder signals in response to the first set of global pre-decoder signals, and to generate a second set of local pre-decoder signals in response to the second set of global pre-decoder signals; and
a first set of word line post-decoder circuits coupled to the first clock pre-decoder circuit and the first set of repeater circuits, and configured to generate a first set of word line signals in response to the first set of clock signals, the first set of local pre-decoder signals and the second set of local pre-decoder signals; and

a first set of memory cells coupled to the first set of word line post-decoder circuits, and configured to store a first set of data in response to at least the first set of word line signals.