Patent ID: 11900993
Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G  H

Claim 13:
14. The semiconductor circuit according to claim 3, further comprising:
a third circuit configured to generate an inverted voltage of a voltage at a third node, the third circuit being configured to apply the inverted voltage to a fourth node;
a fourth circuit configured to generate an inverted voltage of a voltage at the fourth node, the fourth circuit being configured to apply the inverted voltage to the third node;
a third storage element including a seventh terminal, an eighth terminal, and a ninth terminal, the third storage element being configured to set a resistance state between the seventh terminal, the eighth terminal, and the ninth terminal to the first resistance state or the second resistance state in accordance with a direction of a current flowing between the eighth terminal and the ninth terminal;
a fifteenth transistor including a drain coupled to the third node, a source coupled to the seventh terminal of the third storage element, and a gate, the fifteenth transistor being configured to couple the third node to the seventh terminal of the third storage element by being turned on;
a sixteenth transistor including a gate coupled to the third node or the fourth node, a drain coupled to the eighth terminal of the third storage element, and a source, the sixteenth transistor being configured to apply the first voltage to the eighth terminal of the third storage element by being turned on;
a seventeenth transistor including a gate coupled to the third node or the fourth node, a drain coupled to the eighth terminal of the third storage element, and a source, the seventeenth transistor being configured to apply the second voltage to the eighth terminal of the third storage element by being turned on;
a fourth storage element including a tenth terminal, a eleventh terminal, and a twelfth terminal, the fourth storage element being configured to set a resistance state between the tenth terminal, the eleventh terminal, and the twelfth terminal to the first resistance state or the second resistance state in accordance with a direction of a current flowing between the eleventh terminal and the twelfth terminal;
an eighteenth transistor including a drain coupled to the fourth node, a source coupled to the tenth terminal of the fourth storage element, and a gate, the eighteenth transistor being configured to couple the fourth node to the tenth terminal of the fourth storage element by being turned on;
a nineteenth transistor including a gate coupled to a node of the third node and the fourth node that is different from the node to which the gate of the sixteenth transistor is coupled, a drain coupled to the eleventh terminal of the fourth storage element, and a source, the nineteenth transistor being configured to apply the first voltage to the eleventh terminal of the fourth storage element by being turned on; and
a twentieth transistor including a gate coupled to a node of the third node and the fourth node that is different from the node to which the gate of the seventeenth transistor is coupled, a drain coupled to the eleventh terminal of the fourth storage element, and a source, the twentieth transistor being configured to apply the second voltage to the eleventh terminal of the fourth storage element by being turned on.