Patent ID: 11875861
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. A memory, comprising:
a first data line;
an array of memory cells comprising a first string of series-connected memory cells selectively connected to the first data line;
a common source selectively connected to the first string of series-connected memory cells;
a first voltage node;
a first sensing device selectively connected to the first data line; and
a controller for access of the array of memory cells, wherein the controller, during a verify operation on a selected memory cell of the first string of series-connected memory cells, is configured to cause the memory to:
precharge the data line toward a first voltage level;
selectively connect the data line to the common source through the selected memory cell while applying a verify voltage level to a control gate of the selected memory cell, and while the common source is configured to receive the first voltage level;
apply a second voltage level to a control gate of a first p-type field-effect transistor (pFET) connected to the first data line, wherein the second voltage level is configured to place the first pFET in a cut-off state in response to the first data line having a third voltage level lower than the first voltage level;
connect the first data line to the first voltage node through the first pFET, wherein the first voltage node is configured to receive a fourth voltage level lower than the first voltage level and lower than the third voltage level; and
determine whether the selected memory cell has an intended threshold voltage in response to a voltage level developed on the first data line while connected to the first voltage node and selectively connected to the common source.