Patent ID: 11942941
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC H

Claim 9:
10. A device, comprising:
a plurality of tiles including:
a speed tile that includes:
two or more first supply voltage tracks that each provide a first voltage; and
at least one second supply voltage track that provides a second voltage that is less than the first voltage, wherein the speed tile includes more first supply voltage tracks than second supply voltage tracks; and

a power tile that includes:
at least one first supply voltage track that provides the first voltage; and
two or more second supply voltage tracks that provide the second voltage, wherein the power tile includes fewer first supply voltage tracks than second supply voltage tracks,

wherein the speed tile includes at least one third supply voltage track configured to provide a third voltage that is less than the first voltage, wherein the speed tile includes more first supply voltage tracks than third supply voltage tracks.