Patent ID: 11868278
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device, comprising:
a memory array;
a serial interface controller configured to interface with a master device;
a register coupled to the serial interface controller, wherein the register is configured receive a password from the master device via the serial interface controller and store the password received from the master device as a received password, wherein read access to at least a portion of the memory array is enabled if the received password is validated via comparison of the received password with a stored value; and
a second register coupled to the serial interface controller, wherein the second register when in operation stores an indication of whether to enable or prevent write or erase access to the portion of the memory array, wherein alteration of the indication is permitted only subsequent to validation of the received password via the comparison of the received password with the stored value.