Patent ID: 11914253
Assignee: CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 9:
10. A manufacturing method of an array substrate, comprising:
forming a pixel electrode and a thin film transistor;
forming a passivation layer covering the thin film transistor, the passivation layer being provided with a transferring through hole that exposes the pixel electrode and a drain electrode or a source electrode of the thin film transistor simultaneously;
forming a connection electrode on the passivation layer and at the transferring through hole, wherein the connection electrode is simultaneously connected with the pixel electrode, and the drain electrode or the source electrode through the transferring through hole,
wherein the forming a pixel electrode and a thin film transistor on the base comprises:
forming the pixel electrode, a gate line and a gate electrode by means of one patterning process;
forming a gate insulation layer, an active layer, a source electrode, a drain electrode and a data line by means of one patterning process, forming a conductive channel between the source electrode and the drain electrode,
wherein a first compensation block is disposed at a side of the connection electrode close to the gate line, an orthographic projection of the first compensation block on the base includes at least a portion of an orthographic projection of an edge of the drain electrode or the source electrode at a side adjacent to the gate line on the base, the first compensation block extends from a mainbody of the connection electrode towards the gate line, and a size of the first compensation block is smaller than a size of the mainbody in a direction parallel to a direction of the gate line.