Patent ID: 11892948
Assignee: EDGEQ, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 6:
7. A system for data packet processing comprising:
a system-on-a-chip (SoC) comprising multiple clusters with each cluster comprising multiple cores; and
a data plane application architecture comprising:
a plurality of packet processing agents to run data plane applications;
a packet dispatcher thread coupled to the plurality of packet processing agents, the packet dispatcher thread takes packets and distributes data packets among the plurality of packet processing agents for the processing; and
a fast path enabler coupled to the packet dispatcher thread, the fast path enabler is configured for:
learning architecture information about the SoC;
receiving from the packet dispatcher thread resource allocation information of the SOC for a packet processing agent, among the plurality of packet processing agents, to be involved in data packet sharing; and
pre-fetching, one or more packets from a memory into a common cache, identified among multiple common caches in the SoC based on the learned architecture information and the resource allocation information, in a preparation for running the packet processing agent.