Patent ID: 11869574
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 4:
5. The semiconductor memory device of claim 1, wherein the clock correction circuit comprises:
a duty cycle adjuster configured to generate a first corrected clock signal and a second corrected clock signal, which have a phase difference of 180 degrees with respect to each other, by correcting a duty error of the data clock signal including a pair of differential clock signals based on the first control code set;
a clock division circuit configured to divide the first corrected clock signal to generate the first divided clock signal and the third divided clock signal having a phase difference of 180 degrees with respect to each other, and configured to divide the second corrected clock signal to generate the second divided clock signal and the fourth divided clock signal having a phase difference of 180 degrees with respect to each other;
a training scheduler configured to divide the duty training interval into a first interval, a second interval, and a third interval, which are consecutive, and configured to generate training control signals during which a duty training signal based on the duty training command is activated;
a phase skew adjusting circuit configured to generate the first, second, third, and fourth adjusted clock signals by adjusting the first, second, third, and fourth divided clock signals during the duty training interval;
a multi pattern generator configured to generate a first pattern data during the first interval, configured to generate a second pattern data during the second interval, and configured to generate a third pattern data during the third interval, based on a pattern generation control signal in the training control signals;
a clock multiplexer configured to provide the first adjusted clock signal and the third adjusted clock signal as a first selected clock signal and a second selected clock signal from among the first, second, third, and fourth adjusted clock signals based on the first pattern data during the first interval, configured to provide the second adjusted clock signal and the fourth adjusted clock signal as the first selected clock signal and the second selected clock signal from among the first, second, third, and fourth adjusted clock signals based on the second pattern data during the second interval, and configured to provide the first adjusted clock signal and the second adjusted clock signal as the first selected clock signal and the second selected clock signal from among the first, second, third, and fourth adjusted clock signals based on the third pattern data during the third interval;
a duty cycle monitor configured to monitor duty cycles of the first selected clock signal and the second selected clock signal in each of the first interval, the second interval, and the third interval, and configured to generate monitoring information based on a result of monitoring the duty cycles;
a demultiplexer;
a register set configured to store the second control code set and the third control code set which are searched based on the monitoring information during the duty training interval; and
a flip-flop,
wherein the demultiplexer is configured to provide the monitoring information to the register set in the first interval, and is configured to provide the monitoring information to the memory controller through the flip-flop in the second interval, based on a first selection signal in the training control signals.