Patent ID: 11967595
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC B  H

Claim 0:
1. A semiconductor device comprising:
a substrate;
a nanowire spaced apart from the substrate and extending in a first direction;
a gate insulating layer surrounding the nanowire;
a gate electrode extending in a second direction intersecting the first direction and surrounding the nanowire, on the gate insulating layer;
a source/drain on a sidewall of the gate electrode;
a gate spacer between the gate electrode and the source/drain,
wherein the gate spacer includes:
a first inner spacer between the substrate and the nanowire;
a second inner spacer on a top surface of the nanowire; and
an outer spacer being in contact with a top surface of the second inner spacer,

wherein the outer spacer has a first dielectric constant, and
wherein the first inner spacer and the second inner spacer have a second dielectric constant different from the first dielectric constant.