Patent ID: 11875841
Assignee: POWERCHIP SEMICONDUCTOR MANUFACTURING CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 0:
1. A memory device, comprising:
at least one memory chip, each comprising:
a substrate;
a memory array, comprising a plurality of dynamic random access memory cells;
a first inter-layer insulation layer, covering a first surface of the substrate and the transistors of the dynamic random access memory cells;
a plurality of bit lines, coupled to the memory array; and
a plurality of data paths, respectively corresponding to the bit lines, wherein the number of the data paths is equal to or less than the number of the bit lines; and
a sensing amplifier array, comprising a plurality of sensing amplifiers, wherein the bit lines are disposed in the first inter-layer insulation layer, and the bit lines are respectively connected to an input terminal of a corresponding sensing amplifier of the sensing amplifiers via a connection path, wherein the connection path comprises:
a first through hole, a first terminal of the first through hole being coupled to a corresponding bit line of the bit lines;
a first connection wire, a first terminal of the first connection wire being coupled to a second terminal of the first through hole; and
a second through hole, coupled between a second terminal of the first connection wire and the input terminal of the corresponding sensing amplifier; and

a logic chip, comprising:
a plurality of data transmission ports, electrically connected to the data path of the at least one memory chip in a one-to-one manner,

wherein the number of the data transmission ports is equal to a sum of the data paths of the at least one memory chip, and
the logic chip reads or writes a plurality of data from the at least one memory chip through the data transmission ports.