Patent ID: 11967357
Assignee: NATIONAL TSING HUA UNIVERSITY
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 7:
8. A memory unit with time domain edge delay accumulation for computing-in-memory applications, which is controlled by a first word line and a second word line, the memory unit with time domain edge delay accumulation for computing-in-memory applications comprising:
at least one sub-array memory cell module comprising:
at least one first-column memory cell storing a first weight, wherein the at least one first-column memory cell is controlled by the first word line and comprises a first-column local bit line transmitting the first weight; and
at least one second-column memory cell storing a second weight, wherein the at least one second-column memory cell is controlled by the first word line and comprises a second-column local bit line transmitting the second weight;

at least one edge-delay cell multiplexor connected to the at least one sub-array memory cell module and controlled by the second word line, wherein the at least one edge-delay cell multiplexor is configured to generate one of the first weight and the second weight; and
at least one edge-delay cell connected to the at least one edge-delay cell multiplexor and configured to receive a multi-bit analog input voltage, an edge-input signal and the one of the first weight and the second weight, wherein the at least one edge-delay cell is configured to generate an edge-output signal having a delay time according to the multi-bit analog input voltage, the edge-input signal and the one of the first weight and the second weight;
wherein the delay time of the edge-output signal is positively correlated with the multi-bit analog input voltage multiplied by the one of the first weight and the second weight.