Patent ID: 11942418
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 4:
5. A semiconductor structure, comprising:
a combined feature including
a passivation layer,
an interconnecting structure including a conductive pad disposed on the passivation layer, and
a dielectric layer disposed to cover a part of the passivation layer exposed from the conductive pad and a first portion of the conductive pad such that a second portion of the conductive pad is exposed from the dielectric layer;

a protection layer disposed to cover the dielectric layer and a first part of the second portion of the conductive pad such that a second part of the second portion of the conductive pad is exposed from the protection layer;
a polymeric layer disposed on the protection layer and separated from the first part of the second portion of the conductive pad by the protection layer; and
a bump feature formed to extend through the polymeric layer and the protection layer to be connected to the second part of the second portion of the conductive pad,
wherein the protection layer includes a first sub-layer that is in direct contact with the conductive pad, and a second sub-layer that is in direct contact with the polymeric layer, one of the first sub-layer and the second sub-layer being made of an oxide material, the other one of the first sub-layer and the second sub-layer being made of a nitride material.