Patent ID: 11916119
Assignee: GLOBALFOUNDRIES U.S. INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. The method of claim 9, wherein the forming of the structure comprises:
forming a patterned stack of layer above the barrier layer, wherein the patterned stack comprises a gate material layer and at least one protective layer above the gate material layer;
forming a spacer material layer over the patterned stack;
forming a first mask layer on the spacer material layer, wherein the first mask layer has a first opening exposing an area of the spacer material layer above and wider than the patterned stack;
performing etch processes to form gate sidewall spacers from the spacer material layer and to form a source opening and a drain opening on either side of the patterned stack;
removing the first mask layer;
depositing a source/drain metal layer over the patterned stack and filling the source opening and the drain opening;
forming a second mask layer on the source/drain metal layer, wherein the second mask layer has second opening exposing an area of the source/drain metal layer over and on either side of the patterned stack and wherein the second opening is smaller in width than the first opening;
performing an etch process to form the source terminal and a drain terminal; and
removing the second mask layer.