Patent ID: 11886361
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory controller for controlling a memory device in response to a read request from a host, the memory controller comprising:
a buffer memory;
a map data controller;
a map data receiver configured to communicate with the memory device; and
a processor configured to receive the read request, and to control the map data receiver to, receive a plurality of mapping entries included in map data read from the memory device, transfer the plurality of mapping entries to both the buffer memory and the map data controller, and provide a requested logical block address corresponding to the read request to the map data controller,
wherein the map data controller, concurrently with the plurality of mapping entries being transferred to the buffer memory, is configured to detect a mapping entry of the requested logical block address among the plurality of mapping entries, and to output an interrupt signal to the processor in response to detection of the mapping entry of the requested logical block address.