Patent ID: 11935793
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. A method comprising:
etching a recess in a semiconductor fin;
epitaxially growing a source/drain region in the recess;
after epitaxially growing the source/drain region, implanting the source/drain region with arsenic;
after implanting the source/drain region with arsenic, implanting the source/drain region with phosphorous dimer; and
after implanting the source/drain region with phosphorous dimer, activating the arsenic and the phosphorous dimer with an annealing process that causes the arsenic and the phosphorous dimer to spread laterally under a gate spacer, wherein activating the arsenic and the phosphorous dimer further defines:
an arsenic doped region; and
a phosphorous doped region, arsenic of the arsenic doped region extending along sides and below the phosphorous doped region.