Patent ID: 11862637
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A method, comprising:
forming a first active area on a substrate extending in a first direction, the first active area including a first threshold voltage (VT) region defining a first VT and a second VT region defining a second VT different than the first VT, the first and second regions abutting one another to define a boundary therebetween;
forming a plurality of gates contacting the first active area and extending in a second direction perpendicular to the first direction;
forming a first transistor including the first VT region of the first active area and a first one of the gates, the first transistor having the first VT;
forming a second transistor including the second VT region of the first active area and a second one of the gates, the second transistor having the second VT;
forming a tie-off transistor positioned at the boundary of the first VT region and the second VT region such that the first transistor is on a first side of the boundary in the first direction and the second transistor is on a second side of the boundary in the first direction, the tie-off transistor including the first active area and a third one of the gates, where in the third gate is positioned directly over the boundary in the second direction; and
connecting the third gate to a power rail to maintain the tie-off transistor in an off state.