Patent ID: 11923857
Assignee: XILINX, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 0:
1. A digital phase locked loop (DPLL), comprising:
a digital-to-time converter (DTC) configured to receive a reference clock and delay the reference clock based on a received first digital code;
a time-to-digital converter (TDC) configured to output a second digital code indicating a time difference between the delayed reference clock output by the DTC and a clock generated by a digital controlled oscillator (DCO);
circuitry comprising a constrained DTC gain calibration loop and a DTC integral nonlinearity (INL) correction loop configured to generate a nonlinearity correction code;
a combination circuit configured to combine the second digital code with the nonlinearity correction code; and
a digital loop filter configured to receive an output of the combination circuit.