Patent ID: 11861209
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory system comprising:
a memory device including a page storing a first chunk including first user data and first meta data and a second chunk including second user data and second meta data;
a system memory storing an address map table for a physical address of the page in which the first chunk and the second chunk are stored and a logical address mapped to the physical address; and
a controller configured to perform a read operation of the page wherein an error correction operation of the first chunk has failed by:
identifying whether the first meta data of the first chunk includes the logical address mapped to a physical address of the first chunk;
recovering the first meta data using the physical address of the first chunk and the address map table in response to identifying that the logical address was included in the first meta data stored in the first chunk, and
outputting the second user data using the second meta data of the second chunk and using the recovered first meta data, wherein an error correction operation of the second chunk has passed.