Patent ID: 11869581
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. A memory device comprising:
a plurality of static random-access memory (SRAM) cells, the SRAM cells addressed by word lines, bit lines, and bit line bars;
a memory controller configured to send a row number signal for selecting a portion of the word lines and a column number signal for selecting a portion of the bit lines and bit line bars;
a read/write block coupled to each of the bit lines and bit line bars, wherein the read/write block is configured to receive the column number signal and use the column number signal to select a first set of bit lines and bit line bars; and
a recycle multiplexer coupled to each of the bit lines and bit line bars, wherein the recycle multiplexer is configured to receive an inverse of the column number signal and use the inverse of the column number signal to electrically couple to and collect charges from a second set of bit lines and bit line bars not selected by the read/write block.