Patent ID: 11955980
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 5:
6. A method for reducing a coarse lock time of a Phase Locked Loop (PLL), the method comprising:
controlling, by the PLL, a voltage transient in an Automatic Bank Calibration (ABC) current Digital to Analog Converter (DAC) of the PLL using a plurality of switchable voltage clamps, wherein the ABC current DAC comprises a plurality of Metal Oxide Silicon Field Effect Transistors (MOSFETs) and the ABC current DAC is configured to generate at least one ABC code based on a difference between a ring oscillator frequency and a target frequency;
dividing, by the PLL, a loop filter capacitor of the PLL into two segments to reduce a Low Pass Filter (LPF) settling time; and
reducing, by the PLL, the coarse lock time of the PLL using the controlled voltage transients and the divided loop filter capacitor.