Patent ID: 11900994
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 19:
20. The method of claim 18, further comprising:
applying a logic low power to the sleep signal to generate a deactivated sleep signal;
shifting the first word line, coupled to the power header edge cell of the plurality of edge cells, from a logic high power to a logic low power based on the deactivated sleep signal;
turning on the pair of first transistors in the power header edge cell;
shifting the second word line, coupled to the power footer edge cell of the plurality of edge cells, from a logic low power to a logic high power based on the deactivated sleep signal;
turning on the pair of second transistors in the power footer edge cell; and
switching the array of memory cells from the power down mode to the normal power mode based on turning on the first and second transistors.