Patent ID: 11888827
Assignee: HUAWEI TECHNOLOGIES CO., LTD.
Field: Digital communication (Electrical engineering)
Classification: CPC G  H | IPC H

Claim 13:
14. A secure data transfer system comprising:
a first memory comprising a first memory controller; and
a secure data transfer apparatus comprising:
a processor configured to:
run a driver software to generate cryptography information, wherein the cryptography information comprises a key index table comprising a plurality of storage addresses and a first key index corresponding to each of the storage addresses; and
store the key index table in a second memory located outside the secure data transfer apparatus;

a cryptography device configured to:
obtain a current cryptography parameter based on the cryptography information; and
perform a cryptography operation using the current cryptography parameter,

wherein the cryptography operation comprises at least one of the following:
encrypting plaintext data to obtain ciphertext data; or
decrypting the ciphertext data to obtain the plaintext data; and

a first interface configured to perform a ciphertext data exchange with the first memory controller, wherein the ciphertext data exchange comprises at least one of the following:
sending the ciphertext data from the cryptography device to the first memory controller when the first memory needs to be written; or
sending the ciphertext data from the first memory controller to the cryptography device, and

wherein the cryptography device comprises:
a storage configured to store a key lookup table comprising a plurality of second key indexes and a key corresponding to each of the second key indexes; and
a control circuit configured to:
obtain a current storage address corresponding to either writing of the first memory or reading of the first memory;
search the key index table in the second memory to obtain a current key index corresponding to the current storage address; and
search the key lookup table to obtain a current key corresponding to the current key index,

wherein the first memory further comprises:
a second interface coupled to the first interface and configured to:
receive the ciphertext data from the first interface when a write operation is performed on the first memory, or
send the ciphertext data to the first interface when a read operation is performed on the first memory;

a storage medium configured to store the ciphertext data, and
wherein the first memory controller is further configured to perform at least one of the following:
receiving the ciphertext data from the second interface and writing the ciphertext data into the storage medium; or
reading the ciphertext data from the storage medium and sending the ciphertext data to the second interface.