Patent ID: 11901296
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. A method of fabricating a die interconnect substrate, the method comprising:
providing a bridge die having a top side above a bottom side, and a first sidewall and a second sidewall between the top side and the bottom side, the first sidewall laterally opposite the second sidewall, the bridge die having a bridge die pad;
forming a substrate interconnect laterally spaced apart from the first sidewall of the bridge die;
forming an insulating filler structure laterally between the substrate interconnect and the bridge die, the insulating filler structure in contact with the first sidewall of the bridge die;
forming an insulating layer on and in direct contact with the substrate interconnect, on the insulating filler structure, and on the bridge die;
forming a vertical wiring layer in a first opening in the insulating layer, the vertical wiring layer on the substrate interconnect;
forming a first lateral wiring layer on the vertical wiring layer and on the insulating layer;
forming a first contact interface structure on the first lateral wiring layer;
forming a via portion in a second opening in the insulating layer, the via portion on the bridge die pad;
forming a second lateral wiring layer on the via portion and on the insulating layer; and
forming a second contact interface structure on the second lateral wiring layer.