Patent ID: 11880687
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. A system comprising:
an interconnection network having a first plurality of communication lines for transmitting a packet header and a second plurality of communication lines for transmitting a data payload;
a packet network;
a synchronous network;
a processor coupled to the interconnection network, the processor comprising:
a processor core configured to execute a plurality of instructions; and
a core control circuit coupled to the processor core, the core control circuit configured to generate and transmit one or more work descriptor data packets on the interconnection network;

a plurality of configurable circuits arranged in an array, each configurable circuit of the plurality of configurable circuits coupled to the packet network and to the synchronous network, each configurable circuit of the plurality of configurable circuits comprising:
a plurality of synchronous network outputs;
a plurality of synchronous network inputs, each synchronous network input of the plurality of synchronous network inputs coupled to a corresponding synchronous network output, of the plurality of synchronous network outputs, of one or more adjacent configurable circuits of the plurality of configurable circuits of the array, to form a plurality of direct connections between adjacent configurable circuits of the plurality of configurable circuits of the array;
a configurable computation circuit; and
a configuration memory coupled to the configurable computation circuit, the configuration memory comprising:
a first instruction memory configured to store a first plurality of configuration instructions to configure the configurable computation circuit; and
a second instruction memory configured to store a second plurality of configuration instructions or instruction indices, the second plurality of configuration instructions or instruction indices comprising instructions or instruction indices for selection of a configuration instruction of the first plurality of configuration instructions from the first instruction memory and for selection of a synchronous network input from the plurality of synchronous network inputs for receipt of the configuration instruction or a configuration instruction index from another configurable circuit of the plurality of configurable circuits of the array;, and
a dispatch interface circuit coupled to the first, interconnection network and coupled through the packet network to the plurality of configurable circuits of the array, the dispatch interface circuit configured, in response to receiving the one or more work descriptor data packets, to generate and transmit on the packet network one or more data and control packets to one or more configurable circuits of the plurality of configurable circuits of the array to configure the one or more configurable circuits for execution of a corresponding plurality of execution threads.