Patent ID: 11862271
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. A method, comprising:
selecting a column in an array of bitcells for error correction;
writing first data to the column and then reading second data from the column;
comparing the first data to the second data and increasing a column error count based on identifying errors between the first data and the second data;
writing third data to the column and then reading fourth data from the column; and
comparing the third data to the fourth data and increasing the column error count based on identifying errors between the third data and the fourth data, wherein:
the first data refers to a first data sequence,
the second data refers to a second data sequence,
the third data refers to a third data sequence,
the fourth data refers to a fourth data sequence, and
the third data sequence is a complement or an inverse of the first data sequence.