Patent ID: 11940918
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC A  G  Y | IPC G

Claim 0:
1. A circuit device comprising:
a cache memory; and
a first cache controller coupled to the cache memory, wherein the first cache controller includes:
a first scheduler circuit,
a pipeline coupled to the first scheduler circuit and to the cache memory;
a second scheduler circuit coupled to the pipeline and configured to couple to a second cache controller; and
a bypass path coupled between the first scheduler circuit and the second scheduler circuit, wherein the first scheduler circuit is configured to:
receive a first transaction;
determine whether the first transaction is associated with a write of data to the cache memory; and
based on the first transaction not being associated with the write to the cache memory, determine when to provide the first transaction to the second scheduler circuit via the bypass path based on whether a second transaction is in the pipeline.