Patent ID: 11961585
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G  H

Claim 0:
1. A memory device, comprising:
a. centralized command and address (CA) interface region including two or more CA input circuits operably coupled to two or more CA input signals; and
a clock buffer circuit adjacent to at least one of the two or more CA input circuits and configured to supply one or more clock signals to each of the two or more CA input circuits;
wherein at least two of the two or more CA input circuits are configured in CA pairs and each CA pair comprises:
a first CA input circuit and a second CA input circuit adjacently arranged in a mirror relationship;
a first swap circuit configured to:
select, for a first operation, a first CA output for a first internal CA signal; and
select, for a second, different operation, the first CA output for a second internal CA signal; and
a second swap circuit configured to:
select, for the first operation, a second CA output for the second internal CA signal; and
select, for the second, different operation, the second CA output for the first internal CA signal.