Patent ID: 11868267
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus comprising:
a first media on a solid state drive (SSD) having a particular access size corresponding to a logical access unit associated therewith, the logical access unit having a same size as a cache line of a processing device coupled to the first media associated with performance of memory operations;
a second media on the SSD to store a logical to physical data structure whose management entries map management segments of respective physical locations to the first media, wherein each management segment corresponds to a plurality of logical access units having the particular access size, and each management entry comprises at least one of a management segment address, a time stamp, or an access count, or combinations thereof; and
the processing device resident on the SSD and coupled to the first media and the second media, wherein the processing device is configured to:
for each respective management segment, track access requests to constituent access units corresponding to the respective management segment; and
determine whether to perform a memory management operation on the respective management segment based on the tracking.