Patent ID: 11888028
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A semiconductor device, comprising:
an active pattern on a substrate;
a device isolation layer filling a trench that defines the active pattern;
a plurality of semiconductor patterns that are stacked on the active pattern and vertically spaced apart from each other;
a gate electrode on the plurality of semiconductor patterns;
a liner layer on the plurality of semiconductor patterns and the device isolation layer, the liner layer surrounding each of the plurality of semiconductor patterns, the liner layer covering a top surface of the device isolation layer; and
a gate insulating layer on the liner layer,
wherein the liner layer comprises a same semiconductor material as the semiconductor patterns, and
wherein the liner layer is interposed between the device isolation layer and the gate insulating layer.