Patent ID: 11874782
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A computing system comprising:

a CPU;
random access primary memory accessible to the CPU;
a secondary storage device comprising one or more mass storage devices;
an I/O Interface providing a transfer mechanism between the random access primary memory and the secondary storage device;
a controller configured to accept transfer requests from the I/O interface and control the secondary storage device; and
an operating system configured to manage transfers of data contained within buffers located in random access primary memory to/from the secondary storage device;

wherein:

a program issues requests to the operating system for I/O transfers to/from the program buffers and the secondary storage device,
the one or more mass storage devices comprise a random access mass storage device, and
requests sent to the controller include buffer identifiers when the transfer request is queued, and when transfer is imminent the controller requests the address of the associated buffer from the operating system executing on the central processing unit.