Patent ID: 11929759
Assignee: AMS INTERNATIONAL AG
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 18:
19. A digital-to-analog converter, DAC, for use in an incremental analog-to-digital converter, iADC, the DAC being configured for converting a multi-bit word to an analog feedback signal, the multi-bit word representing an integer within a range of integers, the DAC comprising
a mismatch shaping logic block configured to generate a selection vector with a predefined number of bits based on the multi-bit word,
a plurality of output elements configured to generate respective analog portions based on the selection vector, and
a signal combiner for combining the analog portions to the analog feedback signal,, wherein in the mismatch shaping logic block
a predetermined number of switching blocks are arranged cascaded forming layers of switching blocks,
each switching block is configured to receive at least a portion of the multi-bit word, to split the portion into two sub-portions and to forward each sub-portion, wherein switching blocks of preceding layers are configured to forward the sub-portions to one further switching block of a subsequent layer and switching blocks of a last layer are configured to forward the sub-portions to one of the output elements,
in each switching block a weight factor is adjusted by multiplying the weight factor with the difference of the two sub-portions, wherein in each clock period within the conversion cycle of the iADC a new weight factor is provided by a weight generator, wherein successive weight factors decrease according to a monotonically decreasing function, and
each switching block comprises a weight accumulator provided for accumulating successive adjusted weight factors, wherein the way of splitting the portion of a further multi-bit word coming to the respective switching block at a subsequent clock period within the conversion cycle of the iADC is determined based on the sign of the weight accumulator.