Patent ID: 11934251
Assignee: ADVANCED MICRO DEVICES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 14:
15. A data processing system, comprising:
a data fabric operating on a data fabric clock domain;
a memory channel including a physical layer interface (PHY) operating on a memory clock domain for coupling to a DRAM memory;
a memory channel controller including a first interface circuit adapted to couple to the data fabric, and a second interface circuit adapted to couple to the PHY, wherein the memory channel controller operates in a memory channel clock domain according to a set of timing parameters, wherein the first interface circuit includes a clock interface circuit for adapting transfers between the data fabric clock domain and the memory channel clock domain; and
a power controller coupled to the memory channel controller and responsive to a power state change request to send commands to the second interface circuit to change parameters of a memory system, the memory system comprising the memory channel and the DRAM memory, and to update the set of timing parameters of the memory channel controller according to a selected power state of a plurality of power states,
wherein the power controller is further responsive to a request to synchronize the clock interface circuit with a new frequency of only a first clock signal of the data fabric clock domain to change the set of timing parameters of the clock interface circuit without changing the set of timing parameters of the memory system or the selected power state.