Patent ID: 11894477
Assignee: RAYTHEON COMPANY
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 1:
2. An electrical device comprising:
a substrate;
a temperature-sensitive material supported by the substrate, the temperature-sensitive material having a thermal degradation temperature in a range from 50° C. to 250° C.; and
(i) a stress buffer layer supported by the substrate and formable at a temperature less than the thermal degradation temperature of the temperature-sensitive material such that the stress buffer layer is configured to minimize strain at an interface of the temperature-sensitive material; and/or (ii) a stress compensation layer supported by the substrate and formable at a temperature less than the thermal degradation temperature of the temperature-sensitive material such that the stress compensation layer is configured to counteract forces imparted to the substrate to thereby control an amount of substrate bow;
wherein the temperature-sensitive material is between the substrate and the stress buffer layer and/or the stress compensation layer;
wherein the electrical device further comprises a compressive layer overlying at least a part of the substrate;
wherein the stress compensation layer and the compressive layer impart opposing forces to one another, and the stress compensation layer has an intrinsic tensile stress that counteracts an intrinsic compressive stress of the compressive layer to thereby control the amount that the substrate bows;
wherein the compressive layer has an intrinsic compressive stress in the range from −50 MPa to −1 GPa; and
wherein the stress compensation layer is between the temperature-sensitive material and the compressive layer.