Patent ID: 11967361
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. A system, comprising:
a host device configured to generate instructions; and
a memory device configured to execute instructions from the host device to compare a first value to a second value wherein the first value is a first numerical value and the second value is a second numerical value, and wherein:
first memory cells coupled to a sense line of an array of memory cells store first respective bits representing the first numerical value; and
second memory cells coupled to the sense line store second respective bits representing the second numerical value; and

wherein the memory device is configured to compare the first value to the second value by performing a plurality of logical operations without concurrently activating multiple word lines of the array, and provide a comparison result indicating whether the first numerical value is greater than the second numerical value.