Patent ID: 11955153
Assignee: KEPLER COMPUTING INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 18:
19. An apparatus comprising:
a first transistor having a first gate terminal coupled to a word-line, a first source terminal couple to a bit-line, and a first drain terminal coupled to a storage node;
a second transistor coupled to the first transistor, wherein the second transistor includes a second gate terminal coupled to the storage node, a second source terminal couple to a sense line, and a second drain terminal coupled to a bias; and
a plurality of memory elements having a first terminal coupled to the storage node via a metal layer, wherein a second terminal of an individual memory element of the plurality of memory elements is coupled to an individual plate-line, and wherein the plurality of memory elements are planar memory elements that are arranged in a staggered configuration on the metal layer such that a first memory element of the plurality of memory elements is offset along a horizontal plane diagonally from a second memory element of the plurality of memory elements.