Patent ID: 11862287
Assignee: MACRONIX INTERNATIONAL CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. The integrated circuit of claim 17, further comprising:
a third circuit configured to:
during a first phase, separately precharge the sensing node and a bit line that is coupled to a memory cell in a memory device and configured to be disconnected from the sensing node, and
during a second phase after the first phase, discharge a sensing voltage at the sensing node according to an equivalent capacitor by conductively connecting the sensing node to the bit line to generate a sensing current to the memory cell through the bit line, wherein the equivalent capacitor is based on the gate capacitor associated with the sensing transistor and one or more junction capacitors associated with one or more first transistors in the one or more first latch units and one or more second transistors in the one or more second latch units, and wherein a total capacitance of the one or more junction capacitors is substantially larger than a capacitance of the gate capacitor,

wherein the first latch circuit is configured to:
after the second phase, update data latched in the first latch circuit based on a discharged sensing voltage at the sensing node, and

wherein the second latch circuit is configured to:
turn on at least one of the one or more second transistors to update the data latched in the first latch circuit into at least one latch in the second latch circuit.