Patent ID: 11929674
Assignee: STMICROELECTRONICS S.R.L.
Field: Electrical machinery, apparatus, energy (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. An integrated circuit comprising:
an input node configured to receive an input voltage;
an output node configured to be coupled to an output capacitor and configured to produce an output voltage higher than the input voltage;
a first input control node configured to receive a first clock signal;
a second input control node configured to receive a second clock signal, the second clock signal being in phase opposition to the first clock signal, wherein the integrated circuit switches between a first commutation state and a second commutation state as a function of the first and second clock signals;
an ordered sequence of intermediate voltage nodes arranged between the input node and the output node, the ordered sequence comprising a first ordered sub-sequence of intermediate voltage nodes and a second ordered sub-sequence of intermediate voltage nodes;
a respective capacitor coupled between each odd-numbered intermediate voltage node in the first ordered sub-sequence of the ordered sequence and the first input control node, wherein a first intermediate voltage node in the first ordered sub-sequence is configured to be selectively couplable to the input node;
a respective capacitor coupled between each even-numbered intermediate voltage node in the first ordered sub-sequence of the ordered sequence and the second input control node;
a respective capacitor coupled between each odd-numbered intermediate voltage node in the second ordered sub-sequence of the ordered sequence and a corresponding odd-numbered intermediate voltage node in the first ordered sub-sequence of the ordered sequence;
a respective capacitor coupled between each even-numbered intermediate voltage node in the second ordered sub-sequence of the ordered sequence and a corresponding even-numbered intermediate voltage node in the first ordered sub-sequence of the ordered sequence; and
a first plurality of selectively conductive electronic components coupled to the intermediate voltage nodes of the ordered sequence, wherein:
in the first commutation state, the first plurality of selectively conductive electronic components is configured to provide electrically-conductive paths between each of the even-numbered intermediate voltage nodes of the ordered sequence and a respective next odd-numbered intermediate voltage node of the ordered sequence, an electrically-conductive path between the input node and the first intermediate voltage node of the ordered sequence, and an electrically-conductive path between a last intermediate voltage node of the ordered sequence and the output node, and
in the second commutation state, the first plurality of selectively conductive electronic components is configured to provide electrically-conductive paths between each of the odd-numbered intermediate voltage nodes of the ordered sequence and a respective next even-numbered intermediate voltage node of the ordered sequence.