Patent ID: 11863071
Assignee: ANPEC ELECTRONICS CORPORATION
Field: Electrical machinery, apparatus, energy (Electrical engineering)
Classification: CPC H  Y | IPC H

Claim 0:
1. A power converter having a smooth transition control mechanism, comprising:
an oscillator circuit configured to output a clock signal;
a control circuit connected to the oscillator circuit, and configured to receive the clock signal from the oscillator circuit and to output a control signal based on the clock signal;
a driver circuit connected to the control circuit and the oscillator circuit, and configured to output a high-side conduction signal and a low-side conduction signal;
a high-side switch, wherein a first terminal of the high-side switch is coupled to a common voltage, a control terminal of the high-side switch is connected to the driver circuit, and the high-side switch is turned on or off according to the high-side conduction signal from the driver circuit; and
a low-side switch, wherein a first terminal of the low-side switch is connected to a second terminal of the high-side switch, a second terminal of the low-side switch is grounded, a node between the first terminal of the low-side switch and the second terminal of the high-side switch is connected to a first terminal of an inductor, a second terminal of the inductor is connected to a first terminal of an output capacitor, a second terminal of the output capacitor is grounded, a control terminal of the low-side switch is connected to the driver circuit, and the low-side switch is turned on or off according to the low-side conduction signal from the driver circuit;
wherein, the oscillator circuit, according to the high-side conduction signal from the driver circuit, determines whether or not the clock signal outputted to the control circuit needs to be adjusted;
wherein, when the time point at which the high-side conduction signal transits from a high level to a low level is later than a transition time point of the clock signal, the oscillator circuit delays a pulse wave of the clock signal such that a time point at which the pulse wave of the clock signal appears is later than the time point at which the high-side conduction signal transits from the high level to the low level.