Patent ID: 11961761
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for forming a semiconductor structure associated with mitigating pattern collapse, comprising:
etching a first trench within a first dielectric layer;
forming a first metal line within the first trench;
forming a second dielectric layer above the first metal line and the first dielectric layer;
etching a second trench within the second dielectric layer, wherein a portion of the first metal line and a portion of the first dielectric layer are exposed through the second trench;
forming a first metal line barrier within the second trench;
removing a portion of the first metal line barrier over the first metal line to expose at least some of the portion of the first metal line; and
forming a second metal line within the second trench after the removing a portion of the first metal line barrier.