Patent ID: 11959965
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Measurement (Instruments)
Classification: CPC G | IPC G

Claim 1:
2. The test circuit of claim 1, further comprising:
a clock gating circuit configured to receive a scan enable signal through a scan enable terminal, a clock signal through a clock signal terminal and a test signal, and output a first output signal to control whether the clock signal is gated in response to a combination of the scan enable signal and the test signal,
wherein the scan flip-flop includes:
a third multiplexer including a third selection terminal connected to the scan enable terminal, a fifth input terminal connected to the CFI terminal, a sixth input terminal connected to a cell test input (CTI) terminal configured to receive a CTI signal, and a third output terminal; and
a D-flip-flop configured to capture an output signal output from the third output terminal of the third multiplexer in response to the first output signal received through a clock terminal, and to transmit the captured output signal to the third input terminal of the second multiplexer.