Patent ID: 11882703
Assignee: SK HYNIX INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 4:
5. A semiconductor memory device, comprising:
a stacked body comprising a plurality of interlayer insulating layers and a plurality of gate electrodes that are alternately stacked on a substrate; and
a plurality of channel structures configured to vertically pass through the stacked body,
wherein each of the plurality of channel structures comprises a core insulating layer, a first channel layer, a second channel layer, a third channel layer, a tunnel insulating layer, and a charge storage layer that extend vertically towards the substrate,
wherein the first channel layer encloses the core insulating layer, the second channel layer encloses the first channel layer, and the third channel layer encloses the second channel layer,
wherein the first channel layer and the third channel layer are formed of a same material, and
wherein electron mobility of the second channel layer is higher than electron mobility of each of the first channel layer and the third channel layer.