Patent ID: 11972123
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. An apparatus, comprising:
one or more first storage elements configured to store a first set of bits of a row address based at least in part on a first activate command to obtain a first delayed signal of the first set of bits;
one or more second storage elements configured to store a second set of bits of the row address based at least in part on a second activate command to obtain a first delayed signal of the second set of bits;
one or more third storage elements configured to store the first delayed signal of the first set of bits based at least in part on the second activate command to obtain a second delayed signal of the first set of bits; and
a circuit configured to activate a page of memory based at least in part on the second activate command, wherein the page of memory is addressed according to the second delayed signal of the first set of bits and the first delayed signal of the second set of bits.