Patent ID: 11929121
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus, comprising:
a memory array including a plurality of memory cells, wherein each of the plurality of memory cells is programmable to a first data state, a second data state, or a third data state; and
circuitry coupled to the memory array, wherein the circuity is configured to:
select a first memory cell and a second memory cell from the plurality of memory cells, wherein the first memory cell and the second memory cell are coupled to a same access line of the memory array; and
store one data value by programming the first memory cell to the first data state, the second data state, or the third data state and by programming the second memory cell to the first data state, the second data state, or the third data state, wherein:
the one data value corresponds to a combination of the first data state, the second data state, or the third data state to which the first memory cell is programmed and the first data state, the second data state, or the third data state to which the second memory cell is programmed; and
two combinations of the first data state, the second data state, or the third data state to which the first memory cell is programmable and the first data state, the second data state, or the third data state to which the second memory cell is programmable are ineligible to correspond to the one data value.