Patent ID: 11916574
Assignee: MARVELL ASIA PTE LTD
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 20:
21. The receiver circuit of claim 16, wherein:
the error estimator is configured to implement a trellis and sum metrics along paths of the trellis to generate metric sums respectively for the most likely error events; and
the decoder is configured to
for each of the most likely error events, (i) flip corresponding pulse amplitude modulation symbols of the set of decisions to provide a codeword, (ii) compute a syndrome of the flipped pulse amplitude modulation symbols, and (iii) determine if the syndrome is equal to zero indicating the codeword is valid,
if one or more valid codewords are determined,
determine a smallest one of the metric sums for a corresponding one or more of the most likely error events having a valid codeword, and
output the valid codeword of the one or more of the most likely error events having the smallest one of the metric sums, and

if no valid codewords are determined, output hard decisions from a demapper.