Patent ID: 11901219
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 17:
18. A method, comprising:
forming an insulating structure over a substrate;
performing a first annealing process;
recessing the insulating structure;
performing a first ultraviolet (UV) curing process;
forming source/drain epitaxial features over the substrate;
forming a gate electrode layer over the substrate;
forming a dielectric layer over the source/drain epitaxial features and the gate electrode layer;
performing a second annealing process;
forming one or more openings in the dielectric layer;
performing a second UV curing process;
forming conductive features in the one or more openings,
forming a cap layer on each of the conductive features by a plasma enhanced chemical vapor deposition process, wherein the cap layer comprises a metal; and
performing a third UV curing process after forming the cap layer.