Patent ID: 11960392
Assignee: AMAZON TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 4:
5. An integrated circuit, comprising:
a source node;
a first interconnect fabric;
a first address decoder communicatively coupled between the source node and the first interconnect fabric, the first address decoder configured with a first address mapping table that maps a first set of address ranges to a first set of target nodes coupled to the first interconnect fabric;
a second interconnect fabric; and
a second address decoder communicatively coupled between the first interconnect fabric and the second interconnect fabric, the second address decoder configured with a second address mapping table that maps a second set of address ranges to a second set of target nodes coupled to the second interconnect fabric, wherein the second address decoder corresponds to a first target node in the first set of target nodes.