Patent ID: 11868699
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 9:
10. An integrated circuit comprising:
a first active region extending in a first direction, being in a substrate, and being located on a first level, the first active region including a first drain/source region, and a second drain/source region;
a second active region in the substrate, being located on the first level, and being separated from the first active region in a second direction different from the first direction, the second active region including a third drain/source region;
a first insulating region over the first drain/source region;
a second insulating region over the second drain/source region, and being separated from the first insulating region in the first direction;
a first contact extending in the second direction, overlapping the third drain/source region, and being located on a second level different from the first level; and
a second contact extending in the first direction and the second direction, overlapping the first contact, the first insulating region and the second insulating region, the second contact being electrically insulated from the first drain/source region by the first insulating region, and electrically insulated from the second drain/source region by the second insulating region, and being located on a third level different from the first level and the second level.