Patent ID: 11934270
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. An apparatus, comprising: a number of memory devices respectively coupled to a number of channels configured to store sets of data blocks each including respective user data blocks and one or more parity blocks that are grouped together for an error correction operation; and a controller coupled to the number of memory devices and configured to: receive a plurality of write commands to write respective user data blocks to the number of memory devices; retrieve, in response to receipt of the plurality of write commands, parity data blocks respectively corresponding to the user data blocks; update the retrieved parity data blocks based respectively on the user data blocks; and write, among the user data blocks and the updated parity data blocks, at least two user data blocks and one or more parity data blocks targeting different memory devices of the number of memory devices and to the different memory devices.