Patent ID: 11870614
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 14:
15. A flip-flop for implementing decision-feedback equalization (DEE), the flip-flop comprising:
a master latch comprising:
a first amplifier comprising an in-built adder circuit, the first amplifier configured to charge one or more output nodes of the first amplifier to a first voltage using a summed signal based on input data and a feedback signal in response to a first-clock variation, wherein the feedback signal is a partially-regenerated analog output from a regenerating amplifier; and
a second amplifier that is configured to generate the partially-regenerated analog output; and

a slave latch configured to resolve the partially-regenerated analog output into non-return to zero (NRZ) digital values at an output of the third stage.