Patent ID: 11955157
Assignee: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. The PUF apparatus according to claim 4,
wherein the voltage line allows the FeFET pair of each of the plurality of PUF cells to have different threshold voltage states according to variations in the manufacturing process, such that among an initialization phase, an enrollment precharge phase and a provisioning and write-back phase of an enrollment phase of setting a response corresponding to a challenge indicating an address of each PUF cell, in the initialization phase it has a second voltage, and in the enrollment precharge phase and the provisioning and write-back phase it has a third voltage,
wherein the ground line has a first voltage in the initialization phase, and has the third voltage in the enrollment precharge phase and the provisioning and write-back phase,
wherein the selected word line among the plurality of word lines has the first voltage in the initialization phase and the enrollment precharge phase, and has the second voltage in the provisioning and write-back phase, and
wherein unselected word lines among the plurality of word lines have the first voltage in the initialization phase and the enrollment precharge phase, and have the third voltage in the provisioning and write-back phase.