Patent ID: 11942406
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for manufacturing a semiconductor package, comprising:
providing an interconnect bridge embedded within a build-up material formed on a surface of a sacrificial core, the interconnect bridge comprising an interconnect first side with a conductive pad and an interconnect second side opposite the interconnect first side, such that a distance between the interconnect first side and the surface is less than a distance between the interconnect second side and the surface;
forming a first via in the build-up material, wherein the first via has a first end that is narrower than a second end of the first via, and the first end is closer to the surface than the second end is to the surface;
providing, prior to removal of the sacrificial core, a temporary carrier on a side of the semiconductor package opposite to the sacrificial core;
removing the sacrificial core to expose the interconnect first side;
providing additional build-up material at the interconnect first side; and
forming a second via in the build-up material disposed at the interconnect first side, wherein the second via has a first end that is narrower than a second end, wherein the first end of the first via and the first end of the second via face opposite directions.