Patent ID: 11903146
Assignee: KYOCERA CORPORATION
Field: Telecommunications (Electrical engineering)
Classification: CPC H | IPC H

Claim 3:
4. A method for manufacturing a printed wiring board, comprising: preparing, as a core substrate, a member which corresponds to a layer range where an interlayer connection conductor constituting an inner via is continuous and which includes a via inner space which is hollow and which is inside the interlayer connection conductor constituting the inner via; preparing, as one or more build-up layers, one or more members which include one or more holes formed in advance; layering the core substrate and the one or more build-up layers such that the one or more holes of the one or more build-up layers are continuous with the via inner space, wherein the one or more build-up layers are a plurality of build-up layers, the one or more holes are a plurality of holes, the plurality of holes are hollow such that the via inner space is connected and open to the outside through the plurality of holes, and the plurality of build-up layers are layered on the core substrate such that the plurality of holes are layered over the via inner space so as to be continuous.