Patent ID: 11935922
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 10:
11. A semiconductor device comprising:
a substrate;
a 1st transistor formed above the substrate, the 1st transistor comprising at least two 1st channel layers and 1st and 2nd source/drain regions; and
a 2nd transistor stacked above the 1st transistor in a vertical direction, the 2nd transistor comprising at least two 2nd channel layers and 3rd and 4th source/drain regions;
wherein the 2nd source/drain region is partially overlapped by the 4th source/drain region in a vertical direction,
wherein at least one of the two 1st channel layers is not vertically overlapped by any one of the 2nd channel layers, and
wherein a sum of effective channel widths of the 1st channel layers is substantially equal to a sum of effective channel width of the 2nd channel layers.