Patent ID: 11901033
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An operating method of a memory device, the operating method comprising:
receiving an address for memory access from a memory controller;
determining whether a column address in the address is a defect address;
when the column address is not the defect address, accessing first normal memory cells corresponding to the column address; and
when the column address is the defect address, accessing first redundant memory cells corresponding to a repair address,
wherein the memory device includes:
first page buffers arranged collinearly in a first direction and connected to normal memory cells through first bit lines extending in the first direction, the first page buffers divided into a first plurality of repair groups including a first repair group and a second repair group, the first normal memory cells corresponding to the first repair group or the second repair group, and
second page buffers arranged collinearly in the first direction and connected to redundant memory cells through second bit lines extending in the first direction, the second page buffers divided into a second plurality of repair groups including a third repair group and a fourth repair group, the first redundant memory cells corresponding to the third repair group or the fourth repair group,
wherein a width of a region including the first bit lines is the same as a width of a gate in a transistor in a second direction, the transistor included in each of the first page buffers, and
transistors included in each of the first page buffers are collinear in the first direction.