Patent ID: 11934525
Assignee: CISCO TECHNOLOGY, INC.
Field: Digital communication (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 9:
10. A system comprising:
one or more processors; and
memory including instructions that, when executed by the one or more processors, cause the one or more processors to:
obtain, from one or more computing devices, one or more messages comprising a nonce;
generate a signature comprising the nonce and integrity data from the processor, wherein at least one of the integrity data or the one or more messages comprises at least one of a proof of freshness;
validate the proof of freshness based on a state of internal counters within one or more trusted platform module crypto-processors associated with the one or more computing devices and a reference database;
identify a level of trust of each of the one or more computing devices based on the signature; and
determine whether to perform a next step in a cryptographic security protocol based on the level of trust, wherein the cryptographic security protocol comprises at least one of a Secure Shell (SSH) protocol, a Transport Layer Security (TLS) protocol, a Secure Sockets Layer (SSL) protocol, and an Internet Protocol Security (IPsec) protocol.