Patent ID: 11868210
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. A system, comprising:
a host; and
a memory device coupled to the host, the memory device comprising:
an array of memory cells; and
control circuitry coupled to the array, wherein the control circuitry is configured to:
perform a parity operation on a first set of data of a plurality of memory cells coupled to access lines of an array resulting in a first set of parity data corresponding to each of the access lines resulting in access line parity data;
perform an additional parity operation on a second set of data of a plurality of memory cells coupled to sense lines of the array resulting in a second set of parity data corresponding to each of the sense lines resulting in sense line parity data; and
send the access line parity data and the sense line parity data to the host;

wherein the host is configured to:
receive the access line parity data and the sense line parity data;
generate crossed matrix parity values using the first plurality and the second plurality of sets of parity data;
use the crossed matrix parity values to generate instructions to perform an error correction operation on at least a portion of the plurality of memory cells based on the access line parity data and the sense line parity data; and
send the instructions to the memory device.