Patent ID: 11961546
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A memory device, comprising:
a memory array including a plurality of memory cells;
a sense amplifier connected to the memory array;
a reference bit line configured to provide a reference current to the sense amplifier;
a plurality of resistive elements including at least one magnetic tunnel junction (MTJ) coupled to the reference bit line;
a first pair of transistors connected in parallel;
a second pair of transistors connected in parallel; and
the first and second pairs of transistors connected in series between the at least one MTJ and a reference source line wherein the first and second pairs of transistors are configured to selectively flow current through the at least one MTJ in the forward and inverse direction to generate the reference current wherein the first pair of transistors includes first and second transistors connected in parallel, and the second pair of transistors includes third and fourth transistors connected in parallel, and wherein the first, second and third transistors each have a gate terminal connected to a first reference word line, and the fourth transistor has a gate terminal connected to as second reference word line.