Patent ID: 11967552
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. An interconnect structure, comprising:
a first dielectric layer;
a bottom via disposed in the first dielectric layer;
a conductive line disposed over the bottom via, wherein the conductive line includes a first barrier layer and a ruthenium-containing bulk layer, wherein the ruthenium-containing bulk layer is in direct contact with the first dielectric layer, wherein a thickness of the conductive line is less than a thickness of the bottom via;
a second dielectric layer disposed over the conductive line and the first dielectric layer; and
a top via disposed in the second dielectric layer and over the conductive line,
wherein the top via includes a second barrier layer over the first barrier layer and a via bulk layer over the second barrier layer,
wherein the second barrier layer includes a side portion having a first thickness and a bottom portion having a second thickness,
wherein a portion of the first barrier layer directly under the second barrier layer has a third thickness,
wherein the first thickness is smaller than a sum of the second thickness and the third thickness.