Patent ID: 11939625
Assignee: CHANGSHA UNIVERSITY OF SCIENCE AND TECHNOLOGY
Field: Measurement (Instruments)
Classification: CPC C  G | IPC C  G

Claim 1:
2. The method according to claim 1, wherein in step (1), when plating the Al—Cu alloy layer, the Cr—Pd alloy layer and the Au membrane layer sequentially on the substrate layer of the polysilicon gate electrode by the thermal evaporation and magnetron sputtering techniques, a passivation is carried out with Si3N4, the Al—Cu alloy layer comprises the following components in parts by weight: 40-68 parts of Al, 30-60 parts of Cu, 2-12 parts of Ni, 1-8 parts of Fe, 1-6 parts of Ti and 0.01-0.50 part of Nb, the Cr—Pd alloy layer comprises the following components in parts by weight: 40-80 parts of Cr, 10-40 parts of Pd, 2-12 parts of Ni, 1-8 parts of Fe, 1-6 parts of Ti, 0.01-0.50 part of Nb, the Al—Cu alloy layer has a thickness of 20-600 nm, the Cr—Pd alloy layer has a thickness of 20-600 nm, and the Au membrane layer has a thickness of 20-1,000 nm.