Patent ID: 11914893
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. The memory device of claim 17, wherein the first subset of the memory access commands is associated with read commands associated with the first priority, and the second subset of the memory access commands is associated with read commands associated with the second priority, and
wherein the processor is further operable to cause the memory device to:
determine a third subset of the memory access commands associated with write commands associated with the first priority and a fourth subset of the memory access commands associated with write commands associated with the second priority;
route, from the command queue to a fifth queue, the third subset of the memory access commands associated with the first priority;
route, from the command queue to a sixth queue, the fourth subset of the memory access commands associated with the second priority;
process, by the processor, the third subset of the memory access commands from the fifth queue to the third queue at the storage controller according to a third process; and
process, by the processor, the fourth subset of the memory access commands from the sixth queue to the fourth queue at the storage controller according to a fourth process, wherein the third and fourth processes are run concurrently by the execution unit with the first and second processes according to the quantity of the memory access commands in the command queue for the prioritization between the first priority and the second priority.