Patent ID: 11881450
Assignee: ADVANCED MICRO DEVICES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A method for fabricating an integrated circuit comprising:
forming a first metal layer;
forming a first dielectric layer adjacent to the first metal layer;
forming a second metal layer adjacent to the first dielectric layer;
forming a second dielectric layer adjacent to the second metal layer; and
forming a third metal layer adjacent to the second dielectric layer, wherein a metal-insulator-metal (MIM) capacitor of an integrated circuit is formed between the first metal layer and the third metal layer; and
receiving a respective voltage reference level by each of the first metal layer and the third metal layer with one of the respective voltage reference levels being a first power supply voltage reference level that is different from a second power supply voltage level used in another region of the integrated circuit; and
wherein the second metal layer is a floating net with no connection to a voltage reference level used by the integrated circuit.