Patent ID: 11967361
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus, comprising:
a first address space of a memory array comprising a first plurality of memory cells configured to store respective bits collectively representing a first value, wherein the first plurality of memory cells are coupled to a sense line and to a first plurality of word lines, and wherein the first value is a first numerical value;
a second address space of the memory array comprising a second plurality of memory cells configured to store respective bits collectively representing a second value, wherein the second plurality of memory cells are coupled to the sense line and to a second plurality of word lines, and wherein the second value is a second numerical value;
a third address space of the memory array comprising a third number of memory cells configured to store a result of a comparison operation, wherein the third number of memory cells are coupled to the sense line and to a third number of word lines; and
sensing circuitry configured to perform a plurality of logical operations to perform the comparison operation on the first numerical value and the second numerical value;
wherein the result of the comparison operation indicates whether the first numerical value is greater than the second numerical value; and
wherein at least one of the plurality of logical operations is performed without activating multiple word lines concurrently.