Patent ID: 11929440
Assignee: NEXGEN POWER SYSTEMS, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 5:
6. The method of claim 2 further comprising:
forming a metal layer on an upper portion of the plurality of fins, on an upper portion of the gate layer, and on an upper portion of the body diode region;
forming an interlayer dielectric layer on the metal layer, the gate layer, and the isolation region;
forming a third patterned hard mask layer on the interlayer dielectric layer on the metal layer;
etching the interlayer dielectric layer using the third patterned hard mask layer as a mask to forming a plurality of through-holes exposing a surface portion of the metal layer on the upper portion of the plurality of fins and on the upper portion of the body diode region; and
filling the through-holes with a conductive material to form a plurality of vias.