Patent ID: 11901330
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A method of fabricating a microelectronic assembly, the method comprising:
coupling a first die to a package substrate, the package substrate having an uppermost surface, the first die entirely above the uppermost surface of the package substrate, and the first die having a first sidewall and a second sidewall, the second sidewall laterally opposite the first sidewall, the first die comprising through silicon vias, the through silicon vias coupled to the package substrate;
forming first interconnects entirely above the uppermost surface of the package substrate, the first interconnects laterally spaced apart from the first sidewall of the first die, the first interconnects coupled to the package substrate, and the first interconnects extending an entire vertical length of the first die;
forming second interconnects entirely above the uppermost surface of the package substrate, the second interconnects laterally spaced apart from the second sidewall of the first die, the second interconnects coupled to the package substrate, and the second interconnects extending the entire vertical length of the first die;
providing a second die vertically over the first interconnects and a first portion of the first die, the second die coupled to the first interconnects and to the first portion of the first die; and
providing a third die vertically over the second interconnects and a second portion of the first die, the third die coupled to the second interconnects and to the second portion of the first die, the third die laterally spaced apart from the second die.