Patent ID: 11960731
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus, comprising:
a first in first out (FIFO) memory;
first circuitry coupled to the FIFO memory and configured to provide a write pointer of the FIFO memory;
second circuitry coupled to the FIFO memory and configured to provide a read pointer of the FIFO memory; and
third circuitry coupled to the first and second circuitries and configured to:
provide a first signaling indicative of whether a first value of the write pointer for a current cycle of a read clock is a first particular value;
perform a first logical operation on the first signaling and second signaling indicative of the read pointer,
wherein a result of the first logical operation is indicative of a potential error condition being overflow of the FIFO memory;
provide a third signaling indicative of whether a second value of the write pointer for a subsequent cycle of the read clock is a second particular value; and
perform a second logical operation on the third signaling and the second signaling,
wherein a result of the second logical operation is indicative of the potential error condition being underflow of the FIFO memory.