Patent ID: 11880265
Assignee: NVIDIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. A device comprising:
a data link (DL) receiver, a logic device, and a counter, the device to:
receive a first set of data frames;
perform an error detection operation on each data frame of the first set of data frames received;
update a counter value, at the counter, to a first count value corresponding to a number of errors detected in response to performing the error detection operation on each data frame;
receive a period marker signal, at the counter from the logic device, at an end of a programmable period;
reset the first count value to zero in response to receiving the period marker signal and a decrement signal having a zero value; or
reduce the first count value to a second count value in response to receiving the period marker signal from the logic device and the decrement signal having a non-zero value; or
reset the first count value to zero in response to receiving a reset signal; and
output a first interrupt responsive to the first count value or the second count value satisfying a threshold number of errors.