Patent ID: 11871571
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of fabricating a three-dimensional semiconductor device, comprising:
preparing a substrate including a first region and a second region;
forming a mold structure comprising first layers and second layers alternately stacked on the substrate,
patterning a portion of the mold structure to form a staircase structure on the second region;
forming a planarized dielectric layer covering the staircase structure of the mold structure;
forming a plurality of vertical patterns on the first region;
forming a plurality of supporters on the second region; and
removing the second layers to form gate regions between the first layers, the gate regions exposing portions of each of the vertical patterns and portions of each of the supporters; and
forming gate electrodes in the gate regions.