Patent ID: 11894463
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 16:
17. A method of manufacturing an integrated circuit, the method comprising:
alternately forming a plurality of semiconductor layers and a plurality of sacrificial layers on a substrate;
patterning the plurality of semiconductor layers and the plurality of sacrificial layers to form a channel stack extending in a first direction;
forming a dummy gate structure on the channel stack, the dummy gate structure including a dummy gate insulating layer pattern and a dummy gate;
forming a spacer structure on a sidewall of the dummy gate structure, the spacer structure including a first spacer layer and a second spacer layer, the first spacer layer including a portion overhanging laterally and outwardly, and the second spacer layer including a lateral extension extending outwardly;
forming a plurality of semiconductor patterns and forming a recess region by removing a portion of the channel stack, the portion of the channel stack being not covered by the spacer structure;
forming a semiconductor layer in the recess region, a portion of the semiconductor layer being covered by the lateral extension;
forming a gate space by removing the dummy gate structure and the plurality of sacrificial layers; and
forming a gate electrode in the gate space,
wherein a top surface of an uppermost one of the plurality of semiconductor patterns has a first width in the first direction, and a bottom surface of the uppermost one of the plurality of semiconductor patterns has a second width smaller than the first width in the first direction.