Patent ID: 11886737
Assignee: INFINEON TECHNOLOGIES AG
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A memory device comprising:
a plurality of processor memory cells for storing first data;
a plurality of legacy memory cells for storing second data, different than the first data;
a memory interface coupled to the plurality of processor memory cells and the plurality of legacy memory cells, the memory interface configured to store and retrieve the first data at the plurality of processor memory cells and the second data at the plurality of legacy memory cells, the memory interface configured to receive first instructions to perform mathematic and logic operations on the first data stored in the plurality of processor memory cells;
a logic unit coupled to the plurality of processor memory cells, the logic unit comprising digital circuitry configured to perform the mathematic and logic operations on the first data stored in the plurality of processor memory cells; and
a control circuitry coupled to the memory interface and the logic unit, the control circuitry configured to control the memory interface to store and retrieve the first data and the second data, control the logic unit, and determine if the logic unit can perform the mathematic and logic operations on the first data,
wherein in response to the control circuitry determining that the logic unit can perform the mathematic and logic operations on the first data, the control circuitry is configured to cause the logic unit to perform the mathematic and logic operations on the first data, and
wherein in response to the control circuitry determining that the logic unit cannot perform the mathematic and logic operations on the first data, the control circuitry is configured to command the memory interface to output the first data and second instructions to perform the mathematic and logic operations on the first data.