Patent ID: 11935865
Assignee: MITSUI MINING & SMELTING CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for producing a semiconductor package, the method comprising:
(a) providing a tacky sheet comprising a substrate sheet, a soluble tacky layer provided in an intermittent pattern on at least one surface of the substrate sheet, and a linear banking tacky layer surrounding a periphery of a region wherein the soluble tacky layer exists on the surface;
(b) making a first laminate comprising a redistribution layer on a first support substrate;
(c) using the tacky sheet to obtain a second laminate having a second support substrate bonded to a surface on the redistribution layer side of the first laminate with the soluble tacky layer and the banking tacky layer interposed therebetween;
(d) peeling off the first support substrate from the second laminate to obtain a third laminate wherein a surface of the redistribution layer away from the second support substrate is exposed;
(e) immersing the third laminate in a developing solution and/or immersing the third laminate in a stripping solution for a dry film resist and/or immersing the third laminate in in a copper sulfate plating solution to perform a pretreatment for chip mounting on the surface of the redistribution layer away from the second support substrate;
(f) mounting a semiconductor chip on the pretreated surface of the redistribution layer;
(g) immersing the third laminate mounted with the semiconductor chip in a solution to dissolve or soften only the soluble tacky layer or both of the soluble tacky layer and the banking tacky layer; and
(h) peeling off the second support substrate from the third laminate in a state where only the soluble tacky layer is dissolved or softened or both of the soluble tacky layer and the banking tacky layer are dissolved or softened to obtain the semiconductor package.