Patent ID: 11907571
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A method for operating a memory system, which includes a memory device including a plurality of cells and a controller coupled to the memory device, the method comprising:
receiving under direction of a read processor of the controller a read request from a host device;
performing, in response to the read request, under direction of the read processor of the controller multiple read operations on the plurality of cells using multiple read threshold voltages of a read threshold set and at least one read retry threshold set, each of the threshold sets including first and second read thresholds, the multiple read operations acquiring voltages from the plurality of cells of the memory device in order to read data from the plurality of cells of the memory device;
decoding under direction of the controller the data associated with each of the read operations utilizing a decoder in the controller that determines if the multiple read operations using the multiple read threshold voltages of the read threshold set have failed;
determining under direction of an optimum read threshold determiner of the controller, for the decoded data determined in the controller of each of the read operations, an asymmetric ratio (AR) and a number of unsatisfied checks (USCs), the AR indicating a ratio of a number of a first binary value to a number of a second binary value in the decoded data;
determining under direction of the optimum read threshold determiner of the controller, from the decoded data determined in the controller, a Z-axis extending diagonally along two ranges of read threshold values such that AR values of the threshold sets are arranged in a set order along the Z-axis;
determining under direction of the optimum read threshold determiner of the controller, from the decoded data determined in the controller, an optimum read threshold set using coordinate values on the Z-axis, which correspond to a set AR value and a set USC value;
reading under direction of the read processor the data from the plurality of cells using the optimum read threshold set; and
transmitting under direction of the read processor the read data to the host device, wherein
the controller, in response to determining the optimum read threshold set, determines the coordinate values on the Z-axis using only the previously decoded data determined in the controller associated with previous read attempts without needing extra reads to search for an optimum read threshold for soft decoding, and
the controller without needing the extra reads to search for the optimum read threshold thereby reduces a read latency and improves a quality of service of the memory device.