Patent ID: 11923849
Assignee: QUALCOMM INCORPORATED
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 4:
5. A frequency divider, comprising:
a differential clock source configured to output a positive input clock signal and a negative input clock signal that is a complement of the positive input clock signal;
a plurality of N latches, wherein N is a plural positive integer greater than two;
a plurality of N first logic gates, each first logic gate having a first output terminal coupled to a reset input terminal of a corresponding one of the latches, each first logic gate being configured to process a unique pair of overlapping clock signals from a plurality of 2N overlapping clock signals with one of the positive input clock signal and the negative input clock signal to output, at the first output terminal, a corresponding non-overlapping clock signal from a first plurality of N non-overlapping clock signals; and
a plurality of N second logic gates, each second logic gate having a second output terminal coupled to a set input terminal of a corresponding one of the latches, each second logic gate being configured to process a unique pair of overlapping clock signals from the plurality of 2N overlapping clock signals with one of the positive input clock signal and the negative input clock signal to output, at the second output terminal, a corresponding non-overlapping clock signal from a second plurality of N non-overlapping clock signals.