Patent ID: 11901434
Assignee: QUALCOMM INCORPORATED
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An apparatus comprising:
a semiconductor die comprising:
an insulation layer disposed on a substrate;
a gate spacer disposed in the insulation layer;
a gate disposed between the gate spacer;
a first dielectric gate layer disposed on the gate between the gate spacer;
a second dielectric gate layer disposed on the first dielectric gate layer between the gate spacer;
a gate contact coupled to the gate and in contact with the first dielectric gate layer and the second dielectric gate layer;
a source/drain contact, wherein the source/drain contact has a single inner spacer; and
a local interconnect disposed on the source/drain contact, wherein the local interconnect is in contact with the second dielectric gate layer and wherein the gate is not in contact with the second dielectric gate layer.