Patent ID: 11886835
Assignee: CEREMORPHIC, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 16:
17. The multi-stage multiplier of claim 12 where at least one sub-multiplier comprises:
a plurality of AND gates equal in number to the number of sub-value bits, each AND gate having one input coupled to a unique one of the sub-value A bits and the other input coupled to a common one of the sub-value B bits;
each AND gate having an output coupled to a unique analog charge line through a charge transfer capacitor;
each analog charge line coupled to a first terminal of a respective charge scaling capacitor of a charge summing block;
each charge scaling capacitor having a second terminal connected to the input of an analog to digital converter;
the output of the analog to digital converter forming the output of the sub-multiplier.