Patent ID: 11862217
Assignee: TOHOKU UNIVERSITY
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 16:
17. A device, comprising:
an MRAM configured to include multiple memory cells separated into multiple regions including selection transistors and MTJs;
a nonvolatile CPU configured to include a nonvolatile memory;
a nonvolatile FPGA-ACC configured to include a nonvolatile memory and execute a part of operations on the nonvolatile CPU; and
a power-gating controller configured to control power supply to each memory cell in the MRAM, the nonvolatile CPU, and the nonvolatile FPGA-ACC,
the device further comprising:
an access controller configured to control an access to the MRAM by reading and storing data in advance and backing up the data when the data are to be read from the MRAM, wherein
the access controller comprises:
an address-storing register configured to receive an input about an MRAM address that is a reading destination, the address-storing resister storing the address;
a multiplexer configured to output multiple destinations of the MRAM stored in the address-storing register to the MRAM for reading;
multiple data-storing registers configured to store data read from the MRAM; and
a comparator configured to receive a reading instruction together with a specified reading destinations and to compare an address related to the specified reading destination with a reading address stored in the address-storing register, wherein

the access controller configured to receive a reading instruction together with a specified reading destinations and to output data already read and stored in any one of the plurality of data-storing registers in response to the reading instruction when the comparator determines the data have been read from the MRAM in advance.