Patent ID: 11900522
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. The method of claim 1, comprising:
when the group of plural execution lanes are performing the set of processing operations in the co-operative state: the graphics processor encountering a first event that means that a first subset of one or more execution threads associated with a corresponding one or more of the execution lanes in the group of execution lanes in the co-operative state should be terminated, but wherein the condition to immediately terminate the first execution thread is not met, such that the group of execution lanes continue their execution in the co-operative state, and a record is stored that the threads in the first subset of one or more execution threads should subsequently be terminated; and
whilst the group of plural execution lanes are continuing to perform the set of processing operations in the co-operative state: in response to the graphics processor encountering a second event that means that a second subset of one or more execution threads associated with a corresponding one or more other of the execution lanes in the group of execution lanes in the co-operative state should be terminated: determining whether a condition to immediately terminate the first and second subsets of execution threads is met, and when the condition to immediately terminate the first and second subsets of execution threads is met, the group of execution lanes exiting the co-operative state and the execution unit terminating the first and second subsets of execution threads.