Patent ID: 11923238
Assignee: QORVO US, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 20:
21. The method of claim 1 wherein providing the precursor wafer comprises:
providing a starting wafer that includes a common silicon epitaxial layer, a common interfacial layer over the common silicon epitaxial layer, and the silicon handle substrate over the common interfacial layer, wherein the common interfacial layer is formed of SiGe; and
performing a complementary metal-oxide-semiconductor (CMOS) process to provide the precursor wafer, wherein:
the isolation sections extend through the common silicon epitaxial layer and the common interfacial layer and extend into the silicon handle substrate, such that the common interfacial layer is separated into the plurality of individual interfacial layers, and the common silicon epitaxial layer is separated into a plurality of individual silicon epitaxial layers;
each active layer of the plurality of device regions is formed from a corresponding individual silicon epitaxial layer; and
each of the plurality of individual interfacial layers resides over a top surface of a corresponding active layer, and the silicon handle substrate resides over each of the plurality of individual interfacial layers.