Patent ID: 11950422
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. An assembly, comprising:
a vertical stack of alternating insulative levels and wordline levels, the wordline levels comprising conductive regions;
charge-storage regions adjacent the conductive regions and having upper surfaces and lower surfaces, each of the upper and lower surfaces contacting an insulative material of the insulative levels, each of the charge-storage regions having a first vertically curved face and an opposing second vertical face;
charge-blocking regions between the charge-storage regions and the conductive regions, each of the charge-blocking regions having a third vertical face and an opposing fourth vertical face; each of the first, second third and fourth vertical faces being curved;
a first tunneling material entirely within the wordline levels and having concave opposing inner and outer faces; and
a second tunneling material extending along the first tunneling material and along and in direct physical contact with the insulative levels.