Patent ID: 11862282
Assignee: CEREMORPHIC, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 8:
9. A memory performing a logical AND or logical NAND operation, the memory comprising:
a first Single Transistor Static Random Access Memory (STSRAM) having a source, drain, and gate, and storing a charge value which influences a conductivity from the drain to the source when the gate is enabled;
a second STSRAM having a source, drain, and gate, and storing a charge value which influences a conductivity from the drain to the source when the gate is enabled;
a select line (SL) coupled to the first STSRAM drain and also to the second STSRAM drain;
a Bit Line (BL) node coupled to the first STSRAM source, the second STSRAM source, and to a noninverting input of a current comparator amplifier (CCA), the CCA having an inverting input coupled to a current source Iref, the CCA generating a binary output by comparing a combined current IBL from the first STSRAM and second STSRAM delivered to the noninverting input of the CCA to a current Iref delivered to the inverting input of the CCA;
Iref being set to a current Iref11 which is greater than IBL when only one of the first STSRAM or second STSRAM has a stored charge;
the first STSRAM and the second STSRAM having respective stored charge which generate to the noninverting input of the CCA:
a first current when a charge is not stored in the first STSRAM and the second STSRAM;
a second current when a charge is stored in one of the first STSRAM or the second STSRAM;
a third current when a charge is stored in both the first STSRAM and the second STSRAM.