Patent ID: 11960408
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A semiconductor memory device comprising:
a unit page buffer block including first to fourth page buffer pairs arranged in a column direction,
wherein each of the first to fourth page buffer pairs comprises:
a common column decoder block; and
an upper page buffer stage and a lower page buffer stage electrically connected to a corresponding common column decoder block,
wherein the common column decoder block includes first and second sub-common column decoder blocks,
wherein the upper page buffer stage comprises:
an upper selection block;
an upper latch block; and
an upper cache block,
wherein the lower page buffer stage comprises:
a lower selection block;
a lower latch block; and
a lower cache block,
wherein:
the upper selection block includes a first upper unit selection block and a second upper unit selection block arranged in the column direction;
the upper latch block includes first and second upper sub-latch blocks arranged in the row direction,
the upper cache block includes first and second upper sub-cache blocks arranged in the row direction,
the lower selection block includes a first upper unit selection block and a first lower unit selection block arranged in the column direction,
the lower latch block includes first and second lower sub-latch blocks arranged in the row direction,
the lower cache block includes first and second lower sub-cache blocks arranged in the row direction,
the first upper unit selection block, the first upper sub-latch block, and the first upper sub-cache block are electrically connected to each other,
the second upper unit selection block, the second upper sub-latch block, and the second upper sub-cache block are electrically connected to each other,
the first lower unit selection block, the first lower sub-latch block, and the first lower sub-cache block are electrically connected to each other,
the second lower unit selection block, the second lower sub-latch block, and the second lower sub-cache block are electrically connected to each other,
the first upper sub-cache block and the first lower sub-cache block are commonly electrically connected to the first sub-common column decoder, and
the second upper sub-cache block and the second lower sub-cache block are commonly electrically connected to the second sub-common column decoder block.