Patent ID: 11929674
Assignee: STMICROELECTRONICS S.R.L.
Field: Electrical machinery, apparatus, energy (Electrical engineering)
Classification: CPC H | IPC H

Claim 19:
20. A method comprising:
receiving an input voltage at an input node;
generating an output voltage at an output node that is coupled to an output capacitor, the output voltage being higher than the input voltage, wherein an ordered sequence of intermediate voltage nodes is arranged between the input node and the output node, the ordered sequence comprising a first ordered sub-sequence of intermediate voltage nodes and a second ordered sub-sequence of intermediate voltage nodes, wherein a respective capacitor is coupled between each odd-numbered intermediate voltage node in the second ordered sub-sequence of the ordered sequence and a corresponding odd-numbered intermediate voltage node in the first ordered sub-sequence of the ordered sequence, wherein a respective capacitor is coupled between each even-numbered intermediate voltage node in the second ordered sub-sequence of the ordered sequence and a corresponding even-numbered intermediate voltage node in the first ordered sub-sequence of the ordered sequence, and wherein a first plurality of selectively conductive electronic components is coupled to the intermediate voltage nodes of the ordered sequence;
receiving a first clock signal at a first input control node, wherein a respective capacitor is coupled between each odd-numbered intermediate voltage node in the first ordered sub-sequence of the ordered sequence and the first input control node, wherein a first intermediate voltage node in the first ordered sub-sequence is selectively couplable to the input node;
receiving a second clock signal at a second input control node, the second clock signal being in phase opposition to the first clock signal, wherein a respective capacitor is coupled between each even-numbered intermediate voltage node in the first ordered sub-sequence of the ordered sequence and the second input control node;
switching between a first commutation state and a second commutation state based on the first and second clock signals;
in the first commutation state, providing, using the first plurality of selectively conductive electronic components, electrically-conductive paths between each of the even-numbered intermediate voltage nodes of the ordered sequence and a respective next odd-numbered intermediate voltage node of the ordered sequence, an electrically-conductive path between the input node and the first intermediate voltage node of the ordered sequence, and an electrically-conductive path between a last intermediate voltage node of the ordered sequence and the output node; and
in the second commutation state, providing, using the first plurality of selectively conductive electronic components, electrically-conductive paths between each of the odd-numbered intermediate voltage nodes of the ordered sequence and a respective next even-numbered intermediate voltage node of the ordered sequence.