Patent ID: 11935798
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. A method, comprising:
configuring a control circuit, included in a first die of a stacked semiconductor device, in a first configuration,
wherein the control circuit being in the first configuration causes a first transistor to block a die-to-die interconnect between the first die and a second die of the stacked semiconductor device;

performing a first electrical test of the first die while the die-to-die interconnect is blocked,
wherein the first die is independently tested;

configuring the control circuit in a second configuration,
wherein the control circuit being in the second configuration causes:
the first transistor to provide a first conductive path between the first die and the second die, and
a second transistor to block a second conductive path between circuits of the first die; and

performing a second electrical test of the second die while the first conductive path is provided,
wherein the second die is independently tested.