Patent ID: 11899242
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 8:
9. A method comprising:
forming an optical feature on a first integrated circuit die;
forming an interconnect structure overlying the first integrated circuit die, the interconnect structure including a plurality of stacked dielectric layers wherein optical interfaces exist between respective ones of the stacked dielectric layers;
forming a gap in the interconnect structure by removing a portion of the interconnect structure overlying the optical feature; and

filling the gap and covering the interconnect structure with a first bonding dielectric layer;
fusion bonding a second integrated circuit die to the first bonding dielectric layer; and
forming a protective layer over the first bonding dielectric layer and encapsulating the second integrated circuit die, wherein the protective layer and the first bonding dielectric layer form an optical path over the optical feature.