Patent ID: 11880714
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. A method comprising:
determining, by executing an instruction with at least one processor, first device type property information of a first accelerator of a first device;
determining, by executing an instruction with the at least one processor, second device type property information of a second accelerator of a second device;
partitioning, by executing an instruction with the at least one processor, first instructions into a first portion and a second portion, the partitioning capable of being based on (a) a first latency associated with processing the first portion of the first instructions with the first accelerator of the first device, (b) a second latency associated with processing the second portion of the first instructions with the second accelerator of the second device, (c) the first device type property information of the first accelerator of the first device, and (d) the second device type property information of the second accelerator of the second device;
outputting, by executing an instruction with the at least one processor, the first portion of the first instructions to the first accelerator of the first device; and
outputting, by executing an instruction with the at least one processor, the second portion of the first instructions to the second accelerator of the second device.