Patent ID: 11881859
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A system comprising:
a logic circuit adapted to be coupled to a first voltage supply;
a load circuit; and
a buffer circuit coupled between the logic circuit and the load circuit, the buffer circuit including:
an inverter including:
a first pull-down transistor having a control terminal and first and second terminals, the first terminal adapted to be coupled to a second voltage supply;
a second pull-down transistor having a control terminal and first and second terminals, the first terminal of the second pull-down transistor coupled to the second terminal of the first pull-down transistor;
a pull-up resistor having first and second terminals, the first terminal of the pull-up resistor adapted to be coupled to a third voltage supply that provides a voltage higher than a voltage of the first voltage supply; and
a pull-up transistor having a control terminal and first and second terminals, the first terminal of the pull-up transistor coupled to the second terminal of the pull-up resistor, the second terminal of the pull-up transistor coupled to the second terminal of the second pull-down transistor, the control terminals of the first and second pull-down transistors and the pull-up transistor coupled together, wherein a threshold voltage of the first pull-down transistor is less than a threshold voltage of the pull-up transistor, and a threshold voltage of the second pull-down transistor is less than the threshold voltage of the first pull-down transistor;
a hysteresis transistor having a control terminal and first and second terminals, the control terminal of the hysteresis transistor coupled to the second terminals of the pull-up transistor and the second pull-down transistor, the first terminal of the hysteresis transistor coupled to the second terminal of the pull-up resistor and to the first terminal of the pull-up transistor, the second terminal of the hysteresis transistor coupled to the first terminal of the first pull-down transistor; and
a clamp circuit having a first terminal coupled to the first terminal of the first pull-down transistor and having a second terminal coupled to the second terminal of the first pull-down transistor.