Patent ID: 11929321
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 19:
20. The method as claimed in claim 15, further comprising:
forming a second gate electrode layer in the first insulating layer and across the fin structure during the formation of the first gate electrode layer;
forming a second source/drain contact electrically connected to a second source/drain region in the fin structure during the formation of the first source/drain contact;
forming a third via opening and a fourth via opening in the second insulting layer to expose the second gate electrode layer and the second source/drain contact, respectively, during the formation of the first via opening and the second via opening;
forming a third metal via in a third via opening to connect the second gate electrode layer, and a fourth metal via in the fourth via opening and to connect the second source/drain contact; and
selectively growing a third metal hump from a top surface of the third metal via and a fourth metal hump from a top surface of the fourth metal via during the growth of the first metal hump and the second metal hump,
wherein the first metal hump and the third metal hump are laterally merged with each other and fully fill the first trench opening, and the second metal hump and the fourth metal hump are laterally merged with each other and fully fill the second trench opening.