Patent ID: 11886746
Assignee: DREAMBIG SEMICONDUCTOR INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G

Claim 0:
1. A content addressable memory circuit comprising:
an interface to receive a key value;
multiple integrated circuit memory devices that share common memory address locations that are coupled for simultaneous access;
hash logic operative to determine a hash value, based upon the received key value, that corresponds to a common memory address location of the memory devices;
a non-transitory storage device that includes,
a hash information structure that stores multiple hash values determined using the hash logic, wherein the hash information structure associates each hash value with a corresponding common memory address location of the memory devices; and
an activity status information structure that stores information that indicates, for multiple common memory address locations for each memory device, whether the memory device stores content data at the common memory address location; and

memory controller logic to perform operations comprising:
in a read mode,
in response to the hash logic generating a hash value based upon a received key value, wherein the generated hash value is one of the hash values stored in the hash information structure, selecting one or more memory devices from which to output stored content data from a common memory address location that is associated with the hash value that is generated by the hash logic, based upon information stored in the storage activity status information structure for the common memory address location that is associated with the hash value that is generated by the hash logic; and
causing the selected one or more memory devices to output respective stored content data.