Patent ID: 11934480
Assignee: MACRONIX INTERNATIONAL CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A circuit comprising:
three or more multiply-and-accumulate accelerator tiles in an integrated circuit, each tile comprising:
a plurality of NAND blocks, each NAND block having inputs and outputs;
input data paths connected to the NAND block inputs;
output data paths connected to the NAND block outputs;
a plurality of bit lines coupled to the plurality of NAND blocks, and a plurality of block source lines coupled to the plurality of NAND blocks;
input drivers coupled to at least some of the bit lines in the plurality of bit lines;
current sense amplifiers coupled to at least some of the source lines in the plurality of source lines; and
page buffers coupled to at least some of the bit lines in the plurality of bit lines;

an inter-tile bus system on the integrated circuit coupled to the input and output data paths of the three or more multiply-and-accumulate accelerator tiles, wherein the inter-tile bus system is configured to control data flows among the tiles; and
input/output circuits on the integrated circuit coupled to the inter-tile bus system.