Patent ID: 11950402
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 14:
15. A method comprising:
forming a conductive region;
forming first memory cell including a first transistor and a second transistor, the first transistor including a first channel region over the conductive region, and a first charge storage structure separated from the first channel region and the conductive region, the second transistor including a second channel region formed over the first charge structure;
forming a second memory cell including a third transistor and a fourth transistor, the third transistor including a third channel region over the conductive region, and a second charge storage structure separated from the third channel region and the conductive region, the fourth transistor including a fourth channel region formed over the second charge structure;
forming a conductive structure between and electrically separated from the first and second charge storage structures; and
forming a conductive line to form a gate of each of the first, second, third, and fourth transistors.