Patent ID: 11967583
Assignee: MONOLITHIC 3D INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 7:
8. A semiconductor device, the device comprising:
a substrate;
a first metal layer disposed over said first substrate;
a second metal layer disposed over said first metal layer;
a first level comprising a plurality of transistors, said first level disposed over said second metal layer,
wherein said plurality of transistors comprise single crystal silicon;

a third metal layer disposed over said first level;
a fourth metal layer disposed over said third metal layer,
wherein said fourth metal layer is aligned to said first metal layer with a less than 200 nm alignment error; and

a via disposed through said first level,
wherein at least a portion of said third metal layer and a portion of said fourth metal layer are part of heat removal paths, and
wherein said heat removal paths are designed to remove heat from said plurality of transistors to an external surface of said device.