Patent ID: 11929116
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. A method for operating a memory device, the method comprising:
receiving a write enable signal indicating a write operation in a memory device comprising a memory cell and a bit line connected to the memory cell;
generating a write assist enable signal in response to the write enable signal;
enabling a negative voltage generator in response to the write assist signal attaining a first value, the negative voltage generator providing a first write path to the bit line; and
enabling, by a pull down circuit, a second write path to the bit line in response to the write assist signal attaining a second value, wherein enabling the second write path comprises switching on a pull down transistor connected between the between the bit line and ground in response to the write assist enable signal attaining a second value, wherein the pull down circuit comprises a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the pull down circuit is operative to receive data signal, wherein the second input terminal of the pull down circuit is directly connected to the negative voltage generator and is operative to receive the write assist enable signal that is being provided to the negative voltage generator.