Patent ID: 11862610
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of forming fan-out packages, comprising:
attaching an array of complementary die sets to a carrier substrate, wherein the array of complementary die sets has a first periodicity along a first horizontal direction and has a second periodicity along a second horizontal direction that is perpendicular to the first horizontal direction, and wherein each complementary die set comprises a first complementary die comprising a first pair of complementary-die sidewalls laterally extending along a third horizontal direction and comprising a second pair of complementary-die sidewalls laterally extending along a fourth horizontal direction that is perpendicular to the third horizontal direction;
forming a continuous complementary-level molding compound layer around the array of complementary die sets and over the carrier substrate;
attaching an array of primary semiconductor dies to the array of complementary die sets;
forming a continuous primary-level molding compound layer around the array of primary semiconductor dies; and
dicing a bonded assembly including the array of primary semiconductor dies, the continuous primary-level molding compound layer, the array of complementary die sets, the continuous complementary-level molding compound layer, and the carrier substrate into a plurality of fan-out packages by cutting the bonded assembly along first dicing channels that are parallel to the first horizontal direction and along second dicing channel that are parallel to the second horizontal direction,
wherein the method comprises at least one feature selected from:
a first feature that the third horizontal direction is not parallel to the first horizontal direction or the second horizontal direction;
a second feature that each of the primary semiconductor dies comprises a respective primary single crystalline semiconductor substrate, and a <100> crystallographic direction of each of the primary single crystalline semiconductor substrate is aligned along a primary <100> crystallographic lattice direction that is azimuthally offset from the first horizontal direction and from the second horizontal direction by at least 0.5 degree;
a third feature that each of the first complementary dies comprises a respective complementary single crystalline semiconductor substrate, and a <100> crystallographic direction of each of the complementary single crystalline semiconductor substrates is aligned along a complementary <100> crystallographic lattice direction that is azimuthally offset from the first horizontal direction and from the second horizontal direction by at least 0.5 degree; and
a fourth feature that the carrier substrate comprises a single crystalline carrier semiconductor substrate having a <100> crystallographic lattice direction that is azimuthally offset from the first horizontal direction and from the second horizontal direction.