Patent ID: 11927982
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G  H

Claim 15:
16. A system comprising:
a memory;
a processor coupled to the memory; and
a wireless interface to allow the processor to communicate with another device, wherein the processor includes an integrated clock gate which comprises:
an OR-AND-INVERT gate to receive a first enable and a second enable;
a first inverter coupled to the output of the OR-AND-INVERT;
a first NAND gate coupled to the output of the first inverter;
a second NAND gate coupled to the output of the OR-AND-INVERT; and
a second inverter to provide a clock which is gated based on logic values of the first enable and/or the second enable, wherein an output of the second inverter is received as input by the OR-AND-INVERT-gate.