Patent ID: 11947451
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 16:
17. A memory system, comprising:
one or more memory arrays; and
one or more controllers coupled with the one or more memory arrays and configured to cause the memory system to:
determine whether a quantity of read operations performed on a portion of a memory array of the one or more memory arrays satisfies a first threshold;
determine whether a quantity of physical addresses of the portion of the memory array satisfies a second threshold based at least in part on determining that the quantity of read operations satisfies the first threshold;
generate a descriptor for the portion of the memory array based at least in part on determining that the quantity of physical addresses of the portion of the memory array satisfies the second threshold; and
store the descriptor in a cache associated with the memory array.