Patent ID: 11881860
Assignee: SK HYNIX INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 3:
4. A multi-phase clock signal alignment circuit comprising:
a plurality of phase delay circuits configured to control delays of a plurality of multi-phase input clock signals to produce a plurality of multi-phase clock signals, respectively;
a plurality of phase mixing circuits configured to mix phases of the multi-phase clock signals to produce multi-phase output clock signals;
a clock selection circuit configured to select alpha and beta clock signals from among the multi-phase clock signals or from among the multi-phase output clock signals;
a first clock delay circuit configurable to provide a first selection clock signal by outputting the alpha clock signal and configurable to provide the first selection clock signal by adjusting a delay, a phase, both of the alpha clock signal;
a second clock delay circuit configurable to provide a second selection clock signal by outputting the beta clock signal and configurable to provide the second selection clock signal by adjusting a delay, a phase, or both of the beta clock signal;
a phase detection circuit configured to detect a phase difference between the first selection clock signal and the second selection clock signal; and
a phase control circuit configured to control the delays of the plurality of the phase delay circuits according to an output of the phase detection circuit.