Patent ID: 11915735
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. An apparatus, comprising:
tiers of memory cells including a first tier of memory cells and a second tier of memory cells; and
a controller configured to cause the apparatus to:
couple a first memory cell in the first tier of memory cells with a first digit line and coupling, concurrently with coupling the first memory cell, a second memory cell in the second tier of memory cells with a second digit line;
couple the first digit line with a first sense component in the first tier and coupling, concurrently with coupling the first digit line, the second digit line with a second sense component in the second tier; and
sense the first memory cell using the first sense component and sensing, concurrently with sensing the first memory cell, the second memory cell using the second sense component, wherein the first memory cell is sensed based at least in part on coupling the first digit line with the first sense component, and wherein the second memory cell is sensed based at least in part on coupling the second digit line with the second sense component.