Patent ID: 11956957
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 18:
19. A semiconductor memory device comprising:
a common source plate on a substrate;
a first stacked structure on the common source plate, the first stacked structure including first gate electrodes stacked in a first direction;
a first supporter layer on the first stacked structure and separated in a second direction intersecting the first direction, the first supporter layer separated by a first cut pattern;
a second stacked structure on the first stacked structure, the second stacked structure including second gate electrodes stacked in the first direction;
a plurality of first sub-cut structures cutting the first stacked structure and the second stacked structure and arranged in the second direction;
a second sub-cut structure between the first sub-cut structures that are spaced apart from each other in the second direction and being among the plurality of first sub-cut structures, the second sub-cut structure cutting the second stacked structure;
a channel structure including (a) a lower channel structure penetrating the first stacked structure, and (b) an upper channel structure penetrating the first supporter layer and the second stacked structure, side walls of the channel structure having a step;
a second supporter layer on the second stacked structure and separated in the second direction by a second cut pattern; and
a bit line on the second supporter layer, the bit line extending in the first direction, the bit line connected to the channel structure,
wherein the first stacked structure includes a first stack and a second stack separated from each other by the plurality of first sub-cut structures, and a first connection stack below the second sub-cut structure, the first connection stack connecting the first stack and the second stack,
the second stacked structure includes third stacks separated from each other by the plurality of first sub-cut structures and the second sub-cut structure and placed on the first stack, and a fourth stack on the second stack,
the first cut pattern includes a plurality of first connections which overlaps the plurality of first sub-cut structures and the second sub-cut structure in the first direction, the first cut pattern on the first connection stack in the first direction,
the second cut pattern includes a plurality of second connections which overlaps the plurality of first sub-cut structures and the second sub-cut structure in the first direction and arranged in the second direction,
a number of the plurality of first connections is greater than a number of the plurality of second connections, and
a ratio of an area of the first connection to an area of the first supporter layer is different than a ratio of an area of the second connection to an area of the second supporter layer.