Patent ID: 11925012
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A capacitor array structure, comprising:
a substrate, a capacitor contact being exposed on a surface of the substrate, the substrate comprising an array region and a peripheral region, and the capacitor contact being located at the array region;
a bottom supporting layer covering a surface of the substrate and a side wall of the capacitor contact, the bottom supporting layer having a gap therein;
a filling layer filling the gap and covering the capacitor contact and the surface of the bottom supporting layer, a thickness of the filling layer located at the peripheral region being larger than that of the filling layer located at the array region;
a capacitor comprising a lower electrode layer located on the substrate and electrically connected to the capacitor contact, a dielectric layer covering a surface of the lower electrode layer and an upper electrode layer covering a surface of the dielectric layer; and
a plurality of supporting layers connected to a side wall of the lower electrode layer.