Patent ID: 11942977
Assignee: HUAWEI TECHNOLOGIES CO., LTD.
Field: Telecommunications (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A system for calibrating sampler voltage offset drift, the system comprising:
a serializer/deserializer (SerDes) receiver configured to receive a signal, the SerDes receiver comprising a first data sampler having a first voltage offset, a second data sampler having a second voltage offset, a comparator to detect when a first output of the first data sampler differs from a second output of the second data sampler, and calibration circuitry;
wherein the first and second data samplers are configured to convert the received signal in analog form into a digital serial stream;
wherein the calibration circuitry is configured:
cause an initial operating condition of the first data sampler to match the second data sampler, wherein matching the initial operating condition of the first data sampler with the second data sampler comprises adjusting the second voltage offset of the second data sampler until a sampling threshold of the second data sampler matches a sampling threshold of the first data sampler;
adjust the first voltage offset of the first data sampler in a first voltage direction until a bit error rate between the first output of the first data sampler and the second output of the second data sampler meets a first threshold bit error rate value at a first threshold voltage offset value;
adjust the first voltage offset of the first data sampler in a second voltage direction, opposite to the first voltage direction, until the bit error rate between the first output of the first data sampler and the second output of the second data sampler meets a second threshold bit error rate value at a second threshold voltage offset value; and
set the first voltage offset to a value between the first threshold voltage offset value and the second threshold voltage offset value;
a Serial-In Parallel-Out (SIPO) converter configured to convert the sampled digital serial stream to multiple parallel data streams; and
a forward error correction (FEC) module configured to apply error correction, wherein the first threshold bit error rate value and the second threshold bit error rate value are less than or equal to a FEC limit of the FEC module, wherein the FEC module is configured to apply error correction on the parallel data streams output by the SIPO converter.