Patent ID: 11887693
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A system, comprising:
a memory array to store data in a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines;
a sense amplifier array coupled to the memory array;
a logic array integrated with the sense amplifier array, the logic array to implement a configurable logic controlling the plurality of memory cells; and
a control block coupled to the memory array and the logic array, the control block to control a computational pipeline to perform computations on the data by activating at least one of: one or more bitlines of the plurality of bitlines or one or more wordlines of the plurality of wordlines,
wherein the control block is further to:
pre-charge a selected bitline of the plurality of bitlines; and
evaluate, using the configurable logic implementing multi-level voltage evaluation, a row of memory cells addressed by a selected wordline.