Patent ID: 11955157
Assignee: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 4:
5. The PUF apparatus according to claim 4,
wherein each of the plurality of column precharge blocks includes:
a first transmission gate which is connected between a bit line of a corresponding bit line pair and the voltage line, and which supplies the voltage of the voltage line to the bit line, according to the inactivated read enable signal and an inverted read enable signal in which the read enable signal is inverted; and
a second transmission gate which is connected between a bit line bar of a corresponding bit line pair and the voltage line, and which supplies the voltage of the voltage line to the bit line bar, according to the inactivated read enable signal and the inverted read enable signal.