Patent ID: 11968290
Assignee: KONINKLIJKE PHILIPS N.V.
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A function evaluation device comprising:
a memory circuit,
wherein the memory circuit is configured to store a function and circuit,
wherein the function is arranged to compute at least one function output bit(s) from a plurality of function input bits,
wherein each function output bit is representable as a sum of interpolation terms,
wherein each of the sum of interpolation term is a product of zero or more function input bits,
wherein the plurality of function input bits and the interpolation terms forming a plurality of interpolation terms,
wherein the circuit comprises:
circuit wires,
wherein the circuit wires comprise a plurality of input wires and at least one circuit output wire(s),
wherein the plurality of input wires correspond to the plurality of function input bits,
wherein the at least one output wire(s) correspond to the at least one function output bit(s);

at least one conjunction subcircuit(s),
wherein the at least one conjunction subcircuit(s) comprises a first conjunction subcircuit,

wherein each of the at least one or more conjunction subcircuit(s) is arranged to compute a conjunction of at least two function input bits,
wherein the first conjunction subcircuit is arranged to provide a circuit wire corresponding to a current interpolation term as a conjunction of a first circuit wire,
wherein the first circuit wire corresponds to a first interpolation term,
wherein the second circuit wire corresponds to a second interpolation term; and

at least one XOR subcircuit(s),
wherein each of the at least one XOR subcircuit(s) is arranged to compute the first function output bit,
wherein the first function output bit is computed by a current XOR subcircuit,
wherein the first function output bit is represented as a sum of current interpolation terms,
wherein the current XOR subcircuit provides an output wire of the at least one output wires(s) corresponding to the function output bit as a XOR of wires corresponding to the current interpolation terms; and

a processor circuit,
wherein the processor circuit is configured to obtain the plurality of input bits, wherein the processor circuit is configures to evaluate the function on the plurality of input bits by evaluating the circuit.