Patent ID: 11954466
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 20:
21. An apparatus to perform machine learning-guided compiler optimizations for register-based hardware architectures comprising:
an interface circuitry;
instructions;
a processor circuitry to at least one of execute or implement the instructions to:
select a register-based compiler transformation of register-based compiler transformations to apply to source code at a current position in a search tree;
prune the search tree at the current position in response to determining the search tree at the current position is in need of pruning based on an output of a query to a machine learning (ML) model;
apply a selected register-based compiler transformation to the source code to generate a code variant;
calculate a score associated with the source code and the generated code variant at the current position in the search tree; and
update parameters of the ML model to include the calculated score.