Patent ID: 11963352
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. The semiconductor structure of claim 11, wherein:
at least 50% of a total area of the at least one set of vertical field effect transistors has an areal overlap with a total area including each sense amplifier circuit and each bit line bias circuit in a plan view;
the electrically conductive layers comprise word lines of the three-dimensional NAND memory array;
layer contact via structures extend vertically through a dielectric material portion and contact a surface of a respective one of the electrically conductive layers;
a subset of the top electrodes of the at least one set of vertical field effect transistors is electrically connected to a respective one of the word lines; and
each set of vertical field effect transistors comprises a respective gate electrode that laterally surrounds each of the gate dielectrics within a same set of vertical field effect transistors.