Patent ID: 11968836
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A three-dimensional (3D) semiconductor memory device comprising:
a substrate including a cell array region and a connection region;
an electrode structure on the substrate, the electrode structure comprising gate electrodes stacked in a first direction vertical to a top surface of the substrate, and the gate electrodes including electrode pad regions on the connection region;
a first source conductive pattern between the substrate and the electrode structure and on the cell array region;
a lower sacrificial pattern between the substrate and the electrode structure and on the connection region;
a vertical semiconductor pattern penetrating the electrode structure and the first source conductive pattern on the cell array region; and
a dummy vertical semiconductor pattern penetrating one of the electrode pad regions on the connection region,
wherein the lower sacrificial pattern includes a different material from that of the first source conductive pattern.