Patent ID: 11937514
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Field: nan (nan)
Classification: CPC H | IPC H

Claim 14:
15. A semiconductor structure comprising:
two adjacent bottom electrodes in a layer of a first dielectric material and above a metal layer;
two adjacent pillars are each on one of the two adjacent bottom electrodes, wherein each pillar of the two adjacent pillars is composed of a stack of materials for a memory device;
a layer of a spacer material around vertical sides each of the two adjacent pillars and a thinner portion of the layer of the spacer material on surfaces of the first dielectric material;
a second dielectric material on the spacer, on the thinner portion of the spacer material on surfaces of the first dielectric material between the two adjacent pillars, wherein the second dielectric material fills at least a first portion of a gap between the two adjacent pillars; and
a low k material covering the second dielectric material and exposed portions of the thinner portion of the layer of the spacer material on exposed surfaces of the first dielectric material.