Patent ID: 11901025
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. The semiconductor memory device of claim 11, wherein the refresh control circuit includes:
a refresh control logic configured to generate a hammer refresh signal in response to a hammer event detection signal associated with the hammer address;
a refresh clock generator configured to generate a refresh clock signal in response to a refresh signal;
a refresh counter configured to generate a count refresh address associated with the normal refresh operation on the plurality of memory cell rows based on the refresh clock signal;
a hammer address storage configured to store the hammer address and configured to output the hammer address in response to the hammer refresh signal; and
a mapper configured to generate hammer refresh addresses designating addresses of the victim memory cell rows based on the hammer address output from the hammer address storage.