Patent ID: 11910594
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 10:
11. A semiconductor device comprising:
a substrate including:
a first region; and
a second region surrounding the first region,

the substrate including first and second active patterns on the first region and the second region, respectively, the first and second active patterns being defined by an isolation pattern on the substrate;
a first gate structure in an upper portion of the first active pattern;
a plurality of bit line structures on the first region of the substrate;
a first contact plug structure on the first active pattern and between two adjacent bit line structures of the plurality of bit line structures;
a capacitor on the first contact plug structure;
a plurality of key structures on the second region of the substrate, each of the plurality of key structures having an upper surface substantially coplanar with an upper surface of each of the plurality of bit line structures;
a trench disposed between two adjacent key structures of the plurality of key structures that are spaced apart from each other;
a filling pattern in a lower portion of the trench, the filling pattern having a flat upper surface and including a conductive material; and
a first conductive structure on the flat upper surface of the filling pattern, an upper sidewall of the trench, and the upper surface of each of the plurality of key structures.