Patent ID: 11948620
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 11:
12. An apparatus comprising:
a semiconductor substrate including a plurality of source regions and a plurality of drain regions alternately arranged; and
a plurality of gate electrodes each arranged between an associated one of the plurality of source regions and an associated one of the drain regions in a plan view,
wherein the plurality of source regions are coupled in common to a first power supply line,
wherein the plurality of drain regions are coupled in common to a second power supply line,
wherein the plurality of drain regions include first, second, and third drain regions,
wherein the plurality of source regions include a first source region arranged between the first and second drain regions, and a second source region arranged between the first and third drain regions,
wherein the plurality of gate electrodes include a first gate electrode arranged between the first source region and the first drain region in a plan view, a second gate electrode arranged between the second source region and the first drain region in a plan view, a third gate electrode arranged between the first source region and the second drain region in a plan view, and a fourth gate electrode arranged between the second source region and the third drain region in a plan view,
wherein the first and second gate electrodes are supplied with a first control signal in common, and
wherein the third and fourth gate electrodes are supplied with a second control signal different from the first control signal in common.