Patent ID: 11886292
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A memory system comprising:
a memory, configured to, during a read or write operation, write or read a plurality of data, wherein the plurality of data are divided into M bytes, each having N data; and
an encoding circuit, configured to generate, at an encoding stage, X first check codes, each based on a subset of the data at fixed bits among all the bytes, and to generate, at the encoding stage, Y second check codes based on all data in a subset of the bytes, wherein the X first check codes are configured for at least one of error detection or error correction on the N data in each of the bytes, and the Y second check codes are configured for at least one of error detection or error correction on the M bytes;
wherein each of M, N, X and Y is a positive natural number.