Patent ID: 11869574
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 1:
2. The semiconductor memory device of claim 1, further comprising:
a clock generation circuit configured to generate an output clock signal and a strobe signal based on the first, second, third, and fourth adjusted clock signals which are generated based on the first, second and third control code sets searched after the duty training interval; and
a data input/output (I/O) buffer configured to generate a data signal by sampling data from a memory cell array based on the output clock signal and configured to transmit the data signal and the strobe signal to the memory controller,
wherein the clock correction circuit is configured to store the second control code set and the third control code set that were searched in a register set therein and is configured to transmit the first control code set that was searched to the memory controller, and
wherein the memory controller is configured to update the first control code set based on the first control code set that was searched and is configured to store the first control code set that was updated in the mode register set.