Patent ID: 11875183
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 16:
17. A system on chip, comprising:
a plurality of real-time processing circuits;
an interconnect;
a computational resource connected to the interconnect;
a spinlock circuit connected to the interconnect and to the plurality of real-time processing circuits through a plurality of broadside connections such that each of plurality of real-time processing circuits is coupled to the interconnect via a first respective datapath that includes the spinlock circuit and a second respective datapath that does not include the spinlock circuit, wherein a total width of the plurality of broadside connections is at least 1000-bits wide, and wherein the spinlock circuit is configured to:
receive, via a first broadside connection of the plurality of broadside connections, a first instruction associated with a first processor of the plurality of real-time processing circuits that requests access to the computational resource;
receive, via a second broadside connection of the plurality of broadside connections, a second instruction associated with a second processor of the plurality of real-time processing circuits that requests access to the computational resource;
in response to the first instruction and the second instruction requesting access to the computational resource, perform arbitration of the computational resource between the first processor and the second processor to determine a winning processor;
set a flag in response to assigning the computational resource to the winning processor; and
reset the flag upon completion of an event associated with the computational resource; and

a broadside interface that includes the plurality of broadside connections and that is configured to store a last address associated with a most recent access of the computational resource;
wherein the broadside interface is configured to increment the last address to produce a subsequent address for a subsequent access of the computational resource.