Patent ID: 11961572
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. The controller as set forth in claim 9, wherein the rows include full circle rows and the semi-circle rows comprising memory holes forming the strings being partially cut by a shallow hole etch extending vertically into the stack, the particular ones of the rows are both the semi-circle rows and the full circle rows, the plurality of bits includes three bits, total state quantity of the plurality of data states is eight, the plurality of programmed data states includes, in order of the threshold voltage increasing in magnitude, a first data state and a second data state and a third data state and a fourth data state and a fifth data state and a sixth data state and a seventh data state, the highest data state is the seventh data state, and the controller is further configured to:
for the memory cells associated with the plurality of other data word lines and being programmed to any of the plurality of programmed data states during the program operation, instruct the memory apparatus to apply a plurality of program pulses to the plurality of other data word lines, the plurality of program pulses progressively increasing in magnitude in each of the plurality of loops by a first program step voltage;
for the memory cells associated with the at least one edge word line and being programmed to the third data state and the second data state and the first data state during the program operation, instruct the memory apparatus to apply a plurality of program pulses to the at least one edge word line, the plurality of program pulses progressively increasing in magnitude in each of the plurality of loops by the first program step voltage; and
for the memory cells associated with the at least one edge word line and being programmed to the seventh data state and the sixth data state and the fifth data state and the fourth data state during the program operation, instruct the memory apparatus to apply the plurality of program pulses to the at least one edge word line, the plurality of program pulses progressively increasing in magnitude in each of the plurality of loops by a second program step voltage less than the first program step voltage.