Patent ID: 11869612
Assignee: TECHNISCHE UNIVERSITEIT DELFT
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A method for testing an integrated circuit device, the method comprising:
defect modelling of the integrated circuit device,
fault modelling of the integrated circuit device based on the information obtained from the defect modelling,
test development based on information obtained from the fault modelling, and
executing the test on the integrated circuit device,
wherein the defect modelling of the integrated circuit device comprises
executing a physical defect analysis of the integrated circuit device to provide a set of effective technology parameters modified from a set of defect-free technology parameters associated with the integrated circuit device, and
executing an electrical modelling of the integrated circuit device using the set of effective technology parameters to provide a defect-parametrized electrical model based on a defect-free electrical model of the integrated circuit device;

wherein fault modelling comprises a fault analysis based on the defect-parametrized electrical model of the integrated circuit device; and
wherein the fault analysis comprises defining a fault space comprising a description of a plurality of possible faults, and determining which of the plurality of possible faults can be sensitized during executing the test on the integrated circuit device.