Patent ID: 11963351
Assignee: SK HYNIX INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor memory device, comprising:
a circuit structure including a semiconductor substrate;
a gate stacked structure over the circuit structure;
a channel layer passing through the gate stacked structure in a vertical direction;
a memory layer disposed between the channel layer and the gate stacked structure;
a dummy stacked structure over the semiconductor substrate and adjacent to the gate stacked structure;
a first dummy pattern passing through the dummy stacked structure in the vertical direction;
a gap arranged in the first dummy pattern; and
a second dummy pattern arranged farther away from the gate stacked structure than the first dummy pattern and extending in the vertical direction,
wherein the second dummy pattern extends along an outer sidewall of the dummy stacked structure and is closer to an edge of the semiconductor substrate than the dummy stacked structure.