Patent ID: 11954047
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 21:
22. The non-transitory machine readable medium of claim 17, further comprising:
when the address is within a first persistent range of memory indicated by at least one first persistent range register, removing a first persistent base address indicated by at least one persistent base address register from the address to generate a first offset into the persistent range, wherein the appending comprises appending the unique identifier value to the first offset to generate the modified address, and
when the address is within a second persistent range of memory indicated by at least one second persistent range register, removing a second, different persistent base address indicated by the at least one persistent base address register from the address to generate a second offset into the persistent range, wherein the appending comprises appending the unique identifier value to the second offset to generate the modified address.