Patent ID: 11973124
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A method of manufacturing a semiconductor device, comprising:
forming a source/drain epitaxial layer;
forming one or more dielectric layers over the source/drain epitaxial layer;
forming an opening in the one or more dielectric layers to expose the source/drain epitaxial layer;
forming a dielectric cover layer on the exposed source/drain epitaxial layer and a sidewall of the opening of the one or more dielectric layers;
selectively removing a part of the dielectric cover layer formed on the exposed source/drain epitaxial layer;
forming a first silicide layer on the exposed source/drain epitaxial layer;
forming a second silicide layer different from the first silicide layer on the first silicide layer; and
forming a source/drain contact over the second silicide layer.