Patent ID: 11955163
Assignee: ELITE SEMICONDUCTOR MICROELECTRONICS TECHNOLOGY INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 4:
5. A circuit for adaptive column-select line signal generation for a memory device, the circuit comprising:
an initiation signal generating circuit configured to generate a first signal in response to a memory access command;
a column-select line signal control circuit coupled to the initiation signal generating circuit and configured to generate a second signal according to a candidate signal selected from a plurality of candidate signals including a first candidate signal and a second candidate signal, wherein after the first signal is asserted, the first candidate signal is asserted when a configurable time interval with respect to a parameter from a register set elapses and the second candidate signal is asserted when a specified time interval elapses, and the selected candidate signal is asserted before a remaining part of the candidate signals after the first signal is asserted; and
a column-select line (CSL) signal output circuit coupled to the column-select line signal control circuit and configured to generate a column-select line signal according to the first signal and the second signal.