Patent ID: 11960758
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A storage system comprising:
a memory comprising a plurality of single-level cell (SLC) blocks and a multi-level cell (MLC) block; and
a controller coupled to the memory and configured to fold data stored in the plurality of SLC blocks into the MLC block using a multi-stage process;
wherein the controller is further configured to:
perform a first stage of the multi-stage process, wherein in the first stage, a first subset of the plurality of SLC blocks is folded into a first subset of pages of the MLC block; and
in response to successful completion of the first stage of the multi-stage process:
perform a second stage of the multi-stage process, wherein in the second stage, a second subset of the plurality of SLC blocks is folded into a second subset of pages of the MLC block, wherein the second stage is performed without reading data written in the first stage and writing it back in the second stage; and
release the first subset of the plurality of SLC blocks between the first and second stages.