Patent ID: 11915972
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 0:
1. A method comprising:
providing a first transistor structure; and
forming a backside interconnect structure on a backside of the first transistor structure, wherein forming the backside interconnect structure comprises:
forming a first dielectric layer on the backside of the first transistor structure;
removing an epitaxial material adjacent the first dielectric layer to form a first recess;
forming a first via in the first recess and electrically coupled to a first source/drain region of the first transistor structure;
forming a first conductive line on and electrically coupled to the first via;
forming a dielectric spacer adjacent the first conductive line; and
sealing an air spacer adjacent the first conductive line and the dielectric spacer, wherein the first conductive line defines a first boundary of the air spacer, and wherein the dielectric spacer defines a second boundary of the air spacer.