Patent ID: 11936384
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 7:
8. The multi-bit flip-flop of claim 1, wherein the first latch comprises a first NOR gate configured to receive the fourth data bit as a first input and a reset signal as a second input, and a first three-phase inverter configured to transfer an output of the first NOR gate to the first input of the first NOR gate in synchronization with the clock signal and the inverse clock signal, and
the third latch comprises a second NOR gate configured to receive the ninth data bit as a first input and the reset signal as a second input, and a second three-phase inverter configured to transfer an output of the second NOR gate to the first input of the second NOR gate in synchronization with the clock signal and the inverse clock signal.