Patent ID: 11889413
Assignee: NEW YORK UNIVERSITY
Field: Telecommunications (Electrical engineering)
Classification: CPC H  Y | IPC H

Claim 11:
12. An apparatus according to claim 10, wherein the detected start is the start of an nth subframe, and the processor is further configured to:
perform the determining of the first duration, and the determining of the second duration, and the switched architecture reception process in association with an instance of reception signals from the first antenna elements, or for from the second one or more of the antenna elements, or both, that carry a succession of subframes, each of the sub-frames including a respective one or more control slots, or one or more synchronization slots, or both,
perform, responsive to the detecting the start of the nth subframe, an instance of the determining of the first duration value and the second duration value, an instance of the switched architecture reception process with a timing configuration wherein:
the processor enables the first QRA receive CS, for the first duration, at a timing relative to a start of an (n+1)th subframe immediately succeeding the nth subframe that causes the first QRA receive CS to sample and output first QR samples of a temporal interval of the first signals that carries a control slot, or a synchronization slot, or both, of the (n+1)th subframe, and
the processor enables the second QRA receive CS, for the second duration, at a timing relative to the start of the (n+1)th subframe that causes the second the QRA receive CS to sample and output second QR samples of a temporal interval of the second signals that carriers data slots of the (n+1)th subframe, wherein n is an integer.