Patent ID: 11915772
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A data storage device comprising:
a memory comprising a plurality of memory cells; and
a controller coupled with the memory and configured to:
send a first command to the memory that specifies an initial read voltage threshold and a voltage shift;
send a second command to the memory a plurality of times, wherein the memory is configured to, each time in response to receiving the second command:
(a) read data from the plurality of memory cells using a read voltage threshold;
(b) send the data read from the plurality of memory cells to the controller; and
(c) increment the read voltage threshold by a multiple of the voltage shift;

wherein:
a first time the memory receives the second command, the plurality of memory cells are read using the initial read voltage threshold;
each subsequent time the memory receives the second command, the plurality of memory cells are read using the initial read voltage threshold incremented by a different multiple of the voltage shift; and
the memory incrementing the read voltage threshold in response to receiving the second commands avoids a latency that would be incurred by the controller specifying an incremented read voltage threshold.