Patent ID: 11923250
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A method, comprising:
forming a first fin structure comprising:
a p-doped region on a substrate,
a first semiconductor region on the p-doped region, and
a second semiconductor region on the first semiconductor region;

forming a second fin structure comprising:
an n-doped region on a substrate,
a third semiconductor region on the n-doped region, and
a fourth semiconductor region on the third semiconductor region;

forming a dielectric layer on the first and second fin structures;
etching the dielectric layer to expose sidewalls of the second semiconductor layer of the first fin structure and sidewalls of the fourth semiconductor layer of the second fin structure; and
forming a gate structure on the first and second fin structures.