Patent ID: 11907127
Assignee: SMART IOPS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. The method of claim 14, wherein the first non-volatile memory further comprises the second partition of the second non-volatile memory configured as the main memory, and wherein the first controller performs:
the writing of the first data to the at least one first partition of the first non-volatile memory configured as the first cache memory;
the erasing of the first data from the second partition of the second non-volatile memory configured as the main memory or the otherwise considering of the first data as erased and available to be rewritten with new data;
the writing of the processed first data to the second partition of the second non-volatile memory configured as the main memory; and
the erasing of the processed first data from the at least one first partition of the first non-volatile memory configured as the first cache memory or the otherwise considering of the processed first data as erased and available to be rewritten with new data.