Patent ID: 11947379
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 9:
10. The host interface of claim 8, wherein the control logic is further configured to generate an internal clock signal, and
the phase shift detector includes:
a first multiplexer that selects one of the response and the feedback clock signal as the selected value;
a positive edge detector that detects the selected value transitioning from high to low based on a positive edge of the internal clock signal to generates a positive edge detection signal;
a negative edge detector that detects the selected value transitioning from high to low based on a negative edge of the internal clock signal to generate a negative edge detection signal;
a positive edge counter that provides a positive edge count value based on the positive edge of the internal clock signal in response to the positive edge detection signal; and
a negative edge counter that provides a negative count value based on the negative edge of the internal clock signal in response to the negative edge detection signal.