Patent ID: 11942376
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A method for manufacturing a semiconductor structure, comprising:
receiving a substrate having a first source/drain (S/D) region and a first gate structure of a first transistor, and a second S/D region and a second gate structure of a second transistor formed thereon, wherein the first transistor and the second transistor have different conductive types;
reducing a thickness of a first spacer on a vertical surface of the first gate structure and a thickness of a second spacer on a vertical surface of the second gate structure;
disposing a liner layer over the substrate covering the first spacer and the second spacer, the first S/D region and the second S/D region;
exposing the first S/D region and the second S/D region;
increasing amorphous densities of the first S/D region and the second S/D region, thereby providing a first amorphous density of a surficial portion of the first S/D region and a second amorphous density of a surficial portion of the second S/D region;
introducing a substance into an amorphous structure of the first S/D region, wherein an amorphous density of the surficial portion of the first S/D region is increased from the first amorphous density to a third amorphous density;
depositing a contact material layer on the first S/D region and the second S/D region, wherein amorphous densities of the surficial portion of the first S/D region and the surficial portion of the second S/D region remain unchanged prior to the deposition of the contact material, and the contact material is in direct contact with the surficial portion of the first S/D region having the third amorphous density and the surficial portion of the second S/D region having the second amorphous density; and
performing a laser anneal to decrease the amorphous densities of the first S/D region and the second S/D region.