Patent ID: 11887985
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 7:
8. A method comprising:
forming a gate stack on sidewalls and a top surface of a semiconductor fin; and
forming source/drain regions on opposite sides of the gate stack, wherein forming each of the source/drain regions comprises:
performing a first etching process to etch the semiconductor fin in a vertical direction and form a first source/drain recess;
performing a second etching process to etch the semiconductor fin in a vertical direction and a horizontal direction to extend the first source/drain recess, wherein the second etching process continues until etchants of the second etching process are exposed to surfaces of the semiconductor fin that are in the (110) family of crystallographic planes; and

epitaxially growing a semiconductor material in the first source/drain recess, wherein the semiconductor material is in physical contact with the surfaces of the semiconductor fin that are in the (110) family of crystallographic planes.