Patent ID: 11895816
Assignee: ARM LIMITED
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 17:
18. A method comprising:
fabricating multiple devices that are arranged as a bitcell;
fabricating the multiple devices with a pair of P-type transistors that are sequentially arranged in a P-over-P stack configuration;
fabricating the multiple devices with a pair of N-type transistors that are sequentially arranged in an N-over-N stack configuration; and
cross-coupling the pair of P-type transistors with the pair of N-type transistors so as to provide two cross-coupled inverters that are used as a latch for the bitcell,
wherein the pair of P-type transistors in the P-over-P stack configuration is disposed alongside the pair of N-type transistors in the N-over-N stack configuration.