Patent ID: 11875844
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. The SRAM device of claim 17, wherein the control logic further includes a level shifter configured to generate a second internal clock by adjusting a level of the first internal clock, and
wherein the second tracking circuit includes:
a fourth wire including a third capacitor corresponding to the length of the memory cells in the column direction;
a fifth wire including a third resistor corresponding to the length of the memory cells in the column direction;
a driver connected with the third wire, and configured to receive the second internal clock and to output a third signal based on the second capacitor and the second resistor;
a first inverter connected with the fourth wire and the fifth wire, and configured to output a fourth signal based on the third signal, the third capacitor, and the third resistor; and
a second inverter configured to output the second signal in response to the fourth signal.