Patent ID: 11880327
Assignee: AMAZON TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A multi-chip system comprising:
a first system-on-a-chip (SoC) comprising:
a first processor;
a first system memory;
a first coherent interconnect coupled to the first processor and to the first system memory;
a first non-coherent interconnect coupled to the first coherent interconnect; and
a first input/output (I/O) device coupled to the first non-coherent interconnect; and

a second SoC comprising:
a second processor;
a second system memory;
a second coherent interconnect coupled to the second processor and to the second system memory;
a second non-coherent interconnect coupled to the second coherent interconnect; and
a second input/output (I/O) device coupled to the second non-coherent interconnect,

wherein the first coherent interconnect is coupled to the second coherent interconnect via a coherent connection between the first SoC and the second SoC, wherein the coherent connection is configured to maintain coherency between the first processor and the second processor,
wherein the first non-coherent interconnect is coupled to the second non-coherent interconnect via a non-coherent connection between the first SoC and the second SoC,
wherein the non-coherent connection is used for I/O transactions between the first SoC and the second SoC that do not require coherency, and
wherein the coherent connection is used for processor transactions between the first SoC and the second SoC that maintain processor cache coherency.