Patent ID: 11876025
Assignee: NANYA TECHNOLOGY CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. A semiconductor structure, comprising:
a wafer, comprising a first scribe line and a second scribe line orthogonal to the first scribe line; and
a test structure, disposed in the first scribe line of the wafer and comprising:
a first device, comprising a first gate layer along a first direction, wherein the first gate layer has two free ends, and has a uniform width between the two free ends thereof; and
a second device, comprising a second gate layer along a second direction orthogonal to the first direction, wherein the second gate layer has a connecting end and an opposed free end, wherein the second gate layer has a uniform width between the connecting end and the free end;
a third device, disposed adjacent to the first device, wherein the first gate layer is disposed in the third device at a position that the third device is disposed between the two free ends of the first gate layer, the first device, the second device, and the third device are spaced apart from each other and are independent from each other;
wherein the connecting end of the second gate layer is integrally connected to a mid-portion of the first gate layer between the two free ends thereof to form a T-shaped configuration, wherein a length of the first gate layer is larger than a length of the second gate layer.