Patent ID: 11929123
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 3:
4. The semiconductor memory device according to claim 1, wherein
the semiconductor memory device is configured to be able to execute a third erase loop in addition to the first erase loop and the second erase loop, and
when one of the plurality of first conductive layers is assumed to be a third conductive layer, and
when another one of the plurality of first conductive layers is assumed to be a fourth conductive layer,
in the second erase loop, the semiconductor memory device applies the first voltage to the third conductive layer and applies a third voltage larger than the first voltage to the fourth conductive layer, and
in the third erase loop, the semiconductor memory device applies the third voltage to the third conductive layer and applies the first voltage to the fourth conductive layer.