Patent ID: 11935609
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 7:
8. The data storage device of claim 1, wherein, when executing the linked XOR flash data protection scheme, the data storage controller is further configured to:
generate a plurality of linked XOR parity buffers including a plurality of full XOR parity buffers including the first full XOR parity buffer and a plurality of reduced XOR parity buffers including the first reduced XOR parity buffer,
control a memory to store the plurality of linked XOR parity buffers,
determine whether a defect in flash data of the memory is limited to a scope of a single XOR zone bin with respect to one of the plurality of reduced XOR parity buffers, and
responsive to determining that the defect is limited to the scope of the single XOR zone bin, subtracting a re-accumulation of full XOR parity buffers in one or more uncorrupted planes and reduced XOR parity buffers in a corrupted plane from the one of the plurality of reduced XOR parity buffers, and
correct the defect with the subtraction of the re-accumulation of the full XOR parity buffers in the one or more uncorrupted planes and the reduced XOR parity buffers in the corrupted plane from the one of the plurality of reduced XOR parity buffers.