Patent ID: 11903191
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A method comprising:
etching a recess into a semiconductor substrate;
blanket depositing a bottom dielectric layer in the recess and over a non-recessed portion of the semiconductor substrate;
forming a charge storage layer over the bottom dielectric layer, wherein a first portion of the charge storage layer is in the recess and a second portion of the charge storage layer is over the non-recessed portion of the semiconductor substrate;
planarizing the bottom dielectric layer and the charge storage layer, after planarizing the charge storage layer being level with and directly interposing two sidewall portions of the bottom dielectric layer;
forming a top dielectric layer over and physically contacting the charge storage layer;
forming a silicon oxide layer over and physically contacting the non-recessed portion of the semiconductor substrate;
forming a first dielectric layer over and physically contacting the top dielectric layer and the silicon oxide layer; and
patterning to form a first stack and a second stack, the patterning removing a first horizontal portion of the bottom dielectric layer, the first stack comprising first portions of the bottom dielectric layer, the charge storage layer, and the first dielectric layer, the second stack comprising second portions of the silicon oxide layer and the first dielectric layer.