Patent ID: 11968040
Assignee: NVIDIA CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 24:
25. The computer readable media of claim 22, wherein decoding the received linear block code comprises:
receiving or generating input comprising:
either: a plurality of log likelihood ratios (LLRs) corresponding to channel observations regarding one or more bit values of the linear block code; or
a plurality of probability vectors corresponding to channel observations regarding one or more symbol values of the linear block code; and

one or more trainable parameters;

initializing graph nodes of the GNN-based decoder, wherein initializing the graph nodes comprises assigning a plurality of initial variable node values to a plurality of variable nodes based at least in part on the plurality of LLRs or the plurality of probability vectors;
iteratively decoding the received linear block code;
computing one or more final variable node values based on the iterative decoding process;
projecting the computed final variable node value(s) to either final, scalar LLRs or final probability vectors; and
determining the one or more bit values or symbol values of the linear block code based on either the final, scalar LLRs or the final probability vectors.