Patent ID: 11972716
Assignee: XIAMEN TIANMA MICRO-ELECTRONICS CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. The display panel of claim 13, wherein
the first control unit comprises:
a fourth transistor, a source of the fourth transistor receives the input signal, a drain of the fourth transistor is connected to the first node, and a gate of the fourth transistor receives the first clock signal;
the second control unit comprises:
a fifth transistor, a source of the fifth transistor receives the first clock signal, a drain of the fifth transistor is connected to a fourth node, and a gate of the fifth transistor is connected to the first node;
a sixth transistor, a source of the sixth transistor receives the second clock signal, a drain of the sixth transistor is connected to a fifth node, and a gate of the sixth transistor is connected to the fourth node;
a seventh transistor, a source of the seventh transistor receives the first voltage signal, a drain of the seventh transistor is connected to the fourth node, and a gate of the seventh transistor receives the first clock signal;
an eighth transistor, a source of the eighth transistor receives the second voltage signal, a drain of the eighth transistor is connected to the second node, and a gate of the eighth transistor is connected to the first node;
a ninth transistor, a source of the ninth transistor is connected to the fifth node, a drain of the ninth transistor is connected to the second node, and a gate of the ninth transistor receives the second clock signal;
a third capacitor, a first plate of the third capacitor is connected to the fourth node, and a second plate of the third capacitor is connected to the fifth node;
a fourth capacitor, a first plate of the fourth capacitor receives the second voltage signal, and a second plate of the fourth capacitor is connected to the second node;
the third control unit comprises:
a tenth transistor, a source of the tenth transistor receives the first voltage signal, a drain of the tenth transistor outputs an output signal, and a gate of the tenth transistor is connected to the third node;
an eleventh transistor, a source of the eleventh transistor receives the second voltage signal, a drain of the eleventh transistor outputs an output signal, and a gate of the eleventh transistor is connected to the second node.