Patent ID: 11934887
Assignee: ZHEJIANG LAB
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. A distributed model compilation system, comprising a master node and a plurality of slave nodes, wherein
the master node is configured to:
according to model information of a to-be-compiled model, determine a logic calculation graph of the to-be-compiled model;
divide the logic calculation graph into a plurality of logic calculation sub-graphs;
for each of the plurality of the logic calculation sub-graphs, generate a distributing message, and transmit the distributing message to one of the plurality of the slave nodes;
in response to receiving compilation completion information returned from the plurality of the slave nodes, determine completion of a compilation of the to-be-compiled model; and
according to a compiled model, execute a target work; and

each of the plurality of the slave nodes is configured to:
receive the distributing message transmitted by the master node;
according to the distributing message, allocate a local computing resource of the slave node, to compile the logic calculation sub-graph contained in the distributing message based on the local computing resource to determine a task calculation sub-graph; and
according to the task calculation sub-graph, transmit compilation completion information to the master node;

wherein the master node is further configured to:
according to a received compilation request, create an event executor that executes an event for the compilation request, and determine the model information of the to-be-compiled model, and for each of the plurality of the slave nodes, generate the distributing message, and transmit the distributing message to the slave node;
by the event executor, in response to receiving the compilation completion information returned from the plurality of the slave nodes, determine the compiled model, and execute the target work according to the compiled model;
by the event executor, determine statuses of the plurality of the slave nodes;
according to the statuses of the plurality of the slave nodes, divide the logic calculation graph into the plurality of the logic calculation sub-graphs;
after determining the statuses of the plurality of the slave nodes, create a session control executor by the event executor;
by the session control executor, according to the statuses of the plurality of the slave nodes, divide the logic calculation graph into the plurality of the logic calculation sub-graphs; and
determine a logic calculation sub-graph for each of the plurality of the slave nodes.