Patent ID: 11901428
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 9:
10. The method of claim 9, wherein the receiving of the workpiece includes receiving the workpiece having:
sacrificial layers interposing between vertically adjacent layers of the first plurality of semiconductor layers and between vertically adjacent layers of the second plurality of semiconductor layers,
a fourth dielectric feature on the first dielectric feature;
the method further including:
forming a sacrificial gate structure covering the first plurality of the semiconductor layers and the second plurality of the semiconductor layers and a portion of the fourth dielectric feature;
forming source/drain features on both sides of the sacrificial gate structure;
recessing the sacrificial gate structure to expose a top and side surfaces of the fourth dielectric feature;
recessing an exposed portion of the fourth dielectric feature to expose a top surface of the first dielectric feature;
removing the sacrificial layers to form gaps between adjacent layers of the first plurality of semiconductor layers and between adjacent layers of the second plurality of semiconductor layers; and
forming the gate structure in the gaps.