Patent ID: 11948638
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus, comprising:
a plurality of pillars extending vertically through a plurality of tiers of memory cells, each pillar of the plurality of pillars coupled with two memory cells at each tier of the plurality of tiers;
a plurality of bit lines;
a plurality of sets of pillar selectors, each set of pillar selectors associated with a respective conductive line configured to control activation of the set of pillar selectors, wherein a set of pillar selectors is configured to couple a subset of pillars of the plurality of pillars with the plurality of bit lines based at least in part on being activated;
a plurality of sets of word lines, each tier of memory cells coupled with two sets of word lines of the plurality of sets of word lines; and
a controller coupled with the plurality of bit lines, the plurality of sets of pillar selectors, and the plurality of sets of word lines and operable to cause the apparatus to:
apply, during a first duration, a first voltage to a first set of word lines of the plurality of sets of word lines coupled with a first tier of memory cells of the plurality of tiers of memory cells, wherein, during the first duration, at least one memory cell of a first subset of the first tier of memory cells thresholds based at least in part on applying the first voltage to the first set of word lines;
apply, during a second duration after the first duration, a second voltage to the first set of word lines, wherein, during the second duration, at least one memory cell of a second subset of the first tier of memory cells thresholds and the at least one memory cell of the first subset of the first tier of memory cells is written to a first logic state based at least in part on applying the second voltage to the first set of word lines; and
apply, during a third duration after the second duration, a third voltage to the first set of word lines, wherein, during the third duration, the at least one memory cell of the second subset of the first tier of memory cells is written to a second logic state based at least in part on applying the third voltage to the first set of word lines.