Patent ID: 11971821
Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. The computing system as claimed in claim 12, wherein:
the first in-core cache module includes a level 1 cache and a level 2 cache;
the first last-level cache is a level 3 cache;
the write-back and invalidation request is transferred from the level 1 cache to the level 2 cache, and then passed to the level 3 cache by the level 2 cache;
the level 3 cache provides the first synchronization signal to the level 2 cache;
in response to the first synchronization signal, the level 2 cache in the waiting state is awakened to search itself to determine which cache lines within the level 2 cache match the designated key identification code, wherein: if a matched cache line has been modified and does not exist in the level 1 cache, the level 2 cache writes back the matched cache line to the system memory; and, whether modified or not, all matched cache lines within the level 2 cache are invalidated;
after all matched cache lines within the level 2 cache are invalidated, the level 2 cache returns a second synchronization signal to the level 1 cache; and
in response to the second synchronization signal, the level 1 cache in the waiting state is awakened to search itself to determine which cache lines within the level 1 cache match the designated key identification code, wherein: if a matched cache line has been modified, the level 1 cache writes back the matched cache line to the system memory; and, whether modified or not, all matched cache lines within the level 1 cache are invalidated.