Patent ID: 11934263
Assignee: AMPERE COMPUTING LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. The method of claim 16, wherein:
the first block comprises a first plurality of rows comprising:
a first number (N) of rows of bits of the first data portion;
a first row comprising the metadata bits; and
a first row comprising the parity bits; and

the second block comprises a second plurality of rows comprising:
a second N rows of bits of the second data portion;
a first row of ECC bits comprising the first ECC symbol; and
a second row of ECC bits comprising the second ECC symbol; and

demerging the merged second block based on the first block comprises:
for each of the first N rows of bits of the first block, XORing the row of bits of the first block with a corresponding row of the second N rows of bits of the merged second block to generate a row of bits of the restored second block;
XORing the first row of ECC bits with the first row of the first block comprising the metadata bits to generate a row comprising a restored first ECC symbol; and
XORing the second row of ECC bits with the second row of the first block comprising the parity bits to generate a row comprising a restored second ECC symbol.