Patent ID: 11900039
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 14:
15. A circuit comprising:
a first stage having first logic devices arranged for activation with a first input signal and a second input signal, wherein the first stage provides a first output signal based on the first input signal and the second input signal; and
a second stage having second logic devices arranged for activation with a third input signal and the first output signal, wherein the second stage provides a second output signal based on the third input signal and the first output signal, wherein the second output signal refers to an XOR output signal,
wherein the first stage and the second stage are coupled together to operate as a multi-input XOR gate that provides the XOR output signal as a single XOR output signal based on the first input signal, the second input signal and the third input signal.