Patent ID: 11895826
Assignee: NANYA TECHNOLOGY CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for preparing a semiconductor device structure, comprising:
forming a first fin structure and a second fin structure over a semiconductor substrate;
forming an isolation structure over the semiconductor substrate, wherein the first fin structure and the second fin structure protrude from the isolation structure;
partially removing the first fin structure and the second fin structure to form a recessed portion of the first fin structure and a recessed portion of the second fin structure;
epitaxially growing a first source/drain (S/D) structure over the recessed portion of the first fin structure and a second S/D structure over the recessed portion of the second fin structure, wherein the first S/D structure is separated from the second S/D structure by a first opening;
partially removing the isolation structure through the first opening to form a second opening; and
forming a contact etch stop layer (CESL) over the first S/D structure and the second S/D structure such that an air gap is formed and sealed in the first opening and the second opening.