Patent ID: 11955935
Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 5:
6. A method for adjusting parameters for a signal processing device which includes:
a subtractor that subtracts a feedback signal from an input signal that is a digital audio signal and outputs a first digital signal;
a signal processing circuit that performs signal processing on the first digital signal and outputs a second digital signal;
a power amplifier circuit that amplifies the second digital signal, converts the second digital signal amplified into an analog signal, and outputs the analog signal;
an A/D converter that converts the analog signal into a third digital signal and outputs the third digital signal;
an offset adjuster that adjusts a DC offset for the third digital signal;
an amplitude adjuster that adjusts an amplitude for the third digital signal;
a delay adjuster that adjusts a delay of the second digital signal; and
a calculator that extracts a difference signal which is a difference between the third digital signal having the DC offset adjusted by the offset adjuster and the amplitude adjusted by the amplitude adjuster and the second digital signal having the delay adjusted by the delay adjuster, and outputs the feedback signal based on the difference signal,
the method comprising:
determining a first parameter regarding the DC offset determined based on an output of the offset adjuster which is output when no signal is input to the signal processing circuit by the subtractor;
determining a second parameter regarding the amplitude based on (i) an output of the amplitude adjuster which is output when the input signal and the feedback signal are not input to the subtractor and a first test signal is input to the signal processing circuit and (ii) the first test signal; and
determining a third parameter regarding the delay based on the difference signal when the input signal and the feedback signal are not input to the subtractor and a second test signal is input to the signal processing circuit.