Patent ID: 11915769
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. A non-volatile memory device, comprising:
a plurality of non-volatile memory cells arranged in columns of non-volatile memory cells connected to bit lines; and
a control circuit configured to connect to a bit line for program-verify of non-volatile memory cells connected to the bit line, the control circuit comprising:
a first plurality of data latches connected to a first local data bus, the first plurality of data latches configured to store first program-verify pass/fail bits for first non-volatile memory cells connected to the bit line;
a second plurality of data latches connected to a second local data bus, the second plurality of data latches configured to store second program-verify pass/fail bits for second non-volatile memory cells connected to the bit line;
means for counting non-volatile memory cells that fail program-verify;
a shared isolation latch; and
means for selectively blocking any first and second program-verify pass/fail bits from the first and second pluralities of latches that indicate program-verify failure whenever an indictor bit is set in the shared isolation latch so that they are not counted by the means for counting non-volatile memory cells that fail program-verify.