Patent ID: 11869801
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor manufacturing method, comprising:
providing a substrate having a plurality of first trenches, wherein a first pattern is formed between two adjacent first trenches;
depositing a first dielectric layer onto the substrate, the first dielectric layer covering at least one side wall of the first pattern;
depositing a second dielectric layer onto the substrate, the second dielectric layer filling the first trenches;
severing the first pattern to form a second pattern on the substrate, wherein severing the first pattern to form the second pattern comprises etching a plurality of second trenches on the first pattern to cut each of the first pattern into the second pattern; and
removing the second dielectric layer from the first trenches.