Patent ID: 11971831
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. A non-transitory computer-readable medium to store computer-readable code for fabrication of an apparatus comprising:
first-in, first-out (FIFO) buffer circuitry to transfer data from a source domain to a sink domain across a clock domain boundary, the FIFO buffer circuitry comprising:
data transfer circuitry comprising one or more data storage elements to store the data to be transferred across the clock domain boundary;
source domain data transfer control circuitry to maintain a source state vector indicative of a state of the FIFO buffer circuitry in the source domain and sink domain data transfer control circuitry to maintain a sink state vector indicative of a state of the FIFO buffer circuitry in the sink domain;
synchronisation circuitry in each of the source domain and the sink domain to stabilise a signal indicative of a received state vector received from the other of the source domain and the sink domain and to store the received state vector;
wherein for at least one of the source domain and the sink domain:
the respective synchronisation circuitry is clock-gated by an enable signal; and
the respective synchronisation circuitry is responsive to a change in the state of the FIFO buffer circuitry in the respective domain to advance the respective state vector by controlling the enable signal to enable output of one or more elements of the received state vector.