Patent ID: 11888042
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A semiconductor memory device comprising:
a stacked structure comprising a plurality of electrodes and insulating patterns that are stacked alternately and repeatedly on a substrate;
a semiconductor pattern penetrating the stacked structure; and
a tunneling layer, a charge storage layer, a capping layer and a blocking insulation layer between the semiconductor pattern and the electrodes,
wherein each of the insulating patterns has a first sidewall adjacent the semiconductor pattern and a second sidewall opposite the first sidewall,
wherein the tunneling layer, the charge storage layer, and the capping layer extend along the first sidewalls of the respective insulating patterns,
wherein the capping layer comprises a silicon oxide layer,
wherein the blocking insulation layer comprises a high-k dielectric layer, and
wherein the blocking insulation layer includes a first portion extending along the second sidewalls of the insulating patterns.