Patent ID: 11967529
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A semiconductor chip comprising:
an integrated circuit region and a cut region;
a plurality of multilayer metal patterns in the cut region;
an upper metal layer on the plurality of multilayer metal patterns; and
a vertical via connecting a first one of the plurality of multilayer metal patterns at a first distance from the upper metal layer to a second one of the plurality of multilayer metal patterns at a second distance from the upper metal layer,
wherein a number of the plurality of multilayer metal patterns per unit area increases as a distance from the upper metal layer increases,
a cross section is formed at a central portion of at least one of the plurality of multilayer metal patterns, and
an upper surface of the first one of the plurality of multilayer metal patterns contacts the vertical via and is spaced apart from upper surfaces of remaining ones of the plurality of multilayer metal patterns at the first distance from the upper metal layer.