Patent ID: 11923247
Assignee: SK HYNIX INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 17:
18. A method of manufacturing a semiconductor chip, the method comprising:
forming a first layer stack by alternately stacking first material layers and second material layers over a semiconductor substrate, the semiconductor substrate including a chip region and a scribe lane region;
forming first trenches that overlap with the scribe lane region and second trenches that overlap with the chip region, the first and second trenches that substantially penetrate the first layer stack;
forming first crack propagation guides that fill the first trenches and insulating patterns that fill the second trenches;
forming a second layer stack by alternately stacking third material layers and fourth material layers on the first layer stack;
forming first openings that overlap with the scribe lane region and second openings that overlap with the chip region together, the first and second openings substantially penetrating the second layer stack; and
forming second crack propagation guides that fill the first openings and supporters filling the second openings.