Patent ID: 11942478
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. A method, comprising:
forming first, second and third fins;
depositing a first dielectric layer between the first and second fins;
depositing a second dielectric layer on the first dielectric layer between the first and second fins;
depositing a third dielectric layer between the second and third fins;
deposing a fourth dielectric layer on the third dielectric layer between the second and third fins;
forming a sacrificial gate stack on a first portion of each of the first fin, the second fin, the third fin, the first dielectric layer, the second dielectric layer, the third dielectric layer, and the fourth dielectric layer, wherein a second portion of each of the first fin, the second fin, the third fin, the first dielectric layer, the second dielectric layer, the third dielectric layer, and the fourth dielectric layer are exposed;
removing the sacrificial gate stack by a first process; and then
removing portions of the first portion of the third dielectric layer by a second process, wherein the first portion of the fourth dielectric layer is disposed on a portion of the first portion of the third dielectric layer.