Patent ID: 11886910
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. An apparatus comprising:
first circuitry to use a first weight value to weight operating system (OS) priority information to generate a first weighted priority value;
second circuitry to use a second weight value to weight system-on-chip (SoC) hardware priority information to generate a second weighted priority value;
third circuitry to use a third weight value to weight platform priority information to generate a third weighted priority value;
fourth circuitry to sum the first weighted priority value, the second weighted priority value, and the third weighted priority value to generate a quality of service (QoS) value for an SoC interconnect transaction; and
an arbiter to use the QoS value to prioritize the SoC interconnect transaction on an SoC interconnect;
wherein the prioritized SoC interconnect transaction is executed on the SoC.