Patent ID: 11914893
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. The apparatus of claim 14, wherein:
the one or more command routers are further configured to determine the third and fourth subsets of the memory access commands and store the third and fourth subsets in the fifth and sixth queues, respectively; and
the processor is further configured to process the third subset of the memory access commands from the fifth queue to the third queue according to a third process and the fourth subset of the memory access commands from the sixth queue to the fourth queue according to a fourth process, wherein the third and fourth processes are configured to be run concurrently with the first and second processes by the execution unit according to the quantity of the memory access commands in the command queue for the prioritization between the first priority and the second priority.