Patent ID: 11869988
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 5:
6. A method of forming an integrated circuit (IC), comprising:
forming a first series of trenches on a first side of a substrate;
forming a first insulating material in the first series of trenches, the first insulating material lining inner sidewalls and a bottom surface of the first series of trenches;
forming a first conductive material in the first series of trenches over the first insulating material, the first conductive material lining inner sidewalls and a bottom surface of the first insulating material within the first series of trenches;
after the first conductive material has been formed, bonding the first side of the substrate to a first metal interconnect structure disposed on a carrier wafer;
after the bonding, thinning a second side of the substrate opposite the first side; and
etching a second series of trenches into the second side of the substrate;
etching a trench into the substrate;
forming a dielectric layer within the trench;
extending the trench to remove a portion of the dielectric layer and expose a top surface of the first metal interconnect structure; and
forming a through-substrate via (TSV) within the trench to contact the top surface of the first metal interconnect structure.