Patent ID: 11886930
Assignee: SAMBANOVA SYSTEMS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A data processing system, comprising:
a plurality of reconfigurable processors including a first reconfigurable processor operatively coupled to a first processing node and additional reconfigurable processors operatively coupled to a second processing node;
wherein the first reconfigurable processor and the additional reconfigurable processors are operatively coupled to different processing nodes;

a plurality of buffers, buffers in the plurality of buffers including first reconfigurable processor-to-additional reconfigurable processors buffers configured to receive data from the first reconfigurable processor and provide the data to the additional reconfigurable processors, and additional reconfigurable processors-to-first reconfigurable processor buffers configured to receive data from the additional reconfigurable processors and provide the data to the first reconfigurable processor;
runtime logic configured to load one or more configuration files for applications on the first reconfigurable processor for execution, the configuration files including a plurality of functions; and
the runtime logic configured to execute a first set of functions in the plurality of functions and data therefor on the first reconfigurable processor, and a second set of functions in the plurality of functions and data therefor on the additional reconfigurable processors,
wherein functions in the second set of functions and the data therefor are transmitted to the additional reconfigurable processors using one or more of the first reconfigurable processor-to-additional reconfigurable processors buffers,
wherein results of executing the functions and the data therefor on the additional reconfigurable processors are transmitted to the first reconfigurable processor using one or more of the additional reconfigurable processors-to-first reconfigurable processor buffers, and
wherein the first reconfigurable processor-to-additional reconfigurable processors buffers operate in a memory of a first smart Network Interface Controller (SmartNIC) operatively coupled to the first processing node, and the additional reconfigurable processors-to-first reconfigurable processor buffers operate in a memory of a second SmartNIC operatively coupled to the second processing node.