Patent ID: 11960717
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 11:
12. A system, comprising:
a memory device comprising memory cells configured to store data;
a power management integrated circuit (PMIC) configured to perform power control functions for the system and configured to selectively transition between a deactivated state and an activated state;
a first loopback pin of the memory device and the PMIC, the memory device configured to cause the PMIC to transition from the deactivated state to the activated state by sending a first signal via the first loopback pin outside a testing phase of operation;
a first conductive path coupled with the first loopback pin and configured to induce, via inductive coupling with a second conductive path coupled with the PMIC, a second signal on the second conductive path for transitioning the PMIC to the activated state;
a second loopback pin of the memory device; and
a transistor coupled with the second loopback pin and positioned between a first portion of the first conductive path and a second portion of the first conductive path and configured to selectively couple the memory device with the PMIC, wherein the memory device is configured to send, via the second loopback pin, a third signal outside the testing phase of operation to activate the transistor, wherein the third signal activates the transistor outside the testing phase of operation, and wherein the first loopback pin and the second loopback pin are each configured to communicate feedback data during the testing phase of operation.