Patent ID: 11967356
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 15:
16. A method comprising:
receiving a prime row address associated with an access operation at a first plurality of fuse latch comparator circuits, a second plurality of fuse latch comparator circuits, a first predecoder, and a second predecoder, wherein each of the first plurality of fuse latch and comparator circuits is associated with a particular row section of a first plurality of row sections and each of the second plurality of fuse latch and comparator circuits is associated with a particular row section of a second plurality of row sections;
providing, via a first fuse latch comparator circuit of the first plurality of fuse latch comparator circuits, a first match signal in response to a determination that the prime row address matches a respective defective row address stored at a first fuse latch circuit of a first plurality of fuse latch circuits coupled to the first fuse latch comparator circuit;
providing, via a second fuse latch comparator circuit of the second plurality of fuse latch comparator circuits, a second match signal in response to a determination that the prime row address matches a respective defective row address stored at a second fuse latch circuit of a second plurality of fuse latch circuits coupled to the first fuse latch comparator circuit; and
concurrently:
in response to the first match signal, causing, via the first predecoder, a first threshold voltage compensation to be initiated on a first redundant row associated with the first fuse latch comparator circuit;
in response to a determination that the prime row address targets a first prime row of the first plurality of row sections, causing, via the first predecoder, a second threshold voltage compensation operation to be initiated on the first prime row; and
in response to the second match signal, causing, via the second predecoder, a third threshold voltage compensation to be initiated on a second redundant row associated with the second fuse latch comparator circuit; and
in response to a determination that the prime row address targets a second prime row of the second plurality of row sections, causing, via the second predecoder, a fourth threshold voltage compensation operation to be initiated on the second prime row.