Patent ID: 11925013
Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 5:
6. The memory device using a pillar-shaped semiconductor element, according to claim 1, wherein
the voltages to be applied to the first gate conductor layers, the second gate conductor layers, the third gate conductor layers, the fourth gate conductor layers, the first impurity region, and the second impurity region regions are controlled to perform the data write operation for holding a group of positive holes generated by an impact ionization phenomenon or a gate-induced drain leakage current in any or all of the first to fourth semiconductor pillars, and
the voltages to be applied to the first gate conductor layers, the second gate conductor layers, the third gate conductor layers, the fourth gate conductor layers, the first impurity region, and the second impurity region regions are controlled to perform the data erase operation for discharging the group of positive holes from inside of any or all of the first to fourth semiconductor pillars.