Patent ID: 11961128
Assignee: WILLIAM FOSTER
Field: IT methods for management (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. A computer-implemented method comprising:
receiving, by one or more processors of a computing system, a start time and an authorization time for each of a plurality of event components relating to an event;
determining, by the one or more processors, an authorization status of each event component across a predetermined period of time, the authorization status being based on the start time and the authorization time of each of the plurality of event components, wherein the authorization status of each event component is either authorized or not authorized;
determining, by the one or more processors, a validation status of the event across the predetermined period of time by:
performing a logical operation among authorization statuses of every event component across the predetermined period of time; and
(i) identifying the event is valid responsive to determining, based on the logical operation, that every event component is authorized across the predetermined period of time or (ii) identifying the event is invalid responsive to determining, based on the logical operation, that at least one event component is not authorized across the predetermined period of time;

generating, by the one or more processors, a visual representation of the authorization status of each event component and the validation status of the event, the visual representation comprising a bar graph having a respective bar for each of the plurality of event components, wherein portions of the respective bar for each event component have a visual characteristic that varies with the authorization status for said event component;
generating, by the one or more processors, for the visual representation, a graphical icon for each event component corresponding to when the event is valid, wherein the graphical icon is omitted from the visual representation when the event is invalid; and
displaying, by the one or more processors, the visual representation on an electronic display device, wherein the visual representation comprises an indication of one or more steps to validate the event when the event is invalid.