Patent ID: 11961840
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 18:
19. A method for forming a semiconductor device structure, comprising:
forming a plurality of first semiconductor layers vertically stacked;
forming a first source/drain feature and a second source/drain feature disposed at a level higher than the first source/drain feature, wherein the first source/drain feature and the second source/drain feature are in contact with the plurality of first semiconductor layers;
forming a first dipole layer to surround a first group of the plurality of first semiconductor layers, wherein the first dipole layer comprises a first dipole material having a first polarity;
forming a second dipole layer to surround a second group of the plurality of first semiconductor layers, wherein the second dipole layer comprises a second dipole material having a second polarity opposite of the first polarity; and
subjecting the first and second dipole layers to a first thermal treatment.