Patent ID: 11954588
Assignee: UNIVERSITY OF DAYTON
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 1:
2. The method of claim 1, further comprising:
deactivating each input voltage from a plurality of input voltages applied to each corresponding resistive memory, wherein each input voltage from the plurality of input voltages that is deactivated is set to 0.0V;
activating a single input voltage from the plurality of input voltages applied to a single corresponding resistive memory, wherein the single output voltage is applied to a horizontal wire that the single corresponding resistive memory is positioned;
determining whether a single conductance value associated with the single corresponding resistive memory is within the conductance value threshold based on a single output voltage signal that is generated from the activation of the single input voltage that is applied to the single corresponding resistive memory; and
adjusting the single conductance value of the single corresponding resistive memory to be within the conductance value threshold when the conductance value associated with the single corresponding resistive memory deviates beyond the conductance value threshold.