Patent ID: 11871572
Assignee: nan
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 1:
2. The method of claim 1 further comprising forming the high-k dielectric material within the first voids to line the first voids; wherein the forming of the conductive levels comprises forming conductive material within the lined first voids; wherein the forming of the second voids exposes portions of the high-k dielectric material above and below the conductive material; wherein the second voids have a vertical thickness; and further comprising the following steps in the following order;
removing the exposed portions of the high-k dielectric material;
forming strips within the second voids to narrow said vertical thickness;
extending the second voids through the charge-blocking material and then through the charge-storage material to divide the charge-storage material into the vertically-spaced segments; and
at least partially filling the second voids with insulative material.