Patent ID: 11923441
Assignee: APPLIED MATERIALS, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  C  B | IPC C  H

Claim 14:
15. The processing tool of claim 14, wherein the gate-all-around transistor comprises a source region having a source and a source contact, the source region on a top surface of the substrate; a drain region having a drain and a drain contact, the drain region on the top surface of the substrate; a channel located between the source and the drain and having an axis that that is substantially orthogonal to the top surface of the substrate; a gate enclosing the channel between the source region and the drain region; the thermal oxide layer overlying and in contact with one or more of the gate, the source contact, or the drain contact; and the low-κ layer overlying the thermal oxide layer.