Patent ID: 11909856
Assignee: MELLANOX TECHNOLOGIES, LTD.
Field: Digital communication (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 11:
12. The apparatus according to claim 10, wherein the packet processing circuitry is configured to:
receive a first data chunk from the memory;
find that the first data chunk includes a first partial block;
request a first additional data chunk from the memory, responsively to finding that the first data chunk includes the first partial block;
cryptographically process the first partial block and the first additional data chunk together as a whole block using the block cipher yielding a first cryptographically processed data block;
divide the first cryptographically processed data block into the first and second segments;
add the first segment to the first packet; and
store the second segment in the memory until the second packet is processed by the packet processing circuitry.