Patent ID: 11887690
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. A method, comprising:
isolating a conductor of a memory die from a voltage source based at least in part on deactivating a first transistor that is associated with a first level of the memory die above a substrate;
generating a first voltage at the conductor of the memory die based at least in part on coupling a storage element of a memory cell with a digit line and coupling the digit line with the conductor;
shifting the conductor from the first voltage to a second voltage based at least in part on shifting a bias applied to a gate of a second transistor that is associated with a second level of the memory die above the substrate from a third voltage to a fourth voltage, the second transistor having a channel portion coupled between a first portion of the conductor and a second portion of the conductor; and
determining a logic state based at least in part on shifting the conductor from the first voltage to the second voltage.