Patent ID: 11923456
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC B  H | IPC H

Claim 0:
1. A semiconductor device comprising:
channels at a plurality of levels, respectively, the channels spaced apart from each other in a vertical direction on an upper surface of a substrate;
a gate structure on the substrate, the gate structure at least partially surrounding a surface of each of the channels and extending in a first direction substantially parallel to the upper surface of the substrate, and the gate structure including an interface pattern, a gate insulation pattern, a workfunction control pattern, and a gate electrode sequentially stacked from a surface of each of the channels; and
a source/drain layer at each of opposite sides of the gate structure in a second direction substantially parallel to the upper surface of the substrate and crossing the first direction, the source/drain layer being connected to sidewalls of the channels,
wherein a sidewall of the source/drain layer includes a plurality of protrusions spaced apart from each other in the vertical direction, each of the plurality of protrusions protruding in the second direction toward the gate structure and overlapping the workfunction control pattern having a side surface concave theretoward in the second direction.