Patent ID: 11869888
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A structure, comprising:
a substrate with spaced apart first and second isolation regions;
a polysilicon resistor structure on the first isolation region, comprising:
a metal oxide dielectric layer;
a metal nitride layer; and
a doped polysilicon layer overlying an un-doped polysilicon layer;
a first spacer structure on a first sidewall of the polysilicon resistor structure and along a length of the polysilicon resistor structure in a direction perpendicular to the substrate;
a second spacer on a second sidewall of the polysilicon resistor structure and along a length of the polysilicon resistor structure in a direction perpendicular to the substrate; and
a silicide formed on the doped polysilicon layer and extending from the first spacer structure to the second spacer structure;

a transistor structure formed between the first and second isolation regions, comprising:
the metal oxide dielectric layer;
the metal nitride layer;
a metal gate electrode; and
source/drain regions formed in the substrate and adjacent to the metal gate electrode; and

a top contact to direct current flow within the doped polysilicon layer along a length of the polysilicon resistor structure.