Patent ID: 11967368
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. The memory system according to claim 1, wherein writing data corresponding to the first bit, the second bit and the fourth bit in the first memory cell of the k-th string and writing data corresponding to the third bit in the first memory cell of the k-th string are performed such that, among fifteen boundaries existing between adjacent threshold regions in the first to sixteenth threshold regions, a number of boundaries having different values of the first bit, the number of boundaries having different values of the second bit, the number of boundaries having different values of the third bit, and the number of boundaries having different values of the fourth bit are (1, 4, 5, 5), (1, 5, 4, 5), or (3, 3, 4, 5) in order.