Patent ID: 11929352
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC H

Claim 8:
9. A device comprising:
a memory chip including:
a set of first word lines, which are stacked along a first direction and extend in a first region and a second region of the memory chip along a second direction crossing the first direction;
a pillar including:
a semiconductor layer extending through the first word lines along the first direction in the first region, and
an insulating layer between the semiconductor layer and the first word lines;

a set of memory cells in the first region, each of which is disposed at a corresponding intersection of the pillar and one of the first word lines;
a set of first bonding pads in the second region;
a set of transistors in the second region, each of which is configured to electrically connect or disconnect a corresponding one of the first word lines to or from a corresponding one of the first bonding pads; and
a circuit chip disposed above the memory chip along the first direction, the circuit chip including:
a set of second bonding pads which are connected to the first bonding pads; and
a control circuit electrically connected to the transistors through the first and second bonding pads.