Patent ID: 11921630
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A data processing system comprising:
a memory device including a plurality of memory blocks;
a controller including a first memory; and
a host including a second memory and configured to provide a plurality of commands for user data to the controller;
wherein the controller stores data segments of the user data in the first memory, controls the memory device to store the data segments in the memory blocks,
updates logical-to-physical (L2P) mapping entries of map data in response to storage of the data segments in the memory blocks and stores the updated L2P mapping entries in the first memory,
assists the host to store the updated L2P mapping entries to the second memory in the host, and
wherein the controller controls the memory device to store the updated L2P mapping entries, stored in the first memory, in the memory blocks,
wherein the controller updates a second L2P mapping entry group of L2P mapping entries by referencing some part of a first L2P mapping entry group of the L2P mapping entries that has already been updated.