Patent ID: 11966635
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 20:
21. A memory device, comprising:
a plurality of logical units configured to store data, wherein the plurality of logical units are identified by a corresponding plurality of logical unit numbers (LUNs);
a plurality of LUN queue groups,
wherein each LUN queue group, included in the plurality of LUN queue groups, is associated with a different LUN of the plurality of LUNs,
wherein each LUN queue group includes a plurality of LUN queues,
wherein each LUN queue, included in an individual LUN queue group of the plurality of LUN queue groups, is associated with a respective intra-LUN priority level that indicates a priority of that LUN queue compared to every other LUN queue included in the individual LUN queue group,
wherein each LUN queue, included in the individual LUN queue group, is associated with an execution priority level that indicates a priority for execution of commands in that LUN queue compared to every other command included in the plurality of LUN queue groups,
wherein a quantity of intra-LUN priority levels is greater than a quantity of execution priority levels;

an execution queue group to which each command stored in the plurality of LUN queue groups is to be transferred for execution;
a command processor configured to generate commands for placement in LUN queues of the LUN queue groups;
a LUN scheduler configured to select and transfer commands from the plurality of LUN queue groups to the execution queue group based on intra-LUN priority levels; and
a command executor configured to execute commands from the execution queue group based on execution priority levels.