Patent ID: 11948903
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor package, comprising:
a first stack including a first semiconductor substrate;
a plurality of first through-silicon vias (TSVs) passing through the first semiconductor substrate;
a second stack on the first stack, the second stack including a second surface facing a first surface of the first stack;
a first pad on the first surface of the first stack, the first pad being in contact with one or more first TSVs of the plurality of first TSVs;
a second pad on the first surface of the first stack, the second pad being adjacent to the first pad and not being in contact with the plurality of first TSVs;
an interconnection line on the first surface of the first stack, the interconnection line connecting the first pad and the second pad;
a first bump on the first pad;
a third pad on the second surface of the second stack, the third pad being on the first bump;
a second bump on the second pad; and
a fourth pad on the second surface of the second stack, the fourth pad being on the second bump;
wherein the first pad and the second pad are in direct contact with the interconnection line.