Patent ID: 11915992
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A method for forming a package structure, comprising:
forming a semiconductor die over a first side of an interconnect structure;
forming a first stacked die package structure over the first side of the interconnect structure;
forming a second stacked die package structure over the first side of the interconnect structure, wherein the semiconductor die is between the first stacked die package structure and the second stacked die package structure;
forming an underfill layer between the semiconductor die and the first stacked die package structure; and
forming a package layer over the underfill layer, wherein an interface is between the underfill layer and the package layer, and the interface is lower than a top surface of the semiconductor die.