Patent ID: 11955197
Assignee: ROBERT BOSCH GMBH
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A method for shifting memory values, which are stored in memory cells of a first row of a memory device to be shifted, the memory device including:
a cell field having a plurality of memory cells,
a number N of bit lines, which are each respectively connected to at least one of the memory cells of the cell field, N being a whole number greater than one and a bit line number in a range from 1 to N being assignable to each bit line according to a bit line sequence,
N sense amplifiers, a sense amplifier number in the range from 1 to N being assignable to each sense amplifier according to a sense amplifier sequence, and
a bit shift circuit, which has a number S of switch element rows, S being a whole number greater than one and a row number in a range from zero to S−1 being assignable to each switch element row according to a switch element row sequence,
wherein each switch element row has respectively at least one semiconductor switch element, each semiconductor switch element being connected to one of the bit lines and to one of the sense amplifiers, so that in a conductive state of the semiconductor switch element an electrically conductive connection exists between the bit line and the sense amplifier and in a non-conductive state of the semiconductor switch element the bit line is insulated from the sense amplifier,
wherein the semiconductor switch elements of each respective switch element row connects all bit lines whose bit line number is smaller than or equal to the number N minus the row number of the respective switch element row, to sense amplifiers, so that the respective sense amplifier number is equal to the respective bit line number plus the row number of the respective switch element row,
wherein the memory device further includes a controller which is connected to the bit shift circuit, the controller being configured to transfer each switch element row independently of one another into a conductive or non-conductive row state,
wherein in the conductive row state of each switch element row of the switch element rows, all semiconductor switch elements of the switch element row being switched into the conductive state, and in the non-conductive row state of the switch element row, all semiconductor switch elements of the switch element row being switched into the non-conductive state,
wherein the controller is configured to transfer the bit shift circuit into S different circuit states, wherein in a kth of the S circuit states, the switch element row with row number k being in the conductive row state and the switch element rows, which differ from the switch element row with row number k, being in the non-conductive row state, k being a whole number in the range from 0 to S−1, and wherein the controller is configured to transfer the bit shift circuit into a non-conductive circuit state, in which all switch element rows are in the non-conductive row state,
wherein the memory device further includes word lines which are each respectively connected to multiple memory cells, an application of a word line voltage to a word line enabling access via the bit lines to the memory cells that are connected to the word line,
wherein the method comprises the following steps:
applying the word line voltage on a word line which is connected to the memory cells of the first row to be shifted;
(i) when a left shift by u positions is to occur, transferring the bit shift circuit into the 0th circuit state and subsequently transferring the bit shift circuit into a uth circuit state, u being a number in the range from 1 to S−1, and (ii) when a right shift by v positions is to occur, transferring the bit shift circuit into a with circuit state and subsequently transferring the bit shift circuit into the 0th circuit state, v being a number in the range from 1 to S−1; and
terminating the application of the word line voltage.