Patent ID: 11916124
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC B  H | IPC H

Claim 8:
9. A transistor comprising:
a first nanostructure over a semiconductor substrate;
a second nanostructure over the first nanostructure;
a gate dielectric surrounding the first nanostructure and the second nanostructure; and
a gate electrode over the gate dielectric, wherein the gate electrode comprises:
a p-type work function metal, wherein the p-type work function metal extends continuously from a first portion of the gate dielectric on the first nanostructure to a second portion of the gate dielectric on the second nanostructure, wherein the p-type work function metal has a first thickness between the first nanostructure and the second nanostructure, wherein the p-type work function metal has a minimum width between the first nanostructure and the second nanostructure, wherein a ratio of the first thickness to the minimum width is in a range of 0.03 to 1, wherein the minimum width is measured in a first direction parallel to a top surface of the semiconductor substrate, and wherein the first thickness is measured in a second direction perpendicular to the first direction; and
a fill metal over the p-type work function metal.