Patent ID: 11894052
Assignee: ALMA MATER STUDIORUM—UNIVERSITA' DI BOLOGNA
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. The in-memory computation circuit of claim 1:
wherein said memory array further includes a plurality of further memory cells arranged in said matrix of plural rows and plural columns, wherein positive computational weights for the in-memory compute operation are stored in the memory cells and negative computational weights for the in-memory compute operation are stored in the further memory cells; and
wherein the biasing circuit is provided for each bit line and each further bit line; and
wherein the combining by the column combining circuit comprises adding the analog signals generated at the column outputs of the biasing circuits for the bit lines and subtracting the analog signals generated at the column outputs of the biasing circuits for the further bit lines.