Patent ID: 11908701
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A patterning method, comprising:
providing a substrate;
providing a first material layer on the substrate;
providing a second material layer over the first material layer, wherein the second material layer has a first opening partially exposing the first material layer;
depositing a blocking layer in the first opening;
forming a passivation layer in the first opening, wherein the passivation layer covers a top surface of the second material layer, a top surface of the blocking layer, and sidewalls of the first opening;
performing a first etching process to remove a portion of the blocking layer and a portion of the first material layer to form a second opening exposing the substrate; and
performing a second etching process to remove the passivation layer.