Patent ID: 11908932
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A method of forming vertical transistors of an apparatus, the method comprising:
forming a conductive contact;
removing portions of a channel material to form one or more channel regions separated by trenches;
forming a liner material over bottom surfaces of the trenches and over sidewalls of the one or more channel regions;
removing portions of the liner material from horizontal surfaces of the one or more channel regions;
removing exposed portions of the channel material to form elongated trenches;
removing portions of the channel material below the liner material without substantially removing the liner material to form upper regions of the channel regions having a first width and lower regions of the channel regions below a respective upper region and having a second width smaller than the first width, each upper region defining at least one overhang portion extending laterally beyond an outer boundary of a respective lower region;
forming a gate dielectric material over the sidewalls of the lower regions and at least the at least one overhang portion of each of the upper regions of the channel regions;
forming gate electrodes over the conductive contact and adjacent to the gate dielectric material, a first portion of each gate electrode being vertically beneath a respective overhang portion of a respective upper region of the one or more channel regions and a second portion extending past the at least one overhang portion of the upper region of the channel region, wherein each gate electrode is at least partially recessed within a respective channel region relative to an outermost surface of the respective channel region in a direction orthogonal to a longitudinal axis of a respective vertical transistor; and
forming an insulative structure directly between a gate electrode of a first vertical transistor and a gate electrode of a second vertical transistor adjacent to the first vertical transistor, an insulative material of the insulative structure directly intervening between an upper region of a channel region of the first vertical transistor and an upper region of a channel region of the second vertical transistor, and the insulative material of the insulative structure directly vertically intervening between the gate dielectric material and the conductive contact in regions underlying the gate electrodes.