Patent ID: 11900123
Assignee: ADVANCED MICRO DEVICES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A processor comprising:
a processor pipeline having a set of parallel processing units for executing instructions; and
a set manager coupled to the processor pipeline, wherein the set manager is configured to:
receive one or more sets of instructions;
characterize at least one of the received sets of instructions during a first window of time;
subsequent to the characterization, receive a plurality of sets instructions for execution, wherein the plurality of sets of instructions includes at least one previously characterized set of instructions;
determine and apply a set limit comprising a number of instructions to be executed at the processor pipeline during a second window of time subsequent to the first window of time based on the characterization; and
provision a set of instructions of the plurality of sets of instructions to be executed at the processor pipeline during the second window of time based on the set limit.