Patent ID: 11861279
Assignee: KEPLER COMPUTING INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A non-transitory machine-readable storage media having machine-readable instructions stored thereon that when executed cause one or more machines to perform a method of inverter minimization, the method comprising:
receiving one or more inputs including a majority or minority inverter graph and a synthesis objective, wherein a logic circuit is associated with the majority or minority inverter graph;
collecting a list of majority or minority gates, for an individual depth, in an order, wherein the list of majority or minority gates includes ‘r’ majority or minority gates;
for the individual depth, selecting the ‘r’ majority or minority gates;
generating a function of ‘r’ new majority or minority inverter graphs from the majority or minority inverter graph at the individual depth;
simplifying the function of ‘r’ new majority or minority inverter graphs to generate a simplified function of ‘r’ new majority or minority inverter graphs;
determining whether the synthesis objective is delay minimization; and
determining a second majority or minority inverter graph, that results in a smallest delay in the individual depth, based on determining that the synthesis objective is delay minimization and based on the simplified function of the ‘r’ new majority or minority inverter graphs.