Patent ID: 11894367
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 16:
17. An integrated circuit, comprising:
a first gate all around transistor including:
a plurality of first semiconductor nanosheets corresponding to channel regions of the first gate all around transistor;
a first interfacial dielectric layer positioned on the first semiconductor nanosheets;
a dipole layer positioned on the first interfacial dielectric layer and including dipole material; and
a first high-K dielectric layer positioned on the dipole layer; and

a second gate all around transistor including:
a plurality of second semiconductor nanosheets corresponding to channel regions of the second gate all around transistor;
a second interfacial dielectric layer positioned on the second semiconductor nanosheets; and
a second high-K dielectric layer positioned directly on the second interfacial dielectric layer, wherein a concentration of the dipole material is zero in the second interfacial dielectric layer and the second high-K dielectric layer, wherein a distribution of dipole dopants in the first interfacial dielectric layer and a distribution of dipole dopants in the first high-K dielectric layer are arranged to mirror symmetrically along a central line between the first interfacial dielectric layer and the first high-K dielectric layer.