Patent ID: 11862512
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 5:
6. A semiconductor package, comprising:
a substrate having contacts; and
redistribution layers disposed on the substrate and each of the redistribution layers comprising:
a dielectric layer;
a dual damascene redistribution pattern embedded in the dielectric layer, wherein the dual damascene redistribution pattern includes via portions connected with the contacts and a routing line portion disposed on the via portions, the routing line portion is laterally and directly connected with the via portions, no interface is between the via portions and the routing line portion, a slant sidewall of each of the via portions is connected with a slant sidewall of the routing line portion, and the slant sidewall of each of the via portions has a same slope as the slant sidewall of the routing line portion, and the slant sidewall of each of the via portions is aligned with the slant sidewall of the routing line portion, and a top surface of the dual damascene redistribution pattern is lower than a top surface of the dielectric layer, a rounded corner is between the top surface of the dielectric layer and a slant sidewall of the dielectric layer, and the slant sidewall of the dielectric layer is in contact with the slant sidewall of the routing line portion; and
a seed metallic pattern sandwiched between the dual damascene redistribution pattern and the dielectric layer and between the via portions and the contacts.