Patent ID: 11881826
Assignee: CIRRUS LOGIC INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. The circuitry according to claim 12, wherein the circuitry is configured such that during start-up or shut-down of the amplifier circuitry:
the first dummy output stage is coupled to the first and second differential outputs of the first pseudo-differential amplifier;
the first dummy feedback path couples the output of the first dummy output stage to the input of the first pseudo-differential amplifier so as to bias the first pseudo-differential amplifier;
the second dummy output stage is coupled to the first and second differential outputs of the second pseudo-differential amplifier;
the second dummy feedback path couples the output of the second dummy output stage to the input of the second differential amplifier so as to bias the second pseudo-differential amplifier; and
an output of the common mode buffer circuitry is coupled to the first and second output nodes such that the first and second output nodes receive the common mode voltage; and/or
wherein the circuitry is configured such that during normal operation of the amplifier circuitry:
the first real output stage is coupled to the first and second differential outputs of the first pseudo-differential amplifier;
the first real feedback path couples the output of the first real output stage to the input of the first pseudo-differential amplifier;
the second real output stage is coupled to the first and second differential outputs of the second pseudo-differential amplifier;
the second real feedback path couples the output of the second real output stage to the input of the second pseudo-differential amplifier; and
an output of the common mode buffer circuitry is decoupled from the first and second output nodes; and/or
wherein the circuitry is configured such that during a mute state in which no input signal is present at the input node, an output of the common mode buffer circuitry is coupled to the first and second output nodes such that the first and second output nodes receive the common mode voltage.