Patent ID: 11954588
Assignee: UNIVERSITY OF DAYTON
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. The method of claim 5, further comprising:
receiving by a first comparator the complemented dot-product operation value that is applied to the first comparator and a maximum conductance voltage signal that is applied to the first comparator, wherein the maximum conductance voltage signal represents a maximum conductance level;
receiving by a second comparator the complemented dot-product operation value that is applied to the second comparator and a minimum conductance voltage signal that is applied to the second comparator, wherein the minimum conductance voltage signal represents the minimum conductance level;
generating an increased resistance signal when the complemented dot-product operation value is less than the minimum conductance voltage signal to increase the single conductance value of the single corresponding resistive memory until the single conductance value is increased above the minimum conductance level;
generating a decreased resistance signal when the complemented dot-product operation value is above the maximum conductance voltage signal to decrease the signal conductance value of the single corresponding resistive memory until the single conductance value is decreased below the maximum conductance level; and
generating a no-change resistance signal when the complemented dot-product operation value is above the minimum conductance voltage signal and below the maximum conductance voltage signal thereby having the single conductance value of the single corresponding resistive memory remained unchanged.