Patent ID: 11862240
Assignee: GLOBALFOUNDRIES U.S. INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A circuit structure comprising:
a first latch having an input node and an output node;
a second latch having an input node and an output node, wherein the output node of the second latch is coupled to the input node of the first latch, and wherein the input node of the second latch is coupled to the output node of the first latch; and
a read/write (R/W) circuit including a plurality of transistors coupling a word line, a bit line, and an inverted bit line to at least two outputs, one of the at least two outputs being coupled to the input node of the first latch and another of the at least two outputs being coupled to the input node of the second latch.