Patent ID: 11908430
Assignee: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A display device, comprising a display substrate,
wherein the display substrate comprises:
a base substrate and a plurality of shift register units disposed on the base substrate,
wherein the plurality of shift register units are arranged side by side along a first direction;
each shift register unit of the plurality of shift register units comprises an input circuit, an output circuit, a first reset circuit, and a frame reset signal connection line;
the frame reset signal connection line extends along a second direction and is configured to provide a frame reset signal to the first reset circuit, the second direction and the first direction cross each other;
the input circuit is configured to control a level of a first node in response to an input signal;
the output circuit is configured to receive a clock signal and output the clock signal as an output signal to an output terminal under control of the level of the first node;
the first reset circuit is configured to reset the first node and the output terminal during a period of time between two display frames of the display substrate in response to the frame reset signal;
the first reset circuit comprises a first transistor and a second transistor, and the frame reset signal connection line, a gate electrode of the first transistor, and a gate electrode of the second transistor are disposed in a first conductive layer; and
the shift register unit further comprises a first transfer electrode in a second conductive layer, the gate electrode of the first transistor and the gate electrode of the second transistor are connected and both are electrically connected to the frame reset signal connection line through the first transfer electrode;
wherein the first transistor and the second transistor are arranged adjacently along the second direction;
the shift register unit further comprises a first voltage connection line extending along the second direction, the first voltage connection line is configured to provide a first voltage to the shift register unit, and the first voltage is used to reset the first node and the output terminal during the period of time between the two display frames of the display substrate;
the first voltage connection line, a first electrode of the first transistor and a second electrode of the first transistor, and a first electrode of the second transistor and a second electrode of the second transistor are all disposed in the second conductive layer;
the first electrode of the first transistor is electrically connected to the first node, the first electrode of the second transistor is electrically connected to the output terminal, and the second electrode of the first transistor and the second electrode of the second transistor are both electrically connected to the first voltage connection line;
wherein the shift register unit further comprises an input signal connection line extending along the second direction, the input signal connection line is configured to provide the input signal to the input circuit;
the input circuit comprises a third transistor, the input signal connection line and a gate electrode of the third transistor are both disposed in the first conductive layer, and the gate electrode of the third transistor is connected to the input signal connection line;
both a first electrode and a second electrode of the third transistor are disposed in the second conductive layer, the first electrode of the third transistor is electrically connected to the gate electrode of the third transistor, the second electrode of the third transistor is connected to the first electrode of the first transistor, and the first node is a junction node of the second electrode of the third transistor and the first electrode of the first transistor;
wherein the shift register unit further comprises a second transfer electrode disposed in the first conductive layer and a third transfer electrode disposed in the second conductive layer, an orthographic projection of the second transfer electrode on the base substrate and an orthographic projection of the third transfer electrode on the base substrate at least partially overlap;
the second transfer electrode is connected to the gate electrode of the third transistor, the third transfer electrode is connected to the first electrode of the third transistor, and the second transfer electrode is electrically connected to the third transfer electrode.