Patent ID: 11908929
Assignee: FUJI ELECTRIC CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A semiconductor device having an active portion and a gate pad portion on a semiconductor substrate, the semiconductor device comprising:
a first semiconductor layer of a first conductivity type, the first semiconductor layer having a first surface and a second surface opposite to each other;
a second semiconductor layer of a second conductivity type, provided on the first surface of the first semiconductor layer, the second semiconductor layer having a first surface and a second surface opposite to each other, the second surface of the second semiconductor layer facing the first semiconductor layer;
in the active portion:
a plurality of first semiconductor regions of the first conductivity type, selectively provided in the second semiconductor layer at the first surface thereof;
a first electrode provided on the first semiconductor regions; and
a plurality of first trenches penetrating through the first semiconductor regions and the second semiconductor layer and reaching the first semiconductor layer, the first trenches extending in beneath the first electrode in an extending direction that is parallel to the first surface of the first semiconductor layer;

in the gate pad portion:
a gate electrode pad provided above the second semiconductor layer;
a plurality of second trenches provided beneath the gate electrode pad, the second trenches extending in the extending direction; and
a plurality of second semiconductor regions of the second conductivity type, each provided in the first semiconductor layer so as to be in contact with a respective one of bottoms of the second trenches;

a plurality of fourth semiconductor regions of the second conductivity type, each of which is provided in the first semiconductor layer so as to be in contact with a respective one of bottoms of the first trenches; and
one or more fifth semiconductor regions of the second conductivity type, each of which is provided in the first semiconductor layer so as to be in contact with a corresponding one of two opposing sidewalls of the first trenches, and electrically connects the second semiconductor layer and a corresponding one of the fourth semiconductor regions, wherein
each of the second trenches is continuous with a respective one of the first trenches, and
the second semiconductor layer is continuous from the active portion to the gate pad portion.