Patent ID: 11901350
Assignee: NANYA TECHNOLOGY CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for fabricating a semiconductor device, comprising:
providing a first stacking structure comprising:
a first controller die; and
a plurality of first storage dies sequentially stacked on the first controller die;

providing a second stacking structure comprising:
a second controller die; and
a plurality of second storage dies sequentially stacked on the second controller die;

bonding the first controller die onto a bottom die through a plurality of first interconnect units, wherein the plurality of first interconnect units respectively comprise a first exterior layer and a first cavity, the first exterior layer is between the first stacking structure and the bottom die, and the first cavity is enclosed by and directly contacted with the first exterior layer, the first stacking structure, and the bottom die; and
bonding the second controller die onto the bottom die through a plurality of second interconnect units;
wherein the plurality of first storage dies respectively comprise a plurality of first storage units configured as a floating array;
wherein the plurality of second storage dies comprise a plurality of second storage units respectively comprising an insulator-conductor-insulator structure.