Patent ID: 11960409
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A system comprising:
a memory device comprising a plurality of physical memory blocks (PMBs) and associated with a logical address space that comprises a first zone; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
receiving a first request to store a first data referenced by a first logical block address (LBA) associated with the first zone;
obtaining a version identifier of the first zone, wherein the version identifier of the first zone characterizes a number of times the first zone has been invalidated, wherein invalidating the first zone comprises invalidating multiple LBAs of the first zone;
selecting, in view of the version identifier of the first zone, a first PMB of the plurality of PMBs;
mapping the first LBA associated with the first zone to the first PMB; and
storing the first data in the first PMB.