Patent ID: 11943934
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 5:
6. An integrated chip, comprising:
a lower interconnect arranged within a lower inter-level dielectric (ILD) structure over a substrate;
a bottom electrode disposed over the lower interconnect;
a magnetic tunnel junction (MTJ) stack disposed over the bottom electrode;
a top electrode disposed over the MTJ stack;
a glue layer disposed along sidewalls and a lower surface of the top electrode, wherein a top of the glue layer is recessed below a top of the top electrode and wherein the glue layer has a greater thickness directly below outermost edges of the top electrode than directly below a center of the top electrode; and
one or more sidewall spacers disposed along outer sidewalls of the glue layer, wherein a top of the one or more sidewall spacers is below the top of the top electrode and a bottom of the one or more sidewall spacers is below a bottom of the glue layer.