Patent ID: 11943022
Assignee: INTEL CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. The apparatus of claim 1, wherein the processing circuitry is further arranged to:
engage in beamforming using a digital beamforming architecture, the digital beamforming architecture comprising:
an analog-to-digital converter (ADC) that digitizes Nr, analog signals received from a plurality of antennas,
a plurality of synchronization signal (SS) detectors that determine coarse timing and fractional frequency offset (FFO) of SUR beamformed signals,
a beamforming network disposed between the ADC and the SS detectors, the beamforming network supplied with a Nr dimension data sample vector to produce the NRF beamformed signals, the SS detectors configured to detect NSS cells from the NRF beamformed signals,
a plurality of fast Fourier transforms (FFTs) to which outputs of the SS detectors are provided,
fine timing and integer frequency offset (IFO) to determine fine timing and frequency offset synchronization of neighboring cells, and
measurement circuitry to measure at least one of Reference Signal Received Power (RSRP) or Reference Signal Received Quality (RSRQ) of a cell reference signal (CRS) of each of the neighboring cells.