Patent ID: 11973113
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A transistor, comprising:
a substrate having a P-type conductivity;
an isolation region disposed in the substrate to divided the substrate into a lower portion and an upper portion, wherein the upper portion extends along a first direction, and wherein the isolation region comprises:
a dielectric material extending from a top surface of the upper portion to a top surface of the lower portion; and
a doped region physically separating a sidewall and a bottom surface of the dielectric material from the substrate;

a gate structure extending along a second direction different from the first direction and across the upper portion;
source and/or drain (S/D) regions having a N-type conductivity and disposed in the upper portion of the substrate at opposite sides of the gate structure; and
a channel region disposed below the gate structure and abutting between the S/D regions, wherein the channel region has the P-type conductivity type and the channel region has a doping concentration substantially equal to a doping concentration of the substrate.