Patent ID: 11973038
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A package, comprising:
a plurality of metallic patterns;
a molding compound disposed on the plurality of metallic patterns;
a buffer layer disposed on the molding compound;
a die attach film disposed on the molding compound and the buffer layer, and partially overlapped with each of the plurality of metallic patterns;
a semiconductor die disposed on the die attach film and partially overlapped with each of the plurality of metallic patterns, wherein the semiconductor die is electrically and physically separated from the plurality of metallic patterns by the molding compound and the buffer layer, and sidewalls of the semiconductor die are aligned with sidewalls of a film material of the die attach film; and
a plurality of through vias surrounding the semiconductor die and partially overlapped with each of the plurality of metallic patterns.