Patent ID: 11935867
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor package, comprising:
a package substrate that extends in a first direction and a second direction perpendicular to the first direction;
a plurality of logic dies and a memory stack structure on the package substrate; and
an interposer substrate mounted in the package substrate,
wherein the entirety of the memory stack structure vertically overlaps the interposer substrate,
wherein each of the logic dies includes:
a first part that is horizontally offset from the interposer substrate; and
a plurality of first connection terminals that electrically connect the logic dies to the package substrate; and
a plurality of second connection terminals that electrically connect the logic dies to the interposer substrate; and
a second part that vertically overlaps the interposer substrate,

wherein the interposer substrate includes:
an interlayer dielectric layer; and
a plurality of wiring lines in the interlayer dielectric layer, and

wherein the memory stack structure is electrically connected to at least one of the logic dies through the wiring lines of the interposer substrate,
wherein a bottom surface of the interposer substrate is in contact with the package substrate, and
wherein the interposer substrate does not include a conductive structure providing an electrical connection between the wiring lines of the interposer substrate and the bottom surface of the interposer substrate.