Patent ID: 11935754
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. A method comprising:
depositing a gate dielectric around a first nanostructure and a second nanostructure, the first nanostructure is disposed over the second nanostructure;
depositing a work function metal over the gate dielectric, wherein the work function metal completely fills a region extending from a first portion of the gate dielectric surrounding the first nanostructure to a second portion of the gate dielectric surrounding the second nanostructure;
depositing a barrier layer over the work function metal, wherein depositing the barrier layer comprises a first atomic layer deposition (ALD) process; and
depositing a fill metal over the barrier layer, wherein depositing the fill metal comprises using a fluorine-comprising precursor.