Patent ID: 11955728
Assignee: INTEL CORPORATION
Field: Telecommunications (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A semiconductor package, comprising:
a printed circuit board (PCB);
an IC die comprising:
a semiconductor substrate;
a metallization stack comprising layers of conductive metal traces stacked along a thickness of the IC die, separated from each other by a dielectric material, and electrically coupled with conductive vias in the dielectric material;
a ground plane in one of the layers of the metallization stack;
an IC including an inductor, a portion of the IC in the semiconductor substrate and another portion of the IC in the metallization stack, the IC being electrically coupled to the ground plane with one plurality of vias;
a loop antenna surrounding the IC in another one of the layers of the metallization stack and electrically coupled to the ground plane with another plurality of vias; and
a metal shield enclosing the IC die,
wherein the loop antenna includes metal loops configured to cause electric currents in the metal loops to cancel each other when excited in a first direction, and to aggregate when excited in a second direction perpendicular to the first direction.