Patent ID: 11971992
Assignee: LATTICE SEMICONDUCTOR CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 8:
9. The secure PLD failure characterization system of claim 1, further comprising:
an external system comprising a processor and a memory and configured to be coupled to the secure PLD through the configuration input/output (I/O) of the secure PLD, wherein the memory comprises machine-readable instructions which when executed by the processor of the external system are adapted to cause the external system to:
provide a debug configuration to the secure PLD over the configuration I/O;
receive a debug digest from the secure PLD associated with booting and/or execution of the debug configuration by the PLD fabric of the secure PLD;
determine an updated manufacturer trim based, at least in part, on the received debug digest; and
provide the updated manufacturer trim to the secure PLD over the configuration I/O.