Patent ID: 11901019
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 16:
17. A non-volatile memory device, comprising:
a plurality of bit lines each connected to a corresponding plurality of non-volatile memory cells;
a plurality of sense amplifier circuits each configured to read data from memory connected to a corresponding one or more bit lines;
a plurality of sets of internal data latches, each set of internal data latches configured to store data associated with a corresponding one of the sense amplifiers;
a cache buffer comprising a plurality of sets of transfer data latches each corresponding to one of the sets of internal data latches;
an input-output interface configured to provide data to an external data bus; and
one or more control circuits connected to the sense amplifier circuits, the sets of internal data latches, the cache buffer, and the input-output interface, the one or more control circuits configured to:
perform a read operation by each of the plurality of sense amplifiers on a plurality of the corresponding memory cells;
store results of the read operation by each of the sense amplifiers in the corresponding set of internal data latches;
compress, within the corresponding set of internal data latches, the results of the read operation by each of the sense amplifiers;
transfer the compressed results of the read operation from each of the sets of internal data latches to the corresponding set of transfer data latches;
compact the compressed results of the read operation from the sets of transfer data latches into a smaller number of the sets of transfer latches; and
transfer the compacted compressed results of the read operation from the sets of transfer latches data latches to the input-output interface.