Patent ID: 11910607
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 18:
19. A three-dimensional semiconductor memory device, comprising:
a peripheral circuit structure on a first substrate, the peripheral circuit structure including peripheral circuit transistors;
a second substrate on the peripheral circuit structure;
first source conductive patterns on the second substrate;
second source conductive patterns on the first source conductive patterns;
stacks on the second source conductive patterns, each of the stacks including a plurality of gate electrodes stacked on the second source conductive patterns;
vertical channel portions penetrating the stacks and the first and the second source conductive patterns and extending into the second substrate, the vertical channel portions being in contact with a side surface of each of the first source conductive patterns;
charge storing layers interposed between each of the vertical channel portions and each of the stacks; and
a common source pattern interposed between the stacks, the common source pattern extended between the first source conductive patterns and between the second source conductive patterns,
wherein a distance from the center line of the common source pattern to one of the first source conductive patterns is larger than a distance from the center line of the common source pattern to one of the second source conductive patterns.