Patent ID: 11943728
Assignee: BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC.
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A method for clock synchronization for use in high speed asynchronous serial interfaces, comprising:
on a second device:
receiving a signal from a first device comprising at least one active message and encoded idle traffic from the first device;
decoding the signal using 8B10B;
splitting, via a traffic splitter, the signal into an ingress regular traffic and an ingress idle traffic;
monitoring the ingress idle traffic to determine an amount of K28.5 characters;
starting an error check if the amount of K28.5 characters is above a threshold value;
generating a count-up or count-down signal via an up/down counter;
generating a calibration message comprising a calibration feedback traffic from the up/down counter;
merging the calibration message with the at least one active message to form a feedback message;
encoding the feedback message using 8B10B;
transmitting the feedback message to the first device; and

repeating preceding steps for a plurality of sample intervals, thereby reducing a probability of data sampling failure for high speed asynchronous serial interfaces.