Patent ID: 11923295
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of forming a semiconductor structure, the method comprising:
forming a first interconnect layer over a transistor;
forming a second interconnect layer over the first interconnect layer;
forming a third interconnect layer over the second interconnect layer;
forming a fourth interconnect layer over the third interconnect layer, the fourth interconnect layer comprising a conductive line;
forming a first dielectric layer over the fourth interconnect layer;
forming a high resistance layer on the first dielectric layer;
forming a second dielectric layer on the high resistance layer, the first dielectric layer and the second dielectric layer having a same composition;
patterning the second dielectric layer and the high resistance layer, wherein the patterning recesses the first dielectric layer over the conductive line, wherein after patterning the second dielectric layer;
the first dielectric layer has a first thickness over the conductive line;
the first dielectric layer has a second thickness under the high resistance layer, wherein the second thickness is greater than the first thickness; and
the second dielectric layer has a third thickness, wherein the third thickness is equal to the first thickness;

forming a low-k dielectric layer over the second dielectric layer and the first dielectric layer, the low-k dielectric layer extending over a top surface and a sidewall of the first dielectric layer;
forming a first opening through the low-k dielectric layer and the second dielectric layer, the first opening extending into the high resistance layer;
forming a second opening through the low-k dielectric layer and the first dielectric layer, forming the first opening and forming the second opening being performed simultaneously, wherein the first opening and the second opening have same bottom surface areas;
forming a conductive material in the first opening and the second opening; and
planarizing the low-k dielectric layer and the conductive material.