Patent ID: 11868267
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. An apparatus comprising:
a media resident on a solid state drive (SSD) having an access size associated with performance of memory operations having a same size as a cache line of a processing device coupled to the first media resident associated with performance of memory operations;
a data structure whose entries map management segments of respective physical locations to the media, wherein each management segment corresponds to a plurality of logical access units having the access size, and further comprise of at least one of a management segment address, a time stamp, or an access count, or combinations thereof; and
the processing device resident on the SSD and configure to, responsive to a request to perform a memory operation using an access unit having the access size:
determine a management entry to which the access unit corresponds;
update attribute data of the management entry; and
determine whether to perform a media management operation on a particular management segment corresponding to the management entry based on the updated attribute data.