Patent ID: 11923271
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An apparatus comprising:
a first integrated circuit (IC) die;
a second IC die on the first IC die;
a first package bump on the first IC die, the first package bump connected to a power supply;
a second package bump on the first IC die, the second package bump connected to the power supply;
a power distribution structure in the first IC die, the power distribution structure comprising:
a first Through-Silicon Via (TSV) connected to the first package bump,
a first ladder structure connected to the first TSV,
a second TSV connected to the second package bump, and
a second ladder structure connected to the second TSV; and

an interface disposed between the first die and the second IC die, wherein the interface connects the first ladder structure and the second ladder structure to a plurality of vertical top metal elements of the second IC die, and wherein each of the first ladder structure and the second ladder structure comprises a plurality of horizontal elements connected by a plurality of vertical elements.