Patent ID: 11867751
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Measurement (Instruments)
Classification: CPC G | IPC G

Claim 10:
11. A stacked semiconductor chip comprising:
a plurality of core dies, each core die including at least one semiconductor device configured to operate independently; and
a buffer die configured to provide a channel interface independent of each of the plurality of core dies via through-electrodes connected to the plurality of core dies,
wherein the buffer die comprises:
master test pads configured to receive master test operation signals provided by an external test device;
a mode register configured to set a bit signal allocated to indicate that a test access signal pad among the master test pads is not used by the external test device; and
a master test circuit configured to output a toggle detection signal by detecting a toggling of at least one of the master test operation signals, generate the internal master test enable signal in response to the bit signal of the mode register and the toggle detection signal, and transmit, via the through-electrodes, the internal master test enable signal to an internal test enable signal line of a channel selected from among a plurality of channels respectively connected to the plurality of core dies.