Patent ID: 11929761
Assignee: SEAGATE TECHNOLOGY LLC
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An apparatus comprising:
a low density parity check (LDPC) decoder configured decode a codeword of bits, including:
a variable node processor configured to provide a plurality of variable-to-check (v2c) message vectors to an edge combiner in parallel, the plurality of v2c message vectors including estimates for a selected set of bits of the codeword;
the edge combiner configured to:
generate a plurality of output message vectors for a plurality of check node vectors based on the plurality of v2c message vectors;
provide the plurality of output message vectors to the plurality of check node vectors simultaneously;

a check node processor configured to update the plurality of check node vectors based on the plurality of output message vectors; and
a convergence checker circuit configured to detect a valid code word based on bit value estimates from the variable node processor.