Patent ID: 11966471
Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G  H

Claim 9:
10. An integrated circuit comprising:
an interrupt interface on which a plurality of interrupts are monitored;
a monitoring interface on which alerts are triggered responsive to monitoring of the interrupts; and
secure circuitry to:
for each interrupt, track a latency between when the interrupt occurred and when the interrupt was processed;
for each interrupt, track an interval between consecutive occurrences of the interrupt; and
trigger, in response to both the latency exceeding a latency limit and the interval exceeding an interval limit, a latency alert and an interval alert, wherein:
the latency limit corresponds to a maximum length of time in which a processor different than and securely isolated from the secure circuitry and responsible for handling the interrupt is expected to handle the interrupt; and
the latency exceeding the latency limit indicates that the processor is impermissibly not handling the interrupt in a timely manner.