Patent ID: 11886832
Assignee: SIGMASTAR TECHNOLOGY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 3:
4. An operation method performed by an electronic apparatus, wherein the electronic apparatus comprising a quantizer circuit, a buffer circuit, a control circuit, a convolution core circuit and a multiply-add circuit; the operation method comprising:
performing, by the quantizer circuit, asymmetric uniform quantization on first feature data to obtain and store in the buffer circuit second feature data;
performing, by the quantizer circuit, symmetric uniform quantization on a first weighting coefficient to obtain and store in the buffer circuit a second weighting coefficient;
performing, by the convolution core circuit, a convolution operation on the second feature data and the second weighting coefficient according to an instruction of the control circuit to obtain an initial operation result; and
performing, by the multiply-add circuit, a multiply-add operation on the initial operation result, an actual quantization scale factor and an actual bias value to obtain a final operation result,
wherein the step of performing the multiply-add operation on the initial operation result, the actual quantization scale factor and the actual bias value to obtain the final operation result comprises:
receiving, by a trimming circuit, the initial operation result having a first bit width, and trimming, by the trimming circuit, the initial operation result having the first width into an initial operation result having a second bit width;
performing, by the multiply-add circuit, the multiply-add operation on the initial operation result having the second bit width, the actual quantization scale factor and the actual bias value to obtain the final operation result;
wherein, the first bit width is larger than the second bit width, and
wherein the step of performing the multiply-add operation on the initial operation result having the second bit width, the actual quantization scale factor and the actual bias value to obtain the final operation result further comprises:
receiving, by the trimming circuit, the actual bias value having the first bit width, and trimming, by the trimming circuit, the actual bias value having the first bit width into the actual bias value having the second width; and
performing, by the multiply-add circuit, the multiply-add operation on the initial operation result having the second bit width, the actual quantization scale factor and the actual bias value having the second width to obtain the final operation result.