Patent ID: 11907680
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. The MAC operator of claim 7,
wherein the negative number processing circuit includes 2's complement circuits and multiplexers,
wherein each of the 2's complement circuits outputs a 2's complement for one of the plurality of shifted mantissa data, and
wherein each of the multiplexers is configured to:
receive the one of the plurality of shifted mantissa data through a first input terminal, receive the 2's complement of the one of the plurality of shifted mantissa data through a second input terminal, and receive one of the plurality of sign data of the plurality of multiplication data through a control terminal, and
output the one of the plurality of shifted mantissa data as one of the plurality of intermediate mantissa data through an output terminal when the one of the plurality of sign data represents a positive number, and output the 2's complement of the one of plurality of the shifted mantissa data as one of the plurality of intermediate mantissa data through the output terminal when the one of the plurality of sign data represents a negative number.