Patent ID: 11895849
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A memory device, comprising:
a first memory cell disposed over a substrate, comprising:
a transistor, comprising:
a gate pillar structure;
a channel layer laterally wrapping around the gate pillar structure;
a source electrode surrounding the channel layer; and
a drain electrode surrounding the channel layer and separated from the source electrode by a dielectric layer therebetween; and

a data storage structure coupled to the transistor, comprising:
a data storage layer surrounding the channel layer, and sandwiched between a first electrode and a second electrode,

wherein the drain electrode of the transistor and the first electrode of the data storage structure share a common conductive layer.