Patent ID: 11868872
Assignee: AMAZON TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. An apparatus comprising:
a local memory;
a direct memory access (DMA) descriptor queue that stores DMA descriptors, each DMA descriptor including an indirect address;
an address translation table that stores an address mapping between indirect addresses and physical addresses;
a hardware processor coupled with the local memory and configured to execute a computation operation; and
a DMA engine configured to:
fetch a DMA descriptor from the DMA descriptor queue;
translate, using the address translation table and based on the address mapping, a first indirect address of the DMA descriptor to a first physical address of a host memory; and
perform a DMA operation based on executing the DMA descriptor to transfer input data from the first physical address of the host memory to the local memory to be operated on by the hardware processor during the computation operation.