Patent ID: 11936384
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 13:
14. A multi-bit flip-flop comprising:
a signal generation circuit configured to receive a clock signal, output the clock signal and an inverse clock signal, receive a scan enable signal, and output the scan enable signal and an inverse scan enable signal;
a first bit flip-flop; and
a second bit flip-flop,
wherein the first bit flip-flop comprises
a first input multiplexer configured to receive a first data bit as a data input, receive a second data bit as a scan input, and output one of the first data bit and the second data bit as a third data bit in response to the scan enable signal and the inverse scan enable signal,
a first transmission circuit configured to output a fourth data bit in response to the third data bit in synchronization with the clock signal and the inverse clock signal,
a first latch configured to store the fourth data bit in synchronization with the clock signal and the inverse clock signal,
a second transmission circuit configured to output a fifth data bit in response to the fourth data bit in synchronization with the clock signal and the inverse clock signal, and
a second latch configured to store the fifth data bit and output a sixth data bit as a first output data bit in response to the fifth data bit, and
wherein the second bit flip-flop comprises
a second input multiplexer configured to receive a seventh data bit as a data input, receive the sixth data bit as a scan input, and output one of the seventh data bit and the sixth data bit as an eighth data bit,
a third transmission circuit configured to output a ninth data bit in response to the eighth data bit in synchronization with the clock signal and the inverse clock signal,
a third latch configured to store the ninth data bit in synchronization with the clock signal and the inverse clock signal,
a fourth transmission circuit configured to output a tenth data bit in response to the ninth data bit in synchronization with the clock signal and the inverse clock signal, and
a fourth latch configured to store the tenth data bit and output an eleventh data bit as a second output data bit in response to the tenth data bit, and
wherein the first input multiplexer and the second input multiplexer respectively set the third data bit and the eighth data bit to a reset value in response to a reset signal.