Patent ID: 11910589
Assignee: ZENO SEMICONDUCTOR, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 5:
6. An integrated circuit comprising:
a semiconductor memory array comprising a plurality of semiconductor memory cells, wherein each of said semiconductor memory cells comprises:
a memory transistor comprising:
a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states;
a first insulating region located above said floating body region;
second insulating regions adjacent to said floating body region; and
a buried layer region located below said floating body region and said second insulating regions and spaced from said second insulating regions so as not to contact said second insulating regions;
wherein said floating body region is configured to be bounded by said first insulating region above said floating body region, said second insulating regions adjacent to said floating body region, and a depletion region formed as a result of an application of a back bias to said buried layer region;
wherein application of said back bias results in at least two stable floating body charge levels;

an access device comprising a body region, wherein said access device is connected in series to said memory transistor, and wherein said body region is configured to be isolated from said floating body region by said depletion region;
wherein said buried layer region is located underneath at least two of said memory cells; and

a control circuit configured to apply said back bias to said buried layer region.