Patent ID: 11901905
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 15:
16. A system comprising:
a set of data signal input circuits configured to receive a data signal and store the received data signal as a latched data signal;
a clock signal input circuit configured to receive a clock signal;
a set of clock paths that connect the clock signal input circuit to the set of data signal input circuits;
a set of input/output (IO) circuits on the clock paths between the data signal input circuit and the clock signal input circuit, the set of IO circuits are configured to receive, via the set of clock paths, local clock signals at different timings based a clock signal received at the clock signal input circuit; and
a set of multi-delay circuits that on the set of clock paths and connected between the set of data signal input circuits and the clock signal input circuit, each multi-delay circuit of the set of multi-delay circuits includes a first delay circuit that delays a respective local clock signal by a first delay time and a second delay circuit that delays the respective local clock signal by a second delay time, wherein the second delay time is shorter than the first delay time, wherein the set of multi-delay circuits are calibrated to apply the first and second delay time to the local clock signal for each IO circuit of the set of IO circuits based on the latched data signal to align clock edges of the set of local clock signals.