Patent ID: 11972973
Assignee: nan
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A method of manufacturing a semiconductor structure, comprising:
receiving a wafer having a conductive line of an Nth metal layer at a surface of the wafer, wherein N is equal to 1 or greater;
forming a first insulating layer on the surface of the wafer and free from covering a portion of the conductive line;
forming a first dielectric layer on the first insulating layer and free from covering the portion of the conductive line and a portion of the first insulating layer;
forming a second insulating layer on the first dielectric layer and the first insulating layer, wherein the second insulating layer comprises at least a base region over the portion of the conductive line and free from covering the portion of the conductive line;
forming an interconnect base in the base region, comprising:
forming a photoresist layer over the second insulating layer, wherein the base region of the second insulating layer is free from covered by the photoresist layer;
forming at least one conductive material over the photoresist layer, the second insulating layer, and the conductive line, wherein an upper surface of the conductive material over the conductive line is substantially coplanar with an upper surface of the second insulating layer; and
removing the conductive material over the second insulating layer by removing the photoresist layer to form the interconnect base;

forming a second dielectric layer over the second insulating layer;
forming a first conductive trace on the second insulating layer; and
forming an interconnect body on the interconnect base;
wherein the interconnect base is laterally surrounded by the first dielectric layer, the first insulating layer, and the second insulating layer;
wherein the interconnect body is isolated from the first conductive trace by the second dielectric layer; and
wherein the operation of forming the interconnect body on the interconnect base comprises:
forming a first barrier layer in direct contact with the interconnect base and sidewalls of the second dielectric layer;
forming a first copper-phosphorous alloy layer;
forming at least one conductive layer surrounded by the barrier layer, wherein the first copper-phosphorous alloy layer is sandwiched by the first barrier layer and the at least one conductive layer;
forming a second copper-phosphorous alloy layer on the at least one conductive layer; and
forming a second barrier layer on the second copper-phosphorous alloy layer.