Patent ID: 11928497
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. A system, comprising:
a processor; and
logic integrated with the processor, executable by the processor, or integrated with and executable by the processor, the logic being configured to:
receive a request to perform a transaction in persistent memory at a first node, the persistent memory having no fixed block size;
implement the transaction within a volatile transaction cache at the first node, the volatile transaction cache having a shadow copy of data stored in persistent memory at the first node, wherein write modifications made during the transaction are made directly on the shadow copy;
determine, at the first node, parity data for the transaction, wherein determining the parity data for the transaction includes:
determining modified volatile memory address locations in the volatile transaction cache that have been written during the transaction,
identifying first data at the modified volatile memory address locations in the volatile transaction cache,
identifying second data at corresponding persistent memory address locations in the persistent memory, and
performing one or more actions on the first data and the second data to obtain the parity data;

send the parity data from the first node to a parity node;
transfer results of the transaction from the volatile transaction cache to the persistent memory at the first node;
determine modified volatile memory address locations in the volatile transaction cache that have been written to during the transaction;
identify first data at the modified volatile memory address locations in the volatile transaction cache; and
identify second data at corresponding persistent memory address locations in the persistent memory,, wherein:
the first data within the modified volatile memory address locations is copied to corresponding persistent memory address locations in the persistent memory, utilizing a determined correlation,
pools of storage within the volatile transaction cache and the persistent memory are segmented into predetermined memory regions of a predetermined size,
updates to the parity node and data transfers to the persistent memory in the first node are performed in a kernel space, and
the persistent memory contains a completed transaction ID and a current transaction ID, wherein:
in response to an initiation of a copying of transaction results from the volatile transaction cache to the persistent memory, the current transaction ID is incremented at the persistent memory,
as each row within the persistent memory is updated from the volatile transaction cache, its associated row transaction ID is updated with the current transaction ID, and
in response to an updating of all rows associated with the transaction at the persistent memory, the completed transaction ID is updated with the current transaction ID.