Patent ID: 11888082
Assignee: DUAL HELIOS SEMICONDUCTOR EQUIPMENT COMPANY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 21:
22. A wafer processing method, comprising:
providing a frame comprising a frame opening, wherein a membrane with a membrane opening is coupled to the frame covering at least a part the frame opening, wherein a wafer is coupled to the membrane covering the membrane opening;
maintaining the frame, the membrane, and the wafer vertically;
forming a first I-layer over a first surface of the wafer while the wafer is oriented vertically;
forming a second I-layer over a second surface of the wafer while the wafer is oriented vertically, the second surface of the wafer being opposite from the first surface;
forming a N-layer over the first I-layer while the wafer is oriented vertically;
forming a P-layer over the second I-layer while the wafer is oriented vertically; and
providing texturing treatment for the wafer;
wherein the method further comprises, before the act of providing texturing treatment, coupling the membrane with a first isolation grid, wherein the first isolation grid is coupled to a first surface of the membrane.