Patent ID: 11863304
Assignee: UNM RAINFOREST INNOVATIONS
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A method for performing by a field programmable gate array (FPGA) dynamic partial reconfiguration (DPR) for a countermeasure to a side-channel attack to a computer system, the method comprising steps of:
providing an encryption hardware engine comprising hardware components or hardware sub-components, one or more redundant locations, and an encryption algorithm,
using the one or more redundant locations to disconnect from the encryption hardware engine within the FPGA one or more hardware components or hardware sub-components of the encryption hardware engine and randomly changing implementation characteristics of the one or more disconnected hardware components or disconnected hardware sub-components of the encryption hardware engine to produce replicated components, wherein the one or more redundant locations allow the encryption hardware engine to run without stalls while DPR is performed on the one or more redundant locations disconnected from the FPGA,
running connected one or more hardware components or the connected hardware sub-components simultaneously and in parallel with the replicated components to change a behavior of the FPGA to provide the countermeasure to the side-channel attack to the computer system.