Patent ID: 11947801
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus comprising:
a processor to:
receive data, via a network interface card (NIC) of a hardware accelerator device, as part of data transfer from an application of remote application server platform;
identify a destination address of memory of the hardware accelerator device to write the data;
determine that access control bits of the destination address in page tables maintained by a memory management unit (MMU) indicate that memory pages of the destination address are both registered and free;
in response to the access control bits indicating that the memory pages of the destination address are both registered and free, write the data to the memory pages of the destination address; and
subsequent to writing the data to the memory pages, update the access control bits for the memory pages of the destination address to indicate that the memory pages are restricted, wherein setting the access control bits to restricted prevents the NIC and a compute kernel of the hardware accelerator device from accessing the memory pages.