Patent ID: 11961806
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 14:
15. A semiconductor device, comprising:
a substrate including a first region and a second region;
a device isolation layer defining a first active region on the first region and a second active region on the second region;
a pair of first source/drain patterns and a pair of second source/drain patterns on the first active region and the second active region, respectively;
a first channel pattern between the pair of first source/drain patterns;
a second channel pattern between the pair of second source/drain patterns, each of the first and second channel patterns comprising first to third semiconductor patterns sequentially stacked on the substrate;
a first gate electrode and a second gate electrode on the first channel pattern and the second channel pattern, respectively;
a first gate insulating layer between the first channel pattern and the first gate electrode;
a second gate insulating layer between the second channel pattern and the second gate electrode;
a pair of gate spacers provided at opposite sides of each of the first and second gate electrodes;
a gate capping pattern on a top surface of each of the first and second gate electrodes;
a pair of first active contacts electrically connected to the pair of first source/drain patterns;
a pair of second active contacts electrically connected to the pair of second source/drain patterns;
first and second gate contacts electrically connected to the first and second gate electrodes;
a first metal layer on the pair of first active contacts, the pair of second active contacts, and the first and second gate contacts, the first metal layer comprising first interconnection lines electrically connected to the pair of first active contacts, the pair of second active contacts, and the first and second gate contacts;
a second metal layer on the first metal layer; and
a first supporting pattern, which is provided on side surfaces of the first to third semiconductor patterns of the first channel pattern and is in contact with the first to third semiconductor patterns thereof,
wherein the first supporting pattern comprises:
a first vertical portion and a second vertical portion, which are provided on the first active region and are extended from a top surface of the device isolation layer to a top surface of the third semiconductor pattern, and
a connecting portion, which is in contact with the top surface of the third semiconductor pattern and connects the first vertical portion to the second vertical portion,

wherein the first vertical portion and the second vertical portion are spaced apart from each other with the first to third semiconductor pattern of the first channel pattern interposed therebetween.