Patent ID: 11914511
Assignee: APPLE INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A processor comprising:
a data cache; and
a load/store unit coupled to the data cache and configured to execute memory operations, wherein the load/store unit comprises a store queue configured to queue one or more store memory operations that have been executed and are awaiting commit to the data cache, and wherein the load/store unit is configured to access the store queue and the data cache during execution of a load memory operation, wherein the load memory operation has an operation size that specifies an amount of data read by the load memory operation, and wherein the load/store unit implements an atomicity size for compliance with a memory ordering model employed by the processor, wherein the atomicity size is smaller than the operation size for the load memory operation, wherein data read by the load memory operation comprises a plurality of atomic elements of the atomicity size, and wherein an execution of the load memory operation complies with the memory ordering model when a given atomic element of the plurality of atomic elements is read from a single source of a plurality of sources that includes a store memory operation in the store queue and a cache line in the data cache.