Patent ID: 11876043
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A semiconductor device comprising:
a substrate including:
a chip region; and
a scribe lane region surrounding the chip region, the scribe lane region having first edges opposite to each other and second edges opposite to each other, each of the first edges extending in a first direction and each of the second edges extending in a second direction crossing the first direction,

the substrate having first and second active patterns on the chip region and the scribe lane region, the first and second active patterns being defined by an isolation pattern on the substrate;
a gate structure provided at an upper portion of the first active pattern;
a bit line structure on the chip region of the substrate;
a first contact plug on the first active pattern;
a capacitor on the first contact plug;
a second contact plug on the capacitor;
a third contact plug on the second active pattern;
a first insulating interlayer containing the second and third contact plugs;
a second insulating interlayer structure on the first insulating interlayer;
conductive structures on a portion of the scribe lane region of the substrate adjacent to one of the first edges, each of the conductive structures extending through the second insulating interlayer structure in a vertical direction substantially perpendicular to an upper surface of the substrate and extending in the first direction;
a third insulating interlayer on the second insulating interlayer structure, the third insulating interlayer including a material having a dielectric constant greater than that of the second insulating interlayer structure;
first vias on the scribe lane region of the substrate, each of the first vias extending in the first direction through the third insulating interlayer and at least a portion of the second insulating interlayer structure to contact one of the conductive structures on the scribe lane region of the substrate, and each of the first vias directly contacting the portion of the second insulating interlayer structure; and
a first wiring commonly contacting upper surfaces of the first vias,
wherein each of the conductive structures includes second wirings and second vias alternately and repeatedly stacked in the vertical direction, and an uppermost one of the second wirings contacts a corresponding one of the first vias, and
wherein the second wirings on the respective second vias at a same level do not contact each other.