Patent ID: 11934824
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 14:
15. The method of claim 14, further comprising:
loading, via the number of bit lines of the memory array of the memory device, a number of bit groups of a second row into the array of the memory device;
multiplying each bit of each bit group of the number of bit groups of the second row by a first bit of a second operand of the number of operands to generate a second scaled row; and
multiplying each bit of each bit group of the number of bit groups of the second row by at least one additional bit of the second operand of the number of operands to generate one or more additional scaled rows;
wherein generating the number of bits of the row of an output matrix comprises generating the number of bits of the row based at least partly on the first scaled row, the second scaled row, and the one or more additional scaled rows.