Patent ID: 11934686
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A memory subsystem comprising:
a plurality of memory devices, wherein a first region of the memory subsystem comprises one or more first memory devices of the plurality of memory devices and a second region of the memory subsystem comprises one or more second memory devices of the plurality of memory devices; and
a processing device coupled to each of the plurality of memory devices, the processing device to perform operations comprising:
detecting that a media management operation is to be performed at the one or more first memory devices of the first region of the memory subsystem;
determining whether a sequence at which data items were programmed across the one or more first memory devices corresponds to a target sequence associated with accessing host data via the first region, wherein the target sequence corresponds to a sequence that enables a plurality of host data items programmed to the memory subsystem to be accessed in parallel;
responsive to determining that the sequence at which the data items were programmed does not correspond to the target sequence, determining a sequence for copying the data items across the one or more second memory devices of the second region, wherein the determined sequence corresponds to the target sequence;
copying the data items from the one or more first memory devices of the first region to the one or more second memory devices of the second region in view of the determined sequence; and
accessing the data items via the one or more second memory devices in accordance with the target sequence.