Patent ID: 11914998
Assignee: REALTEK SEMICONDUCTOR CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A processor circuit, comprising:
an instruction decode unit, configured to decode a first load instruction included in a plurality of load instructions to generate a first decoding result;
an instruction detector, coupled to the instruction decode unit, the instruction detector being configured to generate an indication signal by detecting if the load instructions use a same register;
an address generator, coupled to the instruction decode unit, the address generator being configured to generate a first address requested by the first load instruction according to the first decoding result; and
a data buffer, coupled to the instruction detector and the address generator, the data buffer being configured to selectively store the first address generated by the address generator according to the indication signal, wherein when the indication signal indicates the first load instruction is one of the load instructions using the same register, the data buffer is configured to store the first address generated from the address generator, and store data requested by the first load instruction according to the first address.