Patent ID: 11894341
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A semiconductor package, comprising:
semiconductor dies, comprising conductive posts;
an encapsulant, wrapping the semiconductor dies while leaving exposed top surfaces of the conductive posts; and
a redistribution structure, comprising:
an elevation tier, disposed directly on the encapsulant and comprising an elevation dielectric layer and elevation vias, wherein the elevation dielectric layer extends on the encapsulant and the semiconductor dies, the elevation vias extend through the elevation dielectric layer, and the elevation vias have one end in physical contact with the conductive posts of the semiconductor dies;
elongated pads disposed on the elevation dielectric layer and connected to a corresponding one elevation via of the elevation vias, wherein the elongated pads have one end in physical contact with the corresponding elevation via and another end extending on the elevation dielectric layer; and
alternately stacked interconnection dielectric layers and interconnection patterns disposed on the elevation tier and the elongated pads, wherein the interconnection patterns comprise routing vias extending through the interconnection dielectric layers and routing lines connected to the routing vias and lying on the interconnection dielectric layers, a first interconnection dielectric layer of the interconnection dielectric layers lies directly on the elevation dielectric layer, and first routing vias of the routing vias extending through the first interconnection dielectric layer land on the other ends of the elongated pads at a distance from the elevation vias.