Patent ID: 11922295
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 33:
34. The arithmetic device of claim 30, wherein the calibrated output distribution signal generator circuit includes:
a multiplier circuit configured to multiply the arithmetic result signal by the first bit set of the output distribution signal;
an adder circuit configured to add the second bit set of the output distribution signal to an output signal of the multiplier circuit to generate a calibration signal;
a first selected output distribution signal extractor circuit configured to generate a first selected output distribution signal from the third bit set of the output distribution signal based on the calibration signal;
a second selected output distribution signal extractor circuit configured to generate a second selected output distribution signal based on the arithmetic result signal and an activation function information signal; and
a calibrated output distribution signal selector circuit configured to select and output one of the first selected output distribution signal and the second selected output distribution signal as the calibrated output distribution signal based on the arithmetic result signal.