Patent ID: 11894060
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 16:
17. A system, comprising:
a memory controller configured to receive data write commands from a host and to internally generate background write commands; and
a plurality of non-volatile memory devices configured to receive and execute commands from the memory controller, each of the non-volatile memory devices comprising:
one or more arrays non-volatile of memory cells, each array comprising a plurality of blocks each of a plurality of the non-volatile memory cells; and
one or more control circuits connected to the one or more arrays and configured to:
receive a write command to program a first set of data to a first of the one or more arrays in a first format;
determine whether the write command is a data write command from the host;
in response to determining that the write command is a write command from the host, write the first set of data into the first array in the first format using a first programming algorithm;
determine whether the write command is a background write command; and
in response to determining that the write command is a background write command, write the first set of data into the first array in the first format using a second programming algorithm, the second programming algorithm being of a slower write speed than the first programming algorithm.