Patent ID: 11916058
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 16:
17. A method, comprising:
arranging a plurality of input stage cells in a plurality of first rows each having a first row height; and
arranging a plurality of data cells in a plurality of second rows each having a second row height different from the first row height, wherein the plurality of input stage cells and the plurality of data cells are interlaced with each other,
wherein a first data cell, corresponding to a first bit of M bits in a multi-bit cell, in the plurality of data cells is configured to output a first bit data as an output signal to a first input stage cell, corresponding to a second bit, in the plurality of the input stage cells, wherein M is a positive integer.