Patent ID: 11959959
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Measurement (Instruments)
Classification: CPC G | IPC G

Claim 7:
8. A bum in board test system, comprising:
a clock generator which generates a clock;
a Device Under Test (DUT) tester connected to a plurality of devices under test through a first channel to test the plurality of devices under test;
a plurality of clock switches which transmit the clock to the plurality of devices under test and including a first clock switch and a second clock switch;
a plurality of DUT switches connected between the plurality of devices under test and the DUT tester; and
a plurality of resistors connected between the plurality of devices under test and the DUT tester,
wherein the plurality of devices under test include a first device under test directly connected to the first clock switch and a second device under test directly connected to the second dock switch,
Wherein a first DUT switch of the plurality of DUT switches connected to the first device under test shorts a sub channel connecting the first device under test to the first channel when the first device under test is tested.