Patent ID: 11876000
Assignee: NANYA TECHNOLOGY CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for preparing a semiconductor device structure, comprising:
forming a target layer over a semiconductor substrate;
forming an energy-sensitive layer over the target layer;
forming a first patterned hard mask on the energy-sensitive layer, wherein the first patterned hard mask has a first through opening to expose a first portion of the energy-sensitive layer;
performing a first energy treating process to form a first treated portion in the energy-sensitive layer at the first portion thereof through the first through opening of the first patterned hard mask;
removing the first patterned hard mask after the first treated portion is formed;
forming a second patterned hard mask on the energy-sensitive layer to cover the first treated portion, wherein the second patterned hard mask has a second through opening to expose a second Portion of the energy-sensitive layer;
performing a second energy treating process to form a second treated portion in the energy-sensitive layer at the second portion thereof through the second through opening of the second patterned hard mask;
removing the second patterned hard mask after the second treated portion is formed;
removing the first treated portion and the second treated portion to form a first opening and a second opening in the energy-sensitive layer, wherein the first opening and the second opening are two separated openings and are spaced apart from each other, wherein each of the first opening and the second opening has a uniform width; and
transferring the first opening and the second opening into the target layer.