Patent ID: 11862260
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 9:
10. A memory system, comprising:
a plurality of memory blocks including an open memory block comprising one or more wordlines containing data and one or more erased wordlines; and
a memory controller, wherein the memory controller is configured to:
apply a pass-through voltage to each wordline that contains data in the open memory;
apply an audit verify voltage to each erased wordline in the open memory block;
determine a bit count indicative of a read disturb level of the one or more erased wordlines;
determine whether the bit count exceeds a threshold value; and
determine whether to continue operation of the open memory block based at least in part on whether the bit count exceeds the threshold value.