Patent ID: 11923298
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A method of fabricating a semiconductor device, the method comprising:
patterning a substrate to form a peripheral active pattern in a peripheral region;
forming a peripheral gate electrode on the peripheral active pattern;
forming a gate spacer on a sidewall of the peripheral gate electrode;
forming a peripheral source/drain pattern in the peripheral active pattern;
forming a gate capping pattern on the peripheral gate electrode, a topmost end of the peripheral gate electrode being interposed between the gate capping pattern and the gate spacer;
forming a first interlayer insulating layer on the peripheral source/drain pattern;
forming a peripheral active contact that penetrates the first interlayer insulating layer and connects to the peripheral source/drain pattern;
forming an insulating structure that covers a top surface of the gate capping pattern, the topmost end of the peripheral gate electrode, and a top surface of the gate spacer; and
forming an interconnection line on the peripheral active contact and the insulating structure.