Patent ID: 11868244
Assignee: QUALCOMM INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 24:
25. The compressed memory system of claim 16, wherein the cache line packing circuit is further configured to:
in response to receiving a cache line write request for the second cache line:
compress the second cache line to obtain a second updated cache line of a second size;
in accordance with a determination that a sum of the second size and the size of the first compressed cache line is less than a first predetermined size of the candidate compressed cache line, perform a read-modify-write operation to write the second updated cache line to the candidate compressed cache line; and
in accordance with a determination that the sum of the second size and the size of the first compressed cache line is not less than the first predetermined size of the candidate compressed cache line, perform (i) a first read-modify-write operation to write a first portion of the second updated cache line to the candidate compressed cache line, and (ii) a second read-modify-write operation to write a remaining portion of the second updated cache line to the overflow block pointed to by the overflow pointer.