Patent ID: 11966625
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. A memory device, comprising:
a cell array including a plurality of cell blocks, each including a plurality of pages; and
a control logic configured to control a program and read operation on the cell array, wherein:
first to Nth IDR data pairs (N is an integer of 2 or more) are stored in the cell array,
each of the first to Nth IDR data pairs includes information data read (IDR) data, including information related to a setting operation of the memory device, and replica IDR data, including inverted bit values of the IDR data, and
the control logic is configured to:
perform a recovery operation for repairing errors in the IDR data based on at least one IDR data pair among the first to Nth IDR data pairs;
read the replica IDR data of the first IDR data pair when a read fail occurs in the IDR data of the first IDR data pair, and
repair the errors in the IDR data by using the replica IDR data of the first IDR data pair when a read fail does not occur in the replica IDR data of the first IDR data pair;
when the read fail occurs in the replica IDR data of the first IDR data pair, repair the errors in the IDR data by reading the first to Nth IDR data pairs;
determine bit values of bits included in the IDR data from each of the first to Nth IDR data pairs, and
based on a majority rule with respect to the bit values determined from the first to Nth IDR data pairs, repair the errors in the IDR data.