Patent ID: 11907136
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus, comprising:
a memory device including memory locations; and
hardware logic coupled to the memory device to:
identify a table that includes indications of a plurality of memory ranges, indications of a plurality of temporal ranges, and indications of a plurality of data invalidation techniques, wherein:
respective ones of the plurality of temporal ranges and respective ones of the plurality of data invalidation techniques correspond to respective ones of the plurality of memory ranges;
respective memory ranges are an address range that correspond to a plurality of the memory locations in the memory device; and
respective temporal ranges are a time range during which data stored in the respective memory ranges is valid according to a data aging policy;

identify, based on an identification that a time value is outside of a temporal range of the plurality of temporal ranges, that the data in a corresponding memory range of the plurality of memory ranges is expired; and
invalidate, based on a data invalidation technique that corresponds to the temporal range and the memory range, the expired data in the memory range.