Patent ID: 11861403
Assignee: NXP USA, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A thread management circuit coupled with a processor core and an accelerator circuit for thread management, the thread management circuit comprising:
a memory element configured to store a thread identifier table and a thread completion table, wherein the thread identifier table has first groups of entries and second groups of entries, one of the first groups and second groups corresponding to rows of the thread identifier table and another of the first groups and second groups corresponding to columns of the thread identifier table, the associations of processing cores and thread identifiers to the respective first group and second group in the thread identifier table being predefined and the thread identifier table indicates for each processing core of the plurality of processing cores one of a first bit indication that a first thread identifier is allocated for the respective processing core and a second bit indication that the first thread identifier is not allocated for the respective processing core and wherein the thread completion table has third groups of entries and fourth groups of entries, one of the third groups and fourth groups corresponding to rows of the thread completion table and another of the third groups and fourth groups corresponding to columns of the thread completion table, each third group associated with a respective processing core of the plurality of processing cores and each fourth group associated with a respective thread identifier of a plurality of thread identifiers, the associations of processing cores and thread identifiers in the thread completion table to the respective third group and fourth group in the thread completion table being predefined and the thread completion table indicates for each processing core of the plurality of processing cores one of a third bit indication that execution of a first portion of the first thread identifier is not complete for the respective processing core and a fourth bit indication that execution of the first portion of the first thread identifier is complete for the respective processing core; and
processing circuitry coupled to the memory element and configured to:
receive, from the processor core, a first request for execution of flail the first portion of an application by the accelerator circuit, wherein the processing core executes another portion of the application based on sending the first request;
allocate, based on the received first request and the first thread identifier of the processing core indicated by the thread identifier table being associated with the second bit indication, the first thread identifier to the processor core for the execution of the first portion by the accelerator circuit and update the second bit indication associated with the first thread identifier to the first bit indication;
communicate, based on the allocation of the first thread identifier, a first response to the processor core, wherein the first response includes the allocated first thread identifier;
communicate a first acceleration request including the first thread identifier to the accelerator circuit for the execution of the first portion;
receive, from the processor core, a thread joining request after the reception of the first request, wherein the processing core halts the execution of the other portion of the application in response to the sending of the thread joining request and until a result of the thread joining request is received; and

communicate, to the processor core, a thread joining response including the first thread identifier based on the thread joining request, wherein the thread joining response is communicated to the processor core based on the fourth indication by the thread completion table that the execution of the first portion by the accelerator circuit is complete, and wherein the executed first portion is integrated with the application, based on the thread joining response, wherein the processing core integrates at least two portions of the application executed by the accelerator circuit;
wherein the processor core, the accelerator circuit, and the thread management circuit are directly coupled to a common communication bus.