Patent ID: 11907134
Assignee: RADIAN MEMORY SYSTEMS, LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. The memory controller of claim 1 wherein the programmably-defined address mapping parameter comprises one of:
a number of pages within a same erase unit to which respective ones of the respective sequentially-received write requests are to be directed before an ensuing, sequentially-received write request is to be also directed to the number of pages;
a number of erase units within a same die to which respective ones of respective sequentially-received write requests are to be directed before an ensuing, sequentially-received write request is to be also directed to the number of erase units; and
a number of dies to which respective ones of the respective sequentially-received write requests are to be directed before an ensuing, sequentially-received write request is to be also directed to the number of dies.