Patent ID: 11948842
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A device, comprising:
a substrate;
semiconductor fins over the substrate;
an etch stop layer over the substrate and laterally between lower portions of two adjacent semiconductor fins;
an isolation structure over the etch stop layer and laterally between the lower portions of the two adjacent semiconductor fins, wherein the semiconductor fins extend above a top surface of the isolation structure;
a gate dielectric layer over the isolation structure and the semiconductor fins;
a conductive layer over the gate dielectric layer; and
a dielectric feature penetrating through the conductive layer, the gate dielectric layer, and the isolation structure and reaching the etch stop layer, wherein the etch stop layer and the isolation structure include different materials.