Patent ID: 11942552
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 0:
1. A semiconductor device comprising:
a first gate-all-around field effect transistor (GAA FET) and a second GAA FET; and
a wall fin disposed between the first GAA FET and the second GAA FET and disposed on an isolation insulating layer, wherein:
the first and second GAA FETs include semiconductor wires or sheets, a gate dielectric layer wrapping around channel regions of the semiconductor wires or sheets, a gate electrode on the gate dielectric layer and a source/drain epitaxial layer,
the wall fin includes a first dielectric layer, a second dielectric layer disposed over the first dielectric layer and a third dielectric layer,
the first, second and third dielectric layers are made of different materials from each other,
the third dielectric layer includes a dielectric material having a dielectric constant higher than the first and second dielectric layers and the isolation insulating layer, and
a fourth dielectric layer different from the first, second and third dielectric layers is disposed on the source/drain epitaxial layer.