Patent ID: 11922011
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A system comprising
one or more memory devices; and
a processing device coupled to each of the one or more memory devices, the processing device to perform operations comprising:
receiving a request to perform a memory access operation to access a data item stored at the one or more memory devices, wherein the memory access operation comprises at least one of a read operation or a write operation;
responsive to identifying, in a logical-to-physical (L2P) table associated with the one or more memory devices, an entry that corresponds a logical address associated with the data item of the received request, obtaining an identifier for a set of virtual management units (MUs) associated with the one or more memory devices from the identified entry, wherein the set of virtual MUs correspond to one or more block stripes across the one or more memory devices;
identifying, in a virtual MU data structure, a record mapping the set of virtual MUs to a physical address associated with a portion of the one or more memory devices that stores the data item of the received request; and
performing the memory access operation using the physical address to access the data item stored at the one or more memory devices in accordance with the request.