Patent ID: 11960408
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. A semiconductor memory device comprising:
a unit page buffer block including four page buffer pairs arranged in a column direction,
wherein each of the four page buffer pairs comprises:
a common column decoder block; and
an upper page buffer stage and a lower page buffer stage, each electrically and commonly connected to the common column decoder block,
wherein the upper buffer stage comprises:
an upper selection block;
an upper latch block; and
an upper cache block,
wherein the lower buffer stage comprises:
a lower selection block;
a lower latch block; and
a lower cache block,
wherein:
the upper selection block includes a plurality of upper sub-selection blocks arranged in a row direction, and each of the plurality of upper sub-selection blocks includes a plurality of upper unit selection blocks,
the upper latch block includes a plurality of upper sub-latch blocks arranged in the row direction,
the upper cache block includes a plurality of upper sub-cache blocks arranged in the row direction,
each of the plurality of upper unit selection blocks, each of the plurality of upper sub-latch blocks, and each of the plurality of upper sub-cache blocks are electrically connected to each other,
the lower selection block includes a plurality of lower sub-selection blocks arranged in the row direction, and each of the plurality of lower sub-selection blocks includes a plurality of lower unit selection blocks,
the lower latch block includes a plurality of lower sub-latch blocks arranged in the row direction,
the lower cache block includes a plurality of lower sub-cache blocks arranged in the row direction, and
each of the plurality of lower unit selection blocks, the plurality of lower sub-latch blocks, and each of the lower sub-cache blocks are electrically connected to each other.