Patent ID: 11862628
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 12:
13. A method, comprising:
forming first circuitry for accessing a plurality of memory cells, the first circuitry comprising a first plurality of transistors formed at least in part by doping portions of a first semiconductor substrate;
forming the plurality of memory cells according to a stack of decks of memory cells above the first semiconductor substrate;
bonding a second semiconductor substrate above the stack of decks of memory cells;
forming second circuitry for accessing the plurality of memory cells, the second circuitry comprising a second plurality of transistors formed at least in part by doping portions of the second semiconductor substrate after bonding the second semiconductor substrate above the stack of decks of memory cells; and
forming, after bonding the second semiconductor substrate above the stack of decks of memory cells, first interconnect circuitry associated with the plurality of memory cells, wherein the first interconnect circuitry couples one or more subsets of transistors of first plurality of transistors of the first circuitry with one or more subsets of transistors of second plurality of transistors of the second circuitry.