Patent ID: 11966739
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 18:
19. A method of operating an apparatus comprising a register file comprising a plurality of data registers, the method comprising:
controlling, in response to an issued instruction, processing circuitry to perform a processing operation to process an input data item to generate an output data item,
wherein
in response to a first encoding of the issued instruction specifying a data register of the plurality of data registers, the controlling comprises at least one of:
reading the input data item for the processing operation from the data register; and
writing the output data item generated in the processing operation to the data register; and

in response to a second encoding of the issued instruction specifying a buffer-region of the register file for storing a queue of data items, the controlling comprises controlling the processing circuitry to perform the processing operation and at least one of:
performing a dequeue operation to dequeue the input data item for the processing operation from the queue; and
performing an enqueue operation to enqueue the output data item generated in the processing operation to the queue.