Patent ID: 11948656
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory system, comprising:
a first row of memory cells that includes a set of memory cells for storing a value of a counter associated with the first row of memory cells, the set of memory cells comprising a first subset and a second subset; and
processing circuitry coupled with the first row of memory cells and comprising a plurality of multiplexers, wherein the processing circuitry is configured to cause the memory system to:
output, during a first testing operation, at least one bit of the first subset from a first multiplexer of the plurality of multiplexers to a second multiplexer of the plurality of multiplexers based at least in part on the first row of memory cells being activated a first quantity of times;
generate a first flag indicating an error condition of the first subset based at least in part on outputting the at least one bit of the first subset from the first multiplexer to the second multiplexer; and
configure the plurality of multiplexers to use the second subset to store the value of the counter and to refrain from using the first subset to store the value of the counter based at least in part on the first flag.