Patent ID: 11909841
Assignee: INTEL CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A system comprising:
a system on chip comprising:
a network interface circuit (NIC) to receive incoming messages from a plurality of distributed edge devices, the incoming messages comprising metadata including priority information and granularity information, the NIC comprising a pending request queue to store at least some of the incoming messages based at least in part on the priority information;
a first interface circuit coupled to the NIC, the first interface circuit to receive the incoming messages from the NIC, wherein the first interface circuit is to store at least some of the incoming messages in a merging queue, the first interface circuit to merge at least two of the incoming messages into a merged message; and
a target circuit coupled to the first interface circuit, wherein the target circuit is to process the at least two of the incoming messages of the merged message, wherein the first interface circuit is coupled to the target circuit via a Peripheral Component Interconnect Express (PCIe) interconnect, wherein the merged message has a width substantially equal to a width of the PCIe interconnect, and the at least two incoming messages have a width substantially less than the width of the PCIe interconnect.