Patent ID: 11864387
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. A method used in forming a memory array comprising strings of memory cells, comprising:
forming a stack over a conductor tier, the stack comprising vertically-alternating first tiers and second tiers;
forming a plurality of channel openings extending through the stack;
forming channel material within the plurality of channel openings, the channel material being in direct physical contact with a conductive material of the conductor tier;
forming horizontally-elongated trenches into the stack to form laterally-spaced memory-block regions, the memory-block regions comprising part of a memory-plane region; and
forming a pair of elevationally-extending walls that are laterally-spaced relative one another and that are individually horizontally-longitudinally-elongated, the pair of walls being in a region that is edge-of-plane relative to the memory-plane region.