Patent ID: 11880319
Assignee: NETLIST, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory subsystem operable with a system memory controller of a host system, comprising:
dynamic random access memory elements on a printed circuit board and configurable to communicate data signals with the system memory controller; and
a memory subsystem controller on the printed circuit board and coupled to the dynamic random access memory elements, the memory subsystem controller having an open drain output, wherein the memory subsystem is configured to provide a first signaling interface via the open drain output during normal operations and a second signaling interface via the open drain output during an initialization operation including initialization operation sequences, wherein the second signaling interface is distinct from the first signaling interface and the initialization operation is distinct from any of the normal operations;
wherein, during the normal memory read or write operations, the memory subsystem controller is configured to receive address and command signals associated with the memory read or write operations and to control the dynamic random access memory elements in accordance with the address and command signals, and the memory subsystem controller is further configured to output via the open drain output a parity error signal in response to a parity error having occurred during the normal memory read or write operations; and
wherein, during the initialization operation, the memory subsystem controller is configured to output via the open drain output a signal related to one or more parts of the initialization operation sequences.