Patent ID: 11860734
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 8:
9. The semiconductor memory device of claim 8, wherein:
the main data comprises a plurality of data bits divided into a plurality of sub data units;
the ECC is represented by a parity check matrix that comprises a plurality of column vectors and a plurality of parity vectors which are divided into a plurality of code groups corresponding to the sub data units and the first parity data; and
the control logic circuit, in response to the poison mode signal designating the poison mode, is configured to:
don't care process a row associated with a first parity bit of the first parity data among a plurality of rows of the parity check matrix that comprises a plurality of column vectors and a plurality of parity vectors; and
change a first parity vector associated with the first parity bit among the plurality of parity vectors such that elements of the first parity vector are not overlapped with elements of each of the plurality of column vectors and elements of second parity vectors among the plurality of parity vectors except the first parity vector to generate a modified parity check matrix.