Patent ID: 11966287
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. The memory device of claim 10, further comprising:
a plurality of second rows coupled with the one or more processors, wherein the one or more processors are further configured to cause the memory device to:
initiate a second scrub operation on the plurality of second rows;
determine whether to perform the initiated second scrub operation using the first error control mode or using the second error control mode; and
perform the second scrub operation based at least in part on determining to perform the second scrub operation using the second error control mode, wherein performing the second scrub operation comprises comparing second data stored in each row of the plurality of second rows with third error control information to correct single-bit errors in the second data of each row of the plurality of second rows.