Patent ID: 11973056
Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
Field: Surface technology, coating (Chemistry)
Classification: CPC H  C | IPC H

Claim 0:
1. A method of making an assembly, comprising:
juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate, the first surface of the first substrate and the major surface of the second surface each comprising a dielectric material, wherein one or both of: (a) the top surface of the first conductive element is recessed below the first surface of the first substrate, and/or (b) the top surface of the second conductive element is recessed below the major surface of the second substrate, and further wherein electrically conductive nanoparticles are disposed between barrier materials on the top surfaces of the first and second conductive elements, the conductive nanoparticles having long dimensions smaller than 100 nanometers;
directly bonding the dielectric material of the first surface with the dielectric material of the major surface; and
heating the first and second conductive elements such that metallurgical joints form between the juxtaposed first and second conductive elements.