Patent ID: 11874734
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 3:
4. A memory, comprising:
a memory core;
an error correction circuit suitable for correcting an error of data that are read from the memory core based on an error correction code that is read from the memory core;
an error check operation control circuit suitable for checking an error in data that are stored in the memory core by using the error correction circuit during an error check operation;
a bad region classification circuit suitable for classifying a bad region based on errors detected during the error check operation; and
an error check address generation circuit suitable for
generating an error check address to be used for the error check operation and increasing the error check address by 1 step for each error check operation, and
decreasing, when the bad region is newly detected, the error check address by N steps, where N is an integer equal to or greater than 1.