Patent ID: 11894069
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. A method comprising:
causing a drain select (SGD) transistor coupled with a bit line to be turned on while ramping a plurality of wordlines, which are coupled with gates of a string of memory cells, from a ground voltage to a pass voltage associated with unselected wordlines in preparation for a read operation;
causing a source select (SGS) transistor coupled with a source voltage line to be turned on while ramping the plurality of wordlines, wherein the string of memory cells is coupled between the SGD transistor and the SGS transistor and belong to an unselected sub-block;
causing, while ramping the plurality of wordlines, a channel of the string of memory cells to be pre-charged by ramping voltages on the bit line and the source voltage line to a target voltage that is greater than a source read voltage level; and
in response to the plurality of wordlines reaching the pass voltage:
causing the SGD and SGS transistors to be turned off, to leave the channel pre-charged to the target voltage during the read operation; and
causing the source voltage line to be discharged to the source read voltage level after the SGS transistor is turned off.