Patent ID: 11881260
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 18:
19. A method of designing a neuromorphic computing device, the method comprising:
designing structures of a first memory cell array, a second memory cell array and an analog-to-digital converting circuit included in the neuromorphic computing device; and
determining a resistance of at least one offset resistor included in the second memory cell array,
wherein the first memory cell array includes a plurality of resistive memory cells, is configured to store a plurality of data, is configured to generate a plurality of read currents based on a plurality of input signals and the plurality of data, and is configured to output the plurality of read currents through a plurality of bitlines or a plurality of source lines,
wherein the second memory cell array includes a plurality of reference resistive memory cells and the at least one offset resistor, and is configured to output at least one reference current through at least one reference bitline or at least one reference source line,
wherein the analog-to-digital converting circuit is configured to convert the plurality of read currents into a plurality of digital signals based on the at least one reference current, and
wherein the at least one offset resistor is connected between the at least one reference bitline and the at least one reference source line.