Patent ID: 11863477
Assignee: INTEL CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 5:
6. An apparatus to be implemented in a user equipment (UE), the apparatus comprising:
a memory to store configuration information for discovery reference signal (DRS) occasions;
a processor circuitry coupled to the memory, the processor circuitry to:
measure DRSs transmitted within the DRS occasions;
update an out-of-sync (OOS) counter in response to a listen-before-talk failure associated with the DRS transmissions;
measure a DRS quality metric associated with one or more signals from one DRS occasion;
map the measured DRS quality metric into a hypothetical physical downlink control channel (PDCCH) block error rate (BLER) value; and
increment the OOS counter in response to the hypothetical PDCCH BLER value exceeding a predetermined threshold.