Patent ID: 11876979
Assignee: MITSUBISHI ELECTRIC CORPORATION
Field: Audio-visual technology (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An image decoding circuit comprising:
a processor to execute a program; and
a memory to store the program which, when executed by the processor, the processor performs processes of:
carrying out an intra-frame prediction process on each of processing blocks to generate an intra prediction image, each of the processing blocks being a coding block or a sub-block obtained by dividing the coding block, and
carrying out a motion-compensated prediction process on a partition of the coding block or a sub-block to generate an inter prediction image;
wherein, when an intra-prediction parameter indicates a horizontal prediction process and a size of the processing block is less than a predetermined size, said processor adds a value to a signal value of a pixel adjacent to left of said processing block and outputs a result of the addition as a predicted value of said prediction image, the value being proportional to an amount of change in a horizontal direction of signal values of pixels adjacent to top of said processing block, and when the intra prediction parameter indicates a horizontal prediction process and the size of the processing block is greater than or equal to the predetermined size, said processor outputs the signal value of the pixel adjacent to left of the processing block as the predicted value of the prediction image;
wherein said decoding circuit obtains reference image from a frame memory storing reference image used to generate said inter prediction image.