Patent ID: 11862232
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 8:
9. The circuit for data transmission of claim 7, wherein the first buffer unit comprises a first gated inverter; the second buffer unit comprises a second gated inverter;
the first gated inverter is configured such that: an input end is configured to receive data cached by the mode register read-write module, a control end is configured to receive the mode register read enable signal, and an output end is electrically connected to the input end of the output driving unit; and
the second gated inverter is configured such that: an input end is electrically connected to the preset voltage; a control end is configured to receive the mode register unselected enable signal, and output the inversion signal of the preset voltage according to the mode register unselected enable signal; and an output end is electrically connected to the input end of the output driving unit.