Patent ID: 11914903
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. A device comprising:
an interconnect interface;
a memory system comprising:
one or more first-type memory devices configured to be high-bandwidth coupled to the interconnect interface through a memory switch, to receive first data;
one or more second-type memory devices coupled to be low-latency, coupled to the interconnect interface through the memory switch to receive second data; and

an accelerator coupled through the memory switch to the one or more first-type memory devices and the one or more second-type memory devices and configured to perform an operation using the first data and the second data, wherein the memory switch is programmable to configure the one or more first-type memory devices and the one or more second-type memory devices.