Patent ID: 11894043
Assignee: INTEGRATED SILICON SOLUTION INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. The management method of the power management circuit in the low-power double data rate memory of claim 14, wherein,
the voltage supplying step further comprises supplying a third voltage and a fourth voltage to another low dropout regulator;
the voltage regulating step further comprises configuring the another low dropout regulator to adjust a second voltage difference between the third voltage of a third transmitting terminal and the first voltage of a fourth transmitting terminal according to another reference voltage and a control signal, and adjust a third voltage difference between the fourth voltage of a fifth transmitting terminal and the first voltage of the fourth transmitting terminal according to the control signal; and
the another low dropout regulator has the third transmitting terminal, the fourth transmitting terminal and the fifth transmitting terminal, the third transmitting terminal is configured to transmit the third voltage of the power supplies, the fourth transmitting terminal is configured to transmit the first voltage of the power supplies, and the fifth transmitting terminal is configured to transmit the fourth voltage of the power supplies.