Patent ID: 11880585
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. The semiconductor memory according to claim 2, wherein the check data comprise parity check data, the written data comprising a plurality of data bits, the parity check data comprising one data bit, and the check module comprising:
a parity check unit, connected to the data transmission module, the parity check unit being configured to generate the parity check data according to the written data;
wherein data of one of the plurality of data bits are correspondingly stored in one of the plurality of data storage units or one of the plurality of check bit storage units, a transmission time duration required for the written data, configured for defining each of the plurality of data bits, to be transmitted from the data transmission module to a corresponding one of the plurality of data storage units being a data transmission time duration, and a transmission time duration required for the parity check data, configured for defining each of the plurality of data bits, to be transmitted from the data transmission module to a corresponding one of the plurality of check bit storage units being a check transmission time duration.