Patent ID: 11908852
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. An integrated circuit comprising:
a semiconductor substrate;
a first logic gate and a second logic gate formed with transistors having channel regions on the semiconductor substrate, a first output of the first logic gate being configured to generate a first output logic signal having a first output phase different from a first input phase of a first input logic signal at a first input of the first logic gate, and wherein the first output of the first logic gate is conductively connected to a second input of the second logic gate;
a horizontal routing track extending in a first direction in a first metal layer;
a first via connector conductively connecting the horizontal routing track to the first input of the first logic gate;
a backside routing track extending in the first direction in a backside metal layer, wherein the channel regions of the transistors are between the backside metal layer and the first metal layer; and
a backside via connector conductively connecting the backside routing track to the first output of the first logic gate.