Patent ID: 11909396
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 11:
12. An integrated circuit, comprising:
a first transistor comprising a first gate and a first active region, and configured to output a first clock signal at the first active region in response to a second clock signal received at the first gate through a first conductive line in a first layer on a back side of the integrated circuit; and
a first latch circuit comprising a second transistor that comprises a second gate and is configured to output, in response to the first clock signal received at the second gate through a second conductive line in the first layer on the back side, a signal to a data out circuit through a third conductive line in a first layer on a front side, opposite the back side, of the integrated circuit.