Patent ID: 11886911
Assignee: EMC IP HOLDING COMPANY LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus comprising:
at least one processing device comprising a processor coupled to a memory;
said at least one processing device being configured:
to associate different classes of service with respective threads of one or more applications executing on at least one of a plurality of processing cores of a storage system;
to configure different sets of prioritized thread queues for respective ones of the different classes of service;
to enqueue particular ones of the threads associated with particular ones of the classes of service in corresponding ones of the prioritized thread queues; and
to implement different dequeuing policies for selecting particular ones of the enqueued threads from the different sets of prioritized thread queues based at least in part on the different classes of service;
wherein the threads of the one or more applications executing on at least one of a plurality of processing cores of the storage system comprise different sub-threads of a first thread of a first application executing on a particular one of the plurality of processing cores of the storage system;
wherein each of the sub-threads of the first thread is in a particular one of multiple designated states at a particular point in time, the multiple designated states including a running state, a ready state and a suspended state, and
wherein different ones of the sub-threads that are in the suspended state are enqueued in respective different ones of the prioritized thread queues in order to wait for access to respective corresponding synchronization objects associated with resources of the particular processing core.