Patent ID: 11967286
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A display substrate, comprising:
a base substrate, comprising a display region and a peripheral region on at least one side of the display region; and
a shift register unit, a first clock signal line, and a second clock signal line, which are in the peripheral region of the base substrate,
wherein the first clock signal line and the second clock signal line extend along a first direction on the base substrate, and are configured to provide a first clock signal or a second clock signal to the shift register unit, respectively;
the shift register unit comprises an input circuit, a first node control circuit, a second node control circuit, a third node control circuit, a fourth node control circuit, and an output circuit;
the input circuit is configured to input an input signal to a first node in response to the first clock signal;
the second node control circuit is configured to input a first voltage or the first clock signal to a second node under control of the first clock signal and a level of the first node, so as to control a level of the second node;
the first node control circuit is configured to input a second voltage to the first node under control of the second clock signal and the level of the second node, so as to perform noise reduction on the first node;
the third node control circuit is configured to control a level of a third node in response to the level of the second node;
the fourth node control circuit is configured to input the level of the third node to a fourth node under control of the second clock signal; and
the output circuit is configured to output the second voltage to an output terminal under control of a level of the fourth node,
wherein the second node control circuit comprises a first control transistor, and the first control transistor comprises a first gate electrode;
the display substrate further comprises a first connection wire, and the first connection wire comprises a first portion and a second portion;
the first portion of the first connection wire is connected to and integrally formed with the first gate electrode of the first control transistor, the first portion of the first connection wire extends along the first direction, and an orthographic projection of the first portion of the first connection wire on the base substrate is on a side of an orthographic projection of an active layer of the first control transistor on the base substrate away from the display region;
the second portion of the first connection wire is connected to and integrally formed with the first gate electrode of the first control transistor, the second portion of the first connection wire extends along a direction, opposite to an extending direction of the first portion of the first connection wire, in the first direction, and an orthographic projection of the second portion of the first connection wire on the base substrate is on a side of the orthographic projection of the active layer of the first control transistor on the base substrate close to the display region;
the first control transistor further comprises a second gate electrode, the first gate electrode and the second gate electrode of the first control transistor are in parallel in the first direction, the second gate electrode of the first control transistor is connected to and integrally formed with the first portion of the first connection wire, and the first gate electrode and the second gate electrode of the first control transistor are connected through the first portion of the first connection wire;
the second gate electrode of the first control transistor is connected to the second portion of the first connection wire through the first portion of the first connection wire and the first gate electrode of the first control transistor, so that the second gate electrode of the first control transistor is not directly connected to the second portion of the first connection wire; and
an opening formed by the first portion of the first connection wire and the first gate electrode and the second gate electrode of the first control transistor is towards the display region.