Patent ID: 11941299
Assignee: INTEGRATED SILICON SOLUTION, (CAYMAN) INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device configured to store information for a processor, the processor accessing the memory device via a memory controller, comprising:
an array of addressable memory cells, wherein said addressable memory cells of said array comprise magnetic random access memory (MRAM) cells and wherein further said array is organized into a plurality of memory banks, and wherein the memory controller is configured to operate in accordance with requirements corresponding to a different type of memory than said addressable memory cells comprising magnetic random access memory (MRAM) cells;
an engine configured to control access to said addressable memory cells organized into said plurality of banks; and
a plurality of pipelines configured to perform access control and communication operations between said engine and said plurality of memory banks of said array of addressable memory cells, wherein at least a portion of operations associated with accessing a first memory bank of said plurality of memory banks via a first pipeline of said plurality of pipelines are performed substantially concurrently or in parallel with at least a portion of operations associated with accessing a second memory bank of said plurality of memory banks via a second pipeline of said plurality of pipelines, wherein said operations associated with accessing the first and second memory banks of said plurality of memory banks are coordinated to compensate for differences in operational requirements of the memory controller and operational constraints of said array of addressable memory cells.