Patent ID: 11941394
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. A method in a processor comprising:
receiving an instruction, the instruction indicating a source packed data operand having a plurality of source data elements, indicating a source packed indices operand having a plurality of indices, and having at least one field specifying a destination packed data register, each of the indices corresponding to a different one of the source data elements in a same relative position; and
performing the instruction and storing a result packed data operand in the destination packed data register, the result packed data operand including a plurality of result data elements that each have a value of one of the source data elements whose corresponding index specifies a data element position of the result data element in the result packed data operand, and the result packed data operand having a replacement value in a given result data element when none of the indices indicate a data element position of the given result data element, wherein the replacement value is a zero value.