Patent ID: 11894103
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 21:
22. An apparatus, comprising:
a first word line tile comprising a first plurality of word line plates stacked in a vertical direction, the first plurality of word line plates comprising a first word line plate that includes a plurality of first word lines in a first plane;
a second word line tile comprising a second plurality of word line plates stacked in the vertical direction, the second plurality of word line plates comprising a second word line plate that includes a plurality of second word lines in the first plane;
a first set of electrodes coupled with a first word line decoder and each coupled with a respective word line plate of the first plurality of word line plates, the first set of electrodes comprising a first electrode coupled with the first word line plate;
a second set of electrodes coupled with a second word line decoder and each coupled with a respective word line plate of the second plurality of word line plates, the second set of electrodes comprising a second electrode coupled with the second word line plate; and
a controller operable to cause the apparatus to:
apply, via the first word line decoder, a first voltage to the first electrode, wherein the first word line decoder is operable to activate the first word line plate based at least in part on applying the first voltage to the first electrode;
apply, via the second word line decoder, a second voltage to the second electrode, wherein the second word line decoder is operable to activate the second word line plate based at least in part on applying the second voltage to the second electrode;
apply a third voltage to a first pillar of a plurality of first pillars extending through a stack of materials comprising the first word line plate and the second word line plate, the first pillar coupled with a first memory cell of a plurality of first memory cells;
apply a fourth voltage to a second pillar of a plurality of second pillars extending through the stack of materials, the second pillar coupled with a second memory cell of a plurality of second memory cells; and
simultaneously access the first memory cell of the plurality of first memory cells and the second memory cell of the plurality of second memory cells based at least in part on applying the first voltage to the first word line plate via the first electrode, applying the third voltage to the first pillar, applying the second voltage to the second word line plate via the second electrode, and applying the fourth voltage to the second pillar.