Patent ID: 11955536
Assignee: UNITED SEMICONDUCTOR (XIAMEN) CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of forming a semiconductor transistor structure, comprising:
providing a substrate with a first conductivity type;
growing a fin structure on the substrate, the fin structure comprising an epitaxial stack disposed at an uppermost portion of the fin, the epitaxial stack comprising a first epitaxial SiGe layer having a second conductivity type opposite to the first conductivity type, a second epitaxial SiGe layer on the first epitaxial SiGe layer and in direct contact with the first epitaxial layer, and a third epitaxial SiGe layer having the second conductivity type on the second epitaxial SiGe layer and in direct contact with the second epitaxial SiGe layer, wherein the first epitaxial SiGe layer and the third epitaxial SiGe layer having the second conductivity type comprise a SiGe layer doped with phosphorus or arsenic, wherein the second epitaxial SiGe layer is an intrinsic SiGe layer;
forming a gate on the fin structure;
forming a buffer layer at a bottom of the fin structure; and
forming a strain relaxed layer on the buffer layer.