Patent ID: 11895824
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. A method of fabricating an integrated circuit array apparatus, the method comprising:
forming a first plurality of cells aligned in a first row on a substrate, wherein each cell comprises a programmable element and a body comprising a first diffusion region, a second diffusion region and a channel of a transistor, wherein the second diffusion region is on the first diffusion region and separated by the channel; and
forming a second plurality of cells aligned in a second row on the substrate, the second row parallel with and adjacent to the first row, wherein each cell comprises a programmable element and a body comprising a first diffusion region, a second diffusion region and a channel of a transistor, wherein the second diffusion region is on the first diffusion region and separated by the channel, the second plurality of cells further comprising a gate stack coupled to one side of the channel, wherein the stack comprises a gate electrode comprising an indivisible body extending between each body of the second plurality of cells and coupled to a channel of each of the first plurality of cells as a second address line.