Patent ID: 11960400
Assignee: CADENCE DESIGN SYSTEMS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. A method, comprising:
sending, by a second-level cache memory circuit, a plurality of probe requests regarding a particular cache line to a plurality of first-level cache memory circuits in response to receiving an acquire request for the particular cache line from a particular first-level cache memory circuit of plurality of first-level cache memory circuits;
in response to determining that a different first-level cache memory circuit of the plurality of first-level cache memory circuits is evicting a local copy of the particular cache line:
receiving the local copy of the particular cache line from the different first-level cache memory circuit,
writing the local copy of the particular cache line to a higher-level memory circuit;
sending a prefetch request for a new copy of the particular cache line to the higher-level memory circuit while the different first-level cache memory circuit responds to a corresponding one of the plurality of probe requests;
selecting, by a control circuit included in the second-level cache memory circuit, a particular bank of a plurality of banks included in the second-level cache memory circuit; and
transferring, by the particular bank, the acquire request from an input queue circuit to an initial pipeline stage of a plurality of pipeline stages included in the particular bank based on a length of time since the acquire request was received.