Patent ID: 11908750
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A device comprising:
a first fin extending upwards from a substrate;
a first gate over and along sidewalls of the first fin;
a first source/drain region in the first fin adjacent the first gate;
a protection layer over the first gate and the first source/drain region, the protection layer being between the first gate and the first source/drain region;
a first gate spacer on the protection layer between the first gate and the first source/drain region, the first gate spacer comprising a low-k material;
an etch stop layer over the first gate, the first gate spacer, and the first source/drain region;
a first dielectric layer over the etch stop layer, the first dielectric layer having a top surface level with the first gate;
a second dielectric layer over the first gate and the first dielectric layer; and
a conductive contact through the first and second dielectric layers to the first source/drain region.