Patent ID: 11889675
Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 5:
6. A method, comprising:
reading a memory cell by:
setting a first bit line and a first inverted bit line to a first power node, the first bit line coupled to a first memory cell node, the first inverted bit line coupled to a second memory cell node, the first memory cell node and the second memory cell node being coupled together;
disconnecting the first bit line and the first inverted bit line from the first power node;
activating a first transistor coupled to the first bit line and activating a second transistor coupled to the first inverted bit line by activating a first word line coupled to gate of the first and second transistors;
in response to the first memory cell node having a high value and the second memory cell node having a low value, discharging a third transistor to the first inverted bit line;
in response to the first memory cell node having a low value and the second memory cell node having a high value, discharging a fourth transistor to the first bit line.