Patent ID: 11875994
Assignee: NANYA TECHNOLOGY CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. The method for preparing a semiconductor device structure of claim 1, wherein the step of performing the etching process comprises:
during a first stage of the etching process, configuring an etching rate of the second energy-sensitive pattern higher than an etching rate of the lining layer to form a first stage opening between the first energy-sensitive patterns, wherein a bottom wall of the first stage opening is positioned above a bottom surface of the lining layer;
during a second stage of the etching process, deepening the second energy-sensitive pattern opening to form a second stage opening, and etching the first energy-sensitive patterns to form a plurality of transitional openings, wherein an etching rate of the first energy-sensitive pattern higher than the etching rate of the lining layer, such that a bottom wall of the second stage opening is positioned above a top surface of the target layer while a bottom wall of each of the transitional openings forms at the top surface of the target layer; and
during a third stage of the etching process, deepening the transitional openings and the second stage opening to form the second openings and the third opening in the target layer, wherein since the etching rate of the first energy-sensitive pattern and the etching rate of the second energy-sensitive pattern are different, the depths of the second openings and the third opening are different.