Patent ID: 11967367
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 0:
1. A nonvolatile memory device comprising:
a memory cell array including a plurality of memory cells arranged in rows and columns, wherein two or more of the memory cells are stacked in a direction perpendicular to a substrate;
a row decoder circuit connected with the rows of the memory cells through wordlines, and configured to select one wordline of the wordlines as a target of a program operation in the program operation;
a page buffer circuit connected with the columns of the memory cells through bitlines, and configured to store data to be written in the memory cells connected with the selected wordline in the program operation; and
a pass/fail check circuit connected with the page buffer circuit, and configured to determine a pass or a fail of the program operation in the program operation,
wherein the bitlines include bitlines of a first bitline group and bitlines of a second bitline group, and
wherein, in the program operation, the pass/fail check circuit detects a first program speed of first memory cells connected with the bitlines of the first bitline group from among the memory cells connected with the selected wordline and a second program speed of second memory cells connected with the bitlines of the second bitline group from among the memory cells connected with the selected wordline, and determines a program fail based on the first program speed and the second program speed.