Patent ID: 11863222
Assignee: CISCO TECHNOLOGY, INC.
Field: Telecommunications (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. The apparatus of claim 1, wherein each of the plurality of sub-rate receiver lanes includes:
an equalizer having a number of taps and one or more decision slicer circuits configured to apply a corresponding slicer threshold of one or more slicer thresholds in generating the digital sub-rate receiver data;
wherein the one or more first DACs include a number of average tap weight DACs equal to the number of taps, and a number of average slicer threshold DACs equal to a number of the one or more slicer thresholds;
wherein the one or more second DACs include a number of mismatch tap cancellation DACs equal to the number of taps of any equalizer of the plurality of sub-rate receiver lanes, and a number of mismatch slicer threshold DACs equal to the number of the one or more slicer thresholds for each of the plurality of sub-rate receiver lanes.