Patent ID: 11907627
Assignee: BATTELLE MEMORIAL INSTITUTE
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. An integrated circuit (IC) assessment method for assessing an IC-under-test, the IC assessment method comprising
training an artificial intelligence (AI) component comprising at least one artificial neural network (ANN) to transform layout rendering tiles of a GDSII or OASIS rendering of a reference IC into corresponding reference layout image tiles extracted from at least one layout image of the reference IC;
using the trained AI component, transforming GDSII or OASIS standard cell layout renderings of a library of GDSII or OASIS standard cell layout renderings into as-fabricated standard cell layout renderings forming a library of as-fabricated standard cell layout renderings; and
identifying instantiated standard cells and their placements in the layout image of the IC-under-test by matching the instantiated standard cells with corresponding as-fabricated standard cell layout renderings retrieved from the library of as-fabricated standard cell layout renderings.