Patent ID: 11947889
Assignee: SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. The chip according to claim 8, wherein:
the chip is used for implementing SHA-256 algorithm;
the rows of the first type of each operation stage include a first row, a second row and a third row, wherein:
the first row includes a first set of register modules and a first set of logical operation modules, the first set of register modules of the first row including 8 16-bit cache register modules A1, A2, B1, B2, C1, C2, D1 and D2 arranged in the form of an array of 1 row and 8 columns,
the second row includes a first set of register modules and a first set of logical operation modules, the first set of register modules of the second row including 8 16-bit cache register modules E1, E2, F1, F2, G1, G2, H1, H2 arranged in the form of an array of 1 row and 8 columns, and
the third row includes a first set of register modules, a first set of logical operation modules and a fifth set of register modules, the first set of register modules of the third row including 8 16-bit extension register modules R0-1, R0-2, R1-1, R1-2, R9-1, R9-2, R14-1 and R14-2 arranged in the form of an array of 1 row and 8 columns, the fifth set of register modules of the third row including 2 16-bit extension register modules R15-1 and R15-2 arranged in the form of an array of 1 row and 2 columns;
the plurality of rows of each operation stage further include a fourth row including a fourth set of modules, the fourth set of modules of the fourth row including 22 16-bit extension register modules R2-1, R2-2, R3-1, R3-2, R4-1, R4-2, R5-1, R5-2, R6-1, R6-2, R7-1, R7-2, R8-1, R8-2, R10-1, R10-2, R11-1, R11-2, R12-1, R12-2, R13-1, R13-2 arranged in the form of an array of 1 row and 22 columns; and
every two adjacent 16-bit cache register modules in each of the first and second rows are used to collectively store one 32-bit intermediate value, every two adjacent 16-bit extension register modules in each of the third and fourth rows are used to collectively store one 32-bit extension data, and the first set of logical operation modules in each of the first, second, and third rows includes 2 logical operation modules adjacent to each other in the Y-direction that are used to collectively process one or more data having a length of 32 bits.