Patent ID: 11868643
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A system comprising:
a plurality of memory devices; and
a processing device, operatively coupled with the plurality of memory devices, to perform operations comprising:
identifying a plurality of block stripes located on a logical unit (LU) identified by a logical unit number (LUN), wherein the LU is one of a plurality of LUs of a memory device;
determining a fill ratio of fully coupled pages for each of the plurality of block stripes;
selecting, among the plurality of block stripes, a block stripe with a highest fill ratio of fully coupled pages;
identifying, from the selected block stripe, a memory block of the LU; and
performing a memory scan operation on the memory block of the memory device.