Patent ID: 11955547
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 3:
4. The integrated circuit device of claim 1, further comprising first lightly doped source/drain (LDD) regions and second LDD regions disposed in the substrate, wherein:
the first source/drain epitaxy region and the second source/drain epitaxy region are disposed on the first LDD regions and the third source/drain epitaxy region and the fourth source/drain epitaxy region are disposed on the second LDD regions; and
the second SiCN spacer liner further has an eleventh surface opposite the fifth surface and the third SiCN spacer liner has a twelfth surface opposite the tenth surface, wherein the eleventh surface extends orthogonally from the first surface away from the first gate stack and over a respective first LDD region, the twelfth surface extends orthogonally from the sixth surface away from the second gate stack and over a respective second LDD region, and the eleventh surface of the second SiCN spacer liner and the twelfth surface of the third SiCN spacer liner physically contact the respective first LDD region and the respective second LDD region, respectively.