Patent ID: 11967594
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 0:
1. A semiconductor device structure, comprising:
a stack of semiconductor layers spaced apart from and aligned with each other;
a first source/drain epitaxial feature in contact with a first one or more semiconductor layers of the stack of semiconductor layers;
a second source/drain epitaxial feature disposed over the first source/drain epitaxial feature, wherein the second source/drain epitaxial feature is in contact with a second one or more semiconductor layers of the stack of semiconductor layers;
a dielectric material disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature; and
a liner disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, wherein the liner is a conformal layer and is in contact with the dielectric material, and the liner is U-shaped.