Patent ID: 11916551
Assignee: FLEX LOGIX TECHNOLOGIES, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A method of routing interconnects of an integrated circuit comprising a field programmable gate array including: (i) a first plurality of non-contiguous logic tiles, wherein each logic tile of the first plurality of logic tiles includes a logic tile interconnect network having a plurality of switches and a plurality of logic tile interconnects, (ii) a second plurality of non-contiguous logic tiles, wherein each logic tile of the second plurality of logic tiles includes a logic tile interconnect network having a plurality of switches and a plurality of logic tile interconnects, and (iii) a tile-to-tile interconnect network, having a plurality of tile-to-tile interconnects, each tile-to-tile interconnect having start/end points to interconnect the logic tile networks of the first plurality of logic tiles and the second plurality of logic tiles, the method comprising:
routing a first plurality of tile-to-tile interconnects in the first plurality of non-contiguous logic tiles in parallel, wherein the start/end point of each tile-to-tile interconnect in the first plurality of non-contiguous logic tiles is independent of the start/end point of the other tile-to-tile interconnects in the first plurality of non-contiguous logic tiles;
after routing the first plurality of tile-to-tile interconnects in a first plurality of non-contiguous logic tiles, routing a second plurality of tile-to-tile interconnects in the second plurality of non-contiguous logic tiles in parallel, wherein the start/end point of each tile-to-tile interconnect in the second plurality of logic tiles is independent of the start/end point of the other tile-to-tile interconnects in the second plurality of non-contiguous logic tiles; and
wherein routing the second plurality of tile-to-tile interconnects in the second plurality of non-contiguous logic tiles includes connecting at least one start/end point of each tile-to-tile interconnect in the second plurality of non-contiguous logic tiles to at least one start/end point of each tile-to-tile interconnect in the first plurality of non-contiguous logic tiles that was routed in the first plurality of non-contiguous logic tiles.