Patent ID: 11966480
Assignee: NVIDIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 6:
7. The accelerator circuit of claim 1, wherein the first descriptor is an encryption operation descriptor, wherein the DMA circuit is further to:
retrieve the first IV and the first encryption key from the secure memory;
encrypt the first IV and a first value of the first block counter with a first block cipher using the first encryption key to obtain a first result;
encrypt the first IV and a second value of the first block counter with a second block cipher using the first encryption key to obtain a second result;
combine the second result and first plaintext to obtain first ciphertext;
combine the first ciphertext with a zero block to obtain a first value for the first computed hash key, wherein the first value is a partial authentication tag for the first data transfer;
retrieve the first IV, a current value of the first block counter, and a current value of the first computed hash key;
encrypt the first IV and the current value of the first block counter with a third block cipher using the first encryption key to obtain a third result;
combine the third result and second plaintext to obtain second ciphertext;
combine the second ciphertext and the current value of the first computed hash key to obtain a fourth result;
combine the fourth result with a length of ciphertext to obtain a fifth result; and
combine the fifth result with the first result to obtain a first authentication tag.