Patent ID: 11907831
Assignee: UNIVERSITY OF DAYTON
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. A method for generating computation operations in parallel by implementing a plurality of resistive memories, comprising:
applying a plurality of input voltages to a plurality of inputs of an analog neuromorphic circuit;
providing, by a plurality of resistive memories, a conductance to each input voltage applied to each of the inputs so that each input voltage is multiplied in parallel by the corresponding conductance of each corresponding resistive memory to generate a corresponding current for each input voltage and each corresponding current is added in parallel;
adjusting a first conductance of the resistive memories positioned on a first wire and a second conductance of the resistive memories positioned on a second wire relative to each other based on a first voltage value associated with a first accumulative current that is conducted by the first wire and a second voltage value associated with a second accumulative current that is conducted by the second wire to obtain a functionality of the analog neuromorphic circuit; and
generating an output signal from each of the input voltages multiplied in parallel with each of the corresponding currents for each of the input voltages added in parallel and the adjusted first conductance and second conductance, wherein the functionality of the analog neuromorphic circuit is executed based on the output signal.