Patent ID: 11955423
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method comprising:
forming a first conductive feature and a second conductive feature over a semiconductor substrate, wherein a lower surface of the first conductive feature is level with a lower surface of the second conductive feature;
forming a passivation structure over the first conductive feature and the second conductive feature;
after forming the passivation structure, etching the passivation structure to form a first opening exposing the first conductive feature;
after forming the passivation structure, etching the passivation structure to form a second opening over the second conductive feature, wherein a first portion of the passivation structure remains between the second opening and the second conductive feature;
forming a first under-bump metallurgy (UBM) structure in the first opening and electrically coupled to the first conductive feature; and
forming a second UBM structure in the second opening, wherein the second UBM structure is electrically isolated from the second conductive feature by the first portion of the passivation structure.