Patent ID: 11908819
Assignee: APPLE INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor package comprising:
a packaging substrate including:
a plurality of metal routing layers;
a plurality of dielectric layers including a top dielectric layer forming a topmost surface;
a patterned metal contact layer, wherein the patterned metal contact layer includes:
an array of surface mount (SMT) metal bumps in a chip mount area, the array of SMT metal bumps partially embedded within the top dielectric layer and protruding from the topmost surface of the top dielectric layer; and
a metal dam structure laterally surrounding the array of SMT metal bumps in the chip mount area, the metal dam structure partially embedded within the top dielectric layer and protruding from the topmost surface of the top dielectric layer; and

a device bonded to the array of SMT metal bumps;
wherein the metal dam structure forms a first geometric shape adjacent a first edge and a second edge of the device, and a second geometric shape adjacent a corner of the device where the first edge intersects with the second edge.