Patent ID: 11901318
Assignee: WINBOND ELECTRONICS CORP.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An integrated circuit structure, comprising:
a substrate comprising thereon a logic core circuit region and an embedded memory area;
a copper interconnect structure disposed on the substrate, wherein the copper interconnect structure comprises an uppermost copper layer covered by a dielectric layer;
an aluminum pad layer disposed on the dielectric layer, wherein the aluminum pad layer comprises a first pad pattern within the logic core circuit region and a second pad pattern within the embedded memory area;
a passivation layer covering the first pad pattern within the logic core circuit region and the second pad pattern within the embedded memory area; and
an aluminum shield layer comprising concentric aluminum routing patterns disposed directly on the embedded memory area and between the uppermost copper layer and the aluminum pad layer, wherein the aluminum shield layer has a thickness that is thinner than that of the aluminum pad layer, wherein the first pad pattern and the second pad pattern respectively contact the uppermost copper layer and the aluminum shield layer at different horizontal levels.