Patent ID: 11968830
Assignee: WINBOND ELECTRONICS CORP.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of manufacturing a memory device, comprising:
providing a substrate, wherein the substrate comprises an array region and a periphery region;
sequentially forming a stack layer, a control structure, a hard mask layer, and a mask pattern on the substrate, wherein the control structure at least comprises a first stop layer, a first oxide layer, a second stop layer, and a second oxide layer;
forming a photoresist layer in the mask pattern of the periphery region;
by using the photoresist layer and the mask pattern as a mask, removing a portion of the hard mask layer, a portion of the second oxide layer, and a portion of the second stop layer in the array region to form a plurality of first openings in the array region;
after removing the photoresist layer, removing a portion of the hard mask layer in the periphery region to form at least one second opening in the periphery region;
performing a first etching process to remove a portion of the control structure so that the plurality of first openings and the second opening extend into the control structure, thereby forming a plurality of third openings and at least one fourth opening, wherein the fourth opening has a bottom surface higher than a bottom surface of the plurality of third openings; and
performing a second etching process to remove a portion of the stack layer so that the plurality of third openings and the fourth opening extend into the stack layer, thereby forming a plurality of fifth openings and at least one sixth opening.