Patent ID: 11870441
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: nan (nan)
Classification: CPC nan | IPC G  H

Claim 13:
14. The clock gating circuit of claim 13, wherein the first inverter comprises:
a third transistor of the first type, the third transistor including a fifth gate terminal, a fifth drain terminal and a fifth source terminal, the fifth gate terminal being configured to receive the second control signal, the fifth drain terminal being coupled to at least the fourth gate terminal, and the fifth source terminal being coupled to the voltage supply; and
a fifth transistor of the second type, the fifth transistor including a sixth gate terminal, a sixth drain terminal and a sixth source terminal, the sixth gate terminal being configured to receive the second control signal, and the sixth source terminal being coupled to the reference voltage supply,
wherein each of the sixth drain terminal, the fifth drain terminal and the fourth gate terminal are coupled together; and
each of the sixth gate terminal, the fifth gate terminal, the second node and the second gate terminal are coupled together.