Patent ID: 11922031
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device, comprising:
a memory array including a plurality of memory cells configured to store data;
a communication connector coupled to the memory array and configured to receive an externally provided command from an external device, wherein the externally provided command is (1) associated with a precharging operation and a target address and (2) used for refreshing a set of neighboring wordlines surrounding the target address;
a command decoder coupled to and between the memory array and the communication connector, the command decoder configured to decode the received refresh command; and
a refresh control circuit coupled to and between the memory array and the command decoder, the refresh control circuit configured to:
identify that a memory bank associated with the target address is in a closed state; and
block capturing of the target address when the memory bank is in the closed state.