Patent ID: 11862637
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. An integrated circuit device, comprising:
a first power rail;
a second power rail;
a first active area extending in a first direction, the first active area including a first region defining a first threshold voltage (VT) and a second region defining a second VT different than the first VT, wherein the first and second regions abut one another to define a first boundary therebetween such that the first and second regions are on opposite sides of the first boundary in the first direction;
a first PMOS transistor including the first region of the first active area and a first gate, the first PMOS transistor having the first VT, the first gate extending in a second direction perpendicular to the first direction;
a second PMOS transistor including the second region of the first active area and a second gate, the second PMOS transistor having the second VT, the second gate extending in the second direction;
a tie-off PMOS transistor including the first and second regions of the first active area and a third gate extending in the second direction directly over the first boundary such that the first PMOS transistor is on a first side of the boundary in the first direction and the second PMOS transistor is on a second side of the boundary in the first direction, and wherein the third gate is connected to the first power rail;
a second active area extending in the first direction, the second active area including a third region defining the first VT and a fourth region defining the second VT, wherein the third and fourth regions abut one another to define a second boundary therebetween such that the third and fourth regions are on opposite sides of the second boundary in the first direction, and wherein the first and second boundaries align in the second direction;
a first NMOS transistor including the third region of the second active area and the first gate, the first NMOS transistor having the first VT;
a second NMOS transistor including the fourth region of the second active area and the second gate, the second NMOS transistor having the second VT; and
a tie-off NMOS transistor including the third and fourth regions of the second active area and the third gate extending in the second direction directly over the second boundary such that the first NMOS transistor is on a first side of the boundary in the first direction and the second NMOS transistor is on a second side of the boundary in the first direction, and wherein the third gate is connected to the second power rail.