Patent ID: 11908527
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device comprising:
a plurality of memory cells respectively connected to a plurality of word lines;
a peripheral circuit configured to perform a read operation of reading data stored in selected memory cells among the plurality of memory cells, the selected memory cells connected to a selected word line among the plurality of word lines; and
a read operation controller configured to control the peripheral circuit to apply a pass voltage to adjacent word lines among the plurality of word lines adjacent to the selected word line during the read operation, discharge the pass voltage to a target pass voltage less than the pass voltage after a predetermined time elapses, and after a target read time elapses from when the pass voltage is discharged to the target pass voltage, obtain data stored in the selected memory cells through bit lines connected to the selected memory cells.