Patent ID: 11950401
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G  B | IPC H

Claim 0:
1. A semiconductor structure, comprising:
a substrate; and
an array of two-port (TP) SRAM cells over the substrate, wherein each of the array of TP SRAM cells includes a write port and a read port,
wherein the array of TP SRAM cells includes a first TP SRAM cell and a second TP SRAM cell, the write port of the first TP SRAM cell abuts the write port of the second TP SRAM cell, the write port of the first TP SRAM cell includes a first write pull-down (W_PD) transistor, and the write port of the second TP SRAM cell includes a second W_PD transistor, the array of TP SRAM cells further includes a first source/drain contact landing on both a source/drain electrode of the first W_PD transistor and another source/drain electrode of the second W_PD transistor,
wherein the first TP SRAM cell includes a first Vss conductor located at a first metal (M1) layer, the first Vss conductor is directly above the first source/drain contact and connected to the first source/drain contact.