Patent ID: 11877441
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 9:
10. A method of fabricating a memory, comprising:
providing a substrate;
forming on the substrate plural bitline grooves that are arranged along a first direction and each of which is S-shaped;
forming in each bitline groove a first separation layer whose thickness is smaller than depth of the bitline groove;
forming bitlines on the first separation layer, wherein total thickness of the first, separation layer and the bitlines is smaller than depth of the bitline groove, the plural bitlines are arranged along the first direction, and each bitline is S-shaped;
forming a second separation layer on the bitline, a top surface of the second separation layer being flush with a top surface of the substrate;
removing the substrate between adjacent separation walls, and retaining the substrate under a bottom surface of the first separation layer, wherein the separation wall includes the first separation layer, the bitlines, and the second separation layer; and
thrilling a third separation layer in a space between the adjacent separation walls, the third separation layer, the second separation layer, and the first separation layer together forming a separation layer,
wherein in the step of forming bitlines on the first separation layer:
each bitline as formed includes plural first bitline structures and plural second bitline structures spaced apart from one another and sequentially connected to one another, the first bitline structures extend along a second direction, the second direction is inclined relative to the first direction, the second bitline structures extend along a third direction, the third direction is inclined relative to the first direction, and a direction of inclination of the third direction relative to the first direction is opposite to a direction of inclination of the second direction relative to the first direction.