Patent ID: 11899583
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 13:
14. A device comprising:
a multi-layered logic structure with multiple layers including a first layer and a second layer arranged vertically in a stacked configuration;
a first inter-layer data routing network having interconnect logic in each layer of the multiple layers including first interconnect logic in the first layer and second interconnect logic in the second layer that is linked to the first interconnect logic by way of the first inter-layer data routing network;
a second inter-layer data routing network having at least one router in each layer of the multiple layers including a first router in the first layer and a second router in the second layer that is linked to the first router by way of the second inter-layer data routing network that is different than the first inter-layer data routing network;
a first logic block disposed in the first layer, wherein the first logic block includes first core processing logic, first L2 cache memory and the first interconnect logic; and
a second logic block disposed in the second layer, wherein the second logic block includes second core processing logic, second L2 cache memory and the second interconnect logic,
wherein the first inter-layer data routing network includes first inter-layer data paths that vertically couple the interconnect logic in each layer together including the first interconnect logic in the first layer to the second interconnect logic in the second layer by way of the first inter-layer data routing network, and
wherein the second inter-layer data routing network includes second inter-layer data paths that vertically couple the at least one router in each layer together including the first router in the first layer to the second router in the second layer by way of the second inter-layer data routing network, which is different than the first inter-layer data routing network that is different than the first inter-layer data routing network.