Patent ID: 11894312
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method comprising:
forming a seed layer over a carrier substrate;
forming a patterned dielectric layer over the seed layer, the patterned dielectric layer comprising a plurality of openings;
plating a first metallization pattern in the plurality of openings;
bonding an interconnect device to a first surface of the first metallization pattern, the interconnect device is free of any transistors;
bonding a passive device to the first surface of the first metallization pattern, the passive device is free of any active devices;
burying the interconnect device and the passive device in a dielectric film;
bonding a first device die to a second surface of the first metallization pattern, the second surface is opposite the first surface; and
bonding a second device die to the second surface of the first metallization pattern, wherein the interconnect device electrically routes signals between the first device die and the second device die.