Patent ID: 11929125
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. An apparatus, comprising:
a control circuit configured to connect to a plurality of sense circuits, each sense circuit comprising a set of internal user data latches, and to a respective transfer data latch of each sense circuit, each respective data transfer latch comprising a first bit value for a subset of a set of data states and a second bit value for data states of the set of data states which are above the subset, the first bit value indicating the data state defined by the respective data transfer latch is not prohibited from having a verify test and the second bit value indicating a data state defined by the respective data transfer latch is prohibited from having a verify test, each sense circuit of the plurality of sense circuits is configured to connect to a respective memory cell of a set of memory cells; and
an interface connected to the control circuit, the control circuit is configured to issue commands via the interface to:
for each sense circuit, load a bit of a set of bits of user data into the respective transfer data latch and remaining bits of the set of bits of user data into the set of internal user data latches;
shift the subset higher by one data state at specified program loops in a program operation; and
with each shift, flip the second bit value to the first bit value for each respective data transfer latch for a data state of the set of data states which becomes encompassed by the subset.