Patent ID: 11895822
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A forming method of a memory structure, comprising:
forming m×n silicon pillars arranged in m rows and n columns for subsequent formation of m×n vertical transistors, the rows extend in a first direction and the columns extend in a second direction;
forming m bit lines, the bit lines extending in the first direction and electrically connected to drains of all the vertical transistors in a same row, the drains are provided below the silicon pillars; and
forming n word lines, the word lines extending in the second direction, located in the middle of the silicon pillars, and serving as gates of all the vertical transistors in a same column;
the first direction and the second direction form a non-right angle.