Patent ID: 11909415
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A memory system, comprising:
a nonvolatile memory including a plurality of memory cells; and
a memory controller configured to control the nonvolatile memory,
wherein in read operation for the memory cells, the memory controller is configured to:
perform tracking including a plurality of reads in which a read voltage is shifted;
determine a hard bit read voltage based on results of the tracking;
calculate a soft bit read voltage based on the determined hard bit read voltage;
perform soft bit read using the calculated soft bit read voltage; and
perform a soft bit decoding process using a result of the soft bit read and a log-likelihood ratio table associated with the calculated soft bit read voltage,
wherein:
the memory controller includes a storage circuit configured to store a first table that stores a set value of the soft bit read voltage and a second table that stores a set limit value of the read voltage; and
the memory controller is configured to:
calculate a difference between the determined hard bit read voltage and a set limit value corresponding to the determined hard bit read voltage in the second table; and
calculate a soft bit read voltage using a reference value corresponding to the difference in the first table.