Patent ID: 11941291
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. An apparatus, comprising:
a memory device; and
a memory sub-system controller coupled to the memory device, wherein the memory subsystem controller includes a memory sub-system memory fencing component configured to:
receive a number of commands and a memory fencing command; and execute a first portion of the number of commands before executing a second portion of the number of commands in response to instructions in the memory fencing command, wherein a latency associated with executing the first portion of the number of commands is greater than a latency associated with executing the second portion of the number of commands and wherein the memory fencing command prevents a non-deterministic protocol used by the memory sub-system from performing the second portion of the number commands with lower latency before the first portion of the number of commands with higher latency, wherein the memory fencing command is configured to execute the first number of commands to move data from a first location to a second location in the memory sub-system before executing the second number of commands to read the data from the second location in the memory sub-system.