Patent ID: 11908911
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A device, comprising:
a source contact and a drain contact in a source contact trench and a drain contact trench;
a channel layer under the source contact and the drain contact, the channel layer having a first depression in a source region beneath the source contact, and the channel layer having a second depression in a drain region beneath the drain contact;
a first spacing layer on a bottom of the source contact and in the first depression in the channel layer, and a second spacing layer on a bottom of the drain contact and in the second depression in the channel layer, wherein the first spacing layer and the second spacing layer are on a surface of the channel layer and line sidewalls of the source contact trench and the drain contact trench each of the first spacing layer and the second spacing layer having a central deeper portion laterally between outer shallower portions, each of the source contact and the drain contact having an upper portion wider than a bottom portion in the respective source contact trench and the drain contact trench;
a gate electrode below the channel layer; and
a dielectric above the gate electrode and underneath the channel layer; and
wherein the first spacing layer and the second spacing layer extend a distance of 15 to 30 nm up along sides of the source contact trench and the drain contact trench.