Patent ID: 11899583
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 6:
7. A device comprising:
a multi-layered logic structure having multiple layers that are arranged vertically in a stacked configuration;
core processing logic and L1 cache memory disposed in a first layer of the multiple layers;
an L2 cache memory split into multiple portions linked together with a first inter-layer data link, wherein a first portion of the L2 cache memory is disposed in a second layer of the multiple layers, and wherein a second portion of the L2 cache memory is disposed in a third layer of the multiple layers; and
a routing network having at least one router disposed in each layer of the multiple layers including a first router disposed in the first layer with the L1 cache memory, second router disposed in the second layer with the first portion of L2 cache memory, and a third router disposed in the third layer with the second portion of L2 cache memory,
wherein the second router is linked to the first router with a second inter-layer data link that is different than the first inter-layer data link, and
wherein the third router is linked to the first router and the second router with the second inter-layer data link that is different than the first inter-layer data link.