Patent ID: 11916067
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 15:
16. A method, comprising:
forming a first well having a first conductivity type within an enclosed portion of a lightly doped epitaxial layer having the first conductivity type, the enclosed portion touching and being bounded laterally by deep wells having a second opposite conductivity type and further touching and being bounded vertically by a buried layer having the second conductivity type connecting the deep wells, the deep wells touching the first well;
forming a transistor formed in or over the first well and having a polysilicon gate electrode formed in a gate-layer;
forming a dielectric isolation structure touching the enclosed portion of the lightly doped epitaxial layer; and
forming a passive component formed in the gate-layer and located over the dielectric isolation structure.