Patent ID: 11967526
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method comprising:
depositing a dielectric cap over a gate structure;
forming a source/drain contact over a source/drain region adjacent to the gate structure;
oxidizing a top portion of the dielectric cap to form an oxidized top portion while a bottom portion of the dielectric cap that is between the oxidized top portion and the gate structure remains un-oxidized, wherein a top surface of the bottom portion is directly connected to a bottom surface of the oxidized top portion;
after oxidizing the top portion of the dielectric cap, depositing an etch stop layer over the oxidized top portion of the dielectric cap and an interlayer dielectric (ILD) layer over the etch stop layer;
etching the ILD layer and the etch stop layer to form a via opening extending though the ILD layer and the etch stop layer; and
filling a source/drain via in the via opening.