Patent ID: 11862628
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A method, comprising:
forming, based at least in part on doping portions of a first silicon substrate, a first plurality of transistors;
forming a first deck of memory cells above the first silicon substrate and coupled with the first plurality of transistors;
forming a second deck of memory cells above the first deck of memory cells;
bonding a second silicon substrate above the second deck of memory cells;
forming, based at least in part on doping portions of the second silicon substrate after bonding the second silicon substrate above the second deck of memory cells, a second plurality of transistors coupled with the second deck of memory cells; and
forming, after bonding the second silicon substrate above the second deck of memory cells, a first plurality of interconnects, wherein each interconnect couples one or more subsets of transistors of the first plurality of transistors with one or more subsets of transistors of the second plurality of transistors.