Patent ID: 11949420
Assignee: BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 6:
7. The clock spread spectrum circuit according to claim 6, wherein the input unit comprises: a first register, a second register, a third register, a fourth register, a first adder, and a second adder; the selection unit comprises: a first selector, a second selector, and a third selector; the output unit comprises: a D flip-flop, a first inverter, and a second inverter;
the first adder and the second adder are connected to the control word providing module;
the first adder, the first register, the second register, and the first selector are connected in sequence;
the second adder, the third register, the fourth register, and the second selector are connected in sequence;
the second register is also connected to a first clock signal terminal;
the first register, the third register, and the fourth register are also connected to a second clock signal terminal;
the first adder is configured to add the first duty cycle control word and information stored in the third register to obtain a first addition result, and store the first addition result in the first register at a first rising edge of a second clock signal provided by the second clock signal terminal connected to the first register, the second register is configured to store the first addition result stored in the first register at a first rising edge of a first clock signal provided by the first clock signal terminal connected to the second register, and output the first addition result to the first selector;
the second adder is configured to add the second duty cycle control word and the information stored in the third register to obtain a second addition result, and store the second addition result in the third register at a second rising edge of the second clock signal provided by the second clock signal terminal connected to the third register, the fourth register is configured to store the second addition result stored in the third register at a third rising edge of the second clock signal provided by the second clock signal terminal connected to the fourth register, and output the second addition result to the second selector;
the selection control signal comprises the first addition result and the second addition result,
the first selector and the second selector are connected to the base output signal generation unit and the third selector, and the third selector is also connected to a first input end of the D flip-flop and the first clock signal terminal;
the first selector is configured to select a first base output signal from the plurality of first base output signals as a first selected first base output signal in response to the first addition result output by the second register, and output the first selected first base output signal to the third selector;
the second selector is configured to select a first base output signal from the plurality of first base output signals as a second selected first base output signal in response to the second addition result output by the fourth register, and output the second selected first base output signal to the third selector;
the third selector is configured to select one of the first selected first base output signal and the second selected first base output signal as the target first base output signal at a second rising edge of the first clock signal provided by the first clock signal terminal, and output the target first base output signal to the D flip-flop;
a second input end of the D flip-flop is connected to an output end of the first inverter, an input end of the first inverter and an input end of the second inverter are both connected to an output end of the D flip-flop, and the D flip-flop is configured to generate the duty cycle control signal based on the target first base output signal and output the duty cycle control signal to the output selection sub-module.