Patent ID: 11874817
Assignee: BANK OF AMERICA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. The computing platform of claim 1, wherein the memory stores additional computer-readable instructions that, when executed by the at least one hardware processor, cause the computing platform to:
initialize at least two processing workers, wherein initializing the at least two processing workers comprises initializing a first processing worker and a second processing worker;
cause the first processing worker to:
perform a first query on the work queue database, wherein performing the first query on the work queue database comprises reading and locking a first set of work items identified in the work queue database; and
initiate parallel processing of the first set of work items, wherein initiating parallel processing of the first set of work items comprises:
processing a first subset of the first set of work items in parallel; and
upon completion of processing each work item of the first subset of the first set of work items, marking the corresponding work item as completed in the work queue database; and

cause the second processing worker to:
perform a second query on the work queue database, wherein performing the second query on the work queue database comprises reading and locking a second set of work items identified in the work queue database; and
initiate parallel processing of the second set of work items, wherein initiating parallel processing of the second set of work items comprises:
processing a first subset of the second set of work items in parallel; and
upon completion of processing each work item of the first subset of the second set of work items, marking the corresponding work item as completed in the work queue database.