Patent ID: 11960855
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. An apparatus for performing deep learning operations, the apparatus comprising:
a systolic array comprising a plurality of multiplier accumulator (MAC) units;
a multiplexer set respectively connected to at least one MAC unit of the plurality of MAC units; and
a control circuit configured to control an operation of the multiplexer set and the plurality of MAC units according to a plurality of operation modes,
wherein the multiplexer set comprises:
a first multiplexer connected to an input terminal of an accumulator of the at least one MAC unit;
a second multiplexer connected to an output terminal of the accumulator of the at least one MAC unit; and
a third multiplexer connected to output terminals of the plurality of MAC units, and

wherein the at least one MAC unit, the first multiplexer, and the second multiplexer operate on a first clock frequency, and the third multiplexer operates on a second clock frequency that is an integer multiple of the first clock frequency.