Patent ID: 11922169
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. An apparatus, comprising:
a summing array including a plurality of non-volatile memory elements arranged in columns, each non-volatile memory element in the summing array being programmed to a high resistance state or a low resistance state based on weights of a neural network, the summing array configured to generate a summed signal for each column based, at least in part, on a plurality of input signals; and
a multiplying array, coupled to the summing array, including a plurality of non-volatile memory elements, each non-volatile memory element in the multiplying array being programmed to a different conductance level based on the weights of the neural network, the multiplying array configured to generate an output signal based, at least in part, on the summed signals from the summing array.