Patent ID: 11862224
Assignee: REALTEK SEMICONDUCTOR CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. A system on chip (SoC) integrated circuit (IC), equipped with a memory calibration function, the SoC IC comprising:
a processing circuit, configured to control operations of the SoC IC;
a physical layer (PHY) circuit, coupled to the processing circuit, configured to communicate with a memory for the processing circuit; and
a pad set, comprising a plurality of pads as terminals of the SoC IC for coupling the SoC IC to at least one external component, wherein the at least one external component comprises the memory;
wherein:
in a power-up and initialization phase of the SoC IC, the processing circuit controls the PHY circuit within the SoC IC to apply power to the memory through the pad set and perform initialization on the memory;
in an impedance-calibration-related phase of the SoC IC, the processing circuit triggers the memory to perform impedance calibration regarding a set of data pins;
in at least one subsequent phase of the SoC IC, during performing calibration operation among a reading-related calibration operation and a writing-related calibration operation, the processing circuit performs a data access test corresponding to a set of test points on a predetermined mask, wherein the predetermined mask is movable with respect to a data eye, and possible positions of the predetermined mask relative to the data eye respectively correspond to multiple candidate positions of a center point of the predetermined mask; and
according to whether the data access test is successful, the processing circuit selectively stops the calibration operation;
wherein the calibration operation is performed in at least one round, wherein
the at least one round corresponds to at least one candidate position among the multiple candidate positions.