Patent ID: 11935804
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A method comprising:
forming a through-via over and electrically connected to a first redistribution structure, wherein forming the through-via comprises:
depositing a seed layer over the first redistribution structure;
plating a first conductive material layer on the seed layer with a first plating process, wherein the first conductive material layer has a first density;
plating a second conductive material layer on the first conductive material layer with a second plating process, wherein the second conductive material layer has a second density; and
plating a third conductive material layer on the second conductive material layer with a third plating process, wherein the third conductive material layer has a third density, and wherein the third density is smaller than the first density and the second density.