Patent ID: 11895836
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An integrated circuit (IC) comprising:
a semiconductor substrate including a logic region and a memory cell region separated by an isolation structure, wherein the isolation structure extends into a top surface of the semiconductor substrate and comprises dielectric material;
a logic device on the logic region, wherein the logic device includes a conductive logic gate electrode;
a memory device on the memory cell region, wherein the memory device includes a first select gate electrode;
a dummy select gate structure made of conductive material disposed on the isolation structure, wherein an upper surface of the dummy select gate structure and an upper surface of the first select gate electrode have equal heights as measured from the top surface of the semiconductor substrate;
wherein an upper surface of the conductive logic gate electrode has a second height as measured from the top surface of the semiconductor substrate, the second height being less than each of the equal heights;
a dummy control gate structure disposed on the isolation structure, wherein the dummy control gate structure has an inner sidewall facing the memory cell region; and
a sidewall spacer along the inner sidewall of the dummy control gate structure and disposed on the isolation structure, wherein the sidewall spacer has an inner sidewall facing the memory cell region; and
wherein the dummy select gate structure is disposed along the inner sidewall of the sidewall spacer and disposed on the isolation structure.