Patent ID: 11887957
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 18:
19. A method of manufacturing semiconductor device, the method comprising:
forming a circuit layer on a semiconductor substrate;
forming an under-bump pattern and a protective layer on the circuit layer, the protective layer exposing at least a portion of a top surface of the under-bump pattern;
forming a seed layer on the under-bump pattern and the protective layer;
forming a resist pattern comprising a guide opening on the seed layer;
forming a preliminary bump pattern in the guide opening of the resist pattern, the preliminary bump pattern including a material different from that of the under-bump pattern;
forming a bump pattern on the preliminary bump pattern by performing an annealing process on the preliminary bump pattern;
forming an organic dielectric layer covering a lateral surface and a top surface of the bump pattern; and
performing a planarization process with respect to the organic dielectric layer until an upper surface of the bump pattern is exposed,
wherein the bump pattern comprises a support pattern which is formed from a portion of the seed layer and a solder pillar pattern which is formed from a portion of the preliminary bump pattern.