Patent ID: 11948977
Assignee: STMICROELECTRONICS S.R.L.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method, comprising:
forming doped source and drain regions in a semiconductor body;
forming a planar epitaxial channel extending between the source and drain regions, the planar epitaxial channel being at least partially recessed below an upper surface of an active region of the semiconductor body;
forming a gate dielectric in contact with the planar epitaxial channel, the gate dielectric having a dielectric length;
forming a conductive gate over the gate dielectric, the conductive gate having a gate length that exceeds the dielectric length by a distance that defines an undercut region; and
encapsulating the conductive gate with a single, continuous encapsulant in contact with a top surface, sidewalls, and an underside of the conductive gate, the single, continuous encapsulant filling the undercut region.