Patent ID: 11948628
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. The memory system of claim 9, further comprising:
a memory controller to:
sense a first current through the second select line according to a parallel resistance of i) a series resistance of the first memory cell and the second memory cell, and ii) a series resistance of the third memory cell and the fourth memory cell to read a first multi-level data stored by the first memory cell, the second memory cell, the third memory cell, and the fourth memory cell, and
sense a second current through the second select line according to a parallel resistance of i) a series resistance of the fifth memory cell and the sixth memory cell, and ii) a series resistance of the seventh memory cell and the eighth memory cell to read a second multi-level data stored by the fifth memory cell, the sixth memory cell, the seventh memory cell, and the eighth memory cell.