Patent ID: 11923860
Assignee: ROHM CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 5:
6. A control method for a Phase Locked Loop (PLL) circuit, wherein the PLL circuit comprises a digitally controlled oscillator structured such that, during a period in which a selection signal is asserted, a ring oscillator is formed so as to oscillate at a frequency that is changed based on a control code, and such that, during a period in which the selection signal is negated, an injection edge based on a reference clock can be injected,
and wherein the control method comprises:
a startup step in which, when the PLL circuit is started up a first time, the PLL circuit repeats a cycle comprising (i) a first process in which the selection signal is asserted so as to oscillate the digitally controlled oscillator, and phase comparison is made between an oscillator clock generated by the digitally controlled oscillator and the reference clock, and (ii) a second process in which the selection signal is negated so as to stop the digitally controlled oscillator, and the control code is updated by a binary search based on a result of the phase comparison; and
a step in which, after completion of the binary search, the digitally controlled oscillator is continuously operated, and the control code is changed such that a phase of the oscillator clock approaches a phase of the reference clock.