Patent ID: 11894846
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 15:
16. A memory device comprising clock distortion calibration circuitry configured to:
detect that a duty cycle calibration (DCC) condition is met, wherein the DCC condition comprises the memory device performing a data write operation and refraining from performing a data read operation based on receiving a command;
after detecting that the DCC condition is met and while executing a DCC operation to adjust a trim value associated with a duty cycle of a voltage signal, detect that the DCC condition is not met;
in response to detecting that the DCC condition is not met, disable the clock distortion calibration circuitry before execution of the DCC operation is complete such that the clock distortion calibration circuitry is disabled (a) from adjusting the trim value as part of the execution of the DCC operation or (b) from using a first adjusted trim value, generated during the execution of the DCC operation, to calibrate the duty cycle of the voltage signal;
after disabling the clock distortion calibration circuitry and while the clock distortion calibration circuitry is disabled, detect that the DCC condition is again met; and
in response to detecting that the DCC condition is met, enable the clock distortion calibration circuitry to execute another DCC operation (i) to adjust the trim value or (ii) to use a second adjusted trim value to calibrate the duty cycle of the voltage signal.