Patent ID: 11880706
Assignee: NANJING QINHENG MICROELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 5:
6. The interrupt control method based on RISC-V according to claim 5, wherein the method of updating the value of the control and status register set in the step (c2) comprises: the control and status register set containing a machine mode status register, and the machine mode status register containing an interrupt enable bit MIE; when MIE=1, maintaining interrupt enable; and when MIE=0, masking the interrupt; and
when any one of the following conditions occurs in the an interrupt response process, setting MIE to be 0; otherwise, setting MIE to be 1:
when the nested interrupt is closed or the first-type memory area does not exist;
when the nested interrupt is opened but the first-type memory area is full; and
when the second-type memory area is full and HS_ENHANCE=0.