Patent ID: 11907139
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 9:
10. A system comprising:
a processor comprising a memory controller;
a first data buffer device;
a first memory channel coupled between the processor and the first data buffer device; and
a dual in-line memory module (DIMM) coupled to the first data buffer device via a second memory channel and a third memory channel, wherein the DIMM comprises a second data buffer device coupled to the first data buffer device via the second memory channel and a third data buffer device coupled to the first data buffer device via the second memory channel, wherein the second data buffer device is to access a first rank of one or more memory devices of the DIMM via the second memory channel and the third data buffer device is to access a second rank of one or more memory devices of the DIMM via the third memory channel.