Patent ID: 11894437
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A structure, comprising:
a substrate with gate structures and source/drain (S/D) structures disposed thereon;
a first dielectric layer comprising a lower conductive structure comprising a ruthenium liner and a cobalt fill, wherein the cobalt fill contacts the ruthenium liner, wherein the ruthenium liner contacts the first dielectric layer, and wherein the lower conductive structure contacts the source/drain (S/D) structures; and
a second dielectric layer comprising a gate conductive structure comprising a ruthenium fill, wherein the gate conductive structure contacts the gate structure, wherein the ruthenium fill contacts the second dielectric layer, and wherein an upper conductive structure contacts the gate conductive structure.