Patent ID: 11886359
Assignee: D-MATRIX CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An AI accelerator apparatus configured with in-memory compute, the apparatus comprising:
a substrate member;
one or N chiplets coupled to the substrate member, where N is an integer greater than 1, each of the chiplets comprising a plurality of tiles, and each of the tiles comprising:
a plurality of slices,
a central processing unit (CPU) coupled to the plurality of slices, and
a hardware dispatch device coupled to the CPU;
a plurality of die-to-die (D2D) interconnects coupled to the each of CPUs in each of the tiles;
a peripheral component interconnect express (PCIe) bus coupled to the CPUs in each of the tiles;
a dynamic random access memory (DRAM) interface coupled to the CPUs in each of the tiles; and
a global reduced instruction set computer (RISC) interface coupled to each of the CPUs in each of the tiles;
wherein each of the slices includes a digital in memory compute (DIMC) device coupled to a clock and configured to allow for a throughput of one or more matrix computations provided in the DIMC device such that the throughput is characterized by a plurality of multiply accumulates per a clock cycle.