Patent ID: 11923372
Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A semiconductor device comprising:
a transistor comprising:
an oxide semiconductor layer comprising a channel formation region;
a first electrode layer below the channel formation region of the oxide semiconductor configured to function as one of a source electrode and a drain electrode; and
a second electrode layer above the channel formation region of the oxide semiconductor configured to function as the other of the source electrode and the drain electrode;

a capacitor comprising:
a dielectric layer;
the first electrode layer below the dielectric layer; and
a third electrode layer above the dielectric layer;

a first layer providing the first electrode layer;
a first insulating layer over the first layer;
a conductive layer over the first insulating layer;
a second insulating layer over the conductive layer;
a second layer over the second insulating layer, the second layer providing the second electrode layer and the third electrode layer;
a first opening and a second opening each penetrating the first insulating layer, the conductive layer and the second insulating layer;
a third insulating layer in contact with a sidewall of the first opening; and
a fourth insulating layer in contact with a sidewall of the second opening,
wherein the oxide semiconductor layer and the third insulating layer are embedded in the first opening,
wherein the dielectric layer and the fourth insulating layer are embedded in the second opening, and
wherein a channel direction of the transistor is perpendicular to a top surface of a substrate.