Patent ID: 11955097
Assignee: SHARP DISPLAY TECHNOLOGY CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A shift register comprising a plurality of stages that operates based on a plurality of clock signals,
wherein each of the plurality of stages comprises a unit circuit including
a first output node,
a first control node,
a second control node,
a first output control transistor having a control terminal connected to the first control node, a first conducting terminal that is supplied with an input clock signal that is one of the plurality of clock signals, and a second conducting terminal connected to the first output node,
a set transistor having a control terminal that is supplied with a set signal that is an output signal that is outputted from a unit circuit comprising a preceding stage, a first conducting terminal that is supplied with the set signal or an ON-level potential, and a second conducting terminal connected to the second control node,
a reset transistor having a control terminal that is supplied with a reset signal that is an output signal that is outputted from a unit circuit comprising a subsequent stage, a first conducting terminal connected to the second control node, and a second conducting terminal that is supplied with an OFF-level potential,
a separation transistor having a control terminal that is supplied with an ON-level potential, a first conducting terminal connected to the first control node, and a second conducting terminal connected to the second control node,
a first capacitor having a first end connected to the first control node and a second end connected to the first output node, and
a second capacitor having a first end connected to the second control node.