Patent ID: 11914973
Assignee: APPLE INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 12:
13. A method, comprising:
retrieving a plurality of weights from a memory array;
pre-charging, by a plurality of multiplier circuits in response to activating corresponding ones of a plurality of activation signals, a global bit line, wherein a given multiplier circuit includes a plurality of device stacks including respective pluralities of devices coupled between the global bit line and a ground supply node, wherein the plurality of activation signals corresponds to a first operand;
receiving, by the given multiplier circuit, a particular weight of the plurality of weights indicative of a second operand;
sinking, by the plurality of device stacks based on corresponding bits included in the particular weight, corresponding currents from the global bit line to modify a voltage level of the global bit line; and
converting, by an analog-to-digital converter circuit, the voltage level of the global bit line to a plurality of bits whose value is indicative of a product of the first operand and the second operand.