Patent ID: 11861239
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A device comprising:
a memory array comprising at least a first memory cell and a second memory cell; and
control logic, operatively coupled with the memory array, the control logic to perform operations comprising:
causing a first threshold voltage state read out of the first memory cell to be converted to a first integer value;
causing a second threshold voltage state read out of the second memory cell to be converted to a second integer value;
indexing, within a decoding table using the first integer value and the second integer value, to determine a set of three logical bits; and
outputting, as a group of logical bits to be returned in response to a read request, the set of three logical bits with a second set of logical bits corresponding to the first threshold voltage state.