Patent ID: 11934675
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A method of evenly balancing a mixed mode in a storage device, comprising:
evaluating a plurality of data blocks within a memory array to be used in the mixed mode, wherein the mixed mode includes a plurality of modes, and wherein the plurality of modes includes a SLC mode and one of a two-or-more-bits-per-cell (2+LC) mode;
determining a first block within the plurality of blocks that has a SLC cycle count that is greater than a corresponding SLC cycle count of other blocks;
erasing the first block into an erased 2+LC data block in the 2+LC mode;
determining a second block within the plurality of blocks that has a 2+LC cycle count that is greater than a corresponding 2+LC cycle count of the other blocks;
erasing the second block into an erased SLC block in the SLC mode;
allocating, in the SLC mode, the second block for storing intermediate data;
wherein each block has a first counter to track SLC mode program/erase cycles and a second counter to track 2+LC mode program/erase cycles; and
wherein values of the first and second counters remain balanced until a maximum threshold number of program/erase cycles of the SLC mode is reached; and
wherein after the maximum threshold number of program/erase cycles of the SLC mode is reached, the block is retired from use in SLC mode and only operates in multiple bit per cell mode thereafter.