Patent ID: 11907062
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A semiconductor system comprising:
a controller configured to:
receive error check scrub (ECS) information from a memory apparatus,
store the ECS information, and
generate ECS resume information comprising address information on which an ECS operation is to be performed based on the ECS information; and

a memory apparatus configured to:
generate the ECS information comprising information with regard to an address at which the ECS operation has been performed based on a command, and
sequentially perform the ECS operation from a region that is selected by the ECS resume information, and
wherein the controller is configured to transmit a count request signal to the memory apparatus before an execution of a power-off operation,
request the ECS information,
receive and store the ECS information, and
wherein the controller is configured to output the ECS resume information to the memory apparatus after a start of a boot-up operation.