Patent ID: 11881273
Assignee: SOCIONEXT INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 14:
15. A semiconductor storage device provided with a read only memory (ROM) cell, comprising:
a word line extending in a first direction;
first and second bit lines extending in a second direction perpendicular to the first direction; and
a ground power supply line extending in the second direction, wherein
the ROM cell includes
a first transistor that is a three-dimensional transistor provided between the first bit line and the ground power supply line, including two transistors lying side by side in the second direction and sharing a first node that is one of a source and a drain,
a second transistor that is a three-dimensional transistor provided between the second bit line and the ground power supply line, including two transistors lying side by side in the second direction and sharing the first node, formed above the first transistor, channel portions of the first and second transistors overlapping each other as viewed in plan,
a first local interconnect that is connected to the first node shared by the two transistors of the first transistor and extends toward a first-oriented direction in the first direction,
a second local interconnect that is connected to the first node shared by the two transistors of the second transistor and extends toward a direction opposite to the first-oriented direction in the first direction,
two third local interconnects that are each connected to a second node that is the other of the source and drain of each of the two transistors of the first transistor and extend toward a second-oriented direction in the first direction, and
two fourth local interconnects that are each connected to the second node of each of the two transistors of the second transistor and extend toward a direction opposite to the second-oriented direction in the first direction,

gates of the first and second transistors are connected to the word line, and
first data is stored in the ROM cell depending on the presence or absence of connection between the first local interconnect and the ground power supply line or the first bit line, and second data is stored in the ROM cell depending on the presence or absence of connection between the second local interconnect and the ground power supply line or the second bit line.