Patent ID: 11941407
Assignee: GSI TECHNOLOGY INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A method for accumulating a plurality N of multiplied M bit values, the method comprising:
for each pair of multiplicands A and B, each of M bits:
in M rows, each of M multiplication units, separately multiplying each bit of said multiplicand A with each bit of said multiplicand B and separately summing results from a previous row of said multiplication units;
in M rows of summing units following said M rows of multiplication units, separately summing results from a previous row of said summing units or said multiplication units, said rows summing output towards an accumulator formed as a column; and
in accumulator units of said accumulator, separately accumulating each bit of a result from the bit output of each row and passing carry values along the bits of said result from the LSB (least significant bit) to the MSB (most significant bit) of said result,
wherein said multiplication units, said summing units and said accumulator units are bit-line processors.