Patent ID: 11971841
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 14:
15. A system comprising:
a first die comprising:
link layer circuitry to implement a link layer of a protocol;
an adapter comprising:
a first interface, wherein link layer data associated with the link layer circuitry is to be communicated over the first interface;
a second interface to couple to a physical layer (PHY) device, wherein the PHY device comprises a plurality of wires to implement a physical layer of a link, the link is to couple the first die to a second die via the PHY device, and the second interface comprises:
a data channel to communicate the link layer data to the PHY device for communication on the link; and
a sideband channel to communicate sideband messages between the adapter and another adapter on the second die; and

circuitry to implement a logical PHY for the link.