Patent ID: 11929347
Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC H

Claim 0:
1. A method of manufacturing two or more base dies on a single wafer comprising:
exposing a first region of a first base die using a first photolithographic-exposure apparatus;
subsequent to exposing the first region of the first base die, exposing a first region of a second base die using the first photolithographic-exposure apparatus;
exposing a second region of the first base die using a second photolithographic-exposure apparatus; and
exposing a second region of the second base die using the second photolithographic-exposure apparatus,
wherein the first photolithographic-exposure apparatus is configured to resolve smaller features with respect to features resolved by the second photolithographic-exposure apparatus.