Patent ID: 11915981
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A semiconductor device, comprising:
a substrate;
a first gate structure over the substrate, wherein the first gate structure comprises:
a first gate dielectric; and
a first work function metal layer over the first gate dielectric, wherein a topmost end of the first gate dielectric is higher than a topmost end of the first work function metal layer;

a second gate structure over the substrate, wherein the second gate structure comprises:
a second gate dielectric;
a second work function metal layer over the second gate dielectric; and
a filling conductor over the second work function metal layer;

first gate spacers on opposite sidewalls of the first gate structure;
second gate spacers on opposite sidewalls of the second gate structure;
a first metal layer over and in contact with the first gate structure; and
a second metal layer over and in contact with the second gate structure, wherein the second metal layer has a top surface level with a top surface of the first metal layer, and a bottom surface higher than a bottom surface of the first metal layer, and wherein the bottom surface of the first metal layer is flatter than the bottom surface of the second metal layer.