Patent ID: 11880669
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A computing system comprising:
a network controller to obtain input code that includes dynamically typed variable information;
a processor coupled to the network controller; and
a memory coupled to the processor, the memory including a set of instructions, which when executed by the processor, cause the computing system to:
generate a first compiler output based on the input code,
generate a second compiler output based on the input code, wherein the second compiler output is to include type check code to verify one or more type inferences associated with the first compiler output, and
execute the first compiler output and the second compiler output in parallel via different threads,
wherein the first compiler output is to further include fallback code to transition the computing system into an execution state that is independent of the one or more type inferences if a verification of the one or more type inferences by the second compiler output fails.