Patent ID: 11966341
Assignee: QUALCOMM INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A computing device, comprising:
a dynamic random-access memory (DRAM);
a static random-access memory (SRAM) of a universal flash storage (UFS) device;
means for determining whether a first logical-to-physical (L2P) table stored in the DRAM is out of synchronization with a second L2P table stored in the SRAM;
means for determining whether the UFS device is configured to enter a hibernate mode in response to determining that the first L2P table is out of synchronization with the second L2P table;
means for retrieving at least one modified L2P map entry from the UFS device in response to the UFS device being configured to enter the hibernate mode, wherein the at least one modified L2P map entry is stored within the second L2P table;
means for updating the first L2P table with the at least one modified L2P map entry; and
means for configuring the UFS device and a link of the UFS device to the computing device to be in the hibernate mode.