Patent ID: 11966737
Assignee: NVIDIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. A multiprocessor configured to be communicatively coupled to a central processing unit and a coprocessor, wherein the multiprocessor is configured to:
establish a connection to the coprocessor, wherein said establishing includes causing the coprocessor to reserve resources on the coprocessor for the operation;
after the connection is established, issue a sequence of write instructions to store input operands for the operation into locations in said reserved resources;
after issuing the sequence of write instructions, issue an operation instruction to cause the coprocessor to execute the operation using said input operands;
issue a plurality of read instructions to read result data of the operation; and
close the connection,, wherein the coprocessor is configured to:
in response to a request from the multiprocessor to establish the connection:
reserve resources on the coprocessor for the operation; and
indicate to the multiprocessor that resources for the operation on the coprocessor have been reserved;

receive the sequence of write instructions, and in response, write the input data into coprocessor-accessible storage locations in the reserved resources;
receive the operation instruction, and in response, execute the operation; and
receive the plurality of read instructions, and in response, write the result data from the coprocessor-accessible storage locations to multiprocessor-accessible storage locations,
wherein the multiprocessor is further configured to issue a macro initiation instruction to cause disabling of interrupts and execution of a predetermined number of instructions following the macro initiation instruction without intervening preemption, and wherein the predetermined number is determined based on an operand of the macro initiation instruction.