Patent ID: 11908605
Assignee: SG MICRO (SUZHOU) LIMITED
Field: Electrical machinery, apparatus, energy (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. A method of fabricating an integrated magnetics (IM) structure, comprising:
etching one or more conductive layers to form patterned metal traces;
embedding the patterned metal traces in a dielectric layer;
laminating the one or more conductive layers between a first magnetic layer and a second magnetic layer;
forming a first magnetic via in a first hole that extends through the first magnetic layer, the dielectric layer, and the second magnetic layer, a first wall of dielectric material being disposed in the first hole and surrounding the first magnetic via;
forming a second magnetic via in a second hole that extends through the first magnetic layer, the dielectric layer, and the second magnetic layer, a second wall of dielectric material being disposed in the second hole and surrounding the second magnetic via, the first magnetic via and the second magnetic via being formed on opposite sides of at least a portion of the patterned metal traces;
providing a level of voltage isolation between the first magnetic via and the patterned metal traces by configuring a thickness of the first wall of dielectric material; and
providing the level of voltage isolation between the second magnetic via and the patterned metal traces by configuring a thickness of the second wall of dielectric material, each of the first magnetic via and the second magnetic via interconnecting the first magnetic layer and the second magnetic layer, thereby defining a flux path as a closed magnetic loop that traverses the first magnetic via, the first magnetic layer, the second magnetic via, and the second magnetic layer and encircles at least the portion of the patterned metal traces.