Patent ID: 11908896
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. An integrated circuit (IC) structure, comprising:
a semiconductor substrate having an IC cell with field-effect transistors (FETs) and a well tap cell surrounding the IC cell;
a doped well continuously extended from the well tap cell to the IC cell such that the IC cell and the well tap cell are within the doped well;
first active regions formed within the well tap cell and second active regions formed on the IC cell;
first source/drain (S/D) features formed on the first active regions and second S/D features formed on the second active regions;
gate stacks formed on the second active regions, wherein the well tap cell is free of any gate electrode;
first contacts formed on the first S/D features and second contacts formed the second S/D features; and
a hard mask disposed on the first active regions and being adjacent the first S/D features.