Patent ID: 11973044
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. The apparatus of claim 5, wherein:
the first semiconductor die has a first end and a second end opposite the first end;
the first semiconductor die has a middle that is between the first end of the first semiconductor die and the second end of the first semiconductor die;
the second semiconductor die has a first end corresponding in location to the first end of the first semiconductor die;
the second semiconductor die has a second end corresponding in location to the second end of the first semiconductor die;
the second semiconductor die has a middle that is between the first end of the second semiconductor die and the second end of the second semiconductor die;
the first top metal layer runs from the first end of the first semiconductor die to the second end of the first semiconductor die;
the first top metal layer connects to I/O pads at the first end of the first semiconductor die;
the first metal interlayer segment is positioned at and connects to the first top metal layer at the second end of the first semiconductor die; and
the first electrical pathway runs from the second interface to the metal transmission layer and then to the electrical circuit at the second end of the second semiconductor die.