Patent ID: 11960856
Assignee: FLEX LOGIX TECHNOLOGIES, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 16:
17. A method of operation within an integrated circuit device having multiply-accumulate circuitry, first data format conversion circuitry, second data format conversion circuitry, first storage circuitry and second storage circuitry, the method comprising:
receiving a plurality of filter weights from the first storage circuitry, each of the filter weights having a first data format and a first bit length;
converting within the first data format conversion circuitry, each of the filter weights having the first data format and the first bit length to a filter weight having a Gaussian floating point data format and a second bit length;
storing, within the second storage circuitry, each of the filter weights having the Gaussian floating point data format and the second bit length;
converting within the second data format conversion circuitry, each of the filter weights having the Gaussian floating point data format and the second bit length to a filter weight having a floating point data format and a third bit length, the third bit length being different from the second bit length; and
executing a plurality of multiply and accumulate operations within the multiply-accumulate circuitry, including multiplying input data with the filter weights having the floating point data format and the third bit length.