Patent ID: 11907154
Assignee: QUALCOMM INCORPORATED
Field: Digital communication (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A clock and data recovery apparatus, comprising:
an oscillator configured to generate a base clock signal with a base frequency;
a clock gating circuit responsive to one or more control inputs and configured to output a gated base clock signal while the clock gating circuit is enabled;
a first counter clocked by the gated base clock signal and configured to provide a counter output that reflects a count of positive and negative edges in the gated base clock signal;
control logic coupled to a first control input of the clock gating circuit and configured to disable the clock gating circuit when the counter output corresponds to a maximum count value; and
an edge synchronization circuit coupled to a one-wire bus and configured to:
ignore edges in a signal received from the one-wire bus while the counter output has a value that is less than the maximum count value; and
reset the first counter in response to an edge detected in the signal received from the one-wire bus.