Patent ID: 11922992
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 2:
3. The memory device of claim 2, wherein the plurality of sub word line driving signals comprise a plurality of first sub word line driving signals obtained by delaying the plurality of sub word line signals and a plurality of second sub word line driving signals obtained by inverting the plurality of sub word line signals,
wherein the plurality of encoded sub word line driving signals comprise a plurality of first encoded sub word line driving signals and a plurality of second encoded sub word line driving signals, and
wherein the row address decoder comprises a sub word line driving signal encoder configured to encode the plurality of first encoded sub word line driving signals based on the plurality of first sub word line driving signals and encode the plurality of second encoded sub word line driving signals based on the plurality of second sub word line driving signals.