Patent ID: 11881507
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 9:
10. A method, comprising:
forming a multi-layer structure having alternating channel layers and sacrificial layers over a substrate;
patterning the multi-layer structure to form a semiconductor fin;
forming a first placeholder gate directly over a first region of the semiconductor fin and a second placeholder gate directly over a second region of the semiconductor fin;
removing the first placeholder gate and the first region of the semiconductor fin to form a trench;
forming a dummy feature in the trench;
selectively removing the second placeholder gate and the sacrificial layers in the second region of the semiconductor fin to form gate openings;
forming a metal gate structure in the gate openings; and
after the forming of the metal gate structure, replacing the dummy feature with an isolation structure.