Patent ID: 11937334
Assignee: ASUSTEK COMPUTER INC.
Field: Digital communication (Electrical engineering)
Classification: CPC H  Y | IPC H

Claim 8:
9. A User Equipment (UE), comprising:
a memory; and
a processor operatively coupled to the memory, wherein the processor is configured to execute program code to:
perform a Sidelink (SL) communication associated with a destination Identity (ID);
have, or be configured with, a SL Discontinuous Reception (DRX) configuration for at least an on-duration timer and a DRX cycle associated with the SL communication;
derive a first offset associated with the SL communication based on the destination ID and the DRX cycle;
derive a second offset associated with the SL communication based on the destination ID and a number of slots per subframe, wherein at least one of:
the second offset is derived by a first value divided by the number of slots per subframe, wherein the first value is a remainder of the destination ID divided by the number of slots per subframe; or
the second offset is set to (the destination ID modulo the number of slots per subframe)/(the number of slots per subframe);

start the on-duration timer after a time period determined based on the second offset from the beginning of a subframe, wherein the subframe is determined based on at least the first offset; and
monitor Sidelink Control Information (SCI) when the on-duration timer is running.