Patent ID: 11881967
Assignee: FRAUNHOFER GESELLSCHAFT ZUR FÖRDERUNG DER ANGEWANDTEN FORSCHUNG E.V.
Field: Digital communication (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 18:
19. A non-transitory storage unit storing instruction which, when executed by a processor, cause the processor to:
generate a transmit signal on the basis of a first sequence,
acquire a receive signal and to multiply the receive signal with a second sequence, to acquire a modified receive signal, wherein the second sequence is different from the first sequence;
analog-to-digital, ADC, convert an integration result in order to acquire a sample value, the integration result being based on an integration of the modified receive signal over a period of time; and
acquire an estimate of the linear system impulse response on the basis of a plurality of sample values,
wherein the first sequence and the second sequence are synchronized with each other and/or are generated from a common system clock signal and/or are synchronized with a common system clock signal,
wherein a clock division is performed by dividing the common system clock signal by a first divider factor parameter to acquire a sampling clock signal to control the ADC conversion and/or to define the period of time of the integration of the modified receive signal,
wherein the first sequence is associated with a first linear signal model, and the second sequence is associated with a second linear model, so as to acquire the estimate of the impulse response on the basis of a relationship between the plurality of sample values, the first linear signal model, and the second linear model,
wherein the first linear model is described by a first sparse representation operator and the second linear model is described by a second sparse representation operator,
wherein the first sparse representation operator is acquired through a factorization which involves at least one Hadamard matrix or Hadamard transform.