Patent ID: 11908948
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A memory device, comprising:
a stack structure including tiers each comprising conductive material and insulative material vertically neighboring the conductive material, the stack structure having a memory array region and a staircase region horizontally neighboring the memory array region;
strings of memory cells within a horizontal area of the memory array region and vertically extending through the stack structure;
a staircase structure within a horizontal area of the staircase region and having steps comprising horizontal ends of at least some of the tiers of the stack structure;
conductive contact structures in contact with the conductive material of the at least some of the tiers of the stack structure at the steps of the staircase structure; and
vertical transistors vertically overlying the stack structure and within the horizontal area of the staircase region, at least one of vertical transistors comprising:
indium-containing material having:
a bottom section coupled to one of the conductive contact structures;
a top section vertically overlying the bottom section; and
a middle section vertically extending from and between the bottom section and the top section, the middle section having a lower atomic concentration of indium than each of the bottom section and the top section;

conductive gate material horizontally neighboring and within vertical boundaries of the middle section of the indium-containing material; and
gate dielectric material horizontally extending from and between the middle section of the indium-containing material and the conductive gate material, the middle section of the indium-containing material and the gate dielectric material each substantially confined within a horizontal area of the bottom section of the indium-containing material.