Patent ID: 11948939
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. An integrated circuit, comprising:
a substrate;
first and second n-type source/drain (S/D) regions disposed on or in the substrate;
first and second p-type S/D regions disposed on or in the substrate; and
a dual gate structure disposed between the first and second n-type S/D regions and between the first and second p-type S/D regions, wherein the dual gate structure comprises:
a first gate structure comprising a first gate dielectric layer and a first gate fill material; and
a second gate structure comprising a second gate dielectric layer and a second gate fill material that is different from the first gate fill material,
wherein a vertical sidewall of the first gate dielectric layer is in contact with a vertical sidewall of the second dielectric layer.