Patent ID: 11862623
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 9:
10. A method, comprising:
arranging a plurality of gate structures above a first active region, a second active region and a non-active region of a substrate of a semiconductor structure, wherein the first and second active regions are spaced apart by the non-active region;
arranging a plurality of contacts above the first and second active regions;
arranging a first separation spacer between the plurality of contacts;
arranging at least one first gate via above the first active region or the second active region, wherein the at least one first gate via is electrically coupled with at least one of the plurality of gate structures; and
selectively arranging at least one local interconnect over the non-active region, to couple a first contact of the plurality of contacts above the first active region to a second contact of the plurality of contacts above the second active region.