Patent ID: 11886885
Assignee: NVIDIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A data pipeline, comprising:
a first mousetrap element and a second mousetrap element included in a first pipeline stage, wherein each of the first mousetrap element and the second mousetrap element comprises:
a request latch that, when enabled, allows a request signal to pass from the first pipeline stage to a second pipeline stage that follows the first pipeline stage in the data pipeline;
a data latch that, when enabled, allows a data element to pass from the first pipeline stage to the second pipeline stage; and
a latch controller that, in operation, enables and disables the request latch and the data latch based on a phase signal, wherein the phase signal alternates between a first value that enables the first mousetrap element to transmit data to the second pipeline stage and a second value that enables the second mousetrap element to transmit data to the second pipeline stage.