Patent ID: 11960392
Assignee: AMAZON TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A system-on-a-chip (SoC) comprising:
a set of source nodes configured to issue transactions;
a first interconnect fabric coupled to a first set of target nodes;
a first set of address decoders, wherein each address decoder in the first set of address decoders is coupled to a corresponding source node in the set of source nodes, and to the first interconnect fabric;
a second interconnect fabric coupled to a second set of target nodes; and
a second set of address decoders coupled between the first interconnect fabric and the second interconnect fabric, wherein the second set of address decoders is part of the first set of target nodes,
wherein each address decoder in the first set of address decoders is configured with a respective first address mapping table that maps a respective first set of address ranges to the first set of target nodes coupled to the first interconnect fabric,
wherein each address decoder in the second set of address decoders is configured with a respective second address mapping table that maps a respective second set of address ranges to the second set of target nodes coupled to the second interconnect fabric, and
wherein one or more address mapping tables in the first set of address decoders or in the second set of address decoders are reconfigurable to allow routing of transactions through the first interconnect fabric or the second interconnect fabric to be modified.