Patent ID: 11916124
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC B  H | IPC H

Claim 13:
14. A method comprising:
depositing a first gate dielectric material around a first nanostructure and a second gate dielectric material around a second nanostructure, the first nanostructure being disposed over the second nanostructure, the first gate dielectric material being spaced apart from the second gate dielectric material by a gap; and
depositing a p-type work function metal on the first gate dielectric material and the second gate dielectric material, wherein depositing the p-type work function metal comprises continuously depositing the p-type work function metal until a seam is defined between the first gate dielectric material and the second gate dielectric material and the p-type work function metal fills an entirety of the gap separating the first gate dielectric material and the second gate dielectric material, wherein depositing the p-type work function metal comprises depositing the p-type work function metal to have:
a first thickness between the first nanostructure and the second nanostructure; and
a minimum width between the first nanostructure and the second nanostructure, wherein a ratio of the first thickness to the minimum width is in a range of 0.03 to 1, and wherein the minimum width is measured in a first direction, and wherein the first thickness is measured in a second direction perpendicular to the first direction.