Patent ID: 11908525
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  B | IPC G  H

Claim 0:
1. A method for controlling a memory device,
the memory device, including:
a memory cell array including a memory block, the memory block including a first sub memory block and a second sub memory block, the first sub memory block including a plurality of first memory cells, and the second sub memory block including a plurality of second memory cells;
a first drain side selective transistor connected to the first memory cells;
a second drain side selective transistor connected to the second memory cells;
a first source side selective transistor connected to the first memory cells;
a second source side selective transistor connected to the second memory cells;
a first source line connected to the first source side selective transistor and the second source side selective transistor;
a plurality of first word lines connected to gates of the first memory cells;
a plurality of second word lines connected to gates of the second memory cells;
a plurality of first control gate lines connected to the plurality of first word lines not via any of the plurality of the second word lines;
a plurality of second control gate lines connected to the plurality of second word lines not via any of the plurality of the first word lines;
a first source side select gate line connected to a gate of the first source side selective transistor; and
a second source side select gate line connected to a gate of the second source side selective transistor;
the method including:
performing an erase operation of erasing data stored in the plurality of first memory cells in the first sub memory block, while erasing data stored in the plurality of second memory cells in the second sub memory block being prohibited.