Patent ID: 11907744
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A system comprising:
a processor comprising:
an execution circuit, in response to a first instruction, to obtain command data from a first location identified in a source operand of the first instruction, access an entry of a process address space (PASID) table using a handle included in the command data and a pointer to obtain a PASID value and quality of service (QoS) information associated with an issuer of the first instruction, insert the PASID value and the QoS information into the command data and send a request comprising the command data to a device;

the device coupled to the processor, wherein the device comprises:
a front end circuit to receive and handle the request based at least in part on the QoS information, the front end circuit including a plurality of registers, wherein the front end circuit is to select the command data of the request to send to a first processing circuit of the device based at least in part on the QoS information; and

a system memory coupled to the processor.