Patent ID: 11881851
Assignee: HRL LABORATORIES, LLC
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A signal processing circuit, comprising:
a sample and hold circuit comprising:
a hold capacitor;
an input switch connected between a common input node and the hold capacitor;
a signal path amplifier having an input connected to the hold capacitor; and
an output switch connected between an output of the signal path amplifier and a common output node,

an input of a voltage feedback amplifier being connected to the hold capacitor, and
an output of the voltage feedback amplifier being operatively coupled to an internal node of the input switch,
wherein the input switch comprises:
a first series switch;
a second series switch; and
a voltage feedback switch,
the first series switch being connected between the common input node and the internal node,
the second series switch being connected between the internal node and the hold capacitor, and
the voltage feedback switch being connected between the output of the voltage feedback amplifier and the internal node, and

a clock circuit having an input, a first output and a second output, the clock circuit being configured to receive a reference clock signal and to produce:
at the first output, a first clock signal having the same frequency as the reference clock signal,
at the second output, a second clock signal having the same frequency as the reference clock signal,

the first output being operatively coupled to one or more control terminals of the first series switch and of the second series switch, and
the second output being operatively coupled to the voltage feedback switch.