Patent ID: 11864393
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 4:
5. The memory device of claim 1, wherein
the controller is configured to, in a reset operation of a selected data storage element among the plurality of data storage elements,
apply a turn-ON voltage via the at least one word line to the gate of the first transistor to turn ON the first transistor,
apply a further turn-ON voltage via the corresponding select bit line to the gate of the second transistor corresponding to the selected data storage element,
apply a turn-OFF voltage via the corresponding select bit lines to the gates of other second transistors among the plurality of second transistors, and
while the first transistor and the second transistor corresponding to the selected data storage element are turned ON and the other second transistors are turned OFF, apply a reset voltage to the at least one bit line to switch a datum stored in the selected data storage element from a first logic value to a second logic value.