Patent ID: 11961577
Assignee: NXP USA, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 14:
15. The integrated circuit of claim 14, wherein the ADC under test is characterized as SARADC, which requires M-bit resolution from the N-bit differential DAC during ADC testing, the memory engine is further configured to, during ADC testing:
access a first address line from the on-chip memory addressed by N−1 upper significant bits of a test DAC input code for the testing of the SARADC, wherein the N−1 upper significant bits of the first test DAC input code is capable of addressing only a first portion of memory locations of the on-chip memory; and
provide a selected pair of calibration codes corresponding to the test DAC input code from one or more predetermined byte locations of the accessed first address line to calibrate the N-bit differential DAC.