Patent ID: 11894331
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A chip package structure, comprising:
a wiring substrate; and
a chip structure over the wiring substrate, wherein the chip structure comprises:
a substrate;
an interconnect layer under the substrate;
a first conductive pad under the interconnect layer; and
a conductive bump connected between the first conductive pad and the wiring substrate, and the conductive bump has a first portion, a second portion, and a neck portion between the first portion and the second portion, a first width of the first portion decreases toward the neck portion, a second width of the second portion decreases toward the neck portion,
the wiring substrate comprises a second conductive pad, the conductive bump is connected between the first conductive pad and the second conductive pad, and a first center portion of the first conductive pad is misaligned with a second center portion of the second conductive pad relative to an axis perpendicular to a surface of the substrate, and the interconnect layer is under the surface.