Patent ID: 11960739
Assignee: APPLE INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. A system comprising:
a memory subsystem including a memory coupled to a memory controller, wherein the memory controller includes a calibration circuit configured to perform reference voltage calibrations, wherein, in performing the reference voltage calibrations, the calibration circuit is configured to:
perform a plurality of horizontal calibrations at different reference voltage values, and wherein ones of the horizontal calibrations comprise determining a range of delay values applied to a data strobe signal at which valid data is read from the memory;
determine scores corresponding to ones of the plurality of horizontal calibrations, wherein a score for a particular one of the plurality of horizontal calibrations is based on a corresponding range of delay values and a reference voltage margin; and
select a calibrated reference voltage based on the scores corresponding to ones of the plurality of horizontal calibrations.