Patent ID: 11915946
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A device comprising:
a vertical stack of nanostructures over a substrate, the vertical stack of nanostructures extending between a first source/drain region and a second source/drain region, wherein the first source/drain region and the second source/drain region extend into the substrate, wherein the nanostructures comprise:
a bottom nanostructure;
a middle nanostructure, wherein the bottom nanostructure is disposed between the substrate and the middle nanostructure; and
a top nanostructure, wherein the middle nanostructure is disposed between the bottom nanostructure and the top nanostructure, wherein thicknesses of the nanostructures progressively increase from a bottom to a top of the vertical stack of nanostructures, wherein the bottom of the vertical stack of nanostructures is closer to the substrate than the top of the vertical stack of nanostructures, and wherein a thickness of one nanostructure is 1.05 times to 1.3 times a thickness of an adjacent nanostructure;

a gate electrode surrounding each of the vertical stack of nanostructures, wherein a first portion of the gate electrode and a second portion of the gate electrode is separated by the top nanostructure, wherein a first spacer extends along a first sidewall of the first portion of the gate electrode, wherein a second spacer extends along a first sidewall of the second portion of the gate electrode, and wherein the first spacer and the second spacer comprise different materials; and
a gate dielectric separating the gate electrode from the vertical stack of nanostructures.