Patent ID: 11923024
Assignee: GLOBALFOUNDRIES U.S. INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 15:
16. A method, comprising:
clocking a level-sensitive register unit coupled to a memory with a first clock signal and a second clock signal, the level-sensitive register unit including a data latch coupled to a flip-flop, the flip-flop including a first latch and a second latch, wherein the data latch is clocked by the first clock signal, the first latch of the flip-flop is clocked by an inverse of the second clock signal, and the second latch of the flip-flop is clocked by the second clock signal; and
clocking the memory with the second clock signal,
wherein a frequency of the first clock signal is 2× a frequency of the second clock signal.