Patent ID: 11862592
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. An integrated chip (IC), comprising:
a semiconductor substrate;
an interconnect structure disposed over the semiconductor substrate;
a first dielectric layer disposed over the interconnect structure, wherein an upper surface of a conductive feature of the interconnect structure is at least partially disposed between opposite sidewalls of the first dielectric layer;
a sidewall spacer disposed along the opposite sidewalls of the first dielectric layer, wherein a thickness of the sidewall spacer continuously decreases from a lower portion of the sidewall spacer to an upper portion of the sidewall spacer;
a conductive structure electrically coupled to the conductive feature of the interconnect structure, wherein the conductive structure is disposed over the first dielectric layer, over the sidewall spacer, and over the upper surface of the conductive feature of the interconnect structure; and
a second dielectric layer disposed between the first dielectric layer and the interconnect structure, wherein the conductive structure is disposed along opposite sidewalls of the second dielectric layer, and wherein the lower portion of the sidewall spacer contacts an upper surface of the second dielectric layer.