Patent ID: 11923292
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A semiconductor package comprising:
a package substrate including an interconnection pattern therein;
a metal pattern on an upper surface of the package substrate and electrically connected to the interconnection pattern, the metal pattern comprising at least one metal pad;
a semiconductor substrate vertically spaced apart from on the upper surface of the package substrate;
a conductive pad disposed on a lower surface of on the semiconductor substrate;
a protective layer disposed on the lower surface of the semiconductor substrate and covering a side surface of the conductive pad and an edge portion of a lower surface of the conductive pad, the protective layer having a pad opening exposing a center portion of the lower surface of the conductive pad;
a connection terminal between the conductive pad and the metal pattern; and
a polymer layer disposed between the package substrate and the protective layer,
wherein the connection terminal comprises:
a pillar pattern disposed in the pad opening and being in contact with the center portion of lower surface the conductive pad; and
a solder pattern being in contact with the metal pattern and provided between the metal pattern and the pillar pattern,
wherein a width of a lower portion of the pillar pattern is greater than a width of a upper portion of the pillar pattern,
and
wherein the solder pattern includes:
a solder seed pattern including copper and spaced apart from an edge portion of a lower surface of the pillar pattern; and
a solder material including at least one of tin, bismuth, lead, and silver, and in contact with the edge portion of the lower surface of the pillar pattern.