Patent ID: 11960392
Assignee: AMAZON TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A method performed by an integrated circuit, comprising:
receiving, by a first address decoder, a transaction from a source node, wherein the first address decoder is communicatively coupled between the source node and a first interconnect fabric, wherein the first address decoder is configured with a first address mapping table that maps a first set of address ranges to a first set of target nodes coupled to the first interconnect fabric, and wherein the transaction includes a destination address targeted to a second target node in a second set of target nodes coupled to a second interconnect fabric;
determining, by the first address decoder, that the destination address maps to a first target node in the first set of target nodes, wherein the first target node corresponds to a second address decoder, the second address decoder communicatively coupled between the first interconnect fabric and the second interconnect fabric, and wherein the second address decoder is configured with a second address mapping table that maps a second set of address ranges to the second set of target nodes;
providing, by the first address decoder, a first target node identifier (ID) identifying the first target node to the first interconnect fabric to route the transaction to the second address decoder;
receiving, by the second address decoder, the transaction from the first interconnect fabric;
determining, by the second address decoder, that the destination address of the transaction maps to the second target node; and
providing, by the second address decoder, a second target node ID identifying the second target node to the second interconnect fabric to route the transaction to the second target node.