Patent ID: 11960855
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. An apparatus for performing deep learning operations, the apparatus comprising:
a systolic array comprising a plurality of multiplier accumulator (MAC) units;
a multiplexer set connected to the plurality of MAC units; and
a control circuit configured to control an operation of the multiplexer set and the plurality of MAC units according to a plurality of operation modes,
wherein each MAC unit comprises an adder and an accumulator that is separate from the adder, the accumulator is configured to perform an accumulating convolution operation of a respective channel for depthwise convolution of plural channels, where all accumulating convolution operations performed by the respective accumulators are distinct from adding operations performed by the respective adders
wherein the multiplexer set comprises:
a plurality of first multiplexers, each first multiplexer is connected to an input terminal of an adder of each respective MAC unit of the plurality of MAC units;
a plurality of second multiplexers, each second multiplexer is connected to an output terminal of an accumulator of each respective MAC unit of the plurality of MAC units; and
a third multiplexer, connected to output terminals of the plurality of MAC units, and receive an output of each respective MAC unit of the plurality of MAC units as input.