Patent ID: 11861209
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 4:
5. The memory system of claim 1, wherein the controller comprises:
a flash translation layer configured to generate the address map table by mapping the physical address of the page and the logical address to each other, and to store the address map table in the system memory;
an error correction circuit configured to perform the error correction operation on data received from the memory device;
a recovery circuit configured to recover the first meta data of the first chunk using the physical address of the first chunk and the address map table stored in the system memory, when a fail signal is output from the error correction circuit; and
a central processing unit configured to control the flash translation layer, the error correction circuit, and the recovery circuit, and to generate a program command, read command, erase command, or combinations thereof.