Patent ID: 11955462
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A device comprising:
a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness;
a second stacked layer including one or more semiconductor dies, components or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer, wherein the second dielectric layer is not vertically in between the one or more semiconductor dies, components or both of the first stacked layer and the one or more semiconductor dies, components or both of the second stacked layer;
a first through mold via in the first dielectric layer, the first through mold via laterally spaced apart from a first lateral sidewall of the one or more semiconductor dies, components or both of the first stacked layer, wherein the first through mold via extends above a top of the one or more semiconductor dies, components or both of the first stacked layer, and wherein the first through mold via does not extend below a bottom of the first dielectric layer; and
a second through mold via in the first dielectric layer, the second through mold via laterally spaced apart from a second lateral sidewall of the one or more semiconductor dies, components or both of the first stacked layer, wherein the second through mold via extends above the top of the one or more semiconductor dies, components or both of the first stacked layer, and wherein the second through mold via does not extend below the bottom of the first dielectric layer.