Patent ID: 11894077
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. The memory apparatus as set forth in claim 5, wherein the control means is further configured to:
start the program operation,
determine the quantity of the plurality of smart verify loops needed to complete programming of the memory cells associated with the first one of the plurality of strings,
determine whether the one of the plurality of planes failed the leak detection operation,
disable the one of the plurality of planes in response to determining the one of the plurality of planes failed the leak detection operation,
discard the smart verify programming voltage in response to determining the leak detection operation should not be triggered,
discard the smart verify programming voltage in response to determining the one of the plurality of planes failed the leak detection operation,
determine the another smart verify programming voltage in another smart verify operation on the memory cells associated with the second one of the plurality of strings, and
end the program operation following the determining another smart verify programming voltage in the another smart verify operation on the memory cells associated with the second one of the plurality of strings.