Patent ID: 11959939
Assignee: NANYA TECHNOLOGY CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 4:
5. A testing fixture comprising:
a first circuit board; and
a chip socket mounted on the first circuit board, and the chip socket comprising:
a pedestal having a first surface and a second surface;
a plurality of conductive traces formed in the pedestal;
a plurality of clamp structures disposed on the first surface of the pedestal, and at least one of the plurality of clamp structures being coupled to a corresponding conductive trace of the plurality of conductive traces and configured to clamp a solder ball of a chip to be tested, wherein the plurality of clamp structures are conductive; and
a plurality of electrical contacts disposed on the second surface of the pedestal, and at least one of the plurality of electrical contacts being coupled to a corresponding clamp structure of the plurality of clamp structures through a corresponding conductive trace of the plurality of conductive traces;
wherein the clamp structure of the plurality of clamp structures comprises:
a conductive body embedded in the pedestal; and
a gap formed in a middle of the conductive body and surrounded by first and second sidewalls of the conductive body, wherein the first sidewalls are longer than the second sidewalls, the first sidewalls and the second sidewalls are contacted with each other so that the gap includes a closed opening with a first width and a bottom with a second width;
wherein when the solder ball of the chip to be tested is not inserted into the gap of the clamp structure, the first width of the closed opening of the gap and the second width of the bottom of the gap are identical, the first width of the closed opening of the gap and the second width of the bottom of the gap are smaller than a third width of the solder ball of the chip to be tested;
wherein when the solder ball of the chip to be tested is inserted into the gap of the clamp structure, the first and second sidewalls surrounding the gap are deformed to increase the first width of the closed opening of the gap to accommodate and clamp the solder ball of the chip to be tested, wherein the first width of the closed opening of the gap is increased to be greater than the second width of the bottom of the gap.