Patent ID: 11942527
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 7:
8. An integrated chip comprising:
a first source/drain region;
a second source/drain region spaced apart from the first source/drain region;
a channel structure extending between the first source/drain region and the second source/drain region;
a gate electrode arranged over the channel structure;
a first upper interconnect contact arranged over and coupled to the gate electrode; and
a backside contact arranged below and electrically coupled to the first source/drain region; and
wherein an upper surface of the first source/drain region and an upper surface of the second source/drain region nearest the first upper interconnect contact are co-planar with one another and are co-planar with an upper surface of the channel structure.