Patent ID: 11928412
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A design method, applied to a capacitor array comprising a plurality of preset capacitor units, each of the preset capacitor units comprising a plurality of unit capacitors, the design method comprising:
acquiring unit simulation models of the preset capacitor units for representing capacitances of the preset capacitor units;
acquiring a first simulation model of the capacitor array based on an arrangement manner of the preset capacitor units in the capacitor array and the unit simulation models of the preset capacitor units, the first simulation model being used to represent a corresponding capacitance of each of the preset capacitor units in the capacitor array and the arrangement manner of the preset capacitor units;
acquiring an arrangement direction of the preset capacitor units based on the arrangement manner of the preset capacitor units, establishing a parasitic resistance equivalent test structure of a group of preset capacitor units in a same arrangement direction;
obtaining a parasitic resistance of each of the preset capacitor units based on the parasitic resistance equivalent test structure; and
establishing a second simulation model representing the capacitor array based on the parasitic resistance of each of the preset capacitor units, and the first simulation model.