Patent ID: 11960755
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. The semiconductor memory device of claim 3, wherein the storage controller comprises:
an address comparator configured to sequentially compare the value of the input address with the values of the addresses stored in the respective ‘K’ address latches and to generate ‘K’ comparison signals corresponding to a comparison result;
a counter controller configured to control a counting operation of each of the ‘K’ counters in response to each of the ‘K’ comparison signals and to adjust the ‘K’ counting values and values of ‘K’ items of count operation information generated by the respective ‘K’ counters; and
a latch controller configured to control a storage operation of each of the ‘K’ address latches in response to each of the ‘K’ items of count operation information, to selectively store the input address in each of the ‘K’ address latches.