Patent ID: 11937514
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Field: nan (nan)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor structure, the semiconductor structure comprising:
two adjacent bottom electrodes in a layer of a first dielectric material and above a metal layer;
two adjacent pillars are each on one of the two adjacent bottom electrodes, wherein each pillar of the two adjacent pillars is composed of a stack of materials for a memory device;
a spacer on the first dielectric layer, on a top portion of the two adjacent bottom electrodes, and around vertical sides of the two adjacent pillars;
a second dielectric material around vertical sides of the spacer and on the layer of the first dielectric material between the two adjacent bottom electrodes, wherein the second dielectric material fills at least a first portion of a gap between the two adjacent pillars; and
a low k material covering the second dielectric material and exposed portions of the layer of the first dielectric material.