Patent ID: 11956968
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A memory device, comprising:
a layer stack disposed on a substrate, wherein the layer stack comprises a first dielectric layer, a first source/drain (S/D) layer, a second dielectric layer, and a second S/D layer stacked in order;
a first conductive pillar, penetrating through the layer stack;
a first ferroelectric layer, wrapping the first conductive pillar;
a first channel layer, disposed between the layer stack and the first ferroelectric layer, wherein the first ferroelectric layer is in contact with the first channel layer and the first conductive pillar; and
a first isolation structure, penetrating through in the first conductive pillar to divide the first conductive pillar into two individual first gate pillars, wherein the first isolation structure further divides the first ferroelectric layer into two individual ferroelectric pillars, and divides the first channel layer into two individual channel pillars.