Patent ID: 11877434
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. An apparatus, comprising:
a memory cell array comprising microelectronic devices, at least one of the microelectronic devices comprising:
features comprising silicon, each feature of at least one pair of the features comprising:
a lower portion with a tapering sidewall adjacent a trench at least partially filled with insulative material; and
a fin portion above the lower portion, the fin portion comprising a sidewall defining a different slope above the insulative material than a slope of the tapering sidewall of the lower portion of the feature; and

elongate conductive structures above the features, the elongate conductive structures comprising portions laterally adjacent the fin portion of the each feature of the at least one pair of the features, the elongate conductive structures being arranged parallel to one another and parallel to a first horizontal axis;
doped features comprising the silicon and at least one dopant, the doped features spacing the elongate conductive structures from one another along a second horizontal axis perpendicular to the first horizontal axis; and
within the trench, at least one additional elongate conductive structure extending substantially perpendicular to the elongate conductive structures,
wherein:
the at least one additional elongate conductive structure comprises one or more of titanium (Ti), tungsten (W), ruthenium (Ru), cobalt (Co), an alloy of any of the foregoing, or one or more compounds or combinations of any of the foregoing,
the insulative material is interposed between the at least one additional elongate conductive structure and the lower portion of the feature, and
the doped features extend to a higher elevation than the fin portions of the features.