Patent ID: 11955417
Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An electronic device, comprising:
a substrate, having a plurality of inner vias, wherein the inner vias comprise a plurality of ground vias, at least one signal via, and a plurality of floating vias, and the substrate has an upper surface and a lower surface;
an upper conductive layer, comprises:
an upper ground trace, disposed on the upper surface, wherein the upper ground trace is electrically connected to at least one ground via of the plurality of the ground vias, the upper ground trace has at least one upper hollow portion, and the at least one upper hollow portion exposes a part of the upper surface; and
at least one upper signal pad, disposed on the part of the upper surface exposed by the at least one upper hollow portion, wherein the at least one upper signal pad is electrically connected to the at least one signal via;

a lower conductive layer, comprises:
a lower ground trace, disposed on the lower surface, wherein the lower ground trace is electrically connected to at least one ground via of the plurality of the ground vias, the lower ground trace has at least one lower hollow portion, and the at least one lower hollow portion exposes a part of the lower surface; and
at least one lower signal pad, disposed on the part of the lower surface exposed by the at least one lower hollow portion, wherein the at least one lower signal pad is electrically connected to the at least one signal via; and
an upper outer layer, having at least one upper outer via, wherein the upper outer layer covers the upper conductive layer and the substrate, and the at least one upper outer via is electrically connected to the at least one upper signal pad;

wherein the floating vias are electrically insulated from the upper conductive layer and the lower conductive layer and electrically floating.