Patent ID: 11972834
Assignee: QUALCOMM INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 18:
19. A level-shifting pulse latch, comprising:
a system-power-domain latch configured to latch a memory select signal to form a pass transistor control signal;
a clock path circuit configured to produce a pair of internal clock signals to control the system-power-domain latch to be transparent while a system clock signal is discharged and a reset signal is not asserted, and to control the system-power-domain latch to be closed while the system clock signal is charged to a system power supply voltage;
a pass transistor configured to switch on to pass an inverted version of the system clock signal to form a latch input signal on an input signal node responsive to an assertion of the pass transistor control signal, and
a memory-power-domain latch configured to latch the latch input signal to provide a self-timed memory clock signal for a memory.