Patent ID: 11916100
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A method for forming an integrated chip, the method comprising:
forming a dielectric structure over a substrate;
patterning the dielectric structure to form a trench in the dielectric structure, the trench having a first side and a second side opposite the first side;
depositing a first electrode comprising a first conductive material in the trench and over the dielectric structure;
depositing a first insulative layer in the trench and over the first electrode;
depositing a second electrode comprising a second conductive material, different from the first conductive material, in the trench and over the first insulative layer;
depositing a second insulative layer in the trench and over the second electrode;
depositing a third electrode comprising the first conductive material in the trench and over the second insulative layer;
depositing a third insulative layer in the trench and over the third electrode;
depositing a fourth electrode comprising the second conductive material in the trench and over the third insulative layer;
laterally recessing the first electrode and the third electrode at sidewalls of the first electrode and the third electrode that are on the second side of the trench with a first etching process;
laterally recessing the second electrode and the fourth electrode at sidewalls of the second electrode and the fourth electrode that are on the first side of the trench with a second etching process different from the first etching process;
forming a first contact on the first side of the trench that is coupled to the first electrode and the third electrode; and
forming a second contact on the second side of the trench that is coupled to the second electrode and the fourth electrode.