Patent ID: 11901035
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 18:
19. A method of controlling temperatures in a high bandwidth memory (HBM) that includes core dies arranged in a stack, each core die including banks, and each bank including memory cells, the HBM further including at least first and second sensing units arranged correspondingly within the core dies, the method comprising:
from a first sensing unit arranged within the HBM, receiving a first threshold voltage corresponding to at least a first transistor in a corresponding at least a first one of the memory cells;
from a second sensing unit arranged within the HBM, receiving a second threshold voltage corresponding to at least a second transistor in a corresponding at least a second one of the memory cells;
for a first set of one or more of the memory cells which includes the first memory cell, controlling a temperature of the first set by adjusting one or more first transistor-temperature-affecting (TTA) parameters of the first set based on the one or more first environmental signals first threshold voltage; and
for a second set of one or more of the memory cells which includes the second memory cell, controlling a temperature of the second set by adjusting one or more second TTA parameters of the second set based on the second threshold voltage.