Patent ID: 11908545
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. An operating method for computing-in-memory (CIM) of a memory device, wherein the memory device comprises a plurality of memory banks and a global multiply accumulate (MAC) circuit, wherein each of the plurality of memory banks comprises first memory array, a first latch circuit, a second latch circuit and a local MAC circuit, wherein the operating method comprises:
latching, using the first latch circuit, a first data from the first memory array in a first read cycle;
latching, using the second latch circuit, a second data from the first memory array in a second read cycle in a second read cycle different from the first read cycle;
performing, using the local MAC circuit, a first stage CIM operation on at least one of a first latched data latched in the first latch circuit and a second latched data latched in the second latch circuit to provide a first CIM result; and
performing, using the global MAC circuit, a second stage CIM operation on a plurality of first stage CIM results from the plurality of memory banks.