Patent ID: 11934343
Assignee: SAMBANOVA SYSTEMS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 1:
2. The data processing system of claim 1, wherein the runtime logic is further configured to:
execute a second forward subgraph in the sequence of forward subgraphs of the graph in a second forward topology of tiling configurations to forward propagate a second set of input tiles through a second input layer and generate a second set of intermediate tiles, forward propagate the second set of intermediate tiles through a second intermediate layer and generate a second set of further intermediate tiles, and forward propagate the second set of further intermediate tiles through a second output layer and generate a second set of non-overlapping output tiles; and
execute a second backward subgraph in the sequence of backward subgraphs of the graph in a second backward topology of tiling configurations to backward propagate a second set of non-overlapping input gradient tiles through a second backpropagation input layer and generate (i) a second set of intermediate gradient tiles and (ii) second input weight gradients for the second output layer, backward propagate the second set of intermediate gradient tiles through a second backpropagation intermediate layer and generate (i) a second set of further intermediate gradient tiles and (ii) second intermediate weight gradients for the second intermediate layer, and backward propagate the second set of further intermediate gradient tiles through a second backpropagation output layer and generate (i) a second set of output gradient tiles and (ii) second output weight gradients for the second input layer.