Patent ID: 11869442
Assignee: LG DISPLAY CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. The display device according to claim 7,
wherein, during the first period, the first charge transistor charges the first control node to the on-level of the second (N−1) scan signal, the first output transistor outputs the off-level of the clock signal to enable the gate-off level of the (N) emission control signal, and the second output transistor outputs the off-level of the clock signal to enable the gate-off level of the first (N) scan signal, or
wherein, during the second period, the first control node is floated to the on-level by the off-level of the second (N−1) scan signal, the first output transistor outputs the on-level of the clock signal to enable the gate-on level of the (N) emission control signal, the second output transistor outputs the on-level of the clock signal to enable the gate-on level of the first (N) scan signal, and a voltage of the first control node is elevated according to the on-level of the clock signal, or
wherein, during the third period, the second charge transistor charges the first control node to the on-level of the second (N+2) scan signal, the first output transistor outputs the off-level of the clock signal to enable the gate-off level of the (N) emission control signal, and the second output transistor outputs the off-level of the clock signal to enable the gate-off level of the first (N) scan signal, or
wherein, during the fourth period, the second control node are charged to the on-level by the high potential power supply voltage, the third output transistor outputs the high potential power supply voltage to the gate-on level of the (N) emission control signal, and the fourth output transistor outputs the low potential power supply voltage to the gate-off level of the first (N) scan signal.