Patent ID: 11955184
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. The method of claim 11, wherein reading the first set of the memory cells with the first set of read parameters and reading the second set of the memory cells with the second set of read parameters comprises:
applying a first read reference voltage to a selected word line while applying a sense voltage to a first set of the bit lines associated with first NAND strings having the first set of memory cells and while applying a lockout voltage to a second set of the bit lines associated with second NAND strings having the second set of memory cells, wherein the selected word line is connected to the first set of memory cells and the second set of memory cells;
sensing the first set of memory cells in response to the first read reference voltage;
applying a second read reference voltage to the selected word line while applying the sense voltage to the second set of the bit lines and while applying the lockout voltage to the first set of the bit lines, wherein the second read reference voltage has a different magnitude than the first read reference voltage to compensate for the different threshold voltage ranges; and
sensing the second set of memory cells in response to the second read reference voltage.