Patent ID: 11893360
Assignee: CEREMORPHIC, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. A process for a pipelined floating point multiplier-accumulator (MAC) implemented with registers separating stages and configured to generate a sum of N products from a corresponding pair of values, each pair of values comprising a floating point input value and a corresponding floating point coefficient value, the process comprising:
each of the N products provided by a dot product controller performing a respective dot product process of:
outputting a sign bit computed from an exclusive OR (XOR) of a sign bit of a floating point input value with a sign bit of a corresponding floating point coefficient value;
computing an exponent sum of an exponent of the floating point input value with an exponent of the corresponding floating point coefficient, determining a maximum exponent (MAX_EXP) value from all N exponent sums, determining an exponent difference (EXP_DIFF) value between the MAX_EXP value and the corresponding exponent sum;
generating a product by multiplying a mantissa from the floating point input value with a mantissa from the corresponding floating point coefficient value and normalizing the product, and asserting an exponent increment (EXP_INC) bit if an overflow results from the multiplication;
when the EXP_DIFF value is 0 and the EXP_INC bit is asserted, incrementing MAX_EXP and asserting a maximum increment (MAX_INC) bit;
when the EXP_DIFF value is not 0 and the EXP_INC bit is not asserted and the MAX_INC bit is asserted, incrementing the EXP_DIFF value;
when the EXP_DIFF value is not 0 and the EXP_INC bit is asserted and the MAX_INC bit is not asserted, decrementing the EXP_DIFF value;
prepending and appending 0 values to the normalized product to generate a padded value, modifying the padded value by taking a two's complement of the padded value if the sign bit is 1, thereafter right shifting the result by the EXP_DIFF value to generate an integer form fraction;

a summing process receiving each of the N integer form fractions and outputting an integer form fraction sum;
converting the integer form fraction sum to a resulting sign bit and resulting normalized mantissa, and outputting a floating point output value comprising the resulting sign bit, an exponent derived from said MAX_EXP value, and the resulting normalized mantissa.