Patent ID: 11928067
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 5:
6. The read operation circuit according to claim 5, wherein the data selector comprises a plurality of data selection units, each of the plurality of data selection units comprising:
a first inverter, an input terminal of the first inverter being configured to receive the inversion flag data through the inversion flag signal line;
a second inverter, an input terminal of the second inverter being connected to the data determination unit to receive the read data from the data determination unit;
a first transmission gate, an input terminal of the first transmission gate being connected to an output terminal of the second inverter, an output terminal of the first transmission gate being connected to the global bus to output the global bus data, a negative control terminal of the first transmission gate being connected to an output terminal of the first inverter, and a positive control terminal of the first transmission gate being configured to receive the inversion flag data through the inversion flag signal line; and
a second transmission gate, an input terminal of the second transmission gate being connected to the data determination unit to receive the read data from the data determination unit, an output terminal of the second transmission gate being connected to the global bus to output the global bus data, a negative control terminal of the second transmission gate being configured to receive the inversion flag data through the inversion flag signal line, and a positive control terminal of the second transmission gate being connected to the output terminal of the first inverter.