Patent ID: 11942372
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A method for manufacturing an integrated chip, comprising:
forming a transistor structure over a substrate, wherein the transistor structure comprises a pair of source/drain regions and a gate electrode between the source/drain regions;
forming a lower etch stop layer and a lower inter-level dielectric (ILD) layer over the pair of source/drain regions and surrounding the gate electrode over the substrate, wherein the lower ILD layer comprises a first dielectric material;
recessing the gate electrode such that a top surface of the gate electrode is below a top surface of the lower etch stop layer;
forming a gate capping layer on the recessed gate electrode such that a top surface of the gate capping layer is aligned with a top surface of the lower ILD layer, wherein the gate capping layer comprises a second dielectric material different from the first dielectric material;
performing a selective etch and deposition process to selectively form a dielectric protection layer along the top surface of the gate capping layer while concurrently selectively etching the lower ILD layer to define contact openings over the source/drain regions, wherein the selective etch and deposition process comprises concurrently flowing a plasma etchant at a first flow rate and a selective precursor gas at a second flow rate less than the first flow rate over the substrate;
performing a removal process to remove the dielectric protection layer; and
forming lower source/drain contacts within the contact openings.