Patent ID: 11928056
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. A memory controller comprising:
a memory buffer configured to store command data corresponding to a request received from a host; and
a cache memory configured to cache the command data,
wherein the cache memory divides the command data and allocates divided command data to cache lines, based on reference addresses of the memory buffer and a flag, the flag being included in the command data and including a start address and an end address of a storage region in the memory buffer in which the command data is stored, and
wherein when the start address is an address other than the reference addresses, the cache memory:
obtains first divided command data corresponding to a first interval between the start address and a first reference address, which is a next address of the start address, among the reference addresses, the first divided command data being a first part of the command data, and
obtains second divided command data corresponding to a second interval between the first reference address and a second reference address, which is a next address of the first reference address, among the reference addresses, the second divided command data being a second part of the command data.