Patent ID: 11928468
Assignee: ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITY
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A method, comprising:
generating, by a processor, a data flow graph expressive of a computational loop configured for execution on the CGRA unit, wherein the data flow graph includes a plurality of nodes;
determining an upper bound modulo timeslot for each node in the data flow graph, the upper bound modulo timeslot being representative of an upper scheduling bound of a CGRA schedule for each node of the plurality of nodes; and
iteratively generating a random schedule for population within the CGRA schedule that schedules each node of the data flow graph to a random timeslot between a lower bound modulo timeslot and the upper bound modulo timeslot of the CGRA schedule with respect to an initiation interval value.