Patent ID: 11954338
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device, comprising:
a memory cell array;
a set of fuse banks including a common fuse bank storing common bit information corresponding to a plurality of defective memory cells in the memory cell array; and
a repair circuit including a plurality of match sub-circuits corresponding to respective defective memory cells of the plurality of defective memory cells, each match sub-circuit configured to provide a determination of whether a memory cell address of a memory cell of the memory cell array matches an address of the respective defective memory cell,
wherein the plurality of match sub-circuits include a shared common bit-processing circuit that is configured to receive common bit-by-bit results of a comparison between a portion of the memory cell address and the common bit information and determine whether the common bit information matches the portion of the memory cell address.