Patent ID: 11886344
Assignee: XILINX, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A system, comprising:
a cache system including:
a computational cache configured to cache state vectors and perform read-modify-write (RMW) operations on the cached state vectors responsive to received RMW commands; and
a computational cache miss-handler configured to perform RMW operations on state vectors stored in a memory responsive to cache misses in the computational cache, wherein the memory is external to the cache system;
wherein the computational cache miss-handler includes a thread assignment circuit configured to assign the RMW commands corresponding to cache misses to threads and an RMW coalescing circuit configured to combine selected RMW commands belonging to a same thread and having a same index into a single RMW command.