Patent ID: 11863204
Assignee: MARVELL ASIA PTE LTD
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A decoder circuit configured to decode data including codewords encoded with an error correction code, the decoder circuit comprising:
a first decoder, wherein the first decoder is a first type of decoder configured to decode and eliminate errors from the data in accordance with a first performance level and a first level of power consumption, the first decoder being configured to (i) receive the data encoded with the error correction code and (ii) decode and eliminate errors from a first subset of the codewords encoded with the error correction code; and
a second decoder, wherein the second decoder is a second type of decoder configured to decode and eliminate errors from the data in accordance with a second performance level greater than the first performance level and a second level of power consumption greater than the first level of power consumption, the second decoder being configured to (i) receive the data encoded with the error correction code and (ii) decode and eliminate errors from a second subset of the codewords without attempting to decode and eliminate errors from the first subset of the codewords, the second subset of the codewords being different from the first subset of the codewords and encoded with the error correction code,
wherein the second decoder is configured to be in a sleep state while the first decoder attempts to decode and eliminate errors from the second subset of the codewords and to transition out of a sleep state in response to the first decoder being unable to decode and eliminate errors from codewords forming the second subset of the codewords.