Patent ID: 11961777
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A package structure, comprising:
a first die and a second die disposed side by side;
a first encapsulant encapsulating the first die and the second die, wherein the second die includes a die stack encapsulated by a second encapsulant;
a redistribution layer (RDL) structure disposed on the first die, the second die, and the first encapsulant;
a buffer layer, extending continuously between the first and second dies and covering facing sidewalls of the first and second dies; and
a plurality of filling structures, comprising an insulating polymer and embedded in the first encapsulant, wherein the plurality of filling structures extending from an interface between the first encapsulant and the RDL structure partially into the first encapsulant and not reach a bottom surface of the first encapsulant opposite to the interface.