Patent ID: 11961513
Assignee: MASSACHUSETTS INSTITUTE OF TECHNOLOGY
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. A decoder comprising:
a feature extraction circuit for calculating one or more feature vectors;
an acoustic model circuit coupled to receive one or more feature vectors from said feature extraction circuit and assign one or more likelihood values to the one or more feature vectors;
an off-chip memory for storing states of transition of the decoder;
an on-chip state lattice populated with at least one of the states of transition stored in the off-chip memory and which represents word hypotheses and having one or more word arcs formed by performing a Viterbi search on a state list by a search circuit; and
an on-chip word lattice generated by generating a snapshot from the on-chip state lattice, the on-chip word lattice having at least one word arc representing a chain of one or more of the word arcs in the on-chip state lattice;
wherein the on-chip state lattice and the on-chip word lattice act as an on-chip cache to reduce reading and writing to the off-chip memory.