Patent ID: 11908507
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. A semiconductor memory device comprising:
a command and address generator configured to decode a command to generate an active command, and to generate an address applied with the active command as a row address;
a control signal generator configured to generate sequence data that changes with a random sequence, the generating the sequence data in response to the active command, and the control signal generator configured to generate a random pick signal in response to the sequence data being equal to previously stored comparison data; and
a memory cell array comprising an odd page memory cell array including a plurality of first memory cells and an even page memory cell array including a plurality of second memory cells, the memory cell array configured to perform an active operation on selected first memory cells in a selected page memory cell array of the odd page memory cell array or selected second memory cells in a selected page memory cell array of the even page memory cell array, the active operation based on the row address and in response to the random pick signal being deactivated in the active command, or configured to simultaneously perform the active operation and a hidden hammer refresh operation on the selected first memory cells of the odd page memory cell array and the selected second memory cells of the even page memory cell array based on the row address and in response to the random pick signal being activated based on the active command.