Patent ID: 11947891
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A computer-implemented method for designing a circuit, the method comprising:
detecting a timing violation on a signal path connected to a local clock buffer in a circuit model, the local clock buffer being configured to generate a first clock signal having a first pulse width;
determining a first metric associated with a first type of timing violation;
determining a second metric associated with a second type of timing violation, the second type of timing violation being different from the first type of timing violation, and the detected timing violation is one of the first type of timing violation and the second type of timing violation;
comparing the first metric with the second metric; and
based on a result of the comparison of the first metric and the second metric, determining whether to retain the generation of the first clock signal or to configure the local clock buffer to generate a second clock signal having a second pulse width different from the first pulse width.