Patent ID: 11860798
Assignee: NYRIAD, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. A system comprising:
a memory; and
a plurality of non-uniform memory access (NUMA) nodes, each NUMA node comprising at least one CPU core in communication with at least a portion of the memory,
wherein the memory stores instructions that, when executed by the plurality of NUMA nodes, cause the plurality of NUMA nodes to:
obtain a list of data paths to at least one persistent storage device through the plurality of NUMA nodes;
associate access performance information with each data path;
receive a request to access a first persistent storage device of the at least one persistent storage device;
calculate a preferred data path to the first persistent storage device using the access performance information;
access the first persistent storage device using the preferred data path; and
update the access performance information of the used data path,
wherein the access performance information of each data path comprises the last update time of the access performance information.