Patent ID: 11922053
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device comprising:
a storage array; and
a controller configured to:
create a data structure in the storage array after erasing a physical block of the storage array, wherein the data structure is configured to track whether a logical-to-physical table region contains a reference to the physical block, and creating the data structure comprises initializing the data structure to indicate that the logical-to-physical table region does not contain a reference to the physical block; and
update the data structure in the storage array in response to a write to the physical block, the update of the data structure including setting an entry in the data structure corresponding to the logical-to-physical table region used in the write, the logical-to-physical table region being one of multiple logical-to-physical table regions of a logical-to-physical table, the entry unset only when the data structure is created.