Patent ID: 11861051
Assignee: RAMBUS INC.
Field: Digital communication (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 7:
8. A cryptographic processing device, comprising:
a cryptographic processing engine, where cryptographic processing is a one of ciphering and deciphering;
a read buffer to store a first set of data blocks in a first memory address order and a second set of data blocks in a second memory address order, the first set of data blocks arriving at the cryptographic processing device in the first memory address order which corresponds to locations in an external memory where the first set of data blocks are stored, and the second set of data blocks arriving at the cryptographic processing device in the second memory address order which corresponds to locations in the external memory where the second set of data blocks are stored;
first circuitry to provide, to the cryptographic processing engine, the first set of data blocks from the read buffer in a first randomly selected cryptographic processing order that is a permutation of the first memory address order, the cryptographic processing engine to cryptographically process the first set of data blocks in the first randomly selected cryptographic processing order, the first randomly selected cryptographic processing order based at least in part on randomly selecting blocks from a subset of the first set of data blocks that have already arrived at cryptographic processing device, the first circuitry also to provide, to the cryptographic processing engine from the read buffer, the second set of data blocks in a second randomly selected cryptographic processing order that is a permutation of the second memory address order, the cryptographic processing engine to cryptographically process the second set of data blocks in the second randomly selected cryptographic processing order; and,
second circuitry to store cryptographically processed versions of the first set of data blocks in an output buffer in a third memory address order that is determined by the first randomly selected cryptographic processing order and that is different from the first memory address order, the second circuitry also to store cryptographically processed versions of the second set of data blocks in the output buffer in a fourth memory address order that is determined by the second randomly selected cryptographic processing order and that is different from the second memory address order.