Patent ID: 11960942
Assignee: EMC IP HOLDING COMPANY LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. A computing system comprising:
a memory; and
a processor configured to create a plurality of objects and generate a lock information binary file that includes information for each lock operation associated with the plurality of objects of the computing device, wherein the processor is further configured to receive a plurality of lock sequences associated with a plurality of objects of the computing device by processing the lock information binary file associated with processing the plurality of objects of the computing device at runtime, wherein the processor is further configured to generate a matrix representative of at least a portion of a lock sequence of the plurality of lock sequences with a reference to a next matrix and an indication of a matrix tower level, wherein the matrix includes one or more rows associated with a matrix index and one or more columns associated with a lock record, wherein the processor is further configured to generate a plurality of matrices for each lock sequence of the plurality of lock sequences to generate a lock sequence matrix tower for each lock sequence of the plurality of lock sequences for each object of the plurality of objects of the computing device, wherein the processor is further configured to combine a plurality of lock sequence matrix towers by utilizing levels of each lock sequence matrix tower, thus defining a combined lock sequence matrix tower, and wherein the processor is further configured to identify one or more lock sequence conflicts within the plurality of lock sequences based upon, at least in part, the combined lock sequence matrix tower.