Patent ID: 11935885
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A device, comprising:
a plurality of standard cells in a layout of an integrated circuit, the plurality of standard cells comprising a first standard cell and a second standard cell disposed next to each other,
wherein the first standard cell is configured to operate as an electrostatic discharge (ESD) protection circuit and comprises:
a first gate including a first gate finger and a second gate finger that are arranged over a first active region, for forming a first transistor and a second transistor, respectively; and
a second gate separate from the first gate, the second gate including a third gate finger and a fourth gate finger that are arranged over a second active region, for forming a third transistor and a fourth transistor, respectively,
wherein the first transistor and the second transistor are connected in parallel, and the third transistor and the fourth transistor are connected in parallel.