Patent ID: 11860732
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 4:
5. The method of claim 1, wherein determining the first physical address comprises:
determining, based on the logical address, a virtual fault tolerant stripe associated with the host data and a virtual management unit (vMU) associated with the host data
providing an indication of the virtual fault tolerant stripe and the redundancy factor as input to a first function and an indication of the vMU and the redundancy factor as input to a second function; and
obtaining a first output of the first function and a second output of the second function, wherein the first output comprises an indication of a fault tolerant stripe associated with the memory device and the second output comprises an indication of a management unit (MU) associated with the memory device,
wherein the first physical address corresponds to the fault tolerant stripe and the MU associated with the memory device.