Patent ID: 11916035
Assignee: POWERTECH TECHNOLOGY INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A packaging structure, comprising:
a first die, comprising a silicon substrate and a through silicon conductor penetrating the silicon substrate;
an encapsulant, covering the first die;
a redistribution circuit structure, located on the encapsulant;
a second die, disposed on the redistribution circuit structure and electrically connected to the redistribution circuit structure;
a third die, disposed on the redistribution circuit structure and electrically connected to the redistribution circuit structure, wherein the third die has an optical signal transmission area; and
a filler, located between the second die and the redistribution circuit structure and between the third die and the redistribution circuit structure, wherein:
a groove is present on an upper surface of the redistribution circuit structure, and the upper surface comprises a first area and a second area located on opposite sides of the groove;
the filler directly contacts the first area;
the filler is away from the second area; and
the redistribution circuit structure is located on an encapsulant surface of the encapsulant, and in a direction perpendicular to the encapsulant surface, the optical signal transmission area of the third die does not overlap at least two of the filler, the redistribution circuit structure, and the encapsulant.