Patent ID: 11893332
Assignee: SYNOPSYS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A system comprising:
a memory storing instructions; and
a processor, coupled with the memory and to execute the instructions, the instructions when executed cause the processor to:
generate a set of assignments based on randomly sampling a set of variation models which models random parameter variations of circuit elements in the circuit design, wherein each assignment includes a parameter variation amount for each class of circuit element;
determine correlations between the variation models based on the set of assignments;
construct a timing-slack-sensitivity model to calculate a timing slack corresponding to a given set of assignments;
generate a set of samples for a set of independent random variables;
map the set of samples to a set of correlated assignments based on the correlations; and
use the timing-slack-sensitivity model to compute a set of timing slacks corresponding to the set of correlated assignments.