Patent ID: 11907680
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. The MAC operator of claim 12, wherein the accumulator includes:
an exponent processing circuit that receives the first maximum exponent upper data and exponent upper data of the latch data to generate and output second maximum exponent upper data, first shift data, and second shift data;
a mantissa shifting circuit that receives the first shift data, the second shift data, the mantissa data of the multiplication addition data, and the mantissa data of the latch data and generates and outputs shifted mantissa data of the multiplication addition data and shifted mantissa data of the latch data;
an accumulative adder that adds the shifted mantissa data of the multiplication addition data and the mantissa data of the latch data to generate and output accumulative mantissa data;
a first normalizer that performs first normalization on the second maximum exponent upper data and the accumulative mantissa data to generate and output first normalized exponent upper data and first normalized mantissa data; and
a latch circuit that latches the first normalized exponent upper data and the first normalized mantissa data and outputs the latched first normalized exponent upper data and the first normalized mantissa data as the exponent upper data and the mantissa data of the MAC data, respectively.