Patent ID: 11923240
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 9:
10. A method of forming a semiconductor device, comprising:
providing a substrate;
forming a first transistor on the substrate, and comprising:
forming a first gate structure, wherein the first gate structure comprises a first high-k layer, a first work function layer, and a first capping layer sequentially formed on the substrate; and

forming a second transistor on the substrate, and comprising
forming a second gate structure, wherein the second gate structure comprises a second high-k layer, a second work function layer, and a second capping layer sequentially formed on the substrate;

forming a third transistor on the substrate, and comprising
forming a third gate structure, wherein the third gate structure comprises a third high-k layer, a third work function layer, and a third capping layer sequentially formed on the substrate,

wherein the first capping layer, the second capping layer and the third capping layer comprise materials having higher resistant to oxygen or fluorine than a material of the second work function layer.