Patent ID: 11936394
Assignee: MARVELL ASIA PTE LTD
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 22:
23. The method of claim 20, further comprising:
controlling the durations of high and low phases, independently; and
in a present cycle of the output clock, effecting a change to the high or low phase, or a combination thereof, in a next cycle of the output clock, based on an indication of expected usage of at least one other circuit in the next cycle, wherein the output clock is associated with a target frequency,
wherein, in an event the indication indicates that the at least one other circuit is expected to be active in the next cycle, the change causes a frequency of the output clock to be lower or higher than the target frequency by altering a period of the output clock in the next cycle by changing a respective target count of signal inversions of a respective signal propagated in the first RO, second RO, or a combination thereof.