Patent ID: 11955436
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A package substrate, comprising:
a dielectric over a conductive layer;
a conductive line on the dielectric;
a plurality of first conductive bumps on a top surface of the conductive line;
a plurality of first metal features on the plurality of first conductive bumps, wherein individual ones of the plurality of first metal features are on a corresponding individual one of the plurality of first conductive bumps, and wherein the plurality of first metal features has a metal conductivity different than that of the plurality of first conductive bumps;
a plurality of second conductive bumps on a bottom surface of the conductive line, wherein the plurality of first and second conductive bumps are conductively coupled to the conductive line, and wherein the plurality of second conductive bumps is embedded in the dielectric;
a plurality of second metal features on the plurality of second conductive bumps, wherein individual ones of the plurality of second metal features are on a corresponding individual one of the plurality of second conductive bumps, and wherein the plurality of second metal features has a metal conductivity different than that of the plurality of second conductive bumps; and
a solder resist over the plurality of first conductive bumps, the conductive line, and the dielectric.