Patent ID: 11954041
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. A memory system comprising:
a memory device including a plurality of memory blocks, each memory block having physical addresses; and
a controller including a first queue and a second queue, configured to:
generate descriptors, each descriptor indicating a mapping relationship between a logical address and a physical address;
sequentially store the descriptors in the first queue having a linear structure;
perform a calculation for storing a selected descriptor, included in the descriptors stored in the first queue, into the second queue having a binary tree structure;
transmit the selected descriptor from the first queue to the second queue in the binary tree structure when the calculation of the selected descriptor is finished;
delaying transmitting a next descriptor stored in the first queue to the second queue until the calculation of the selected descriptor is finished;
store status information indicating whether any of the descriptors are stored in at least one of the first queue, the second queue, and both the first queue and the second queue in status buffers;
receive a target logical address from a host; and
search for a descriptor associated with the target logical address in at least one of the first queue, the second queue, and both the first queue and the second queue based on a structure of each of the descriptors stored in the first queue and the second queue which is determined by the status information.