Patent ID: 11868872
Assignee: AMAZON TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. The apparatus of claim 7, wherein:
the DMA descriptor queue comprises an input data DMA descriptor queue and an output data DMA descriptor queue;
the DMA descriptor comprises an input data DMA descriptor;
and
the hardware processor is configured to:
control the DMA engine to:
fetch the input data DMA descriptor from the input data DMA descriptor queue,
translate, using the address translation table, the first indirect address to the first physical address of the host memory, and
execute the input data DMA descriptor to perform a first DMA operation, the first DMA operation comprising transferring the input data from the first physical address of the host memory to the local memory;
perform the computation operation based on the first input data from the local memory to generate output data, and to store the output data in the local memory; and

control the DMA engine to:
fetch an output data DMA descriptor from the output data DMA descriptor queue,
translate, using the address translation table, a second indirect address of the output data DMA descriptor to a second physical address of the host memory, and
execute the output data DMA descriptor to perform a second DMA operation, the second DMA operation comprising transferring the output data from the local memory to the second physical address of the host memory.