Patent ID: 11929123
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 16:
17. The semiconductor memory device according to claim 11 wherein
the semiconductor memory device is configured to be able to execute the erase operation that includes a first erase verify operation and a second erase verify operation,
in the first erase verify operation, the semiconductor memory device applies an erase verify voltage to at least a part of the plurality of first conductive layers, applies a fourth voltage smaller than the erase verify voltage to at least a part of the plurality of second conductive layers, and applies a filth voltage smaller than the erase verify voltage to the first wiring, and
in the second erase verify operation, the semiconductor memory device applies the erase verify voltage to at least a part of the plurality of second conductive layers, applies the fourth voltage to at least a part of the plurality of first conductive layers, and applies the fifth voltage to the first wiring.