Patent ID: 11871625
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 11:
12. The method according to claim 11, wherein the forming the array structure layer on the silicon-based substrate comprises:
forming a first insulating layer on the silicon-based substrate; the first insulating layer in the display area and the peripheral area being formed with a first via hole;
forming a first conductive pillar in the first via hole;
forming a reflective electrode and a first connection electrode; the reflective electrode in the display area being connected with the second electrode of the driving transistor by the first conductive pillar, and the first connection electrode in the peripheral area being connected with the power supply electrode by the first conductive pillar;
forming a second insulating layer covering the reflective electrode and the first connection electrode; the second insulating layer in the display area and the peripheral area being formed with a second via hole, and the second insulating layer in the binding area being formed with a third via hole; and
forming a second conductive pillar and a third conductive pillar in the second via hole and the third via hole, respectively; the second conductive pillar in the display area being connected with the reflective electrode, the second conductive pillar in the peripheral area being connected with the first connection electrode, and the third conductive pillar in the binding area being connected with the bonding pad assembly.