Patent ID: 11948919
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A semiconductor package, comprising:
a first semiconductor structure and a second semiconductor structure that are sequentially stacked on a package substrate, the second semiconductor structure exposing a portion of the first semiconductor structure,
wherein the first semiconductor structure includes a first memory chip and a first peripheral circuit chip in contact with a portion of a top surface of the first memory chip, the first peripheral circuit chip being electrically connected to the first memory chip,
wherein the second semiconductor structure includes a second memory chip and a second peripheral circuit chip in contact with a portion of a top surface of the second memory chip, the second peripheral circuit chip being electrically connected to the second memory chip, and
wherein the second memory chip overlaps the first memory chip and does not overlap the first peripheral circuit chip.