Patent ID: 11948073
Assignee: ATI TECHNOLOGIES ULC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. An apparatus comprising:
a plurality of computing cores;
a control unit comprising circuitry; and
a table for mapping memory bandwidth reduction schemes to a processor core designated to broadcast data to one or more other processor cores;
wherein responsive to receipt of data indicative of a type of machine learning model, the control unit is configured to:
access the table to determine a given memory bandwidth reduction scheme to use in performing an indicated computing operation;
program a first computing core of the plurality of computing cores to implement the given bandwidth reduction scheme, wherein the bandwidth reduction scheme causes:
at least one of the plurality of computing cores to fetch and broadcast first data; and
two or more of the plurality of computing cores to receive the first data broadcast by the at least one of the plurality of computing cores;

wherein each of the two or more computing cores of the plurality of computing cores is configured to:
fetch second data for processing with the first data; and
perform one or more computations using the first data and the second data in order to perform the computing operation.