Patent ID: 11901905
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 8:
9. An apparatus, comprising:
an interface for receiving a data signal and receiving a clock signal;
a set of input/outputs (IOs) connected to the interface along a set of clock paths, wherein the set of clock paths communicate a set of local clock signals to the set of IOs based on the received clock signal; and
a controller in communication with the interface and the set of IOs, wherein the controller causes the apparatus to perform:
receiving a data signal on the interface;
storing the received data signal as a latched data signal;
receiving a clock signal on the interface;
calibrating the local clock signals for each latch circuit of the set of latch circuits based on the latched data signal, wherein the calibrating comprises:
determining, for each IO of the set of IOs, a delay to apply to a respective local clock signal of the set of local clock signals based on the latched data signal to align clock edges of the set of local clock signals; and
delaying the local clock signal for each IO of the set of IOs;

calibrating the latched data signal based on the calibrated local clock signals; and
processing the calibrated data signal based on the calibrated local clock signals.