Patent ID: 11887653
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 13:
14. The memory device of claim 13,
wherein the first selection circuit includes:
a first PMOS transistor connected between a first input terminal that is configured to receive the first word line selection signal and the first word line, the first PMOS transistor being configured to operate in response to the sub-word line driver enable signal;

and
a first NMOS transistor connected between the first word line and a low voltage terminal that is configured to receive the non-selection voltage, the first NMOS transistor being configured to operate in response to the sub-word line driver enable signal, and

wherein the second selection circuit includes:
a second PMOS transistor connected between a second input terminal that is configured to receive the second word line selection signal and the second word line, the second PMOS transistor being configured to operate in response to the sub-word line driver enable signal; and
a second NMOS transistor connected between the second word line and the low voltage terminal, and configured to operate in response to the sub-word line driver enable signal.