Patent ID: 11900157
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. At least one non-transitory computer readable storage medium, comprising a set of instructions, which when executed by a computing device, cause the computing device to:
manage one or more virtual graphic processor units;
map schedule information into a graphics memory space, wherein the schedule information includes schedule account information;
co-schedule the one or more virtual graphic processor units based on both general processor instructions and graphics processor instructions;
co-schedule the one or more virtual graphic processor units based on the graphics processor instructions when a graphics processor schedule stub inserted at an end of a virtual graphics processor workload is reached; and
update the schedule account information in the graphics memory space based on one or more of graphics memory space access instructions and graphics processor pipeline instructions, wherein the schedule account information is associated with scheduling policies implemented by graphics processor commands.