Patent ID: 11935853
Assignee: nan
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. An apparatus, comprising:
a bond pad formed on a backside of a substrate of a memory die, wherein the substrate has a frontside opposite the backside;
complementary metal-oxide-semiconductor (CMOS) circuitry on the frontside of the substrate of the memory die; and
a memory array on the memory die, the memory array over the CMOS circuitry on the frontside of the substrate of the memory die;
wherein the bond pad is (1) electrically coupled to the CMOS circuitry through a via that passes through the substrate of the memory die to the CMOS circuitry and stops at a plane of the memory die containing the memory array and (2) configured to provide an interface between the memory array and one or more external components.