Patent ID: 11973080
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A structure, comprising:
a portion of a p-type substrate doped to form a deep n-type well;
a p-type well over the deep n-type well;
a doped drain region and a doped source region within the p-type well;
a first embedded semiconductor region (ESR) on the deep n-type well and abutting opposite sides of the p-type well, wherein the first ESR is intrinsic;
a dielectric layer on the first ESR and surrounding the p-type well;
a first n-type well over the deep n-type well and surrounding the first ESR from a top view; and
a second n-type well over the deep n-type well and surrounding the first n-type well, wherein a second ESR abuts the first n-type well, the second n-type well, and the deep n-type well, and wherein the second ESR is intrinsic and surrounds the first n-type well.