Patent ID: 11923861
Assignee: QUALCOMM INCORPORATED
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 18:
19. The apparatus of claim 17, wherein N is an even integer number, wherein the RO further comprises a set of N/2 cross-coupled inverters, wherein each of the set of N/2 cross-coupled inverters comprises:
a first inverter including a first PMOS FET coupled in series with a first NMOS FET between the at least one second upper voltage rail and the at least one second lower voltage rail; and
a second inverter including a second PMOS FET coupled in series with a second NMOS FET between the at least one second upper voltage rail and the at least one second lower voltage rail;
wherein each ith first PMOS FET includes a gate coupled to the output of the (i+N/2+2)mod Nth inverter, wherein each ith first NMOS FET includes a gate coupled to the output of the (i+N/2)mod Nth inverter, wherein each ith second PMOS FET includes a gate coupled to the output of the (i+2)mod Nth inverter, wherein each ith second NMOS FET includes a gate coupled to the output of the ith inverter, wherein drains of each ith first PMOS FET and each ith first NMOS FET is coupled to the gate of each ith second NMOS FET, and wherein drains of each ith second PMOS FET and each ith second NMOS FET is coupled to the gate of each ith first NMOS FET, for i=0 to (N/2)−1.