Patent ID: 11880706
Assignee: NANJING QINHENG MICROELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 13:
14. The interrupt control system based on RISC-V according to claim 13, wherein the control and status register set further comprises a machine mode status register, and the machine mode status register comprises an interrupt enable bit MIE; when MIE=1, interrupt enable is maintained; and when MIE=0, the interrupt is masked; and
when any one of the following conditions occurs in an interrupt response process, MIE is set to be 0; otherwise, MIE is set to be 1:
when a nested interrupt is closed or a first-type memory area does not exist;
when the nested interrupt is opened but the first-type memory area is full; and
when a second-type memory area is full and HS ENHANCE=0.