Patent ID: 11906584
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. The simulation system according to claim 12, wherein the control signals applied to the control signal terminals of the PCB include a clock signal, a first chip selection signal, a second chip selection signal, a first command and address and a second command and address,
a first memory clock signal, a first memory chip selection signal, and a normal memory command and address are generated at the first driver output terminals,
a second memory clock signal, a second memory chip selection signal, and an inversion memory command and address are generated at the second driver output terminals,
a third memory clock signal, a third memory chip selection signal, and a mirror memory command and address are generated at the third driver output terminals, and
a fourth memory clock signal, a fourth memory chip selection signal, and a mirror_inversion memory command and address are generated at the fourth driver output terminals,
wherein the first command and address and the second command and address are applied at a double data rate (DDR), and
wherein the normal memory command and address, the inversion memory command and address, the mirror memory command and address, and the mirror_inversion memory command and address are generated at a single data rate (SDR), and comprise 1-cycle or 2-cycle command and address.