Patent ID: 11934307
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 25:
26. A method of providing coherence data within an apparatus that implements a cache coherency protocol, comprising:
receiving at the apparatus requests from a plurality of processing units, where multiple of the plurality of processing units have associated cache storage;
employing a snoop unit to implement the cache coherency protocol when a request received by the apparatus identifies a cacheable address within memory;
providing a plurality of snoop filter tables organised in a hierarchical arrangement to form snoop filter storage, wherein the plurality of snoop filter tables comprise a primary snoop filter table at a highest level in the hierarchy, and each snoop filter table at a level in the hierarchy other than the highest level forms a backup snoop filter table for an adjacent snoop filter table at a higher level in the hierarchy;
arranging each snoop filter table as a multi-way set associative storage structure to provide a plurality of entries, and providing each backup snoop filter table with a different number of sets than are provided in the adjacent snoop filter table at the higher level in the hierarchy;
employing each entry in the snoop filter tables to store, for an associated address, coherence data used to determine which cache storages provided within the multiple processing units need to be subjected to a snoop operation in response to a request specifying that associated address; and
controlling allocation of coherence data into entries of the snoop filter tables by, when new coherence data is to be allocated into the snoop filter storage, applying an allocation policy to determine into which of the plurality of snoop filter tables the new coherence data is allocated.