Patent ID: 11907628
Assignee: GRAPHCORE LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A computer design verification system comprising:
a parsing module configured to receive output messages from a testing tool arranged to test a computer component and to compose formatted objects from the output messages, each formatted object comprising a set of fields, each field having a field descriptor and at least some of the fields holding test values; and
a signoff module holding a plurality of signoff objects, each comprising a plurality of fields, each field having a field descriptor and at least some of the fields populated with a signoff expression, each signoff object associated with a severity level indicative of the severity of a condition represented by the signoff object,
wherein the signoff module is configured to receive the formatted objects from the parsing module and to compare at least one test value in the formatted objects with at least one signoff expression in the signoff objects to determine if a signoff object matches the formatted object, and in the case that it is determined that a signoff object matches the formatted object, associating the severity level of the signoff object with the formatted object.