Patent ID: 11923285
Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 4:
5. An electronic device package, comprising:
a circuit structure comprising:
a first dielectric layer;
a pad embedded in the first dielectric layer and having a first surface exposed by a bottom surface of the first dielectric layer and a second surface opposite to the first surface;
a first wiring layer disposed over the second surface of the pad; and
a first conductive via disposed between the first wiring layer and the pad; and

a first solder contacting the first surface of the pad, wherein a thickness of the pad is greater than a sum of a thickness of the first wiring layer and a thickness of the first conductive via;
wherein the circuit structure further comprises a second wiring layer over the first wiring layer, and a thickness of the second wiring layer is less than the thickness of the first wiring layer; and
wherein the circuit structure further comprises a second conductive via between the first wiring layer and the second wiring layer, a first interface is formed between the second conductive via and the first wiring layer, a second interface is formed between the first conductive via and the pad, and a width of the first interface is less than a width of the second interface.