Patent ID: 11861758
Assignee: NVIDIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 25:
26. A non-transitory machine-readable medium having stored thereon a set of instructions, which if performed by one or more processors, cause the one or more processors to at least:
detect receipt of a set of packets by a network interface;
cause at least a portion of a Parallel Processing Unit (“PPU”) memory associated with a PPU to be flushed after packet data transmitted by the set of packets is stored in the PPU memory; and
write, to a shared memory that is shared between the one or more processors and the PPU executing a process, an indication indicating that the packet data is available for processing after the portion of the PPU memory has been flushed, the PPU memory comprising the shared memory, the process being executed by the PPU before the indication is written to the shared memory, the process processing the packet data to obtain processed packet data after the PPU detects the indication.