Patent ID: 11955201
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A method, comprising:
turning on, in response to a first control signal, a first switch and a second switch in a first memory array of a plurality of memory arrays coupled in parallel to couple a first data line with a second data line and to couple a third data line with a fourth data line, wherein first portions of the first and third data lines extend in a row direction below the first and second switches, and
a plurality of memory cells in the first memory array are arranged between the first portions of the first and second data lines and the first to second switches;
transmitting, by the first switch, a data signal from the first data line to the second data line; and
transmitting, by the second switch, the data signal from the third data line to a sense amplifier through the fourth data line,
wherein control terminals of the first switch and the second switch are coupled together to a control line.