Patent ID: 11871570
Assignee: SK HYNIX INC.
Field: nan (nan)
Classification: CPC nan | IPC H

Claim 0:
1. A method of manufacturing a semiconductor device, comprising:
forming a stack including first material layers and second material layers which are alternately stacked;
forming an etch stop layer on the stack;
forming an insulating layer including vertical parts passing through the etch stop layer;
forming a slit extending to pass through the etch stop layer between the vertical parts that are adjacent to each other and extending to pass through the stack, wherein the second material layers are exposed by the slit in a state in which the vertical parts of the insulating layer cover sidewalls of the etch stop layer; and
replacing the second material layers with line patterns through the slit,
wherein the vertical parts of the insulating layer remain to cover the sidewalls of the etch stop layer during replacing the second material layers with the line patterns.