Patent ID: 11960987
Assignee: HANGZHOU HAICUN INFORMATION TECHNOLOGY CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A discrete three-dimensional (3-D) processor, comprising:
a plurality of storage-processing units (SPU's), each of said SPU's comprising a non-memory circuit and more than one 3-D memory (3D-M) array;
a first die on a first semiconductor substrate, wherein said 3D-M array comprises memory cells stacked above said first semiconductor substrate, and an in-die peripheral-circuit component of said 3D-M array is disposed on said first semiconductor substrate;
a second die on a second semiconductor substrate, wherein at least a portion of said non-memory circuit and an off-die peripheral-circuit component of said 3D-M array are disposed on said second semiconductor substrate;
wherein, said non-memory circuit is not a part of a memory; said first die does not comprise said off-die peripheral-circuit component; said first and second dice are communicatively coupled by a plurality of inter-die connections; said first and second semiconductor substrates are separate semiconductor substrates.