Patent ID: 11935939
Assignee: SK HYNIX INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor device comprising:
a substrate;
a first doped region and a second doped region formed to be spaced apart from each other by a trench in the substrate;
a gate dielectric layer over the trench;
a buried gate over the gate dielectric layer; a channel between the first doped region and the second doped region along a profile of the trench;
a first dipole inducing portion formed in the gate dielectric layer between the buried gate and the channel; and
a second dipole inducing portion formed in the gate dielectric layer between the buried gate and the first and second doped regions,
wherein the gate dielectric layer is a single layer of a silicon oxide,
wherein the gate dielectric layer includes the first and second dipole inducing portions embedded in the gate dielectric layer,
wherein the first dipole inducing portion is a silicon oxide containing a first chemical species, and wherein the second dipole inducing portion is a silicon oxide containing a second chemical species different from the first chemical species; and
wherein the buried gate comprises a lower buried portion and an upper buried portion on the lower buried portion, the lower buried portion directly contacting the first dipole inducing portion, and the upper buried portion directly contacting the second dipole inducing portion.