Patent ID: 11871561
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 10:
11. A manufacturing method of a semiconductor structure, comprising:
providing a substrate;
forming word lines in the substrate, and forming a bit line contact hole between each two adjacent word lines;
forming a first isolation layer on a side wall of the bit line contact hole; and
forming a bit line contact plug in the first isolation layer, the first isolation layer covering a side wall of the bit line contact plug,
wherein said forming the bit line contact plug comprises:
depositing a first layer of polycrystalline silicon in the first isolation layer, the first layer of polycrystalline silicon covering the bit line contact hole;
depositing a metal material on the polycrystalline silicon; and
depositing a second layer of polycrystalline silicon on the metal material.