Patent ID: 11928067
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A read operation circuit configured to be used in a semiconductor memory, wherein the semiconductor memory comprises a Data Queue (DQ) port and a memory bank, the read operation circuit comprising:
a data determination module connected to the memory bank, wherein the data determination module is configured to read data from the memory bank, determine whether to invert the read data according to number of bits of low data in the read data, and to output global bus data for transmission through a global bus and inversion flag data for transmission through an inversion flag signal line;
a data receiving module connected to the global bus and the inversion flag signal line, wherein the data receiving module is configured to determine whether to invert the global bus data according to the inversion flag data and to output cache data;
a parallel-to-serial conversion circuit connected between the data receiving module and the DQ port, wherein the parallel-to-serial conversion circuit is configured to perform parallel-to-serial conversion on the cache data and to generate output data of the DQ port;
a data buffer module connected to the memory bank through the global bus; and
a precharge module connected to a precharge signal line and configured to set an initial state of the global bus to High.