Patent ID: 11875844
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. The memory device of claim 11, wherein the driver includes a third inverter including an input terminal configured to receive the second internal clock, an output terminal configured to output the first signal, a first transistor, and a second transistor,
wherein the first transistor includes a first end configured to receive a first voltage through a fourth wire, a gate configured to receive the second internal clock, and a second terminal connected with the second transistor,
wherein the second transistor includes a first end connected with the second end of the first transistor, a gate configured to receive the second internal clock, and a second end connected with a ground terminal,
wherein the second end of the first transistor and the first end of the second transistor are connected with the first wire,
wherein the fourth wire is identical to the plurality of word lines,
wherein a length of the fourth wire is n % of the length of the one of the plurality of word lines, and
wherein the “n” is a positive integer of 100 or less.