Patent ID: 11947841
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 22:
23. An apparatus, comprising:
a memory array; and
a controller coupled with the memory array, the controller configured to cause the apparatus to:
receive a command for an address of the memory array;
decode, by a decoder, the address of the memory array based at least in part on the command;
read, from the memory array based at least in part on the command, a first set of tag bits indicating access information for a set of addresses that includes the address;
generate, by the decoder, a second set of tag bits based at least in part on the command and the decoded address, the generated second set of tag bits indicating updated access information for the decoded address;
generate, by a first error correction code (ECC) engine, a codeword based at least in part on the first set of tag bits and the generated second set of tag bits, wherein the first ECC engine is different than a second ECC engine configured to perform ECC operations on data bits stored in the memory array; and
store the codeword in the memory array.