Patent ID: 11888500
Assignee: MITSUBISHI ELECTRIC CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A decoding circuit comprising:
likelihood calculating circuitry capable of calculating likelihood information of a polar code of a first code length, the likelihood calculating circuitry being configured to calculate likelihood information corresponding to a polar code of a second code length less than or equal to the first code length on the basis of an input signal and a decoding interim result;
decoding processing circuitry to select decoding candidates on a bit-by-bit basis by sequential decoding using the likelihood information calculated by the likelihood calculating circuitry;
first bit arrangement changing circuitry to generate a first bit sequence of the first code length by arranging the decoding candidates selected by the decoding processing circuitry in the first bit sequence according to an arrangement rule that depends on a ratio of the second code length and the first code length;
first polar encoding circuitry to perform polar encoding on the first bit sequence, and input the first bit sequence polar-encoded to the likelihood calculating circuitry as the decoding interim result;
control circuitry to control the likelihood calculating circuitry and the decoding processing circuitry on the basis of the second code length such that sequential decoding is performed according to the second code length;
decoded bit selecting circuitry to, in response to the decoding candidates of a data length to be processed being calculated by the decoding processing circuitry, select decoded bits as a decoding result using the decoding candidates; and
frozen bit removing circuitry to remove a frozen bit from the decoding result.