Patent ID: 11868252
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 19:
20. A memory system, comprising:
a memory controller; and
a memory device operably connected to the memory controller,
wherein the memory device includes a plurality of memory dies,
wherein each memory die of the plurality of memory dies includes command/address decoders and master selection circuitry,
wherein the command/address decoders of each memory die are configured to receive command and address signals from external contacts of the memory device at inputs of the command/address decoders,
wherein the command/address decoders of each memory die are further configured, when enabled, to decode the command and address signals and transmit the decoded command and address signals to every other one of the plurality of memory dies,
wherein the master selection circuitry of each memory die is configured to enable, or disable, or both respective command/address decoders of the plurality of memory dies after the plurality of memory dies are packaged in the memory device based at least in part on an input from a host device or the memory controller or both to the memory device, a fuse or antifuse setting of one or more memory dies of the plurality of memory dies, or a setting of one or more registers of the memory device, or any combination thereof,
wherein the input from the host device or the memory controller or both, the fuse or antifuse setting of the one or more memory dies, the setting of the one or more registers, or the any combination thereof is based at least in part on difference detected between one or more characteristics of at least two memory dies of the plurality of memory dies, wherein the one or more characteristics include drive strengths of the at least two memory dies, first characteristics corresponding to a ring oscillator delta distribution related to the at least two memory dies, second characteristics corresponding to process corners of the memory dies, run speeds of the memory dies, or a combination thereof, and
wherein the command/address decoders of only one memory die of the plurality of memory dies are enabled.