Patent ID: 11973153
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G  Y | IPC G  H

Claim 0:
1. A memory controller comprising:
a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller;
an acknowledgement interface to receive a combined acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, wherein the combined acknowledgment status packet is formed from a logical combination of individual acknowledgment status packets corresponding to each of the plurality of memory devices, wherein each of the individual acknowledgment status packets comprises a plurality of fields, wherein each of the individual acknowledgement status packets comprises acknowledgment information associated with a corresponding memory device of the plurality of memory devices and stored in a respective designated field of the plurality of fields, and wherein a remainder of the plurality of fields in each individual acknowledgment status packet besides the respective designated field comprise default values, the acknowledgment information to indicate whether the command was successfully received by the corresponding memory device; and
a memory controller core to decode the combined acknowledgment status packet to identify the acknowledgement information corresponding to each of the plurality of memory devices.