Patent ID: 11927612
Assignee: MARVELL ASIA PTE LTD
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A circuit, comprising:
a first signal delay line configured to output a first delayed signal, the first signal delay line being comprised of delay elements having a first threshold voltage;
a second signal delay line configured to output a second delayed signal, the second delay line being comprised of delay elements having a second threshold voltage that is higher than the first threshold voltage;
a phase detector configured to compare the first and second delayed signals and output a comparison signal indicating which of the first and second signal delay lines exhibits a shorter delay;
a reset circuit configured to reset the first and second signal delay lines in response to the comparison signal; and
a clock controller configured to output a command to adjust a clock frequency based on the comparison signal.