Patent ID: 11868269
Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 16:
17. A non-transitory computer-readable medium, having stored thereon computer-executable instructions that, when executed by a processor-based device, cause the processor-based device to:
detect a memory access operation directed to a memory block of a plurality of memory blocks that results in at least one of a cache miss and a TLB miss; and
responsive to detecting the memory access operation, increment an access count value of a plurality of access count values of an access count table, wherein the access count table is a packed table and the access count value corresponds to the memory block
detect a memory access operation directed to the memory block that results in a cache hit or a translation lookaside buffer (TLB) hit;
responsive to detecting the memory access operation to the memory block that results in the cache hit or the TLB hit, set an access-track indicator of a plurality of access-track indicators of an access-track table, wherein the access-track table is a packed table and the access-track indicator corresponds to the memory block; and
responsive to an accounting interval being triggered, clear the access-track indicator corresponding to the memory block.