Patent ID: 11862560
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A method of manufacturing a package structure, comprising:
providing a semiconductor die; and
forming a redistribution circuit structure, wherein the redistribution circuit structure is electrically coupled to the semiconductor die, and forming the redistribution circuit structure comprises:
forming a first metallization layer over the semiconductor die;
disposing a first dielectric material to embed the first metallization layer therein; and
planarizing the first dielectric material to form a first dielectric layer, wherein a first end of the first metallization layer being disposed at a location in the first dielectric layer, a second end of the first metallization layer being protruded out of the first dielectric layer, and the first end is opposite to the second end, wherein the second end is further away from the semiconductor die than the first end is, and a second lateral size of the second end is less than a first lateral size of the first end, wherein the second end of the first metallization layer have a top surface, a first sidewall and a second sidewall connecting the top surface and the first sidewall, and an extending plane of the top surface, an extending, plane of the first sidewall and an extending plane of the second sidewall are different.