Patent ID: 11966677
Assignee: SYNOPSYS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. A system, comprising:
a memory for storing operations; and
one or more processors, communicatively coupled to the memory, configured to perform the operations comprising:
computing a time delay for each path of a plurality of paths of a circuit design;
determining, a commonality score based on a number of segments that are common between the plurality of paths of the circuit design, the commonality score being proportional to the number of segments that are common between the plurality of paths;
determining, a criticality score based on the time delay for each path of the plurality of paths of the circuit design, the criticality score being proportional to the time delay;
generating, a graphical representation of the plurality of paths, wherein a first dimension of the graphical representation corresponds to the commonality score and wherein a second dimension of the graphical representation corresponds to the criticality score; and
providing, the graphical representation of the plurality of paths in a graphical user interface (GUI) to represent the plurality of paths in the circuit design.