Patent ID: 11955198
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. An integrated-circuit memory component comprising:
a programmable register to store a logical-width value;
a timing signal input to receive a data timing signal;
data signal receivers;
a data storage array; and
means for:
enabling reception of write data exclusively via a first subset of the data signal receivers at times indicated by transitions of the data timing signal if the logical-width value specifies a first data-interface width;
enabling reception of the write data exclusively via a second subset of the data signal receivers at times indicated by transitions of the data timing signal if the logical-width value specifies a second data-interface width narrower than the first data-interface width, the second subset of the data signal receivers including (i) fewer of the data signal receivers than the first subset and (ii) at least one of the data signal receivers not included in the first subset; and
storing the write data within the data storage array.