Patent ID: 11871552
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 11:
12. A memory device comprising:
a transistor comprising a gate structure, a source and a drain formed on a substrate;
an extended contact below and interfacing a first via;
the first via above and interfacing the extended contact, wherein the first via has an elongated oval shape having a first length at least 1.5 times a first width, the first length extending in a first direction parallel a top surface of the substrate and the first width extending in a second direction parallel a top surface of the substrate, the second direction perpendicular the first direction;
a first Vss conductive element disposed on a first metallization layer, wherein the first Vss conductive element directly interfaces a top surface of the first via, the top surface of the first via having the elongated oval shape, wherein the first Vss conductive element has a second length in the first direction greater than the first length and a second width in the second direction greater than the first width;
a second Vss conductive element disposed on a second metallization layer; and
a second via interfaces the second Vss conductive element and extends to interface a Vss conductive line disposed on a third metallization layer and extending in the second direction.