Patent ID: 11934253
Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITY
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A computing-in-memory apparatus, comprising:
a voltage regulator having an amplifier and a reference current source, wherein the amplifier has a current input and a voltage output, and the amplifier and the reference current source are connected to each other;
a computing-in-memory array having a plurality of computing units and connected to the voltage regulator having the amplifier and the reference current source, wherein the voltage regulator having the amplifier and the reference current source provides an output voltage to the computing-in-memory array having the plurality of computing units; and
a detection circuit respectively connected to the voltage regulator and the computing-in-memory array having the plurality of computing units, wherein an output current of the detection circuit is inputted into the voltage regulator having the amplifier and the reference current source to compare the output current of the detection circuit with the reference current source of the voltage regulator, wherein a negative feedback convergence or a negative feedback mechanism is performed according to a comparison result of the output current of the detection circuit and the reference current source of the voltage regulator, and wherein the output voltage provided by the voltage regulator to the computing-in-memory array having the plurality of computing units is adjusted via the negative feedback convergence or the negative feedback mechanism.