Patent ID: 11908507
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 15:
16. A memory system comprising:
a controller circuit configured to receive a command and address and transmit and receive data; and
a memory configured to receive the command and address and to transmit and receive the data,
wherein the memory comprises:
a command and address generator configured to decode a command included in the command and address to generate an active command, and to generate an address included in the command and address applied with the active command as a row address;
a control signal generator configured to generate sequence data changing with a random sequence, and generate a random pick signal when the sequence data is equal to previously stored comparison data; and
a memory cell array comprising an odd page memory cell array including a plurality of first memory cells and an even page memory cell array including a plurality of second memory cells, and configured to perform an active operation on selected first memory cells or selected second memory cells of a selected page memory cell array based on the row address in response to the random pick signal being deactivated based on the active command, or to simultaneously perform the active operation and a hidden hammer refresh operation on the selected first memory cells of the odd page memory cell array and the selected second memory cells of the even page memory cell array based on the row address and in response to the random pick signal being activated in response to the active command,
wherein the active operation and the hidden hammer refresh operation are the same.