Patent ID: 11908800
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. A semiconductor structure comprising:
a multi-level interconnect structure;
a passivation layer above the multi-level interconnect structure;
a pad layer partially in the passivation layer and above the multi-level interconnect structure; and
a barrier layer between the multi-level interconnect structure and the pad layer, wherein the barrier layer comprises:
a first tantalum-containing layer;
a second tantalum-containing layer above the first tantalum-containing layer; and
a third tantalum-containing layer above the second tantalum-containing layer, wherein the first tantalum-containing layer and the third tantalum-containing layer have nitrogen concentrations higher than that of the second tantalum-containing layer, and threading dislocation defects in the first tantalum-containing layer are misaligned with threading dislocation defects of the third tantalum-containing layer.