Patent ID: 11950432
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 16:
17. A method of forming a semiconductor package, comprising:
providing a first die, the first die comprising a first substrate, a first bonding structure and a memory cell between the first substrate and the first bonding structure;
providing a second die, the second die comprising a second substrates plurality of through vias in the second substrate, a second bonding structure and a peripheral circuit between the second substrate and the second bonding structure;
bonding the first die and the second die through the first bonding structure and the second bonding structure, to electrically connect the memory cell and the peripheral circuit; and
mounting the first die and the second die onto a circuit structure, comprising:
removing portions of the second substrate to expose the plurality of through vias;
forming a plurality of conductive terminals on the plurality of through vias; and
bonding the second substrate onto the circuit structure through the plurality of conductive terminals, wherein the second die is disposed between the first die and the circuit structure.