Patent ID: 11914509
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. Circuitry comprising:
memory address translation circuitry to access memory circuitry storing translation information defining memory address translations from input memory addresses to respective output memory addresses;
in which the translation information stored by the memory circuitry comprises a hierarchy of page table levels from a highest page table level to a lowest page table level, each page table level having one or more level tables each comprising two or more entries, in which an entry of a level table at a page table level other than a last page table level of the hierarchy points to a level table at a next lower page table level in the hierarchy;
the memory address translation circuitry being configured to select an entry of a level table at each page table level according to a selection value, the selection value being dependent upon a portion, applicable to that page table level, of a given input memory address;
in which the memory circuitry is configured to store entries as groups of entries, a group of entries being accessible by a single memory retrieval operation;
and in which, for at least a subset of the page table levels, a group of entries stored by the memory circuitry comprises a set of entries from two or more respective level tables.