Patent ID: 11876127
Assignee: RENESAS ELECTRONICS CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 17:
18. The method of manufacturing the semiconductor device according to claim 17,
wherein the silicon substrate in a planar view includes: a cell formation region including the n-type emitter layer, the p-type base layer, the trench gate, the trench emitter, the p-type floating layer and the n-type hole barrier layer; and a peripheral region surrounding the cell formation region,
the first dislocation suppressing layer is formed below the peripheral region in a planar view,
the first dislocation suppressing layer includes the upper surface in the region of the first main surface and the lower surface in the region of the second main surface, and
each of the upper surface and the lower surface has the hetero junction.