Patent ID: 11862517
Assignee: KEPLER COMPUTING INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 17:
18. A device comprising:
a first region comprising:
a first conductive interconnect within a first dielectric in a first level;
a second level above the first level, the second level comprising:
a first electrode structure on at least a portion of the first conductive interconnect, the first electrode structure comprising:
a first conductive hydrogen barrier layer; and
a first conductive fill material adjacent to the first conductive hydrogen barrier layer;

an insulator layer laterally surrounding the first electrode structure;
a memory device on least a portion of the first electrode structure, the memory device comprising a ferroelectric material or a paraelectric material; and

a second dielectric spanning the first region, the second dielectric comprising an amorphous, greater than 90% film density hydrogen barrier material, wherein the memory device is directly adjacent to and embedded within the second dielectric; and

a second region adjacent to the first region, the second region comprising:
a second conductive interconnect within the first level;
a via structure on the second conductive interconnect, the via structure within the second level;
a metal line within a third level, the metal line in contact with the via structure;
a third dielectric comprising a less than 90% film density material on the insulator layer, the third dielectric laterally adjacent to and in contact with the second dielectric, and wherein the via structure and the metal line are laterally surrounded by the third dielectric, wherein the third dielectric laterally extends on an uppermost surface of the second dielectric;
wherein the first region further comprises:
a second electrode structure coupled with the memory device, the second electrode structure comprising:
a via electrode on at least a portion of the memory device and adjacent to the second dielectric, the via electrode comprising:
 a second conductive hydrogen barrier layer comprising a first lateral portion on the memory device and first substantially vertical portions directly adjacent to the second dielectric; and
 a second conductive fill material on the second conductive hydrogen barrier layer; and
a trench electrode on the via electrode, the trench electrode adjacent to the third dielectric, the trench electrode comprising:
 the second conductive hydrogen barrier layer comprising a second lateral portion on the second dielectric; and
 second substantially vertical portions directly adjacent to the third dielectric, wherein the second conductive fill material is directly adjacent to the second conductive hydrogen barrier layer and wherein the second conductive fill material extends continuously from a lowermost surface of the third dielectric to an uppermost surface of the third dielectric.