Patent ID: 11959965
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Measurement (Instruments)
Classification: CPC G | IPC G

Claim 0:
1. A test circuit for testing an integrated circuit core or an external circuit of the integrated circuit core, the test circuit comprising:
a bypass terminal configured to receive a bypass signal;
a cell function input (CFI) terminal configured to receive a CFI signal from the integrated circuit core or the external circuit;
a cell function output (CFO) terminal configured to transmit a CFO signal to the integrated circuit core or the external circuit;
a first multiplexer including a first selection terminal connected to the bypass terminal, a first input terminal connected to the CFI terminal, a second input terminal, and a first output terminal connected to the CFO terminal, and the first multiplexer configured to transmit the CFI signal to the integrated circuit core or the external circuit through the first output terminal as the CFO signal in response to the bypass signal;
a scan flip-flop;
a second multiplexer including a second selection terminal connected to a safe mode terminal configured to receive a safe mode signal, a third input terminal connected to an output terminal of the scan flip-flop, a fourth input terminal connected to a safe value terminal configured to receive a safe value signal, and a second output terminal connected to the second input terminal of the first multiplexer, and
a cell test output (CTO) terminal connected to the output terminal of the scan flip-flop.