Patent ID: 11888489
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 9:
10. A memory device, comprising:
a clock signal delay circuit configured to receive a reference clock signal and to provide the reference clock signal to an output circuit; and
a delay locked loop comprising a replica fine delay circuit configured to replicate a fine delay circuit, a variable delay circuit, and a replica delay circuit,
wherein the variable delay circuit comprises a coarse delay circuit and the fine delay circuit,
wherein the coarse delay circuit is configured to delay the reference clock signal to generate a first clock signal,
wherein the fine delay circuit is configured to delay the first clock signal to generate a second clock signal,
wherein the replica delay circuit is configured to delay the first clock signal to generate a fourth clock signal, and
wherein the replica fine delay circuit is configured to delay the fourth clock signal to generates a fifth clock signal.