Patent ID: 11887930
Assignee: ICOMETRUE COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A chip package comprising:
a first integrated-circuit (IC) chip comprising a first semiconductor substrate, a plurality of first transistors at a surface of the first semiconductor substrate and a first interconnection scheme over the surface of the first semiconductor substrate, wherein the first interconnection scheme comprises a first interconnection metal layer over the surface of the first semiconductor substrate, a second interconnection metal layer over the first interconnection metal layer and a first insulating dielectric layer between the first and second interconnection metal layers;
a second integrated-circuit (IC) chip on and over the first integrated-circuit (IC) chip, wherein the second integrated-circuit (IC) chip couples to the first integrated-circuit (IC) chip, wherein the second integrated-circuit (IC) chip comprises a second semiconductor substrate having a surface facing the surface of the first semiconductor substrate, a plurality of second transistors at the surface of the second semiconductor substrate and a second interconnection scheme under the surface of the second semiconductor substrate, wherein the second interconnection scheme comprises a third interconnection metal layer under the surface of the second semiconductor substrate, a fourth interconnection metal layer under the third interconnection metal layer and a second insulating dielectric layer between the third and fourth interconnection metal layers;
a connector on and over the first integrated-circuit (IC) chip and at a same horizontal level as the second integrated-circuit (IC) chip, wherein the connector comprises a substrate over the first integrated-circuit (IC) chip and a plurality of through vias vertically extending in the substrate of the connector, wherein the connector has no transistor therein;
a polymer layer on and over the first integrated-circuit (IC) chip, wherein the polymer layer has a portion between the second integrated-circuit (IC) chip and connector; and
a third interconnection scheme on a top surface of the polymer layer, a top surface of the second integrated-circuit (IC) chip, a top surface of the substrate of the connector and a top surface of each of the plurality of through vias, wherein the third interconnection scheme comprises a fifth interconnection metal layer over the top surface of the polymer layer, the top surface of the second integrated-circuit (IC) chip and the top surface of the substrate of the connector and on the top surface of each of the plurality of through vias, wherein the fifth interconnection metal layer couples to the first integrated-circuit (IC) chip through a through via of the plurality of through vias.