Patent ID: 11915055
Assignee: THROUGHPUTER, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 11:
12. A method of operating a multi-user multi-stage processing system comprising at least one entry/exit stage processor and a plurality of hardware processor stages, all interconnected by a packet switch, the method comprising:
dynamically assigning reconfigurable logic regions on the plurality of hardware processor stages to respective users of a plurality of users based on demand;
for each reconfigurable logic region of a given hardware processor stage of the plurality of hardware processor stages assigned to a respective user, instantiating one or more configurable application tasks on demand in that reconfigurable logic region on behalf of that respective user;
at the at least one entry/exit stage processor,
communicating via network data packets with users remote to the system, and distributing user data packets through the packet switch to the plurality of hardware processor stages, in dependence on the configurable application tasks instantiated at each hardware processor stage;

at hardware logic on each of the plurality of hardware processor stages,
receiving multiplexed packets through the packet switch, the multiplexed packets addressed to respective ones of multiple functions configured on that hardware processor stage, the multiplexed packets including first packets addressed to a first application task currently instantiated on a given reconfigurable logic region of that hardware processor stage, and
demultiplexing the first packets and buffering them for delivery to the first application task; and

at the at least one entry/exit stage processor,
executing a master task for each user of the plurality of users assigned at least one dynamically assigned reconfigurable logic region, and
configuring the at least one entry/exit stage processor to prevent the master task for a first user of the plurality of users from communicating with a reconfigurable logic region assigned to a different user of the plurality of users;

wherein, in at least a first dynamic configuration of the system, the respective user is the same user for each of the plurality of hardware processor stages, and, in at least a second dynamic configuration of the system, the respective user is a different user for at least two of the plurality of hardware processor stages.