Patent ID: 11955169
Assignee: QUALCOMM INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A multi-port memory, comprising:
a multi-port bitcell including a first read port having a first read port bit line, the multi-port bitcell further including a pair of write port bit lines and a second read port having a second read port bit line;
a sense amplifier coupled to the pair of write port bit lines;
a first inverter coupled to the first read port bit line;
a first multiplexer configured to select between a data output bit from the sense amplifier and a data output bit from the first inverter to provide a selected data output bit;
a second inverter coupled to the second read port bit line; and
a second multiplexer configured to select between a complement data output bit from the sense amplifier and a complement data output bit from the second inverter to provide a selected complement data output bit.