Patent ID: 11956952
Assignee: MONOLITHIC 3D INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A 3D memory device, the device comprising:
a first level comprising first memory cells, each of said first memory cells comprising a first transistor;
a second level comprising second memory cells, each of said second memory cells comprising a second transistor,
wherein said second level is disposed above said first level,
wherein a plurality of said first memory cells comprise a shared first source line and a shared first drain line,
wherein a plurality of said second memory cells comprise a shared second source line and a shared second drain line, and
wherein at least one of said first memory cells is self-aligned to at least one of said second memory cells; and

a third level comprising memory control circuits,
wherein said third level is bonded above said second level,
wherein said plurality of said second memory cells comprise channel regions disposed in-between said shared second source line and said shared second drain line,
wherein said channel regions are controlled by right side gate lines and left side gate lines,
wherein said device further comprises:

a plurality of horizontal word lines above said second layer,
wherein said horizontal word lines comprise odd word lines and even word lines, and
wherein said odd word lines are connected to said right side gate lines, and
wherein said even word lines are connected to said left side gate lines.