Patent ID: 11942156
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device, comprising:
a plurality of memory cells configured to store data;
a voltage generator configured to apply program voltages to a word line coupled to the plurality of memory cells during a program operation in which the plurality of memory cells are programmed to a plurality of program states;
a cell speed determiner configured to determine a program speed of the plurality of memory cells depending on a number of pulses for the program voltages applied to the word line while the program operation is being performed; and
a program manager configured to change a condition for remaining program operations depending on the program speed determined by the cell speed determiner,
wherein the program manager is configured to:
generate an operation code so that at least one of a level of each program voltage, an active time of the program voltage, a level of a step voltage for the program voltage, at least one of offsets for the program voltage that are included in the condition for the remaining program operations, and a verify voltage is controlled depending on the program speed determined by the cell speed determiner, and
transmit the operation code to the voltage generator.