Patent ID: 11894068
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 4:
5. The non-volatile memory device of claim 4, wherein the non-volatile memory cells are multi-level memory cells, and, to perform the read operations in the first read mode, the control circuit is further configured to:
perform a third hard bit read operation at a read level configured to determine a third hard bit value for each of one or more selected ones of the non-volatile memory cells, the third hard bit value indicating whether the memory cells is either reliably in a third data state or unreliability in a fourth data state;
perform a second soft bit read operation configured to generate a second soft bit value indicating a reliability value for each of the memory cells determined to be in the fourth data state, but not for memory cells determined to be in the third data state; and
provide the third hard bit values and the second soft bit values to the error correction code engine, the error correction code engine further configured determine the data content of selected memory cells from the third hard bit values and the second soft bit values.