Patent ID: 11908795
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A structure comprising:
a first via and a second via over and electrically coupled to a first die;
a second die over the first die, a front side of the second die facing away from the first die;
a first encapsulant encapsulating the first die, the second die, the first via, and the second via;
a first redistribution structure over the first die, the second die, the first via, the second via, and the first encapsulant, the first redistribution structure comprising:
a third via on the first via;
a fourth via on the second via;
a first metallization pattern on the third via, a first sidewall of the first metallization pattern directly overlying the first via; and

a second metallization pattern on the fourth via, a second sidewall of the second metallization pattern directly overlying the second via, wherein the first die is electrically coupled to the second die through the first via and at least a portion of the first redistribution structure.