Patent ID: 11908891
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of forming an integrated chip, comprising:
forming a plurality of separate isolation structures within a substrate, wherein the plurality of separate isolation structures have outermost sidewalls that face one another and that are separated from one another by the substrate;
selectively etching the substrate to form a gate base recess within the substrate, the gate base recess extending past the outermost sidewalls of the plurality of separate isolation structures;
selectively etching the plurality of separate isolation structures to form a plurality of gate extension trenches extending outward from the gate base recess;
forming a conductive material within the gate base recess and the plurality of gate extension trenches to form a gate electrode; and
forming a source region and a drain region on opposing sides of the gate electrode.