Patent ID: 11928333
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. A memory system, comprising:
an interface for receiving, from a host device, a reset command for performing a reset operation at the memory system,
circuitry for detecting a successful performance of the reset operation performed based at least in part on receiving the reset command,
a mode register operable to:
store a first value indicating a successful execution of the reset operation, or
store a second value indicating an error associated with executing the reset operation; and

one or more controllers coupled with the interface and the circuitry and operable to cause the memory system to:
determine whether to set the mode register to the first value or the second value;
set the mode register to the second value based at least in part on the circuitry failing to detect the successful performance of the reset operation;
generate an indication that the reset operation is unsuccessful based at least in part on setting to mode register to the second value; and
communicate the indication to the interface, wherein the interface transmits the indication to the host device.