Patent ID: 11862560
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A package structure, comprising:
a semiconductor die; and
a first redistribution circuit structure, disposed on and electrically coupled to the semiconductor die, and comprising a first build-up layer comprising a first metallization layer and a first dielectric layer laterally wrapping the first metallization layer, wherein a first end of the first metallization layer is disposed at a location in the first dielectric layer, a second end of the first metallization layer is protruded out of the first dielectric layer, and the first end is opposite to the second end, wherein the second end is further away from the semiconductor die than the first end is, and a second lateral size of the second end is less than a first lateral size of the first end,
wherein the second end of the first metallization layer have a top surface, a first sidewall and a second sidewall connecting the top surface and the first sidewall, and an extending plane of the top surface, an extending plane of the first sidewall and an extending plane of the second sidewall are different.