Patent ID: 11956340
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. The device of claim 8, wherein the clock generation circuitry includes:
clock gate and reset circuitry coupled to the first handoff circuitry and configured to generate a gated clock signal;
a current mode logic (CML) driver coupled to the clock gate and reset circuitry and configured to convert the gated clock signal to a CML clock signal;
a CML to complementary metal-oxide semiconductor (CMOS) converter coupled to the clock gate and reset circuitry, the CML driver, and the serializer circuitry and configured to convert the CML clock signal to generate the transmission clock; and
a clock divider coupled to first handoff circuitry, the second handoff circuitry, the serializer circuitry, and the CML to CMOS converter and configured to divide the transmission clock to generate the divided transmission clock.