Patent ID: 11863743
Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
Field: Audio-visual technology (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A decoder, comprising:
circuitry; and
memory, wherein
using the memory, the circuitry, in operation:
determines a number of first pixels and a number of second pixels used in a deblocking filter process, the first pixels located at an upper side of a block boundary and the second pixels located at a lower side of the block boundary, and
determines whether a location of the block boundary is an upper edge of a coding tree unit (CTU), and
performs the deblocking filter process on the block boundary;

wherein,
the number of the first pixels and the number of the second pixels are selected from among candidates, the candidates including at least 4 and M larger than 4, and
responsive to the location of the block boundary being the upper edge of the CTU, the number of the first pixels used in the deblocking filter process is limited to be 4.