Patent ID: 11961585
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G  H

Claim 16:
17. The memory system of claim 12, wherein the two or more CA input signals include seven input signals, and a layout arrangement is configured with:
a first CA pair operably coupled to a CA0 input signal and a CA6 input signal;
a second CA pair operably coupled to a CA,1 input signal and a CA5 input signal;
a third CA pair operably coupled to a CA2 input signal and a CA4 input signal; and
one unassociated CA input circuit operably coupled to a CA3 input signal;
wherein the first CA pair, the second CA pair, and the third CA pair are arranged in a mirror relationship in a first direction and adjacently arranged in a second direction.