Patent ID: 11907156
Assignee: STMICROELECTRONICS FRANCE
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 9:
10. A method, comprising:
having a system-on-chip comprising a master device and a slave device, wherein an operation of the system-on-chip is clocked by a clock circuit;
emitting a first access request by the master device to the slave device,
generating an interruption based on determining, by a control system, a deactivated state of the clock circuit stored in a clock controller, a power-off state of the slave device stored in a power-on controller, or a combination thereof;
activating, by the master device, the clock circuit stored in the clock controller based on receiving the interruption and determining that the clock circuit is in a deactivated state of the clock circuit;
activating, by the master device, a power-on state of the slave device in the power-on controller by the master device based on receiving the interruption and determining that the slave device is in a power-off state; and
emitting a second access request by the master device to the slave device after the clock circuit is activated, the slave device is powered on, or a combination thereof.