Patent ID: 11921843
Assignee: CEREMORPHIC, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A fault-detecting pipeline processor comprising a multi-thread pipelined processor and a fault detector;
the multi-thread pipelined processor configured to execute control instructions and data instructions and outputting branch status from branch instructions to the fault detector;
the multi-thread pipelined processor configured to execute at least two program threads on different instruction cycles, at least one thread being an executable program thread and at least one thread being a redundant branch program thread;
the executable program thread having control instructions, data instructions, and branch control instructions, the branch control instructions being a subset of the control instructions;
the redundant branch thread having only branch control instructions;
the fault detector comparing branch status between the executable program thread and the redundant branch thread and asserting a fault detect output when the branch status of the executable program does not match the branch status of the redundant branch thread;
where the redundant branch thread is derived from the executable program thread by either:
replacement of instructions that are not branch control instructions with no operation (NOP) instructions; or
removal of instructions that are not branch control instructions while preserving branch target addresses.