Patent ID: 11862722
Assignee: INNOSCIENCE (SUZHOU) TECHNOLOGY CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. A semiconductor device structure, comprising:
a substrate;
a first nitride semiconductor layer disposed on the substrate;
a second nitride semiconductor layer disposed on the first nitride semiconductor layer and having a bandgap greater than that of the first nitride semiconductor layer;
a third nitride semiconductor layer disposed on the second nitride semiconductor layer,
wherein the third nitride semiconductor layer comprises a first surface adjacent to the second nitride semiconductor layer and a second surface away from the second nitride semiconductor layer;
a source electrode;
a drain electrode;
a gate structure disposed on the second surface of the third nitride semiconductor layer; and
a barrier layer disposed between the gate structure and the second nitride semiconductor layer, wherein the barrier layer has a bandgap greater than that of the second nitride semiconductor layer,
wherein the source electrode and drain electrode are disposed on the second nitride semiconductor layer, and contact with an upper surface of the second nitride semiconductor layer, and
wherein the barrier layer is in contact with the drain electrode, and is spaced away from the source electrode.