Patent ID: 11901345
Assignee: SK HYNIX INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 19:
20. The semiconductor package according to claim 18, wherein the first internal channel pad includes a plurality of first internal channel pads arranged along the first side surface of the buffer chip,
wherein the memory chip pad includes a plurality of memory chip pads arranged along a side surface of the memory chip facing the buffer chip,
wherein the redistribution line includes a plurality of redistribution lines connecting the plurality of memory chip pads and the plurality of first internal channel pads, respectively,
wherein at least one of the plurality of redistribution lines includes horizontal portions substantially parallel to the first side surface of the buffer chip and the side surface of the memory chip, and
wherein, when a number of the horizontal portions disposed between the first internal channel pad and the memory chip pad is N, where N is a natural number equal to or greater than 2, a width of the redistribution line is W1, and a distance between adjacent horizontal portions is S1, a distance between the first internal channel pad and the memory chip pad has a value greater than N*W1+(N+1)*S1.