Patent ID: 11914716
Assignee: LATTICE SEMICONDUCTOR CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 11:
12. The secure PLD asset management system of claim 11, further comprising:
the secure PLD, wherein the secure PLD comprises a plurality of programmable logic blocks (PLBs) arranged in the PLD fabric of the secure PLD, and a configuration engine configured to program the PLD fabric according to a configuration image stored in a non-volatile memory (NVM) of the secure PLD and/or coupled through the configuration input/output (I/O) to the configuration engine, wherein the secure PLD is configured to perform a secure PLD-implemented method comprising:
receiving the secure PLD asset unlock request from the external system;
receiving a secure PLD asset access request from the PLD fabric or the external system;
performing a secure PLD asset update process corresponding to the secure PLD asset access request, wherein the performing the asset update process is based on a lock status associated with the secure PLD asset, and wherein the performing the secure PLD update process comprises receiving the one or more device keys and/or the configuration image for the PLD fabric from the external system; and
receiving the secure PLD asset lock request from the external system.