Patent ID: 11955462
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A stacked package comprising:
a first stacked layer, wherein:
the first stacked layer includes one or more semiconductor dies, components or both, and includes a first dielectric layer,
the first stacked layer is thinned to a first thickness; and the first stacked layer comprising:
a first through mold via in the first dielectric layer, the first through mold via laterally spaced apart from a first lateral sidewall of the one or more semiconductor dies, components or both of the first stacked layer, wherein the first through mold via extends above a top of the one or more semiconductor dies, components or both of the first stacked layer, and wherein the first through mold via does not extend below a bottom of the first dielectric layer; and
a second through mold via in the first dielectric layer, the second through mold via laterally spaced apart from a second lateral sidewall of the one or more semiconductor dies, components or both of the first stacked layer, wherein the second through mold via extends above the top of the one or more semiconductor dies, components or both of the first stacked layer, and wherein the second through mold via does not extend below the bottom of the first dielectric layer; and

one or more additional stacked layers, wherein:
each additional stacked layer includes one or more semiconductor dies, components or both, and includes a dielectric layer, wherein the dielectric layer of a first of the additional stacked layers is not vertically in between the one or more semiconductor dies, components or both of the first stacked layer and the one or more semiconductor dies, components, or both of the first of the additional stacked layers, and
each additional stacked layer is attached to a previous stacked layer by chip to wafer bonding, the previous stacked layer being thinned to a certain thickness;
a metallization layer formed on a front side of the first stacked layer; and
a ball grid array attached to the metallization layer.