Patent ID: 11941133
Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Field: Measurement (Instruments)
Classification: CPC G | IPC G

Claim 9:
10. A method to protect a field-programmable gate array (FPGA) chip mounted on a printed circuit board (PCB), comprising:
configuring the FPGA chip to include a control logic block and a detection logic block;
coupling an output of the control logic block to an enablement pin of a joint test action group (JTAG) interface of the FPGA chip to allow the control logic block to receive a control signal from an off-chip control unit and control a logical value of the enablement pin based on the received control signal, thereby facilitating the off-chip control unit to lock or unlock the JTAG interface; and
coupling an input of the detection logic block to the enablement pin to detect an unauthorized access to the FPGA chip, wherein a conductive trace coupling the input of the detection logic block and the enablement pin is situated on an inner layer of the PCB;
wherein an output of the control logic block and the enablement pin is coupled via a conductive trace situated on a top layer of the PCB, wherein the conductive trace comprises a detachable resistor, and wherein the method further comprises detaching the resistor during development of the FPGA chip to decouple the control logic block from the FPGA chip.