Patent ID: 11876516
Assignee: SYNOPSYS, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A level shifter circuit, comprising:
a first current mirror coupled between a power terminal and a ground terminal, wherein the first current mirror comprises a first n-type transistor gated by an input signal, and wherein the first current mirror is self-timed;
a second current mirror coupled between the power terminal and the ground terminal, wherein the second current mirror comprises a second n-type transistor gated by an inverse of the input signal, and wherein the second current mirror is self-timed;
a level shifter, wherein the level shifter includes a first transistor coupled to the first current mirror and a second transistor coupled to the second current mirror, wherein the first current mirror and the second current mirror control a state of the first transistor and the second transistor;
a first shoot-thru current section comprising a first inverter and a second inverter directly coupled between a gate of the first transistor and the first current mirror; and
a second shoot-thru current section comprising a third inverter and a fourth inverter directly coupled between a gate of the second transistor and the second current mirror.