Patent ID: 11928588
Assignee: UIF (UNIVERSITY INDUSTRY FOUNDATION), YONSEI UNIVERSITY
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A multi-bit memory cell array, comprising:
one or more multi-bit units, each of which stores input data in each of a plurality of multi-bit application nodes based on an input signal, groups the plurality of multi-bit application nodes into a plurality of groups, and outputs a per-group sum value summed for each group by applying a multi-bit weight to the stored input data of each of the multi-bit application nodes; and
a final summation unit which is connected through a switch to the one or more multi-bit units, adjusts a ratio for each group to receive a per-group sum value based on a switching operation of the switch, and outputs a final output value by summing the input per-group sum value,
wherein each of the one or more multi-bit units includes:
a weight storing unit which is supplied with a power voltage between a first bit line and a second bit line and stores multi-bit weights based on the power voltage;
a multi-bit weight application unit which includes the plurality of multi-bit application nodes connected in parallel and applies one bit weight among the multi-bit weights to the input data stored in a capacitor connected to each of the plurality of multi-bit application nodes to output a weight applied value; and
a per-group summation unit which groups the plurality of multi-bit application nodes into the plurality of groups to sum the weight applied value for each group to output a sum value for each group.