Patent ID: 11923840
Assignee: NXP B.V.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 19:
20. A circuit, comprising:
a power down signal generator configured to generate a power down signal, the power down signal generator comprising:
a detection transistor that comprises (i) a gate terminal configured to receive a first supply voltage in a first voltage domain, (ii) a drain terminal, and (iii) a source terminal;
a protection transistor that comprises (i) a drain terminal configured to receive a target current, (ii) a gate terminal configured to receive a first bias voltage that is derived from a second supply voltage in a second voltage domain, and (iii) a source terminal coupled to the drain terminal of the detection transistor;
a compensation transistor that comprises (i) a drain terminal coupled to the source terminal of the detection transistor, (ii) a gate terminal configured to receive a second bias voltage that is derived from the second supply voltage, and (iii) a source terminal; and
a first resistor that is coupled in parallel between the source terminal and the drain terminal of the compensation transistor,
wherein the protection transistor and the detection transistor are located in a current path, and
wherein the generation of the power down signal is based on a voltage of a node in the current path.