Patent ID: 11894456
Assignee: NUVOTON TECHNOLOGY CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H  Y | IPC H

Claim 7:
8. The semiconductor device according to claim 1, wherein
in a first current path defined by specifications, a first inlet/outlet vertical MOS transistor, among the N vertical MOS transistors, that is located at an inlet or an outlet of the first current path and a second inlet/outlet vertical MOS transistor, among the N vertical MOS transistors, that is located at the outlet or the inlet of the first current path are adjacent to each other in a plan view of the semiconductor layer,
in a second current path defined by the specifications, the first inlet/outlet vertical MOS transistor, among the N vertical MOS transistors, that is located at an inlet or an outlet of the second current path and a third inlet/outlet vertical MOS transistor, among the N vertical MOS transistors, that is located at the outlet or the inlet of the second current path are adjacent to each other in a plan view of the semiconductor layer,
in a third current path defined by the specifications, the second inlet/outlet vertical MOS transistor, among the N vertical MOS transistors, that is located at an inlet or an outlet of the third current path and the third inlet/outlet vertical MOS transistor, among the N vertical MOS transistors, that is located at the outlet or the inlet of the third current path are adjacent to each other in a plan view of the semiconductor layer, and
the gate pad of the third inlet/outlet vertical MOS transistor is located on an extension of a boundary line between the first inlet/outlet vertical MOS transistor and the second inlet/outlet vertical MOS transistor.