Patent ID: 11967547
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor structure, comprising:
a first substrate including a first plurality of conductive pads that are laterally spaced apart from one another on the first substrate;
a first plurality of conductive bumps disposed on the first plurality of conductive pads, respectively; and
a multi-tiered solder-resist structure comprising a dielectric material disposed on the first substrate, the dielectric material extending continuously along a lateral plane from a first sidewall of a first conductive bump of the first plurality of conductive bumps to a second sidewall of a second conductive bump of the first plurality of conductive bumps, the multi-tiered solder-resist structure having different widths at different heights over the first substrate and contacting sidewalls of the first plurality of conductive bumps at each of the different heights to separate the first plurality of conductive bumps from one another;
wherein a width of the dielectric material as measured between the first sidewall and the second sidewall on the lateral plane is less than a width of the first conductive bump as measured between outermost sidewalls of the first conductive bump along the lateral plane.