Patent ID: 11967060
Assignee: KLA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. A system comprising:
a semiconductor wafer inspection system; and
a processor in electronic communication with the semiconductor wafer inspection system,
wherein the processor is configured to:
receive a wafer map, wherein the wafer map is for a surface of an entire wafer, wherein the processor is configured to run a machine learning based model for classifying the wafer map;
classify the wafer map using the machine learning based model and a signature on the wafer map, wherein the machine learning based model uses transfer learning, and wherein a confidence matrix is used to control purity of signature classes in the machine learning based model;
determine a confidence level for the classifying, wherein the confidence level is based on criticality of a defect in the signature; and
determine if the signature is outside of the confidence level.