Patent ID: 11895840
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 17:
18. A memory device comprising:
a first structure; and
a second structure on the first structure,
wherein the first structure comprises a peripheral circuit, a first upper bonding pad connected to the peripheral circuit, and a second upper bonding pad connected to the peripheral circuit,
the second structure comprises a first lower bonding pad connected to the first upper bonding pad of the first structure, a first through via connected to the first lower bonding pad of the second structure, a first lower line connecting the first lower bonding pad of the second structure to the first through via of the second structure, a third upper bonding pad connected to the first through via of the second structure, a second lower bonding pad connected to the second upper bonding pad of the first structure, a first bit line connected to the second lower bonding pad of the second structure, and a memory cell array connected to the first bit line of the second structure,
the first bit line of the second structure comprises a first portion, a second portion, and a first gap between the first portion of the first bit line of the second structure and the second portion thereof, and
the first lower line of the second structure is not connected to the first portion and the second portion of the first bit line of the second structure,
wherein the second structure further comprises a second through via connected to the second lower bonding pad of the second structure, and a fourth upper bonding pad connected to the second through via,
the first bit line of the second structure further comprises a third portion and a second gap between the second portion of the first bit line of the second structure and the third portion of the first bit line, and
the second lower bonding pad of the second structure is connected to the second through via of the second structure and the second portion and the third portion of the first bit line of the second structure.