Patent ID: 11934867
Assignee: NVIDIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. A system comprising:
at least one graphics processing unit configured to sequentially execute different shards of a warp in a Single Instruction Multiple Thread (SIMT) manner, each shard comprising one or more threads of the warp; and
logic to:
detect a long stall hint instruction in a first shard of the different shards; and
in response to detecting the long stall hint instruction:

perform a runtime test for a long stall in the first shard;
on condition that the long stall is detected:
suspend execution of the first shard;
select a second shard of the different shards for execution, the second shard selected at least in part for being divergent from the first shard;
initiate execution of the second shard;
wherein the long stall hint instruction is detected in the first shard between a long-latency producer instruction and a consumer instruction that utilizes a result of the long-latency producer instruction.