Patent ID: 11871589
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An apparatus comprising:
a substrate;
a pillar extending in a direction perpendicular to the substrate;
a first conductive region located in a first level of the apparatus, the first conductive region being separated from the pillar by a first dielectric located in the first level;
a second conductive region located in a second level of the apparatus, the second conductive region being separated from the pillar by a second dielectric located in the second level;
a memory cell located between the first and second conductive regions and electrically separated from the first and second conductive regions, the memory cell including a first material located in a third level of the apparatus between the first and second levels and coupled to the pillar, and a second material located in a fourth level of the apparatus between the first and second levels and coupled to the pillar, the first and second materials having different conductivity types; and
a conductive connection coupled to the first material.