Patent ID: 11862098
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A shift register, comprising:
an input control circuit, respectively coupled with an input signal end, a first control clock signal end, a second control clock signal end, a first reference signal end, a second reference signal end, a pull-down node and a first pull-up node, wherein the input control circuit is configured to provide a signal of the input signal end to the first pull-up node in response to a signal of the first control clock signal end, provide a signal of the second reference signal end to a signal of the first pull-up node in response to a signal of the pull-down node and a signal of the second control clock signal end, and control the signal of the pull-down node according to the signal of the first pull-up node, the signal of the first control clock signal end and a signal of the first reference signal end;
a first transistor, wherein a grid electrode of the first transistor is configured to be coupled with the first reference signal end, a first electrode of the first transistor is configured to be coupled with the first pull-up node, and a second electrode of the first transistor is configured to be coupled with a second pull-up node;
a cascade output circuit, respectively coupled with the pull-down node, the second pull-up node, the second reference signal end, the second control clock signal end and a cascade signal end, wherein the cascade output circuit is configured to provide the signal of the second control clock signal end to the cascade signal end under control of a signal of the second pull-up node, and provide the signal of the second reference signal end to the cascade signal end under control of the signal of the pull-down node; and
a driving output circuit, respectively coupled with the cascade signal end, a first noise reduction clock signal end, a second noise reduction clock signal end, the first reference signal end, the second reference signal end and a driving signal end, wherein the driving output circuit is configured to provide the signal of the second reference signal end to the driving signal end in response to a signal of the cascade signal end, and provide the signal of the first reference signal end to the driving signal end in response to signals of the first noise reduction clock signal end and the second noise reduction clock signal end.