Patent ID: 11888041
Assignee: KIOXIA CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A nonvolatile semiconductor memory device comprising:
an underlying insulating layer provided above a substrate;
a source layer provided above the underlying insulating layer;
memory cells including a plurality of first electrode layers separately stacked from each other in a first direction above the source layer and a first columnar portion extending in the first direction through the first electrode layers, the first columnar portion including a first semiconductor channel layer extending in the first direction;
a bit line provided above the memory cells;
a first select transistor provided between the memory cells and the bit line in the first direction, the first select transistor including a second electrode layer and a second columnar portion extending in the first direction through the second electrode layer, the second columnar portion including a second semiconductor channel layer of which a first end is electrically connected to the bit line and a second end is electrically connected to the first semiconductor channel layer, each of the first semiconductor channel layer and the second semiconductor channel layer having a tubular configuration;
a second select transistor provided between the memory cells and the source layer in the first direction, the second select transistor including a third electrode layer and a third columnar portion extending in the first direction through the third electrode layer, the third columnar portion including a third semiconductor channel layer of which a first end is electrically connected to the source layer and a second end is electrically connected to the first semiconductor channel layer, the first to third columnar portions being included in a columnar part piercing through the first electrode layers, the second electrode layer, and the third electrode layer in the first direction; and
a first core layer provided inside the tubular configuration of the first and second semiconductor channel layers, the first core layer continuously extending in the first direction through the second electrode layer and at least three layers of the first electrode layers proximal to the second electrode layer,
the third columnar portion of the columnar part having a first diameter in a second direction perpendicular to the first direction and the first columnar portion of the columnar part having a second diameter in the second direction inside a lowermost first electrode layer of the first electrode layers, the first diameter being larger than the second diameter.