Patent ID: 11949016
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 8:
9. A method, comprising:
providing a fin element in a device region;
forming a dummy gate over the fin element;
forming a source/drain feature within a source/drain region adjacent to the dummy gate, wherein the source/drain feature includes a bottom region and a top region contacting the bottom region at an interface interposing the top and bottom regions; and
performing a plurality of dopant implants into the source/drain feature, wherein the plurality of dopant implants includes implantation of a first dopant within the bottom region and implantation of a second dopant within the top region, wherein the first dopant has a first graded doping profile within the bottom region, and wherein the second dopant has a second graded doping profile within the top region.