Patent ID: 11907549
Assignee: QUALCOMM INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 6:
7. A system for allocating data structures to a plurality of processing nodes, each processing node having a respective local memory, the system comprising: a first processor; and a first memory in electrical communication with the first processor, the first memory comprising instructions which, when executed by a processing unit comprising at least one of the first processor and a second processor, and in electronic communication with a memory module comprising at least one of the first memory and a second memory, program the processing unit to: (a) select a set of data structures, each data structure having a read-write ratio greater than a read-write threshold; (b) compute a respective value of a memory access parameter for each data structure; (c) determine a respective duplication factor for each data structure by optimizing a function of the respective values of the memory access parameter, subject to a memory capacity constraint based on a number N of processing nodes, N being greater than one; and (d) generate a statement allocating different portions of the data structure duplicated by each duplication factor, across the plurality of processing nodes, wherein to optimize the function, the processing unit is programmed to solve a mixed integer linear programming representation of the function and the memory capacity constraint, to minimize the function, or to maximize the function.