Patent ID: 11887647
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. An apparatus, comprising:
random access memory having:
a first region configured to store instructions and store matrices of an artificial neural network;
a second region configured to store inputs to the artificial neural network; and
a third region configured to store outputs generated by the artificial neural network responsive to the inputs;

a field-programmable gate array (FPGA) or application specific integrated circuit (ASIC) comprising:
a memory interface to access the random access memory;
a control unit; and
at least one processing unit configured to operate on two matrix operands of an instruction executed in the FPGA or ASIC, wherein the FPGA or ASIC is configured to autonomously execute the instructions stored in the first region to process, using the matrices stored in the first region, the inputs in the second region, wherein the control unit is configured to load, in response to the inputs being written into the second region, the instructions from the first region of the random access memory for execution by the FPGA or ASIC;

a first interface configured for a memory controller of a central processing unit located outside of the apparatus to access the third region of the random access memory; and
a second interface configured for a direct memory access controller located outside of the apparatus to access the second region of the random access memory;
wherein the first interface and the second interface are configured to provide, to the central processing unit and the direct memory access controller, concurrent access to the random access memory; and
wherein the control unit is configured to start autonomous execution of the instructions stored in the first region of the random access memory in response to an indication being written into a predetermined location of the random access memory, the indication including:
an identification of a location in the random access memory where the FPGA or ASIC is to retrieve an input for the autonomous execution; and
an identification of a location in the random access memory where the FPGA or ASIC is to store an output from the autonomous execution.