Patent ID: 11955552
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 5:
6. A semiconductor device structure, comprising:
a first source/drain feature disposed in a first region of the semiconductor device structure, wherein the first source/drain feature comprises a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface;
a first dielectric layer having a first surface and a second surface opposing the first surface, the first surface being a continuous surface in contact with the entire second surface of the first source/drain feature, and the second surface being in contact with an interlayer dielectric;
a first semiconductor layer disposed in the first region of the semiconductor device structure and in contact with the first source/drain feature;
a first gate dielectric layer disposed between and in contact with the continuous surface of the first dielectric layer and the first semiconductor layer;
a first gate electrode layer surrounding a portion of the first semiconductor layer;
a second source/drain feature disposed in a second region of the semiconductor device structure, wherein the second source/drain feature comprises a first surface, a second surface opposing the first surface of the second source/drain feature, and a sidewall connecting the first surface to the second surface of the second source/drain feature;
a second dielectric layer disposed in the second region of the semiconductor device structure; and
a second semiconductor layer disposed in the second region of the semiconductor device structure and in contact with the second source/drain feature.