Patent ID: 11877522
Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A method, implemented by a processor, for determining a critical timing path in a superconducting circuit design, wherein the superconducting circuit design comprises a plurality of logic gates, and wherein each of the plurality of logic gates comprises at least one Josephson junction, the method comprising:
receiving a selection of a first sink terminal having a minimum of a maximum rise time values for single flux quantum (SFQ) pulses from among a plurality of sink terminals associated with a target logic gate selected from among the plurality of logic gates;
receiving an assignment of a phase to the target logic gate;
if the first sink terminal is not reachable within a predetermined range of arrival time, then inserting a first Josephson transmission line (JTL) between a source terminal associated with the target logic gate and the first sink terminal;
upon determining that the first sink terminal is reachable, after an insertion of the first JTL, within the predetermined range of arrival time, removing the first sink terminal from among the plurality of sink terminals as being associated with the critical timing path; and
upon determining that the first sink terminal is not reachable, even after an insertion of the first JTL, within the predetermined range of arrival time, inserting a second JTL between the source terminal associated with the target logic gate and the first sink terminal.