Patent ID: 11876735
Assignee: CISCO TECHNOLOGY, INC.
Field: Digital communication (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 0:
1. A system, comprising:
a primary memory comprising a first buffering capacity and a first memory speed;
a secondary memory communicatively coupled to the primary memory and comprising a second buffering capacity and a second memory speed, the second memory speed being slower than the first memory speed; and
a processor communicatively coupled to the primary memory and the secondary memory, and configured to:
control data packet transmissions received via an input to the primary memory and the secondary memory;
monitor a current buffering level of the primary memory;
compare the current buffering level to a first buffering threshold, the first buffering threshold being indicative of a buffering capacity difference between the first buffering capacity and the second buffering capacity; and
in response to determining that the current buffering level is equal to or greater than the first buffering threshold, pause the data packet transmissions via the input to the primary memory and the secondary memory.