Patent ID: 11915941
Assignee: TOKYO ELECTRON LIMITED
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. The method of claim 1, wherein said adjusting the purge time of the first purge step and/or the purge time of the second purge step comprises:
eliminating the first purge step and/or the second purge step during one or more first cycles of the wet ALE process;
performing the first purge step and/or the second purge step during one or more second cycles of the wet ALE process, wherein the one or more second cycles are performed after the one or more first cycles, and wherein the purge time of the first purge step and/or the purge time of the second purge step performed during the one or more second cycles is insufficient to prevent mixing between the at least one surface modification solution and the dissolution solution; and
performing the first purge step and/or the second purge step during one or more third cycles of the wet ALE process, wherein the one or more third cycles are performed after the one or more second cycles, and wherein the purge time of the first purge step and/or the purge time of the second purge step performed during the one or more third cycles prevents mixing between the at least one surface modification solution and the dissolution solution.