Patent ID: 11971821
Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 27:
28. The method as claimed in claim 23, further comprising:
through a channel between the first die and a second die, operating the first last-level cache to provide the write-back and invalidation request received from the first in-core cache module to a second last-level cache of a second processor fabricated on the second die, wherein the second processor further includes a third core, and the third core includes a third in-core cache module; and
in response to the write-back and invalidation request, operating the second last-level cache to search itself to determine which cache lines within the second last-level cache match the designated key identification code, wherein: if a matched cache line has been modified and does not exist in any upper-level cache, the second last-level cache writes back the matched cache line to the system memory; and, whether modified or not, all matched cache lines within the second last-level cache are invalidated.