Patent ID: 11908534
Assignee: FUJITSU LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A semiconductor device comprising a plurality of built-in memories, wherein
each of the built-in memories includes:
a plurality of memory cells;
a selector circuit that connects a selected memory cell among the memory cells to an outside;
a memory cell relief circuit that, when a fault has occurred in one of the memory cells, transmits, to the selector circuit, a relief signal configured to connect a normal memory cell to the outside without connecting the one of the memory cells in which the fault has occurred, to the outside, and switches selection in the selector circuit; and
an abnormality detection circuit that performs abnormality detection for the memory cell relief circuit, based on a temporal change in the relief signal output from the memory cell relief circuit during an operation, other than testing, of the built-in memories.