Patent ID: 11861452
Assignee: CADENCE DESIGN SYSTEMS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. An integrated circuit comprising:
memory;
processing circuitry configured into a plurality of neural network layers; and
softmax circuitry coupled to the processing circuitry and configured to:
receive, at an input to a softmax circuitry from an output layer of the plurality of neural network layers, a non-normalized output comprising a plurality of intermediate network decision values;
for each intermediate network decision value of the plurality of intermediate network decision values:
calculate a difference between the intermediate network decision value and a maximum network decision value;
request, from a lookup table in the memory, a corresponding lookup table value using the difference between the intermediate network decision value and the maximum network decision value, wherein an index value for each entry value of the lookup table is determined according to index=xj+size(LUT)−max−1, wherein index is the index value, wherein xj is a value of a fixed point value for a corresponding index value, wherein size (LUT) is a number of entry values in the lookup table following removal of entry values having a zero value, and wherein max is a maximum value of all index values of the lookup table; and
select the corresponding lookup table value as a corresponding decision value; and

generate a normalized output comprising the corresponding lookup table value for the each intermediate network decision value of the plurality of intermediate network decision values.