Patent ID: 11901350
Assignee: NANYA TECHNOLOGY CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 4:
5. A method for fabricating a semiconductor device, comprising:
providing a bottom die;
forming a first stacking structure on the bottom die through a plurality of first interconnect units, wherein the plurality of first interconnect units respectively comprise a first exterior layer and a first cavity, the first exterior layer is between the first stacking structure and the bottom die, and the first cavity is enclosed by and directly contacted with the first exterior layer, the first stacking structure, and the bottom die; and
forming a second stacking structure on the bottom die through a plurality of second interconnect units;
wherein the first stacking structure comprises:
a first controller die on the plurality of first interconnect units; and
a plurality of first storage dies stacked on the first controller die and configured as a floating array;
wherein the second stacking structure comprises:
a second controller die on the plurality of second interconnect units; and
a plurality of second storage dies stacked on the second controller die and respectively comprising an insulator-conductor-insulator structure.