Patent ID: 11900885
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 15:
16. a display panel comprising:
a substrate;
a plurality of sub-pixels disposed on a side of the substrate; the plurality of sub-pixels being arranged in a plurality of rows and a plurality of columns, sub-pixels in a row being arranged in a first direction and sub-pixels in a column being arranged in a second direction; and a sub-pixel including a pixel drive circuit and a light-emitting device electrically connected to the pixel drive circuit; and
a gate drive circuit located on a same side of the substrate as the plurality of sub-pixels, wherein the gate drive circuit includes a plurality of cascaded shift registers, and a shift register is electrically connected to a plurality of pixel drive circuits in a row of sub-pixels; the shift register includes a plurality of device groups, and a device group is located in a region between two adjacent sub-pixels in the corresponding row of sub-pixels; and the device group includes at least one transistor and/or at least one capacitor;
wherein the gate drive circuit further includes a plurality of cascade input signal lines and a plurality of cascade display reset signal lines; a cascade input signal line is configured to connect a shift signal terminal of one shift register and an input signal terminal of another shift register; and a cascade display reset signal line is configured to connect a shift signal terminal of one shift register and a display reset signal terminal of another shift register; and
the display panel has a plurality of sub-pixel regions for arranging the plurality of sub-pixels and first gap regions each located between two adjacent columns of sub-pixels regions; and the cascade display reset signal lines and the cascade input signal lines are disposed in the first gap regions, and both are disposed in different first gap regions;
wherein each sub-pixel region includes a sub-pixel circuit region for arranging a corresponding pixel drive circuit and a sub-pixel light-emitting region for arranging a corresponding light-emitting device that are arranged in the second direction;
in the second direction, any three adjacent rows of sub-pixel regions are a first row of sub-pixel regions, a second row of sub-pixel regions, and a third row of sub-pixel regions; and
a region between the first row of sub-pixel regions and the second row of sub-pixel regions is a second gap region, and a region between the second row of sub-pixel regions and the third row of sub-pixel regions is a third gap region;
wherein in the rist row of sub-pixel regions and the second row of sub-pixel regions, sub-pixel light-emitting regions are all closer to the second gap region than sub-pixel cricuit regions; and
in the second row of sub-pixel regions and the third row of sub-pixel regions, sub-pixel circuit regions are all closer to the third gap region than sub-pixel light-emitting regions;
the display panel further comprising:
a plurality of gate lines, wherein each of the gate lines is in a shape of a polyline and substantially extends along the first direction, and a gate line is electrically connected to pixel drive circuits in a row of sub-pixels;
wherein the gate line includes a plurality of first extension segments, a plurality of second extension segments and a plurality of connection segments, each of the first extension segments and each of the second extension segments substantially extend along the first direction, the plurality of first extension segments and the plurality of second extension segments are alternately arranged, and a first extension segment and an adjacent second extension segment are connected by a connection segment; and in the second direction, a distance exists between extension lines of the first extension segment and the adjacent second extension segment;

the first extension segment and two connection segments connected to the first extension segment together constitute a first recess, and an opening of the first recess is disposed towards a side of the gate line away from the third gap region;
the second extension segment and two connection segments connected to the second extension segment together constitute a second recess, and an opening of the second recess is disposed towards the third gap region; and
at least a portion of the pixel drive circuit is located in the first recess or the second recess.