Patent ID: 11942377
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A semiconductor device, comprising:
a semiconductor substrate;
multiple channel regions, including a p-type channel region an n-type channel region, and a third channel region, disposed over the semiconductor substrate;
a high-k gate dielectric layer disposed over each of the channel regions;
an n-type WFM layer over the n-type channel region and not over the p-type channel region or the third channel region, wherein the high-k gate dielectric layer is disposed between the n-type WFM layer and the n-type channel region;
a p-type WFM layer over the n-type WFM layer and over the p-type channel region, but not over the third channel region, wherein the high-k gate dielectric layer is disposed between the p-type WFM layer and the p-type channel region; and
a fill metal layer disposed over the high-k gate dielectric layer.