Patent ID: 11967504
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 3:
4. The method of claim 1, further comprising:
depositing the sacrificial layer around a third nanostructure and a fourth nanostructure using the non-conformal deposition process, wherein the third nanostructure is disposed over and separated from the fourth nanostructure by a second recess in a second device region, wherein patterning the sacrificial layer comprises removing the sacrificial layer from the second device region; and
depositing the first work function tuning layer around the third nanostructure and the fourth nanostructure, wherein after patterning the first work function tuning layer, remaining portions of the first work function tuning layer are disposed around the third nanostructure and the fourth nanostructure.