Patent ID: 11901351
Assignee: SILICON GENESIS CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A method of forming a three-dimensional integrated circuit (3DIC), the method comprising:
forming an interconnect network layer having an interconnect structure on a semiconductor substrate, the interconnect structure having a first plurality of electrodes, a second plurality of electrodes, and a plurality of connection structures coupling the first plurality of electrodes to the second plurality of electrodes, the first plurality of electrodes being exposed on a first surface of the interconnect layer;
implanting ions into the semiconductor substrate to form a cleave plane in the semiconductor substrate;
bonding the interconnect structure to a lower device structure so that electrodes of the first plurality of electrodes are coupled to corresponding electrodes on a lower device structure; and
cleaving the substrate of the bonded interconnect layer at the cleave plane.