Patent ID: 11887853
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. The method of manufacturing the semiconductor device according to claim 6, wherein the step of forming on the doped region a first dielectric layer which covers the first region and exposes the second region of the doped region comprises:
depositing the first dielectric layer covering an upper surface of the doped region, the first dielectric layer having a thickness equal to a width of the first region; and
etching back the first dielectric layer to remove the first dielectric layer located on the upper surface of the gate structure and located on the doped region other than the first region while keeping the first dielectric layer which covers the first region, so as to form an isolating side wall of the gate structure, by which the second region is defined.