Patent ID: 11910616
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A device comprising:
a word line;
a memory layer on a sidewall of the word line;
a channel layer on a sidewall of the memory layer;
a back gate layer on a sidewall of the channel layer;
an isolation region on a sidewall of the back gate layer;
a bit line having a first main region and a first extension region, the back gate layer disposed between the channel layer and the first extension region of the bit line in a top-down view; and
a source line having a second main region and a second extension region, the back gate layer disposed between the channel layer and the second extension region of the source line in the top-down view, the bit line and the source line disposed at opposing sides of the isolation region in the top-down view.