Patent ID: 11954355
Assignee: ATLAS POWER TECHNOLOGIES INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. The apparatus of claim 1 wherein the device is selected as the first device, the first device comprising another circuit for controlling reading out of the information from the plurality of tristate bidirectional memory cells by receiving an address; decoding said address; and activating the first word line or another first word line by another word line driver based upon said decoded address, and activating two corresponding first bit lines by another bit line driver based upon the decoded address, which includes voltage assignment for each first bit line's specific voltage state, and where the apparatus is operable to read and decode the information from the plurality of tristate bidirectional memory cells; if the information is written in a forward bias the information is referred to as positive, or if the information is written with no charge the information is referred to as zero, or if the information is written in a reverse bias the information is referred to as negative.