Patent ID: 11922220
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 18:
19. The semiconductor apparatus of claim 15, wherein the logic coupled to the one or more substrates is to:
analyze an execution function during an initial execution of the function;
store usage data generated from the analysis of the function as a meta data file for subsequent invocation of the execution function, each invocation of the function generating at least one meta data file for the execution function;
reclaim the execution function based on one or more factors, each of the one or more factors indicating execution status of the execution function, the execution status indicating whether to reclaim the execution function; and
apply a security policy to the execution function, the security policy associated with the execution environment of the function, one or more function sets of the execution function being encoded with a same security key.