Patent ID: 11954338
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 18:
19. A memory device, comprising:
a memory array including a plurality of memory cells;
a set of fuse banks including a first fuse bank corresponding to a first defective memory cell, a second fuse bank corresponding to a second defective memory cell, and a third fuse bank corresponding to both the first defective memory cell and the second defective memory cell; and
a repair circuit operatively coupled to the memory array and the set of fuse banks and configured to generate bit-by-bit results of comparisons between at least a portion of an address for memory operations and bit information stored in at least one of the first fuse bank, the second fuse bank, or the third fuse bank, the repair circuit including a first match sub-circuit to provide a first determination of whether the address for memory operations corresponds to the first defective memory cell based on a first portion of the bit-by-bit results and a second match sub-circuit to provide a second determination of whether the address for memory operations corresponds to the second defective memory cell based on a second portion of the bit-by-bit results, the first portion of the bit-by-bit results and the second portion of the bit-by-bit results including bit-by-bit results that are common to both the first portion and the second portion,
wherein the first match sub-circuit and the second match sub-circuit include a common sub-circuit that is configured to receive and compare the common bit-by-bit results, the common bit-by-bit results corresponding to the third fuse bank.