Patent ID: 11954496
Assignee: NVIDIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A system comprising:
a memory; and
a processor comprising processing circuitry to:
determine a total number of iterations;
separate the total number of iterations to determine a plurality of sets of iterations;
based on the total number of iterations, determine a set of iterations of the plurality of sets of iterations includes a first number of iterations that is less than a second number of iterations;
based at least on the first number of iterations being less than the second number of iterations, and during execution of the set of iterations, generate a predicate flag corresponding to a first excess iteration of a number of excess iterations of the set of iterations, wherein the number of excess iterations is associated with a difference between the second number of iterations and the first number of iterations;
based at least on the predicate flag, prevent writing one or more first values corresponding to the first excess iteration of the number of excess iterations of the set of iterations to the memory; and
based on the predicate flag corresponding to the first excess iteration and a second excess iteration of the number of excess iterations of the set of iterations being executed after the first excess iteration of the set of iterations, prevent writing one or more second values corresponding to the second excess iteration of the set of iterations to the memory.