Patent ID: 11963468
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. An integrated chip, comprising:
an inert metal lower electrode disposed on a first interconnect over a substrate;
a metal diffusion barrier on the inert metal lower electrode;
a data storage structure on the metal diffusion barrier;
a metal upper electrode on the data storage structure;
a dielectric spacer disposed along sidewalls and an upper surface of the metal upper electrode;
an insulating layer disposed along sidewalls and an upper surface of the dielectric spacer, the insulating layer vertically extending from below a bottom of the dielectric spacer to over a top of the dielectric spacer; and
a second interconnect extending through the dielectric spacer and the insulating layer to contact the metal upper electrode.