Patent ID: 11870441
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: nan (nan)
Classification: CPC nan | IPC G  H

Claim 8:
9. The clock gating circuit of claim 8, wherein the NOR logic gate comprises:
a first transistor of a second type different from the first type, the first transistor including a gate terminal of the first transistor, a drain terminal of the first transistor and a source terminal of the first transistor, the gate terminal of the first transistor being configured to receive the first enable signal, the drain terminal of the first transistor being coupled to the first node, and the source terminal of the first transistor being coupled to a reference voltage supply; and
a second transistor of the second type including a gate terminal of the second transistor, a drain terminal of the second transistor and a source terminal of the second transistor, the gate terminal of the second transistor being configured to receive the second enable signal, the drain terminal of the second transistor being coupled to the first node and the drain terminal of the first transistor, and the source terminal of the second transistor being coupled to the reference voltage supply.