Patent ID: 11929106
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. The memory device according to claim 6, wherein
the control circuit is further configured to:
in the first detection, apply a first voltage to the first interconnect, then turn the first interconnect into a floating state, and while the first interconnect is in the floating state, apply a second voltage lower than the first voltage to a second interconnect coupled to the first memory cell to decrease the voltage of the first interconnect, and
in the second detection, apply the first voltage to the first interconnect, then turn the first interconnect into the floating state, and while the first interconnect is in the floating state, apply the second voltage to the second interconnect to decrease the voltage of the first interconnect,
each of the first value and the second value is a value obtained by decreasing the voltage of the first interconnect from the first, voltage, and
at least one of the first value and the second value is a value during the decrease in the voltage of the first interconnect.