Patent ID: 11955409
Assignee: QUALCOMM INCORPORATED
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 20:
21. A method for fabricating a substrate, comprising:
providing a core layer with at least one cavity;
placing a match structure in the at least one cavity of the core layer, the match structure comprising:
at least one first match interconnect extending vertically and horizontally in the match structure;
at least one second match interconnect extending vertically in the match structure, wherein the at least one first match interconnect and the at least one second match interconnect are configured for skew matching; and
at least one structure dielectric layer that is located at least laterally to the core layer;

forming at least one first dielectric layer over to a first surface of the core layer; and
forming at least one second dielectric layer over to a second surface of the core layer.