Patent ID: 11869809
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A stacked semiconductor device comprising:
two or more semiconductor components in a stacked array, each of the two or more semiconductor components comprising:
a semiconductor substrate having a circuit side and a back side opposite the circuit side;
a polymer layer having an inner surface in contact with the back side of the semiconductor substrate;
a plurality of conductive vias extending from the circuit side to an outer surface of the polymer layer, each conductive via filled with a conductive metal and comprising
a substrate portion embedded in the semiconductor substrate; and
a terminal via integrally connected to the substrate via and embedded in the polymer layer, the terminal portion having a planarized contact surface generally parallel and coplanar with the outer surface of the polymer layer,
wherein the conductive vias are circumferentially lined with an insulator that extends from the circuit side to the outer surface of the polymer layer; and

a plurality of redistribution conductors on the outer surface of the polymer layer, each of the plurality of redistribution conductors electrically coupled to the terminal portion of an individual one of the plurality of conductive vias,

wherein the two or more semiconductor components are configured to be stacked back side to circuit side with terminal portions of conductive vias of a first semiconductor component bonded to conductive vias at a circuit side of an adjacent second semiconductor component.