Patent ID: 11900120
Assignee: MARVELL ASIA PTE LTD
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A method of scheduling instructions for execution by a processor, said method comprising:
identifying a first instruction in an instruction queue, wherein said first instruction is comprised in a first group of instructions;
identifying a second instruction in said instruction queue, wherein said second instruction is comprised in a second group of instructions;
determining that an instruction, that is comprised in said first group of instructions and said second group of instructions, is identified in said instruction queue;
selecting a first scenario from a plurality of scenarios based on said determining, wherein said first group of instructions and said second group of instructions are both comprised in said first scenario, wherein said first scenario comprises instructions corresponding to a set of instruction opcodes, wherein said set of instruction opcodes is defined to avoid conflicts among said first instruction and said second instruction with respect to parallel execution of said first instruction and said second instruction by said processor, and wherein further said first instruction and said second instruction are compatible with respect to said parallel execution; and
selecting said first instruction and said second instruction for issuing to corresponding functional units of said processor for parallel execution.