Patent ID: 11868813
Assignee: HT RESEARCH INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 19:
20. A computer system comprising:
a third execution pylon; and
a third fail-over pylon coupled to the third execution pylon through a third workgroup fail-over link, wherein the third fail-over pylon is configured to provide real time fail-over support to the third execution pylon, wherein the third fail-over pylon includes a third fail-over communication link,
wherein the third execution pylon comprises:
a third top control block;
a third mid-memory block coupled to the third top control block through a third plurality of first workgroup execution links; and
a third base attribute block coupled to the third mid-memory block through a third plurality of second workgroup execution links;

wherein the third base attribute block comprises:
an array execution pylon coupled to the third mid-memory block through the third plurality of second workgroup execution links;
a matrix execution pylon coupled to the third mid-memory block through the third plurality of second workgroup execution links; and
a tie execution pylon coupled to the third mid-memory block through the third plurality of second workgroup execution links,

wherein the matrix execution pylon comprises:
a first top control block;
a first mid-memory block coupled to the first top control block through a first plurality of first workgroup execution links; and
a first base attribute block coupled to the first mid-memory block through a first plurality of second workgroup execution links;

wherein the first base attribute block comprises:
a first first-type base block;
a plurality of second-type base blocks, each coupled to the first first-type base block through a first plurality of third workgroup execution links;
a plurality of third-type base blocks coupled to the plurality of second-type base block through a first plurality of fourth workgroup execution links so that the plurality of second-type base block are disposed between the first first-type base block and the plurality of third-type base blocks,
wherein one of the plurality of third-type base blocks is coupled to the first mid-memory block through the first plurality of second workgroup execution links,

wherein the tie execution pylon comprises:
a second top control block;
a second mid-memory block coupled to the second top control block through a second plurality of first workgroup execution links; and
a second base attribute block coupled to the second mid-memory block through a second plurality of second workgroup execution links;
wherein the second base attribute block comprises a plurality of the matrix execution pylons.