Patent ID: 11929347
Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC H

Claim 11:
12. The method of claim 1, wherein:
(i) exposing the second region of the first base die and (ii) exposing the second region of the second base die exposes metal fill for backend of line (BEOL) layers of the first base die and the second base die; and
the method further comprises:
exposing the second region of the first base die using the second photolithographic-exposure apparatus a second time to expose through silicon vias (TSVs) in the second region of the first base die; and
exposing the second region of the second base die using the second photolithographic-exposure apparatus a second time to expose through TSVs in the second region of the second base die.