Patent ID: 11929748
Assignee: STMICROELECTRONICS (ROUSSET) SAS
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 14:
15. A system, comprising:
a memory; and
a wobulated signal generator coupled to the memory, the wobulated signal generator including:
a chain of delay elements including first delay elements, second delay elements, and third delay elements;
control circuitry coupled to the chain of delay elements; and
an output node coupled to the chain of delay elements, wherein the control circuitry, in operation:
enables a number of the first delay elements;
disables a number of the third delay elements;
enables a selected number of the second delay elements, defining a period of time between two consecutive rising edges of a digital wobulated signal at the output node;
monitors an average frequency of the digitally wobulated signal; and
selectively modifies the number of enabled first delay elements and the number of disabled third delay elements based on the monitored average frequency of the digitally wobulated signal.