Patent ID: 11876535
Assignee: SILICON MOTION, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A method for controlling data in a decoding pipeline, for use in a data storage device, wherein the data storage device comprises a memory controller and a flash memory, and a data-reading procedure of the flash memory comprises a low-density parity-check (LDPC) decoding procedure, and the memory controller comprises a memory-index control circuit and a decoder, and the LDPC decoding procedure comprises an initial phase, a decoding phase, and an output phase, the method comprising:
after the data storage device is booted up, utilizing the decoder to read a plurality of first codewords from a variable-node memory using a first order via the memory-index control circuit for LDPC decoding; and
in response to the decoder determining that a specific codeword among the first codewords has decoding failure, resetting the decoder to read a plurality of second codewords from the variable-node memory using a second order via the memory-index control circuit for LDPC decoding,
wherein the first order is different from the second order.