Patent ID: 11903222
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 0:
1. A method of manufacturing a memory device, the method comprising:
forming a stack structure by repeatedly and alternately depositing a sacrificial layer and an isolating layer on a substrate;
forming a channel hole penetrating through the stack structure;
removing a portion of the sacrificial layer such that an inner surface of the channel hole has a concavo-convex shape in a first direction perpendicular to a stack direction of the stack structure;
sequentially forming a gate insulating layer, a channel layer, and a recording material layer on the inner surface of the channel hole;
depositing an insulating material in the channel hole;
forming a gate hole by removing all of a remaining portion of the sacrificial layer; and
depositing an electrode material in the gate hole.