Patent ID: 11901352
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A device structure, comprising:
a substrate comprising an n-well disposed between a first p-well and a second p-well along a first direction;
a first active region and a second active region disposed over the n-well and extending along a second direction perpendicular to the first direction;
a third active region and a fourth active region disposed over the first p-well and extending along the second direction;
a fifth active region and a sixth active region disposed over the second p-well and extending along the second direction;
a first gate structure disposed over the third active region;
a second gate structure disposed over the fourth active region;
a third gate structure disposed over the fifth active region; and
a fourth gate structure disposed over the sixth active region,
wherein the first gate structure and the fourth gate structure are electrically coupled together by way of a first word line disposed in a first metal layer,
wherein the second gate structure and the fourth gate structure are electrically coupled together by way of a second word line disposed in a second metal layer different from the first metal layer.