Patent ID: 11894067
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 3:
4. The memory apparatus as set forth in claim 3, wherein the control means further includes a garbage collector configured to prepare the plurality of blocks for an erase operation, the control means is further configured to:
set the one of the plurality of blocks inaccessible and let the one of the plurality of blocks relax for the predetermined relaxation time after the data has been relocated,
set the one of the plurality of blocks accessible and send it to the garbage collector once the predetermined relaxation time has elapsed,
finish one of the erase operation and a program operation of the one of the plurality of blocks after setting the one of the plurality of blocks being accessible, and
determine and record the current time stamp after finishing one of the erase operation and the program operation of the one of the plurality of blocks.