Patent ID: 11882703
Assignee: SK HYNIX INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A method of manufacturing a semiconductor memory device, comprising:
forming a stacked body by alternately stacking a plurality of interlayer insulating layers and a plurality of sacrificial layers on a substrate;
forming a plurality of holes configured to vertically pass through the stacked body; and
successively forming a blocking insulating layer, a charge storage layer, a tunnel insulating layer, a first channel layer, a second channel layer, and a third channel layer on a sidewall of each of the plurality of holes,
wherein the first channel layer and the third channel layer are formed of a same material, and
wherein each of the first channel layer and the third channel layer is a material layer having higher electron mobility than the second channel layer.