Patent ID: 11961802
Assignee: TOKYO ELECTRON LIMITED
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A method of microfabrication, comprising:
forming a device plane including an array of cells each including a transistor device, the device plane formed on a working surface of a substrate, the device plane having a front side and a backside opposite the front side;
forming a buried power rail (BPR) that is positioned below the device plane on the backside of the device plane;
forming a signal wiring structure on the front side of the device plane;
forming a front-side power distribution network (FSPDN) on the front side of the device plane; and
forming a power tap structure in the device plane, the power tap structure electrically connecting the BPR to the FSPDN and electrically connecting the BPR to the transistor device to provide power to the transistor device.