Patent ID: 11954040
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A device comprising:
a first tier comprising only one tier having a processor and cache control logic configured to operate as a computing architecture, wherein the processor and the cache control logic are disposed together in the only one tier in the first tier without cache memory being disposed in the only one tier in the first tier;
a snoop filter operably connected to the cache control logic and configured for coherence tracking;
a second tier having a first cache memory coupled to the processor via the cache control logic in the first tier, wherein only the first cache memory is disposed in the second tier, and wherein the second tier is separate from the first tier; and
a third tier having a second cache memory coupled to the first cache memory in the second tier, wherein only the second cache memory is disposed in the third tier, and wherein the third tier is separate from the first tier and the second tier,
wherein the first tier, the second tier and the third tier are integrated together with the computing architecture to operate as a stackable cache memory architecture.