Patent ID: 11910621
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Electrical machinery, apparatus, energy (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for manufacturing a memory device comprising:
forming a dielectric layer over a substrate;
forming a bottom electrode via opening in the dielectric layer;
forming a bottom electrode in the bottom electrode via opening;
etching back the bottom electrode, wherein a bottom surface of the bottom electrode is substantially coplanar with a bottom surface of the dielectric layer;
forming a selector in the bottom electrode via opening and over and in direct contact with the bottom electrode;
forming a capping layer in the bottom electrode via opening and over and in direct contact with the selector, wherein a sidewall of the bottom electrode, a sidewall of the selector, and a sidewall of the capping layer are coplanar, wherein forming the capping layer comprises:
depositing a capping material in the bottom electrode via opening and over the dielectric layer; and
planarizing the capping material with a top surface of the dielectric layer to form the capping layer in the bottom electrode via opening;

forming a memory material layer over and in direct contact with the planarized capping layer;
forming a top electrode layer over the memory material layer; and
etching the top electrode layer and the memory material layer to form a memory layer over the capping layer and a top electrode over the memory layer, wherein an entire of a top surface of the memory layer is wider than an entire of a top surface of the capping layer, and the memory layer is in direct contact with the top surface of the capping layer.