Patent ID: 11942950
Assignee: ELITE SEMICONDUCTOR MICROELECTRONICS TECHNOLOGY INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An input clock buffer, comprising:
a first capacitor;
a second capacitor;
a first amplifier, configured to generate a first output signal, comprising a first input terminal coupled to the first capacitor and comprising a second input terminal coupled to the second capacitor, wherein the first capacitor and the second capacitor receives a differential input signal and form a first pair of signal paths for the differential input signal;
a second amplifier, configured to generate a second output signal, comprising a first input terminal and a second input terminal, wherein the first input terminal of the second amplifier and the second input terminal of the second amplifier form a second pair of signal paths for the differential input signal;
a frequency detection circuit, configured to generate a frequency detection signal according to a frequency of the differential input signal; and
a switch, located between an output of the first amplifier and an output of the second amplifier, configured to turn on and turn off according to the frequency detection signal.