Patent ID: 11967368
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory system comprising:
a nonvolatile semiconductor memory device comprising:
first to n-th strings, where n is an integer of 2 or more, each of the first to n-th strings including a plurality of memory cells and a select transistor, the plurality of memory cells being connected in series, the select transistor being electrically connected in series with the memory cells, the memory cells including a first memory cell, a second memory cell and a third memory cell, the memory cells storing 4-bit data by correlating first to fourth bits with sixteen threshold regions including a first threshold region indicating an erased state in which data is erased and second to sixteenth threshold regions having a higher voltage level than that of the first threshold region and indicating a written state in which data is written;
a bit line electrically connected to the first to n-th strings;
first to n-th select gate lines, a k-th, where k is an integer that satisfies 1≤k≤n, select gate line electrically connected to a gate of the select transistor of a k-th string;
a first word line electrically connected to gates of the first memory cells of the first to n-th strings;
a second word line electrically connected to gates of the second memory cells of the first to n-th strings;
a third word line electrically connected to gates of the third memory cells of the first to n-th strings, and
a memory controller configured to perform first to n-th write processes, to perform (n+1)-th to 2n-th write processes after the first to n-th write processes, to perform (2n+1)-th to 3n-th write processes after the (n+1)-th to the 2n-th write processes, to perform (3n+1)-th to 4n-th write processes after the (2n+1)-th to the 3n-th write processes and to perform (4n+1)-th to 5n-th write processes after the (3n+1)-th to the 4n-th write processes, wherein
the (e+1)-th (e is an integer that satisfies 1≤e≤(n−1)) write process is performed after the e-th write process,
the (f+1)-th (f is an integer that satisfies (n+1)≤f≤(2n−1)) write process is performed after the f-th write process,
the (g+1)-th (g is an integer that satisfies (2n+1)≤g≤(3n−1)) write process is performed after the g-th write process,
the (h+1)-th (h is an integer that satisfies (3n+1)≤h≤(4n−1)) write process is performed after the h-th write process,
the (i+1)-th (i is an integer that satisfies (4n+1)≤i≤(5n−1)) write process is performed after the i-th write process,
the k-th write process includes writing data corresponding to the first bit, the second bit and the fourth bit in the first memory cell of the k-th string,
the (n+k)-th write process includes writing data corresponding to the first bit, the second bit and the fourth bit in the second memory cell of the k-th string,
the (2n+k)-th write process includes writing data corresponding to the third bit in the second memory cell of the k-th string,
the (3n+k)-th write process includes writing data corresponding to the first bit, the second bit and the fourth bit in the third memory cell of the k-th string,
the (4n+k)-th write process includes writing data corresponding to the third bit in the second memory cell of the k-th string,
the memory controller is configured to perform the writing data corresponding to the first bit, the second bit and the fourth bit in the memory cell such that a threshold region in the memory cell becomes any threshold region of a seventeenth threshold region indicating an erased state in which data is erased and eighteenth to twenty-fourth threshold regions having a higher voltage level than that of the seventeenth threshold region and indicating a written state in which data is written according to the data of the first bit, the second bit and the fourth bit, and
the memory controller is configured to perform the writing data corresponding to the third bit in the memory cell such that the threshold region in the memory cell becomes any threshold region in two threshold regions among the first to sixteenth threshold regions from any threshold region of the seventeenth to twenty-fourth threshold regions according to the data of the third bit.