Patent ID: 11947254
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Optics (Instruments)
Classification: CPC G | IPC G

Claim 7:
8. A system of semiconductor manufacturing, comprising:
a processor;
a testing tool coupled to the processor;
a mask manufacturing tool coupled to the processor; and
an IC manufacturing tool coupled to the processor;
wherein the processor is configured to:
calculate a first grid pattern density map associated with a device layout and a second grid pattern density map associated with the device layout, wherein a density of a first grid volume of the first grid pattern density map is larger than a density of a second grid volume of the second grid pattern density map;
calibrate an optical proximity correction (OPC) model by adjusting a plurality of parameters including a first set of parameters and a second set of parameters, wherein the first set of parameters indicate a long-range effect caused by an electron-beam lithography tool for making a mask used to manufacture a structure, and the second set of parameters indicate a geometric feature of a structure or a manufacturing process to make the structure, wherein the second grid pattern density map is used during the calibration;
perform an OPC to generate a corrected mask layout, at least based on the calibrated OPC model and using the first grid pattern density map;
control the IC manufacturing tool to use the corrected mask layout to expose a resist layer on a wafer to form a patterned resist layer;
determine whether a measured critical dimension (CD) of the patterned resist layer is within a predetermined range;
adjust the second set of parameters without modifying the first set of parameters if the determined measured CD is not within the predetermined range;
iteratively perform the calibrating the OPC model, the performing the OPC, and the adjusting the second set of parameters until the measured CD is within the predetermined range to generate a final corrected mask layout;
control the mask manufacturing tool to produce the final corrected mask layout as a mask; and
control the IC manufacturing tool to produce a photo resist pattern on a wafer.