Patent ID: 11972144
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. An apparatus, comprising:
a memory array comprising a plurality of memory cells configured to store data; and
a controller coupled with the memory array and configured to:
receive a first command associated with a first operation on the data, wherein the first command comprises an assignment of the first operation to a queue slot of a status bank;
receive a second command requesting a status of the first operation based at least in part on receiving the first command, wherein the second command is associated with an output of status for the status bank on a data bus coupled with a plurality of devices, a device of the plurality of devices comprising the memory array and the controller;
receive a third command associated with a second operation on the data, wherein the third command is associated with a third plane of the memory array, and wherein the third command comprises a second assignment of the second operation to a second queue slot of the status bank that is different than the queue slot;
generate a bit indicating the status of the first operation performed on the memory array based at least in part on receiving the second command; and
output the bit onto a first channel of the data bus based at least in part on generating the bit and an association between the assigned queue slot of the status bank and the first channel.