Patent ID: 11929105
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 6:
7. A reading/writing method of a magnetic memotv, wherein the magnetic memory comprises at least one cell layer, and the cell layer comprises:
a plurality of parallel first wires, disposed in a first plane;
a plurality of parallel second wires, disposed in a second plane, the first plane being parallel to the second plane, and projections of the second wires onto the first plane intercrossing the first wires; and
a plurality of storage elements, disposed between the first plane and the second plane; the storage elements comprising magnetic tunnel junctions and bi-directional gating components connected in series along a direction perpendicular to the first plane, the magnetic tunnel junctions being connected to the first wires, the bi-directional gating components being connected to the second wires, and the bi-directional gating components being configured to be conductive upon application of at least one of a threshold voltage or a threshold current; wherein the first wires comprise first ends and second ends, the magnetic memory further comprises a plurality of write bitlines and a plurality of first selection transistors, and the first selection transistors are configured to electrically connect the first ends of the first wires to the write Wines in response to a first control signal;
the reading writing method comprising:
providing a first current and a second current to the magnetic memory while performing a write operation thereon, the first current passing through the first wires but not through the storage elements, the second current passing through selected storage elements, and the first current and the second current equalizing changing trends for resistances of the magnetic tunnel junctions to increase or decrease;
the reading writing method further comprising:
controlling the first selection transistors through the first control signal, so that the first selection transistors electrically connect the first ends of the first wires to the write bitlines in response to the first control signal, so as to enable the first current to pass through the first wires but not through the storage elements.