Patent ID: 11942145
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A method for memory cell placement, comprising:
placing a memory cell region in a layout area;
placing, in the layout area, a well pick-up region and a first power supply routing region along a first side of the memory cell region;
placing, in the layout area, a second power supply routing region and a bitline jumper routing region along a second side of the memory cell region, wherein the second side is on an opposite side to that of the first side; and
placing, in the layout area, a device region along the second side of the memory cell region, wherein the bitline jumper routing region is between the second power supply routing region and the device region, and wherein placing the memory cell region, the well pick-up region, the first power supply routing region, the second power supply routing region, the bitline jumper routing region, and the device region are performed by one or more processors.