Patent ID: 11886341
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. An apparatus, comprising:
a memory system comprising memory configured as a cache; and
a controller coupled with the memory system, wherein the controller is configured to:
transmit a mapping between logical and physical addresses of a first region of the memory system associated with a first read request;
receive a second read request based at least in part on transmitting the mapping, the second read request comprising a physical address of the memory system;
identify an index in a table stored in the cache, wherein the index is associated with the physical address, and wherein the table comprises a plurality of indices each associated with respective logical and physical addresses of respective regions of the memory system;
promote the index to a first position in the table;
transmit data from the physical address associated with the second read request;
transmit a mapping between logical and physical addresses of a second region of the memory system associated with a third read request;
receive a fourth read request, the fourth read request comprising a second physical address of the memory system;
determine whether the second physical address is associated with the second region associated with the third read request;
identify a second index in the table stored in the cache, wherein the second index is associated with the second physical address;
refrain from promoting the second index to a first position in the table based at least in part on determining that the second physical address is not associated with the second region associated with the third read request; and
transmit second data from the second physical address associated with the fourth read request.