Patent ID: 11908784
Assignee: NXP USA, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A semiconductor device comprising:
a packaged semiconductor product including:
a package substrate,
a die having a first major surface attached to a first major surface of the package substrate,
electrical connections between the die and the first major surface of the package substrate,
an encapsulant surrounding the die and the electrical connections, and
interconnect pads formed on a second major surface of the package substrate;

a reinforcing interposer including:
a first set of interconnect pads on a first major surface of the reinforcing interposer,
a second set of interconnect pads on a second maj or surface of the reinforcing interposer,
one or more routing layers, and
for each of the interconnect pads in the first and second sets of interconnect pads, conductive material extending through the one or more routing layers connecting one of the first set of interconnect pads on the first major surface of the reinforcing interposer to a corresponding one of the second set of interconnect pads on the second maj or surface of the reinforcing interposer;

for each of the interconnect pads on the package substrate and each of the first set of interconnect pads on the reinforcing interposer, low temperature solder material connecting one of the interconnect pads on the package substrate to a corresponding one of the first set of interconnect pads on the reinforcing interposer
a printed circuit board;
a first set of interconnect pads on a first major surface of the printed circuit board;
for each of the interconnect pads on the second major surface of the reinforcing interposer and the first set of interconnect pads on the first major surface of the printed circuit board, low temperature solder material connecting one of the first set of interconnect pads formed on the first major surface of the printed circuit board to a corresponding one of the second set of interconnect pads on the second major surface of the reinforcing interposer;
a first adhesive layer between the second major surface of the package substrate and the first major surface of the reinforcing interposer; and
a second adhesive layer between the second major surface of the reinforcing interposer and the first major surface of the printed circuit board, wherein the second adhesive layer is in direct contact with the second major surface of the reinforcing interposer and in direct contact with the first major surface of the printed circuit board.