Patent ID: 11943940
Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  B | IPC H

Claim 18:
19. A memory apparatus, comprising:
(a) a substrate;
(b) a plurality of electrodes mounted to the substrate; and
(c) an array of cross-wire memory units, each unit comprising:
(1) a first plurality of conductive nanowires, each nanowire having two ends with each end coupled to an electrode;
(2) a second plurality of conductive nanowires, each nanowire having two ends with each end coupled to an electrode; wherein each nanowire in the first plurality of conductive nanowires crossing over a nanowire in the second plurality of conductive nanowires; and
(3) a plurality of nucleic acid-based memory elements, each said memory element connecting a first nanowire with a second nanowire; wherein each said memory element having a controlled conductance to encode a data bit.