Patent ID: 11908533
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An operation method of a memory device including a leakage detecting circuit and a row decoder configured to control a voltage of a first word line through a first driving line, the method comprising:
floating the first driving line from the first word line and precharging the first driving line with a first voltage;
floating the first driving line from the first voltage to sense a first voltage variation of the first driving line;
storing the first voltage variation in a first capacitor of the leakage detecting circuit;
electrically connecting the first driving line to the first word line and precharging the first driving line and the first word line with the first voltage;
floating the first driving line and the first word line from the first voltage to sense a second voltage variation of the first driving line and the first word line; and
outputting, by the leakage detecting circuit, a first detection signal corresponding to a first leakage current through the first word line based on the first voltage variation stored in the first capacitor and the second voltage variation.