Patent ID: 11955463
Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 33:
34. A method comprising:
forming a directly bonded die stack by directly bonding a first bonding surface of at least a first integrated device die and a second bonding surface of at least a second integrated device die without an adhesive;
providing a top die over the directly bonded die stack, the top die having a footprint larger than at least one of the first and second integrated device dies;
providing a non-die layer between the top die and the directly bonded die stack, wherein providing the non-die layer comprises providing a compliant layer between the top die and the directly bonded die stack;
providing a first lateral die support layer disposed along at least a portion of a sidewall of the first integrated device die, an entirety of the first lateral die support layer disposed laterally outside a footprint of the first integrated device die; and
providing a second lateral die support layer disposed laterally adjacent the top die and at least a portion of the first lateral die support layer, an entirety of the second lateral die support layer disposed laterally outside the directly bonded die stack.