Patent ID: 11967595
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC B  H

Claim 12:
13. A semiconductor device comprising:
a substrate comprising a first region and a second region;
a first nanowire spaced apart from the substrate in the first region;
a second nanowire spaced apart from the substrate in the second region;
a first gate insulating layer surrounding the first nanowire;
a second gate insulating layer surrounding the second nanowire;
a first metal layer surrounding the first nanowire, on the first gate insulating layer;
a first gate electrode surrounding the first nanowire, on the first metal layer, wherein the first metal layer is between the first gate insulating layer and the first gate electrode;
a first gate spacer on a sidewall of the first gate electrode; and
a second metal layer surrounding the second nanowire, on the second gate insulating layer,
wherein the first gate spacer includes:
a first inner spacer between the substrate and the first nanowire;
a second inner spacer on a top surface of the first nanowire; and
an outer spacer being in contact with a top surface of the second inner spacer,

wherein the outer spacer has a first dielectric constant, and
wherein the first inner spacer and the second inner spacer have a second dielectric constant different from the first dielectric constant.