Patent ID: 11925011
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 3:
4. The memory structure of claim 1, wherein the dummy FinFET is a first dummy FinFET and the p-type epitaxial source/drains are first p-type epitaxial source/drains, and in the second region, the memory structure further includes a second dummy FinFET disposed over the first p-well, wherein:
the second dummy FinFET includes a third p-type semiconductor fin extending from the first p-well, wherein the third p-type semiconductor fin extends lengthwise along the second direction and the third p-type semiconductor fin has the second width;
the second dummy FinFET includes second p-type epitaxial source/drains disposed on the second p-type semiconductor fin; and
a spacing is between the second p-type semiconductor fin and the third p-type semiconductor fin along the first direction and no semiconductor fins extend from the n-well in the spacing between the second p-type semiconductor fin and the third p-type semiconductor fin.