Patent ID: 11875184
Assignee: METISX CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A manycore system comprising:
one or more clusters comprising a plurality of cores; and
a memory access module that controls access to a memory associated with one or more cores of the one or more clusters,
wherein the memory access module is configured to:
after a thread associated with one or more tasks according to an offloading request from a host processor is created and allocated to the one or more cores, receive translation setting information for determining a physical address of data in a memory associated with the one or more cores accessed by the thread;
receive the identification information of the thread accessing the memory;
receive a virtual address of data accessed by the thread; and
determine a physical address of the data in the memory based on the translation setting information, the virtual address, and the identification information of the thread, and
the determining is performed by the memory access module without intervention of an operating system of the manycore system.