Patent ID: 11894332
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A device comprising:
a substrate comprising:
first pads in a core area of the substrate;
second pads in a corner area of the substrate; and
third pads in an edge area of the substrate, the edge area extending around each side of the core area in a top-down view, a widest portion of the third pads having a lesser width than a widest portion of the first pads and a widest portion of the second pads in a cross-sectional view; and

a chip comprising bumps, each of the bumps having a substantially same width as the widest portion of the first pads and the widest portion of the second pads in the cross-sectional view, a first subset of the bumps connected to the first pads of the substrate, a second subset of the bumps connected to the second pads of the substrate, a third subset of the bumps connected to the third pads of the substrate.