Patent ID: 11880599
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A memory device, comprising:
a data register storing data requested by a data read command;
a status register storing status information of the memory device; and
a control logic controlling an operation of the memory device; and
wherein the control logic is configured to:
receive the data read command from a memory controller in order to read the data stored in the memory device;
receive N read enable toggle signals (N is a natural number greater than or equal to 2) from the memory controller to output the data requested by the data read command;
receive an additional read enable toggle signal from the memory controller, after the N read enable toggle signals are inputted from the memory controller and the data requested by the data read command is outputted to the memory controller;
output the status information of the memory device to the memory controller in response to the additional read enable toggle signal inputted from the memory controller; and
switch an activated register for outputting the data to the memory controller from the data register to the status register after receiving the N read enable toggle signals.