Patent ID: 11879938
Assignee: NAGRAVISION SàRL
Field: Measurement (Instruments)
Classification: CPC G  H | IPC G

Claim 9:
10. A logic circuit for implementing the method of claim 1 while processing data operations along a plurality of datapaths coordinated by a clock signal, comprising at least one test circuit configured to operate according to a calibration mode and a detection mode, said calibration mode being designed to determine a critical propagation delay of a digital signal through at least one of said datapaths, and said detection mode being designed to detect a perturbation in the logic circuit, said at least one test circuit comprising:
first registers configured to be loaded with inputs,
a logic unit storing a function configured to calculate a Boolean result from a computation using two operands to provide an output from the inputs,
second registers for storing expected outputs provided by the function for said inputs,
a comparator configured to verify whether the output is equal to one of the expected outputs,
an error generator for outputting an error in case the comparator provides a negative event,
a programmable length datapath for varying a propagation delay of the digital signal allowing to get the output from the input, wherein one of the first registers is connected to the programmable length datapath and
a switching unit for switching calibration mode into detection mode and for switching detection mode into calibration mode.