Patent ID: 11870444
Assignee: PUFSECURITY CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 11:
12. The entropy source circuit of claim 11, wherein the flag signal generator comprises:
an inverter, configured to receive the start signal;
a first AND gate, wherein a first input terminal of the first AND gate is coupled to an output terminal of the inverter, and a second input terminal of the first AND gate is configured to receive the determination signal;
a first flip-flop, wherein a data input terminal of the first flip-flop is coupled to an output terminal of the first AND gate, and a clock terminal of the first flip-flop is configured to receive the system clock;
a second AND gate, wherein a first input terminal of the second AND gate is coupled to the output terminal of the inverter, and a second input terminal of the second AND gate is coupled to a data output terminal of the first flip-flop;
a second flip-flop, wherein a data input terminal of the second flip-flop is coupled to an output terminal of the second AND gate, and a clock terminal of the second flip-flop is configured to receive the system clock; and
an exclusive-OR (XOR) gate, coupled to the first flip-flop and the second flip-flop, configured to perform an XOR logic operation on an output of the first flip-flop and an output of the second flip-flop, in order to generate the flag signal.