Patent ID: 11959939
Assignee: NANYA TECHNOLOGY CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 10:
11. A chip testing method comprising:
forming a chip socket comprising a plurality of clamp structures and a plurality of electrical contacts, wherein each of the plurality of clamp structures comprises a conductive body, and a gap formed in a middle of the conductive body and surrounded by first and second sidewalls of the conductive body, wherein the first sidewalls are longer than the second sidewalls, the first sidewalls and the second sidewalls are contacted with each other so that the gap includes a closed opening with a first width and a bottom with a second width, the first width of the closed opening of the gap and the second width of the bottom of the gap are identical, the first width of the closed opening of the gap and the second width of the bottom of the gap are smaller than a third width of one of solder balls of a first chip to be tested;
mounting the plurality of electrical contacts of the chip socket on a first circuit board;
attaching the first chip to the chip socket by inserting the solder balls of the first chip into the gaps of the plurality of clamp structures, increasing the first width of the closed opening of the gap to accommodating and clamping the one of the solder balls of the first chip with the plurality of clamp structures of the chip socket, wherein the first width of the closed opening of the gap is increased to be greater than the second width of the bottom of the gap; and
testing the first chip by sending signals to and receiving signals from the first chip through the first circuit board.