Patent ID: 11923200
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. An integrated circuit comprising:
a gate structure over a substrate;
a first silicon-containing material structure in a recess adjacent to the gate structure, wherein the first silicon-containing material structure comprises:
a first layer having an uppermost surface below a top surface of the substrate and a bottommost surface in direct contact with the substrate;
a second layer over the first layer, wherein an entirety of the second layer is above the top surface of the substrate, a first region of the second layer closer to the gate structure has a variable thickness, a second region of the second layer farther from the gate structure has a uniform thickness, and thickness is measured in a direction perpendicular to the top surface of the substrate; and
a third layer between the first layer and the second layer, wherein an entirety of the third layer is below the top surface of the substrate; and

a lightly doped drain (LDD) extending from the first silicon-containing material in a direction parallel to the top surface of the substrate, wherein the LDD directly contacts the third layer.