Patent ID: 11901279
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor package, comprising:
a semiconductor die;
an encapsulant laterally encapsulating the semiconductor die; and
a redistribution structure disposed on the encapsulant along a stacking direction, overlapping with the semiconductor die and electrically connected with the semiconductor die, wherein the redistribution structure comprises a first conductive via, a first conductive wire, a second conductive via, a first dielectric layer and a second dielectric layer, the first conductive via, the first conductive wire and the second conductive via are arranged along the stacking direction, the first conductive via has a first via surface contacting the first conductive wire, the second conductive via has a second via surface contacting the first conductive wire, an area of a first cross section of the first conductive via is greater than an area of the first via surface of the first conductive via, an area of a second cross section of the second conductive via is greater than an area of the second via surface of the second conductive via, the first via surface of the first conductive via and the first conductive wire are wrapped by the first dielectric layer, the second via surface of the second conductive via is substantially coplanar with a bottom surface of the second dielectric layer, and the second conductive via is farther away the semiconductor die than the first conductive via.