Patent ID: 11950402
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A method comprising:
forming levels of materials, the levels of materials including a dielectric material;
forming first trenches in at least the dielectric material, each of the first trenches including a length in a first direction, a first side wall formed by a first portion of the dielectric material, and a second side wall formed by a second portion of the dielectric material;
forming materials in the first trenches including forming first charge storage material in the first trenches, forming second charge storage material separated from the first charge storage material in the first trenches, and forming a conductive material between and separated from the first and second charge storage materials; and
forming second trenches extending in a second direction across the materials in the first trenches including the first and second charge storage materials, and the conductive material to form memory cells from a remaining part of the materials in the first trenches including a remaining part of the first and second charge storage materials, such that a first memory cell of the memory cells is adjacent a portion of the first side wall of a trench of the first trenches, a second memory cell of the memory cells is adjacent a portion of the second side wall of the trench of the first trenches, and such that the remaining part of the first and second charge storage materials form respective charge storage structures of the first and second memory cells, and a portion of the conductive material is between the charge storage structures of the first and second memory cells.