Patent ID: 11907133
Assignee: SAFEGRAPH, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. A system including one or more processors coupled to memory, the memory loaded with computer instructions that when executed on the processors, implement actions comprising:
receiving an address string for a place-of-interest, wherein the address string has a plurality of address substrings;
one-to-one mapping respective address substrings in the address string to respective address components;
one-to-many mapping at least one of the address substrings to two or more address components, and partitioning a one-to-many mapped address substring into address substrings that correspond to respective address components;
using a template that specifies an order of concatenating the address substrings, and concatenating the address substrings according to the specified order; and
making the address substrings concatenated in the specified order available for further use, wherein a model processes the address string as input through a convolutional neural network and generates a substring-by-substring output that classifies each of the output substrings as the address substrings and non-address substrings, wherein the convolutional neural network uses trigram layers and residual connections to mix information from words on either side of a target word so that an output word is of a same dimensionality as the target word.