Patent ID: 11869589
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. A method, comprising:
maintaining a data structure listing locations of invalid data stored in a main content addressable memory mapped to corresponding locations of data stored in a buffer content addressable memory, wherein to maintain the data structure includes maintaining an entry for a first location of first data written to the main content addressable memory mapped to a second location of the first data written to the buffer content addressable memory until a threshold amount of time has elapsed from a time when the first data is written to the main content addressable memory; and
utilizing the data structure to determine whether to substitute a result of a comparison of the second location of the first data written to the buffer content addressable memory to input data for a result of a comparison of the first location of the first data written to the main content addressable memory to the input data; and
wherein the first data is written concurrently to the first location in the main content addressable memory and to the second location in the buffer content addressable memory.