Patent ID: 11868696
Assignee: SYNOPSYS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A method for designing a circuit, the method comprising:
adding, to a circuit design, a power switch lacking an input supply port and an output supply port, wherein the power switch is configured to produce an output over an acknowledgement port;
adding, to the circuit design, an isolation circuit lacking isolation power circuitry and corruption circuitry, wherein the isolation circuit comprises a driver configured to clamp an output of the isolation circuit, and wherein a select pin of the isolation circuit controls whether the isolation circuit outputs the clamped output or an input value;
adding, to the circuit design, a retention circuit comprising:
a clock gating enabled register;
a first AND gate, wherein an output of the first AND gate is input to a clear pin of the clock gating enabled register; and
a second AND gate, wherein an output of the second AND gate is input to a chip enable pin of the clock gating enabled register; and

compiling, by a processing device, the circuit design that includes the power switch, the isolation circuit, and the retention circuit.