Patent ID: 11886733
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. A method for testing a memory, applied to a circuit for testing a memory comprising a switch control circuit, the switch control circuit being connected between a discharge end and a negative bias signal end of a Sub Wordline Drive (SWD), the method comprising:
initializing a to-be-tested circuit, so that a stored signal of the to-be-tested circuit and voltage value of a Bit Line (BL) signal end meet a preset test condition, the to-be-tested circuit being a corresponding circuit in a single memory;
inputting a trigger signal through the switch control circuit to trigger potential of a Word Line (WL) signal end in the to-be-tested circuit to meet a preset potential suspension range; and
determining that there is leakage behavior between the WL signal end and the BL signal end in the to-be-tested circuit when it is detected that a present level state of the stored signal is inconsistent with an initial level state within preset time length.