Patent ID: 11876076
Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A memory structure, comprising:
a NAND block comprising a plurality of oxide layers stacked in a vertical direction, the plurality of oxide layers forming a staircase structure at a first edge of the NAND block;
a plurality of vias disposed on the staircase structure of the NAND block, two or more of the plurality of vias terminating along a same plane;
a plurality of first bonding interconnects electrically connected with the plurality of vias;
a plurality of bitlines extending across the NAND block; and
a plurality of second bonding interconnects electrically connected with the bitlines, wherein the bitlines are disposed between the second bonding interconnects and the oxide layers in the vertical direction.