Patent ID: 11960896
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. A semiconductor apparatus comprising:
one or more substrates; and
logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable logic or fixed-functionality hardware logic, the logic coupled to the one or more substrates to:
trigger an idle state in a first command streamer in response to a request to reset a second command streamer that shares graphics hardware with the first command streamer, wherein the first command streamer and the second command streamer are to be executed via a first set of execution units on a render engine and a second set of execution units on a compute engine, and wherein the request to reset is to be from any of various levels in a software stack consisting of a kernel mode operating system, a kernel mode graphics driver, and a graphics scheduler;
determine an event type associated with the request, wherein the event type is to be associated with one or more different types of asynchronous reset events; and
conduct the reset based on the event type.