Patent ID: 11881482
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 18:
19. A semiconductor device, comprising:
a substrate including an active pattern;
an impurity region provided in the active pattern;
a word line disposed in the substrate and crossing the active pattern;
a bit line disposed on the substrate and extending in a direction crossing the word line;
a storage node contact disposed on the substrate and electrically connected to the impurity region;
a landing pad electrically connected to the storage node contact;
a bottom electrode electrically connected to the landing pad;
an upper supporting pattern and a lower supporting pattern provided between the bottom electrode and an adjacent bottom electrode;
a top electrode covering the bottom electrode and the upper supporting pattern; and
a dielectric layer provided between the bottom electrode and the top electrode and between the upper supporting pattern and the top electrode,
wherein the bottom electrode includes a first portion including a seam and a second portion on the first portion,
a top end of the second portion is disposed at a height lower than an upper surface of the upper supporting pattern, and
a portion of a bottom end of the second portion is exposed to the seam.