Patent ID: 11930632
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 13:
14. A manufacturing method of a semiconductor structure, comprising:
providing an initial structure, the initial structure comprising a substrate, as well as active regions and isolation regions which are formed in the substrate, the isolation regions isolating the active regions;
etching the active regions and the isolation regions on the substrate to form gate grooves, the gate grooves being alternately arranged with the isolation regions and the active regions;
forming a gate dielectric layer on an inner surface of each of the gate grooves;
forming a work function layer on the gate dielectric layer and in each of the gate grooves, the work function layer comprising a first portion that is lower than a top surface of the active regions and a second portion that is distributed along a direction substantially perpendicular to a bottom of the gate grooves, a first groove being formed between the first portion of the work function layer and the second portion of the work function layer;
forming a first gate material layer on an inner surface of the work function layer, the first gate material layer filling up the first groove; and
forming a second gate material layer on a top surface of the work function layer, a top surface of the first gate material layer and a surface of the gate dielectric layer, the second gate material layer being lower than the top surface of the active regions;
wherein a height ratio of the second portion of the work function layer to the first gate material layer to the second gate material layer is 3-8:1-1.5:1.