Patent ID: 11960391
Assignee: REBELLIONS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A processing device comprising processing circuitry comprising:
a plurality of processors;
a first memory shared by the plurality of processors; and
a cache comprising a second memory comprising a plurality of memory units, each of the plurality of memory units in the second memory being associated with a respective one of a plurality of request identifiers,
wherein the cache is configured to cause:
receiving, from at least one of the plurality of processors, a memory read request including a request identifier and a memory address,
identifying an allocated memory address identifier for the memory address,
accessing the first memory to read data of the memory address,
obtaining one or more request identifiers which requested data of the memory address from the second memory based on the allocated memory address identifier, and
transmitting the data of the memory address to one or more processors which requested data of the memory address based on the one or more request identifiers,
wherein the cache further comprises:
a third memory including a plurality of memory units, each of the plurality of memory units in the third memory being associated with a respective one of a plurality of memory address identifiers,
wherein obtaining the one or more request identifiers comprises:
accessing a memory unit of the third memory based on the allocated memory address identifier to obtain a head request identifier and a tail request identifier, and
accessing the second memory based on the head request identifier and the tail request identifier to obtain the one or more request identifiers.