Patent ID: 11921632
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. A method, comprising:
storing a plurality of memory pages in a two-level non-uniform memory access (NUMA) memory system, the two-level NUMA memory system to include two memory regions, a first memory region to comprise a byte-addressable persistent memory (PMEM) to store a first set of memory pages, and a second memory region to comprise a byte-addressable dynamic random access memory (DRAM) to store a second set of memory pages, the DRAM having an access speed faster than an access speed of the PMEM;
identifying a first memory page of the plurality of memory pages stored in the PMEM of the two-level NUMA memory system, wherein the first memory page is a first guest memory page for an application executing in a virtual machine (VM) of the processor;
determining whether the first memory page of the plurality of memory pages is a candidate for migration to the DRAM of the two-level NUMA memory system based on a defined migration policy for migrating memory pages, the migration policy based on a frequency of access of the first memory page; and
migrating the first memory page from the PMEM of the two-level NUMA memory system to a target memory page of the DRAM of the two-level NUMA memory system.