Patent ID: 11955180
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 6:
7. The memory of claim 6, further comprising:
a plurality of first access lines; and
a plurality of second access lines;
wherein each first access line of the plurality of first access lines is connected to a control gate of the first memory cell portion of a respective split-gate memory cell of each string of series-connected split-gate memory cells of the first plurality of strings of series-connected split-gate memory cells;
wherein each first access line of the plurality of first access lines is further connected to a control gate of the first memory cell portion of a respective split-gate memory cell of each string of series-connected split-gate memory cells of the second plurality of strings of series-connected split-gate memory cells;
wherein each second access line of the plurality of second access lines is connected to a control gate of the second memory cell portion of a respective split-gate memory cell of each string of series-connected split-gate memory cells of the first plurality of strings of series-connected split-gate memory cells; and
wherein each second access line of the plurality of second access lines is further connected to a control gate of the second memory cell portion of a respective split-gate memory cell of each string of series-connected split-gate memory cells of the second plurality of strings of series-connected split-gate memory cells.