Patent ID: 11860671
Assignee: WINBOND ELECTRONICS CORP.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. A method of redirecting memory addresses, for use in a memory circuit, wherein the memory circuit comprises a memory-control logic and a memory-cell array, and the memory-cell array is divided into a plurality of regions, and the regions comprise at least one damaged region, and the memory-control logic comprises a one-time-programmable (OTP) memory array, and the memory circuit receives an address signal, the method comprising:
programming an available memory-size ratio of the memory-cell array, a region-failure flag corresponding to each region in the memory-cell array, and a redirecting mapping table corresponding to each region in a first array, a second array, and a third array of the OTP memory array;
performing a programming operation on the redirecting mapping table corresponding to each region stored in the OTP memory array according to the available memory-size ratio to direct the redirecting mapping table corresponding to each damaged region to non-repetitive good regions among the regions;
converting the address signal into a first redirected address signal according to the redirecting mapping table corresponding to each region stored in the OTP memory array; and
converting the first redirected address signal into a second redirected address signal according to the available memory-size ratio, and inputting the second redirected address signal into the memory-cell array,
wherein:
the region-failure flag indicates whether the corresponding region is the damaged region, and
the address-redirecting circuit masks one or more of the highest bits in the first redirected address signal according to the available memory-size ratio of the memory-cell array,
the first array is a binary array,
in response to determining the binary array is a first value, a first highest bit of the second redirected address signal is set to a first highest bit of the first redirected address signal,
in response to determining the binary array is a second value, the first highest bit of the second redirected address signal is set to 0,
in response to determining the binary array is the third value, the first highest bit and a second highest bit of the second redirected address signal are set to 0.