Patent ID: 11907580
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus, comprising:
a memory device; and
a controller coupled with the memory device and configured to cause the apparatus to:
identify a read error based at least in part on receiving, from the memory device, first information that is associated with a first read operation of the memory device;
select a trim setting from a plurality of trim settings based at least in part on identifying a data retention condition associated with the first information;
transmit, to the memory device, an indication to initiate a second read operation of the memory device in accordance with the selected trim setting; and
perform a decoding operation based at least in part on receiving, from the memory device, second information that is associated with the second read operation of the memory device.