Patent ID: 11895837
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 17:
18. A semiconductor device comprising:
a lower substrate;
a driving transistor disposed on the lower substrate;
a lower interlayer insulation layer disposed on the lower substrate covering the driving transistor;
an upper substrate disposed on the lower interlayer insulation layer, the upper substrate including a memory cell region and a connection region and the lower interlayer insulation layer being in contact with a bottom surface of the upper substrate;
a plurality of gate electrodes stacked on the upper substrate;
a channel structure disposed in the memory cell region and penetrating the plurality of gate electrodes, the channel structure including a channel layer extending in a vertical direction perpendicular to an upper surface of the upper substrate;
a cell dummy channel structure disposed in the memory cell region and penetrating the plurality of gate electrodes, the cell dummy channel structure including a cell dummy channel layer extending in the vertical direction;
a dummy channel structure disposed in the connection region and penetrating the plurality of gate electrodes, the dummy channel structure including a dummy channel layer extending in the vertical direction;
a first semiconductor layer disposed in the memory cell region and disposed between the upper substrate and a lowermost gate electrode of the plurality of gate electrodes, the first semiconductor layer at least partially surrounding the channel structure and the cell dummy channel structure;
an insulating separation structure disposed in the connection region and between the upper substrate and the lowermost gate electrode and at least partially surrounding the dummy channel structure; and
a second semiconductor layer disposed between the first semiconductor layer and the lowermost gate electrode and disposed between the insulating separation structure and the lowermost gate electrode, the second semiconductor layer at least partially surrounds the channel structure, the cell dummy channel structure, and the dummy channel structure.