Patent ID: 11870603
Assignee: NXP B.V.
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. The circuit arrangement of claim 8, where the dual mode bus termination circuit comprises:
first and second resistors connected in series between the first and second bus wires of the serial bus, where each of the first and second resistors has a first resistance value that matches an impedance of the serial bus when operating in the differential communication mode;
a splitting capacitor connected between a ground reference voltage and a shared node of the first and second resistors; and
a third resistor connected between the first and second bus wires of the serial bus, where the third resistor has a resistance value, when combined with the first and second resistors, that matches an impedance of the serial bus when operating in the single-ended communication mode.