Patent ID: 11954491
Assignee: SIMPLEX MICRO, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 22:
23. The processor of claim 1 further comprising:
a register scoreboard coupled to the time counter to record a write back time of a first destination register referenced by the first instruction of the first thread and a write back time of a second destination register referenced by a second instruction of a second thread;
wherein the instruction issue unit is coupled to the register scoreboard for receiving a third instruction from the first thread, wherein a source register referenced by the third instruction of the first thread is the same as the first destination register that is referenced by the first instruction of the first thread, and the wherein instruction issue unit issues the third instruction of the first thread with a first preset execution time based on the write back time of the first destination register, that is referenced by the first instruction of the first thread;
wherein the instruction issue unit receives a fourth instruction from the second thread, wherein a source register referenced by the fourth instruction of the second thread is the same as the second destination register, that is referenced by the second instruction of the second thread, and the instruction issue unit issues the fourth instruction of the second thread with a second preset execution time based on the write back time of the second destination register, that is referenced by the second instruction of the second thread; and
wherein the execution queue receives the third instruction of the first thread and the fourth instruction of the second thread from the instruction issue unit and dispatches the third instruction to the functional unit for processing by the functional unit at the first preset execution time, and further dispatches the fourth instruction to the functional unit for processing by the functional unit at the second preset execution time.