Patent ID: 11917806
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 5:
6. The method of manufacturing a semiconductor structure according to claim 5, wherein the step of removing a part of the photoresist layer and a part of the etching sacrificial layer, to form multiple second grooves arranged at intervals, and each of the second grooves exposes a top surface of one bit line, comprises:
removing a part of the photoresist layer, such that a retained photoresist layer forms multiple third grooves arranged at intervals, wherein each of the third grooves exposes the top surface of the etching sacrificial layer; and
removing the etching sacrificial layer exposed in each of the third grooves, such that a retained etching sacrificial layer forms the second groove.