Patent ID: 11972132
Assignee: XILINX, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A device, comprising:
a data processing engine array having a plurality of data processing engines organized in a grid having a plurality of rows and a plurality of columns;
wherein each data processing engine includes a core, a memory module including a memory, and a direct memory access engine;
wherein each data processing engine includes a stream switch, wherein the stream switch of each data processing engine is connected to the core and the direct memory access engine in a same data processing engine, and to the stream switch of one or more adjacent data processing engines;
wherein each memory module includes a plurality of memory interfaces including a first memory interface directly coupled to the core in the same data processing engine and one or more second memory interfaces directly coupled to the core of each of the one or more adjacent data processing engines; and
wherein each core coupled to a selected memory interface of the plurality of memory interfaces of a selected memory module is configured to access the memory of the selected memory module via the selected memory interface independently of the stream switch.