Patent ID: 11973023
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 18:
19. A structure, comprising:
a semiconductor die laterally encapsulated by an insulating encapsulant;
a first dielectric layer in direct contact with conductive pillars of the semiconductor die and the insulating encapsulant;
a bottom patterned seed layer disposed on the conductive pillars of the semiconductor die and embedded in the first dielectric layer;
a first conductive via disposed on the bottom patterned seed layer and embedded in the first dielectric layer, wherein sidewalls of the first conductive via are in direct contact with the first dielectric layer, and wherein the first conductive via is located above the conductive pillars of the semiconductor die;
a first patterned seed layer disposed on the first conductive via, wherein the first patterned seed layer, the first conductive via and the bottom patterned seed layer are in contact with the first dielectric layer;
a first redistribution wiring disposed on the first patterned seed layer;
a second dielectric layer disposed over the first dielectric layer and the first redistribution wiring; and
a second conductive via disposed over the first redistribution wiring, the second conductive via being electrically connected to the first redistribution wiring, wherein a first angle between a top surface of the first conductive via and a sidewall of the first conductive via is less than a second angle between a top surface of the second conductive via and a sidewall of the second conductive via.