Patent ID: 11961577
Assignee: NXP USA, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 16:
17. The integrated circuit of claim 16, wherein the ADC under test is characterized as an SDADC, which requires N-bit resolution from the N-bit differential DAC during ADC testing, the memory engine is further configured to, during ADC testing:
access a first address line from the on-chip memory addressed by N−1 upper significant bits of a test DAC input code for the testing of the SDADC, wherein the N−1 upper significant bits is capable of addressing any memory line of the on-chip memory; and
provide a selected pair of calibration codes corresponding to the test DAC input code from the accessed first address line, based on an LSB of the test DAC input code, to calibrate the N-bit differential DAC.