Patent ID: 11862246
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. The memory system according to claim 1, further comprising:
a plurality of first conductive layers stacked on a substrate;
a plurality of second conductive layers respectively stacked between the plurality of first conductive layers;
a pillar extending in a stacking direction of the plurality of first conductive layers and the plurality of second conductive layers and having the plurality of memory cells at intersections with the plurality of first conductive layers and the plurality of second conductive layers;
a first contact plug extending in the stacking direction of the plurality of first conductive layers and the plurality of second conductive layers and connected to the plurality of first conductive layers; and
a second contact plug extending in the stacking direction of the plurality of first conductive layers and the plurality of second conductive layers and connected to the plurality of second conductive layers.