Patent ID: 11901010
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A memory device comprising:
a first string of memory cells in a first sub-block of a block of memory cells, the first sub-block comprising a selected sub-block, wherein the first string of memory cells comprises a first plurality of memory cells coupled to a plurality of word lines; and
a second string of memory cells in a second sub-block of the block of memory cells, the second sub-block comprising an unselected sub-block, wherein the second string of memory cells comprises a second plurality of memory cells coupled to the plurality of word lines coupled to the first string of memory cells, wherein a first subset of the plurality of word lines is configured to receive a first positive voltage signal during a seeding phase of a program operation performed on the selected sub-block, wherein each of the first subset of the plurality of word lines is coupled to a corresponding memory cell of a first subset of the second plurality of memory cells in the second string of memory cells, the first subset of the plurality of word lines comprising a selected word line associated with the program operation, at least one word line adjacent to the selected word line on a drain-side of the selected word line, and at least one word line adjacent to the selected word line on a source-side of the selected word line, and wherein one or more second word lines are configured to receive a second positive voltage signal during the seeding phase of the program operation, wherein the one or more second word lines coupled to one or more of the second plurality of memory cells on a source-side of the first subset of the second plurality of memory cells in the second string of memory cells.