Patent ID: 11860227
Assignee: SYNOPSYS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. The method of claim 10, wherein the combinatorial path is a first combinatorial path spanning a first number of FPGAs, wherein the delay is a first delay, and further comprising:
determining a second delay for a second combinatorial path spanning a second number of FPGAs, wherein the second number of FPGAs is less than the first number of FPGAs; and
determining, responsive to the second delay being greater than the first delay, that the second combinatorial path is a critical path, wherein the compiler allocates a first time-division multiplexing (TDM) ratio to the first combinatorial path and allocates a second TDM ratio to the second combinatorial path, the second TDM ratio greater than the first TDM ratio.