Patent ID: 11923868
Assignee: MICRON TECHNOLOGY, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 12:
13. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to:
receive a codeword from a memory device, the codeword including a plurality of bits;
flip, by a bit flipping decoder using a first plurality of bit flipping rules, one or more of the plurality of bits in the codeword in each of a plurality of error correction iterations responsive to the one or more of the plurality of bits in the codeword satisfying the first plurality of bit flipping rules;
detect a stall condition in the plurality of error correction iterations;
select a second plurality of bit flipping rules in response to detecting the stall condition; and
flip, by the bit flipping decoder using the second plurality of bit flipping rules, one or more of the plurality of bits in the codeword in each of one or more subsequent error correction iterations responsive to the one or more of the plurality of bits in the codeword satisfying the first plurality of bit flipping rules, wherein the second plurality of bit flipping rules differs from the first plurality of bit flipping rules in two or more of:
use of channel information,
an order the bit flipping decoder evaluates the plurality of bits of the codeword for flipping, and
a bit flipping threshold, wherein the bit flipping threshold is compared against an energy function of each of the plurality of bits of the codeword in determining which bits to flip.