Patent ID: 11923207
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A method comprising:
encapsulating an integrated circuit die and a through via adjacent the integrated circuit die with a molding compound; and
forming a redistribution structure over the integrated circuit die, the molding compound, and the through via, wherein forming the redistribution structure comprises:
depositing a dielectric layer over the integrated circuit die, the through via, and the molding compound, the dielectric layer being made of a photo-sensitive material;
patterning the dielectric layer to form a plurality of openings extending through the dielectric layer, and wherein patterning the dielectric layer comprises positioning a photomask over the dielectric layer and exposing the dielectric layer to an energy source patterned through the photomask, wherein an entire top surface of the dielectric layer is simultaneously exposed to the energy source patterned through the photomask; and
depositing a conductive feature in the plurality of openings, the conductive feature electrically connecting the integrated circuit die to the through via.