Patent ID: 11910589
Assignee: ZENO SEMICONDUCTOR, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 10:
11. An integrated circuit comprising:
a semiconductor memory array comprising a plurality of semiconductor memory cells, wherein each of said semiconductor memory cells comprises:
a memory transistor comprising:
a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states;
insulating regions adjacent to said floating body region;
a buried layer region located below said floating body region and said insulating regions and spaced from said insulating regions so as not to contact said insulating regions;
wherein said floating body region is configured to be bounded by said insulating regions and a depletion region formed as a result of an application of a back bias to said buried layer region;
wherein said buried layer region generates impact ionization when said memory cell is in one of said first and second states, and wherein said back-bias region does not generate impact ionization when the memory cell is in the other of said first and second states;

an access device comprising a body region, wherein said access device is connected in series to said memory transistor, and wherein said body region is configured to be isolated from said floating body region by said depletion region;
wherein said buried layer region is located underneath at least two of said memory cells; and

a control circuit configured to apply said back bias to said buried layer region.