Patent ID: 11901347
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A microelectronic package comprising:
a memory die communicatively coupled with a package substrate of the microelectronic package, wherein the memory die comprises:
a first memory cell at a first n-type metal-oxide-semiconductor (NMOS) layer of the memory die, wherein the first memory cell includes a first dynamic random-access memory (DRAM) cell with an n-type metal-oxide-semiconductor field-effect transistor (MOSFET);
a second memory cell at a second NMOS layer of the memory die, wherein the second memory cell includes a second DRAM cell with an n-type MOSFET;
a complimentary metal-oxide semiconductor (CMOS) layer comprising control logic for the memory die; and
a conductive element; and

a system-on-chip (SOC) communicatively coupled with the package substrate of the microelectronic package by the conductive element in the memory die.