Patent ID: 11955157
Assignee: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A PUF apparatus comprising:
a PUF cell array in which a plurality of PUF cells are arranged each including a FeFET pair whose gates are commonly connected to a corresponding word line among a plurality of word lines, and whose drains and sources are respectively connected to a corresponding bit line pair and a corresponding source line pair among a plurality of bit line pairs and a plurality of source line pairs running in a direction crossing the plurality of word lines; and
a read-write-back block which is activated according to a read enable signal, and senses and amplifies a voltage difference occurring in a corresponding bit line pair among the plurality of bit line pairs according to the difference in driving strength due to a deviation in a manufacturing process of the FeFET pair included in a PUF cell selected by a selected word line among the plurality of word lines,
wherein the read-write-back block includes:
an amplifying block having a plurality of first sense amplifiers which are disposed between the plurality of bit line pairs and a voltage line, respectively, and which cross-sense the corresponding bit line pair and amplify the voltage difference between the corresponding bit line pair; and
a write-back block having a plurality of second sense amplifiers which are disposed between the plurality of source line pairs and a ground line, respectively, and which are activated according to the read enable signal, cross-sense the corresponding bit line pair and generate a voltage difference in the corresponding source line pair.