Patent ID: 11922992
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. The memory device of claim 7, wherein the sub word line driving signal encoder comprises:
a plurality of third AND circuits configured to commonly receive the odd signal, receive the plurality of second sub word line driving signals in the third order, and output an AND operation result on the odd signal and the plurality of second sub word line driving signals in the third order;
a plurality of fourth AND circuits configured to commonly receive the even signal, receive the plurality of second sub word line driving signals in the fourth order, and output an AND operation result on the even signal and the plurality of second sub word line driving signals in the fourth order;
a plurality of second NOR circuits each configured to receive one AND operation result among the plurality of third AND circuits and one AND operation result among the plurality of fourth AND circuits and perform a NOR operation on the received AND operation results; and
a plurality of second inverters configured to perform an inverting operation on output values of the plurality of second NOR circuits.