Patent ID: 11923041
Assignee: TSMC CHINA COMPANY, LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A device, comprising:
a memory array having a plurality of bit cells arranged in rows and columns;
a plurality of bit line pairs, each bit line pair connected to a respective column of bit cells;
a plurality of word lines, each word line connected to a respective row of bit cells;
a modulation circuit coupled with at least one bit line pair;
a word line decoder coupled with the plurality of word lines; and
a control signal generator coupled with the modulation circuit and the word line decoder, wherein the control signal generator is configured to produce a first control signal to the word line decoder for generating word line signals, and the control signal generator is configured to produce a second control signal to the modulation circuit in reference with a tracking wiring, wherein a high-level duration of the second control signal encloses high-level durations of the word line signals.