Patent ID: 11956970
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 12:
13. An apparatus, comprising:
a first tile of a memory array associated with a first level above a substrate, the first tile comprising:
a plurality of first memory cells;
a plurality of first digit lines each aligned along a first direction; and
a plurality of first word lines each aligned along a second direction and each operable to activate a plurality of first transistors of the first tile to couple a respective storage element, of each first memory cell of a respective row of first memory cells, with each first digit line of the plurality of first digit lines;

a second tile of the memory array associated with a second level above the substrate, the second tile comprising:
a plurality of second memory cells;
a plurality of second digit lines each aligned along the first direction; and
a plurality of second word lines each aligned along the second direction and each operable to activate a plurality of second transistors of the second tile to couple a respective storage element of each second memory cell of a respective row of second memory cells with each second digit line of the plurality of second digit lines;

a first activation line of the first level aligned along the second direction and operable to activate a plurality of third transistors of the first level, each third transistor of the plurality of third transistors operable to couple a respective first digit line of a set of first digit lines of the plurality of first digit lines with a first plate node; and
a second activation line of the second level aligned along the second direction and operable to activate a plurality of fourth transistors of the second level, each fourth transistor of the plurality of fourth transistors operable to couple a respective second digit line of a set of second digit lines of the plurality of second digit lines with a second plate node.