Patent ID: 11893942
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 18:
19. A method of driving a gate on array unit circuit in a cycle time, wherein transistors of the gate on array unit circuit are N-type transistors, the gate on array unit circuit is configured to receive a first voltage signal set at a high or turn-on voltage level for the N-type transistor and a second voltage signal set at a low or turn-off voltage level for the N-type transistor, the method comprising:
providing a first clock signal and an input signal at a high voltage level to an input sub-circuit to start a first period of the cycle time while keeping a second clock signal to a first output sub-circuit and a third clock signal to a pull-up sub-circuit at a low voltage level, thereby setting a first node to the high voltage level, a second node to the low voltage level, and a third node to the low voltage level, and outputting a first output signal at the low voltage level and a second output signal at the low voltage level;
providing a second clock signal at the high voltage level to start a second period of the cycle time while changing the first clock signal and the input signal to the low voltage level and keeping the third clock signal at the low voltage level, thereby keeping the first node at the high voltage level, the second node at the low voltage level, and the third node at the low voltage level, and outputting the first output signal at the high voltage level and the second output signal at the low voltage level;
providing a third clock signal at the high voltage level to start a third period of the cycle time while keeping the first clock signal, the second clock signal, and the input signal at the low voltage level, thereby setting the second node to the high voltage level, the third node to the high voltage level and changing the first node to the low voltage level, and outputting the first output signal at the low voltage level and the second output signal at the high voltage level;
providing the first clock signal again at the high voltage level to start a fourth period of the cycle time while keeping the second clock signal, the input signal, and the third clock signal at the low voltage level, thereby keeping the first node at the low voltage level, the second node and the third node at the high voltage level, and outputting the first output signal at the low voltage level and the second output signal at the high voltage level;
providing the second clock signal again at the high voltage level to start a fifth period of the cycle time while changing the first clock signal to the low voltage level and keeping the third clock signal and the input signal to the low voltage level, thereby keeping the first node at the low voltage level, the second node and the third node at the high voltage level, and outputting the first output signal at the low voltage level and the second output signal at the high voltage level; and
providing the third clock signal again at the high voltage level to start a sixth period of the cycle time while changing the second clock signal to the low voltage level and keeping the first clock signal and the input signal at the low voltage level, thereby keeping the first node at the low voltage level, the second node and the third node at the high voltage level, and outputting the first output signal at the low voltage level and the second output signal at the high voltage level;
wherein the gate on array unit circuit further comprises a second output sub-circuit
the second output sub-circuit comprises a thirteenth transistor, a fourteenth transistor, a third capacitor, and a fourth capacitor;
wherein the method further comprises:
coupling the thirteenth transistor, the fourteenth transistor and the third capacitor are respectively to a second output terminal for outputting the second output signal;
providing the first voltage signal set at the turn-on voltage level to a first terminal of the thirteenth transistor;
coupling a gate terminal of the thirteenth transistor to the third node;
coupling a second terminal of the thirteenth transistor to the second output terminal;
providing the second voltage signal set at the turn-off voltage level to a first terminal of the fourteenth transistor;
coupling a gate terminal of the fourteenth transistor to the first node;
coupling a second terminal of the fourteenth transistor to the second output terminal;
coupling a first terminal of the third capacitor to the third node;
coupling a second terminal of the third capacitor to the second output terminal;
coupling a first terminal of the fourth capacitor to the first node; and
coupling a second terminal of the fourth capacitor to the first terminal of the fourteenth transistor.