Patent ID: 11922108
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 3:
4. The method of claim 1, wherein the generating the layout design of the memory cell array further comprises:
generating a fourth set of conductive feature layout patterns extending in the first direction, the fourth set of conductive feature layout patterns being located on a third layout level and a fourth layout level different from the first layout level, the second layout level and the third layout level, and the fourth set of conductive feature layout patterns corresponding to fabricating another portion of the source line; and
generating a set of via layout patterns, the set of via layout patterns being located between the third layout level and the fourth layout level, and the set of via layout patterns corresponding to fabricating vias coupled between the source line and the another portion of the source line.