Patent ID: 11941396
Assignee: SHANGHAI BIREN TECHNOLOGY CO., LTD
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A current variation slope (DIDT) control method for a multi-core processor, wherein the multi-core processor comprises a plurality of arithmetic logic units (ALUs) and each of the ALUs is associated with a DIDT control module, and the method comprises, at each of the DIDT control modules:
obtaining a local operation load of a local ALU in each clock cycle;
obtaining a global operation load of the plurality of ALUs in each cycle period;
determining an operation load index of the local ALU based on local historical load information and a local historical load weight set of the local ALU and global historical load information and a global historical load weight set of the plurality of ALUs, wherein the global historical load information comprises a first number of the global operation loads, the local historical load information comprises a second number of the local operation loads; and
adjusting an operation load of the local ALU based on the operation load index of the local ALU and a predetermined load threshold to control a DIDT of the local ALU.