Patent ID: 11893271
Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. The computing-in-memory circuit according to claim 8, wherein the first amplifier circuit comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a toggle switch, and an energy storage unit;
a source of the first PMOS transistor serves as a first input terminal of the first amplifier circuit, and a gate of the first PMOS transistor receives a bias voltage, and a drain of the first PMOS transistor is connected to a gate of the second PMOS transistor, a source of the second PMOS transistor and a source of the third PMOS transistor;
a drain of the second PMOS transistor is connected to a drain of the third PMOS transistor;
the source of the third PMOS transistor is connected to a drain of the fourth PMOS transistor;
a gate of the fourth PMOS transistor is connected to one end of the toggle switch and a gate of the sixth PMOS transistor, and a source of the fourth PMOS transistor is connected to a source of the fifth PMOS transistor and a source of the sixth PMOS transistor;
a gate of the fifth PMOS transistor is connected to another end of the toggle switch and the energy storage unit, and a drain of the fifth PMOS transistor and a drain of the sixth PMOS transistor are connected to the current node; and
a control end of the toggle switch receives a switching control signal.