Patent ID: 11861284
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A system, comprising:
a processing device; and
a memory operably connected to the processing device and storing instructions, that when executed by the processing device, cause operations to be performed, the operations comprising:
determining a placement of components in an integrated circuit that includes all of Manhattan-routed conductors, diagonal-routed conductors, and at least one conductor that is neither Manhattan-routed nor diagonal-routed;
determining a tree for each respective net in the integrated circuit based on the placement;
determining a number of conductor layers to be used for Manhattan routing of conductors, the determining comprising calculating a first ratio for Manhattan edges in the trees;
determining a number of conductor layers to be used for diagonal routing of conductors, the determining comprising calculating a second ratio for diagonal edges in the trees;
selecting a conductor scheme for the integrated circuit based on the first and the second ratios; and
generating a layout of the integrated circuit.