Patent ID: 11961565
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. A method comprising:
causing, by control logic of a memory device comprising an array of memory cells configured as multi-level cell memory, first data to be programmed to a plurality of memory cells of the array of memory cells, the first data comprising an erase distribution programmed below an erase Vt level and multiple first voltage distributions programmed relative to multiple first Vt levels; and
causing, by the control logic without erasing the plurality of memory cells, second data to be programmed to the plurality of memory cells, the second data comprising multiple second voltage distributions programmed relative to multiple second Vt levels, the multiple second Vt levels being higher than a highest Vt level of the multiple first Vt levels.