Patent ID: 11915655
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. A shift register unit, comprising: a first transistor to an eighteenth transistor, and a first capacitor to a fourth capacitor,
wherein a gate electrode of the first transistor is coupled to a first enable signal terminal to receive a first enable signal, a first electrode of the first transistor is coupled to a first voltage terminal to receive a first voltage, and a second electrode of the first transistor is coupled to an output terminal;
a gate electrode of a second transistor is coupled to a second enable signal terminal to receive a second enable signal, a first electrode of the second transistor is coupled to a second node, and a second electrode of the second transistor is coupled to a second voltage terminal to receive a second voltage;
a gate electrode of a third transistor is coupled to a first node, a first electrode of the third transistor is coupled to a third voltage terminal to receive a third voltage, and a second electrode of the third transistor is coupled to the second node;
a gate electrode of a fourth transistor is coupled to the first node, a first electrode of the fourth transistor is coupled to a fourth voltage terminal to receive a fourth voltage, and a second electrode of the fourth transistor is coupled to a first electrode of a fifth transistor;
a gate electrode of the fifth transistor is coupled to the first node, and a second electrode of the fifth transistor is coupled to the output terminal;
a gate electrode of a sixth transistor is coupled to a fourth clock signal terminal to receive a fourth clock signal, a first electrode of the sixth transistor is coupled to the second node, and a second electrode of the sixth transistor is coupled to a fifth voltage terminal to receive a fifth voltage;
a gate electrode of a seventh transistor is coupled to the output terminal, a first electrode of the seventh transistor is coupled to a sixth voltage terminal to receive a sixth voltage, and a second electrode of the seventh transistor is coupled to the second node;
a gate electrode of an eighth transistor is coupled to the second node, a first electrode of the eighth transistor is coupled to the output terminal, and a second electrode of the eighth transistor is coupled to a seventh voltage terminal to receive a seventh voltage;
a gate electrode of a ninth transistor is coupled to the output terminal, a first electrode of the ninth transistor is coupled to the first electrode of the fifth transistor, and a second electrode of the ninth transistor is coupled to an eighth voltage terminal to receive an eighth voltage;
a first electrode of the first capacitor is coupled to the output terminal, and a second electrode of the first capacitor is coupled to the second node;
a gate electrode of a tenth transistor is coupled to an input terminal to receive an input signal, a first electrode of the tenth transistor is coupled to a second electrode of an eleventh transistor, and a second electrode of the tenth transistor is coupled to a ninth voltage terminal to receive a ninth voltage;
a gate electrode of the eleventh transistor is coupled to a first clock signal terminal to receive a first clock signal, and a first electrode of the eleventh transistor is coupled to a third node;
a gate electrode of a twelfth transistor is coupled to the input terminal to receive the input signal, a first electrode of the twelfth transistor is coupled to a tenth voltage terminal to receive a tenth voltage, and a second electrode of the twelfth transistor is coupled to a fourth node;
a gate electrode of a thirteenth transistor is coupled to a first electrode of a fourteenth transistor, a first electrode of the thirteenth transistor is coupled to an eleventh voltage terminal to receive an eleventh voltage, and a second electrode of the thirteenth transistor is coupled to the fourth node;
a gate electrode of the fourteenth transistor is coupled to a twelfth voltage terminal to receive a twelfth voltage, and a second electrode of the fourteenth transistor is coupled to the third node;
a gate electrode of a fifteenth transistor is coupled to the third node, a first electrode of the fifteenth transistor is coupled to the first node, and a second electrode of the fifteenth transistor is coupled to a second clock signal terminal to receive a second clock signal;
a first electrode of a second capacitor is coupled to the first node, and a second electrode of the second capacitor is coupled to the third node;
a first electrode of a third capacitor is coupled to the third node, and a second electrode of the third capacitor is coupled to a thirteenth voltage terminal to receive a thirteenth voltage;
a gate electrode of a sixteenth transistor is coupled to a third clock signal terminal to receive a third clock signal, a first electrode of the sixteenth transistor is coupled to a fourteenth voltage terminal to receive a fourteenth voltage, and a second electrode of the sixteenth transistor is coupled to a gate electrode of a seventeenth transistor;
a first electrode of the seventeenth transistor is coupled to a fifteenth voltage terminal to receive a fifteenth voltage, and a second electrode of the seventeenth transistor is coupled to the gate electrode of the thirteenth transistor;
a gate electrode of the eighteenth transistor is coupled to the fourth node, a first electrode of the eighteenth transistor is coupled to a sixteenth voltage terminal to receive a sixteenth voltage, and a second electrode of the eighteenth transistor is coupled to the first node; and
a first electrode of the fourth capacitor is coupled to the gate electrode of the seventeenth transistor, and a second electrode of the fourth capacitor is coupled to the first electrode of the seventeenth transistor.