Patent ID: 11901297
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of manufacturing a semiconductor memory device, the method comprising:
preparing a substrate including a cell area and a peripheral area;
forming a plurality of lower electrodes on the cell area of the substrate;
forming a capacitor dielectric layer covering the plurality of lower electrodes;
forming an upper electrode, wherein the forming the upper electrode includes forming a first upper electrode layer covering the capacitor dielectric layer and including a semiconductor material, and forming a second upper electrode layer covering the first upper electrode layer and including a metallic material;
forming a filling insulation layer on the second upper electrode layer, the filling insulation layer having a first wiring contact hole;
forming a first wiring contact plug filling the first wiring contact hole, the first wiring contact plug electrically connecting to the upper electrode, and
forming a plurality of wiring lines on the filling insulation layer, at least one of the plurality of wiring lines electrically connecting to the first wiring contact plug.