Patent ID: 11916074
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. A dual transmission gate, comprising:
a first pair of transistors including a first transistor that is connected to a first region situated along a first interconnection layer of a semiconductor stack along a first row from among a plurality of rows of an electronic device design real estate and a second transistor that is connected to a second region situated along the first interconnection layer along a second row from among the plurality of rows;
a third region, situated along the first interconnection layer along a third row from among the plurality of rows of the electronic device design real estate, that corresponds to a first terminal of the dual transmission gate and is connected to the first transistor and the second transistor;
a second pair of transistors including a third transistor from among the second pair of transistors that is connected to the first region and a fourth transistor from among the second pair of transistors that is connected to the second region;
a fourth region, situated along the first interconnection layer along a fourth row from among the plurality of rows of the electronic device design real estate, that corresponds to a second terminal of the dual transmission gate and is connected to the third transistor and the fourth transistor; and
a fifth region, situated along a second interconnection layer of the semiconductor stack along a first column from among a plurality of columns of the electronic device design real estate, that is connected to the first pair of transistors and the second pair of transistors.