Patent ID: 11955170
Assignee: UNTETHER AI CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. The static random-access memory of claim 3, wherein a voltage Vddr is applied to one of the first bitline or second bitline during data reading wherein Vddr is equal to or less than the power supply voltage Vdd, and wherein the voltage Vddr is driven by cross-coupled first and second PMOS transistors and a third PMOS transistor,
wherein a source of the first cross-coupled PMOS transistor is connected to the voltage Vddr, a gate of the first cross-coupled PMOS transistor is configured to receive a cross-coupled enable PMOS signal (ΦA), and a drain of the first cross-coupled PMOS transistor is connected to respective sources of the second cross-coupled PMOS transistor and the third PMOS transistor,
wherein a drain of the second cross-coupled PMOS transistor is connected to the first bitline and a gate of the second cross-coupled PMOS transistor is connected to the second bitline,
wherein a drain of the third PMOS transistor is connected to the second bitline and a gate of the third PMOS transistor is connected to the first bitline,
wherein the cross-coupled enable PMOS signal (CP_en) is applied no earlier than the second step,
wherein a first source of the first NMOS transistor is connected to a Vss, a first gate of the first NMOS transistor is configured to receive a cross-coupled enable NMOS signal (CN_en), and a first drain of the first NMOS transistor is connected to respective sources of the second NMOS transistor and the third NMOS transistor,
wherein a second drain of the second NMOS transistor is connected to the first bitline and a second gate of the second NMOS transistor is connected to the second bitline,
wherein a third drain of the third NMOS transistor is connected to the second bitline and a third gate of the third NMOS transistor is connected to the first bitline, and
CN_en is applied after CP_en is applied.