Patent ID: 11941404
Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. The processor of claim 7, wherein
when the multiple sets are called a first plurality of sets, and
the one direction is called a first shift direction,
a second plurality of sets are stored in a fifth register,
each of the second plurality of sets includes the first value and the second value,
the second plurality of sets is arranged in line, and
the shift processing includes the shifting, by one set, the second plurality of sets in a second shift direction and moving a second set, located at one end in the second shift direction, out of the second plurality of sets to a specified area in the third register, the specified area being adjacent to a first set, located at one end in a direction opposite from the first shift direction, out of the first plurality of sets.