Patent ID: 11934313
Assignee: APPLE INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. A system, comprising:
a plurality of processor cores;
a plurality of graphics processing units;
a plurality of peripheral devices distinct from the processor cores and the graphics processing units;
a plurality of memory controller circuits configured to interface with a system memory; and
an interconnect fabric configured to provide communication between the memory controller circuits and the processor cores, the graphics processing units, and the peripheral devices;
wherein the processor cores, the graphics processing units, the peripheral devices and the memory controller circuits are configured to communicate via a unified memory architecture in which a given page within a unified address space defined by the unified memory architecture is distributed among the plurality of memory controller circuits; and
wherein the processor cores, the graphics processing units, the peripheral devices, the memory controller circuits, and the interconnect fabric are included in a system on a chip (SOC) integrated onto one or more co-packaged semiconductor dies.