Patent ID: 11868275
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 8:
9. A processor comprising:
a register file configured to store ciphertext data;
an instruction fetch and decode unit configured to fetch and decode instructions; and
a functional unit configured to process the stored ciphertext data, wherein the functional unit further includes:
a decryption module configured to decrypt ciphertext data from the register file to receive cleartext data using an encryption key stored within the functional unit;
a local buffer configured to store the cleartext data, wherein the decryption module does not decrypt the ciphertext data into the cleartext data when a determination is made that the cleartext data is already located in the local buffer;
an arithmetic logical unit configured to generate cleartext computation results using the cleartext data; and
an encryption module configured to encrypt the cleartext computation results to generate ciphertext computation results for storage back into the register file.