Patent ID: 11899532
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus, comprising:
a memory device comprising a plurality of memory cells, and
one or more controllers coupled with the memory device and configured to cause the apparatus to:
receive an indication of a timeout duration for a boot sequence of a host system;
determine a quantity of bits configured to be output by respective memory cells of a set of memory cells of the plurality of memory cells;
select, based at least in part on the timeout duration, the set of memory cells based at least in part on the quantity of bits being less than a data level threshold;
store information for the boot sequence in the set of memory cells based at least in part on selecting the set of memory cells; and
access the information for the boot sequence that is stored in the set of memory cells based at least in part on an initialization of the boot sequence.