Patent ID: 11954340
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. The nonvolatile memory of claim 1, wherein the chip address initialization circuit includes:
a timing control circuit configured to output a clock signal, a data output enable signal, and the next enable signal;
a chip address register configured to receive the clock signal; and
a next chip address generator configured to receive the data output enable signal,
wherein the timing control circuit receives a chip address initialization command through a plurality of data lines connected to the plurality of input/output pads and generates the clock signal and the data output enable signal, which are based on the current enable signal or a write enable signal, in response to the chip address initialization command,
wherein the chip address register stores the current chip address in response to the clock signal and outputs the current chip address to the next chip address generator, and
wherein the next chip address generator generates the next chip address by using the current chip address from the chip address register and outputs the next chip address through the plurality of input/output pads in response to the data output enable signal.