Patent ID: 11963352
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. The semiconductor structure of claim 11, wherein:
the three-dimensional NAND memory array comprises a three-dimensional NAND array of memory elements that includes portions of the memory films that are located adjacent to a respective one of vertical semiconductor channels;
the metal interconnect structures comprise:
lower-level metal interconnect structures underlying the alternating stack;
upper-level metal interconnect structures overlying the alternating stack; and
memory-level connection via structures vertically extending between a horizontal plane including a top surface of the alternating stack and a horizontal plane including a bottom surface of the alternating stack and connecting the lower-level metal interconnect structures to the upper-level metal interconnect structures;

a subset of the top electrodes of the at least one set of vertical field effect transistors is electrically connected to a respective one of the bit lines;
the at least one set of vertical field effect transistors comprises:
a first set of vertical field effect transistors including a respective bottom electrode that is electrically connected to a respective sense amplifier circuit located on the semiconductor substrate; and
a second set of vertical field effect transistors including a respective bottom electrode that is electrically connected to a bit line bias circuit located on the semiconductor substrate; and

each of the upper-electrode-connection metal lines is electrically connected to a respective set of a top electrode within the first set of vertical field effect transistors and a top electrode within the second set of vertical field effect transistors.