Patent ID: 11960127
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A semiconductor package, comprising:
a semiconductor die;
a device layer stacked over the semiconductor die, the device layer comprising a base layer, a mode coupler located at an edge of the semiconductor package and a waveguide connected to the mode coupler;
an insulator layer stacked over the device layer, the insulator layer comprising a first dielectric material;
a buffer layer stacked over the insulator layer, the buffer layer comprising a second dielectric material;
bonding vias extending through the base layer of the device layer;
connective terminals, disposed on the buffer layer and reaching the insulator layer through contact openings of the buffer layer, wherein the bonding vias electrically connect the semiconductor die to the connective terminals, the bonding vias are spaced apart from the insulator layer by the connective terminals, and ends of the bonding vias protrude from a surface of the device layer; and
an etch stop layer disposed in contact with the insulator layer on one side, and spaced apart from the waveguide by the base layer, wherein the etch stop layer comprises a material conferring etching selectivity to the etch stop layer with respect to the first dielectric material, and portions of the etch stop layer surrounding the bonding vias are in contact with the connective terminals.