Patent ID: 11962327
Assignee: MICRON TECHNOLOGY, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 0:
1. A memory system comprising:
a plurality of memory components; and
a controller in communication with the plurality of memory components and configured to:
perform error correction code (ECC) decoding on a received word read from the plurality of memory components
comprising:
(i) performing a single decoding attempt to detect one or more random errors in a portion of the received word, the portion corresponding to one memory component within the plurality of memory components, and correct the detected random errors; and
(ii) when the correcting of the detected random errors fails, iteratively performing decoding attempts with each attempt marking symbols in the remaining portions of the received word that correspond respectively to remaining memory components of the plurality of memory components, as erasures, and using counter logic to obtain erasure location information corresponding to the erasures.