Patent ID: 11880687
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. A system comprising:
an interconnection network;
a packet network;
a synchronous network;
a processor coupled to the interconnection network, the processor configured to execute a fiber create instruction and to generate and transmit a plurality of first work descriptor data packets on the interconnection network;
a network interface circuit coupled to the interconnection network, the network interface circuit configured to receive one or more first work descriptor data packets of the plurality of first work descriptor data packets;
a plurality of configurable circuits arranged in an array, each configurable circuit of the plurality of configurable circuits coupled to the packet network and to the synchronous network, each configurable circuit of the plurality of configurable circuits comprising:
a configurable computation circuit; and
a configuration memory coupled to the configurable computation circuit,
the configuration memory comprising:
a first instruction memory configured to store a first plurality of configuration instructions to configure the configurable computation circuit; and
a second instruction memory configured to store a second plurality of configuration instructions or instruction indices, the second plurality of configuration instructions or instruction indices comprising instructions or instruction indices for selection of a configuration instruction of the first plurality of configuration instructions from the first instruction memory and for selection of a network input from the synchronous network for receipt of the configuration instruction or a configuration instruction index from another configurable circuit of the plurality of configurable circuits of the array;, and
a dispatch interface circuit coupled to the network interface circuit and coupled through the packet network to the plurality of configurable circuits of the array, the dispatch interface circuit configured, in response to receiving the one or more first work descriptor data packets from the network interface circuit, to generate and transmit on the packet network one or more data and control packets to one or more configurable circuits of the plurality of configurable circuits to configure the one or more configurable circuits for execution of a corresponding plurality of execution threads.