Patent ID: 11870504
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Telecommunications (Electrical engineering)
Classification: CPC G  H | IPC H

Claim 8:
9. The test system of claim 8, wherein the plurality of first I/O circuits are configured to sample each of the first NRZ signal and the second NRZ signal based on a first internal clock signal having a first frequency to generate a most significant bit and a least significant bit, and
the translation circuit comprises:
an aligner configured to generate an aligned signal from the most significant bit and the least significant bit based on the first internal clock signal;
a data selector configured to generate a selected signal from the aligned signal based on a second internal clock signal having a second frequency; and
a multiplexer configured to multiplex the selected signal based on a third internal clock signal having a third frequency which is higher than each of the first frequency and the second frequency.