Patent ID: 11955475
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 16:
17. A method of manufacturing a resistor comprising:
forming a stack including a plurality of alternately stacked sacrificial layers and a plurality of channel layers on a substrate, the substrate including an active region in an N well region;
forming a first trench in an upper portion of the substrate and forming a device isolation layer in the first trench;
forming a second trench in the upper portion of the substrate and forming a buried insulating layer in the second trench, the buried insulating layer dividing the active region into a first active region and a second active region extending in a first horizontal direction;
forming dummy gate structures extending in a second horizontal direction crossing the first horizontal direction on the stack, each of the dummy gate structures including dummy gate electrodes and gate spacers on side surfaces of the dummy gate electrodes;
forming inner spacers on lower surfaces of the plurality of channel layers;
forming a first doped region and second doped region each disposed on side surfaces of the dummy gate structures and on the first active region and the second active region;
removing the dummy gate electrodes and forming gate electrodes in a space where the dummy gate electrodes are removed; and
forming a plurality of contact plugs in contact with upper surfaces of the first doped region and the second doped region,
wherein the first doped region and the second doped region is in contact with the N well region and including n impurities.