Patent ID: 11966727
Assignee: LZLABS GMBH
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A non-transitory computer readable medium configured to store instructions, the instructions when executed by one or more processors cause the one or more processors to execute a first program compiled for a source architecture on a machine having a target architecture different from the source architecture by performing steps comprising:
receiving by a processor said first program comprising first executable code compiled to execute on a source architecture;
decompiling by a decompiler module executing on the processor a load module into intermediate computer code formatted according to an intermediate code format;
identifying by the decompiler module a set of addresses that are exposed for external reference by a second program compiled to execute on the source architecture;
storing in a computer memory an index of said addresses that are exposed for external reference, wherein the index comprises values that correspond to a range of invalid addresses in the target architecture, wherein the identifying by the decompiler includes:
in a first pass by the decompiler module, examining syntax of instructions in machine code of said first program;
determining from the syntax of the instructions that a set of symbols are addresses; and
adding the set of symbols to the index;

recompiling by a compiler module, the intermediate code into target executable code configured for the target architecture, wherein the compiler module incorporates the index of said addresses into the target executable code; and
executing said target executable code on a processor having said different target architecture, wherein said executing generates at least one invalid address and wherein an exception handler translates said invalid address into a valid address using the incorporated index.