Patent ID: 11948634
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. A memory device, comprising:
a memory array comprising a plurality of memory elements organized into word lines and bit lines;
a snap detection circuit coupled to the word lines of the memory array;
a first circuit that when in operation selectively outputs a voltage to a first word line of the word lines in conjunction with a selection operation to select a target memory cell of the first word line as a first memory element of the plurality of memory elements;
a second circuit that when in operation selectively outputs a second voltage to the first word line of the memory array in conjunction with the selection operation to select the target memory cell of the first word line as the first memory element of the plurality of memory elements; and
a control circuit comprising a first input coupled to the snap detection circuit and an output coupled to the first circuit and the second circuit, wherein the control circuit comprises a second input that when in operation receives location information of a location of the target memory cell with respect to a row decoder coupled to the first word line.