Patent ID: 11966737
Assignee: NVIDIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. A method performed by a multiprocessor to execute an operation on a communicatively coupled coprocessor, the method comprising:
establishing a connection to the coprocessor, wherein the establishing causes the coprocessor to reserve resources on the coprocessor for the operation;
issuing a macro initiation instruction, wherein the macro initiation instruction causes disabling of interrupts;
following the macro initiation instruction, issuing a sequence of write instructions to write input operands for the operation into coprocessor-accessible storage locations in said reserved resources;
after issuing the sequence of write instructions, issuing an operation instruction to cause the coprocessor to execute the operation using said input data;
issuing a plurality of read instructions to read result data of the operation from the coprocessor-accessible storage locations to multiprocessor-accessible storage locations; and
closing the connection,
wherein the macro initiation instruction provides for execution of a predetermined number of instructions without intervening preemption and the predetermined number is determined based on an operand of the macro initiation instruction.