Patent ID: 11923864
Assignee: SHAOXING YUANFANG SEMICONDUCTOR CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 5:
6. The PLL of claim 2, wherein said second oscillator is implemented as a third PLL with a third bandwidth higher in magnitude compared to said second bandwidth,
wherein said second PLL comprises a second low-pass-filter with a second passband to generate a second filtered error signal by filtering said second error signal,
wherein said second oscillator generates said output clock based on said second filtered error signal,
wherein said second filtered error signal is provided as an input signal to said third PLL and said third PLL provides said output clock,
wherein to switch to said different frequency of said output clock, said control unit changes a configuration of each of said first PLL, said second PLL and said third PLL substantially simultaneously to generate said output clock at said different frequency.