Patent ID: 11967373
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 10:
11. A method of operating memory, comprising:
providing a first negative configuration pre-decoded address signal and a second negative configuration pre-decoded address signal to a NAND logic gate of pre-decoder circuitry, wherein the first negative configuration pre-decoded address signal and the second negative configuration pre-decoded address signal have a high voltage value or a low voltage value;
providing a third negative configuration pre-decoded address signal and a fourth negative configuration pre-decoded address signal to a first NOR logic gate of the pre-decoder circuitry, wherein the third negative configuration pre-decoded address signal and the fourth negative configuration pre-decoded address signal have a different high voltage value or a different low voltage value; and
providing the third negative configuration pre-decoded address signal and the fourth negative configuration pre-decoded address signal to a second NOR logic gate of the pre-decoder circuitry.