Patent ID: 11935586
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. The memory device of claim 1, further comprising N read word lines and 2N write word lines, where N is a natural number, wherein
the plurality of rows in the memory array comprises N first rows of the first memory cells and N second rows of the second memory cells,
the N first rows and the N second rows are alternately arranged along the column direction,
each of the N read word lines is coupled to the first memory cells in one of the N first rows and the second memory cells in an adjacent one of the N second rows, and
each of the 2N write word lines is coupled either to the first memory cells in one of the N first rows or the second memory cells in one of the N second rows.