Patent ID: 11894418
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A preparation method of a semiconductor structure, comprising:
providing a substrate having an active area;
forming a sacrificial layer having a hollow cavity and located on the substrate, an inner sidewall surface of the hollow cavity having an uneven structure;
forming a first electrode layer located on the inner sidewall surface of the hollow cavity, a surface of the first electrode layer having an uneven structure, the first electrode layer being electrically connected to the active area, and the first electrode layer extending in a direction perpendicular to the substrate;
removing the sacrificial layer;
forming a dielectric layer located on the surface of the first electrode layer, a surface of the dielectric layer having an uneven structure; and
forming a second electrode layer located on the surface of the dielectric layer,
wherein a projection of the first electrode layer on the substrate is a first ring, and a projection of the dielectric layer on the substrate comprises a second ring and a third ring, the second ring being nested inside the first ring, and the third ring being sleeved outside the first ring; and
wherein a projection of the second electrode layer on the substrate comprises a solid portion and a fourth ring, the solid portion being located inside the second ring, and the fourth ring being sleeved outside the third ring.