Patent ID: 11973046
Assignee: SJ SEMICONDUCTOR(JIANGYIN) CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for preparing a semiconductor structure, comprising following steps: providing a Si substrate; patterning a groove in the Si substrate; forming an insulating layer in the groove to cover an entire bottom surface and side walls of the groove; forming a Cu layer and filling the groove with a Cu post, wherein the insulating layer covers side walls and a bottom surface of the Cu post and is in contact with the Si substrate; performing planarization on the Cu layer to expose the Si substrate, the insulating layer, and the Cu post; performing a wet etch process to remove Cu residues and a part of the Cu post, wherein a first height difference is configured to be between a top surface of the Cu post and a top surface of the insulating layer; and dry etching the Si substrate, wherein a second height difference is configured to be between a top surface of the Si substrate and the top surface of the insulating layer, and wherein the second height difference is configured to be greater than the first height difference, wherein the first height difference is in a range of 0.1 μm to 0.5 μm, and wherein the second height difference is in a range of 2 μm to 3 μm.