Patent ID: 11950434
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 8:
9. A method for forming an integrated chip, the method comprising:
depositing a data storage layer over a first conductive layer;
etching the data storage layer along a first direction to form a first data storage line and a second data storage line from the data storage layer, wherein the first data storage line and the second data storage line are elongated in the first direction;
etching the first conductive layer along the first direction to form a first word line and a second word line that are elongated in the first direction, wherein the first word line is under the first data storage line, and wherein the second word line is under the second data storage line;
depositing a first dielectric layer between the first data storage line and the second data storage line such that a void is within the first dielectric layer between the first data storage line and the second data storage line, wherein the void is delimited by one or more surfaces of the first dielectric layer;
depositing a second conductive layer over the first data storage line and the second data storage line;
etching the second conductive layer along a second direction, transverse to the first direction, to form a first bit line and a second bit line from the second conductive layer, wherein the first bit line and the second bit line are elongated in the second direction; and
etching the first data storage line and the second data storage line along the second direction to form a first data storage segment and a fourth data storage segment from the first data storage line and to form a second data storage segment and a third data storage segment from the second data storage line, wherein the first data storage segment and the second data storage segment are under the first bit line, and wherein the third data storage segment and the fourth data storage segment are under the second bit line.