Patent ID: 11915937
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method comprising:
forming a plurality of nanostructures over a substrate;
etching the plurality of nanostructures to form recesses;
forming source/drain regions in the recesses;
removing first nanostructures of the plurality of nanostructures leaving second nanostructures of the plurality of nanostructures;
depositing a gate dielectric over and around the second nanostructures;
depositing a protective material over the gate dielectric, the protective material comprising a metal;
performing a fluorine treatment on the protective material;
removing the protective material;
depositing a first conductive material over the gate dielectric; and
depositing a second conductive material over the first conductive material.