Patent ID: 11916072
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 16:
17. A method, comprising:
receiving a workpiece comprising:
a first dielectric fin, a second dielectric fin, and a third dielectric fin,
a first gate structure disposed between the first dielectric fin and the second dielectric fin, and
a second gate structure disposed between the second dielectric fin and the third dielectric fin;

forming a patterned hard mask layer over the workpiece, the patterned hard mask layer comprising an opening to expose the second dielectric fin;
removing the second dielectric fin to form an isolation trench;
depositing a dielectric material in the isolation trench to form a gate isolation structure;
planarizing the workpiece to remove the dielectric material on the patterned hard mask layer;
selectively removing the patterned hard mask layer; and
forming a first metal layer over the first gate structure and a second metal layer over the second gate structure.