Patent ID: 11960430
Assignee: INSPUR (BEIJING) ELECTRONIC INFORMATION INDUSTRY CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 10:
11. The method as claimed in claim 1, wherein data exchanged between the server with the FPGA BOX comprises: data type comprise reading operation, writing operation, and interruption operation;
Wherein a writing operation of a register or Direct Memory Access (DMA) in an FPGA is implemented by the following steps: a virtual ID, corresponding to the FPGA heterogeneous accelerator card, of the current environment of the server is acquired first and then according to an IP address of the FPGA heterogeneous accelerator card, a protocol packaging operation is performed according to a development interface of the high-speed interconnection mechanism; and next, data is sent to a remote FPGA heterogeneous accelerator card by an optical module to complete the writing operation;
the reading operation is implemented by the following steps: the server detects an Ethernet receiving data packet, and performs UDP unpacking operation according to a high-speed interconnection mechanism protocol to complete data receiving;
the interruption operation is implemented by the following steps: the FPGA heterogeneous accelerator card actively sends a feature packet, and after parsing the packet as a feature packet, the server transmits the feature packet to an upper-layer OpenCL/RTL development framework by a signal mechanism.