Patent ID: 11948987
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 16:
17. A semiconductor structure, comprising:
a first vertical stack of channel members disposed directly over a first semiconductor capping layer and a first bottom dielectric layer;
a first gate structure wrapping around each of the first vertical stack of channel members and disposed directly over a top surface of the first semiconductor capping layer;
a second vertical stack of channel members disposed directly over a second semiconductor capping layer and a second bottom dielectric layer;
a second gate structure wrapping around each of the second vertical stack of channel members and disposed directly over a top surface of the first semiconductor capping layer;
an epitaxial feature extending between the first vertical stack of channel members and the second vertical stack of channel members; and
a backside contact extending between the first semiconductor capping layer and the second semiconductor capping layer as well as between the first bottom dielectric layer and the second bottom dielectric layer to electrically couple to a bottom surface of the epitaxial feature,
wherein the first semiconductor capping layer and the second semiconductor capping layer are formed of a semiconductor material deposited using an epitaxial deposition process,
wherein a bottom surface of the first gate structure is in direct contact with a top surface of the first semiconductor capping layer,
wherein a bottom surface of the second gate structure is in direct contact with a top surface of the second semiconductor capping layer,
wherein the first semiconductor capping layer and the second semiconductor capping layer are formed of silicon.