Patent ID: 11928507
Assignee: INVENSENSE, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. The system of claim 9, wherein the FIFO component further comprises:
an event priority manager configured to generate the predefined sequence and push the one or more asynchronous events according to the predefined sequence, the predefined sequence generated according to at least one of a temporal order and a predefined priority ranking of the one or more asynchronous events;
an event FIFO component configured to store the one or more pushed asynchronous events according to the predefined sequence, to form one or more stored events; and
an event read controller configured to read at least one event among the one or more stored events in the event FIFO component according to the predefined sequence and send the at least one event to the function enable generator, when the DSP component is idle.