Patent ID: 11916119
Assignee: GLOBALFOUNDRIES U.S. INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A method comprising:
forming a barrier layer on a channel layer; and
forming a structure comprising:
a gate comprising:
a first gate section on the barrier layer; and
a second gate section on the first gate section;

a source-side gate sidewall spacer on the barrier layer and positioned laterally adjacent to the first gate section, wherein the second gate section extends laterally at least partially over the source-side gate sidewall spacer;
a source terminal comprising:
a first source region extending through the barrier layer, wherein the first source region has a proximal portion positioned laterally immediately adjacent to a lower portion of the source-side gate sidewall spacer and further has a distal portion; and
a second source region on the distal portion of the first source region; and

a source-side dielectric liner on the proximal portion of the first source region positioned laterally immediately adjacent to an upper portion of the source-side gate sidewall spacer, wherein the source-side dielectric liner is further positioned laterally between the second gate section and the second source region.