Patent ID: 11887897
Assignee: TOKYO ELECTRON LIMITED
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of fabricating a semiconductor device, the method comprising:
forming a multilayer stack on a substrate, the multilayer stack including alternate metal layers and dielectric layers;
forming a first opening and a second opening through the multilayer stack to uncover a semiconductor layer of the substrate;
forming a first vertical channel structure within the first opening, the first vertical channel structure having a first source region and a first drain region being in direct contact with vertical sidewalls of a first metal layer and a third metal layer of the metal layers of the multilayer stack uncovered by the first opening, respectively, and a first gate region being in contact with a vertical sidewall of a second metal layer of the metal layers of the multilayer stack uncovered by the first opening; and
forming a second vertical channel structure within the second opening, the second vertical channel structure having a second source region and a second drain region being in direct contact with another vertical sidewalls of the first and third metal layers of the multilayer stack uncovered by the second opening, respectively, and a second gate region being in contact with another vertical sidewall of the second metal layer of the metal layers of the multilayer stack uncovered by the second opening.