Patent ID: 11862292
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. An integrated circuit comprising:
a first register to store an address of a corresponding one of a plurality of memory banks;
a second register indicating a first entry storing an address of a memory bank, on which a write process is predicted to be completed next among the plurality of memory banks;
a third register indicating a second entry to be updated; and
a controller to:
update, for a first clock cycle, the second entry according to an input address of a target memory bank of the plurality of memory banks to store input data through the write process,
set the third register to indicate a third entry subsequent to the second entry, in response to updating the second entry, and
configure, for the first clock cycle, one or more buffers of a plurality of buffers to perform the write process, according to the updated second entry.