Patent ID: 11923251
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  C | IPC C  H

Claim 16:
17. An integrated circuit device comprising:
a semiconductor substrate;
a first semiconductor fin protruding higher than the semiconductor substrate;
a second semiconductor fin protruding higher than the semiconductor substrate;
a dielectric region between the first semiconductor fin and the second semiconductor fin;
a first gate stack on the first semiconductor fin, wherein the first gate stack comprises a first sidewall and a second sidewall parallel to each other, and a third sidewall and a fourth sidewall parallel to each other, wherein the first sidewall is perpendicular to the third sidewall;
a dielectric hard mask over and contacting the dielectric region, wherein the dielectric hard mask comprises edges vertically aligned to respective sidewalls among the first sidewall, the second sidewall, the third sidewall, and the fourth sidewall;
a second gate stack on the second semiconductor fin;
a first source/drain region on a side of the first gate stack, wherein the first source/drain region and the first gate stack are comprised in a first transistor; and
a second source/drain region on a side of the second gate stack, wherein the second source/drain region and the second gate stack are comprised in a second transistor.