Patent ID: 11863188
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. The flip-flop circuit of claim 11, wherein the master latch circuit comprises:
a first P-type transistor having a gate terminal connected to the first node, a source terminal connected to a sixth node, and a drain terminal connected to the second node; and
a first N-type transistor having a gate terminal connected to the first node, a source terminal connected to a seventh node, and a drain terminal connected to the second node, and
the slave latch circuit comprises:
a second P-type transistor having a gate terminal configured to receive the second control signal, a source terminal connected to a positive power node, and a drain terminal connected to the sixth node; and
a second N-type transistor having a gate terminal configured to receive the first control signal, a source terminal connected to a negative power node, and a drain terminal connected to the seventh node.