Patent ID: 11948656
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. The meory system of claim 19, wherein, to generate the first flag, the processing circuitry is configured to cause the memory system to:
activate the first row of memory cells a first time;
output, to the first input line of the first multiplexer, a first bit of the first subset based at least in part on activating the first row of memory cells the first time, wherein the first bit represents a least significant bit associated with the first subset;
activate the first row of memory cells a second time; and
output, from the first multiplexer to a first input line of the second multiplexer, the first bit of the first subset based at least in part on activating the first row of memory cells the second time, wherein the first bit represents a next significant bit associated with the first sub set.