Patent ID: 11908693
Assignee: NANYA TECHNOLOGY CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for preparing a semiconductor device structure, comprising:
forming a target layer over a semiconductor substrate;
forming a plurality of first mask patterns over the target layer;
forming a lining layer conformally covering the first mask patterns and the target layer, wherein a first opening is formed over the lining layer and between the first mask patterns;
filling the first opening with a plurality of second mask patterns by the steps of:
forming a second mask layer on the lining layer, wherein the second mask layer has a first portion filled in the first opening and a second portion formed over a top surface of the lining layer; and
removing the second portion of the second mask layer, wherein the first portion of the second mask layer is remained in the first opening to form each of the second mask patterns between the first mask patterns, such that the second mask patterns are alternating with the first mask patterns, wherein a flat top surface of the second mask pattern is coplanar with a flat top surface of the lining layer; and
performing an etching process on the lining layer and the target layer using the first mask patterns and the second mask pattern as a mask such that a plurality of second openings are formed in the target layer, wherein each of the second openings is formed between the first mask pattern and the second mask pattern, wherein a width of each of the second openings is smaller than a width of each of the first openings, wherein the etching process comprises the steps of:
during a first stage of the etching process, a top portion of the lining layer above top surfaces of the first mask patterns is etched to expose the first mask patterns, wherein an etching rate of the lining layer is higher than an etching rate of the second mask patterns, wherein the top surfaces of the first mask patterns are coplanar with the flat top surface of the lining layer after the first stage of the etching process;
during a second stage of the etching process, removing portions of the lining layers between the first mask patterns and second mask pattern are etched to be removed to form a plurality of third openings so as to expose a top surface of the target layer, wherein the etching rate of the lining layer is higher than an etching rate of the first mask patterns; and
during a third stage of the etching process, deepening the third openings in the target layer to form the second openings respectively, wherein a bottom of each of the third openings is above a bottom of the target layer, such that a width of the target layer at the second opening is reduced and is smaller than a width of the target layer at the first mask pattern;
wherein after the third stage of the etching process, the target layer is etched to form a base portion coving the semiconductor substrate and a plurality of protruding portions integrally, spacedly, and upwardly extended from the base portion, wherein each of the third openings is defined between every two of the protruding portions and the base portion, such that the third openings are alternating with the protruding portions and located above the base portion.