Patent ID: 11954037
Assignee: NVIDIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. A computing system comprising:
a processing device coupled with at least one central processing unit (CPU) and at least one graphics processing unit (GPU);
a farthest level of cache from the processing device; and
a second-farthest level of cache from the processing device coupled between the farthest level of cache and the processing device; and
wherein the processing device is to:
generate a plurality of virtual addresses that are sequentially numbered for data that is to be at least one of processed or transferred in response to an input-output (I/O) request received from the at least one CPU or the at least one GPU;
allocate, for the data, a continuous range of physical addresses of the farthest level of cache, wherein the continuous range of physical addresses is limited to a size of the cache;
generate a set of hash-based values based on one of respective physical addresses or mappings between the plurality of virtual addresses and respective physical addresses of the continuous range of physical addresses;
identify a unique cache line of the second-farthest level of cache that corresponds to each respective hashed-based value of the set of hash-based values; and
cause the data to be directly stored in the unique cache lines of the second-farthest cache.