Patent ID: 11876090
Assignee: CYPRESS SEMICONDUCTOR CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. The sensor circuit of claim 12, wherein the control circuit is further for sensing instructions to the ESD protection circuit, the instructions for, when Vpin exceeds a negative trigger voltage large enough to break down a drain junction of one or more of the plurality of PFETs pulling-down the voltage of the VHigher-Driver node to less than ground potential:
forward biasing a drain terminal of a first NFET connected to the VHigher-Driver node;
forward biasing a parasitic NPN transistor in the first NFET formed by an n+ drain junction of the first NFET, a P-well in which the n+ drain junction is formed, and a second DN-well in which the P-well is formed; and
conducting current from VHigher-Driver node through the parasitic NPN transistor and through a junction between the second DN-well and a substrate in which the circuit is formed to the substrate and to a second NFET connected between first NFET and ground, whereby the drain terminal of the first NFET is shorted to ground and a voltage of the VHigher-Driver node is substantially held to ground potential.