Patent ID: 11900522
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A graphics processor comprising:
a programmable execution unit operable to execute programs to perform graphics processing operations, wherein the execution unit is configured as a plurality of execution lanes, wherein individual execution threads in a group of plural execution threads can be executed by respective execution lanes, and wherein a group of plural execution lanes can be caused to be in a co-operative state in which the group of plural execution lanes perform processing operations together;
a thread termination circuit that is operable to cause individual subsets of one or more threads within a group of plural execution threads being executed by the programmable execution unit to be terminated; and
a thread termination management circuit that is configured such that when a group of plural execution lanes are performing a set of processing operations in a co-operative state, in response to the thread termination circuit determining that a subset of one or more execution threads associated with a corresponding one or more of the execution lanes in the group of execution lanes in the co-operative state should be terminated, the thread termination management circuit determines whether a condition to immediately terminate the subset of one or more execution threads is met, and wherein when such condition is not met, the group of execution lanes is allowed to continue their execution in the co-operative state, and the thread termination management circuit stores a record that the threads in the subset of one or more execution threads should subsequently be terminated.