Patent ID: 11869963
Assignee: INFINEON TECHNOLOGIES AG
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. A semiconductor device, comprising:
a support substrate having a first surface capable of supporting the epitaxial growth of at least one III V semiconductor and a second surface opposing the first surface;
at least one mesa positioned on the first surface, the at least one mesa comprising an epitaxial III-V semiconductor-based multi-layer structure on the first surface of the support substrate, the III-V semiconductor-based multi-layer structure forming a boundary with the first surface;
a parasitic channel suppression region positioned laterally adjacent the boundary,
wherein a thickness of the parasitic channel suppression region is less than a height of the at least one mesa, the height of the at least one mesa being a distance between the first surface and an upper surface of the at least one mesa opposite from the first surface.