Patent ID: 11961887
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 8:
9. A semiconductor device structure, comprising;
a plurality of semiconductor layers vertically stacked;
a gate electrode layer surrounding each semiconductor layer of the plurality of semiconductor layers;
a high-k (HK) dielectric layer in contact with the gate electrode layer;
a source/drain feature in contact with each semiconductor layer of the plurality of semiconductor layers; and
a dielectric spacer disposed between the HK dielectric layer and the source/drain feature, wherein the dielectric spacer has a first side in contact with the source/drain feature and a second side in contact with the HK dielectric layer, and the second side comprising:
a first section has a first curved surface having a first radius of curvature; and
a second section has a second curved surface having a second radius of curvature different than the first radius of curvature,
wherein the first section and the second section are connected and formed as an integral.