Patent ID: 11894270
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 3:
4. A method of forming an interconnect structure, comprising:
disposing a first interconnect layer into a first interlayer dielectric (ILD), wherein the first interconnect layer comprises a plurality of first conductive traces;
selectively disposing a second ILD over exposed surfaces of the first ILD between the first conductive traces, wherein an uppermost surface of the second ILD is above an uppermost surface of the first conductive traces;
disposing a helmet layer over the second ILD, wherein the helmet layer is deposited with an atomic layer deposition (ALD) processes that comprises spinning a substrate on which the interconnect structure is formed; and
disposing a third ILD over the interconnect structure, wherein the third ILD fills gaps between portions of the helmet layer on corresponding portions of the second ILD.