Patent ID: 11916550
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. An integrated circuit, comprising:
a first data line set;
a second data line set;
a plurality of output data lines;
a clock generator comprising first and second NAND gates configured to generate respective first and second latching clock signals in response to a select signal and a clock signal having a clock signal waveform, wherein the clock generator is configured to generate each of the first latching clock signal and the second latching clock signal having the clock signal waveform; and
a plurality of multiplexing latch circuits configured to output a latched data set to the plurality of output data lines based on either a first data set received on the first data line set or a second data set received on the second data line set based on the first and second latching clock signals.