Patent ID: 11860225
Assignee: RENESAS ELECTRONICS CORPORATION
Field: Measurement (Instruments)
Classification: CPC G | IPC G

Claim 2:
3. The method of manufacturing the semiconductor device according to claim 2,
wherein the test apparatus includes a socket configured to be arranged on the test board and house the unit,
wherein the socket has a package housing portion,
wherein the (c) includes:
(c1) after the (a) and the (b), arranging the first semiconductor package in the package housing portion of the socket;
(c2) after the (c1), pushing the first semiconductor package toward the unit, thereby bringing the first external terminal of the first semiconductor package into contact with the first tip portion of the probe pin and bringing the second tip portion of the probe pin into contact with the terminal of the test board, and further supplying a current or voltage to the first semiconductor chip via the test board, the probe pin, and the first external terminal, thereby performing the electrical test of the first semiconductor package; and
(c3) after the (c2), taking out the first semiconductor package from the package housing portion of the socket, and

wherein the (f) includes:
(f1) after the (d) and the (e), arranging the second semiconductor package in the package housing portion of the socket;
(f2) after the (f1), pushing the second semiconductor package toward the unit, thereby bringing the second external terminal of the second semiconductor package into contact with the second tip portion of the probe pin and bringing the first tip portion of the probe pin into contact with the terminal of the test board, and further supplying a current or voltage to the second semiconductor chip via the test board, the probe pin, and the second external terminal, thereby performing the electrical test of the second semiconductor package; and
(f3) after the (f2), taking out the second semiconductor package from the package housing portion of the socket.