Patent ID: 11960718
Assignee: STMICROELECTRONICS S.R.L.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 25:
26. A non-transitory computer-readable medium having contents which cause a memory management circuit to perform a method, the method comprising:
receiving a request to store new data at a memory location of a bitwise programmable non-volatile memory;
sensing data stored at the memory location of the bitwise programmable memory;
comparing bits of the sensed data with bits of the new data;
generating an indication of a cost difference between:
a first burst of bitwise programming operations associated with programming bits of the new data which are different from bits of the sensed data; and
a second burst of bitwise programming operations associated with programming bits of a complementary inversion of the new data which are different from bits of the sensed data; and

executing one of the first burst of bitwise programming operations or the second burst of bitwise programming operations based on the generated indication of the cost difference, wherein, when a size of the memory location is smaller than a size of a memory word including the memory location, and an inversion flag associated with the memory word has to be programmed, the cost difference takes into account programming operations for inverting of all the other bits belonging to the memory word outside of the memory location, and the programming burst comprises programming all the other bits at a complementary inverted state.