Patent ID: 11966633
Assignee: CADENCE DESIGN SYSTEMS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. A system comprising:
a non-transitory memory that stores machine-readable instructions; and
a processing unit that accesses the memory and executes the machine-readable instructions, the machine-readable instructions comprising:
a non-volatile memory (NVM) algorithm generator that evaluates a Liberty file characterizing an NVM module and a memory view of the NVM module that identifies ports and associated operations of the NVM module to generate a control algorithm, the control algorithm comprising:
a read algorithm that includes an order of operations for assigning values to ports of the NVM module to assert a read condition of a strobe port of the NVM module, executing a memory read on the NVM module and setting values to the ports on the NVM module to assert a complement of a program condition of the strobe port on the NVM module; and
a program algorithm that includes an order of operations for assigning values to ports of the NVM module to assert the program condition of the strobe port of the NVM module, executing a memory write on the NVM module and setting values to the ports on the NVM module to assert the complement of the program condition of the strobe port on the NVM module.