Patent ID: 11915968
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. A semiconductor structure, comprising:
a base, at least one shallow trench isolating structure being formed in the base and several active regions arranged at an interval being isolated by the at least one shallow trench isolating structure in the base;
a first trench located in the base, a part of the several active regions being exposed in the first trench;
a first conducting structure filling the first trench fully;
a first dielectric layer located on the base;
a second trench located in the first dielectric layer, the first conducting structure being exposed in the second trench and a width of a top of the second trench being greater than a width of a top of the first trench; and
a second conducting structure located in the second trench, wherein:
the second trench is an inverted trapezoidal trench,
each of the first conducting structure and the second conducting structure at least comprises a polysilicon structure, and
the first dielectric layer comprises a second spin-coated hard mask layer and a second silicon oxide layer stacked in sequence from a second dielectric layer of the base.