Patent ID: 11869573
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 13:
14. The semiconductor memory of claim 1, wherein the voltage regulation unit comprises a first resistor, a second resistor, a first PMOS transistor, and a second PMOS transistor, wherein:
one end of the first resistor is coupled to one end of the second resistor and the other end of the first resistor is coupled to a drain of the first PMOS transistor;
the other end of the second resistor is coupled to a ground;
a positive input end of the operational amplifier is coupled to an electrical connection point between the first resistor and the second resistor;
a negative input end of the operational amplifier is coupled to a reference voltage;
an output end of the operational amplifier is coupled to a gate of the first PMOS transistor;
a supply end of the operational amplifier is coupled to the external input first voltage;
a source of the first PMOS transistor is coupled to the external input first voltage;
an electrical connection point formed between the drain of the first PMOS transistor and the first resistor outputs the second voltage;
a source of the second PMOS transistor is coupled to the external input first voltage;
a gate of the second PMOS transistor is coupled to the output end of the operational amplifier; and
a drain of the second PMOS transistor is coupled to a bias current regulation end of the operational amplifier to regulate a bias current of the operational amplifier.