Patent ID: 11942179
Assignee: MACRONIX INTERNATIONAL CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. A memory device comprising:
a memory cell array comprising a plurality of memory cells;
a plurality of memory cell lines connecting respective lines of memory cells in the memory cell array; and
a page buffer circuit comprising a plurality of page buffers coupled to the plurality of memory cell lines, each page buffer comprising:
a latch circuit comprising a latch and a sensing transistor coupled to the latch; and
a compensation circuit coupled to the sensing transistor,
wherein the sensing transistor comprises a gate terminal coupled to a sensing node, a first terminal coupled to the latch, and a second terminal coupled to the compensation circuit, and
wherein the compensation circuit is configured to apply a control voltage to the second terminal to compensate for a variation of a threshold voltage of the sensing transistor.