Patent ID: 11935612
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory, comprising:
a storage circuit comprising a plurality of sense amplifier arrays and a plurality of storage unit arrays, the sense amplifier arrays and the storage unit arrays being arranged alternately, and the sense amplifier arrays being configured to perform data reading and writing on the storage unit arrays, wherein the sense amplifier arrays comprise a first sense amplifier array and a second sense amplifier array that are adjacent to each other;
a first reading circuit which is electrically connected to the first sense amplifier array through a first data line, and is configured to compare a reference voltage signal with a signal on the first data line corresponding to the first reading circuit, and output a comparison result as read-out data;
a second reading circuit which is electrically connected to the second sense amplifier array through a first data line, and is configured to compare a reference voltage signal with a signal on the first data line corresponding to the second reading circuit, and output a comparison result as read-out data; and
a plurality of correcting circuits configured to perform at least one of error detection and error correction on the read-out data, wherein the first reading circuit and the second reading circuit are configured to respectively transmit the read-out data outputted therefrom to different correcting circuits.