Patent ID: 11915357
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus comprising:
execution circuitry comprising a plurality of functional units to execute a plurality of ray shaders and generate a plurality of primary rays and a corresponding plurality of ray messages;
a buffer to queue the plurality of ray messages generated by the plurality of functional units prior to storage in a memory-backed stack and/or a memory subsystem;
a cache to store one or more of the plurality of primary rays;
the memory-backed stack to store a first subset of the plurality of ray messages in a corresponding plurality of entries, wherein a second subset of the plurality of ray messages are to be stored to the memory-backed stack, or to be stored to the memory subsystem based, at least in part, on a number of entries currently occupied by ray messages in the memory-backed stack;
ray traversal circuitry to read a next ray message from the memory-backed stack, retrieve a next primary ray identified by the ray message from the cache or the memory subsystem, and perform traversal operations on the next primary ray; and
throttling circuitry is to throttle dispatching of a plurality of ray shaders based, at least in part, on the number of entries currently occupied by the ray messages in the memory-backed stack and/or ray message occupancy in the buffer, wherein one or more threshold values for throttling are to be adjusted based, at least in part, on the number of entries currently occupied by the ray messages in the memory-backed stack and/or the ray message occupancy in the buffer.