Patent ID: 11900981
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 10:
11. A method of operation fora memory apparatus having a first set of dynamic random access memory (DRAM) banks and a second set of DRAM banks, the method comprising:
with an interface, receiving, from a memory controller, commands for the first set of DRAM banks, including
a first command to perform a refresh operation in a first bank in the first set of DRAM banks, and
a second command to access a selected bank of the first set of DRAM banks;

wherein for the interface, a period is to expire following completion of the refresh operation and prior to receipt of the second command, the period for the first interface being at least
a first time interval when the first bank and the selected bank are the same bank in the first set of DRAM banks, and
a second time interval when the first bank and the selected bank are different banks in the first set of DRAM banks; and

wherein the first time interval is greater than the second time interval; and
with an interface, receiving commands, from the memory controller, for the second set of the DRAM banks.