Patent ID: 11887986
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. The semiconductor memory device of claim 1, further comprising:
a first semiconductor substrate;
a second semiconductor substrate facing the first semiconductor substrate, the second semiconductor substrate including peripheral circuits integrated thereon;
first bonding pads; and
second bonding pads, wherein
the bit line is one of a plurality of bit lines,
the first bonding pads are connected to the bit lines,
the second bonding pads are connected to the peripheral circuits integrated on the second semiconductor substrate,
the first capacitor and the second capacitor are on the first semiconductor substrate,
the interlayer insulating layer covers the first capacitor and the second capacitor on the first semiconductor substrate, and
the first bonding pads are coupled to the second bonding pads.