Patent ID: 11880607
Assignee: MEDIATEK SINGAPORE PTE. LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A system operative to perform self-repair, comprising:
a test circuit to generate test patterns and to identify defective memory cells;
a fuse memory coupled to the test circuit to store a repair address shared by row repair and column repair of a cell array; and
a memory circuit in a chip that is coupled to the test circuit and the fuse memory, the memory circuit further comprising:
the cell array including a plurality of rows and a plurality of columns of memory cells;
a controller to receive an input of a fuse signal that indicates the repair address, the fuse signal including an enable signal that indicates whether the repair address is for the row repair or the column repair;
a row repair decoder to receive the repair address of a defective row from the controller when the enable signal indicates the row repair, and to map the defective row to a redundant row of the cell array; and
a column repair decoder to receive the repair address of a defective column from the controller when the enable signal indicates the column repair, and to map the repair address to another column of the cell array,

wherein the memory circuit is to receive the fuse signal from the fuse memory through a plurality of fuse pins of the chip.