Patent ID: 11908535
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device comprising: a memory cell array comprising a plurality of normal word lines and at least one spare word line; and a repair controller configured to set memory cells which are connected to at least one weak word line from among the normal word lines to a first operation mode, and further configured to set memory cells connected to the at least one spare word line to a second operation mode, wherein the at least one weak word line is detected based on a test result, wherein, during a test process, memory cells connected to the plurality of normal word lines are set to a third operation mode configured to write (n+m)-bit data, the first operation mode is configured to write n-bit data to the memory cells connected to the at least one weak word line, the second operation mode is configured to write m-bit data to the memory cells connected to the at least one spare word line, and both n and m are natural numbers greater than or equal to 1 and m is greater than n.