Patent ID: 11923024
Assignee: GLOBALFOUNDRIES U.S. INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 14:
15. The memory built-in self-test system according to claim 8, further comprising a second level-sensitive register unit for reading data from the memory, the second level-sensitive memory unit including:
a transparent latch coupled to the first clock signal for receiving data from the memory; and
a second flip-flop including a first latch and a second latch, wherein an output of the transparent latch is coupled to an input of the first latch of the second flip-flop,
wherein the second latch of the second flip-flop is clocked by the second clock signal, and wherein the first latch of the second flip-flop is clocked by the inverse of the second clock signal.