Patent ID: 11967365
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A memory structure comprising:
bitcell circuitry having transistor logic and passgates, wherein the transistor logic is configured to store data, and wherein the passgates are coupled to the transistor logic and configured to access the data stored in the transistor logic; and
read-write circuitry having wordlines and bitlines coupled to the passgates, wherein the passgates are time-multiplexed with the wordlines and the bitlines so as to increase a first number of read-write ports to a second number of read-write ports that is greater than the first number of read-write ports,
wherein the passgates include a first write passgate and a second write passgate with outputs coupled together, wherein the passgates include a third write passgate and a fourth write passgate with outputs coupled together, wherein the wordlines include first write wordlines coupled to the first write passgate, wherein the wordlines include second write wordlines coupled to the second write passgate, wherein the wordlines include third write wordlines coupled to the third write passgate, and wherein the wordlines include fourth write wordlines coupled to the fourth write passgate.