Patent ID: 11915745
Assignee: DXCORR DESIGN INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. The method of claim 9, wherein controlling the power supply rails to the array power headers and the retention header within the decoder slice(s), comprises:
selecting the one or more memory segments comprising the decoder slice(s) for performing read/write operations in normal mode;
activating the array power header of the selected one or more memory segments to operate in the normal mode by a logic value 1 of decoder/segment select input; and
simultaneously deactivating array power header of unselected one or more memory segments to operate in deep sleep retention mode by switching the decoder/segment select input to a logic value 0 and ds_retention input to a lower voltage value, wherein voltage value of input Vddg of the array power header is lowered from full voltage to a voltage value higher than a retention voltage.