Patent ID: 11940836
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A method comprising:
setting a first clock of a first semiconductor circuit and a second clock of a second semiconductor circuit to a common clock source when both the first and second semiconductor circuits are in a slow clock speed, wherein an input/output (IO) at an interface between the first and second semiconductor circuit is capable of operating at the slow clock speed;
synchronizing a first division counter of the first clock and a second division counter of the second clock at the slow clock speed;
simultaneously switching both the first and second semiconductor circuits to a fast clock speed that is a multiple of the slow clock speed, wherein the IO is not capable of operating at the fast clock speed;
using a pulse of the first division counter to shadow the first division counter to a third division counter on the second semiconductor circuit;
comparing the third division counter to the second division counter;
detecting a difference between the third division counter and the second division counter;
stopping functional logical of the second semiconductor circuit;
aligning the second division counter and the third division counter while the functional logical is stopped; and
restarting the functional logical once the second division counter is aligned with the third division counter, such that each of the second division counter and the third division counter and the first division counter are all synchronized.