Patent ID: 11948638
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A method, comprising:
applying, during a first duration, a first voltage to a first set of word lines coupled with a first tier of memory cells of a plurality of tiers of memory cells, wherein each tier of the plurality of tiers is coupled with two sets of alternating word lines and a plurality of pillars extend vertically through the plurality of tiers, each pillar of the plurality of pillars coupled with a respective bit line and two memory cells at each tier of the plurality of tiers, and wherein, during the first duration, at least one memory cell of a first subset of the first tier of memory cells thresholds based at least in part on applying the first voltage to the first set of word lines;
applying, during a second duration after the first duration, a second voltage to the first set of word lines, wherein, during the second duration, at least one memory cell of a second subset of the first tier of memory cells thresholds and the at least one memory cell of the first subset of the first tier of memory cells is written to a first logic state based at least in part on applying the second voltage to the first set of word lines; and
applying, during a third duration after the second duration, a third voltage to the first set of word lines, wherein, during the third duration, the at least one memory cell of the second subset of the first tier of memory cells is written to a second logic state based at least in part on applying the third voltage to the first set of word lines.