Patent ID: 11967573
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A method, comprising:
providing a metal line embedded in an inter-metal dielectric layer;
forming a first dielectric layer over the metal line;
patterning the first dielectric layer to expose a portion of the metal line in a first opening;
forming a first pattern-forming layer over the first dielectric layer, thereby filling the first opening;
forming a second pattern-forming layer over the first pattern-forming layer;
patterning the first and second pattern-forming layers to form a second opening;
etching the first pattern-forming layer to form a footing profile that laterally extends a bottom portion of the second opening; and
forming a redistribution layer (RDL) in the second opening such that the RDL is electrically coupled to the metal line.