Patent ID: 11942172
Assignee: REALTEK SEMICONDUCTOR CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 12:
13. A chip debugging method, comprising:
outputting a plurality of first signals in a plurality of sets of debug signals according to a plurality of address signals, wherein the plurality of sets of debug signals are respectively generated from a plurality of functional circuitries in a chip;
selecting a plurality of second signals from the plurality of first signals according to the plurality of address signals;
selecting a plurality of first data from the plurality of second signals according to a plurality of split signals and outputting the plurality of first data to be first debug data, wherein each of the plurality of first data is partial data of a corresponding signal of the plurality of second signals; and
determining whether to output the first debug data or at least one output signal associated with the plurality of functional circuitries via a plurality of output ports of the chip according to a plurality of switching signals.