Patent ID: 11955930
Assignee: ANALOG DEVICES, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A phase lock loop (PLL) circuit, the PLL circuit comprising:
an input to receive a reference oscillator signal and an output to provide an output clock signal;
a feedback loop that corrects phase error between the output clock signal and the reference oscillator signal; and
a multi-phase oscillator circuit to generate the output clock signal, the multi-phase oscillator circuit including:
a ring oscillator circuit including multiple inverters connected in series in a ring, wherein a circuit supply of the inverters is a control voltage;
multiple level translator circuits, each level translator circuit including a first input transistor, a second input transistor, an output, and a connection to a circuit supply different from the circuit supply of the inverters; and
wherein an output of an inverter of the ring oscillator circuit is coupled to the next inverter of the ring oscillator circuit and to only one input transistor of a level translator circuit, and the other input transistor of the level translator circuit is coupled to an output of another level translator circuit.