Patent ID: 11935612
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 2:
3. The memory of claim 2, wherein the first amplification circuit comprises:
a first transistor configured to enable a source to be electrically connected to a first voltage;
a second transistor configured to enable a source to be electrically connected to a first voltage node, and a drain to be electrically connected to a drain of the first transistor;
a third transistor configured to enable a source to be electrically connected to the first voltage, a drain to be electrically connected to a gate of the first transistor, and a gate to be electrically connected to the drain of the first transistor; and
a fourth transistor configured to enable a source to be electrically connected to a second voltage node, a drain to be electrically connected to each of the drain of the third transistor and the gate of the second transistor, and a gate to be electrically connected to the drain of the first transistor.