Patent ID: 11894371
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A method of manufacturing an integrated circuit device, the method comprising:
preparing a substrate having a peripheral circuit region;
forming a semiconductor epitaxial layer on the substrate in the peripheral circuit region;
forming a semiconductor amorphous layer on the semiconductor epitaxial layer; and
forming a semiconductor crystalline layer by crystallizing the semiconductor amorphous layer by performing heat treatment by using the semiconductor epitaxial layer as the seed;
forming a plurality of fin-type active regions defined by trenches forming by etching an upper portion of the substrate, and a plurality of semiconductor layers by etching the semiconductor epitaxial layer and the semiconductor crystalline layer, each of the plurality of semiconductor layers including a lower semiconductor layer that is a portion of the semiconductor epitaxial layer and an upper semiconductor layer on the lower semiconductor layer that in a portion of the semiconductor crystalline layer; and
forming a plurality of gate electrodes on the plurality of fin-type active regions and plurality of semiconductor layers,
wherein a semiconductor interface is provided between the lower semiconductor layer and the upper semiconductor layer of the each of the plurality of semiconductor layers.