Patent ID: 11922029
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A system comprising:
a memory device comprising a plurality of memory cells; and
a processing device operatively coupled with the memory device, the processing device to:
receive a first read command at a first time, wherein the first read command is with respect to a set of memory cells of the plurality of memory cells of the memory device;
receive a second read command at a second time, wherein the second read command is with respect to the set of memory cells of the plurality of memory cells of the memory device;
increment a read counter for the memory device by a value reflecting a difference between the first time and the second time;
determine that a value of the read counter satisfies a threshold criterion; and
responsive to determining that the value of the read counter satisfies the threshold criterion, perform a data integrity scan with respect to the set of memory cells.