Patent ID: 11929430
Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of forming a transistor device, comprising:
providing a semiconductor body comprising a plurality of two-dimensional charge carrier gas channels that are disposed at different vertical depths below an upper surface of the semiconductor body;
forming a gate fin in the semiconductor body by forming a pair of gate trenches in an upper surface of the semiconductor body, the pair of gate trenches exposing each one of two-dimensional charge carrier gas channels in the plurality at first and second sidewalls of the gate fin;
providing source and drain contacts that are arranged such that the gate fin is between the source and drain contacts in a current flow direction of the gate fin and such that each of the source and drain contacts is electrically connected to each one of the plurality of two-dimensional charge carrier gas channels;
providing a gate structure that is configured to control a conductive connection between the source and drain contacts by controlling a conductive state of each one of the plurality of two-dimensional charge carrier gas channels;
wherein providing the gate structure comprises:
forming a region of doped type III-nitride semiconductor material that covers the gate fin and extends into the gate trenches;
forming a conductive Schottky contact material on top of layer of doped type III-nitride semiconductor material; and
forming a conductive gate electrode on top of the conductive Schottky contact material; and

wherein the method further comprises forming one or more current blocking devices that are configured to prevent carriers from flowing into or out of the region of doped type III-nitride semiconductor material,
wherein each of the two-dimensional charge carrier gas channels extends to the first and second sidewalls of the gate fin, and wherein the one or more current blocking devices are configured to prevent carriers from flowing in both directions between the region of doped type III-nitride semiconductor material and each of the two-dimensional charge carrier gas channels at the first and second sidewalls of the gate fin.