Patent ID: 11900135
Assignee: CADENCE DESIGN SYSTEMS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. An emulation method comprising:
emulating, by the processor, a circuit design by a circuit that operates with an unknown logic state, the processor including:
a first multiplexer having a first input configured to receive a first ternary signal, and a second input configured to receive a second ternary signal,
a second multiplexer having a first input configured to receive the first ternary signal, and a second input configured to receive the second ternary signal, and
a third multiplexer having a first input coupled with an output of the second multiplexer, a second input configured to receive input based on the first ternary signal and the second ternary signal, and an output configured to indicate whether an output of the first multiplexer is known or unknown;
receiving, by the processor at one or more of the first multiplexer and the second multiplexer, an unknown reset signal associated with a signal transition of one or more devices of the circuit, and wherein the plurality of inputs further includes a selector signal for selecting one or more of the first ternary signal and the second ternary signal, the first ternary signal and the second ternary signal associated with combinational logic of the circuit design; and
emulating, by the processor, an output of the one or more devices having a known logic state in a mode selected from a plurality of modes of operation, the plurality of modes of operation configured to resolve a behavior of a flip-flop of the combinational logic with the known logic state, the unknown logic state, and the unknown reset signal.