Patent ID: 11941291
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. An apparatus, comprising:
a memory device; and
a memory sub-system controller coupled to the memory device, wherein the memory subsystem controller including a memory sub-system memory fencing component configured to:
receive a first number of commands, a second number of commands, and a memory fencing command, wherein a latency associated with executing the first number of commands is greater than a latency associated with executing the second number of commands; and
execute at least one of the first number of commands before executing at least one of the second number of commands in response to instructions in the memory fencing command, wherein the memory fencing command prevents a non-deterministic protocol used by the memory sub-system from performing the second number of commands with lower latency before the first number of commands with higher latency; wherein the memory fencing command is configured to execute the first number of commands to move data from a first location to a second location in the memory sub-system before executing the second number of commands to read the data from the first location with the address in the memory sub-system.