Patent ID: 11910606
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A method of forming an integrated assembly, comprising:
forming conductive levels that alternate with insulative levels to form a stack; the forming the conductive levels comprising:
forming first regions of the conductive levels by forming a conductive core material and forming a conductive liner material along upper and lower surfaces of the conductive core material; the conductive liner material being compositionally different from the conductive core material; and
forming second regions of the conductive levels laterally adjacent the first regions, the second regions comprising a conductive rail having at least two portions laterally offset relative to one another, with one of the at least two portions having a first uniform composition along its total vertical thickness, and with another of the at least two portions having a second uniform composition, different from the first uniform composition, along its total vertical thickness.