Patent ID: 11921160
Assignee: SYNOPSYS, INC.
Field: Measurement (Instruments)
Classification: CPC G | IPC G

Claim 0:
1. A method comprising:
running scan tests on an integrated circuit containing logic circuits; wherein the logic circuits are interconnected to form one or more logic scan chains, and running the scan tests comprises shifting out scan test data from the logic circuits through the logic scan chains; and
shifting out sensor data from sensor blocks on the integrated circuit, the sensor blocks capturing measurements of operating conditions for the logic circuits during the scan tests and producing the sensor data from the captured measurements; wherein the sensor blocks are interconnected to form one or more sensor scan chains, and the sensor data is shifted out through the sensor scan chains concurrently with the shifting out of the scan test data through the logic scan chains;
wherein the scan tests are controlled according to a scan enable signal that defines a shift period and a capture period, the method further comprising:
during the capture period, capturing the scan test data by the logic scan chains and capturing the sensor data by the sensor scan chains; and
during the shift period, shifting out the scan test data through the logic scan chains and shifting out the sensor data through the sensor scan chains.