Patent ID: 11923453
Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. An LDMOS device, comprising:
a semiconductor substrate, a body region and a drift region being formed in the semiconductor substrate, a source region being provided in the body region, a drain region being provided in the drift region, and a gate structure being further provided on the semiconductor substrate;
a first oxide layer provided on a part of the drift region and adjoining the drain region; a barrier layer, comprising n−1 etch stop layers, n being an integer greater than or equal to 2;
wherein when n is greater than 2, the etch stop layers are provided in a stacked manner, an insulating layer is provided between adjacent etch stop layers;
the barrier layer covers both directly on the drift region and directly on the first oxide layer;
the barrier layer has a step, and a plane of the barrier layer directly covered on the drift region is lower than a plane of the barrier layer directly covered on the first oxide layer; and
an interlayer dielectric layer covering the semiconductor substrate;
wherein the LDMOS device further comprises n levels of hole field plates, a first level hole field plate to an (n−1)-th level hole field plate are provided on a first etch stop layer to an (n−1)-th etch stop layer corresponding to the barrier layer directly covered on the drift region respectively, and an n-th level hole field plate is further provided on the ((n−1)-th etch stop layer corresponding to the barrier layer directly covered on the first oxide layer.