Patent ID: 11875844
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. The memory device of claim 11, wherein the level shifter is configured to generate the second internal clock by further adjusting a phase of the first internal clock,
wherein the driver includes a third inverter, and a fourth inverter, the third inverter including a first transistor and a second transistor,
wherein the first transistor includes a first end configured to receive a first voltage, a gate configured to receive the second internal clock, and a second end connected with the second transistor,
wherein the second transistor includes a first end connected with the second end of the first transistor, a gate configured to receive the second internal clock, and a second end connected with a ground terminal through a fourth wire,
wherein the fourth inverter includes an input terminal connected with the second end of the first transistor and an output terminal connected with the first wire and configured to output the first signal,
wherein the fourth wire is identical to the plurality of word lines,
wherein a length of the fourth wire is n % of the length of the one of the plurality of word lines, and
wherein the “n” is a positive integer of 100 or less.