Patent ID: 11922108
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 9:
10. The method of claim 9, wherein
the placing the third set of conductive feature layout patterns between the first set of memory cell layout patterns and the second set of memory cell layout patterns comprises:
placing a third conductive feature layout pattern on a third layout level different from the first layout level and the second layout level, the third conductive feature layout pattern extending in the first direction, and the third conductive feature layout pattern corresponding to fabricating a first portion of the source line coupled to the first set of memory cells and the second set of memory cells; and
placing a fourth conductive feature layout pattern on a fourth layout level different from the first layout level, the second layout level and the third layout level, the fourth conductive feature layout pattern extending in the first direction, and the fourth conductive feature layout pattern corresponding to fabricating a second portion of the source line coupled to the first set of memory cells and the second set of memory cells; and

the generating the layout design of the memory cell array further comprises:
placing a second set of via layout patterns between the third layout level and the fourth layout level, and the second set of via layout patterns corresponding to fabricating vias coupled between the first portion of the source line and the second portion of the source line.