Patent ID: 11895836
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. An integrated circuit (IC), comprising:
a memory device, comprising:
first and second individual source/drain regions disposed in a semiconductor substrate;
a common source/drain region in the semiconductor substrate, laterally spaced between the first and second individual source/drain regions, wherein the common source/drain region is separated from the first individual source/drain region by a first channel region, and wherein the common source/drain region is separated from the second individual source/drain region by a second channel region;
an erase gate electrode over the common source/drain region;
first and second floating gate electrodes respectively over the first and second channel regions;
first and second control gate electrodes respectively overlying the first and second floating gate electrodes; and
a first select gate electrode and a second select gate electrode respectively over the first and second channel regions, and laterally spaced from the common source/drain region respectively by the first and second floating gate electrodes;
an isolation structure extending into a top surface of the semiconductor substrate and laterally separating the memory device from a logic device, the isolation structure comprising dielectric material and having an uppermost surface and a slanted upper surface extending from the uppermost surface to an edge of the isolation structure proximate to the first and second select gate electrodes; and
a dummy select gate structure made of conductive material disposed on the uppermost surface of the isolation structure, wherein an upper surface of the dummy select gate structure and an upper surface of the first select gate electrode have equal heights as measured from the top surface of the semiconductor substrate.