Patent ID: 11961907
Assignee: NXP USA, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A transistor comprising:
a trench formed in a semiconductor substrate;
a substantially vertical conductive spacer formed in the trench, the conductive spacer proximate to a first sidewall of the trench;
a dielectric material formed in the trench, the dielectric material substantially surrounding the conductive spacer;
a drift region formed in the semiconductor substrate adjacent to the first sidewall and a first portion of a second sidewall of the trench, the drift region having a first conductivity type;
a drain region formed in the drift region, the drain region directly adjacent to a second portion of the second sidewall separate from and above the first portion of the second sidewall;
a first gate region overlapping a portion of the drift region, the first gate region separate from the conductive spacer; and
a non-conductive layer formed over the drift region and the dielectric material between the first gate region and the conductive spacer, the non-conductive layer overlapping a top portion of the first gate region.