Patent ID: 11942446
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A semiconductor package comprising:
at least one semiconductor chip stacked on a package substrate; and
an underfill layer interposed between the package substrate and the at least one semiconductor chip, the underfill layer is composed of an insulating resin and fillers;
wherein the package substrate comprises: a first passivation layer including a first recess region extending from an uppermost surface of the first passivation layer to a lowermost surface of the first passivation layer; and a first pad covering a bottom surface and sidewalls of the first recess region, the first pad having a concave top surface,
wherein the at least one semiconductor chip comprises: a conductive bump protruding toward the package substrate; and an inter-metal compound pattern disposed in the first recess region and positioned between sidewalls of the first pad, the inter-metal compound pattern is in direct contact with both the conductive bump and the first pad,
wherein the underfill layer is in direct contact with both the conductive bump and the inter-metal compound pattern and extends within the first recess region, a lowermost surface of the underfill layer extending within the first recess region is positioned below the uppermost surface of the first passivation layer.