Patent ID: 11901038
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 10:
11. A method of executing a link speed change in a memory system, the memory system including a nonvolatile memory, and a controller electrically connected to the nonvolatile memory and including at least an equalizer circuit and a clock-and-data output circuit, said method comprising:
reducing, by the equalizer circuit, an inter-symbol interference jitter of a first data signal received from a host via a serial communication;
outputting the first data signal with the reduced inter-symbol interference jitter from the equalizer circuit as a second data signal;
extracting, by the clock-and-data output circuit, a third data signal and a clock signal from the second data signal;
outputting the third data signal and the clock signal;
executing a process to detect predetermined data in the third data signal based on the first data signal; and
resetting a state of the clock-and-data output circuit when the predetermined data is not detected within a predetermined period of time.