Patent ID: 11887656
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 3:
4. The memory of claim 1, further comprising:
a fourth cell array arranged adjacent to the third cell array, sharing the row lines with the third cell array, and including a plurality of fourth column lines and a plurality of fourth memory cells, each of which is coupled to one row line among the row lines and one column line among the fourth column lines;
a fourth even bit line sense amplifier array positioned on one side of the fourth cell array and suitable for amplifying data of the fourth memory cells corresponding to the selected row line and even fourth column lines among the fourth column lines; and
a fourth odd bit line sense amplifier array positioned on another side of the fourth cell array and suitable for amplifying data of the fourth memory cells corresponding to the selected row line and odd fourth column lines among the fourth column lines.