Patent ID: 11955470
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A semiconductor device comprising:
a first peripheral circuit region comprising a first peripheral circuit substrate, a plurality of lower circuitries, and a plurality of lower conductive lines;
a cell region comprising a cell substrate on the first peripheral circuit region, a plurality of gate lines on the cell substrate, a plurality of conductive pad regions connected to the plurality of gate lines, and a plurality of first bonding metal pads; and
a second peripheral circuit region apart from the first peripheral circuit region with the cell region between the first peripheral circuit and the second peripheral circuit region, such that a lower surface of the cell region is on an upper surface of the first peripheral circuit region and lower surface of the second peripheral circuit region is on an upper surface of the cell region, the second peripheral circuit region comprising (A) a second peripheral circuit substrate, (B) a plurality of upper circuitries, (C) a plurality of upper conductive lines, and (D) a plurality of second bonding metal pads bonded to the plurality of first bonding metal pads,
wherein the plurality of gate lines comprise (A) a first gate line connected to a first lower circuitry selected from the plurality of lower circuitries and (B) a second gate line connected to a first upper circuitry selected from the plurality of upper circuitries.