Patent ID: 11972789
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. The circuit according to claim 7, wherein the comparison sub-circuit comprises a plurality of comparators and an output sub-circuit, wherein the plurality of comparators are in one-to-one correspondence with bits in the decoding information;
each of the plurality of comparators is configured to receive a corresponding bit signal and a corresponding characteristic signal in the decoding information, and output a result signal based on a comparison result between the bit signal and the characteristic signal, wherein a value of the characteristic signal indicates whether a bit having a value of 1 and not lower than corresponding bit of the comparator exists in the historical maximum decoding information; and
the output sub-circuit is configured to determine and output the valid enable signal or the invalid enable signal based on the result signal outputted by each of the plurality of comparators.