Patent ID: 11967398
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A semiconductor device comprising:
a control pulse generation circuit configured to generate a control pulse when a mode control operation is performed;
a mode delay circuit configured to set a mode delay period on the basis of a delay select signal, and generate a mode input control signal by delaying the control pulse by the mode delay period;
a read strobe signal generation circuit configured to generate a read strobe signal on the basis of the control pulse;
a read delay circuit configured to generate a read input control signal by delaying the read strobe signal by a read delay period; and
a read pipe circuit configured to receive mode data on the basis of the mode input control signal, and receive cell data on the basis of the read input control signal.