Patent ID: 11886972
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A non-volatile memory (NVM) crossbar module for an artificial neural network (ANN) accelerator, comprising:
a plurality of digital-to-analog converters (DACs), each DAC configured to receive digital input data and output a respective analog voltage signal;
an NVM crossbar including a plurality of row signal lines coupled to the DACs, a plurality of multiply-and-accumulate (MAC) column signal lines, a correction column signal line, a MAC cell disposed at each intersection of a row signal line and a MAC column signal line, and a correction cell disposed at each intersection of a row signal line and the correction column signal line; and
a plurality of analog-to-digital converters (ADCs),
where each MAC cell includes one or more NVM elements programmed to a conductance level representing one of a plurality of unipolar weights of an ANN, and each correction cell includes one or more NVM elements programmed to a predetermined conductance level,
where each MAC column signal line is configured to generate a MAC signal based on the analog voltage signals and the respective MAC cells, and the correction column signal line is configured to generate a correction signal based on the analog voltage signals and the correction cells, and
where each MAC signal is corrected based on the correction signal.