Patent ID: 11869579
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. A page buffer circuit comprising:
a plurality of page buffers connected to a plurality of bitlines,
wherein each of the plurality of page buffers comprises a bitline selection transistor configured to connect a corresponding bitline of the plurality of bitlines to a sensing node, a precharge circuit configured to precharge the sensing node in response to a load signal, a dynamic latch circuit configured to store data in a storage node, a first sensing node sharing transistor configured to connect the sensing node of each of the plurality of page buffers and the sensing node of a previous page buffer of the plurality of page buffers in response to a sensing node sharing signal, and a second sensing node sharing transistor configured to connect the sensing node of each of the plurality of page buffers and the sensing node of a next page buffer of the plurality of page buffers in response to the sensing node sharing signal,
wherein N page buffers of the plurality of page buffers are configured to connect the sensing nodes of the N page buffers to each other in response to the sensing node sharing signal,
where N is an integer greater than 1,
wherein the N page buffers are configured to perform a first precharge operation that precharges the sensing nodes of the N page buffers in response to the load signal,
wherein one page buffer of the N page buffers is configured to perform a first read operation that stores inverted data that are inverted from the data of the storage node of the one page buffer to the sensing nodes of the N page buffers in response to a read signal,
wherein the one page buffer is configured to perform a first write operation that stores the inverted data of the sensing nodes of the N page buffers to the storage node of the one page buffer in response to a write signal,
wherein the N page buffers are configured to perform a second precharge operation that precharges the sensing nodes of the N page buffers in response to the load signal,
wherein the one page buffer is configured to perform a second read operation that stores the data that are inverted from the inverted data of the storage node of the one page buffer to the sensing nodes of the N page buffers in response to the read signal, and
wherein the one page buffer is configured to perform a second write operation that stores the data of the sensing nodes of the N page buffers to the storage node of the one page buffer in response to the write signal.