Patent ID: 11954037
Assignee: NVIDIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A method comprising:
generating, by a processing device coupled with a cache in a computing system, a plurality of virtual addresses that are sequentially numbered for data that is to be at least one of processed or transferred in response to an input/output (I/O) request;
allocating, for the data, a continuous range of physical addresses of a volatile memory of the computing system, wherein the continuous range of physical addresses is limited to a size of the cache;
generating, by the processing device, a set of hash-based values based on respective physical addresses of the continuous range of physical addresses;
identifying, by the processing device, a unique cache line of the cache that corresponds to each respective hashed-based value of the set of hash-based values; and
causing, by the processing device, the data to be directly stored in the unique cache lines of the cache.