Patent ID: 11928523
Assignee: GRAPHCORE LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. The processing device of claim 1, wherein the circuitry of the external sync controller is configured to:
receive a first at least one sync request from the first set of processors indicating that the first set of processors has reached the first barrier synchronisation;
in response to the first at least one sync request, provide a sync acknowledgment to each of the first set of processors so as to cause each of the first set of processors to enter the first exchange phase, wherein the first sync messages include the first at least one sync request;
receive a second at least one sync request from the second set of processors indicating that the second set of processors has reached the second barrier synchronisation; and
in response to the second at least one sync request, provide a sync acknowledgment to each of the second set of processors so as to cause each of the second set of processors to enter the second exchange phase, wherein the second sync messages include the second at least one sync request.