Patent ID: 11915764
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 21:
22. The memory of claim 21, wherein the array operation is a first array operation, wherein the controller is further configured to perform a second array operation on the array of memory cells different than the first array operation, and wherein the controller is further configured to cause the memory to:
load each value of a third plurality of values to a respective register of a third plurality of registers of the memory, wherein each value of the third plurality of values corresponds to a respective duration for a delay interval for the second array operation; and
further generate the look-up table for determining the delay interval duration for the array operation as a function of the indication of temperature, and for determining a delay interval duration for the second array operation as a function of the indication of temperature, in response to the first plurality of values, the second plurality of values, and the third plurality of values.