Patent ID: 11869826
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A memory module comprising:
a substrate that includes a central portion, an upstream edge, a downstream edge opposite the upstream edge, a first array area between the upstream edge and the central portion, a second array area between the downstream edge and the central portions, and a surface extending from the upstream edge to the downstream edge, wherein:
the surface includes one or more die attach locations in each of the first and second array areas,
the upstream edge is upstream from the central portion with respect to an airflow across the substrate, and
the downstream edge is downstream from the central portion with respect to the airflow across the substrate, and

a first semiconductor die attached to the surface of the substrate in a first die attach location in the first array area; and
a second semiconductor die attached to the surface of the substrate in a second die attach location in the second array area;
wherein a first operating parameter of the first semiconductor die has a first variance between different temperatures and the and a second operating parameter of the second semiconductor die has a second variance between different temperatures that is less than the first variance.