Patent ID: 11955480
Assignee: STMICROELECTRONICS (TOURS) SAS
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A method, comprising:
forming a first trench in a first region of a substrate;
forming a stack of layers on a surface of the first region and in the first trench, the stack of layers including a first conductive layer, a second conductive layer, and a first dielectric layer stacked between the first conductive layer and the second conductive layer, the stack of layers extending on a lateral wall and a bottom of the first trench, the first conductive layer proximate to the lateral wall of the first trench, the second conductive layer laterally on a side of the first dielectric layer opposite to the first conductive layer;
forming a first contact structure in contact with the first conductive layer outside the first trench; and
forming a second contact structure in contact with the second conductive layer outside the first trench;
forming an insulation layer on a second region of the substrate, the stack of layers are on the insulation layer and the insulation layer does not extend on the first region.