Patent ID: 11973122
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 7:
8. A method comprising:
etching a first recess in a first nanostructure and a second nanostructure, the second nanostructure over the first nanostructure, the first recess disposed at a first side of a gate stack, a boundary structure disposed at a second side of the gate stack, the second side opposite the first side;
etching, through the first recess, sidewalls of the first nanostructure to form a sidewall recess of the first nanostructure;
depositing a sidewall spacer layer structure in the sidewall recess and over the gate stack, the sidewall spacer layer structure having a first height on the first side of the gate stack and extending into the first recess, the sidewall spacer layer structure having a second height on the second side of the gate stack and over the boundary structure, the first height being greater than the second height, wherein the sidewall spacer layer structure includes a first sidewall spacer layer adjoined to a second sidewall spacer layer;
doping the first sidewall spacer layer or the second sidewall spacer layer with a first dopant; and
etching the sidewall spacer layer structure to form an inner spacer in the sidewall recess.