Patent ID: 11942955
Assignee: SK HYNIX INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A delay locked loop circuit comprising:
a delay line configured to delay, based on a delay control voltage, a reference clock signal to generate an internal clock signal and a feedback clock signal;
a selection controller configured to provide the internal clock signal and the feedback clock signal respectively as a first selection clock signal and a second selection clock signal when a deterioration enable signal is disabled, and to provide the reference clock signal as the first selection clock signal and the second selection clock signal when the deterioration enable signal is enabled;
a phase detector configured to compare phases of the first selection clock signal and the second selection clock signal to generate an up-signal and a down-signal; and
a charge pump configured to generate the delay control voltage based on the up-signal and the down-signal.