Patent ID: 11943022
Assignee: INTEL CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. The apparatus of claim 1, wherein the processing circuitry is further arranged to:
engage in beamforming using a hybrid beamforming architecture, the hybrid beamforming architecture comprising:
an analog front end (AFE) to which signals from a plurality of antennas is supplied,
an analog-to-digital converter (ADC) that digitizes analog signals,
a beamforming network disposed between the AFE and the ADC, the beamforming network supplied with Nr analog signals to produce NRF beamformed signals,
coarse timing and fractional frequency offset (FFO) circuitry configured to determine coarse timing and a FFO of the NRF beamformed signals,
a plurality of fast Fourier transforms (FFTs) configured to receive a beam controlled output of the coarse timing and FFO circuitry,
a controller disposed between the coarse timing and FFO circuitry and the FFTs and configured to provide feedback to the beamforming network to adjust a beam direction to a neighboring cell having a stronger signals than that of a current cell, and
fine timing and integer frequency offset (IFO) configured to receive an output of the FFTs and to determine fine timing and frequency offset synchronization of neighboring cells.