Patent ID: 11887667
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A memory device comprising:
a vertical pillar of memory cells;
a data line;
a transistor to couple the data line to the vertical pillar of memory cells, the transistor having a channel structure and a gate, the channel structure separated from the gate;
a first portion of the channel structure of the transistor coupled to channel material of the vertical pillar of memory cells and extending vertically from the channel material; and
a segmented portion of the channel structure extending vertically from the first portion, the segmented portion having a fin contacting and extending vertically from the first portion of the channel structure and a non-conductive region contacting and extending vertically from the first portion of the channel structure, the first portion having a border with the non-conductive region, with the border decreasing from the fin to a location below a lowest level of the fin.