Patent ID: 11901189
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 12:
13. A method for forming a semiconductor structure, comprising:
etching a dielectric layer on a substrate to form a plurality of first trenches having a first pattern density in a first region of the substrate and a plurality of second trenches having a second pattern density in a second region of the substrate, the first pattern density being greater than the second pattern density;
applying a spin-on coating (SOC) layer comprising a cross-linkable material on the substrate to fill the plurality of first trenches and the plurality of second trenches, a portion of the SOC layer overlying the plurality of first trenches being thicker than another portion of the SOC layer overlying the plurality of second trenches;
baking the SOC layer at a first temperature ranging from 80° C. to 110° C. under a first atmosphere with an oxygen level greater than 20% to remove a solvent from the SOC layer;
heating the SOC layer to a second temperature ranging from 120° C. to 200° C. under a second atmosphere with an oxygen level less than 5% to reduce a thickness variation of the SOC layer in the first region and the second region, wherein the second temperature is higher than the first temperature, and the thickness variation of the SOC layer is reduced by at least about 50%; and
cross-linking the cross-linkable material at a third temperature ranging from 150° C. to 300° C. under a third atmosphere with an oxygen level greater than 20%, wherein the third temperature is higher than the second temperature.