Patent ID: 11966677
Assignee: SYNOPSYS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A method, comprising:
computing, by one or more processing devices, a time delay for each path of a plurality of paths of a circuit design;
determining, by the one or more processing devices, a commonality score based on a number of segments that are common between the plurality of paths of the circuit design, the commonality score being proportional to the number of segments that are common between the plurality of paths;
determining, by the one or more processing devices, a criticality score based on the time delay for each path of the plurality of paths of the circuit design, the criticality score being proportional to the time delay;
generating, by the one or more processing devices, a graphical representation of the plurality of paths, wherein a first dimension of the graphical representation corresponds to the commonality score and wherein a second dimension of the graphical representation corresponds to the criticality score; and
providing, by the one or more processing devices, the graphical representation of the plurality of paths in a graphical user interface (GUI) to represent the plurality of paths in the circuit design.