Patent ID: 11949020
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. An integrated circuit, comprising:
a substrate having a first transistor embedded therein; and
an interconnection structure disposed on the substrate, comprising;
dielectric layers; and
a second transistor, comprising:
a first gate electrode embedded in one of the dielectric layers;
a first capping layer, a crystalline semiconductor oxide layer, and a second capping layer sequentially disposed over the first gate electrode, wherein a contour of the second capping layer completely overlaps with a contour of the crystalline semiconductor oxide layer from a top view;
a first gate dielectric layer located between the first gate electrode and the first capping layer; and
source/drain contacts disposed on the second capping layer, wherein the crystalline semiconductor oxide layer and the source/drain contacts are located on two opposite sides of the second capping layer.