Patent ID: 11929109
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. A memory system, comprising:
a plurality of memory cells including a first group of memory cells, a second group of memory cells, a third group of memory cells, and a fourth group of memory cells;
a common word line driver configured to apply a common control signal to the plurality of memory cells;
a first sub-word line driver configured to apply a first control signal to the first group of memory cells;
a second sub-word line driver configured to apply a second control signal to the second group of memory cells;
a third sub-word line driver to apply a third control signal to the third group of memory cells; and
a fourth sub-word line driver to apply a fourth control signal to the fourth group of memory cells;
wherein the common word line driver, the first sub-word line driver, the first group of memory cells, the second group of memory cells, the second sub-word line driver, the third sub-word line driver, the third group of memory cells, the fourth group of memory cells, and the fourth sub-word line driver are disposed next to one another in such a sequence along a lateral direction.