Patent ID: 11955960
Assignee: CHIP-GAN POWER SEMICONDUCTOR CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A depletion mode GaN transistor control circuit, comprising:
a current detecting module formed on a silicon wafer and configured to detect a leakage current of a depletion mode GaN transistor formed on a depletion mode GaN wafer; and
a gate voltage adjusting module formed on the silicon wafer and configured to adjust the gate voltage of the depletion mode GaN transistor according to the detected leakage current;
wherein the gate voltage adjusting module comprises both a voltage source configured to provide a fixed voltage to the gate of the depletion mode GaN transistor and a negative voltage converter configured to provide a negative voltage according to the detected current to the gate of the depletion mode GaN transistor, wherein the gate voltage of the depletion mode GaN transistor is modified by the combination of the fixed voltage and the negative voltage.