Patent ID: 11900121
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 18:
19. A method comprising:
predicting instructions for execution using prediction circuitry comprising a plurality of hierarchical prediction units, comprising a lowest level prediction unit and one or more higher level prediction units to, wherein said predicting comprises:
performing respective hierarchical predictions of each of the instructions for execution, wherein predictions higher in the hierarchy have a higher expected accuracy than predictions lower in the hierarchy; and
responsive to a given prediction higher in the hierarchy being different from a corresponding prediction lower in the hierarchy, correcting the corresponding prediction lower in the hierarchy,

determining a prediction correction metric indicative of an incidence of uncorrected predictions performed by the prediction circuitry, the uncorrected predictions being predictions matching predictions of the one or more higher level prediction units; and
fetching instructions for execution, the fetching comprising:
fetching instructions predicted by at least one of said plurality of hierarchical predictions; and
in response to the prediction correction metric indicating an incidence of uncorrected predictions being below a threshold, applying a delay before said fetching.