Patent ID: 11862548
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A semiconductor package, comprising:
a package substrate film including:
a film substrate including an upper surface and a lower surface, the film substrate including a test section, an input section, an output section, and a chip section between the input section and the output section such that the entire test section is between the chip section and one outer edge of the film substrate;

a redistribution pattern including:
an upper redistribution line pattern extending on the upper surface of the film substrate;
a lower redistribution line pattern extending on the lower surface of the film substrate; and
a redistribution via pattern penetrating the film substrate and connecting the upper redistribution line pattern to the lower redistribution line pattern;

a test pattern including:
an upper test line pattern extending on the upper surface of the film substrate;
a lower test line pattern extending on the lower surface of the film substrate;
a first test via pattern penetrating the film substrate and connecting the upper test line pattern to the lower test line pattern;
a second test via pattern penetrating the film substrate at an outer side of the first test via pattern such that the first test via pattern is between the chip section and the second test via pattern, the second test via pattern connecting the upper test line pattern to the lower test line pattern; and
a test pad on the test section of the film substrate and between the first test via pattern and the second test via pattern, the test pad including at least one first test pad at an outer side of the first test via pattern and at least one second test pad at an inner side the second via pattern; and

a semiconductor chip on the chip section of the film substrate.