Patent ID: 11961763
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 0:
1. A device comprising:
a substrate;
a first gate structure wrapping around a channel layer disposed over the substrate;
a second gate structure wrapping around another channel layer disposed over the substrate;
a dielectric fin structure formed over a shallow trench isolation (STI) feature, wherein the dielectric fin structure is between the first gate structure and the second gate structure;
at least one metallization layer on the first gate structure, the dielectric fin structure, and the second gate structure and contiguously extending from the first gate structure to the second gate structure, wherein an upper surface of each of the first gate structure, the second gate structure, and the dielectric fin structure provide a continuous planar surface, the at least one metallization layer interfacing the continuous planar surface.