Patent ID: 11861207
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to:
determine, by the processing device, a first time period for executing an erase suspend operation on the memory device;
execute a portion of an erase operation during the first time period;
responsive to detecting an expiration of a second time period for executing the portion of the erase operation, execute, during the first time period, the erase suspend operation to suspend the erase operation, wherein the second time period is based on a plurality of execution times of erase operations performed on the memory device;
responsive to detecting completion of the erase suspend operation, execute one or more commands during a third time period; and
execute, by the processing device, an erase resume operation to resume the erase operation on the memory device.