Patent ID: 11942181
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. The semiconductor device of claim 8, wherein the second reception circuit comprises:
a second current sourcing circuit configured to regulate, during an activation period of the second clock signal, an amount of current provided to a fifth current path according to the second signal inputted through the third transmission path, and
regulate, during the activation period of the second clock signal, an amount of current provided to a sixth current path according to the reference voltage; and
a second sensing output circuit configured to:
determine, during the activation period of the second clock signal, a logic level of the second intermediate signal by sensing and amplifying a difference between amounts of current flowing through the fifth and sixth current paths, and
initialize a logic level of the second intermediate signal in response to the enable signal.