Patent ID: 11971818
Assignee: CADENCE DESIGN SYSTEMS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 18:
19. A method for generating a memory view file of a non-volatile memory (NVM) module, the method comprising:
parsing, by a memory view generator operating on a computing platform, a Liberty file characterizing the NVM module to provide a port alias for a memory view file identifying ports of the NVM module, wherein the port alias for a set of ports of the NVM module characterizes a type of port in the set of ports;
determining, by the memory view generator a port action for the memory view file identifying ports of the NVM module that are assigned a static value based on the Liberty file;
determining, by the memory view generator, a port access for the memory view file identifying ports of the NVM module that have a dynamic value;
determining, by the memory view generator, an address limit of the memory view file characterizing a number of words in the NVM module;
determining, by the memory view generator, an address partition of the memory view file that characterizes address bits and data bits of the NVM module; and
setting, by the memory view generator a read delay of the NVM module that defines a number of clock cycles needed to hold an address bus stable after a strobe port transitions to an inactive state to enable proper reading of data from the NVM module.