Patent ID: 11935612
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 1:
2. The memory of claim 1, wherein the first reading circuit comprises a plurality of first reading circuit units, each of the first reading circuit units is electrically connected to the first sense amplifier array through the first data line corresponding to the first reading circuit; the first reading circuit unit comprises:
a first input circuit which is electrically connected to the first data line, and is configured to receive the signal on the first data line;
a first reference circuit configured to receive the reference voltage signal;
a first amplification circuit which is electrically connected to each of the first input circuit and the first reference circuit, and is configured to compare the reference voltage signal with the signal on the first data line corresponding to the first reading circuit, and amplify a comparison result; and
a first output circuit which is electrically connected to the first amplification circuit, and is configured to output an amplified comparison result.