Patent ID: 11954061
Assignee: BEIJING TSINGMICRO INTELLIGENT TECHNOLOGY CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 3:
4. The mapping method for the reconfigurable array according to claim 3, wherein S54 is aerformed by a formula (6):, ∑
              
                j
                ∈
                M
              
            
            ⁢
            
              
                support
                
                  op
                  ⁡
                  
                    (
                    j
                    )
                  
                
              
              *
              V
              ⁢
              
                
              
              ⁢
              2
              ⁢
              
                M
                ⁡
                
                  (
                  
                    i
                    ,
                    j
                  
                  )
                
              
            
          
          =
          1
        
        ,
        
          ∀
          
            i
            ∈
            V
          
        
        ,
      
    
    
      
        (
        6
        )
      
    
  

where supportop(j) represents a group of constraint matrices, indicating different types of processing elements, wherein in a constraint matrix indicating one type of processing elements, processing elements of this type are represented by a corresponding value of 1, and other processing elements are represented by 0;
wherein S55 is performed by a formula (7):, ∑
              
                b
                ∈
                L
              
            
            ⁢
            
              E
              ⁢
              2
              ⁢
              
                L
                ⁡
                
                  (
                  
                    a
                    ,
                    b
                  
                  )
                
              
            
          
          ≥
          1
        
        ,
        
          
            ∀
            
              a
              ∈
              E
            
          
          ;
        
      
    
    
      
        (
        7
        )
      
    
  

and
wherein S56 is performed by a formula (8):, ∑
              
                a
                ∈
                E
              
              
                
              
            
            ⁢
            
              
            
            ⁢
            
              E
              ⁢
              
                
              
              ⁢
              2
              ⁢
              
                
              
              ⁢
              
                L
                ⁡
                
                  (
                  
                    a
                    ,
                    
                      
                        ii
                        *
                        L
                        ⁢
                        
                          
                        
                        ⁢
                        _
                        ⁢
                        
                          
                        
                        ⁢
                        num
                      
                      +
                      b
                    
                  
                  )
                
              
            
          
          ≤
          1
        
        ,
        
          ∀
          
            b
            ∈
            
              L
              ⁢
              
                
              
              ⁢
              _
              ⁢
              
                
              
              ⁢
              num
            
          
        
        ,
        
          ∀
          
            ii
            ∈
            II
          
        
        ,
      
    
    
      
        (
        8
        )
      
    
  

where L_num represents a number of the links of the reconfigurable architecture.