Patent ID: 11955532
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An integrated circuit structure, comprising:
an inter-layer dielectric layer having a trench therein, the trench having a sidewall;
a semiconductor substrate having a semiconductor fin protruding therefrom and extending into the trench in the inter-layer dielectric layer;
a trench isolation layer on the semiconductor substrate around a lower portion of the semiconductor fin, wherein an upper portion of the semiconductor fin extends above the trench isolation layer;
a gate dielectric over the upper portion of the semiconductor fin, the gate dielectric having a portion laterally spaced apart from the semiconductor fin and along the sidewall of the trench in the inter-layer dielectric layer;
a conductive layer over the gate dielectric, the conductive layer comprising titanium, nitrogen and oxygen, and a portion of the conductive layer in contact with the portion of the gate dielectric laterally spaced apart from the semiconductor fin;
a P-type metal gate layer over the conductive layer, the P-type metal gate layer having an uppermost surface above an uppermost surface of the conductive layer, and a portion of the P-type metal gate layer in contact with the portion of the gate dielectric laterally spaced apart from the semiconductor fin;
an N-type metal gate layer over the P-type metal gate layer, a portion of the N-type metal gate layer in contact with the portion of the gate dielectric laterally spaced apart from the semiconductor fin; and
a conductive fill over the N-type metal gate layer.