Patent ID: 11961572
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. The memory apparatus as set forth in claim 3, wherein the rows include full circle rows and the semi-circle rows, the particular ones of the rows are both the semi-circle rows and the full circle rows, the plurality of bits includes three bits, total state quantity of the plurality of data states is eight, the plurality of programmed data states includes, in order of the threshold voltage increasing in magnitude, a first data state and a second data state and a third data state and a fourth data state and a fifth data state and a sixth data state and a seventh data state, the highest data state is the seventh data state, and the controller is further configured to:
for the memory cells associated with the plurality of other data word lines and being programmed to one of the first data state and the second data state and the third data state and the fourth data state and the fifth data state and the sixth data state and the seventh data state during the program operation, apply each of a plurality of program pulses to the plurality of other data word lines progressively increasing in magnitude in each of a plurality of loops during the program operation until the memory cells being programmed to the one of the first data state and the second data state and the third data state and the fourth data state and the fifth data state and the sixth data state and the seventh data state respectively reach one of a low first voltage level for the first data state and a low second voltage level for the second data state and a low third voltage level for the third data state and a low fourth voltage level for the fourth data state and a low fifth voltage level for the fifth data state and a low sixth voltage level for the sixth data state and a low seventh voltage level for the seventh data state;
for the memory cells associated with the at least one edge word line and being programmed to one of the first data state and the second data state and the third data state and the fourth data state during the program operation, apply each of the plurality of program pulses to the plurality of other data word lines progressively increasing in magnitude in each of the plurality of loops during the program operation until the memory cells being programmed to the one of the first data state and the second data state and the third data state and the fourth data state respectively reach one of the low first voltage level for the first data state and the low second voltage level for the second data state and the low third voltage level for the third data state and the low fourth voltage level for the fourth data state; and
for the memory cells associated with the at least one edge word line and being programmed to one of the fifth data state and the sixth data state and the seventh data state during the program operation, apply each of the plurality of program pulses to the plurality of other data word lines progressively increasing in magnitude in each of the plurality of loops during the program operation until the memory cells being programmed to the one of the fifth data state and the sixth data state and the seventh data state respectively reach one of a high fifth voltage level for the fifth data state and a high sixth voltage level for the sixth data state and a high seventh voltage level for the seventh data state, the high fifth voltage level being greater in magnitude than the low fifth voltage level and the high sixth voltage level being greater in magnitude than the low sixth voltage level and the high seventh voltage level being greater in magnitude than the low seventh voltage level.