Patent ID: 11915750
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A memory device, comprising:
a plurality of memory cells arranged in at least one array of memory cells, wherein the plurality of memory cells comprises:
a first group of memory cells; and
a second group of memory cells programmed to a predefined logic state of at least two logic states, each logic state corresponding to a respective nominal electric resistance value of the each of the memory cells of the second group; and

a memory controller coupled to the plurality of memory cells and configured to:
set an initial test voltage such that it corresponds to a reading voltage applied to the memory cells of the second group;
bias a corresponding word line to a word line selection voltage lower than the reading voltage;
apply a test voltage to the memory cells of the second group to assess a logic state thereof;
responsive to the logic state of at least one memory cell of the second group assessed with the test voltage being different from the predefined logic state, increase the value of the test voltage; and
responsive to the logic state of all the memory cells of the second group assessed with the test voltage being equal to the predefined logic state, set the recovery voltage according to the test voltage used in the last application of the test voltage to the memory cells of the second group.