Patent ID: 11961572
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 4:
5. The memory apparatus as set forth in claim 3, wherein the rows include full circle rows and the semi-circle rows, the particular ones of the rows are both the semi-circle rows and the full circle rows, and the controller is further configured to:
apply each of a plurality of program pulses to the plurality of other data word lines progressively increasing in magnitude in each of a plurality of loops during the program operation until the memory cells being programmed to the highest data state and associated with the plurality of other data word lines reach a low highest verify voltage level for the highest data state; and
apply each of the plurality of program pulses to the at least one edge word line progressively increasing in magnitude in each of the plurality of loops during the program operation until the memory cells being programmed to the highest data state associated with the at least one edge word line reach a high highest verify voltage level for the highest data state, the high highest verify voltage level being greater in magnitude than the low highest verify voltage level.