Patent ID: 11886340
Assignee: APPLE INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus comprising:
a processor circuit including:
a load-store circuit configured to perform loads of data from and stores of data to one or more memories external to the processor;
one or more buffers configured to store load and store memory requests for transmission to the one or more memories; and
one or more configuration registers configured to store information indicative of a first range of physical addresses of the one or more memories that are reserved for real-time memory requests, wherein addresses in a second, non-overlapping range of physical addresses are shared between real-time and non-real-time memory requests, wherein the configuration registers are further configured to indicate portions of the one or more buffers that are reserved for real-time memory requests;
wherein the processor circuit is configured to tag a particular memory access request as a real-time memory request in response to detecting that a physical address of the particular memory request falls within the first range of physical addresses.