Patent ID: 11973070
Assignee: SJ SEMICONDUCTOR(JIANGYIN) CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 2:
3. The method for making the double-layer stacked 3D fan-out packaging structure according to claim 1,
wherein the first rewiring layer comprises a first wiring dielectric layer and a first metal wiring layer disposed in the first wiring dielectric layer, and wherein the second rewiring layer comprises a second wiring dielectric layer and a second metal wiring layer disposed in the second wiring dielectric layer;
wherein each of a material of the first wiring dielectric layer and a material of the second wiring dielectric layer comprises one or more of epoxy resin, silicone rubber, polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), silicon oxide, phosphorosilicate glass, and fluorine-containing glass; and
wherein each of a material of the first metal wiring layer and a material of the second metal wiring layer comprises one or more of copper, aluminum, nickel, gold, silver, and titanium.