Patent ID: 11901363
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 14:
15. A resistance measuring structure comprising:
a first Complementary Field Effect Transistor (CFET) stack on a substrate, the first CFET stack comprising:
a first upper transistor comprising a first upper drain region; and
a first lower transistor between the substrate and the first upper transistor, the first lower transistor comprising a first lower drain region;

a second CFET stack on the substrate, the second CFET stack comprising:
a second upper transistor comprising a second upper drain region; and
a second lower transistor between the substrate and the second upper transistor, the second lower transistor comprising a second lower drain region; and

a first conductive connection that contacts the substrate, the first upper drain region, the first lower drain region, the second upper drain region, and the second lower drain region.