Patent ID: 11889515
Assignee: APPLE INC.
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. The apparatus of claim 1, wherein the processing circuitry is further configured to align at least one of: a DCI format 3_0 size or a DCI format 3_1 size to a legacy DCI format size according to a fixed size or a configurable size, based on DCI format 0_0, DCI format 0_1, DCI format 0_2, DCI format 1_0, DCI format 1_1, DCI format 1_2, or a maximum number of reserved resources for the NR sidelink communication, wherein, in response to the legacy DCI format size comprising DCI format 0_0 or DCI format 0_1, the processing circuitry is further configured to align the at least one of: the DCI format 3_0 size or the DCI format 3_1 size by zero padding.