Patent ID: 11907545
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 4:
5. The non-volatile memory of claim 1, the control circuit further comprising:
an internal data bus connecting the plurality of sets of internal data latches to the input-output interface,
wherein the plurality of data buffers are first in, first out data buffers (FIFOs) and the input-output interface further includes:
logic circuitry;
multiplexing circuitry,, wherein the control circuit is further configured to:
receive the compressed results of the read operation at the logic circuitry from the internal data bus;
perform the re-ordering of the bits of the compressed results in the logic circuitry; and
perform the replacement of the compressed results of the read operation from defective ones of the regular columns with the corresponding compressed results of the read operation from the spare columns by the multiplexing circuitry from the re-ordered bits of the compressed results of the read operation stored.