Patent ID: 11942552
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 10:
11. A semiconductor device comprising:
a first semiconductor fin and a second semiconductor fin disposed over a semiconductor substrate;
an isolation insulating layer disposed between the first semiconductor fin and the second semiconductor fin;
a wall fin disposed on the isolation insulating layer;
a gate structure disposed over a channel region of the first semiconductor fin and a channel region of the second semiconductor fin;
a first source/drain epitaxial layer disposed over a source/drain region of the first semiconductor fin and a second source/drain epitaxial layer disposed over a source/drain region of the second semiconductor fin; and
a first fin liner layer disposed on a bottom part of the first source/drain epitaxial layer, and a second fin liner layer disposed on a bottom part of the second source/drain epitaxial layer, wherein:
the first source/drain epitaxial layer and the second source/drain epitaxial layer are separated by the wall fin,
the wall fin includes a first dielectric layer, a second dielectric layer disposed over the first dielectric layer and a third dielectric layer,
the first, second and third dielectric layers are made of different materials from each other, and
the third dielectric layer includes a dielectric material having a dielectric constant higher than the first and second dielectric layers and the isolation insulating layer.