Patent ID: 11934268
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A system, comprising:
a memory array; and
a memory sub-system controller coupled to the memory array, the memory sub-system controller configured to:
compare a quantity of bad blocks for at least one of a number of superblocks of the memory array to a bad block criteria; and
check whether a superblock write value for each of the number of superblocks meets a superblock write value criteria, wherein the superblock write value indicates an amount of data written since a last partial superblock was written to; and
in response to the superblock write value meeting the superblock write value criteria for a particular superblock of the number of superblocks, write host data to the particular superblock with the quantity of bad blocks.