Patent ID: 11967550
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A method of forming a semiconductor structure, comprising:
providing a substrate; and
forming an interconnection structure over the substrate, comprising:
forming a first tier of conductive structure in a first dielectric layer, the first tier of conductive structure comprises a first conductive line and a second conductive line, wherein the first conductive line and the second conductive line laterally extend along a first direction and are spaced from each other by the first dielectric layer therebetween;
forming a second dielectric layer over the first dielectric layer;
forming a via trench in the second dielectric layer to expose portions of the first conductive line and the second conductive line and a portion of the first dielectric layer laterally between the portions of the first conductive line and the second conductive line;
forming a conductive via in the via trench;
forming an etching stop layer on the second dielectric layer and forming a third dielectric layer over the second dielectric layer and the conductive via, wherein the etching stop layer separates the second dielectric layer and the third dielectric layer;
forming a conductive line trench in the third dielectric layer and through the etching stop layer to expose the conductive via and a portion of the second dielectric layer; and
forming a second tier of conductive structure over the first tier of conductive structure including forming a third conductive line in the conductive line trench,
wherein the third conductive line is located in the third dielectric layer and extends along a second direction different form the first direction, the conductive via extends vertically between the first conductive line and the third conductive line, and extends vertically between the second conductive line and the third conductive line, wherein the conductive via, in a vertical direction, is overlapped with a portion of the first dielectric layer that is laterally between the first conductive line and the second conductive line, and the conductive via is in direct contact with the first, second, and third conductive lines,

wherein the lateral dimension of the conductive via in the first direction is less than the lateral dimension of the third conductive line in the first direction, and the lateral dimension of the first conductive line in the first direction is larger than the lateral dimension of the third conductive line in the first direction,
wherein the lateral dimension of the third conductive line in the second direction is greater than the lateral dimension of the conductive via in the second direction, and the lateral dimension of the conductive via in the second direction is larger than the lateral dimension of the first conductive line in the second direction.