Patent ID: 11927982
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G  H

Claim 7:
8. An apparatus comprising:
an OR-AND-INVERT gate to receive a first enable and a second enable;
a first inverter coupled to an output of the OR-AND-INVERT gate;
a first NAND gate coupled to the output of the first inverter;
a second NAND gate coupled to the output of the OR-AND-INVERT gate;
a second inverter to provide a clock which is gated based on logic values of the first enable and/or the second enable; and
a third inverter coupled to an output of the first NAND gate, wherein an output of the third inverter is received as input by the OR-AND-INVERT-gate.