Patent ID: 11949391
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. An electronic device, comprising:
a first biasing circuit comprising a PMOS drive transistor for biasing in a subthreshold region, the PMOS drive transistor comprising a PMOS gate and a PMOS drain;
a second biasing circuit comprising an NMOS drive transistor for biasing in the subthreshold region, the NMOS drive transistor comprising an NMOS gate and an NMOS source; and
an input circuit coupled to the PMOS drain; and
an output circuit coupled to the PMOS gate and the NMOS gate,
wherein:
the output circuit comprises at least two boosting stages;
each of the at least two boosting stages comprises at least two matching transistors; and
at least one or more resistive elements connect the at least two boosting stages.