Patent ID: 11948840
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A method, comprising:
forming a structure comprising a plurality of fins within a dielectric material over a substrate, the plurality of fins comprising a first fin, a second fin, a first dummy fin, and a second dummy fin, the first fin and the second fin comprising different materials;
forming isolation regions from the dielectric material between each of the plurality of fins, the first fin and the first dummy fin being separated by a first opening, the second fin and the second dummy fin being separated by a second opening;
expanding the first opening and expanding the second opening;
performing a first reduction of the first opening and the second opening, wherein the first reduction comprises forming a first capping layer over the first fin and a second capping layer over the second fin, wherein a thickness of the first capping layer is lesser than a thickness of the second capping layer;
performing a second reduction of the first opening and the second opening, wherein the second reduction comprises forming a first dielectric layer over the first capping layer, a first dummy dielectric layer over the first dummy fin, a second dielectric layer over the second capping layer, and a second dummy dielectric layer over the second dummy fin, wherein a combined thickness of the first capping layer and the first dielectric layer is greater than a thickness of the first dummy dielectric layer; and
forming gate structures over the first fin and the second fin.