Patent ID: 11899940
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. The apparatus according to claim 4,
wherein the pending load buffer circuitry is arranged to store for each of the load requests buffered in the pending load buffer circuitry a status indicator,
wherein the status indicator for load requests received from the address generation circuitry is initially set to indicate a valid state,
wherein in response to the address proximity condition being satisfied the status indicator corresponding to the set of one or more subsequent load requests is set to indicate an invalid state, and
the coalescing circuitry is responsive to an invalid load request in the pending load buffer circuitry to suppress forwarding of the invalid load request_wherein in response to the tentative proximity condition being satisfied the status indicator for the set of one or more subsequent load requests is set to indicate a hold state,
wherein the coalescing circuitry is responsive to a load request having the hold state in the pending load buffer circuitry to provisionally suppress forwarding of the load request having the hold state, and
wherein in response to the address proximity condition not being satisfied the status indicator corresponding to the set of one or more subsequent load requests is reset to the valid state.