Patent ID: 11947889
Assignee: SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. The chip according to claim 8, wherein:
the chip is used for implementing SHA-256 algorithm;
the rows of the first type of each operation stage include a first row, wherein:
the first row includes a first set of register modules and a first set of logical operation modules, the first set of register modules of the first row including 4 32-bit cache register modules A, B, C and D arranged in the form of an array of 1 row and 4 columns;
the rows of the second type of each operation stage include a second row and a third row, wherein:
the second row includes a third set of register modules and a third set of logical operation modules, the third set of register modules of the second row including 8 16-bit cache register modules E1, E2, F1, F2, G1, G2, H1, H2 arranged in the form of an array of 2 rows and 4 columns, the third row includes a third set of register modules, a third set of logical operation modules and a sixth set of register modules, the third set of register modules of the third row including 8 16-bit extension register modules R0-1, R0-2, R1-1, R1-2, R9-1, R9-2, R14-1 and R14-2 arranged in the form of an array of 2 rows and 4 columns, the sixth set of register modules of the third row including 2 16-bit extension register modules R15-1 and R15-2 arranged in the form of an array of 2 rows and 1 column;
the plurality of rows of each operation stage further include a fourth row including a fourth set of modules, the fourth set of modules of the fourth row including 11 32-bit extension register modules R2, R3, R4, R5, R6, R7, R8, R10, R11, R12, R13 arranged in the form of an array of 1 row and 11 columns;
each 32-bit cache register module is used to store one 32-bit intermediate value, each 32-bit extension register module is used to store one 32-bit extension data, every two adjacent 16-bit cache register modules in the second row that are provided sequentially in the Y-direction are used to collectively store one 32-bit intermediate value, every two adjacent 16-bit extension register modules in the third row that are provided sequentially in the Y-direction are used to collectively store one 32-bit extension data, and the third set of logical operation modules in each of the second and third rows includes 2 logical operation modules adjacent to each other in the Y-direction that are used to collectively process one or more data having a length of 32 bits.