Patent ID: 11880686
Assignee: AMPERE COMPUTING LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A device comprising:
a system bus;
a link interface circuit coupled to an external link;
a conversion circuit coupled to the system bus and to the link interface circuit, the conversion circuit configured to, in response to receiving a write instruction, at least one first cache line, and metadata associated with the at least one first cache line on the system bus, provide a flow control unit (FLIT) to the link interface circuit for transmission on the external link, the FLIT comprising:
a first header slot comprising write information based on the write instruction for writing the at least one first cache line to an external memory coupled to the external link;
a first metadata slot comprising the metadata; and
at least two generic slots, each comprising a cache line chunk, each cache line chunk comprising bytes of a cache line.