Patent ID: 11899242
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A method comprising;
forming an optical feature on a first integrated circuit die;
forming an interconnect structure overlying the first integrated circuit die, the interconnect structure including a plurality of stacked materials, wherein the interconnect structure imposes a first degree of optical interference on a light path extending to the optical feature;
removing a portion of the interconnect structure to thereby form a gap in the interconnect structure overlying the optical feature; and
filling the gap with a first bonding dielectric layer, the first bonding dielectric layer imposing a second degree of optical interference on the light path that is less than the first degree of optical interference, and
fusion bonding the first bonding dielectric layer to a second bonding dielectric layer, the second bonding dielectric layer being a topmost layer of a second integrated circuit die.