Patent ID: 11886848
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 3:
4. The method of claim 2 wherein the reconciling, by the binary translator using the compiler-produced metadata, original compiler-produced aliasing information with how lower-level machine instructions access the memory locations described by the aliasing information according to predetermined criteria, further comprising:
in response to receiving the descriptive binary data further comprising aliasing information applicable to the original IR and information including annotation/tracking of each original machine instruction that references memory, creating by the binary translator, aliasing information for memory references by combining analysis of the machine instructions in the raw binary code with original aliasing information in the descriptive binary data;
in response to a determination a memory reference on an original machine instruction being processed by the binary translator is at least one same as, and a part of, a reference in the descriptive binary data aliasing information based on the original IR, duplicating aliasing information in an alias graph, of the descriptive binary data, for a corresponding reference in the IR;
in response to a determination a memory reference consists of multiple references that are present in the descriptive binary data aliasing information, computing a union of aliases of all references in descriptive binary data aliasing information corresponding to this single memory location; and
in response to a determination the memory reference does not have a corresponding reference in the IR, creating the aliasing information that the memory reference is aliased with all other memory references, refined later by analyzing at least one of a data area and an offset of the memory reference in the raw binary code and comparing with other references in the descriptive binary data aliasing information.