Patent ID: 11862547
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An assembly, comprising:
a substrate having a first interconnect and a second interconnect, wherein the first interconnect has a first conductive pad and a second conductive pad, and wherein the second interconnect has a third conductive pad and a fourth conductive pad; and
a socket over the substrate, wherein the socket has a first pin, a second pin, and a base layer, wherein the base layer includes a first pad and a second pad, wherein the first pin is vertically over the first interconnect, wherein the second pin is vertically over the second interconnect, wherein the first pad is directly coupled to the first pin and the fourth conductive pad of the second interconnect, and wherein the second pad is directly coupled to the second pin and the second conductive pad of the first interconnect.