Patent ID: 11963397
Assignee: HEFEI BOE JOINT TECHNOLOGY CO., LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 18:
19. A method for manufacturing a display panel, comprising forming a plurality of display circuitries on a substrate, wherein each display circuitry comprises a display region and a transparent region, the display region comprises a plurality of pixel driving circuitry setting regions arranged sequentially in a first direction, and each pixel driving circuitry setting region extends in a second direction intersecting the first direction, wherein each display circuitry comprises a plurality of subpixels in one-to-one correspondence with the pixel driving circuitry setting regions, each subpixel comprises a subpixel driving circuitry and a light-emitting element coupled to each other, the subpixel driving circuitry is located in a corresponding pixel driving circuitry setting region, the light-emitting element is located at a side of the subpixel driving circuitry away from the substrate, a width of the light-emitting element is greater than a width of the corresponding pixel driving circuitry setting region in the first direction, and a length of the light-emitting element is smaller than a length of the corresponding pixel driving circuitry setting region in the second direction;
wherein each display circuitry comprises: a first scanning line, at least a part of which extends in the first direction; a second scanning line, at least a part of which extends in the first direction; a sensing signal line, at least a part of which extends in the second direction; and a first power source signal line, at least a part of which extends in the second direction; each subpixel further comprises a data line, at least a part of which extends in the second direction;
the subpixel driving circuitry comprises a first transistor, a second transistor, a third transistor and a storage capacitor;
a gate electrode of the first transistor is coupled to the first scanning line, a first electrode of the first transistor is coupled to the data line, and a second electrode of the first transistor is coupled to a gate electrode of the second transistor;
a first electrode of the second transistor is coupled to the first power source signal line, and a second electrode of the second transistor is coupled to an anode of a light-emitting element;
a gate electrode of the third transistor is coupled to the second scanning line, a first electrode of the third transistor is coupled to the sensing signal line, and a second electrode of the third transistor is coupled to the anode of the light-emitting element; and
a first electrode plate of the storage capacitor is coupled to the gate electrode of the second transistor, and a second electrode plate of the storage capacitor is coupled to the second electrode of the second transistor.