Patent ID: 11967575
Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 17:
18. An apparatus, comprising:
a first bonding area of a wafer or die, the first bonding area configured for direct bonding and including a dielectric material;
a second bonding area of the wafer or die, the second bonding area surrounding the first bonding area, including the dielectric material, and configured for direct bonding;
a first recessed non-bonding area at least substantially surrounding the first bonding area, the first recessed non-bonding area comprising at least one etched recess bounded by the dielectric material and separating the first bonding area from the second bonding area; and
a second recessed non-bonding area disposed along an entire outer perimeter of the wafer or die, surrounding the second bonding area.