Patent ID: 11882723
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 16:
17. The display substrate according to claim 16, wherein the source-drain pattern comprises a source, a drain, and a signal trace, the gate pattern comprises a gate, the thin film transistor further comprises a target insulating layer and a capacitor plate located between the gate and the interlayer dielectric layer, and an orthographic projection of the capacitor plate onto the base substrate overlaps with an orthographic projection of the gate onto the base substrate;
the source and the drain are respectively connected with the active layer through via holes in the interlayer dielectric layer, the target insulating layer, and the gate insulating layer; and
the signal trace comprises a first signal line and a second signal line insulated from each other, the first signal line is connected with the capacitor plate through a via hole in the interlayer dielectric layer, and the second signal line is connected with the gate through via holes in the interlayer dielectric layer and the target insulating layer.