Patent ID: 11929030
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A display panel, comprising:
a base substrate comprising a display region and a non-display region; wherein
the display region comprises:
a plurality of subpixels arranged in a matrix along a plurality of rows and a plurality of columns;
a plurality of driving lines, wherein one row of the subpixels is correspondingly and electrically connected to at least one of the driving lines; and
a plurality of data lines wherein one column of the subpixels is correspondingly and electrically connected to at least one of data lines; and
the non-display region comprises:
a gate driving circuit comprising: a plurality of clock signal lines, and a plurality of shift register units sequentially arranged in an extension direction of the clock signal lines, wherein the plurality of clock signal lines are divided into a plurality of clock signal line groups;
the plurality of shift register units are divided into a plurality of register unit groups, wherein all shift register units in a same register unit group are cascaded, two shift register units adjacent in the extension direction of the clock signal lines are located in different register unit groups, and the different register unit groups correspond to different clock signal line groups; and
each of the shift register units comprises an input transistor and an output transistor, wherein a gate of the input transistor is electrically connected to one clock signal line in a corresponding clock signal line group, a first pole of the input transistor is electrically to an input signal end, and a second pole of the input transistor is electrically connected to a gate of the output transistor; and a second pole of the output transistor is correspondingly and electrically connected to at least one driving line;
wherein the display panel further comprises:
a semiconductor layer located on the base substrate, and comprising active layers of the input transistor and the output transistor, wherein each of the active layers comprises a source region, a drain region, and a channel region between the source region and the drain region;
a gate insulating layer on one side facing away from the base substrate, of the semiconductor layer;
a first conductive layer on one side facing away from the base substrate, of the gate insulating layer, and comprising the plurality of driving lines, a plurality of first connection lines, a plurality of second connection lines, the gate of the input transistor and the gate of the output transistor, wherein one of the shift register units corresponds to at least one of the first connection lines and at least one of the second connection lines;
a first insulating layer on one side facing away from the base substrate, of the first conductive layer;
a second conductive layer on one side facing away from the base substrate, of the first insulating layer, and comprising the plurality of clock signal lines, wherein a first transfer part is electrically connected to the source region of the active layer of the output transistor; and the second conductive layer further comprises: a first power line, wherein
for one shift register unit and the clock signal line group corresponding to the shift register unit, one end of the first connection line is directly electrically connected to the gate of the input transistor in the shift register unit, the other end of the first connection line is electrically connected to one clock signal line in the clock signal line group through a first via hole, one end of the second connection line is electrically connected to the first transfer part through a second via hole; and
the first via hole and the second via hole are formed at intervals.