Patent ID: 11870441
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: nan (nan)
Classification: CPC nan | IPC G  H

Claim 16:
17. A method of operating a circuit, the method comprising:
disabling a clock gating circuit in response to at least a first enable signal or a second enable signal, wherein disabling the clock gating circuit comprises:
generating a first control signal;
enabling, by a transmission gate, a first path between a first node and a second node in response to at least an inverted clock input signal or an output clock signal;
disabling, by a first transistor, a second path between a third node and a fourth node in response to a second control signal;
enabling, by at least a second transistor, a third path between the second node and the third node in response to at least the second control signal; and
setting, by a third transistor, the output clock signal in response to at least the second control signal; and

outputting, by the fourth node, the output clock signal in response to at least the first enable signal, or the second control signal,
wherein a clock input signal does not correspond to the output clock signal.