Patent ID: 11907066
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
executing a first parity generation operation based on a set of multiple planes of host data to generate a set of multi-page parity data associated with a memory device;
storing the set of multi-page parity data in a cache memory of the memory device;
executing a second parity generation operation based on multiple sub-blocks of the host data to generate multi-plane multi-sub-block parity data; and
in response to a multi-plane failure, performing, by a processing device, a data recovery operation based on the set of multi-page parity data and of the multi-plane multi-sub-block parity data associated with the host data.