Patent ID: 11955549
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A manufacturing method of a semiconductor device, comprising:
forming a device layer over a substrate;
forming a first dielectric layer over the device layer;
forming a channel layer and a high-k dielectric layer sequentially on the first dielectric layer;
patterning the channel layer and the high-k dielectric layer to form a channel pattern and a high-k dielectric pattern sequentially on the first dielectric layer;
forming a second dielectric layer over the channel pattern and the high-k dielectric pattern;
patterning the second dielectric layer to form a gate trench;
patterning the second dielectric layer and the high-k dielectric pattern to form two contact openings;
forming a metal layer filling the gate trench and the contact openings to form a gate pattern and two contacts at two side of the gate pattern, wherein the high-k dielectric pattern is in contact with inner facing sidewalls of the contacts but separate from outer sidewalls of the contacts; and
forming a ferroelectric tunnel junction electrically connected to one of the contacts,
wherein the ferroelectric tunnel junction comprises a layered structure comprising crystalline oxide layers and ferroelectric layers alternately stacked, and two adjacent crystalline oxide layer and ferroelectric layer are in direct contact with each other.