Patent ID: 11908534
Assignee: FUJITSU LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. A semiconductor device control method for detecting abnormality of a plurality of built-in memories in the semiconductor device, the method comprising:
in each of the built-in memories,
connecting a selected memory cell, among a plurality of memory cells in the built-in memory, to an outside through a selector circuit;
transmitting, when a fault has occurred in one of the memory cells, a relief signal configured to connect a normal memory cell to the outside without connecting the one of the memory cells in which the fault has occurred to the outside, from a memory cell relief circuit to the selector circuit; and
performing abnormality detection for the memory cell relief circuit, based on a temporal change in the relief signal output from the memory cell relief circuit during an operation, other than testing, of the built-in memories.