Patent ID: 11967379
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device comprising:
a memory cell array including a memory cell;
a plurality of bit lines connected to the memory cell array;
a plurality of sense amplifier units each respectively connected to a respective one of the bit lines of the plurality of bit lines connected to the memory cell array; and
a controller configured to perform a write operation to a memory cell of the memory cell array, wherein
the memory cell array includes a first storage region specified by a first address,
the sense amplifier units include a buffer region capable of storing data, the buffer region includes a first portion and a second portion,
when receiving a first command set including a first command specifying the write operation to write first data to one or more memory cells of the memory cell array, the first address of the first storage region, and the first data, the controller is configured to:
store the first data to the first portion of the buffer region;
write the first data stored in the first portion of the buffer region of the plurality of sense amplifier units to the first storage region of the memory cell array;
read, after the first data is written to the first storage region of the memory cell array, second data from the first storage region of the memory cell array;
compare the first data stored in the first portion of the buffer region and the second data read from the first storage region of the memory cell array, and
wherein the writing the first data stored in the first portion of the buffer region to the first storage region of the memory cell array comprises executing a plurality of program loops each comprising a program operation and a verify operation, wherein, in each of the program loops,
the controller is configured to:
apply a program voltage to a word line connected to memory cells of the memory cell array during the program operation; and
apply a verify voltage to the word line connected to the memory cells of the memory cell array during the verify operation.