Patent ID: 11900503
Assignee: IMAGINATION TECHNOLOGIES LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A graphics processing unit comprising a plurality of cores, wherein one of the plurality of cores comprises a master unit configured to:
receive a set of geometry processing tasks comprising:
an indication of a set of elements in an element buffer, and
topology information, wherein the topology information defines the semantics of the element buffer;

group the elements in the element buffer into primitives based on the topology information;
split the set of geometry processing tasks into at least a first trigger and a second trigger, wherein the first trigger comprises an indication of a first starting primitive in the element buffer and an instruction to render a first number of primitives starting from the first starting primitive, and the second trigger comprises an indication of a second starting primitive in the element buffer and an instruction to render a second number of primitives starting from the second starting primitive;
assign the first trigger to a first core of the plurality of cores;
assign the second trigger to a second core of the plurality of cores;
send the first trigger to the first core; and
send the second trigger to the second core.