Patent ID: 11968820
Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 5:
6. A semiconductor device comprising:
a driver circuit comprising a plurality of transistors using a silicon substrate for a channel; and
an element layer in which a plurality of transistor layers are stacked,
wherein the element layer comprises a first transistor layer to a third transistor layer each comprising a plurality of transistors using a metal oxide for a channel,
wherein the first transistor layer comprises a first memory cell comprising a first transistor and a first capacitor,
wherein the second transistor layer comprises a second memory cell comprising a second transistor and a second capacitor,
wherein the third transistor layer comprises a switching circuit and an amplifier circuit,
wherein the first transistor is electrically connected to a first local bit line,
wherein the second transistor is electrically connected to a second local bit line,
wherein the switching circuit is configured to select the first local bit line or the second local bit line and electrically connect the selected local bit line to the amplifier circuit,
wherein the element layer is stacked over the silicon substrate, and
wherein the third transistor layer is provided between the first transistor layer and the second transistor layer.