Patent ID: 11894462
Assignee: ADEIA SEMICONDUCTOR SOLUTIONS LLC
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A method comprising:
providing a substrate having thereon a first region comprising a layer of first epitaxial channel material and a second region comprising a layer of second epitaxial channel material;
patterning a hardmask above the first and second regions;
performing a first etch, using the hardmask as a mask, to form an upper portion of a first fin comprising the layer of first epitaxial channel material and an upper portion of a second fin comprising the layer of second epitaxial channel material;
forming a liner over exposed surfaces of the upper portions of the first and second fins;
performing a second etch, using the liner as a mask, to form a lower portion of the first fin and a lower portion of the second fin;
subsequent to performing the second etch, filling a gap between the first and second fins with a dielectric material;
recessing the dielectric material to a level below the upper surfaces of the first and second fins; and
removing the liner,
subsequent to removing the liner, forming a gate dielectric on exposed surfaces of the upper portions of the first and second fins, wherein the gate dielectric extends beyond bottom surfaces of the layers of first and second epitaxial channel materials.