Patent ID: 11862222
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 2:
3. The refresh circuit according to claim 2, wherein the counting subunit comprises an asynchronous binary addition counter composed of a plurality of D flip-flops connected in series, the regulating subunit comprises an OR gate and a plurality of AND gates, at least one input terminal of the AND gate is connected to a counting terminal of the asynchronous binary addition counter, an output terminal of the AND gate is connected to an input terminal of the OR gate, and an output terminal of the OR gate acts as an output terminal of the regulating subunit;
all input terminals of at least one of the AND gates are connected to the counting terminal, and when a level of the counting terminal represents a default value, at least one of the AND gates outputs a high level; and
one input terminal of at least another one of the AND gates receives the temperature signal, and when the level of the counting terminal represents a first value, at least another one of the AND gates outputs a high level, the first value being less than the default value.