Patent ID: 11916150
Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 1:
2. A semiconductor device comprising:
a first scan line driver circuit configured to scan wirings in odd-numbered rows;
a second scan line driver circuit configured to scan wirings in even-numbered rows; and
a pixel portion provided between the first scan line driver circuit and the second scan line driver circuit, the pixel portion comprising a plurality of pixels,
wherein each of the plurality of pixels comprises a liquid crystal element,
wherein at least one of the first scan line driver circuit and the second scan line driver circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor,
wherein one of a source and a drain of the first transistor is electrically connected to a first wiring for inputting a clock signal,
wherein the other of the source and the drain of the first transistor is electrically connected to the pixel through a second wiring for outputting an output signal,
wherein one of a source and a drain of the second transistor is electrically connected to the second wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to a first power supply line,
wherein one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to a first signal line,
wherein one of a source and a drain of the fourth transistor is electrically connected to the gate of the first transistor,
wherein the other of the source and the drain of the fourth transistor is electrically connected to a second signal line,
wherein one of a source and a drain of the fifth transistor is electrically connected to the gate of the first transistor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the first power supply line,
wherein a gate of the fifth transistor is electrically connected to a gate of the second transistor,
wherein one of a source and a drain of the sixth transistor is electrically connected to the gate of the second transistor,
wherein the other of the source and the drain of the sixth transistor is electrically connected to the first power supply line,
wherein one of a source and a drain of the seventh transistor is electrically connected to the gate of the second transistor,
wherein the other of the source and the drain of the seventh transistor is electrically connected to a second power supply line,
wherein a gate of the seventh transistor is electrically connected to one of a source and a drain of the eighth transistor and one of a source and a drain of the ninth transistor,
wherein one of a source and a drain of the tenth transistor is electrically connected to the gate of the second transistor,
wherein the other of the source and the drain of the tenth transistor is electrically connected to the first power supply line,
wherein a gate of the tenth transistor is electrically connected to the gate of the first transistor,
wherein a potential of the first power supply line is lower than a potential of the second power supply line, and
wherein a channel width of the first transistor is larger than a channel width of each of the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, and the tenth transistor.