Patent ID: 11863222
Assignee: CISCO TECHNOLOGY, INC.
Field: Telecommunications (Electrical engineering)
Classification: CPC H | IPC H

Claim 18:
19. The apparatus of claim 17, wherein each of the plurality of sub-rate receiver lanes includes one or more decision slicer circuits configured to apply a corresponding slicer threshold of one or more slicer thresholds in generating the digital sub-rate receiver data, wherein a number of first DACs is equal to a number of the one or more slicer thresholds, and a number of the one or more second DACs for each of the plurality of sub-rate receiver lanes is equal to the number of the one or more slicer thresholds, wherein the logic circuit is further configured to generate an average slicer threshold control for each of the one or more first DACs and a mismatch slicer threshold control for each of the one or more second DACs in each of the plurality of sub-rate receiver lanes.