Patent ID: 11923357
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A three-dimensional integrated circuit, comprising:
a first device layer;
a first structure disposed over the first device layer, wherein the first structure comprises:
a first dielectric layer;
a first conductive feature disposed in the first dielectric layer;
a first cap layer disposed on the first conductive feature, wherein the first conductive feature is different from the first cap layer; and
a first thermal conductive layer disposed directly on the first dielectric layer, wherein the first thermal conductive layer comprises diamond-like carbon or graphene oxide, and a maximum thickness of the first cap layer is substantially the same as a maximum thickness of the first thermal conductive layer;

a second structure disposed on the first structure, wherein the second structure comprises:
a second thermal conductive layer disposed over the first thermal conductive layer;
a second dielectric layer disposed on the second thermal conductive layer;
a second conductive feature disposed in the second dielectric layer, wherein the second conductive feature is disposed over a portion of the first conductive feature and a portion of the first thermal conductive layer; and
a second cap layer disposed between the second conductive feature and the first cap layer, wherein the second conductive feature is different from the second cap layer; and

a second device layer disposed over the second structure.