Patent ID: 11908916
Assignee: SK HYNIX SYSTEM IC INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of fabricating a high voltage semiconductor device, the method comprising:
forming a gate pattern over a first region and a second region of a semiconductor region having a first conductivity type, wherein the gate pattern has a stepped surface profile over a boundary region between the first and second regions;
forming a planarized ion implantation buffer layer covering the gate pattern, wherein a thickness of the planarized ion implantation buffer layer over the first region is different from a thickness of the planarized ion implantation buffer layer over the second region; and
implanting impurity ions into the gate pattern using the planarized ion implantation buffer layer as a screen layer to form a gate electrode, and
wherein forming the planarized ion implantation buffer layer includes:
forming an ion implantation buffer layer covering the gate pattern, wherein the ion implantation buffer layer has a stepped surface profile over a boundary region between the first and second regions; and
planarizing the ion implantation buffer layer.