Patent ID: 11956127
Assignee: ARTERIS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 8:
9. A computer-implemented method for generation of an updated topology, the method comprising:
receiving an initial Network-on-Chip (NoC) topology that satisfies and is based on initial requirements, wherein the initial NoC topology includes elements and connections;
receiving an update to the initial requirements, wherein the update results in updated requirements;
making incremental modifications to a portion of the initial NoC topology that is impacted by the updated requirements in order to satisfy the updated requirements and generate an incremental updated NoC topology, each incremental modification is in response to the update and changes existing components in the initial NoC topology, which becomes outdated and results in at least one of an unnecessary element and an unnecessary connection, and preserves names of the existing components in the initial NoC topology;
removing at least one of the unnecessary element and the unnecessary connection;
generating an updated NoC topology that combines the initial NoC topology with the incremental updated NoC topology that satisfies the update; and
generating a computer readable format of the updated NoC topology thereby minimizing delays and costs resulting from topology modifications.