Patent ID: 11868870
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. A multi-bit neuromorphic operation method, the method comprising:
determining, as a first input, an i-th bit of an n-bit axon to be sequentially assigned to a single axon circuit for each time period of different time periods;
determining, as a second input, a j-th bit of an m-bit synaptic weight to be assigned to a single synaptic circuit for each of the different time periods;
receiving the determined first input from the single axon circuit;
storing the determined second input in the single synaptic circuit and outputting a synaptic operation value as a function between the first input and the second input; and
obtaining, by a single neuron circuit, each bit value of a multi-bit neuromorphic operation result between the n-bit axon and the m-bit synaptic weight, based on the output synaptic operation value,
wherein the first input and the second input are determined for the different time periods until the multi-bit neuromorphic operation result is obtained sequentially from a lower bit value to an upper bit value,
wherein n and m are each a natural number, i is a natural number between 1 and n, and j is a natural number between 1 and m, and
wherein the controller is further configured to determine the first input and the second input that are to be assigned at each time period such that bits indicating the multi-bit neuromorphic operation result are sequentially obtained by the single neuron circuit from a value of a least significant bit (LSB) to a value of a most significant bit (MSB).