Patent ID: 11942860
Assignee: MURATA MANUFACTURING CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 5:
6. A gate driver circuit for regulating an ON resistance, RON, of a power FET in a power converter circuit, the gate driver circuit including:
(a) a current source coupled between a first voltage source and a node;
(b) a voltage regulator coupled to the node and configured to provide a voltage at the node;
(c) a voltage control circuit including a first selectable configuration electrically disconnected from the node, and a second selectable configuration electrically coupled to the node, wherein the voltage at the node when the voltage control circuit is in the first selectable configuration is higher than in the second selectable configuration; and
(d) driving circuitry, coupled between the node and the gate of the power FET, for applying at least two selectable voltages to the gate of the power FET such that the RON of the power FET is lower when the voltage control circuit is in the first selectable configuration than when the voltage control circuit is in the second selectable configuration.