Patent ID: 11876078
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A method for fabricating a TSV interconnection structure, comprising:
providing a plurality of upper substrate structures, and forming a plurality of TSVs in each of the plurality of upper substrate structures;
forming connecting wires in the plurality of TSVs;
sequentially bonding the plurality of upper substrate structures, wherein the plurality of upper substrate structures is displaced from adjacent upper substrate structures, at least some of the connecting wires of each upper substrate structure are connected to corresponding connecting wires of the adjacent upper substrate structures, and corresponding circuits on the plurality of upper substrate structures are connected;
providing a bottom substrate structure, wherein the plurality of upper substrate structures are disposed on the bottom substrate structure and connected with a circuit on the bottom substrate structure, and
forming a plurality of contacts formed in the plurality of upper substrate structures and the bottom substrate structure, and the contacts connected with the connecting wires,
wherein at least one of the contacts in each of the plurality of upper substrate structures and the bottom substrate structure is not connected with the connecting wires.