Patent ID: 11875750
Assignee: HEFEI BOE JOINT TECHNOLOGY CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. The array substrate according to claim 10, wherein orthographic projections of the plurality of shift registers on the substrate are respectively located in N rows of shift register regions, orthographic projections of the first group of shift registers on the substrate are located in X rows of shift register regions, and orthographic projections of the second group of shift registers on the substrate are located in (N−X) rows of shift register regions;
the second portion of the first branch transmission section passes through the X rows of shift register regions;
the first portion of the second branch transmission section passes through the X rows of shift register regions; and
the second portion of the second branch transmission section passes through the (N−X) rows of shift register regions, and X and N satisfy that:

X·C1=(N−X)C1+X·C2;

wherein X and N are both positive integers, and X is less than N;
C1 is a resistance-capacitance delay generated on a branch transmission section when the branch transmission section passes through a row of pixel region and a row of shift register region and is connected to a shift register; and
C2 is a resistance-capacitance delay generated on the branch transmission section when the branch transmission section passes through the row of pixel region and the row of shift register region.