Patent ID: 11906332
Assignee: STMICROELECTRONICS (ROUSSET) SAS
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 11:
12. A system, comprising:
an integrated circuit, including:
a first substrate; and
a first MOS transistor having a first polysilicon region electrically isolated from the first substrate and including a gate region, a second polysilicon region electrically isolated from the first polysilicon region and from the first substrate, said second polysilicon region including a source region, a substrate region and a drain region of said first MOS transistor, wherein the first polysilicon region is located between an area of the first substrate and the second polysilicon region;
wherein the first MOS transistor is a PMOS transistor; and
wherein the source region the first MOS transistor connected to ground and wherein the first MOS transistor has a threshold voltage such that it is in an on state in response to a zero voltage is applied to the gate region and in an off state in in response to a negative bias applied to the gate region.