Patent ID: 11869775
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A semiconductor package comprising:
a redistribution substrate;
a wafer level package on the redistribution substrate;
a molding layer on the redistribution substrate and covering the wafer level package;
an upper redistribution layer on the molding layer;
a conductive structure that vertically extends from the redistribution substrate toward the upper redistribution layer; and
an upper package on the upper redistribution layer,
wherein the wafer level package comprises a semiconductor chip and an external connection member between the semiconductor chip and the redistribution substrate,
wherein the semiconductor chip includes a substrate, a front-end-of-line structure on the substrate, and a back-end-of-line structure on the front-end-of-line structure,
wherein the back-end-of-line structure includes:
a plurality of metal layers stacked on the front-end-of-line structure, an uppermost metal layer of the metal layers including a pad therein;
a redistribution line on the pad, the redistribution line being configured to electrically connect the pad and the external connection member; and
a first dielectric layer between the uppermost metal layer and the redistribution line,

wherein the external connection member includes an under-bump pattern electrically connected to the redistribution line,
wherein the redistribution line includes a first recess in an upper portion thereof, and
wherein a lower portion of the under-bump pattern is in the first recess.