Patent ID: 11962568
Assignee: AT&T INTELLECTUAL PROPERTY I, L.P.
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A system, comprising:
a processor; and
a memory that stores executable instructions which, when executed by the processor of the system, facilitate performance of operations, the operations comprising:
creating a hierarchical structure of nodes from a specified origin internet address block to a specified lower level of internet address blocks of the specified origin internet address block that is lower than a level associated with the specified origin internet address block;
for each node in the hierarchical structure of nodes, where the node comprises at least one internet address, of an internet address block associated with the node, that is assigned to at least one respective device:
marking the node as unavailable,
in response to determining that an origin node of the hierarchical structure of nodes associated with the specified origin internet address block is not marked as unavailable, marking the origin node as unavailable,
marking all nodes in a path between the origin node and the node as unavailable, and
marking any nodes in the hierarchical structure of nodes that are descendants of the node as unavailable;

determining a count of available internet address blocks of the hierarchical structure of nodes that are not assigned to any devices based on nodes below the origin node that are not marked as unavailable; and
displaying, via a display device, a user interface comprising the count of available internet address blocks.