Patent ID: 11875150
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 14:
15. A system, comprising:
a multi-user network comprising a pool of shared computing resources;
a computing node configured to access the multi-user network; and
circuitry couplable to the pool of shared computing resources, wherein the circuitry is to:
receive a request from the computing node to perform an arithmetic operation or a logical operation, or both, using at least one operand;
receive a parameter from the computing node corresponding to performance of the operation using the at least one operand, the parameter comprising a bit string length and an exponent bit length for the first operand;

set the bit string length and the exponent bit length for the at least one operand based on the parameter prior to performance of the arithmetic operation or the logical operation, or both; and
cause, based, at least in part, on the request and the received parameter, performance of the arithmetic operation or the logical operation, or both, using the pool of shared computing resources.