Patent ID: 11879936
Assignee: AMPERE COMPUTING LLC
Field: Measurement (Instruments)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus for measuring jitter of a clock under test having a frequency, the apparatus comprising:
a delay line comprising a plurality of fixed-delay elements connected in series to a delay line input;
a clock divider circuit for providing, to the delay line input, the clock under test with the frequency divided by two;
an adjustable delay circuit that provides a latch signal comprising the clock under test, delayed according to a programmed delay;
a first plurality of clocked latches that use the latch signal to substantially simultaneously latch outputs of each of at least a subset of the plurality of fixed-delay elements;
an edge detector circuit that detects a location in a time domain of a transition of the clock under test based on the outputs of the first plurality of clocked latches and indicates the location in the time domain of the transition of the clock under test by setting a corresponding one of a plurality of edge detector output signals to an active state and setting the other of the plurality of edge detector output signals to an inactive state; and
a second plurality of latches for latching the plurality of edge detector output signals, each latch being set when the corresponding one of the plurality of edge detector output signals goes to the active state.