Patent ID: 11862234
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. The memory system of claim 1, wherein the first data line driver circuit includes a first reference voltage generator configured to the first reference voltage set including a first upper reference voltage and a first lower reference voltage that are concurrently output,
wherein the first reference voltage generator includes:
an adder circuit configured to add the first code and the second code to generate a first sub-code for the first upper reference voltage;
a first decoder circuit configured to decode the first sub-code;
an upper reference voltage selector circuit configured to output the first upper reference voltage, based on the decoding result of the first decoder circuit;
a subtractor circuit that performs a subtraction operation on the first code and the second code to generate a second sub-code for the first lower reference voltage;
a second decoder circuit configured to decode the second sub-code; and
a lower reference voltage selector circuit configured to output the first lower reference voltage, based on the decoding result of the second decoder.