Patent ID: 11869568
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. The memory system of claim 15, wherein the target address generation circuit comprises:
an area control circuit suitable for:
updating, during the active operation, the count read from the row hammer area, the read count corresponding to a first received address, and
saving, during the active operation, the updated count in the row hammer area;

a saving circuit suitable for:
updating, during the active operation, a candidate count to the updated count when the updated count is greater than a current value of the candidate count, and
generating a flag signal whenever updating the candidate count, and resetting the candidate count in response to a reset signal; and

a target address output circuit suitable for:
saving therein the first received address as the target address in response to the flag signal,
outputting the target address to the first memory bank during the smart refresh operation, and
generating the reset signal after the smart refresh operation is performed.