Patent ID: 11940945
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. An apparatus comprising:
a SIMD engine comprising a plurality of SIMD processing elements (SPEs), wherein each SPE of the plurality of SPEs comprises an SPE data input, an SPE control input, and an SPE data output, wherein each SPE is configured to provide on the SPE data output a respective result of a respective selected arithmetic logic unit (ALU) operation on the SPE data input, and wherein the selected ALU operation of each said SPE is determined as a function of the SPE control input;
a rewriteable control memory having an address input and a data output, wherein the address input is operably coupled with a decode stage of a pipelined processor to receive an address determined as a function of an instruction decoded by the decode stage, wherein the control memory data output is operably coupled with the SPE control inputs of the plurality of SPEs to provide a plurality of SPE control signals read from the control memory to the SPE control inputs of the plurality of SPEs, and wherein the control memory is an M×N control memory having M rows and N columns configured to retrievably store M possible SIMD operations and N SPE control signals;
an input FIFO having a plurality of inputs configured to receive data comprising a plurality of operands, wherein the input FIFO has a plurality of outputs operably coupled with the SPE data inputs of the plurality of SPEs, wherein the input FIFO has a plurality of per-thread read pointers and a plurality of per-thread write pointers, and wherein the input FIFO read pointers and the input FIFO write pointers are modifiable by processor executable instructions; and
an output FIFO having a plurality of inputs operably coupled with the SPE data outputs of the plurality of SPEs, wherein the output FIFO has a plurality of per-thread read pointers and a plurality of per-thread write pointers, and wherein the output FIFO read pointers and the output FIFO write pointers are modifiable by processor executable instructions, and wherein the output FIFO has an output configured to provide an output of the SIMD engine determined as a function of individual results output by the plurality of SPEs.