Patent ID: 11942403
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A package comprising:
metal interconnects disposed over a substrate;
a first integrated circuit device attached to the metal interconnects, the first integrated circuit device having a first edge and a second edge opposite the first edge;
an underfill having a first portion disposed beneath the first integrated circuit device and having a first fillet extending along the first edge of the first integrated circuit device, an edge of the first portion of the underfill being planar with the second edge of the first integrated circuit device; and
an encapsulant around the first integrated circuit device and the underfill, the encapsulant having a first surface planar with the edge of the first portion of the underfill and the second edge of the first integrated circuit device.