Patent ID: 11960359
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G  H

Claim 8:
9. A memory controller comprising:
a first interface for communication with a host outside of the memory controller;
a second interface for communication with a memory device; and
a control circuit configured to:
receive, through the first interface, a read command requesting to read data stored in the memory device,
execute a defense code on the data when a failure occurs during an operation of reading the data from the memory device in response to the read command through the second interface, and
transmit, through the first interface to the host, defense code information related to the execution of the defense code for the data,
wherein transmittal of the defense code information to the host indicates that the data read from the memory device was recovered by execution of the defense code.