Patent ID: 11862697
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for manufacturing a buried gate, comprising:
providing a trench on an active region of a substrate;
filling a gate structure in a bottom of the trench, and exposing a trench sidewall above the gate structure;
forming a protective layer covering the trench sidewall, an upper surface of the gate structure and an upper surface of the substrate out of the trench;
removing the protective layer on the trench sidewall and retaining the protective layer on the upper surface of the gate structure with an etching process, and exposing the trench sidewall above the gate structure;
growing an epitaxial layer on the exposed trench sidewall with an epitaxial growth process, wherein the epitaxial layer does not close the trench; and
filling an isolation layer in the trench.