Patent ID: 11868250
Assignee: GROQ, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 3:
4. A memory system comprising:
a plurality of memory slices each comprising a plurality of memory tiles for storing data;
a plurality of instruction control circuits each located at one end of a respective memory slice of the plurality of memory slices, and configured to provide instructions to memory tiles of the respective memory slice, wherein the instructions are propagated sequentially over the plurality of memory tiles of the respective memory slice; and
a plurality of data lanes connecting corresponding memory tiles of the plurality of memory slices,
wherein a memory tile of a memory slice of the plurality of memory slices receives at least one instruction provided by its respective instruction control circuit during a first cycle and executes an instruction of the at least one instruction on data during a second cycle, the second cycle having a predetermined temporal relationship with the first cycle based upon an instruction type of the instruction,
wherein an instruction control circuit of the plurality of instruction control circuits is configured to provide, during each of a plurality of clock cycles, a read instruction and a write instruction for each of one or more threads to memory tiles of its respective memory slice.