Patent ID: 11862290
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 10:
11. The memory system according to claim 10, wherein the data has a readout path, the readout path comprises stages for reading out the data from the memory cell and outputting the data through the data port, and the data transmitted on the readout path is defined as intermediate data; and the memory chip comprises:
a delay module, wherein the delay module is provided on the readout path, an input terminal of the delay module receives the intermediate data, a control terminal of the delay module receives the reference voltage, an output terminal of the delay module outputs the intermediate data based on the reference voltage, and a length of the delay of the delay module from receiving the intermediate data to outputting the intermediate data corresponds to the value of the reference voltage; and
an adjustment module, wherein an output terminal of the adjustment module is connected to the control terminal of the delay module, an input terminal of the adjustment module receives a preset reference voltage, a control terminal of the adjustment module receives a control signal, and the output terminal of the adjustment module outputs, based on the control signal and the preset reference voltage, the reference voltage with the adjustable value, wherein
the controller is connected to the control terminal of the adjustment module, and the controller is configured to: obtain the characterization parameter and generate the control signal based on the characterization parameter.