Patent ID: 11860685
Assignee: ADVANCED MICRO DEVICES, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 4:
5. The apparatus as recited in claim 4, wherein the multiplexer circuit comprises:
a first pass gate circuit configured to:
receive an inverted version of the second output clock signal as a first data input signal; and
convey, in the given clock cycle, a non-inverted version of the second output clock signal as the second intermediate clock signal, responsive to the reset signal being negated; and

a second pass gate circuit configured to:
receive the first intermediate clock signal as a second data input signal; and
convey, in the given clock cycle, an inverted version of the first intermediate clock signal as the second intermediate clock signal, responsive to assertion of the reset signal.