Patent ID: 11950514
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 7:
8. A confined memory cell structure, comprising:
conductive materials deposited in a recess of a dielectric substrate to form a bottom lead;
antiferromagnetic materials disposed over the bottom lead to form an antiferromagnetic region;
magnetic materials disposed over the antiferromagnetic region to form a magnetic pinned region;
dielectric materials disposed over the magnetic pinned region and having a via formed therein to expose a portion of the magnetic pinned region;
barrier materials deposited to form a barrier region, comprising a first horizontal portion and a vertical portion deposited into the via such that the first horizontal portion and the vertical portion fills a portion of a volume of the via, such that all surfaces of Page 4 the via are covered by the barrier region, and a second horizontal portion is deposited on top of and in contact with the dielectric materials;
magnetic materials deposited onto the barrier region to form a free region, wherein the free region entirely fills a remaining volume of the via, and wherein a volume of the free region is entirely contained in the via and is surrounded by the barrier region; and
conductive materials deposited directly on top of the free region and the barrier region to form a top lead, such that the top lead is in direct contact with the free region and the barrier region, a vertical cross-section of the free region is entirely contained by the barrier region and the top lead, and wherein lateral edges of the top lead are vertically aligned with lateral edges of each of the bottom lead, the antiferromagnetic region, and the magnetic pinned region.