Patent ID: 11862224
Assignee: REALTEK SEMICONDUCTOR CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A non-transitory computer-readable medium, the non-transitory computer-readable medium storing a program code which causes a system-on-chip (SoC) integrated circuit (IC) to perform a memory calibration procedure when executing the program code, the memory calibration procedure comprising:
in a power-up and initialization phase of the SoC IC, controlling a physical layer (PHY) circuit within the SoC IC to apply power to a memory through a pad set and perform initialization on the memory;
in an impedance-calibration-related phase of the SoC IC, triggering the memory to perform impedance calibration regarding a set of data pins;
in at least one subsequent phase of the SoC IC, during performing calibration operation among a reading-related calibration operation and a writing-related calibration operation, performing a data access test corresponding to a set of test points on a predetermined mask, wherein the predetermined mask is movable with respect to a data eye, and possible positions of the predetermined mask relative to the data eye respectively correspond to multiple candidate positions of a center point of the predetermined mask; and
according to whether the data access test is successful, selectively stopping the calibration operation;
wherein the calibration operation is performed in at least one round,
wherein the at least one round corresponds to at least one candidate position among the multiple candidate positions.