Patent ID: 11915975
Assignee: RENESAS ELECTRONICS CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of manufacturing a semiconductor device, the method comprising steps of:
(a) providing an SOI (Silicon On Insulator) substrate having a main surface including a first region and a second region, and having a stacked structure including a semiconductor substrate, an insulating layer on the semiconductor substrate, and a semiconductor layer on the insulating layer, the main surface being located on the semiconductor layer;
(a1) after the step of (a), forming an element isolation region buried in a trench that penetrates through the semiconductor layer and the insulating layer and reaches the semiconductor substrate;
(b) after the step of (a1), forming a first MISFET composing a certain circuit on the semiconductor layer in the first region, and forming a second MISFET composing a TEG (Test Elemental Group) for VC (Voltage Contrast) inspection on the semiconductor layer in the second region;
(c) forming a first interlayer insulating film on the main surface of the SOI substrate so as to cover the first MISFET and the second MISFET;
(d) forming a plurality of first contact holes in the first interlayer insulating film located in the first region, and forming a plurality of second contact holes in the first interlayer insulating film located in the second region; and
(e) forming a plurality of first contact plugs in the plurality of first contact holes, respectively, and forming a plurality of second contact plugs in the plurality of second contact holes, respectively,
wherein the plurality of second contact plugs includes a third contact plug electrically connected to both the semiconductor layer located in the second region and the semiconductor substrate located in the second region,
wherein the third contact plug reaches the semiconductor substrate, and
wherein the third contact plug is formed at a boundary between the semiconductor layer and the element isolation region surrounding the semiconductor layer in a plan view.