Patent ID: 11914525
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A non-transitory computer-readable medium comprising one or more instructions that when executed on at least one processor configure the at least one processor to perform one or more operations to:
receive, from a deep learning (DL) hardware circuitry communicatively coupled to a last-level cache (LLC) by an interconnect, a plurality of cache access requests;
responsive to a cache line conflict in the LLC for a cache access request of the plurality of cache access requests, implementing a context-based eviction policy to determine a cache way in the LLC to evict in order to resolve the cache line conflict; and
responsive to a cache miss for the cache access request, selecting a variable cache line size to allocate and fill from the LLC, wherein the variable cache line size is selected based on a total size of data indicated in metadata received with the cache access request and based on data utilization of the LLC by a DL network.