Patent ID: 11880687
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. The system of claim 15, wherein the interconnection network is configured to use a split header and payload configuration for pipelining a plurality of communications or for delayed payload switching, and wherein the interconnection network is further configured to use a single header to route a plurality of data payloads as a sequential data burst;
and wherein each configurable circuit, of the plurality of configurable circuits, further comprises:
a plurality of synchronous network inputs; and
a plurality of synchronous network outputs;
wherein the synchronous network is configured to couple each synchronous network input of the plurality of synchronous network inputs to a corresponding synchronous network output, of the plurality of synchronous network outputs, of one or more adjacent configurable circuits of the plurality of configurable circuits of the array to form a plurality of direct connections between adjacent configurable circuits of the plurality of configurable circuits of the array, and wherein the synchronous network further comprises at least one pass through connection between adjacent configurable circuits of the plurality of configurable circuits of the array.