Patent ID: 11973070
Assignee: SJ SEMICONDUCTOR(JIANGYIN) CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 3:
4. The method for making the double-layer stacked 3D fan-out packaging structure according to claim 3, wherein the forming of the first rewiring layer and forming of the second rewiring layer each comprises:
forming a dielectric layer using a chemical vapor deposition process or a physical vapor deposition process, and etching the dielectric layer to form the wiring dielectric layer, and
forming a metal layer on a surface of the wiring dielectric layer using a chemical vapor deposition process, a physical vapor deposition process, a sputtering process, an electroplating process, or an electroless plating process, and etching the metal layer to form a metal wiring layer, wherein the metal connecting pillar is electrically connected to the metal wiring layer.