Patent ID: 11877440
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 3:
4. A forming method for a buried bit line, comprising:
forming a first blocking layer on an inner wall of a bit line slot;
forming a first bit line layer in the bit line slot, wherein a top of the first bit line layer is lower than a surface of a substrate;
forming a contact metal layer in the bit line slot, wherein the contact metal layer covers the first bit line layer, the first blocking layer and the inner wall of the bit line slot;
forming a second bit line layer in the bit line slot, wherein the second bit line layer communicates the first bit line layer with a drain region in the substrate; and
performing a thermal treatment on the substrate, so that a contact surface of the second bit line layer and the contact metal layer reacts with a contact surface of the second bit line layer and the substrate to generate a second blocking layer and a third blocking layer;
wherein the contact metal layer is formed between the third blocking layer and the first bit line layer, and the contact metal layer and the third blocking layer form an ohmic contact.