Patent ID: 11860687
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 17:
18. A semiconductor device comprising:
a first clock circuit configured to:
receive a first clock signal and provide a second clock signal to a first processor based on the first clock signal; and
transmit a first request in response to receiving a first clock stop request from the first processor,

a clock manager circuit configured to:
receive a third clock signal;
provide the first clock signal to the first clock circuit and a monitoring clock signal to a dynamic voltage frequency scaling (DVFS) circuit based on the third clock signal;
transmit a second request to the DVFS circuit to stop providing the monitoring clock signal in response to receiving the first request; and
receive a first acknowledgment from the DVFS circuit,

a second clock circuit configured to:
receive a fourth clock signal;
provide the third clock signal to the clock manager circuit based on the fourth clock signal.