Patent ID: 11894433
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 9:
10. A stacked semiconductor device comprising:
a lower source/drain epi located on top of a dielectric layer, wherein the lower source/drain epi is comprised of a n-type epi, or a p-type epi;
an isolation layer located on top of the lower source/drain epi and the side of the lower source/drain epi;
an upper source/drain epi located on top of the isolation layer, wherein the upper source/drain epi is comprised of a n-type epi, or a p-type epi;
an interlayer dielectric formed around the upper source/drain epi;
an upper electrical contact that extends through the interlayered dielectric to connect to the upper source/drain epi; and
a lower electrical contact that extends through the interlayer dielectric and the isolation layer to be connected to the lower source/drain epi, wherein the lower electrical contact is in direct contact with multiple surfaces of the lower source/drain epi, wherein the lower electrical contact extends under the lower source/drain epi.