Patent ID: 11899609
Assignee: NVIDIA CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 10:
11. A method comprising:
performing a synchronization of one or more data lanes of a link, the synchronization comprising a first phase and a second phase, wherein the first phase comprises:
receiving a first set of bits from each data lane of one or more data lanes, a number of bits in the first set of bits corresponding to a frame size;
determining that the first set of bits received from a data lane of the one or more data lanes does not correspond to a frame boundary of a frame;
shifting the first set of bits received at the data lane of the one or more data lanes by one or more unit intervals (UIs) in response to determining the first set of bits does not correspond to the frame boundary, wherein the second phase comprises:
receiving a second set of frames on each data lane of the one or more data lanes;
determining that a value received at the data lane of the one or more data lanes is different than a value received at the remaining data lanes of the one or more data lanes; and
shifting the second set of frames received at the data lane by one burst unit interval (BUI) in response to determining the value at the data lane is different.