Patent ID: 11962462
Assignee: STMICROELECTRONICS (ALPS) SAS
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A system on a chip, comprising:
a plurality of master pieces of equipment;
a plurality of slave resources;
an interconnection circuit coupled between the master pieces of equipment and the slave resources and capable of routing transactions between the master pieces of equipment and the slave resources;
a processing unit configured to implement within the system on a chip at least one configuration diagram of the system defined by a set of configuration pieces of information including at least one piece of identification information assigned to each master piece of equipment;
a first master piece of equipment, of the master pieces of equipment, configured to boot during a first boot of the system on a chip to allow the implementation of the configuration diagram;
a second master piece of equipment, of the master pieces of equipment; and
a restore unit configured to allow the second master piece of equipment to restore the configuration diagram, instead of the first master piece of equipment, in response to an exit from a standby mode of the system on a chip, wherein the restore unit comprises:
a first backup memory configured to back up the configuration diagram to be restored;
a second program memory configured to store, upon control of the first master piece of equipment, a restore program executable by the second master piece of equipment;
a secure storage unit configured to store a signature of the restore program and a start address of the restore program in the second program memory; and
a wake-up source configured to generate a wake-up signal to the second master piece of equipment in response to the system on a chip exiting from the standby mode.