Patent ID: 11861167
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. An apparatus, comprising:
a first counter;
a second counter coupled with the first counter;
a third counter associated with performing a wear-leveling operation on sets of memory cells in a memory device;
a fourth counter associated with a first set of the sets of memory cells; and
a fifth counter for indicating a global offset value relative to a value of the third counter;
a second incrementor coupled with the second counter and configured to increment a value of a quantity of wear-leveling operations;
a comparator coupled with the first counter and configured to compare a value of the first counter with a threshold; and
one or more selection circuits coupled with the comparator and configured to determine incremented counter values of the first counter and the second counter based at least in part on one or more outputs of the comparator.