Patent ID: 11908520
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 14:
15. A method, comprising:
providing a first chip including a first substrate, a first circuit provided on the first substrate, a first electrode, and a first memory cell array;
providing a second chip including a second substrate, a second circuit provided on the second substrate, a second electrode, and a second memory cell array; and
bonding the first chip to the second chip through the first and second electrodes, such that the one or more first decoders are coupled to the first memory cell array, the first electrode faces a bonding surface of the first chip and the second chip with the first electrode electrically connected to the first circuit, the first memory cell array is provided between the first substrate and the first electrode and electrically connected to the first circuit, the second electrode faces the bonding surface with the second electrode electrically connected to the second circuit and being in contact with the first electrode, and the second memory cell array is provided between the second substrate and the second electrode and electrically connected to the second circuit.