Patent ID: 11862264
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. The memory circuit of claim 17, wherein the latch further comprises:
a first inverter comprising a first input terminal of the first inverter coupled to the first output terminal of the first NAND logic gate and configured to receive the first NAND output signal, and a first output terminal of the first inverter configured to generate an inverted first NAND output signal; and
a second inverter comprising a first input terminal of the second inverter coupled to the first output terminal of the second NAND logic gate and configured to receive the second NAND output signal, and a first output terminal of the second inverter configured to generate an inverted second NAND output signal,
wherein the inverted first NAND output signal corresponds to the first value stored in the first non-volatile memory cell, and the inverted second NAND output signal corresponds to the second value stored in the second non-volatile memory cell.