Patent ID: 11960319
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. An electronic device comprising:
a host configured to output an external clock signal, a chip enable signal, and at least one external enable signal;
a memory device configured to operate responsive to the external clock signal and the chip enable signal, and configured to generate an internal enable signal based on the at least one external enable signal, wherein the memory device is configured to generate and output a monitoring signal that indicates whether the memory device is operating under control of the host,
wherein the memory device comprises a plurality of flip-flop circuits that are electrically connected in a daisy chain configuration, and wherein each of the flip-flop circuits is configured to receive an internal clock signal or the internal enable signal,
wherein an initial flip-flop circuit of the daisy chain configuration is configured to output a first logic signal to a next flip-flop circuit of the daisy chain configuration in accordance with the internal clock signal, and
a final flip-flop circuit of the daisy chain configuration is configured to output an output of a previous flip-flop circuit of the daisy chain configuration as the monitoring signal in accordance with the internal enable signal.