Patent ID: 11875057
Assignee: NVIDIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. A non-transitory computer-readable medium storing program instructions that, when executed by a processor, cause a performance monitor to perform steps of:
receiving a first set of one or more signals;
generating a first input based on the first set of one or more signals;
determining, based on the first input and a current state, that a first state transition condition is satisfied, wherein the first state transition condition is stored in a first data entry in a memory associated with the performance monitor;
in response to determining that the first state transition condition is satisfied, transmitting a trigger signal to an internal logic analyzer;
changing a mode of the memory from a first mode associated with a state machine of the performance monitor to a second mode associated with the internal logic analyzer; and
in response to the trigger signal, causing a second set of one or more signals to be stored in the memory via the internal logic analyzer.