Patent ID: 11888403
Assignee: UNITED STATES OF AMERICA AS REPRESENTED BY THE SECRETARY OF THE AIR FORCE
Field: Electrical machinery, apparatus, energy (Electrical engineering)
Classification: CPC H  Y | IPC H

Claim 0:
1. A method for galvanically isolating a load from a power source and limiting current from the power source to the load, the method comprising:
receiving a direct current (DC) input voltage and an input current from a power source;
switching one of a full-bridge inverter and a half-bridge inverter to synthesize a first alternating voltage waveform that magnetically couples through a transformer to induce a second alternating voltage waveform with galvanic isolation from the first alternating voltage waveform, the galvanic isolation provided by the transformer preventing a potentially-faulted load from having a direct electrical connection to the power source;
rectifying the second alternating voltage waveform to produce a DC output voltage having output current through more than one secondary side transistor;
current limiting more than one primary side drive transistor to reduce or prevent brown-out, black-out, or protective race conditions in non-faulted portions of DC power generation systems and DC distribution electrical power systems by:
utilizing a transistor to control a voltage or a current mode control output signal to the gate drive circuitry; and
utilize negative gate bias to rapidly disable the gate drive signal, without modifying voltage or current mode control design or operation;

comparing the output current to a programmed current limit;
in response to the output current being greater than the programmed current limit, shutting off the more than one primary side drive transistor to limit output current; and
in response to the output current not being greater than the programmed current limit, supplying a common collector voltage to respective gate drives circuitry of the more than one primary side drive transistor.