Patent ID: 11880706
Assignee: NANJING QINHENG MICROELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 3:
4. The interrupt control method based on RISC-V according to claim 3, wherein sub-memory areas of the first-type memory area are set from the level 2 sub-memory area to a level m sub-memory area, sub-memory areas of the second-type memory area are set from the level 1 sub-memory area to a level n sub-memory, and m>n;
when the processor sends out an n+1th nested interrupt in the process of handling an nth interrupt event, the following steps are executed:
(n1) receiving and responding to an n+1th interrupt request, and stopping handling the nth interrupt event;
(n2) jumping, by the processor, to an n+1th interrupt entry, and meanwhile, storing the content in the control and status register set before handling an n+1th interrupt event begins to be processed into a level n+1 sub-memory area of the first-type memory area, and then protecting the content in the Caller-save type general-purpose register before handling the n+1th interrupt event by software, without accessing the second-type memory area;
(n3) handling, by the processor, the n+1th interrupt event; and
(n4) once the n+1th interrupt event is completed, restoring the content in the Caller-save type general-purpose register by software, then returning to continuously process the n th interrupt event, and meanwhile, loading back a content from the level n+1 sub-memory area into the control and status register set.