Patent ID: 11860793
Assignee: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. The computing system according to claim 7, wherein each time a page table entry subgroup is created, the controller is configured to combine the valid information in the first page table entry of the created page table entry subgroup with the valid information in the first page table entry of at least one previously created page table entry subgroup, and
wherein when all of the first predetermined number of bits in the valid information in the first page table entries of the page table entry subgroups are set to the first state, the controller is configured to create a page table entry group, change remaining bits except for the selected bit of the first predetermined number of bits in the valid information in the first page table entry of the page table entry subgroup of the page table entry group from the first state to the second state, and increase the size information in the first page table entry of the page table entry subgroup of the page table entry group.