Patent ID: 11894308
Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. A substrate, comprising:
a dielectric layer, having a first surface and a second surface opposite to the first surface, the dielectric layer defining a die region and a peripheral region adjoining to the die region;
a first conductive via located in the peripheral region and extending between the first surface and the second surface, the first conductive via comprising a first pattern;
a second conductive via located in the die region and extending between the first surface and the second surface; and
a third conductive via located in the peripheral region and extending between the first surface and the second surface, the third conductive via comprising a third pattern:
wherein the first pattern comprises at least two first geometric centers corresponding to at least two first geometric patterns, respectively, and wherein the third pattern comprises at least two third geometric centers corresponding to at least two third geometric patterns, respectively, and
wherein a first imaginary line connecting the at least two first geometric centers is non-parallel to a second imaginary line connecting the at least two third geometric centers.