Patent ID: 11895851
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. An apparatus, comprising:
a memory array having a plurality of decks and a plurality of bit lines, each of the plurality of bit lines coupled with one or more decks of the plurality of decks, the plurality of bit lines comprising a first bit line, a second bit line, and a third bit line;
a plurality of bit line decoders positioned beneath the memory array; and
a plurality of bit line sockets comprising a first subset of bit line sockets that are arranged according to a first periodicity and couple respective segments of the first bit line with respective bit line decoders of the plurality of bit line decoders, a second subset of bit line sockets that are arranged according to a second periodicity and couple respective segments of the second bit line with respective bit line decoders of the plurality of bit line decoders, and a third subset of bit line sockets that are arranged according to the second periodicity and couple respective segments of the third bit line with respective bit line decoders of the plurality of bit line decoders.