Patent ID: 11894306
Assignee: PING-JUNG YANG
Field: Semiconductors (Electrical engineering)
Classification: CPC H  C  Y | IPC H

Claim 0:
1. A chip package comprising:
a solid layer having a first surface and a second surface opposite to said first surface, wherein said solid layer comprises a compound of silicon and oxygen, wherein said solid layer has a thickness between 50 and 150 micrometers, wherein said solid layer comprises a first region and a second region between said first region and a first edge of said solid layer;
a plurality of metal posts in a plurality of through holes in said second region respectively, wherein one of said plurality of metal posts comprises a first copper layer contacting a sidewall of one of said plurality of through holes, wherein said first region has a width in a direction greater than a shortest distance between said sidewall of one of said plurality of through holes and said first edge in said direction and greater than a pitch between two neighboring metal posts of said plurality of metal posts;
a first interconnection scheme over said first surface, wherein said first interconnection scheme comprises a first metal interconnect over said second surface and a polymer layer over said first metal interconnect, wherein said first metal interconnect is connected to a first metal post of said plurality of metal posts, wherein said first metal interconnect comprises a first metal layer and a second copper layer over said first metal layer;
a first metal bump over said first interconnection scheme, wherein said first metal bump comprises a second metal layer and a first tin-containing layer over said second metal layer; and
a first semiconductor chip under said second surface, wherein said first interconnection scheme comprise a second metal interconnect across over a sidewall of the first semiconductor chip, wherein said first semiconductor chip comprises a third metal interconnect on a first metal pad of said first semiconductor chip, wherein said third metal interconnect comprises a third metal layer on said first metal pad and a third copper layer over said third metal layer, wherein said third copper layer has a thickness between 5 and 30 micrometers, wherein said first semiconductor chip is connected to a second metal post of said plurality of metal posts through said third metal interconnect.