Patent ID: 11879942
Assignee: MICRON TECHNOLOGY, INC.
Field: Measurement (Instruments)
Classification: CPC G | IPC G

Claim 21:
22. A method, comprising:
loading, by a system that includes a first integrated circuit and a second integrated circuit, test data into at least one of:
a plurality of lower-level input scan flip-flops of the first integrated circuit, wherein the plurality of lower-level input scan flip-flops of the first integrated circuit are arranged in a plurality of stages,
a plurality of lower-level output scan flip-flops of the first integrated circuit, wherein the plurality of lower-level output scan flip-flops of the first integrated circuit are arranged in a plurality of stages,
a plurality of lower-level core scan flip-flops of the first integrated circuit,
a plurality of lower-level input scan flip-flops of the second integrated circuit, wherein the plurality of lower-level input scan flip-flops of the second integrated circuit are arranged in a plurality of stages,
a plurality of lower-level output scan flip-flops of the second integrated circuit, wherein the plurality of lower-level output scan flip-flops of the second integrated circuit are arranged in a plurality of stages,
a plurality of lower-level core scan flip-flops of the second integrated circuit,
a first plurality of upper-level output scan flip-flops of the system, wherein the first plurality of upper-level output scan flip-flops are arranged in a plurality of stages that includes a final stage that is connected to inputs of the first integrated circuit,
a first plurality of upper-level input scan flip-flops of the system, wherein the first plurality of upper-level input scan flip-flops are arranged in a plurality of stages that includes an initial stage that is connected to outputs of the first integrated circuit,
a second plurality of upper-level output scan flip-flops of the system, wherein the second plurality of upper-level output scan flip-flops are arranged in a plurality of stages that includes a final stage that is connected to inputs of the second integrated circuit,
a second plurality of upper-level input scan flip-flops of the system, wherein the second plurality of upper-level input scan flip-flops are arranged in a plurality of stages that includes an initial stage that is connected to outputs of the second integrated circuit, or
a plurality of upper-level core scan flip-flops of the system; and

executing, by the system, a test based on loading the test data into at least one of the plurality of lower-level input scan flip-flops of the first integrated circuit, the plurality of lower-level output scan flip-flops of the first integrated circuit, the plurality of lower-level core scan flip-flops of the first integrated circuit, the plurality of lower-level input scan flip-flops of the second integrated circuit, the plurality of lower-level output scan flip-flops of the second integrated circuit, the plurality of lower-level core scan flip-flops of the second integrated circuit, the first plurality of upper-level output scan flip-flops of the system, the first plurality of upper-level input scan flip-flops of the system, the second plurality of upper-level output scan flip-flops of the system, the second plurality of upper-level input scan flip-flops of the system, or the plurality of upper-level core scan flip-flops of the system; and
obtaining, by the system, test results based on executing the test.