Patent ID: 11894079
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. A memory device comprising:
a memory cell array including a first block of first memory cells and a second block of second memory cells; and
control logic configured to preprogram and then erase the first memory cells such that each of the first memory cells has a first threshold voltage level, wherein fast cells are detected among the memory cells according to a threshold voltage less than or equal to a second threshold voltage less than the first threshold voltage,
wherein the control logic is further configured to generate fast cell information associated with the fast cells and store the fast cell information in the second block, and upon receiving a program command directed to the first memory cells, over-programming the fast cells by referencing the fast cell information stored in the second memory cells, and
wherein the control logic is further configured to compare a number of the fast cells to a reference threshold value, and
stores the fast cell information in the second memory cells block only if the number of fast cells is greater than the reference threshold value.