Patent ID: 11869569
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. A memory system comprising:
a system-on-chip including a memory controller configured to output a clock signal and a command, and to input or output data;
a semiconductor memory device comprising:
a memory cell array including a plurality of memory cells; and
a control logic circuit configured to receive the clock signal and the command from the memory controller, and to control the semiconductor memory device to transmit the data stored in the memory cell array to the memory controller or to store the data received from the memory controller in the memory cell array; and

a display device,
wherein the control logic circuit comprises:
a mode register;
a clock monitor configured to count a clock number of the clock signal received from the memory controller;

a data counter configured to count a data number of the data transmitted or received to or from the memory controller;
a command counter configured to count a read and write command number of read and write commands received from the memory controller, and to count a refresh command number of refresh commands received from the memory controller;
an accumulator configured to calculate an accumulated clock number by accumulating the clock number, to calculate an accumulated data number by accumulating the data number, to calculate an accumulated read and write command number by accumulating the read and write command number, and to calculate an accumulated refresh command number by accumulating the refresh command number; and
a remaining lifetime code generator configured to calculate a remaining clock number by subtracting the accumulated clock number from a maximum clock number corresponding to a maximum lifetime of the semiconductor memory device, to calculate a remaining data number by subtracting, the accumulated data number from a maximum data number corresponding to the maximum lifetime, to calculate a remaining read and write command number by subtracting the accumulated read and write command number from a maximum read and write command number corresponding to the maximum lifetime, to calculate a remaining refresh command number by subtracting the accumulated refresh command number from a maximum refresh command number corresponding to the maximum lifetime, and to generate the remaining lifetime code based on the remaining clock number, the remaining data number, the remaining read and write command number and/or the remaining refresh command number,

wherein the memory controller receives the remaining lifetime code stored in the mode register from the semiconductor memory device by performing a mode register read operation,
wherein the system-on-chip transfers image data for the remaining lifetime represented by the remaining lifetime code to the display device, and
wherein the display device displays the remaining lifetime of the semiconductor memory device based on the image data.