Patent ID: 11966329
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A solid-state drive memory system, comprising:
non-volatile media having a quantity of memory units, wherein the non-volatile media includes a flash memory, and wherein an address map is stored in the non-volatile media;
a volatile memory that stores a first portion of the address map, the address map defining logical addresses in terms of physical addresses of the memory units in the non-volatile media; and
a controller configured to process requests from a host system to store data in the non-volatile media or retrieve data from the non-volatile media, the host system having a memory connected to the memory system via a communication channel;
wherein a cache manager stores a second portion of the address map in the memory of the host system;
wherein in response to an operation that uses a logical address defined in the second portion, the cache manager is configured to swap the first portion of the address map and the second portion of the address between the volatile memory of the solid-state drive memory system and the memory of the host system by:
retrieving the second portion of the address map from the memory of the host system through the communication channel and storing the second portion of the address map in the volatile memory of the memory system;
transmitting the first portion of the address map from the volatile memory of the memory system through the communication channel to the memory of the host system;

wherein the memory of the host system is accessible to the controller at a speed greater than accessing the non-volatile media; and
wherein the memory of the host system is identified to the memory system during the powering up via a base address register;
wherein, before the first portion of the address map has been swapped into the memory of the host system, the first portion of the address map is changed or updated:
while the first portion of the address map is stored in the volatile memory of the memory system, and
during first operations involving logical addresses defined in the first portion of the address map, wherein the first operations are performed by the controller responsive to a first request from the host system;

wherein, after the second portion of the address map has been swapped into the volatile memory of the memory system, the second portion of the address map is changed or updated:
while the second portion of the address map is stored in the volatile memory of the memory system, and
during second operations involving logical addresses defined in the second portion of the address map, wherein the second operations are performed by the controller responsive to a second request from the host system;

wherein, after the second portion of the address map has been swapped into the volatile memory of the memory system and the first portion of the address map has been swapped into the memory of the host system, in response to a request to shut down the memory system, the cache manager stores, in the non-volatile media of the memory system, the second portion of the address map from the volatile memory of the memory system that has been changed or updated during the second operations; and
wherein further in response to the request to shut down the memory system, the cache manager stores, in the non-volatile media of the memory system, the first portion of the address map from the memory of the host system that has been changed or updated during the first operations, such that changes to both of the first portion and the second portion of the address map resulting from the first operations and the second operations, respectively, are saved in the address map stored in the non-volatile memory upon shutdown of the memory system;
wherein the controller is configured to perform, in response to a first request associated with the first operations, a real time analysis of data stored in the memory of the memory system, wherein the data stored in the memory of the memory system comprises sensor data collected from a plurality of sensors, and wherein the plurality of sensors are real time sensors connected to the memory system;
wherein the controller is configured to determine, based on the real time analysis, a reduced data set responsive to the first request; and
wherein the controller is configured to communicate the reduced data set to the host system.