Patent ID: 11930679
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 11:
12. The preparation method for the array substrate according to claim 11, wherein the forming the pattern of the dielectric layers between the source-drain electrode and the substrate comprises:
depositing an organic silicon glass solution for forming a buffer layer on the substrate and performing a pre-baking process before forming the thin film transistor;
adopting a half-tone mask to expose and develop the buffer layer subjected to the pre-baking process, wherein the pattern of the buffer layer is formed in a mode that: a thickness of a region of the buffer layer where the thin film transistor is to be formed is greater than a thickness of a region of the buffer layer where the color resist is to be formed; and
performing a post-baking process on the buffer layer to form a dense SiOx material.