Patent ID: 11955425
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A method comprising:
forming a plurality of gate electrodes extending along a first direction, wherein the plurality of gate electrodes has a gate pitch (GP), wherein at least one of the plurality of gate electrodes is disposed over and engages a respective channel region and the at least one of the plurality of gate electrodes is disposed between respective source/drain regions; and
forming an interconnect structure over the plurality of gate electrodes, wherein the forming the interconnect structure includes:
forming odd-numbered interconnect routing layers oriented along a second direction that is substantially perpendicular to the first direction,
forming even-numbered interconnect routing layers oriented along a third direction that is substantially parallel to the first direction, wherein a first of the even-numbered interconnect routing layers has a first pitch (P2) and a third of the even-numbered interconnect routing layers has a second pitch (P6), and
configuring the first pitch and the second pitch, such that a ratio of the gate pitch to the first pitch to the second pitch (GP:P2:P6) is 3:2:4.