Patent ID: 11922062
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A controller that controls a memory device, the controller comprising:
a host interface suitable for fetching a write command received from a host;
a buffer suitable for storing write data associated with the write command; and
a processor suitable for controlling a host write operation of the write data to the memory device in response to the fetched write command and a background operation onto the memory device,
wherein, when a workload of the background operation is greater than a workload of the host write operation and an available capacity of the buffer is smaller than a threshold capacity, the host interface is further suitable for:
generating a completion response in response to the write command;
determining a delay amount of time;
delaying the completion response by the delay amount of time; and
providing the host with the delayed completion response,
wherein, during the delay amount of time, the processor performs the background operation onto the memory device and the host write operation such that the workloads of the processor are reduced, and, after the delay amount of time, a next command from the host is received by the host interface,
wherein the host interface determines the delay amount of time based on a free buffer size as the available capacity and an estimated-required buffer size, and
wherein the host interface is further suitable for determining the estimated-required buffer size based on a number of commands received from the host but unfetched, a ratio of write commands among recently fetched commands and a data size of the fetched write command.