Patent ID: 11935886
Assignee: NANYA TECHNOLOGY CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A method of generating a semiconductor layout used for an electrostatic discharge (ESD) protection circuit, comprising:
forming a core circuit;
forming a MOS transistor, spaced apart from the core circuit;
forming a dummy structure, arranged between the MOS transistor and the core circuit, wherein the dummy structure comprises at least one of a poly layer and a metal layer;
utilizing a portion of the at least one of the poly layer and the metal layer to form a resistor;
overlapping the resistor with at least a portion of the dummy structure, wherein a distance between the resistor and the MOS transistor is smaller than that of between the resistor and the core circuit; and
encircling the MOS transistor by distributing the resistor along edges of the MOS transistor.