Patent ID: 11876535
Assignee: SILICON MOTION, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A memory controller, for use in a data storage device, wherein a low-density parity-check (LDPC) decoding procedure performed by the memory controller comprises an initial phase, a decoding phase, and an output phase in sequence, the memory controller comprising:
a memory-index control circuit, configured to control data access of a variable-node memory; and
a decoder, comprising a decoding pipeline to perform the decoding phase of the LDPC decoding procedure,
wherein after the data storage device is booted up, the decoder reads a plurality of first codewords from the variable-node memory using a first order via the memory-index control circuit for LDPC decoding,
wherein in response to the decoder determining that a specific codeword among the first codewords has decoding failure, the decoder is reset to read a plurality of second codewords from the variable-node memory using a second order via the memory-index control circuit for LDPC decoding,
wherein the first order is different from the second order.