Patent ID: 11908525
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  B | IPC G  H

Claim 25:
26. The method for controlling the memory device according to claim 1, further comprising:
a plurality of third memory cells connected between the first drain side selective transistor and the first source side selective transistor;
a plurality of fourth memory cells connected between the second drain side selective transistor and the second source side selective transistor;
a plurality of third word lines connected to gates of the third memory cells; and
a plurality of fourth word lines connected to gates of the fourth memory cells,
the plurality of first control gate lines being connected to the plurality of fourth word lines not via any of the plurality of the second word lines or any of the plurality of the third word lines, and
the plurality of second control gate lines being connected to the plurality of third word lines not via any of the plurality of the first word lines or any of the plurality of the fourth word lines.