Patent ID: 11869582
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 1:
2. The method of claim 1, wherein the first verify skip period comprises at least one loop and corresponds to a period in which only a plurality of program pulses, sequentially increasing as much as a step voltage, are applied,
a length of the first verify skip period is inversely proportional to the first off cell count,
the second verify skip period comprises at least one loop and corresponds to a period in which a plurality of program pulses, sequentially increasing as much as the step voltage, and the plurality of verify pulses are applied,
the plurality of verify pulses comprise verify pulses for remaining program states other than a completed program state, from among a plurality of program states, and
a length of the second verify skip period is inversely proportional to the second off cell count.