Patent ID: 11971821
Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 33:
34. A method for write-back and invalidation in a hierarchical cache structure based on a plurality of designated key identification codes, comprising:
in response to a second instruction of an instruction set architecture that is fetched by a first core for write-back and invalidation in a hierarchical cache structure based on a plurality of designated key identification codes, operating a decoder of the first core to output at least one microinstruction, wherein the first core is provided by a first processor that is fabricated on a first die;
based on the at least one microinstruction decoded from the second instruction, storing the designated key identification codes in a storage unit of the first core and, through a memory ordering buffer of the first core, providing a plurality of write-back and invalidation requests, corresponding to the different designated key identification codes read from the storage unit, to a first in-core cache module of the first core,
wherein write-back and invalidation in the hierarchical cache structure based on the next designated key identification code is performed after write-back and invalidation in the hierarchical cache structure based on a current designated key identification code is finished.