Patent ID: 11895831
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A manufacturing method for memory, comprising:
providing a substrate, and forming a first isolation layer and discrete bit lines on the substrate, wherein the bit lines extend along a first direction, and the first isolation layer is located on surfaces of the bit lines away from the substrate and further located between adjacent bit lines;
removing part of the first isolation layer by a thickness to form discrete first trenches, wherein the first trenches extend along a second direction, and the second direction is different from the first direction;
forming word lines filling the first trenches, wherein the first isolation layer with a certain thickness is provided between the word lines and the bit lines, and the word lines each has a first side wall and a second side wall opposite to each other;
forming discrete through holes each being between adjacent word lines, wherein the through holes expose the first side wall and the second side wall of each of the word lines, and the surfaces of the bit lines; and the first side wall and the second side wall are arranged oppositely;
forming a first dielectric layer on a surface of the exposed first side wall, and forming a second dielectric layer on a surface of the exposed second side wall, wherein a thickness of an equivalent-gate dielectric layer of the first dielectric layer is greater than a thickness of an equivalent-gate dielectric layer of the second dielectric layer; and
forming an active layer filling the through holes after the first dielectric layer and the second dielectric layer are formed.