Patent ID: 11928475
Assignee: CEREMORPHIC, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus comprising:
a primary processor comprising a primary processor pipeline, wherein the primary processor pipeline comprises an execute stage and a load/store stage;
a secondary processor comprising a secondary processor pipeline, wherein the secondary processor pipeline comprises an execute stage and a load/store stage;
a store data comparator having a first input operably coupled with the primary processor pipeline, a second input operably coupled with the secondary processor pipeline, and an output, wherein the store data comparator is configured to indicate at the output a result of comparing delayed primary processor pipeline signals with delayed secondary processor pipeline signals;
a primary processor pipeline store data control gate configured to output delayed primary processor pipeline signals to the primary processor pipeline load/store stage only if the store data comparator output indicates agreement between the delayed primary processor pipeline signals and the delayed secondary processor pipeline signals compared by the store data comparator; and
a secondary processor pipeline store data control gate configured to output delayed secondary processor pipeline signals to the secondary processor pipeline load/store stage only if the store data comparator output indicates agreement between the delayed primary processor pipeline signals and the delayed secondary processor pipeline signals compared by the store data comparator;
wherein the primary processor pipeline execute stage has an output operably connected through a primary processor pipeline store data path delay module to a first input of the primary processor store data control gate; and
the primary processor pipeline store data path delay module is a three-stage triple module redundancy buffer delay module wherein each stage is configured to pass only majority data.