Patent ID: 11869929
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A laminated capacitor, comprising:
a substrate;
a first isolation insulation spacer and a plurality of discrete bottom bonding pads arranged in the first isolation insulation spacer on the substrate;
N connection structures and N+1 sub-capacitor structures located on the first isolation insulation spacer and the bottom bonding pads, wherein N is an integer greater than or equal to 1, and the N+1 sub-capacitor structures and the N connection structures are alternately arranged along a direction perpendicular to the substrate;
wherein each of the sub-capacitor structures comprises a plurality of discrete bottom electrodes, a plurality of discrete top electrodes, and a dielectric medium between the bottom electrodes and the top electrodes; and the plurality of bottom bonding pads are respectively electrically connected with the plurality of bottom electrodes of a sub-capacitor structure adjacent to the plurality of bottom bonding pads in one-to-one correspondence.