Patent ID: 11973035
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A semiconductor memory device, comprising:
a first substrate including a first surface and a second surface opposite to the first surface;
circuit elements on the first surface of the first substrate;
a first interlayer insulating layer on the first substrate and the circuit elements;
a second substrate on the first interlayer insulating layer, the second substrate including a third surface facing the first surface of the first substrate and a fourth surface opposite to the third surface;
a stacked structure on the fourth surface of the second substrate, the stacked structure including word lines;
a channel structure penetrating the stacked structure;
a dummy conductive structure extending through at least a portion of the word lines to contact the second substrate, the dummy conductive structure including a first metal core pattern and a first spacer extending along a side surface of the first metal core pattern;
and
a through contact plug electrically connected to the circuit elements,
wherein a height of an upper surface of the dummy conductive structure is greater than a height of an upper surface of the channel structure relative to the fourth surface of the second substrate.