Patent ID: 11934867
Assignee: NVIDIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 20:
21. A method comprising:
executing a single instruction multi-thread (SIMT) application as a plurality of threads;
splitting the execution of the plurality of threads into sequentially executed groups of threads in response to execution divergence among the plurality of threads, each of the groups executed in a SIMT manner, wherein each of the groups is a shard;
detecting a long stall in a first one of the shards, the detecting triggered by execution of a compiler-generated hint instruction in the first one of the shards;
in response to detecting the long stall in the first one of the shards, switching execution from the first one of the shards to a second one of the shards; and
wherein the compiler-generated hint instruction is executed in the first one of the shards between a long-latency producer instruction and a consumer instruction that utilizes a result of the long-latency producer instruction.