Patent ID: 11936791
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 17:
18. A computing device comprising:
a processor and a memory containing instructions executable by the processor to cause the processor to perform a process that includes:
displaying, via a user interface, a reliability requirement associated with instructions for a device;
receiving an assertion in relation to the reliability requirement, the assertion comprising a string value;
generating a cryptographic assertion tracer (CAT) based at least in part on the received assertion;
receiving a request to associate the CAT and assertion-related instructions from a first copy of the instructions for the device; and
generating a first code verification encrypted reproducible record (ERR) based at least in part on the CAT and the associated assertion-related instructions from the first copy of the instructions for the device;
receiving a request to determine whether the reliability requirement is addressed in a second copy of the instructions for the device;
generating a second code verification ERR based at least in part on the CAT and the assertion-related instructions from the second copy of the instructions for the device;
comparing the first and second code verification ERRs; and
when the first and second code verification ERRs do not match, based on the comparison, reporting that the reliability requirement is not addressed.