Patent ID: 11917813
Assignee: NANYA TECHNOLOGY CORPORATION
Field: nan (nan)
Classification: CPC H | IPC H

Claim 0:
1. A memory array, comprising:
a first group of active areas and a second group of active areas, formed of laterally separate surface portions of a semiconductor substrate, wherein top surfaces of the first group of the active areas are recessed with respect to top surfaces of the second group of the active areas;
capacitor contacts disposed on the first group of active areas and the second group of active areas, respectively;
an isolation structure, extending between the first group of active areas and the second group of active areas, and in contact with bottom portions of the first group of active areas and the second group of active areas; and
contact enhancement caps, capping top portions of the first group of active areas and the second group of the active areas, respectively, wherein the capacitor contacts penetrate through the contact enhancement caps to directly contact with the first group of active areas and the second group of the active areas, respectively;
wherein the contact enhancement caps respectively comprise:
a contact enhancement layer, lying the top surface of one of the first group of active areas and the second group of active areas; and
a contact enhancement sidewall spacer, laterally surrounding the top portion of the one of the first group of active areas and the second group of active areas;
wherein the contact enhancement sidewall spacers of a first group of the contact enhancement caps covering the top portions of the first group of the active areas are shorter in height as compared to the contact enhancement sidewall spacers of a second group of the contact enhancement caps covering the top portions of the second group of the active areas.