Patent ID: 11929110
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 15:
16. The memory circuit of claim 11, wherein the global control circuit comprises:
a clock gating circuit configured to generate the first clock signal in response to a second clock signal and a chip enable signal;
an address latch circuit configured to generate the first set of local address signals, a second set of local address signals, and a third set of local address signals in response to the memory address signal;
a first pre-decoder circuit coupled to the address latch circuit, and configured to generate the first set of global pre-decoder signals in response to at least the second set of local address signals or an inverted second set of local address signals; and
a second pre-decoder circuit coupled to the address latch circuit, and configured to generate the second set of global pre-decoder signals in response to at least the third set of local address signals or an inverted third set of local address signals.