Patent ID: 11955180
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 10:
11. A memory, comprising:
an array of memory cells comprising a string of series-connected split-gate memory cells, wherein each split-gate memory cell of the string of series-connected split-gate memory cells comprises a first memory cell portion and a second memory cell portion on opposing sides of a semiconductor pillar; and
a controller for access of the array of memory cells, wherein the controller is configured to cause the memory to:
during a first programming operation on a selected split-gate memory cell of the string of series-connected split-gate memory cells, program user data to the first memory cell portion of the selected split-gate memory cell; and
during a second programming operation on the selected split-gate memory cell of the string of series-connected split-gate memory cells, program predetermined data to the second memory cell portion of the selected split-gate memory cell.