Patent ID: 11962309
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G  Y | IPC H

Claim 11:
12. The phase adjusting circuit of claim 11, wherein a number of the bits of the preset fixed value and a number of the bits of the count value are identical, and both are n;
the adjustment sub-circuit comprises (n+1) inverting sub-circuits, and a first inverting sub-circuit is always in an on state;
when the adjustment sub-circuit belongs to the first adjustment circuit or the third adjustment circuit, whether an (i+1)-th inverting sub-circuit is turned on depends on an i-th bit of the preset fixed value;
when the adjustment sub-circuit belongs to the second adjustment circuit or the fourth adjustment circuit, whether the (i+1)-th inverting sub-circuit is turned on depends on an i-th bit of the count value;
wherein, n is a positive integer, i is a positive integer, and i is less than or equal to n.