Patent ID: 11861282
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A method of manufacturing an integrated circuit (IC) structure, the method comprising:
forming a first plurality of fins extending in a first direction on a substrate;
forming a second plurality of fins extending in the first direction on the substrate adjacent to the first plurality of fins;
forming a third plurality of fins extending in the first direction on the substrate adjacent to the second plurality of fins; and
forming a fourth plurality of fins extending in the first direction on the substrate adjacent to the third plurality of fins,
wherein
the forming each fin of each of the first and fourth pluralities of fins comprises forming one of an n-type fin or a p-type fin,
the forming each fin of each of the second and third pluralities of fins comprises forming the other of the n-type fin or the p-type fin,
the forming each of the first and third pluralities of fins comprises forming a first total number of fins, and
the forming each of the second and fourth pluralities of fins comprises forming a second total number of fins fewer than the first total number of fins.