Patent ID: 11927620
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 14:
15. The method for simulating electricity of a wafer chip of claim 14, after repairing the abnormality of the obtained semiconductor structure, further comprising:
obtaining the spectroscopic data of the repaired semiconductor structure;
simulating electrical data of a repaired target wafer chip based on the spectroscopic data of the obtained repaired semiconductor structure and the database;
determining whether or not the electrical data of the repaired target wafer chip is abnormal;
performing a next process step to the repaired target wafer chip in a case where the electrical data of the repaired target wafer chip is normal;
retaining the repaired target wafer chip in a current process step in a case where the electrical data of the repaired target wafer chip is abnormal;
testing whether or not the repair process is abnormal, and analyzing the abnormality present in the repaired semiconductor structure;
repairing the repaired semiconductor structure again in a case where the abnormality present in the repaired semiconductor structure is repairable; and
scrapping the repaired semiconductor structure in a case where the abnormality present in the repaired semiconductor structure is irreparable.