Patent ID: 11956940
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 15:
16. A method of forming a memory cell, comprising:
forming a source region, a drain region, and a channel region of a transistor, wherein the source region, the drain region and the channel region are stacked in a first direction;
forming a gate structure of the transistor adjacent the channel region and extending lengthwise in a second direction perpendicular to the first direction;
forming a first conductor of a capacitive device, wherein the first conductor is stacked on the transistor and extends above the transistor in the first direction;
forming a dielectric material of the capacitive device on the first conductor; and
forming a second conductor of the capacitive device on a side of the dielectric material opposite the first conductor, wherein the second conductor extends lengthwise in a third direction perpendicular to the first direction and the second direction.