Patent ID: 11861278
Assignee: KEPLER COMPUTING INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. A system comprising:
a memory to store one or more instructions;
a processor coupled to the memory, wherein the processor is to execute the one or more instructions; and
a communication interface to allow the processor to communicate with another device, wherein the processor is to:
receive one or more inputs including a majority or minority inverter graph and a list of fan-ins for majority gates or minority gates, wherein the list of fan-ins includes variable fan-ins;
simulate the majority or minority inverter graph;
annotate an individual non-terminal node of the majority or minority inverter graph with an input signal, wherein to annotate the individual non-terminal node is based on simulation of the majority or minority inverter graph; and
iteratively process a list of non-terminal nodes of the majority or minority inverter graph, wherein the list of non-terminal nodes includes the individual non-terminal node of the majority or minority inverter graph, and wherein to iteratively process the list of non-terminal nodes generates a pruned majority or minority inverter graph.