Patent ID: 11887975
Assignee: DAICEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor device manufacturing method comprising:
a preparation step of preparing a reinforced wafer having a laminated structure that includes a wafer including an element forming surface and a back surface opposite therefrom, a supporting substrate, and a temporary adhesive layer forming temporary adhesion, the temporary adhesive layer being provided between the supporting substrate and a side of the element forming surface of the wafer;
a thinning step in which the wafer of the reinforced wafer is ground from a side of the back surface, forming a thinned wafer;
a bonding step in which a surface of the reinforced wafer and a surface of another wafer having an element forming surface and a back surface opposite therefrom are bonded, forming a wafer laminate;
a removal step of removing the supporting substrate from the wafer laminate; and
a multilayering step in which a surface of the wafer laminate that has been subjected to the removal step is bonded to a surface of another wafer laminate, forming a second wafer laminate from the wafer laminate and the another wafer laminate; wherein
the second wafer laminate obtained through the multilayering step has a laminated configuration that is symmetric in a thickness direction thereof.