Patent ID: 11962305
Assignee: NXP B.V.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 9:
10. The true random number generator circuit of claim 8, wherein the synchronization circuit comprises:
a NOR logic gate having a first input coupled to the node between two adjacent stages, a second input coupled to receive a first clock signal, and an output;
an OR logic gate having a first input coupled to the output of the NOR logic gate, a second input coupled to receive a second clock signal, and an output;
a first NAND logic gate having a first input coupled to the node between two adjacent stages, a second input coupled to receive the first clock signal, and an output;
a second NAND logic gate having a first input coupled to the output of the first NAND logic gate, a second input coupled to receive the second clock signal, and an output;
a first counter having an input coupled to the output of the OR logic gate, and an output; and
a second counter having an input coupled to the output of the second NAND logic gate, and an output.