Patent ID: 11862220
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 19:
20. A memory device comprising:
a substrate;
a gate structure comprising a first gate dielectric layer, a ferroelectric layer, and a gate layer stacked on the substrate;
a first source/drain disposed at one side of the gate structure;
a second source/drain disposed at another side of the gate structure;
a ground line in contact with the first source/drain and extending in a first horizontal direction;
a bit line in contact with the second source/drain and extending in the first horizontal direction;
a first channel and a second channel each contacting the gate structure, and each extending in a vertical direction from the gate structure;
a channel connection layer disposed on the gate layer, the channel connection layer connecting the first channel to the second channel, and contacting the gate structure;
a selection word line disposed between the first channel and the second channel and extending in a second horizontal direction;
a second gate dielectric layer extending between the first channel and the selection word line, between the second channel and the selection word line, and between the channel connection layer and the selection word line;
a cell word line disposed on top of the first channel and top of the second channel; and
a third gate dielectric layer disposed between the cell word line and the selection word line.