Patent ID: 11971448
Assignee: CEREMORPHIC, INC.
Field: Measurement (Instruments)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A process for scanning combinatorial logic, the combinatorial logic having:
a Scan_test_Mode input having a functional mode and a test mode;
a functional logic input and a functional logic output;
a multiplexer selecting between the functional logic output and a test input according to the Scan_test_Mode input, the multiplexer coupling a selection to a mux output;
a low threshold voltage master latch (LTVML) having an input coupled to the mux output, the LTVML generating an output coupled to the functional logic input;
a standard threshold voltage slave latch (STVSL) having an input coupled to the LTVML output and configured to provide a test output for a subsequent scan chain element;
a master functional clock (M_F_CLK) input and master test clock (M_T_CLK) input coupled to the LTVML, the LTVML latching the mux output when the M_T_CLK is 1 and the M_F_CLK is 0;
the process comprising:
when the Scan_test_Mode input is in a functional mode:
coupling to the STVSL a slave functional clock (S_F_CLK) and a slave test clock (S_T_CLK);
the STVSL latching the LTVML output when the S_T_CLK is 1 and the S_F_CLK is 0;

when the Scan_test_Mode input is in a test mode:
causing the S_T_CLK and S_F_CLK to be inactive;
causing the multiplexer to select the functional logic output;
causing the S_T_CLK to be 180 degrees out of phase from the S_F_CLK.