Patent ID: 11862234
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. A memory system comprising:
a memory device; and
a memory controller configured to transmit first input data to the memory device through a first data line and a second data line,
wherein the memory device comprises:
a first data line driver circuit configured to determine bit values of the first input data received through the first data line based on a first reference voltage set; and
a second data line driver circuit configured to determine bit values of the first input data received through the second data line based on a second reference voltage set,
wherein the first reference voltage set includes a first upper reference voltage and a first lower reference voltage, and
wherein the second reference voltage set includes a second upper reference voltage different from the first upper reference voltage and a second lower reference voltage different from the first lower reference voltage.