Patent ID: 11910733
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A method comprising:
forming a plurality of bottom electrodes;
forming a first dielectric layer, wherein the first dielectric layer continuously extends to regions directly over the plurality of bottom electrodes, and wherein an entirety of the first dielectric layer is formed of a homogeneous material;
forming a plurality of Phase-Change Random Access Memory (PCRAM) regions, each being in contact with a surface of the first dielectric layer that is formed of the homogeneous material;
forming a plurality of top electrodes over and electrically connected to the plurality of PCRAM regions; and
forming a plurality of filaments in the first dielectric layer, wherein the plurality of filaments are in contact with the plurality of PCRAM regions.