Patent ID: 11887659
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. An apparatus comprising:
a. memory array comprising a plurality of banks wherein each bank of the plurality of banks includes a plurality of mats each including a respective first mat;
a first plurality of main data lines each coupled to the plurality of banks and each configured to receive read data from the plurality of banks, wherein the first plurality of main data lines includes a first main data line:
a second plurality of main data lines each coupled to a subset of the plurality of banks and configured to provide write data to the subset of the plurality of banks, wherein each of the first plurality of main data lines is further configured to provide the write data to a remaining set of the plurality of banks, wherein the remaining set of the plurality of banks is exclusive of the subset of the plurality of banks, wherein the second plurality of main data lines includes a second main data line, wherein the second main data line is configured to write data only to the respective first mats of the subset of the plurality of banks, and wherein the first main data line is configured to write data only to the respective first mats of the remaining set of the plurality of banks;
a plurality of local data lines;
a plurality of sub-amplifiers coupled between the plurality of local data lines and the first plurality of main data lines and the second plurality of main data lines;
a plurality of bit lines coupled to memory cells of the memory array;
a plurality of sense amplifiers coupled between the local data lines and the bit lines;, a global data bus coupled to the first plurality of main data lines and the second plurality, of main data lines; and
an input/output circuit coupled to the global data bus.