Patent ID: 11929258
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A method comprising:
providing a first interlayer dielectric layer that includes a first metal line, a second metal line, a first polymeric feature disposed on the first metal line and a second polymeric feature disposed on the second metal line;
forming a second interlayer dielectric layer on the first interlayer dielectric layer;
forming a first hole through the second interlayer dielectric layer to expose a portion of a top surface of the first interlayer dielectric layer and the second polymeric feature;
removing at least a portion of the exposed second polymeric feature to expose the second conductive feature;
forming a trench within the second interlayer dielectric layer that overlaps with the hole;
forming a metal material in the trench and the hole.