Patent ID: 11862700
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 2:
3. A method for forming a semiconductor device structure, comprising:
forming a first dielectric wall between a plurality of first semiconductor layers and a plurality of second semiconductor layers, wherein the plurality of first and second semiconductor layers are vertically stacked and parallelly arranged;
forming a second dielectric wall adjacent to the plurality of first semiconductor layers;
forming a third dielectric wall adjacent to the plurality of second semiconductor layers;
forming a dummy material over the first dielectric wall, the second dielectric wall, the third dielectric wall, and the plurality of first and second semiconductor layers, wherein the dummy material is deposited so that the dummy material over the second and third dielectric walls and the dummy material over each of plurality of first and second semiconductor layers are merged, and the dummy material partially fills regions between adjacent first semiconductor layers and regions between adjacent second semiconductor layers such that an air gap is formed in the regions between adjacent first semiconductor layers of the plurality of first semiconductor layers and regions between adjacent second semiconductor layers of the plurality of second semiconductor layers; and
after forming a dummy material over the first dielectric wall, the second dielectric wall, the third dielectric wall, and the plurality of first and second semiconductor layers, performing an etch-back process so that a top of the dummy material is recessed to a level between a top surface and a bottom surface of a topmost first semiconductor layer of the plurality of first semiconductor layers.