Patent ID: 11948938
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. A method of forming a semiconductor device, comprising:
performing a first etch into a substrate to form a recess;
depositing a gate dielectric layer lining and partially filling the recess, and further overlying a top surface of the substrate;
performing a planarization into the gate dielectric layer until a top surface of the gate dielectric layer is level with the top surface of the substrate;
depositing a conductive layer covering the gate dielectric layer and filing a remainder of the recess after the planarization;
forming a mask overlying the conductive layer and the recess;
performing a second etch into the conductive layer with the mask in place to form a gate electrode overlying the gate dielectric layer;
doping the substrate to form a source region and a drain region respectively on opposite sides of the gate electrode and spaced from the gate dielectric layer;
depositing an interlayer dielectric (ILD) layer covering the source and drain regions and the mask;
performing a second planarization into the ILD layer to expose the mask; and
removing the mask to form an opening exposing the gate electrode.