Patent ID: 11895851
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 24:
25. A method, comprising:
identifying at least one cell of a memory array, the memory array comprising a plurality of tiles each tile of the plurality of tiles comprising a plurality of sub-blocks and a plurality of decks, wherein each sub-block of the plurality of sub-blocks comprises a plurality of memory cells of the memory array addressable via a plurality of word lines and a plurality of bit lines, the plurality of bit lines comprising a first bit line coupled with a first deck and a second deck of the plurality of decks, a second bit line coupled with a third deck and a fourth deck of the plurality of decks, and a third bit line coupled with a fifth deck and a sixth deck of the plurality of decks; and
accessing the at least one cell of the memory array using a plurality of bit line decoders positioned beneath the memory array wherein a first bit line decoder of the plurality of bit line decoders is coupled with the first bit line using a first configuration of sockets within a first subset of the plurality of sub-blocks, a second bit line decoder of the plurality of bit line decoders is coupled with the second bit line using a second configuration of sockets within a second subset of the plurality of sub-blocks, and a third bit line decoder of the plurality of bit line decoders is coupled with the third bit line using a third configuration of sockets within a third subset of the plurality of sub-blocks.