Patent ID: 11960718
Assignee: STMICROELECTRONICS (GRENOBLE 2) SAS
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 20:
21. A system, comprising:
a processing device; and
a bitwise programmable non-volatile memory coupled to the processing device and including memory management circuitry, wherein the memory management circuitry, in operation, responds to a request from the processing device to store new data at a memory location of the bitwise programmable non-volatile memory by:
sensing data stored at the memory location of the bitwise programmable memory;
comparing bits of the sensed data with bits of the new data;
generating an indication of a cost difference between:
a first burst of bitwise programming operations associated with programming bits of the new data which are different from bits of the sensed data; and
a second burst of bitwise programming operations associated with programming bits of a complementary inversion of the new data which are different from bits of the sensed data; and

executing one of the first burst of bitwise programming operations or the second burst of bitwise programming operations based on the generated indication of the cost difference wherein, when a size of the memory location is smaller than a size of a memory word including the memory location, and an inversion flag associated with the memory word has to be programmed, the cost difference takes into account programming operations for inverting of all the other bits belonging to the memory word outside of the memory location, and the programming burst comprises programming all the other bits at a complementary inverted state.