Patent ID: 11868654
Assignee: RENESAS ELECTRONICS CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A semiconductor device comprising:
a nonvolatile memory cell including a plurality of first memory cells and a plurality of second memory cells;
a bit latch; and
a saved register, wherein
in a first writing operation, first writing data are simultaneously stored in both the bit latch and the saved register, and writing to the plurality of first memory cells is executed on a basis of the first writing data stored in the bit latch,
during the first writing operation, in response to the first writing operation being interrupted on a basis of a suspension command, a second writing operation is executed,
in the second writing operation, second writing data are stored in the bit latch, and writing to the plurality of second memory cells is executed on a basis of the second writing data, and
after the second writing operation is ended, the first writing data of the saved register is reset to the bit latch on a basis of a resume command, and the interrupted first writing operation is restarted on a basis of the first writing data reset to the bit latch.