Patent ID: 11972810
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory apparatus, comprising:
memory cells each connected to one of a plurality of word lines and disposed in strings and configured to retain a threshold voltage corresponding to one of a plurality of data states; and
a control means coupled to the plurality of word lines and the strings and configured to:
apply a program voltage to each one of selected ones of the plurality of word lines while applying one of a plurality of pass voltages to unselected ones of the plurality of word lines and ramp down both the one of the selected ones of the plurality of word lines and the unselected ones of the plurality of word lines to a recovery voltage at a start of a verify phase of each of a plurality of program loops and apply one of a plurality of targeted word line biases to each of the plurality of word lines during the verify phase, and
adjust the recovery voltage based on the one of the plurality of targeted word line biases applied to each of the plurality of word lines during the verify phase.