Patent ID: 11929111
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 1:
2. The sense amplifier of claim 1, wherein the plurality of switches of the control circuit comprise:
a first switch, a first terminal of the first switch being connected to the first node, and a second terminal of the first switch being connected to a gate of the first PMOS transistor;
a second switch, a first terminal of the second switch being connected to the gate of the first PMOS transistor, and a second terminal of the second switch being connected to the second node;
a third switch, a first terminal of the third switch being connected to a gate of the second PMOS transistor, and a second terminal of the third switch being connected to the first node;
a fourth switch, a first terminal of the fourth switch being connected to the second node, and a second terminal of the fourth switch being connected to the gate of the second PMOS transistor;
a fifth switch, a first terminal of the fifth switch being connected to the first bitline, and a second terminal of the fifth switch being connected to the first node; and
a sixth switch, a first terminal of the sixth switch being connected to the second bitline, and a second terminal of the sixth switch being connected to the second node,
wherein in the first offset compensation stage of the sense amplifier, the first switch, the fourth switch, the fifth switch and the sixth switch are turned on, and the second switch and the third switch are turned off.