Patent ID: 11869570
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. The refresh counter circuit of claim 1, wherein
the second counter comprises a plurality of flip-flops and a plurality of inverters; an output Q port of a flip-flop for a lower bit is connected to a clock CLK port of a flip-flop for a bit which is higher than the lower bit by one; an output Q port of each of the flip-flops is connected to an input terminal of an inverter, an output terminal of which is connected to an input D port of the flip-flop; a clock CLK port of a lowest bit flip-flop is connected to an output terminal of the second signal generator to receive the second carry signal; the output Q port of each of the flip-flops is connected to an input terminal of the output unit, and outputs the second output signal to the output unit.