Patent ID: 11961762
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A method comprising:
forming a metal pad;
depositing a passivation layer over and contacting the metal pad;
forming a patterned planarization layer on the passivation layer;
performing a first etching process to etch through the passivation layer;
performing a second etching process to laterally recess the passivation layer, wherein a first top surface of the passivation layer is exposed;
performing a third etching process to etch the passivation layer that has been laterally recessed, so that the passivation layer has a second top surface, and the second top surface is lower than the first top surface, wherein during the second etching process and the third etching process, the patterned planarization layer is exposed to respective etching chemicals; and
depositing a metal seed layer extending into the passivation layer, wherein the metal seed layer is in contact with both of the first top surface and the second top surface.