Patent ID: 11923035
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A pseudo dual port memory device comprising:
a first column line;
a second column line which is different from the first column line;
a write driver connected to both of the first and second column lines; and
a sense amp connected to both of the first and second column lines,
wherein the first column line includes:
a first memory cell;
a pair of first bit lines connected to the first memory cell;
a first column multiplexer connected to the first bit lines and configured to connect the first bit lines to the write driver in response to a first write multiplexer control signal and connect the first bit lines to the sense amp in response to a first read multiplexer control signal; and
a first bit line precharge circuit configured to precharge the first bit lines in response to the first write multiplexer control signal and the first read multiplexer control signal, and

wherein the second column line includes:
a second memory cell;
a pair of second bit lines connected to the second memory cell;
a second column multiplexer connected to the second bit lines and configured to connect the second bit lines to the write driver in response to a second write multiplexer control signal and connect the second bit lines to the sense amp in response to a second read multiplexer control signal; and
a second bit line precharge circuit configured to precharge the second bit lines in response to the second write multiplexer control signal and the second read multiplexer control signal.