Patent ID: 11875050
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A memory device comprising:
a page buffer with a plurality of latches, the page buffer configured to store first logic page data, second logic page data, and third logic page data in a portion of the plurality of latches, respectively; and
a data pattern manager configured to control the page buffer to convert original data into variable data by moving the first to third logic page data of the original data between the latches,
wherein, when the original data is converted into the variable data, the data pattern manager is configured to control the page buffer to generate the variable data with data a plurality of combinations that are divided into a plurality of groups according to a number of a first level bit included in the first to third logic page data, and
wherein the number of the first level bits of data combinations included in each of the plurality of the groups among the plurality of data combinations is the same.