Patent ID: 11973008
Assignee: ALLEGRO MICROSYSTEMS, LLC
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 5:
6. A method for providing a leadless signal isolator IC package, comprising:
employing a leadframe including a die paddle having first and second surfaces, wherein the first and second surfaces are on opposite sides of the die paddle and are parallel to each other the first surface to support a die and the second surface being exposed on an exterior surface of the IC package; and
employing a die supported by the die paddle, the die having a width,
wherein a width of the second surface of the die paddle is less than the width of the die along an entire length of the die and edges of the die along the length of the die are outside of edges of the exposed second surface of the die paddle, and
wherein a width of the first surface of the die paddle is greater than the width of the die along the entire length of the die.