Patent ID: 11941404
Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. The processor of claim 6, wherein
multiple sets are stored in the third register,
each of the multiple sets includes the first value and the second value,
the multiple sets are arranged in line,
the processor is configured to read, in accordance with the single instruction, the first value and the second value of a set stored in a predetermined area of the third register as the first value for use in the multiplication processing and the second value for use in the replacement processing, respectively, and
the processor is configured to further perform, in accordance with the single instruction, shift processing including shifting, in one direction, the multiple sets stored in the third register such that a set stored in an area adjacent to the predetermined area moves to the predetermined area.