Patent ID: 11942549
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of manufacturing a semiconductor device, the method comprising:
lining a semiconductor fin with a first liner;
lining the semiconductor fin with a second liner different from the first liner;
lining the semiconductor fin with a third liner different from the second liner;
annealing the third liner to form silicon oxide;
lining the semiconductor fin with a fourth liner different from the third liner;
depositing a capping layer over the fourth liner;
annealing the capping layer to transform the capping layer to silicon oxide;
depositing a dielectric cap over the capping layer;
planarizing the dielectric cap to the semiconductor fin; and
exposing a sidewall of the semiconductor fin.