Patent ID: 11886272
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. A memory device, comprising:
a plurality of control receiver circuits to receive control information including first control information and second control information;
a plurality of data transmitter circuits to transmit data stored in a memory array to a controller; and
a first steering circuit coupled to the memory array and the plurality of data transmitter circuits, the first steering circuit to, based on the first control information received via the plurality of control receiver circuits, select between concurrently routing data received from the memory array across all of the plurality of data transmitter circuits when all of the plurality of data transmitter circuits are enabled and to employ at least partial serialization to route the data received from the memory array to a first subset of the plurality of data transmitter circuits when a second subset of the plurality of data transmitter circuits are disabled in response to the first control information the first subset and the second subset to be disjoint, the first steering circuit also to, based on the second control information, loopback data received via at least one of the plurality of data transmitter circuits.