Patent ID: 11915978
Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A manufacturing method for a transistor, comprising:
(i) forming a nucleation layer on a first substrate;
(ii) forming a sacrificial layer on the nucleation layer;
(iii) forming a gate isolation layer on the sacrificial layer;
(iv) forming a channel layer of a first nitride semiconductor on the gate isolation layer, wherein forming the channel layer comprises growing crystals in a c-axis direction;
(v) forming a barrier layer of a second nitride semiconductor on the channel layer, wherein forming the barrier layer comprises growing crystals in the c-axis direction;
(vi) forming a first bonding layer on the barrier layer;
(vii) forming an etching stop layer on a second substrate made of a semiconductor with no nitrogen contained;
(viii) forming a second bonding layer on the etching stop layer;
(ix) bonding the first substrate and the second substrate by bonding the second bonding layer to the first bonding layer;
(x) removing the first substrate;
(xi) exposing a surface of the gate isolation layer by removing the sacrificial layer;
(xii) forming, after the sacrificial layer is removed, a first groove and a second groove through the barrier layer and the channel layer, wherein a region in which a gate electrode is to be formed is interposed between the first groove and the second groove; and
(xiii) forming, in the first groove and the second groove, respectively, a source region and a drain region in contact with the channel layer by regrowing a semiconductor with no nitrogen contained in which impurities are injected from a side of a bottom surface of the first groove and from a side of a bottom surface of the second groove.