Patent ID: 11962299
Assignee: HANGZHOU GEO-CHIP TECHNOLOGY CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  Y | IPC H

Claim 0:
1. A fractional frequency divider, comprising a counter, a multiplexer, and a delay module, wherein
the multiplexer has signal control terminals respectively connected to output terminals of the counter and configured to enable clock signals received at signal input terminals of the multiplexer to be transferred to a signal output terminal of the multiplexer, the clock signals received at the signal input terminals having the same clock period and the same duty cycle;
the delay module has a clock signal input terminal connected to the signal output terminal of the multiplexer, and is configured to delay, in a steady state, a first clock signal received at the clock signal input terminal to output a second clock signal via a clock signal output terminal of the delay module;
the counter has a clock signal input terminal connected to the clock signal output terminal of the delay module, and is configured to perform cyclic count based on the second clock signal received at the clock signal input terminal of the counter; and
the delay module comprises a plurality of delay units and a driver connected in series, and is configured to generate a signal selection window and perform calibration.