Patent ID: 11955180
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 18:
19. A memory, comprising:
an array of memory cells comprising a string of series-connected split-gate memory cells, wherein each split-gate memory cell of the string of series-connected split-gate memory cells comprises a first memory cell portion and a second memory cell portion on opposing sides of a semiconductor pillar; and
a controller for access of the array of memory cells, wherein the controller is configured to cause the memory to:
during a first programming operation:
enable the second memory cell portion of a selected split-gate memory cell of the string of series-connected split-gate memory cells for programming for the first programming operation;
apply a plurality of first programming pulses to a control gate of the second memory cell portion of the selected split-gate memory cell;
perform a verify operation on the second memory cell portion of the selected split-gate memory cell to determine whether it is deemed to have reached a desired threshold voltage; and
in response to determining that the second memory cell portion of the selected split-gate memory cell is deemed to have reached the desired threshold voltage, disable the second memory cell portion of the selected split-gate memory cell from programming for the first programming operation; and

during a second programming operation occurring after the first programming operation:
enable the first memory cell portion of the selected split-gate memory cell for programming for the second programming operation; and
apply a second programming pulse to a control gate of the first memory cell portion of the selected split-gate memory cell.