Patent ID: 11934824
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 8:
9. A memory system, comprising:
at least one memory array; and
logic coupled to the at least one memory array, the logic comprising a sequencer and a sense amplifier array, the logic configured to:
receive, at the sequencer, an input including a number of bits; and
receive, at the sense amplifier array, a row of a memory array of the at least one memory array, the row comprising groups of bits, wherein each bit of the group of bits is received at the logic substantially simultaneously;
multiply each bit of each group of bits of the groups of bits by each bit of the input to generate a number of groups of scaled rows, each scaled row of each group of scaled rows of the number of groups of scaled rows including a number of columns and each scaled row of each group of scaled rows of the number of groups of scaled rows shifted at least one column position relative to an adjacent scaled row within an associated group of scaled rows; and
sum scaled rows across columns within each group of scaled rows to generate an output row.