Patent ID: 11915135
Assignee: ZHEJIANG LAB
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. The graph compiling and optimization method for neural network computation according to claim 5, wherein defining the condition of inserting the route selector specifically is that: when a predecessor node of a junction node of multiple paths of computation flow of the computation graph constitutes two or more different sub-graphs and each of the sub-graphs comprises a definition node of the redefined variable, a condition 1 and a condition 2 are simultaneously satisfied and the route selector for the redefined variable is inserted at the definition node of the redefined variable of the computation graph;
the condition 1 is that connecting edges exist between the different sub-graphs and the junction node of multiple paths of computation flow of the computation graph and the connecting edges have a unique common node which is the junction node of multiple paths of computation flow of the computation graph; and
the condition 2 is that in one time of execution flow of the computation graph, the junction node of multiple paths of computation flow of the computation graph cannot simultaneously flow through the connecting edges between the different sub-graphs and the junction node of multiple paths of computation flow of the computation graph and can only select one of the connecting edges.