Patent ID: 11967556
Assignee: nan
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A system, comprising:
a three-dimensional array of memory devices comprising:
a stack structure comprising insulative materials interleaved with conductive materials;
a staircase structure within the stack structure and having steps comprising lateral ends of the conductive materials of the stack structure;
contacts with different height-to-width ratios from one another, the contacts extending toward steps at upper elevations of the staircase structure;
additional contacts extending to steps at lower elevations of the staircase structure; and
conductive extensions between the steps at the upper elevations of the staircase structure and a liner material of the contacts;

at least one processor in operable communication with the three-dimensional array of memory devices; and
at least one peripheral device in operable communication with the at least one processor.