Patent ID: 11914893
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. An apparatus, comprising:
an interface configured to receive memory access commands from a host and to send and receive data associated with the memory access commands, the interface comprising:
a command queue configured to store the memory access commands received by the interface;
a processor, comprising:
an execution unit;
a first queue configured to store a first subset of the memory access commands associated with a first priority;
a second queue configured to store a second subset of the memory access commands associated with a second priority; and
one or more command routers configured to obtain the memory access commands from the command queue, determine the first and second subsets of the memory access commands, and store the first and second subsets in the first and second queues, respectively;
a buffer coupled with the interface and configured to store the data associated with the memory access commands;
a storage memory comprising a plurality of memory cells;
a storage controller configured to move the data associated with the memory access commands between the buffer and the storage memory, the storage controller comprising:
a third queue associated with the first priority; and
a fourth queue associated with the second priority,
wherein the processor is configured to transfer the first subset of the memory access commands from the first queue at the storage controller to the third queue at the storage controller according to a first process and transfer, concurrent with transferring the first subset of the memory access commands from the first queue to the third queue, the second subset of the memory access commands from the second queue at the storage controller to the fourth queue at the storage controller according to a second process, wherein processing the first subset of the memory access commands and processing the second subset of the memory access commands are configured to be run concurrently by the execution unit according to a quantity of the memory access commands in the command queue for a prioritization between the first priority and the second priority.