Patent ID: 11948972
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 7:
8. A circuit, comprising:
a substrate;
a first device on the substrate, comprising:
a stack of first and second nano-sheet layers, wherein the first nano-sheet layers comprise a first semiconductor material and the second nano-sheet layers comprise a second semiconductor material different from the first semiconductor material;
first source/drain (S/D) epitaxial structures abutting end-portions of the stack of first and second nano-sheet layers; and
a first gate structure on the stack of first and second nano-sheet layers comprising a first dielectric and a second dielectric disposed on a top surface of one of the second nano-sheet layers, wherein the first dielectric is in contact with the top surface of one of the second nano-sheet layers and the first S/D epitaxial structures, and wherein sidewalls of the first dielectric are aligned with sidewalls of the one of the second nano-sheet layers; and

a second device on the substrate, comprising:
second S/D epitaxial structures on the substrate;
third nano-sheet layers comprising a third semiconductor material similar to the second semiconductor material, wherein the third nano-sheet layers are disposed between the second S/D epitaxial structures; and
a second gate structure surrounding the third nano-sheet layers and between the second S/D epitaxial structures, the second gate structure comprising a third dielectric.