Patent ID: 11887929
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An integrated circuit device, comprising:
a semiconductor substrate;
a metal interconnect structure comprising a plurality of metal interconnect layers over the semiconductor substrate;
an array of device structures disposed between two of the plurality of metal interconnect layers, wherein the device structures comprise top electrodes;
a hydrophobic dielectric that fills gaps between the device structures;
an interlayer dielectric disposed above the hydrophobic dielectric;
an interfacial layer of hydrophilic dielectric between the interlayer dielectric and the hydrophobic dielectric; and
top electrode vias connecting the top electrodes to conductors within an upper of the two metal interconnect layers;
wherein the top electrode vias rise from respective top electrodes and pass successively through the hydrophobic dielectric, the interfacial layer, and the interlayer dielectric.