Patent ID: 11966835
Assignee: NVIDIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. A system comprising:
an encoder to:
generate a compressed input activation vector;
generate a compressed weight vector; and
apply the compressed input activation vector and the compressed weight vector to a parallelism discovery unit;

a decoder to:
receive an encoded sequence; and
decode a column sequence and a row sequence of the encoded sequence into matched pairs of input activations and weights from the compressed input activation vector and the compressed weight vector, and into validity markers indicating which pairs match;

at least one computing element distinct from the parallelism discovery unit and comprising at least one multiply and accumulate unit to generate an output activation for the matched pairs;
the parallelism discovery unit to:
receive the compressed input activation vector and the compressed weight vector;
associate the input activations and the weights with channel indices;
compare and encode the channel indices as the encoded sequence including the column sequence and the row sequence; and
apply the channel indices to the at least one computing element.