Patent ID: 11888494
Assignee: NUVOTON TECHNOLOGY CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A semiconductor circuit including a data converter that outputs a digital output signal corresponding to a measured signal, the semiconductor circuit comprising:
an analog circuit that quantizes the measured signal inputted; and
a digital circuit that outputs the digital output signal,
wherein the analog circuit includes:
a correction element group including one or more correction elements each for correcting nonlinearity that occurs during a process of converting the measured signal into the digital output signal in the analog circuit; and
a test element group including one or more test elements for testing the one or more correction elements,

the digital circuit tests the correction element group using the test element group,
the digital circuit includes:
a self-diagnostic code generation circuit that generates a self-diagnostic code for (i) enabling or disabling each of the one or more correction elements included in the correction element group and (ii) enabling or disabling each of the one or more test elements included in the test element group;
an error detection circuit that detects, as an error signal, a difference between a quantizer output signal of the analog circuit and a predetermined threshold value, the quantizer output signal being outputted in response to the self-diagnostic code; and
a self-diagnostic circuit that generates a self-diagnostic signal indicating a diagnostic result of the correction element group, based on the error signal,

the digital circuit causes the self-diagnostic circuit to self-diagnose each of the one or more correction elements included in the correction element group,
the self-diagnostic code generation circuit has a first weight test code output mode and a second weight test code output mode,
in the first weight test code output mode, the self-diagnostic code generation circuit:
sets a first bit signal to 1 or 0, the first bit signal being for controlling a first correction element selected as a test target from the correction element group;
causes a second correction bit signal group to have an inverted logical value of the first bit signal, the second correction bit signal group being for controlling a correction element having an adjustment weight smaller than an adjustment weight of the first correction element;
causes a test bit signal to have the inverted logical value of the first bit signal, the test bit signal being for controlling the one or more test elements; and
outputs one or more other bit signals as one or more predetermined fixed signals,
in the second weight test code output mode, the self-diagnostic code generation circuit:
causes the first bit signal to have an inverted logical value when the first weight test code output mode is set;
causes the second correction bit signal group to have the inverted logical value of the first bit signal;
causes the test bit signal to have the inverted logical value of the first bit signal; and
outputs one or more other bit signals as one or more predetermined fixed signals, and
at time of testing, the digital circuit:
enters the first weight test code output mode and generates a first error signal, based on the error signal from the error detection circuit;
enters the second weight test code output mode and generates a second error signal, based on the error signal from the error detection circuit; and
calculates a difference between the first error signal and the second error signal, and performs a weighted diagnosis on the correction element group.