Patent ID: 11959956
Assignee: REALTEK SEMICONDUCTOR CORPORATION
Field: Measurement (Instruments)
Classification: CPC G | IPC G

Claim 4:
5. An electronic apparatus, configured to check a to-be-tested circuit, wherein the to-be-tested circuit comprises at least one first node related to a gate voltage of at least one transistor device and a plurality of second nodes, the electronic apparatus performs a circuit check method on the to-be-tested circuit, and the circuit check method comprises:
setting endpoint voltages of a plurality of input interface ports of the to-be-tested circuit;
obtaining a first node voltage of the first node according to a conduction path of the to-be-tested circuit and the gate voltage of the transistor device, wherein the first node voltage comprises a first maximum value and a first minimum value of the first node;
obtaining a second node voltage of each second node through analysis according to the conduction path, the endpoint voltages, and the first node voltage; and
performing circuit static check on the to-be-tested circuit by applying the first node voltage and the second node voltage;
wherein the transistor device is a metal oxide semiconductor (MOS) device, and the MOS device is an N-type MOS (NMOS) device, a P-type MOS (PMOS) device, or any combination of the NMOS device and the PMOS device;
wherein when the MOS device is the NMOS device and is turned on, a source voltage maximum value of the NMOS device is a smaller one in a difference between a gate voltage maximum value and a threshold voltage and a drain voltage maximum value of the NMOS device, and is taken as the first maximum value; and a drain voltage minimum value of the NMOS device is a source voltage minimum value, and is taken as the first minimum value; and
when the MOS device is the PMOS device and is turned on, a drain voltage maximum value of the PMOS device is a source voltage maximum value, and is taken as the first maximum value; and a source voltage minimum value of the PMOS device is a larger one in a difference between a gate voltage minimum value and a threshold voltage and a drain voltage minimum value of the PMOS device, and is taken as the first minimum value.