Patent ID: 11935602
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G  H

Claim 0:
1. A memory device, comprising:
an array of memory cells;
a plurality of registers, wherein each register of the plurality of registers corresponds to a respective memory device of a plurality of memory devices containing the memory device, wherein each register of the plurality of registers is configured to store an expected peak current magnitude of its respective memory device, wherein the plurality of registers comprises a plurality of subsets of registers, and wherein a particular subset of memory devices of the plurality of subsets of memory devices contains the memory device; and
a controller for access of the array of memory cells, wherein the controller is configured to cause the memory device to:
determine whether the memory device is expecting to initiate a next phase of an access operation on the array of memory cells;
in response to determining that the memory device is expecting to initiate the next phase of the access operation:
generate a first sum of the respective expected peak current magnitudes of each register of the plurality of registers other than the respective register of the memory device, and an expected peak current magnitude for the next phase of the access operation in the selected operating mode;
generate a second sum of the respective expected peak current magnitudes of each register of the particular subset of registers other than the respective register of the memory device, and an expected peak current magnitude for the next phase of the access operation in the selected operating mode;
compare the first sum to a first current demand budget for the plurality of the memory devices;
compare the second sum to a second current demand budget for the particular subset of memory devices, wherein the second current demand budget is less than the first current demand budget; and
in response to the first sum being less than or equal to the first current demand budget and the second sum being less than or equal to the second current demand budget, initiate the next phase of the access operation in the selected operating mode.