Patent ID: 11955981
Assignee: MICRON TECHNOLOGY, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 18:
19. A method, comprising:
at a primary memory die of a three-dimensional stack of a memory device, receiving a clock from a host device;
in the primary memory die, dividing the clock to generate a divided clock;
in the primary memory die, dividing the divided clock to generate a plurality of lower frequency clocks having a frequency lower than a frequency of the divided clock;
transmitting the plurality of lower frequency clocks from the primary memory die to one or more internal memory die in the three-dimensional stack of the memory device using first inter-die interconnects;
at one or more internal memory die of the three-dimensional stack, receiving the plurality of lower frequency clocks from the primary memory die over the first inter-die interconnects;
in the one or more internal memory die, reconstructing the divided clock from the received lower frequency clocks; and
in the one or more internal memory die, decoding command and address bits using the reconstructed divided clock.