Patent ID: 11869847
Assignee: ICOMETRUE COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. A multichip package comprising:
a first circuit substrate;
a solder bump on a bottom surface of the first circuit substrate and at a bottom of the multichip package;
a first chip package over a top surface of the first circuit substrate and coupling to the first circuit substrate, wherein the first chip package comprises a second circuit substrate over the top surface of the first circuit substrate, a first metal bump between the first and second circuit substrates and coupling the first circuit substrate to the second circuit substrate, and a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip over the second circuit substrate and coupling to the second circuit substrate; and
a second chip package over the top surface of the first circuit substrate, at a same horizontal level as the first chip package and coupling to the first circuit substrate, wherein the second chip package comprises a third circuit substrate over the first circuit substrate, a second metal bump between the first and third circuit substrates and coupling the first circuit substrate to the third circuit substrate, a non-volatile memory (NVM) integrated-circuit (IC) chip over the third circuit substrate and coupling to the third circuit substrate, wherein the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip is to be configured in accordance with configuration data stored in the non-volatile memory (NVM) integrated-circuit (IC) chip.