Patent ID: 11888479
Assignee: KEPLER COMPUTING INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 3:
4. The apparatus of claim 3, wherein the inverter is a first inverter, wherein the logic comprises:
a first NOR gate coupled to an output of the inverter, wherein the first NOR gate receives a second reset, wherein the second reset is inverse of the first reset, wherein an output of the first NOR gate is coupled to a 5-input majority gate of the 1-bit full adder, and wherein the second reset is to condition the output of the first NOR gate during the reset phase;
a second inverter which is coupled to the 3-input majority gate; and
a second NOR gate coupled to an output of the second inverter, wherein the second NOR gate is controllable by the second reset, wherein an output of the second NOR gate is a carry output, and wherein the second reset is to condition the output of the second NOR gate during the reset phase.