Patent ID: 11916555
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. A circuit comprising:
n flip-flop circuits, where n is an integer greater than 1, each of the n flip-flop circuits configured to receive a primary clock signal, a first section of each of the n flip-flop circuits being configured to generate a clock buffer signal having a series of pulses, each delayed by a set amount of time relative to a corresponding pulse of the primary clock signal, generate an intermediate clock signal based on the primary clock signal and the clock buffer signal, generate an inflated low pulse width clock signal having a low pulse width that is greater than a low pulse width of the primary clock signal, and generate a complement inflated low pulse width clock signal, the inflated low pulse width clock signal and the complement inflated low pulse width clock signal being applied internally in the circuit;
wherein each of the n flip-flop circuits is further configured to generate, based on the primary clock signal and the clock buffer signal, an inflated high pulse width clock signal having a high pulse width that is greater than a high pulse width of the primary clock signal, and generate a complement inflated high pulse width clock signal, the inflated high pulse width clock signal and the complement inflated high pulse width clock signal being applied internally in the circuit.