Patent ID: 11971638
Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 8:
9. A semiconductor device comprising:
first to ninth transistors,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein the one of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the third transistor,
wherein the one of the source and the drain of the first transistor is electrically connected to a first wiring,
wherein one of a source and a drain of the fourth transistor is electrically connected to a gate of the first transistor,
wherein the one of the source and the drain of the fourth transistor is electrically connected to one of a source and a drain of the fifth transistor
wherein the one of the source and the drain of the fourth transistor is electrically connected to one of a source and a drain of the sixth transistor,
wherein one of a source and a drain of the seventh transistor is electrically connected to a gate of the second transistor,
wherein the one of the source and the drain of the seventh transistor is electrically connected to a gate of the fifth transistor,
wherein one of a source and a drain of the eighth transistor is electrically connected to a gate of the seventh transistor,
wherein one of a source and a drain of the ninth transistor is electrically connected to the gate of the seventh transistor,
wherein the other of the source and the drain of the second transistor is electrically connected to a second wiring,
wherein the other of the source and the drain of the third transistor is electrically connected to the second wiring,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the second wiring,
wherein the other of the source and the drain of the sixth transistor is electrically connected to the second wiring,
wherein the other of the source and the drain of the ninth transistor is electrically connected to the second wiring,
wherein the other of the source and the drain of the fourth transistor is electrically connected to a third wiring,
wherein a gate of the fourth transistor is electrically connected to a fourth wiring,
wherein the other of the source and the drain of the seventh transistor is electrically connected to a fifth wiring,
wherein a gate of the third transistor is electrically connected to a sixth wiring,
wherein a gate of the sixth transistor is electrically connected to the sixth wiring,
wherein the other of the source and the drain of the eighth transistor is electrically connected to a gate of the eighth transistor,
wherein the first wiring is configured to output a signal,
wherein the third wiring is configured to be supplied a first potential,
wherein the second wiring is configured to be supplied a second potential lower than the first potential, and
wherein the fifth wiring is configured to be supplied the first potential and the second potential.