Patent ID: 11862291
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. The memory device of claim 8, wherein the adder comprises:
an address generator including a first XOR gate performing XOR logic processing on two of the internal count value, the register value and the carry signal output by the bit counter of the lower bit and a second XOR gate performing XOR logic processing on a remainder of the internal count value, the register value and the carry signal output by the bit counter of the lower bit and an output of the first XOR gate; and
a carry generator including first, second and third NAND gates each of which performs NAND logic processing on one of three combinations each of which comprises two of the internal count value, the register value and the carry signal output by the bit counter of the lower bit, and a fourth NAND gate performing NAND logic processing on outputs of the first, second and third NAND gates.