Patent ID: 11972800
Assignee: EMEMORY TECHNOLOGY INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. The non-volatile memory cell array as claimed in claim 1, wherein the non-volatile memory cell array further comprises a second non-volatile memory cell, and the second non-volatile memory cell comprises:
a third select transistor, wherein a first source/drain terminal of the third select transistor is connected with the program source line, and a gate terminal of the third select transistor is connected with the first program word line;
a third floating gate transistor, wherein a first source/drain terminal of the third floating gate transistor is connected with a second source/drain terminal of the third select transistor, and a second source/drain terminal of the third floating gate transistor is connected with a second program bit line;
a fourth floating gate transistor, wherein a first source/drain terminal of the fourth floating gate transistor is connected with the read source line, and a floating gate of the fourth floating gate transistor is connected with a floating gate of the third floating gate transistor; and
a fourth select transistor, wherein a first source/drain terminal of the fourth select transistor is connected with a second source/drain terminal of the fourth floating gate transistor, a gate terminal of the fourth select transistor is connected with the first read word line, and a second source/drain terminal of the fourth transistor is connected with a second read bit line.