Patent ID: 11908805
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A package substrate, comprising:
a plurality of substrates and/or dielectric materials, wherein the plurality of substrates and/or dielectric materials includes:
a first substrate and/or dielectric material having a first surface, the first surface (i) being a topmost surface of the package substrate relative to all other substrates and/or dielectric materials of the plurality of substrates and/or dielectric materials, (ii) located at a first side of the package substrate, and (iii) including a die attach area, and
a second substrate and/or dielectric material having a second surface, the second surface (i) being a bottommost surface of the package substrate relative to all other substrates and/or dielectric materials of the plurality of substrates and/or dielectric materials and (ii) located at a second side of the package substrate opposite the first side; and

a ground plane positioned between the first surface and the second surface, wherein the ground plane is exposed via an opening in the bottommost surface.