Patent ID: 11967394
Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. The memory system of claim 16, wherein:
the memory column access circuit comprises:
a plurality of first column multiplexer circuits each coupled to a unique set of the plurality of first bit lines, and each coupled to a unique set of X number of the plurality of first flying bit lines, wherein ‘X’ is a positive integer greater than or equal to two (2);
the plurality of first column multiplexer circuits each configured to multiplex a first bit line among the coupled set of first bit lines and the coupled set of first flying bit lines to a corresponding first multiplex output; and

a plurality of second column multiplexer circuits each coupled to a unique set of the plurality of third bit lines, and each coupled to a unique set of X number of the plurality of second flying bit lines, wherein ‘X’ is a positive integer greater than or equal to two (2);
the plurality of second column multiplexer circuits each configured to multiplex a second bit line among the coupled set of third bit lines and the coupled set of second flying bit lines to a corresponding second multiplex output;

the memory driver circuit further configured to:
in response to the memory access request to the first memory sub-bank:
cause each first column multiplexer circuit of the plurality of first column multiplexer circuits to multiplex a first bit line among its coupled X first bit lines and its coupled X first flying bit lines to its corresponding first multiplex output; and

in response to the memory access request to the first memory sub-bank:
cause each second column multiplexer circuit of the plurality of second column multiplexer circuits to multiplex a second bit line among its coupled X third bit lines and its coupled X second flying bit lines to its corresponding second multiplex output.