Patent ID: 11947254
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Optics (Instruments)
Classification: CPC G | IPC G

Claim 4:
5. The system of claim 1, wherein, for calibrating the OPC model, the processor is further configured to:
form a test mask with test structures based on a test layout different from the device layout;
form a patterned layer on a substrate by using the test mask in a lithography process;
measure a contour or a critical dimension (CD) of the patterned layer;
generate a second grid pattern density map of the test layout;
receive a value of the first parameter indicative of the long-range effect, and a value of the second parameter indicative of the geometric feature of the structure or the manufacturing process;
measure a contour or CD of a patterned layer of the test layout; and
iterating: adjusting the value of the second parameter indicative of the geometric feature of the structure or the manufacturing process to a second value, calculating a mask pattern shape using a mask model including the second value indicative of the geometric feature, and calculating a new calculated contour or a new calculated CD of the test layout at least based on the calculated mask pattern shape, until a difference between the new calculated contour or the new calculated CD of the test layout and the measured contour or the measured CD of the patterned layer is within a predetermined range.