Patent ID: 11962309
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G  Y | IPC H

Claim 1:
2. The phase adjusting circuit of claim 1, wherein,
the detection circuit is configured to receive any three signals of the first clock signal, the second clock signal, a third clock signal and a fourth clock signal, and output the first detection signal and the second detection signal based on the received signals;
wherein, a phase difference between the third clock signal and the first clock signal is 180 degrees, a phase difference between the fourth clock signal and the second clock signal is 180 degrees, the first detection signal indicates a phase difference between a rising edge of the first clock signal and a rising edge of the second clock signal, and the second detection signal indicates a phase difference between the rising edge of the second clock signal and a falling edge of the first clock signal.