Patent ID: 11899607
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 2:
3. An apparatus comprising:
an interconnect to provide communication paths between agents coupled to the interconnect;
a coordination agent coupled to the interconnect and configured to perform an operation that requires sending, as a response to a single input request received from a requesting agent coupled to the interconnect, a request to each of a plurality of target agents selected for the operation from the agents coupled to the interconnect, and receiving a response from each of the plurality of target agents, the operation being unable to complete until the response has been received from each of the plurality of target agents; and
storage circuitry accessible to the coordination agent and configured to store, for each agent that the coordination agent may communicate with via the interconnect, a latency indication for communication between that agent and the coordination agent;
wherein:
the coordination agent is configured, prior to performing the operation, to determine a sending order in which to send the request to each of the plurality of target agents, the sending order being determined in dependence on the latency indication for each of the plurality of target agents;
the operation comprises a maintenance operation, and the request comprises a request to perform a maintenance action in respect of a respective microarchitectural structure for each of the target agents;
the input request comprises a cache coherency request issued by the requesting agent when seeking to access data at a target location in memory;
the maintenance operation comprises a cache coherency operation; and
the respective microarchitectural structure for each of the target agents comprises a data cache used to store a subset of data accessible in the memory.