Patent ID: 11943919
Assignee: nan
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A memory device, comprising:
a stack structure comprising vertically alternating conductive structures and insulating structures arranged in tiers;
a staircase structure at a horizontal end the stack structure, the staircase structure having steps comprising edges of the tiers;
a string driver transistor vertically overlying the staircase structures and comprising:
a channel region comprising at least one 2D material;
lateral double-diffused regions horizontally neighboring the channel region and comprising the at least one 2D material; and
source and drain regions horizontally neighboring the lateral double-diffused regions and comprising the at least one 2D material;

at least one additional conductive structure extending from and between the string driver transistor and one of the steps of the staircase structure; and
a string of memory cells vertically extending through the stack structure.