Patent ID: 11915745
Assignee: DXCORR DESIGN INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A method for optimizing leakage currents in SRAM comprising:
providing an array power header and a retention header within decoder slice(s) of each memory segment for controlling leakage currents within each of memory bitcells within the each memory segment, wherein the at least one array power header, the retention header and a pmos transistor connected to the retention header, are configured to control wake-up current and wake-up time of plurality of memory segments from deep sleep retention mode to normal mode;
segmenting power supply rails running in a second direction within each memory bitcell array to form one or more segmented power supply node; and
controlling mode of operations of one or more memory segments comprising the decoder slice(s) by controlling the power supply rails to the array power headers and the retention header within the decoder slice(s), wherein controlled mode of operations of the one or more memory segments results in reduced leakage currents within the each of the memory bitcells and wherein voltage of the power supply rails is lowered to higher than retention voltage.