Patent ID: 11940940
Assignee: GRAPHCORE LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 7:
8. A data processing device comprising:
a first processor, comprising a first instruction memory storing a first local program;
a second processor, comprising a second instruction memory storing a second local program, the first local program and the second local program together providing at least part of a computer program;
a first interface and a second interface enabling egress data packets to be provided to external devices;
a switching fabric comprising a first bus that is associated with the first processor and is configured to transport ones of the egress data packets that are output by the first processor, the switching fabric further comprising a second bus that is associated with the second processor and is configured to transport ones of the egress data packets that are output by the second processor,
first switching circuitry associated with the first interface and a first interface circuit associated with the first interface,
second switching circuitry associated with the second interface and a second interface circuit associated with the second interface,
wherein the first processor is configured to, in dependence upon a schedule indicated in the first local program, send a first message to the first interface circuit identifying the second processor,
wherein the first interface circuit is configured to, during a first phase of execution of the computer program, and in response to receipt of the first message, control the first switching circuitry to connect to the second bus so as to enable reception, at the first interface, of a first set of one or more egress data packets from the second processor,
wherein a third processor of the data processing device is configured to, in dependence upon the schedule or a different schedule, send a second message to the second interface circuit identifying the second processor,
wherein the second interface circuit is configured to, during a second phase of execution of the computer program, and in response receipt of the second message, control the second switching circuitry to connect to the second bus so as to enable reception, at the second interface, of a second set of one or more egress data packets from the second processor,
wherein the first interface circuit is configured to receive the first message by controlling the first switching circuitry to connect to the first bus, wherein the second interface circuit is configured to receive the second message by controlling the second switching circuitry to connect to the first bus.