Patent ID: 11930674
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. The method according to claim 14, further comprising: forming an array structure layer on the silicon-based substrate in the binding area, and forming an auxiliary pad assembly on the array structure layer in the binding area, wherein the auxiliary pad assembly is configured to be bound to a flexible printed circuit;
wherein forming the array structure layer on the silicon-based substrate in the display area and the binding area and forming the auxiliary pad assembly on the array structure layer in the binding area comprises:
forming a first insulating layer on the silicon-based substrate, wherein the first insulating layer in the display area is formed with a first via exposing the driving transistor of the silicon-based substrate, and the first insulating layer in the binding area is formed with a third via exposing the pad assembly of the silicon-based substrate;
forming a first conductive pillar in the first via and forming a third conductive pillar in the third via;
forming a reflective electrode and an auxiliary pad assembly on the first insulating layer, wherein the reflective electrode is arranged in the display area and connected with the driving transistor through the first conductive pillar, and the auxiliary pad assembly is arranged in the binding area and connected with the pad assembly through the third conductive pillar;
forming a second insulating layer, wherein the second insulating layer in the display area is formed with a second via exposing the reflective electrode; and
forming a second conductive pillar in the second via, wherein the second conductive pillar is connected with the reflective electrode.