Patent ID: 11934310
Assignee: CENTAUR TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A microprocessor, comprising:
plural cores, each of the cores comprising a level 1 (L1) cache and a level 2 (L2) cache; and
a shared level 3 (L3) cache comprising plural L3 tag array entries, wherein a first portion of the plural L3 tag array entries is associated with data in the shared L3 cache and a second portion of the plural L3 tag array entries is decoupled from data in the shared L3 cache and available in the L2 cache of one of the plural cores, wherein each L3 tag array entry comprises tag information and data zero information, the data zero information indicating whether any data associated with the tag information is known to be zero or not.