Patent ID: 11908855
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC B  H

Claim 14:
15. A semiconductor device, comprising:
a circuit area; and
an external dummy area adjacent the circuit area,
wherein the circuit area includes circuit active regions, circuit gate lines overlapping the circuit active regions in a vertical direction, and circuit source/drain regions,
wherein the external dummy area includes an external dummy active region, external dummy gate lines overlapping the external dummy active region in the vertical direction, and edge gate lines, the external dummy gate lines located between the edge gate lines and the circuit gate lines and isolated from direct contact with the circuit gate lines, wherein the external dummy active region has
a linear shape extending in a first horizontal direction, or
a shape including active portions isolated from direct contact with each other and extending sequentially in the first horizontal direction,

wherein the external dummy gate lines have a shape of lines of bars parallel to each other,
wherein at least portions of the edge gate lines are “U” shaped,
wherein the circuit active regions include
a first plurality of circuit active regions extending sequentially in the first horizontal direction, and
a second plurality of circuit active regions extending sequentially in a second horizontal direction perpendicular to the first horizontal direction,

wherein each circuit active region of the circuit active regions includes a circuit active pattern and circuit active layers on the circuit active pattern, the circuit active layers spaced apart from each other in the vertical direction and adjacent to the circuit source/drain regions, and
wherein the external dummy active region includes a dummy active pattern and dummy active layers on the dummy active pattern, the dummy active layers spaced apart from each other in the vertical direction.