Patent ID: 11968835
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A Vertical type semiconductor device, comprising:
a stacked structure disposed on a semiconductor substrate that includes a plurality of insulation layers and a plurality of first conducive patterns that are alternately and repeatedly stacked;
a plurality of channel holes passing through the stacked structure, and extending into an upper inner portion of the substrate;
a first structure including a blocking layer, a charge storage layer, and a tunnel insulation layer sequentially stacked on a surface of each of the channel holes, and
wherein the first structure includes an upper portion disposed on a sidewall of the stacked structure in the channel hole and a lower portion disposed under an upper surface of the substrate;
a channel layer on the first structure in the channel hole; and
a semiconductor layer interposed between the stacked structure and the substrate, wherein the semiconductor layer contacts the channel layers disposed between the upper portion of the first structure and the lower portion of the first structure, and the stacked structure is disposed on the semiconductor layer,
wherein a sidewall of each of the channel holes includes an inflection point where an inclination changes.