Patent ID: 11869572
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A system, comprising:
a memory array coupled between a first voltage and a second voltage;
a header device having a single power gating switch with only one transistor coupled in series between the first voltage and the memory array, wherein the only one transistor receives the first voltage as a positive supply voltage and provides an applied first voltage to the memory array based on the positive supply voltage, and wherein the only one transistor has a single gate;
a footer device that power gates the second voltage to the memory array as an applied second voltage;
a central biasing header stage with a plurality of transistors that are arranged and coupled together to receive the applied first voltage from the only one transistor and then selectively activate the header device with a negative voltage biasing signal by applying a feedback signal to the single gate of the single transistor based on sensing a changing voltage level of the applied first voltage; and
a central biasing footer stage that selectively activates the footer device based on sensing a changing voltage level of the applied second voltage,
wherein the central biasing header stage uses a leakage current drawn from a settled voltage level of the core supply voltage as a reference current to bias the central biasing header stage itself for regulating the applied core voltage without comparing the applied core voltage with an additional reference voltage.