Patent ID: 11935962
Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 6:
7. A semiconductor device comprising:
a first insulating layer comprising an oxide;
a second insulating layer comprising a nitride;
an oxide semiconductor layer over the first insulating layer and the second insulating layer, the oxide semiconductor layer comprising indium, gallium and zinc,
wherein the oxide semiconductor layer comprises a channel formation region and a low-resistance region having a lower resistance than the channel formation region;
a gate insulating layer over and in contact with the channel formation region of the oxide semiconductor layer;
a gate electrode over the channel formation region with the gate insulating layer therebetween;
a metal nitride layer over and in contact with the low-resistance region of the oxide semiconductor layer;
a third insulating layer over the metal nitride layer, the third insulating layer comprising hydrogen; and
a conductive layer over the third insulating layer,
wherein the conductive layer is in contact with the low-resistance region of the oxide semiconductor layer through an opening of the third insulating layer and an opening of the metal nitride layer.