Patent ID: 11923043
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: nan (nan)
Classification: CPC nan | IPC G  H

Claim 15:
16. A memory, comprising:
a clock generation circuit, configured to generate a first oscillation signal and a second oscillation signal, wherein the first oscillation signal and the second oscillation signal have a same frequency but opposite phases, and a duty cycle of the first oscillation signal and a duty cycle of the second oscillation signal are both within a first preset range; and
a differential input circuit, configured to receive a first external signal and a second external signal, and generate a first internal signal and a second internal signal; wherein the differential input circuit is further configured to receive the first oscillation signal and a second oscillation signal;
wherein the clock generation circuit is further configured to monitor at least one of a duty cycle of the first internal signal or a duty cycle of the second internal signal, and enable the at least one of the duty cycle of the first internal signal or the duty cycle of the second internal signal to be within a second preset range:
wherein the differential input circuit comprises:
a differential amplification circuit;
a second selector, wherein the first oscillation signal, the second oscillation signal, the first external signal and the second external signal are connected with the second selector, and wherein the first oscillation signal and the second oscillation signal are taken as a first differential signal pair, and the first external signal and the second external signal are taken as a second differential signal pair; and
wherein the second selector is configured to select one of the first differential signal pair and the second differential signal pair to be input into the differential amplification circuit.