Patent ID: 11966330
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. An apparatus, comprising:
processor circuitry, in a source cluster, to issue a cache coherence message to a target central processing unit (CPU) cluster by selection of a target cluster among two or more target clusters and issuance of the cache coherence message to the target cluster via a first path, wherein
the processor circuitry is to select the target CPU cluster based on a memory map data that specifies which target CPU cluster is physically closest to a die-to-die interconnect interface that is physically closest to the source cluster,
the processor circuitry is to select the target cluster from among the two or more target clusters by minimizing a number of die boundary traversals, and
the first path is to traverse a first die-to-die interconnect interface for the source cluster and a second die-to-die interconnect interface to the selected target cluster and

the processor circuitry is to receive a response to the cache coherence message and access a cache based on response, wherein the response comprises one or more of: no match, match with data, data shared, data exclusive owned and wherein the response traverses the first path but in an opposite direction to the source cluster from the selected target cluster.