Patent ID: 11862591
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 4:
5. A method, comprising:
providing a first semiconductor die including a first dielectric layer, wherein the first dielectric layer includes a first bond pad having a first top surface recessed with respect to a first surface of the first dielectric layer, and wherein a conductive buffer layer is disposed on the bond pad, the conductive buffer layer including aggregates of conductive particles and being flexible to deform in response to pressure applied to the conductive buffer layer;
providing a second semiconductor die including a second dielectric layer having a second surface, wherein the second dielectric layer includes a second bond pad having a second top surface;
attaching the first and second semiconductor dies such that the first surface is in contact with the second surface to form a bonding interface and the first bond pad is aligned to and facing the second bond pad; and
heating the first and second semiconductor dies attached to each other.