Patent ID: 11868773
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A processor for processing instructions, the processor comprising:
an instruction dispatch unit configured to dispatch instructions of a compare immediate-conditional branch instruction sequence, the compare immediate-conditional branch instruction sequence comprising a first instruction, a compare immediate instruction, and a conditional branch instruction;
a logical register mapper having a plurality of entries, each logical register mapper entry configured to map a logical register to a physical register entry in a physical register file;
an issue queue to hold the instructions dispatched from the instruction dispatch unit;
an execution unit to execute the instructions issued by the issue queue; and
a compare register having at least one entry to hold information in a plurality of fields,
wherein the processor is configured to:

write information from the first instruction of the compare immediate-conditional branch instruction sequence into one or more of the plurality of fields in the at least one entry in the compare register;
write, in response to the first instruction not being executed in the execution unit before the compare immediate instruction of the compare immediate-conditional branch instruction sequence is dispatched from the instruction dispatch unit, an immediate field and an ITAG of the compare immediate instruction into the at least one entry in the compare register;
write, in response to dispatching the conditional branch instruction of the compare immediate-conditional branch instruction sequence from the instruction dispatch unit, an inferred compare result value into the at least one entry in the compare register;
write, in response to executing the first instruction in the execution unit, a writeback result of the first instruction into a data field in the at least one entry in the compare register without executing in the execution unit the compare immediate instruction or the conditional branch instruction of the compare immediate-conditional branch instruction sequence;
compare the writeback result of the first instruction written into the data field in the at least one entry in the compare register to the immediate field of the compare immediate instruction written into the at least one entry in the compare register to generate a computed compare result value;
compare the computed compare result value to the inferred compare result value stored in the at least one entry in the compare register;
flush, in response to the computed compare result value not matching the inferred compare result value, instructions in the processor.