Patent ID: 11929139
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A method of optimizing the placement of memories in a memory device including a substrate and an electrical component electrically coupled to the substrate, the method comprising:
testing the memories to determine at least one parameter for each of the memories, wherein the at least one parameter indicates an ability of the memory to process signals from the electrical component, and wherein each of the memories comprises multiple semiconductors dies packaged together;
labeling each memory with a label based on the determined parameter, wherein the labels include at least a first label and a second label, and wherein the first label indicates that the memories with the first label are better able to process signals from the electrical component than the memories with the second label; and
electrically coupling the memories to the substrate based on the labeling such that the memories with the second label are positioned closer to the electrical component than the memories with the first label.