Patent ID: 11921623
Assignee: SECURED-IC SAS
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A device for testing a bit sequence generated by a Random Number Generator, wherein the device is configured to apply one or more statistical tests to the bit sequence, in response the detection of N bits generated by the Random number generator, each statistical test being configured to test randomness in said N bits generated by the Random number generator, each statistical test providing at least one sum value derived from the bits of said sequence, the testing device comprising:
a comparator for comparing at least one test parameter related to each statistical test to one or more thresholds;
a validation unit configured to determine if said bit sequence is valid depending on the comparison made by the comparator for each statistical test;
wherein at least one of said test parameter and said at least one threshold is determined from N and from a target error probability;
wherein said at least one test parameter corresponds to a sum value,
the device further comprising:
a threshold determination unit (101) configured to determine, for each statistical test, at least one threshold pair comprising a lower threshold and a higher threshold, the lower threshold and the higher threshold depending on the parameter N and on a target error probability,
wherein the comparator (102) is configured to compare, for each statistical test, each sum value with the associated lower threshold and higher threshold.