Patent ID: 11887674
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 4:
5. The memory apparatus as set forth in claim 3, wherein the threshold voltage possible for each of the memory cells spans a threshold window, each of the memory cells is configured to store a plurality of bits, the plurality of data states includes an erased state at a first end of the threshold window and a plurality of programmed data states each corresponding to the threshold voltage being higher than the threshold voltage associated with the erased state, the plurality of programmed data states including at least one higher data state at a second end of the threshold window opposite the first end and associated with the threshold voltage being higher than the threshold voltage associated with the erased state and at least one other of the plurality of programmed data states and at least one lower data state between the at least one higher data state and the erased state, and the kick voltage applied to the one of the plurality of bit lines coupled to the one of the memory cells during the read operation is relatively lower in magnitude for the at least one lower state compared to the at least one higher state and relatively higher in magnitude for the at least one higher state compared to the at least one lower state.