Patent ID: 11961577
Assignee: NXP USA, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 7:
8. The method of claim 1, wherein the testing the first set of ADCs using the pairs of calibration codes stored in the on-chip memory and the full N-bit resolution of the DAC comprises:
generating a first DAC input code;
accessing a first address line of the on-chip memory addressed by N−1 upper significant bits of the first DAC input code, wherein the N−1 upper significant bits is capable of addressing any memory line of the on-chip memory;
providing a selected pair of calibration codes corresponding to the received first DAC input code from the first accessed address line, based on an LSB of the first input code, to calibrate the DAC during testing the first set of ADCs.