Patent ID: 11948069
Assignee: ARM LIMITED
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A processor arranged to compress neural network activation data comprising:
an input module for obtaining uncompressed neural network activation data from memory;
a block creation module arranged to split the uncompressed neural network activation data into a plurality of blocks of uncompressed neural network activation data;
a metadata generation module, comprising hardware logic, for generating metadata associated with each of the plurality of blocks of uncompressed neural network activation data, the metadata comprising statistics calculated by:
a zero-counter of the metadata generation module, arranged to calculate a number of zero point values of each of the plurality of blocks of uncompressed neural network activation data;
a unique non-zero counter of the metadata generation module, arranged to calculate a number of unique non-zero point values of each of the plurality of blocks of uncompressed neural network activation data; and
a non-zero counter of the metadata generation module, arranged to calculate a number of non-zero point values of each of the plurality of blocks of uncompressed neural network activation data;

a selection module for selecting a compression scheme for each of the plurality of blocks of uncompressed neural network activation data, wherein the compression scheme is selected based on at least the statistics associated with each block of the uncompressed neural network activation data;
a compression module for applying the selected compression scheme to the corresponding block of uncompressed neural network activation data to produce compressed neural network activation data; and
an output module for outputting the compressed neural network activation data.