Patent ID: 11915357
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A method comprising:
executing a plurality of ray shaders and generating a plurality of primary rays and a corresponding plurality of ray messages by execution circuitry comprisng a plurality of functional units;
queuing the plurality of ray messages in a buffer prior to storage in a memory-backed stack and/or a memory subsystem;
storing one or more of the plurality of primary rays in a cache;
storing a first subset of the plurality of ray messages in a corresponding plurality of entries of the memory-backed stack;
either storing a second subset of the plurality of ray messages to the memory-backed stack, or storing the second subset of the plurality of ray messages to the memory subsystem based, at least in part, on a number of entries currently occupied by ray messages in the memory-backed stack;
throttling dispatching of a plurality of ray shaders based, at least in part, on the number of entries currently occupied by the ray messages in the memory-backed stack and/or ray message occupancy in the buffer, wherein one or more threshold values for throttling are to be adjusted based, at least in part, on the number of entries currently occupied by the ray messages in the memory-backed stack and/or the ray message occupancy in the buffer;
reading a next ray message from the memory-backed stack;
retrieving a next primary ray identified by the ray message from the cache or a memory subsystem; and
performing traversal operations on the next primary ray.