Patent ID: 11923271
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. An apparatus comprising:
a first package bump on a first integrated circuit (IC) die, the first package connected to a power supply,
a second package bump on the first IC die, the second package bump connected to the power supply, wherein a second IC die is stacked on the first IC die in a face-to-face configuration;
a power distribution structure in the first IC die, the power distribution structure comprising:
at least one Through-Silicon Via (TSV) connected to the first package bump or the second package bump, and
a ladder structure connected to the at least one TSV; and

an interface disposed between the first IC die and the second IC die, wherein the interface connects the ladder structure to a plurality of vertical top metal elements of the second IC die, and wherein the ladder structure comprises a plurality of horizontal elements connected by a plurality of vertical elements.