Patent ID: 11972827
Assignee: WINBOND ELECTRONICS CORP.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. The reading method according to claim 10, wherein,
when a page comprises n sectors, the ECC chip performs the error detection and correction of the data on a sector-by-sector basis, a time for reading the memory array is set as tARRAY, a time for the NAND chip to transmit the data of one sector to the ECC chip is set as tDOUT1, a time for the ECC chip to output the data of the one sector to the outside is set as tDOUT2, and a latency from outputting the data of the one sector from the NAND chip to an end of the error detection and correction of the sector is set as tLTCY, and there are limitation specified by the following equations (1) to (4):

tDOUT1+tLTCY<tDOUT2×n/2  (1)

tDOUT1<tDOUT2  (2)

tARRAY+tDOUT1+tLTCY<tDOUT2×n  (3)

tARRAY+tDOUT1×n/2<tDOUT2×n  (4).