Patent ID: 11948513
Assignee: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. The method of driving the shift register according to claim 13, wherein the first period includes an input period and a scanning period;
in the input period, in response to the level of the first clock signal, the input circuit is turned on and transmits the level of the input signal to the first node;
under the control of the voltage of the first node, the output circuit is turned on and transmits a level of the second clock signal to the output signal terminal;
under the control of the voltage of the first node and the level of the second clock signal, the first control circuit transmits the first voltage signal to the second node, so as to control the voltage of the second node; and
under the control of the voltage of the second node, the holding circuit is turned off;
in the scanning period, in response to another level of the first clock signal, the input circuit is turned off;
the voltage of the first node remains substantially unchanged, and under the control of the voltage of the first node, the output circuit remains in an on state and transmits another level of the second clock signal to the output signal terminal;
under the control of the voltage of the first node and the another level of the second clock signal, the first control circuit transmits the first voltage signal to the second node, so as to control the voltage of the second node; and
under the control of the voltage of the second node, the holding circuit is turned off;
the second period includes a first holding period and a second holding period;
in the first holding period, in response to the level of the first clock signal, the input circuit is turned on and transmits the another level of the input signal to the first node;
under the control of the voltage of the first node, the output circuit is turned off;
under the control of the voltage of the first node and the level of the second clock signal, the first control circuit transmits the level of the second clock signal to the second node, so as to control the voltage of the second node; and
under the control of the voltage of the second node, the holding circuit is turned off in the second holding period, in response to the another level of the first clock signal, the input circuit is turned off;
the voltage of the first node remains substantially unchanged, and under the control of the voltage of the first node, the output circuit remains in an off state;
under the control of the voltage of the first node and the another level of the second clock signal, the first control circuit transmits the another level of the second clock signal to the second node, so as to control the voltage of the second node; and
under the control of the voltage of the second node, the holding circuit is turned on and transmits the first voltage signal to the output signal terminal.