Patent ID: 11955429
Assignee: SK HYNIX INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for manufacturing a three-dimensional memory device, comprising:
forming, on a substrate, a sacrificial layer including a plurality of sacrificial patterns for vias and a sacrificial pattern for a row line, which has a projection coupled to a corresponding sacrificial pattern for a via from among the plurality of sacrificial patterns for vias;
forming an interlayer dielectric layer that covers the sacrificial pattern for a row line and the sacrificial pattern for a via coupled to the sacrificial pattern for a row line and that has a plurality of holes exposing sacrificial patterns for vias, from among the plurality of sacrificial patterns for vias, that are not coupled to the sacrificial pattern for a row line;
forming a plurality of first conductive patterns in the plurality of holes;
repeating the forming of the sacrificial layer, the forming of the interlayer dielectric layer and the forming of the plurality of first conductive patterns to stack a plurality of sacrificial layers, a plurality of interlayer dielectric layers and a plurality of first conductive patterns on the substrate; and
replacing the plurality of sacrificial layers with a conductive material.