Patent ID: 11967354
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. The semiconductor memory device of claim 1, wherein the refresh control circuit includes:
a command generation circuit suitable for generating a target refresh command according to the refresh command, and generating an internal read signal and an internal write signal according to the active command and a row-hammer reset signal;
a latch circuit suitable for storing, according to a latch enable signal, the input address and the first data respectively as the sampling address and maximum counting data;
a latch control circuit suitable for generating the latch enable signal by comparing the first data with the maximum counting data; and
a row-hammer analysis circuit suitable for calculating a plurality of adjacent addresses based on the sampling address, outputting a row-hammer address by scheduling the adjacent addresses based on the second data according to the target refresh command, and enabling the row-hammer reset signal.