Patent ID: 11967521
Assignee: INNOSCIENCE (SUZHOU) SEMICONDUCTOR CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An integrated semiconductor device, comprising:
a substrate;
a plurality of semiconductor circuit layers being disposed above the substrate;
an insulating material being disposed on the semiconductor circuit layers; and
an interconnection layer being embedded in the insulating material and electrically connected to one or more of the semiconductor circuit layers,
wherein the semiconductor circuit layers include a plurality of device portions and one or more isolating portions, and the isolating portions are disposed among the device portions, and the isolating portions provide electrical isolation between adjacent device portions, and the interconnection layer has a plurality of circuits embedded in the insulating material on the device portions, and the insulating material has one or more isolating structures raised from top surfaces of the circuits on the device portions, and some of the semiconductor circuit layers form at least one heterojunction.