Patent ID: 11864387
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. A method used in forming a memory array comprising strings of memory cells, comprising:
forming a stack comprising vertically-alternating first tiers and second tiers, the stack comprising a memory-array region and a stair-step region;
forming horizontally-elongated trenches into the stack to form laterally-spaced memory-block regions extending from the memory-array region into the stair-step region, the memory-block regions in the stair-step region comprising laterally-spaced stair-step-structure regions;
forming a pair of elevationally-extending walls in the laterally-spaced stair-step-structure regions that are spaced laterally-inward from sides of the respective stair-step-structure region, that are laterally-spaced relative one another, and that are individually horizontally-longitudinally-elongated, the stair-step-structure regions being formed to comprise at least one of (a), (b), and (c), where:
(a): the individual stair-step-structure regions being devoid of operative TAV's laterally-between the pair of walls;
(b): at least one of the walls neither being horizontally parallel horizontal-longitudinal-orientation of its individual stair-step structure region nor angled orthogonally relative said horizontal-longitudinal-orientation; and
(c): the individual stair-step-structure regions being devoid of any interconnecting wall that extends laterally between the pair of walls.