Patent ID: 11972121
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G

Claim 8:
9. A method of operation within a stacked-die memory component having an inter-die signaling path, a base die coupled to the inter-die signaling path and a memory die coupled to the inter-die signaling path, the method comprising:
receiving, via a signaling interface of the base die, a chip-select signal, chip-identifier value and command/address value from a source external to the stacked-die memory component;
driving the chip-identifier value onto one or more chip-identifier lines of the inter-die signaling path during a first interval;
driving the command/address value onto one or more command/address lines of the inter-die signaling path during a second interval that commences a predetermined time after the first interval;
receiving the chip-identifier value within the memory die via the one or more chip-identifier lines;
asserting or deasserting a first control signal within the memory die according to whether the chip-identifier value matches or does not match, respectively, a resident identifier value of the memory die; and
receiving the command/address value within the memory die via the one or more command/address lines if the first control signal is asserted and disabling reception of the command/address value within the memory die if the first control signal is deasserted.