Patent ID: 11966591
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device, comprising:
a memory array including memory cells configured to store data, wherein the memory cells are grouped into at least a first deck and a second deck; and
a memory system controller operably coupled to the memory array and configured to—
program the first deck before the second deck;
determine a deck separation delay representative of a duration between programming the first and second decks;
identify an offset level based on the deck separation delay, wherein the offset level represents an imbalance in charge loss across the first and second decks during the deck separation delay;
determine a base read level for reading from the first deck, the second deck, or a combination thereof; and
compute a deck-specific read level based on the base read level, the offset level, or a combination thereof.