Patent ID: 11888490
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 2:
3. The delay estimation device according to claim 1, wherein the mode selecting circuit comprises:
a first buffer, having an input terminal, an output terminal and a control terminal, wherein the input terminal of the first buffer receives the reference clock signal, the output terminal of the first buffer is coupled with an input terminal of the DCDL, and the control terminal of the first buffer receives the first mode selection signal; and
a second buffer, having an input terminal, an output terminal and a control terminal, wherein the input terminal of the second buffer receives the first clock signal from the pulse generator, the output terminal of the second buffer is coupled with the input terminal of the DCDL and the output terminal of the first buffer, and the control terminal of the second buffer receives a second mode selection signal inverted to the first mode selection signal.