Patent ID: 11968466
Assignee: BRILLNICS SINGAPORE PTE. LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G  H | IPC H

Claim 2:
3. The solid-state imaging device of claim 1,
wherein each of the asynchronous counter modules includes:
a pixel signal input terminal to which a corresponding one of bits of the read-out reset signal and a corresponding one of bits of the read-out signal are input;
a capture signal input terminal to which a capture signal is input to capture the corresponding one of the bits of the read-out reset signal and the corresponding one of the bits of the read-out signal are input;
a carry signal input terminal;
a signal output terminal;
a carry signal output terminal;
a first logic gate for performing a logical operation between (i) the read-out reset signal or the read-out signal fed to a first input terminal and (ii) the capture signal, to produce a first signal corresponding to the read-out reset signal or the read-out signal;
a second logic gate for performing a logical operation between (i) the read-out reset signal or the read-out signal fed to a first input terminal and (ii) the capture signal, to invert a level of the read-out reset signal or the read-out signal and produce a second signal having a reversed phase when compared with the first signal;
a third logic gate for performing a logical operation between the second signal from the second logic gate and a carry signal from a lower-order one of the asynchronous counter modules input through the carry signal input terminal, to produce a third signal;
a fourth logic gate for performing a logical NOR between the first signal and the third signal, to produce a fourth signal; and
a fifth logic gate for inverting the fourth signal from the fourth logic gate, to produce a clock signal,
wherein, in the D flip-flop, a data output Q is connected to the signal output terminal, a data inverting output terminal QB is connected to a data input D of the D flip-flop and to the carry signal output terminal, a clock terminal is connected to a clock signal output terminal of the fifth logic gate,
wherein the carry signal input terminal is connected to a carry output terminal of a lower-order one of the asynchronous counter modules, and
wherein the carry signal output terminal is connected to a carry signal input terminal of a higher-order one of the asynchronous counter modules.