Patent ID: 11899613
Assignee: KEPLER COMPUTING INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G  Y | IPC G

Claim 0:
1. An apparatus comprising:
a processor core coupled to an accelerator core via an interconnect; and
a first memory coupled to the processor core, wherein the accelerator core is coupled to a second memory, wherein the processor core is to fetch an instruction and to determine whether the instruction is to be scheduled for processing by the processor core of a compute die or the accelerator core of an accelerator die based on a type of the instruction, wherein the processor core is to assemble the instruction in a command packet that includes data address associated with the second memory, and to send the command packet to the accelerator core via the interconnect, and wherein the processor core and/or the accelerator core includes ferroelectric logic.