Patent ID: 11900539
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A method comprising:
rendering objects on a graphics processor that is configured in a tile-based immediate render mode, including:
generating a plurality of batches of objects to be rendered, each of the plurality of batches sized according to a size of a cache memory of the graphics processor;
determining tiles intersected by objects in each of the plurality of batches;
maintaining lit transaction information for the plurality of batches based on the intersected tiles; and
performing a play sequencing of each of the objects based on the lit transaction information, wherein object data and associated control data are stored to the cache memory of the graphics processor for use during play sequencing, wherein performing the play sequencing includes:
selecting, based on the lit transaction information, a cache aware tile-walk pattern; and
walking lit tiles according to the tile-walk pattern, wherein to walk a lit tile includes to process primitive commands for objects in the plurality of batches of objects that are associated with the lit tile.