Patent ID: 11966480
Assignee: NVIDIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 11:
12. The method of claim 11, further comprising:
receiving, by the accelerator circuit, a second descriptor of a second data transfer of a second size associated with a second application, the second descriptor specifying a second index in the secure memory corresponding to the second application;
splitting, by the accelerator circuit, the second data transfer into a second set of portions, each portion being less than or equal to the second size and required to complete execution before a context switch to another application;
executing, by the accelerator circuit during a third period, a first subset of the second set of portions sequentially using a second IV and a second encryption key associated with the second application;
storing, by the accelerator circuit at an end of the third period, a second computed hash key and a second block counter in the secure memory at the specified second index;
executing, by the accelerator circuit during a fourth period subsequent to the third period, a second subset of the second set of portions sequentially using the second computed hash key and the second block counter stored in the secure memory at the specified second index; and
storing, by the accelerator circuit at an end of the fourth period, a second authentication tag associated with the second data transfer.