Patent ID: 11973055
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: nan (nan)
Classification: CPC nan | IPC B  H

Claim 0:
1. A method comprising:
obtaining a first wafer comprising a first semiconductor substrate, a first dielectric layer, and first die connectors;
removing a first portion of the first dielectric layer in an edge region of the first wafer with a first trim process, the first trim process removing the first dielectric layer at a faster rate than the first semiconductor substrate;
removing a second portion of the first semiconductor substrate in the edge region of the first wafer with a second trim process, the second trim process removing the first semiconductor substrate at a faster rate than the first dielectric layer; and
bonding a second wafer to the first wafer, the second wafer comprising a second semiconductor substrate, a second dielectric layer, and second die connectors, the second dielectric layer bonded to the first dielectric layer with dielectric-to-dielectric bonds, the second die connectors bonded to the first die connectors with metal-to-metal bonds.