Patent ID: 11967580
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. A method of fabricating a microelectronic assembly, the method comprising:
forming a first package substrate portion;
providing a first component above the package substrate portion, the first component having a top side and a bottom side, and a first sidewall and a second sidewall between the top side and the bottom side, the second sidewall laterally opposite the first sidewall, and the first component comprising a plurality of through substrate vias;
forming a first conductive pillar laterally distanced apart from the first sidewall of the first component;
forming a second conductive pillar laterally distanced apart from the second sidewall of the first component;
forming a mold material on the first package substrate portion and laterally surrounding the first component, the first conductive pillar, and the second conductive pillar, the mold material in contact with the first conductive pillar, the second conductive pillar, the first sidewall of the first component, and the second sidewall of the first component;
forming a second package substrate portion having a top surface and a bottom surface, the bottom surface on the first conductive pillar, on the second conductive pillar, on the mold material, and over the first component;
providing a second component coupled to the top surface of the second package substrate portion, the second component vertically over the first component; and
providing a third component coupled to the top surface of the second package substrate portion, the third component vertically over the first component, and the third component laterally distanced apart from the second component, wherein the first component electrically couples the second component to the third component.