Patent ID: 11971821
Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. A computing system with write-back and invalidation in a hierarchical cache structure based on a plurality of designated key identification codes, comprising:
a first core provided within a first processor that is fabricated on a first die, including a decoder, a memory ordering buffer, and a first in-core cache module; and
a first last-level cache, fabricated in the first processor;
wherein:
in response to a second instruction of an instruction set architecture that is provided for write-back and invalidation in a hierarchical cache structure based on a plurality of designated key identification codes, the decoder outputs at least one microinstruction;
based on the at least one microinstruction decoded from the second instruction, the designated key identification codes are stored in a storage unit of the first core, and a plurality of write-back and invalidation requests corresponding to the different designated key identification codes read from the storage unit are provided to the first in-core cache module through the memory ordering buffer; and
write-back and invalidation in the hierarchical cache structure based on the next designated key identification code is performed after write-back and invalidation in the hierarchical cache structure based on a current designated key identification code is finished.