Patent ID: 11862293
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. A semiconductor memory device comprising:
a substrate including a plurality of first regions, a second region, and a third region, the plurality of first regions being arranged in a first direction, the second region extending in the first direction, the second region being arranged with the plurality of first regions in a second direction intersecting with the first direction, the third region being arranged with the plurality of first regions and the second region in the first direction;
a first memory cell array disposed in one of the plurality of first regions, the first memory cell array including a plurality of first memory cells and a plurality of first word lines connected to the plurality of first memory cells;
a second memory cell array disposed in another of the plurality of first regions, the second memory cell array including a plurality of second memory cells and a plurality of second word lines connected to the plurality of second memory cells;
a plurality of first wirings electrically connected to the plurality of first word lines and the plurality of second word lines;
a voltage generation circuit disposed in the third region, the voltage generation circuit including a plurality of output terminals disposed corresponding to the plurality of first wirings;
a first circuit disposed in the second region, the first circuit being disposed corresponding to the first memory cell array; and
a second circuit disposed in the second region, the second circuit being disposed corresponding to the second memory cell array, wherein
the first circuit includes:
a first node electrically connected to the plurality of first word lines and the plurality of first wirings;
a plurality of first transistors disposed in a plurality of current paths between the first node and the plurality of first word lines; and
a plurality of second transistors disposed in a plurality of current paths between the first node and the plurality of first wirings, wherein

the second circuit includes:
a second node electrically connected to the plurality of second word lines and the plurality of first wirings;
a plurality of third transistors disposed in a plurality of current paths between the second node and the plurality of second word lines; and
a plurality of fourth transistors disposed in a plurality of current paths between the second node and the plurality of first wirings.