Patent ID: 11874734
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A method for operating a memory, comprising:
generating a first address;
performing an error check operation on memory cells corresponding to the first address in a memory core;
generating a second address which is increased by one step from the first address;
performing an error check operation on memory cells corresponding to the second address in the memory core;
detecting an error which is equal to or greater than a threshold value in a region including the memory cells corresponding to the second address;
classifying the region as a bad region in response to the detection of an error which is equal to or greater than the threshold value;
generating a third address which is decreased by N steps, where N is an integer equal to or greater than 1, from the second address in response to the classification of the bad region; and
performing an error check operation on memory cells corresponding to the third address in the memory core.