Patent ID: 11972121
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G

Claim 15:
16. A stacked-die memory component comprising:
memory dies disposed in a stack;
die-to-die signaling paths each coupled exclusively to a corresponding one of the memory dies;
a base die coupled to the die-to-die signaling paths and having:
a first signaling interface to receive a chip-select signal, chip-identifier value and command/address value from a source external to the stacked-die memory component, the chip-identifier value indicating a selected one of the die-to-die signaling paths; and
circuitry to drive the command/address value exclusively onto the selected one of the die-to-die signaling paths, to be received by a corresponding one of the memory dies, while maintaining each other of the die-to-die signaling paths in an idle state.