Patent ID: 11950405
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor device comprising:
a substrate;
a semiconductor pattern on the substrate and extending in a first direction that is parallel to a top surface of the substrate, the semiconductor pattern including a first outer side surface, a second outer side surface that is opposite the first outer side surface, and an inner side surface between the first outer side surface and the second outer side surface;
a bit line on the first outer side surface of the semiconductor pattern and extending in a second direction that is parallel to the top surface of the substrate and is perpendicular to the first direction;
a first insulating layer on the substrate;
a second insulating layer on the first insulating layer, wherein the bit line is between the first insulating layer and the second insulating layer;
a capacitor lower electrode on the second outer side surface of the semiconductor pattern and extending in the first direction;
a gate electrode between the bit line and the capacitor lower electrode, the gate electrode including a first portion that is on a bottom surface of the semiconductor pattern, a second portion that is on a top surface of the semiconductor pattern, and a third portion that is on the inner side surface of the semiconductor pattern and extends in a third direction that is perpendicular to the top surface of the substrate; and
a gate dielectric layer between the semiconductor pattern and the gate electrode,
wherein the gate dielectric layer is on the top surface, the bottom surface, and the inner side surface of the semiconductor pattern,
wherein the first portion and the second portion of the gate electrode are between the first insulating layer and the second insulating layer, and
the third portion of the gate electrode contacts the first portion and the second portion of the gate electrode.