Patent ID: 11881771
Assignee: NXP USA, INC.
Field: Electrical machinery, apparatus, energy (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 13:
14. The method of claim 13, further comprising:
during a rising phase of the half-bridge voltage, the controller circuit comparing a value of the multi-bit status signal with a first lower limit value corresponding to a first lower limit voltage, to determine whether the half-bridge voltage is lower than the first lower limit voltage; and
the high-side delay circuit generating the high-side control signal using the delay control signal to reduce a predetermined delay time from a current first delay time in response to the half-bridge voltage being lower than the first lower limit voltage;
wherein the method further comprises: the high-side switch being on in response to the high-side control signal by applying the first delay time;
and wherein the method further comprises:
during the rising phase of the half-bridge voltage, the low-side delay circuit generating the low-side control signal using the delay control signal to add a predetermined delay time into a current second delay time in response to the half-bridge voltage being lower than the first lower limit voltage; and
the low-side switch being off in response to the low-side control signal by applying the second delay time.