Patent ID: 11967578
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. The semiconductor package according to claim 1, wherein:
the insulating layer comprises a first insulating layer, a second insulating layer, and a third insulating layer that are sequentially stacked on the lower surface of the semiconductor chip;
the redistribution pattern comprises a first redistribution pattern on a lower surface of the first insulating layer, and a second redistribution pattern on a lower surface of the second insulating layer; and
the via comprises a first via connecting the semiconductor chip and the first redistribution pattern while extending through the first insulating layer in the vertical direction, and a second via electrically interconnecting the first redistribution pattern and the second redistribution pattern while extending through the second insulating layer in the vertical direction.