Patent ID: 11881480
Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 12:
13. The method according to claim 12, after forming the first isolation structure and the second isolation structure, and before forming the first gate structure and the second gate structure, further comprising:
forming a first dummy gate structure on the first region, wherein the first dummy gate structure spans the initial first nanostructure, the initial second nanostructure, and the first isolation structure;
forming a second dummy gate structure on the second region, wherein the second dummy gate structure spans the initial third nanostructure, the initial fourth nanostructure, and the second isolation structure;
forming a dielectric layer on the substrate, wherein the dielectric layer is located on a sidewall of the first dummy gate structure and a sidewall of the second dummy gate structure;
removing the first dummy gate structure and the second dummy gate structure, and forming a first gate opening in the dielectric layer on the first region, wherein the first gate opening exposes a portion of the sidewall surface of the initial first nanostructure and a portion of the sidewall surface of the initial second nanostructure; and
forming a second gate opening in the dielectric layer on the second region, wherein the second gate opening exposes a portion of a sidewall surface of the initial third nanostructure and a portion of a sidewall surface of the initial fourth nanostructure.