Patent ID: 11875761
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A display driving circuit comprising:
a frame rate extractor configured to
receive a vertical synchronization signal indicating a start of a k-th frame, k-th frame data including information about the k-th frame, and a data enable signal indicating an active period of the k-th frame and a variable blank period that occurs after the active period, and
extract a frame rate of the k-th frame, based on the vertical synchronization signal; and

an image corrector configured to
correct frame data for a (k+1)th frame received after reception of the k-th frame data, based on the frame rate of the k-th frame, and
output the corrected frame data as output image data,

wherein the vertical synchronization signal is received before a start time point of the active period.