Patent ID: 11923409
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 0:
1. A semiconductor device, comprising:
a source/drain feature over a semiconductor substrate;
channel layers over the semiconductor substrate and connected to the source/drain feature;
a gate portion between vertically adjacent channel layers;
a first inner spacer between the source/drain feature and the gate portion and between adjacent channel layers;
a first air gap between the first inner spacer and the source/drain feature;
a second inner spacer between the semiconductor substrate and the first inner spacer;
a third inner spacer above the first inner spacer;
a second air gap between the second inner spacer and the source/drain feature; and
a third air gap between the third inner spacer and the source/drain feature,
wherein the source/drain feature has a first surface exposed in the first air gap, a second surface exposed in the second air gap, and a third surface exposed in the third air gap,
wherein the first surface has a first curved segment including an apex at a mid-height of the first air gap, the second surface has a second curved segment including an apex at a mid-height of the second air gap, and the third surface has a third curved segment including an apex at a mid-height of the third air gap,
wherein the first curved segment has a greater curvature than the second curved segment but a smaller curvature than the third curved segment.