Patent ID: 11973133
Assignee: WINBOND ELECTRONICS CORP.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 1:
2. The method of claim 1, further comprising:
forming a barrier layer on the substrate;
forming a p-type semiconductor layer on the barrier layer;
patterning the p-type semiconductor layer, the barrier layer, and the substrate to form the first mesa isolation and the second mesa isolation;
removing the p-type semiconductor layer on the capacitor region;
forming a first hard mask on the first mesa isolation and the second mesa isolation;
forming a source electrode and a drain electrode in the first hard mask on the HEMT region;
forming a source electrode extension and a drain electrode extension on the HEMT region;
forming a bottom electrode on the first hard mask of the capacitor region;
forming a second hard mask on the source electrode extension, the drain electrode extension, and the bottom electrode; and
forming a gate electrode on the HEMT region and a top electrode on the capacitor region.