Patent ID: 11902685
Assignee: META PLATFORMS TECHNOLOGIES, LLC
Field: Audio-visual technology (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. The apparatus of claim 1, wherein the frame memory controller is configured to:
within a first time, when the in-pixel memory of a first row and a second row of pixel cells of the array of pixel cells is connected to, respectively and simultaneously, a first row and a second row of memory cells of the frame memory:
receive a first subset of the digital outputs from the in-pixel memory of the first row of pixel cells;
receive a second subset of the digital outputs from the in-pixel memory of the second row of pixel cells;
store the first subset of the digital outputs at the second row of memory cells of the frame memory; and
store the first subset of the digital outputs at the second row of memory cells of the frame memory; and

within a second time, when the in-pixel memory of a third row and a fourth row of pixel cells of the array of pixel cells is connected to, respectively and simultaneously, a third row and a fourth row of memory cells of the frame memory:
receive a third subset of the digital outputs from the in-pixel memory of the third row of pixel cells;
receive a fourth subset of the digital outputs from the in-pixel memory of the fourth row of pixel cells;
store the third subset of the digital outputs at the third row of memory cells of the frame memory; and
store the fourth subset of the digital outputs at the fourth row of memory cells of the frame memory.