Patent ID: 11916569
Assignee: SILICON MOTION, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G  Y | IPC G  H

Claim 5:
6. A flash memory controller coupled to a flash memory module comprising a plurality of first blocks and at least one second block, comprising:
a plurality of channels respectively connected to the flash memory module; and
the flash memory controller is configured to:
classify data into a plurality of groups, and perform an error code encoding operation on the groups of data to generate corresponding parity check code;
write the groups of data and the corresponding parity check code into the plurality of first blocks of the flash memory module according to a randomizer seed rule of the at least one second block;
after the groups of data are written into the plurality of first blocks, controlling the flash memory module to write the groups of data and corresponding parity check code from the plurality of first blocks to the at least one second block.