Patent ID: 11948890
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A device comprising:
an integrated circuit die;
a through via adjacent the integrated circuit die;
a molding compound encapsulating the integrated circuit die and the through via;
a first dielectric layer on the molding compound;
a first conductive via extending through the first dielectric layer, the first conductive via connected to the through via, a top surface of the first conductive via extending above a top surface of the first dielectric layer;
a second conductive via extending through the first dielectric layer, the second conductive via connected to a die connector of the integrated circuit die, a top surface of the second conductive via extending above the top surface of the first dielectric layer; and
a conductive line on the top surface of the first conductive via, a sidewall of the first conductive via, the top surface of the second conductive via, a sidewall of the second conductive via, and the top surface of the first dielectric layer.