Patent ID: 11948903
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 18:
19. A semiconductor package, comprising:
a first stack including a center area and an edge area around the center area, the first stack including a first semiconductor substrate;
a plurality of first TSVs passing through the first semiconductor substrate;
a plurality of first pads on a top surface of the center area, the plurality of first pads being in contact with the plurality of first TSVs;
a second pad on the top surface of the edge area, the second pad being in contact with one first TSV of the plurality of first TSVs;
a third pad on the top surface of the edge area, the third pad being adjacent to the second pad and not being in contact with the plurality of first TSVs;
an interconnection line extending along the top surface of the edge area, the interconnection line being in direct contact with the second pad and the third pad;
a plurality of bumps on the plurality of first pad, the second pad, and the third pad;
a fourth pad on one of the plurality of bumps, the fourth pad overlapping with the second pad;
a fifth pad on one of the plurality of bumps, the fifth pad overlapping with the third pad and being spaced apart from the fourth pad; and
a second stack including a semiconductor device layer including an insulating film and metal lines,
wherein:
the fourth pad and the fifth pad are on a bottom surface of the second stack, and
the fourth pad and the fifth pad are connected with the metal lines of the second stack.