Patent ID: 11966727
Assignee: LZLABS GMBH
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A system for executing a first program compiled for a source architecture on a machine having a target architecture different from the source architecture, the system comprising:
a first platform comprising one or more processors of a source architecture;
a decompiler installed on the first platform and configured to execute on a processor of the one or more processors of said source architecture, the decompiler adapted to:
receive said first program comprising first executable code compiled to execute on a source architecture;
decompile a load module of the first program into intermediate computer code formatted according to an intermediate code format;
identify a set of addresses that are exposed for external reference by a second program compiled to execute on the source architecture, wherein identify includes:
in a first pass, examine syntax of instructions in machine code of said first program;
determine from the syntax of the instructions that a set of symbols are addresses;
add the set of symbols to an index of said set of addresses; and

store in a computer memory the index of said set of addresses that are exposed for external reference, wherein the index comprises values that correspond to invalid addresses in the target architecture;

a second platform, comprising one or more processors of a target architecture, wherein the second platform is coupled to the first platform through a computer network;
a compiler installed on the second platform adapted to execute on a processor of the target architecture, the compiler adapted to receive the intermediate computer code and the index generated by the decompiler, to compile the intermediate code into an executable program of the target architecture comprising machine code of the target architecture, and to incorporate the index of the set of addresses into the executable program of the target architecture; and
an exception handler installed on the second platform wherein, in response to detection by a processor of the second platform of the execution of an instruction to access an invalid address, said exception handler translates said invalid address into a valid address using the incorporated index in the executable program of the target architecture.