Patent ID: 11940700
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Optics (Instruments)
Classification: CPC G  H | IPC G  H

Claim 0:
1. An array substrates, comprising:
a display area and a non-display area surrounding the display area, wherein:
the display area includes a plurality of gate lines, a plurality of data lines, and a plurality of pixel units defined by intersections of gate lines and data lines, each of the pixel units including a thin film transistor having a drain electrode and a pixel electrode electrically connected to the drain electrode of the thin film transistor;
the non-display area includes a plurality of dummy pixel units arranged around the display area, each of the dummy pixel units including a dummy thin film transistor having a drain electrode and a dummy pixel electrode floating relative to the drain electrode of the dummy thin film transistors;
the dummy pixel units include first dummy pixel units and second dummy pixel units; dummy pixel units located at two ends of an extending direction of the gate lines are the first dummy pixel units, and dummy pixel units located at two ends of an extending direction of the data lines are the second dummy pixel units; drain electrodes of dummy thin film transistors in at least some of the second dummy pixel units have overlapping regions with dummy pixel electrodes;
the non-display area further includes a dummy common electrode structure, dummy pixel electrodes of at least some of the dummy pixel units being electrically connected to the dummy common electrode structure.