Patent ID: 11875738
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. A display driver integrated circuit, comprising:
a gamma circuit configured to generate a plurality of gamma voltages based on gamma control information, a first gamma power supply voltage, and a second gamma power supply voltage;
a control circuit configured to calculate a gamma limit value based on panel brightness information, voltage levels of the first and second gamma power supply voltages, and a number of the plurality of gamma voltages, and configured to compare the gamma limit value with a mode determination reference value to generate a mode determination signal representing one of a first driving mode and a second driving mode; and
an output buffer circuit including a plurality of buffer circuits that provide analog image signals to a plurality of pixels included in a display panel, wherein each of the plurality of buffer circuits includes an input stage, an amplification stage and an output stage, and the input stage includes first transistors having a first type and second transistors having a second type,
wherein the input stage includes:
a first input unit including p-type metal oxide semiconductor transistors;
a second input unit including n-type metal oxide semiconductor transistors;
a first bias unit including a first bias transistor that supplies a first bias current to the first input unit;
a second bias unit including a second bias transistor that supplies a second bias current to the second input unit; and
a mode change unit including at least one of a first mode change transistor connected to a gate of the first bias transistor and a second mode transistor connected to a gate of the second bias transistor, and configured to, in the first driving mode, block supply of one of the first bias current and the second bias current,

wherein, in the first driving mode, each of the plurality of buffer circuits is configured to turn off one of the first and second mode change transistors to turn off one of the first and second input units and turn on the other of the first and second input units, and
wherein, in the second driving mode, each of the plurality of buffer circuits is configured to turn on at least one of the first and second mode change transistors to turn on both of the first and second input units,
wherein, the gamma limit value includes a first limit value, and the mode determination reference value includes a first mode determination reference value, and
wherein, the control circuit is configured to generate the mode determination signal representing the first driving mode in response to the first limit value being higher than the first mode determination reference value.