Patent ID: 11889699
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A semiconductor memory device comprising:
a substrate including a first region and a second region;
a plurality of first transistors provided in the first region;
a plurality of second transistors provided in the second region, the plurality of second transistors being electrically coupled to the plurality of first transistors, respectively, and a breakdown-voltage of the second transistors being lower than a breakdown-voltage of the first transistors;
a plurality of joint metals provided above the first region, the plurality of joint metals being electrically coupled to the plurality of first transistors, respectively;
a plurality of bit lines provided in an upper layer with respect to the plurality of joint metals, the plurality of bit lines being coupled to the plurality of joint metals, respectively; and
a plurality of memory cells provided in an upper layer with respect to the plurality of bit lines, the plurality of memory cells being coupled to the plurality of bit lines, respectively,
wherein the first transistors and the plurality of joint metals overlap in a planar view, and a pitch of the plurality of joint metals in a first direction approximately doubles a pitch of a first transistor in the first direction.