Patent ID: 11869892
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 17:
18. A method for forming a semiconductor device structure, comprising:
forming first and second semiconductor fins in an N-type region and third semiconductor fin in a P-type region;
forming a sacrificial gate structure across a portion of the first, second, and third semiconductor fins;
forming a spacer on opposite sidewalls of the sacrificial gate structure;
recessing the first, second, and third semiconductor fins not covered by the sacrificial gate structure and the spacer such that a height of the first, second, and third semiconductor fins is gradually decreased along the direction away from the sacrificial gate structure;
forming a first source/drain epitaxial feature on the recessed first and second semiconductor fins and a second source/drain epitaxial feature on the recessed third semiconductor fin;
removing the sacrificial gate structure to expose the first, second, and third semiconductor fins;
forming a recess in a top portion of the exposed first, second, and third semiconductor fins, respectively, wherein each recess has a bottom surface and a sidewall surface extending upwardly from the bottom surface; and
forming a replacement gate structure in each recess and in contact with the bottom surface, the sidewall surface, and the spacer, wherein a bottom of the replacement gate structure is at a level lower than a bottom of the spacer.