Patent ID: 11955421
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A method, comprising:
depositing a first interlevel dielectric layer over a semiconductor substrate of an integrated circuit;
patterning a mask on the first interlevel dielectric layer;
irradiating a first region of the first interlevel dielectric layer exposed by the mask;
preventing irradiation of a second region of the first interlevel dielectric layer with the mask;
forming first trenches in the first region of the first interlevel dielectric layer;
forming second trenches in the second region of the first interlevel dielectric layer; and
forming first metal signal lines in the first trenches and first and second electrodes of a capacitor in the second trenches by depositing a metal in the first and second trenches, wherein the first and second electrodes include interleaving finger portions.