Patent ID: 11963355
Assignee: SK HYNIX INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 5:
6. A method of manufacturing a semiconductor memory device, the method comprising:
forming a memory cell array on a first substrate, wherein the memory cell array includes:
a gate stack structure with interlayer insulating layers and conductive patterns, which are alternately stacked in a vertical direction,
a plurality of channel structures penetrating the gate stack structure, the plurality of channel structures each with an end portion extending into the first substrate, and
a memory layer extending from between the plurality of channel structures and the gate stack structure to between the end portion of each of the plurality of channel structures and the first substrate;

forming a bit line that is connected to the memory cell array;
removing the first substrate to expose the memory layer;
forming a first source layer on the top of the entire structure including the memory layer;
etching the first source layer, the memory layer, and the end portion of each of the plurality of channel structures by performing a Chemical Mechanical planarization (CMP) process; and
forming a second source layer on the top of the entire structure that includes the first source layer, the memory layer, and the end portion of each of the plurality of channel structures, which are planarized.