Patent ID: 11947810
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. A memory system comprising:
a semiconductor memory device; and
a memory controller configured to communicate with the semiconductor memory device and configured to control the semiconductor memory device,
wherein the semiconductor memory device comprises:
a memory cell array comprising a plurality of volatile memory cells coupled to respective ones of a plurality of word-lines and respective ones of a plurality of bit-lines;
a first cyclic redundancy check (CRC) engine, in a memory operation on the memory cell array, configured to perform operations comprising:
detecting an error in a main data and a system parity data received from the memory controller through a link; and
generating a first error flag indicating whether the error that was detected corresponds to either a first type of error associated with the link or a second type of error associated with the volatile memory cells based on the system parity data; and

an on-die error correction code (ECC) engine configured to perform an ECC encoding operation on the main data and the system parity data and configured to perform an ECC decoding operation on the main data and the system parity data to correct a correctable error in the main data.