Patent ID: 11916703
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An equalizer circuit, comprising:
a decision feedback equalizer (DFE) circuit having a first output and a second output;
a sign-sign least mean squares (SS-LMS) adaptation circuit having a weight value output coupled to the DFE circuit;
an error sampler circuit coupled to the DFE circuit and the SS-LMS adaptation circuit, the error sampler circuit comprising a master latch circuit, and the master latch circuit including a slicer circuit configured to:
generate a first difference signal as a difference of the first output and a first reference signal; and
generate a second difference signal as a difference of the second output and a second reference signal; and
a slave latch circuit coupled to the master latch circuit and the SS-LMS adaptation circuit, and configured to:

generate a third difference signal as a difference of the first difference signal and the second difference signal;
latch the third difference signal; and
provide the third difference signal to the SS-LMS adaptation circuit.