Patent ID: 11869965
Assignee: MONOLITHIC 3D INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 14:
15. A 3D semiconductor device, the device comprising:
a first level comprising a first single crystal layer, said first level comprising a plurality of first transistors and at least one first metal layer,
wherein said at least one first metal layer overlays said first single crystal layer, and
wherein said at least one first metal layer comprises interconnects between said first transistors thus comprising forming first control circuits;

a second metal layer overlaying said at least one first metal layer;
a second level overlaying said at least one metal layer, said second level comprising a plurality of second transistors;
a third level overlaying said second level, said third level comprising a plurality of third transistors,
wherein said second level comprises a plurality of first memory cells, said first memory cells each comprising at least one of said second transistors,
wherein said third level comprises a plurality of second memory cells, said second memory cells each comprising at least one of said third transistors,
wherein at least one of said second memory cells is at least partially disposed atop of said control circuits,
wherein said first control circuits are connected to control data written to at least one of said second memory cells; and

a third metal layer disposed above said third level;
a fourth metal layer disposed above said third metal layer;
wherein at least one of said third transistors comprises a polysilicon channel,
wherein at least one of said second transistors comprises a portion being processed by a first lithography step,
wherein at least one of said third transistors comprises a portion being processed by a second lithography step,
wherein said fourth metal layer has a typical thickness which is at least twice a typical thickness of said second metal layer; and

a conductive path from said fourth metal layer to said second metal layer,
wherein said conductive path comprises a via disposed through said third level, and
wherein said via has a diameter of less than 1 micron.