Patent ID: 11960761
Assignee: PHISON ELECTRONICS CORP.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 29:
30. A memory storage device, comprising:
a connection interface unit configured to couple to a host system;
a rewritable non-volatile memory module; and
a memory control circuit unit, coupled to the connection interface unit and the rewritable non-volatile memory module,
wherein the memory control circuit unit is configured to:
receive at least one write command from the host system;
temporarily store first type data into a first storage space in a buffer memory and temporarily store second type data into a second storage space in the buffer memory according to the at least one write command;
determine, based on a first logical unit of the first type data, that the first type data should be stored into the rewritable non-volatile memory module by a first programming mode;
determine, based on a second logical unit of the second type data, that the second type data should be stored into the rewritable non-volatile memory module by a second programming mode, and the first programming mode is different from the second programming mode;
determine whether a data volume of the first type data in the buffer memory reaches a first threshold, and determine whether a data volume of the second type data in the buffer memory reaches a second threshold, wherein the first threshold is less than the second threshold; and
in a state that the data volume of the first type data in the buffer memory does not reach the first threshold, trigger an operation to store the first type data from the buffer memory into the rewritable non-volatile memory module in response to that the data volume of the second type data in the buffer memory reaches the second threshold.