Patent ID: 11968288
Assignee: QUALCOMM INCORPORATED
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A device comprising:
one or more transceivers configured to receive analog signals;
an analog-to-digital converter (ADC) configured to generate ADC samples; and
one or more processors configured to:
obtain a set of ADC samples generated by the ADC based on the analog signals and an ADC input clock;
generate, at a first time point, a start signal indicating a starting point of capturing the set of ADC samples;
synchronize, at a second time point, the start signal and a system clock;
generate, at a third time point, a capturing sample clock for capturing the set of ADC samples;
input the synchronized start signal and the capturing sample clock to a counter to determine a time difference between the second time point and the third time point; and
determine an ADC output timing of the set of ADC samples based on the time difference.