Patent ID: 11948644
Assignee: LODESTAR LICENSING GROUP LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 20:
21. A memory, comprising:
an array of memory cells comprising a plurality of memory cells, wherein each memory cell of the plurality of memory cells is selected for programming to a respective data state of a plurality of data states; and
control logic;
wherein the control logic is configured to cause the memory to:
store data corresponding to the respective data states for a first subset of memory cells of the plurality of memory cells in a first subset of latches of a plurality of latches and store inhibit data in a second subset of latches of the plurality of latches;
program the first subset of memory cells using a first set of program pulses having programming voltages within a first range of programming voltages;
store data corresponding to the respective data states for a second subset of memory cells of the plurality of memory cells in the second subset of latches and store inhibit data in the first subset of latches;
program the second subset of memory cells using a second set of program pulses having programming voltages within a second range of programming voltages;
store data corresponding to the respective data states for a third subset of memory cells of the plurality of memory cells in a third subset of latches of the plurality of latches and program the third subset of memory cells using the first set of program pulses; and
store data corresponding to the respective data states for the third subset of memory cells of the plurality of memory cells in the third subset of latches and program the third subset of memory cells using the second set of program pulses;
wherein the first range of programming voltages overlaps the second range of programming voltages.