Patent ID: 11887657
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 3:
4. The amplifier circuit according to claim 2, comprising:
the offset cancellation circuit comprises:
a first offset cancellation transistor, with one of a source or a drain coupled to the bit line, the other one of the source or the drain coupled to the complementary readout node, and a gate used for receiving the offset cancellation signal, wherein
the first offset cancellation transistor is configured to be turned on based on the offset cancellation signal at the offset cancellation stage to couple the complementary readout node to the bit line; and
a second offset cancellation transistor, with one of a source or a drain coupled to the complementary bit line, the other one of the source or the drain coupled to the readout node, and a gate used for receiving the offset cancellation signal, wherein
the second offset cancellation transistor is configured to be turned on based on the offset cancellation signal at the offset cancellation stage to couple the readout node to the complementary bit line.