Patent ID: 11908685
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method, comprising:
forming a dummy gate structure over a semiconductor fin that protrudes from a substrate;
forming a gate spacer on a sidewall of the dummy gate structure, wherein the forming of the gate spacer includes depositing a spacer layer over the substrate and recessing the spacer layer to form the gate spacer on the sidewall of the dummy gate structure;
forming source/drain (S/D) features in the semiconductor fin and adjacent to the gate spacer;
after forming the S/D features, performing a silicon implantation process to an upper portion of the gate spacer using a first dosage source including silicon, thereby forming a silicon-implanted upper portion of the gate spacer;
after performing the silicon implantation process, performing a carbon implantation process to the silicon-implanted upper portion of the gate spacer using a second dosage source including carbon, thereby increasing concentration of carbon in the silicon-implanted upper portion of the gate spacer with respect to a lower portion, wherein the second dosage source is different from the first dosage source;
forming an interlayer dielectric (ILD) layer over the carbon-implanted upper portion of the gate spacer;
replacing the dummy gate structure with a high-k metal gate structure, wherein the high-k metal gate structure is disposed in the ILD layer; and
forming a dielectric layer in the ILD layer and over the S/D features.