Patent ID: 11960717
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. A method, comprising:
sending, from a memory device to a power management integrated circuit (PMIC) via a first loopback pin of the memory device, a first signal to activate one or more components of the PMIC, the first signal sent outside a testing phase of operation;
sending, via a second loopback pin of the memory device outside the testing phase of operation and from the memory device to a transistor coupled with the second loopback pin and configured to selectively couple the memory device with the PMIC, a second signal to activate the transistor outside the testing phase of operation, wherein the first loopback pin and the second loopback pin are each configured to communicate feedback data during the testing phase of operation; and
inducing, by the first signal via inductive coupling between a first conductive path coupled with the first loopback pin of the memory device and a second conductive path coupled with the PMIC, a third signal on the second conductive path, the third signal for activating the one or more components of the PMIC.