Patent ID: 11914473
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 3:
4. The apparatus of claim 3, wherein the controller is further configured to cause the apparatus to:
identify a plurality of third sets of parity bits associated with the plurality of data units;
generate a plurality of fourth sets of parity bits associated with the plurality of data units;
compare respective parity bits from the plurality of third sets of parity bits with respective parity bits from the plurality of fourth sets of parity bits; and
determine that one or more parity bits from the plurality of third sets of parity bits do not match corresponding parity bits from the plurality of fourth sets of parity bits, wherein determining the error associated with the one or more data units of the plurality of data units is based at least in part on determining the one or more parity bits from the plurality of third sets of parity bits do not match the corresponding parity bits from the plurality of fourth sets of parity bits.