Patent ID: 11880686
Assignee: AMPERE COMPUTING LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 21:
22. A device comprising:
data storage;
a link interface circuit coupled to an external link;
a conversion circuit coupled to the link interface circuit and the data storage, the conversion circuit configured to:
receive, from the link interface circuit, a read flow control unit (FLIT) comprising a read instruction requesting at least one cache line from the data storage;
generating a response FLIT comprising:
a header slot comprising response information based on the read instruction for the at least one first cache line;
a first metadata slot comprising metadata associated with the at least one first cache line; and
at least two generic slots, each comprising a cache line chunk, each cache line chunk comprising bytes of one of the at least one first cache line.