Patent ID: 11973128
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 0:
1. A method, comprising:
forming a stack over a substrate, wherein the stack comprises a plurality of silicon layers interleaved by a plurality of silicon germanium layers, wherein each silicon germanium layer has a first thickness T1 and each silicon layer has a second thickness T2, T1 is smaller than T2;
forming a fin-shaped structure from the stack and the substrate, the fin-shaped structure comprising a channel region and a source/drain region;
forming a dummy gate stack over the channel region;
recessing the source/drain region to form a source/drain trench that exposes sidewalls of the plurality of silicon layers and the plurality of silicon germanium layers;
selectively and partially recessing the plurality of silicon germanium layers and the plurality of silicon layers to form a plurality of inner spacer recesses, and to cause at least one of the plurality of silicon layers to include a tilted top surface and a tilted bottom surface, and wherein a ratio of a height H1 of one of the plurality of inner spacer recesses to T1 is about 1.1 to about 1.5;
forming a plurality of inner spacer features in the plurality of inner spacer recesses;
forming a source/drain feature in the source/drain trench, wherein a portion of the source/drain feature extends into the substrate;
removing the dummy gate stack;
selectively removing the plurality of silicon germanium layers in the channel region;
trimming the plurality of silicon layers in the channel region to form a plurality of trimmed silicon layers, wherein a shape of a cross-sectional view of each of the plurality of trimmed silicon layers comprises a dog-bone shape; and
forming a gate structure to wrap around each of the plurality of trimmed silicon layers, wherein the gate structure comprises a work function layer and a seam enclosed in the work function layer.