Patent ID: 11861782
Assignee: IMAGINATION TECHNOLOGIES LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. The control stream decoder of claim 8, wherein:
each primitive block entry comprises a data pointer that identifies the location in memory of the control data block for the corresponding primitive block;
the control stream comprises at least one control data base address entry which specifies at least a portion of a control data base address;
the control stream decoder further comprises a control data base address entry analyser configured to receive one or more control data base address entries and, for each received control data base address entry, extract at least a portion of a control data base address from that control data base address entry, and update a current control data base address based on the extracted at least a portion of the control data base address;
the primitive block entry analyser is configured to generate an address of a control data block in memory from a combination of the current control data base address and the data pointer of the primitive block entry; and
the entry type analyser is configured to, in response to determining that a received entry is a control data base address entry, forward the control data base address entry to the control data base address entry analyser.