Patent ID: 11973109
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. A method of fabricating a semiconductor device, comprising:
forming a first fin pattern and a second fin pattern aligned in a first direction, each of the first fin pattern and the second fin pattern extending in the first direction;
forming a third fin pattern extending in the first direction and spaced apart from the first fin pattern in a second direction;
forming a pre gate structure disposed on the first fin pattern and the third fin pattern and extending in the second direction, the pre gate structure not intersecting the second fin pattern and overlapping an end of the first fin pattern;
removing a part of the pre gate structure and a part of the third fin pattern; and
forming an element isolation structure at a position from which the pre gate structure and the third fin pattern are removed.