Patent ID: 11961555
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A resistive memory device comprising:
a first bit line group including a first plurality of bit lines;
a first bit line group selection line;
a first edge bit line disposed at an outermost position in the first bit line group;
a first middle bit line included in the first bit line group, the first middle bit line being adjacent to the first edge bit line; and
a second bit line group adjacent the first bit line group and including a second plurality of bit lines; and
a second bit line group selection line that is separate from the first bit line group selection line,
wherein the first edge bit line is connected to a first global bit line through a first edge transistor,
the first middle bit line is connected to a second global bit line through a first decoding transistor,
the first edge bit line is further connected to a node through a first boundary transistor, the node supplying a non-selection voltage;
a gate of the first edge transistor and a gate of the first decoding transistor are connected to the first bit line group selection line, and
a gate of the first boundary transistor is connected to the second bit line group selection line.