Patent ID: 11961798
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A method for manufacturing the semiconductor structure according to claim 1, comprising:
providing an electrode layer of the at least two electrode layers;
forming the dielectric layer, the dielectric layer covering the electrode layer of the at least two electrode layers, and the air gap being arranged in the dielectric layer; and
forming another electrode layer of the at least two electrode layers located on the dielectric layer, two adjacent electrode layers of the at least two electrode layers being parallel to each other and arranged in different layers, the two adjacent electrode layers overlapping with each other and having the overlapping area, the dielectric layer being arranged between the two adjacent electrode layers, and the air gap being arranged in the dielectric layer located in the overlapping area,
wherein before forming the dielectric layer, the method further comprises forming a barrier layer on the electrode layer,
wherein forming the dielectric layer comprises:
forming a plurality of annular side walls on the barrier layer, the plurality of annular side walls being arranged on the barrier layer and interval arranged; and
forming the filling layer on the barrier layer, the filling layer covering the plurality of annular side walls and extending into the plurality of annular side walls and to be between adjacent annular side walls of the plurality of annular side walls, the dielectric layer comprising the plurality of annular side walls and the filling layer covering the plurality of annular side walls, and the air gap being arranged in the part in the filling layer located in each of the plurality of annular side walls and the part located between the adjacent annular side walls.