Patent ID: 11900124
Assignee: COHERENT LOGIX, INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. An apparatus, comprising:
one or more execution units that include multiple pipelines;
a fetch unit configured to fetch a multi-part instruction from an instruction stream, wherein the multi-part instruction includes a plurality of fields; and
a plurality of address generator units;
wherein a first address generator unit of the plurality of address generator units is configured to generate, based on a first field of the multi-part instruction, an address from which to retrieve first data to be stored in a first register for use by an execution unit for the multi-part instruction or a subsequent multi-part instruction;
wherein a second address generator unit of the plurality of address generator units is configured to generate, based on a second field of the multi-part instruction, an address from which to retrieve second data to be stored in a second register for use by an execution unit for the multi-part instruction or a subsequent multi-part instruction; and wherein the one or more execution units are configured to:
perform a first operation, operating on operands from a plurality of registers, using a first pipeline of the multiple pipelines, based on a third field of the plurality of fields; and
perform a second operation, operating on operands from the plurality of registers, using at least two pipelines of the multiple pipelines in parallel, based on a fourth field of the plurality of fields, wherein performing the second operation using the at least two pipelines in parallel comprises generating, by a second pipeline of the at least two pipelines, a first set of partial products and generating, by a third pipeline of the at least two pipelines, a second set of partial products dependent upon at least one partial product of the first set of partial products.