Patent ID: 11894043
Assignee: INTEGRATED SILICON SOLUTION INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 3:
4. The power management circuit in the low-power double data rate memory of claim 1, wherein the low dropout regulator comprises:
a transistor electrically connected between the first transmitting terminal and the second transmitting terminal; and
a comparator electrically connected to the first transmitting terminal, the second transmitting terminal and the transistor, wherein the comparator is configured to compare the reference voltage and the second voltage to generate a comparison signal, and the comparison signal is electrically connected to the transistor to adjust the voltage difference between the first voltage and the second voltage;
wherein the transistor is a PMOS transistor and has a source electrode, a gate electrode and a drain electrode, and the source electrode, the gate electrode and the drain electrode are electrically connected to the first voltage, the comparison signal and the second voltage, respectively.