Patent ID: 11948897
Assignee: PSEMI CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An integrated circuit susceptible to accumulated charge and fabricated on a silicon-on-insulator (SOI) high resistivity substrate, including at least one field effect transistor (FET) having a VGS characteristic and configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same VGS characteristic as during an active mode, thereby eliminating or reducing changes in accumulated charge, further including at least one substrate contact near at least one FET, each substrate contact comprising a resistive conduction path formed between a first contact region at a surface of a layer of the integrated circuit and a second contact region at or near a surface of the high resistivity substrate, wherein each substrate contact penetrates through at least one dielectric layer.