Patent ID: 11870441
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: nan (nan)
Classification: CPC nan | IPC G  H

Claim 18:
19. The method of claim 18, further comprising:
enabling the clock gating circuit in response to at least the first enable signal or the second enable signal, wherein enabling the clock gating circuit comprises:
generating the first control signal;
disabling and enabling, by the transmission gate, the first path between the first node and the second node in response to at least the inverted clock input signal or the output clock signal;
disabling, by at least the second transistor, the third path between the second node and the third node in response to at least the second control signal; and
setting, by the fourth transistor or a sixth transistor, the output clock signal in response to at least the inverted clock input signal;

wherein the clock input signal corresponds to the output clock signal.