Patent ID: 11929110
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 17:
18. The memory circuit of claim 16, wherein each word line post-decoder circuit of the first set of word line post-decoder circuits comprises:
a first set of AND logic gates configured to generate a first set of signals in response to the first set of local pre-decoder signals, one local pre-decoder signal of the second set of local pre-decoder signals and one of the first set of clock signals or the second set of clock signals; and
a first set of inverters coupled to the first set of AND logic gates, and configured to generate the first set of word line signals in response to the first set of signals, the first set of signals being inverted from the first set of word line signals.