Patent ID: 11887917
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A method of forming an encapsulated interconnect, the method comprising:
forming an encapsulation material on a land side of a semiconductor package substrate to contact a trace on the land side, the encapsulation material having an encapsulation height;
forming a via in the encapsulation material;
depositing a vertical interconnect in the via at a terminal end of the trace, the vertical interconnect having a portion that extends beyond the encapsulation height, the vertical interconnect having a frusto-conical cross-sectional area or a stepped right-cylindrical cross-sectional area, and wherein the vertical interconnect has a first height that extends from the trace to a plane at which the vertical interconnect emerges from the encapsulation material, a second height that extends beyond the encapsulation height, and a diameter on the plane at which the vertical interconnect emerges from the encapsulation material; and
assembling the vertical interconnect to a land side substrate at the portion that extends beyond the encapsulation height, and under conditions to form an electrical-bump mass between the encapsulation height and the land side substrate, the electrical-bump mass being an integral portion of the vertical interconnect, the second height being a height of a meniscus formed by the electrical-bump mass.