Patent ID: 11876025
Assignee: NANYA TECHNOLOGY CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor structure, comprising:
a wafer; and
a test structure, disposed on the wafer and comprising:
a first device, comprising a first source/drain layer and a first gate layer disposed above the first source/drain layer, wherein the first source/drain layer is disposed between two free ends of the first gate layer, wherein the first gate layer has a uniform width between the two free ends thereof;
a second device, comprising a second source/drain layer and a second gate layer disposed above the second source/drain layer, the second gate layer having a connecting end connected to the first gate layer and a free end, wherein the second source/drain layer is disposed between the connecting end and the free end of the second gate layer, wherein the second gate layer has a uniform width between the connecting end and the free end; and
a third device, disposed adjacent to the first device and comprising a third source/drain layer, wherein the first source/drain layer, the second source/drain layer, and the third source/drain layer are spaced apart from each other and are independent from each other;
wherein the first gate layer is disposed above the third source/drain layer at a position that the third source/drain layer is disposed between the two free ends of the first gate layer;
wherein the first gate layer is disposed along a first direction and the second gate layer is disposed along a second direction orthogonal to the first direction;
wherein the first source/drain layer and the third source/drain layer are separated by a first distance along the first direction;
wherein the second source/drain layer and the first gate layer are separated by a second distance along the second direction;
wherein the first distance is greater than the second distance.