Patent ID: 11908749
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. A method of forming a semiconductor structure, comprising:
forming a first pair of source/drain regions and a second pair of source/drain regions in a substrate;
depositing an interlayer dielectric layer over the substrate, the interlayer dielectric layer having a first trench between the first pair of source/drain regions and a second trench between the second pair of source/drain regions;
forming a layer stack over the interlayer dielectric layer in the first trench and the second trench, wherein the layer stack has a first number of layers in the first trench and a second number of layers, different from the first number of layers, in the second trench; and
depositing a conductive layer in the first trench and the second trench over the layer stack.