Patent ID: 11942377
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A semiconductor device, comprising:
a semiconductor substrate;
a p-type channel region, an n-type channel region, and a third channel region disposed over the semiconductor substrate;
a high-k gate dielectric layer disposed over each of the p-type channel region and the n-type channel region;
an n-type WFM layer over the n-type channel region and not over the p-type channel region or the third channel region, wherein the n-type WFM layer is over and in direct contact with the high-k gate dielectric layer;
a p-type WFM layer over both the n-type channel region and the p-type channel region, but not over the third channel region;
a glue metal layer over all three regions, wherein the high-k gate dielectric layer is disposed between the glue metal layer and the p-type channel region, wherein the glue metal layer is configured to provide a p-type work function over the p-type channel region, wherein the glue metal layer is over and in direct contact with the high-k gate dielectric layer; and
a fill metal layer disposed over and in direct contact with the glue metal layer.