Patent ID: 11900563
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. An apparatus, comprising:
a memory; and
one or more processors;
wherein the memory and the one or more processors are connected with each other; and
the memory stores computer-executable instructions for controlling the one or more processors to:
input a low-resolution image into a generator; and
generate a high-resolution image using the generator based on the low-resolution image by processing the low-resolution image through a plurality of super-resolution generating units arranged in series in the generator;
wherein a respective output from a respective one of the plurality of super-resolution generating units has a respective increased image resolution as compared to a respective input to the respective one of the plurality of super-resolution generating units;
wherein the respective one of the plurality of super-resolution generating units comprises a super-resolution generating block and a bilinear interpolation block;
wherein the memory further stores computer-executable instructions for controlling the one or more processors to:
input a respective input to the super-resolution generating block and the bilinear interpolation block, respectively;
process the respective input using the super-resolution generating block to generate a first intermediate output from the super-resolution generating block;
input the first intermediate output from the super-resolution generating block to the bilinear interpolation block; and
generate a second intermediate output using the bilinear interpolation block based on the respective input and the first intermediate output;
wherein the super-resolution generating block comprises a plurality of encoding modules and a plurality of decoding modules arranged in a u-net architecture;
a respective one of the plurality of encoding modules comprises a down-sampling convolutional layer, and a plurality of first residual blocks arranged in series; and
a respective one of the plurality of decoding modules comprises a plurality of second residual blocks arranged in series, and an up-sampling convolutional layer.