Patent ID: 11923455
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor device, comprising:
a substrate;
a gate structure over the substrate;
a plug disposed over and electrically connected to the gate structure; and
a hard mask structure over the gate structure, comprising a first hard mask layer and a second hard mask layer, wherein the first hard mask layer surrounds and is in contact with the plug, the second hard mask layer surrounds the first hard mask layer and has a bottom surface at the same level height as a bottom surface of the plug, the second hard mask layer contacts and covers a top surface of the first hard mask layer, and a material of the first hard mask layer is different from a material of the second hard mask layer, and wherein a bottom surface of the first hard mask layer is spaced apart from the second hard mask layer, and a portion of a bottom surface of the second hard mask layer is spaced apart from the first hard mask layer.