Patent ID: 11886737
Assignee: INFINEON TECHNOLOGIES AG
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A system comprising:
a memory device, the memory device comprising:
a plurality of memory cells comprising a plurality of legacy memory cells and a plurality of processor memory cells, the plurality of processor memory cells configured to store first data, the plurality of legacy memory cells configured to store second data, different than the first data;
a memory port coupled to the plurality of legacy memory cells and the plurality of processor memory cells, the memory port configured to read and/or write the first data to the plurality of processor memory cells and to read and/or write the second data to the legacy memory cells;
a logic unit coupled to the processor memory cells, the logic unit comprising digital circuitry configured to perform mathematic and logic operations; and
a control logic circuitry coupled to the memory port and the logic unit, the control logic circuitry configured to control the memory port to access the plurality of processor memory cells and the plurality of legacy memory cells, and the control logic circuitry configured to control the logic unit;

a processing device;
a specialized device; and
an interconnect coupling the memory port of the memory device to the specialized device and the processing device,
wherein the processing device is configured to provide, to the memory port, first instructions to perform processing operations on the first data stored in the plurality of processor memory cells,
wherein the memory device is configured to determine if the logic unit can perform the processing operations on the first data,
wherein in response to the memory device determining that the logic unit can perform the processing operations on the first data, the control logic circuitry is configured to cause the logic unit to perform the processing operations on the first data, and
wherein in response to the memory device determining that the logic unit cannot perform the processing operations on the first data, the control logic circuitry is configured to command the memory port to provide, to the specialized device, the first data and second instructions to perform the processing operations on the first data.