Patent ID: 11968823
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 8:
9. A semiconductor device comprising:
a substrate having a cell region, a peripheral region, and an interface region between the cell region and the peripheral region, the interface region including a device isolation layer;
a cell gate structure buried in the substrate of the cell region in a first direction that is parallel to a top surface of the substrate, and extending in the device isolation layer of the interface region of the substrate, the cell gate structure including a first conductive layer, a second conductive layer that is disposed on the first conductive layer, and a cell gate capping layer that is disposed on the second conductive layer;
a bit line structure arranged on the cell region of the substrate in a second direction that is perpendicular to the first direction, and extending on the device isolation layer of the interface region of the substrate;
a peripheral gate structure on the peripheral region of the substrate;
a first insulation layer arranged on the device isolation layer of the interface region of the substrate, and disposed between the bit line structure and the peripheral gate structure;
a second insulation layer on the first insulation layer;
a direct contact in the first insulation layer and the second insulation layer, the direct contact including a first portion and a second portion that is disposed on the first portion, the second portion of the direct contact including a first width that is adjacent to a top surface of the second insulation layer, and a second width that is adjacent to a bottom surface of the second insulation layer in the first direction or in the second direction; and
a wiring on the direct contact,
wherein the first portion of the direct contact passes through the first insulation layer, the cell gate capping layer and the second conductive layer of the cell gate structure,
wherein the first portion of the direct contact is in contact with the first conductive layer of the cell gate structure, and
wherein the first width of the second portion of the direct contact is greater than the second width of the second portion of the direct contact.