Patent ID: 11929125
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus, comprising:
a control circuit configured to connect to a plurality of sense circuits, each sense circuit comprising a set of internal user data latches, and to a respective external data transfer latch of each sense circuit, each sense circuit of the plurality of sense circuits is configured to connect to a respective memory cell of a set of memory cells, each memory cell is programmable to a data state of a set of data states in a program operation in which each respective external data transfer latch holds a first bit value for a subset of the set of data states and a second bit value for data states of the set of data states which are above the subset, the first bit value indicating a data state not prohibited from having a verify test and the second bit value indicating a data state prohibited from having a verify test, the control circuit is configured to:
for each sense circuit, load user data into the respective external data transfer latch and the set of internal user data latches to assign the data state of the set of data states to the respective memory cell in the program operation; and
at specified program loops of the program operation, shift the subset to encompass higher data states of the set of data states, and flip the second bit value to the first bit value for respective external data transfer latches for data states of the set of data states which become encompassed by the subset.