Patent ID: 11881276
Assignee: SK HYNIX INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H  Y | IPC G  H

Claim 8:
9. An error correcting code (ECC) decoder, comprising:
a variable node;
a memory comprising a memory region configured to have a size corresponding to a reliability value to be transmitted to the variable node;
a first converter configured to transmit a hard bit, received from a channel for a hard decoding operation of the variable node, to the memory to store the hard bit in a first area of the memory region, and transmit a subsequent hard bit, received from the channel, to the memory to store the subsequent hard bit in a second area of the memory region; and
a second converter configured to decide a reliability value corresponding to the hard bit based on data read from the memory region for the hard decoding operation, and transmit the reliability value to the variable node.