Patent ID: 11860747
Assignee: INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. An apparatus for performing a power stress test on a field programmable gate array (FPGA) acceleration card, comprising a processor and a memory, wherein the memory is configured to store a computer program, and the processor is configured to call the computer program stored in the memory and run the computer program to:
divide the FPGA acceleration card into a static region and a dynamic partial reconfiguration (PR) region according to a partial reconfiguration method; and burn FPGA firmware with a partial reconfiguration function to a Flash memory, the static region being a hardware logic implementation region for functional tests other than the power stress test, the dynamic PR region comprising a blank mode occupying no hardware resource and a power test mode for performing the power stress test, wherein the dynamic PR region in the blank mode is used for performing a test other than the power stress test in conjunction with the static region;
in response to receiving a request for power stress test, set an operating mode of the dynamic PR region as the power test mode; and load dynamic PR profiles burned in the Flash memory to the dynamic PR region; and
call power stress test modules to perform the power stress test in the dynamic PR region.