Patent ID: 11922220
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. The semiconductor apparatus of claim 15, wherein the logic coupled to the one or more substrates is to:
monitor the execution of one or more functions of the plurality of functions;
partition one or more computing resources of the computing system into one or more shared resources, each function of the plurality of functions having access to the one or more shared resource;
provide a scheduling of allocation of one or more computing resources for executing the plurality of functions, the scheduling being generated based, at least, upon history-based resource scheduling of functions being executed by the computing system;
redirect data of the one or more functions to selected computing devices for execution;
select one or more functions of the plurality of functions according to service level parameters associated with the one or more functions;
combine the selected one or more functions into a combined function for execution.