Patent ID: 11942954
Assignee: GIGADEVICE SEMICONDUCTOR (SHANGHAI) INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 14:
15. The DLL circuitry system of claim 14, wherein the DCC circuit comprises:
a duty cycle detection circuit coupled at an input terminal thereof to the output terminal of the replica clock buffer circuit and configured to detect a duty cycle of the feedback clock signal;
a DCC controller coupled to an output terminal of the duty cycle detection circuit and configured to generate a duty cycle control signal based on a detection result from the duty cycle detection circuit; and
a DCC adjustment circuit coupled to the DCC controller and the DLL delay line and configured to receive the external clock signal, generate a corresponding input clock signal and provide it to the DLL delay line, and adjust a duty cycle of the generated input clock signal under the control of the duty cycle control signal until the duty cycle of the internal clock signal reaches the predetermined value.