Patent ID: 11949430
Assignee: SK HYNIX INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 10:
11. A system for error code detection, comprising:
a data source comprising a first storage medium; and
a controller configured to perform LDPC encoding of data bit information from the data source and generate a codeword before transferring data from the first storage medium to a second storage medium,
wherein the controller is programmed to:
calculate partial syndromes using a user portion including the data and using a low density parity check matrix,
calculate a parity portion of the codeword using the partial syndromes and using a quasi-cyclic matrix having slots therein filled with at least one circulant matrix and other slots filled with all zero values, wherein the quasi-cyclic matrix GT satisfies p=sGT, where the parity portions p are expressed as a parity vector and the partial syndromes s are expressed as a syndrome vector,
generate the parity portion without matrix multiplication of sGT by segment processing of at least one segment of the quasi-cyclic matrix having the at least one circulant matrix, and
concatenate the user portion and the parity portion to complete the codeword, and transmit the codeword completed without matrix multiplication of sGT to the second storage medium.