Patent ID: 11955095
Assignee: LAPIS TECHNOLOGY CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. The output circuit according to claim 10,
wherein the controller sets a first period as a transient period for switching from the negative voltage signal to the positive voltage signal output from the first output terminal, a second period in which the positive voltage signal is output from the first output terminal, a third period as a transient period for switching from the positive voltage signal to the negative voltage signal output from the first output terminal, and a fourth period in which the negative voltage signal is output from the first output terminal,
wherein, in the first period, supply of the positive voltage signal from the positive voltage signal supply circuit is cut off, supply of the negative voltage signal from the negative voltage signal supply circuit is cut off, the third switch and the fourth switch are both turned on, the first control device and the second control device are activated and inactivated, respectively, the first voltage control circuit and the second voltage control circuit are inactivated and activated, respectively, control is performed such that the reference power supply voltage is supplied from the third voltage control circuit to the back gate of the first PMOS transistor switch, control is performed such that a voltage obtained by shifting the level of the voltage of the source or the drain of the first NMOS transistor switch is supplied from the fourth voltage control circuit to the back gate of the first NMOS transistor switch, and thus the first PMOS transistor switch is turned off, the first NMOS transistor switch is turned on, and the reference power supply voltage is supplied to the first node and the second node and the first output terminal,
wherein, in the second period, while supply of the negative voltage signal from the negative voltage signal supply circuit is continuously cut off, the positive voltage signal is supplied from the positive voltage signal supply circuit to the first node, the third switch and the fourth switch are turned off and on, respectively, the first control device and the second control device are inactivated and activated, respectively, the first voltage control circuit and the second voltage control circuit are activated and inactivated, respectively, control is performed such that a voltage obtained by shifting the level of the voltage of the source or the drain of the first PMOS transistor switch is supplied from the third voltage control circuit to the back gate of the first PMOS transistor switch, control is performed such that the reference power supply voltage is supplied from the fourth voltage control circuit to the back gate of the first NMOS transistor switch, and thus the first PMOS transistor switch is turned on, the first NMOS transistor switch is turned off, the positive voltage signal is supplied to the first output terminal via the first PMOS transistor switch, and the reference power supply voltage is supplied to the second node via the fourth switch,
wherein, in the third period, supply of the negative voltage signal from the negative voltage signal supply circuit is continuously cut off, supply of the positive voltage signal from the positive voltage signal supply circuit is cut off, the third switch and the fourth switch are both turned on, the first control device and the second control device are continuously inactivated and activated, respectively, the first voltage control circuit and the second voltage control circuit are continuously activated and inactivated, respectively, control is performed such that a voltage obtained by shifting the level of the voltage of the source or the drain of the first PMOS transistor switch is continuously supplied from the third voltage control circuit to the back gate of the first PMOS transistor switch, control is performed such that the reference power supply voltage is continuously supplied from the fourth voltage control circuit to the back gate of the first NMOS transistor switch, and thus the first PMOS transistor switch is turned on, the first NMOS transistor switch is turned off, and the reference power supply voltage is supplied to the first node and the second node and the first output terminal, and
wherein, in the fourth period, while supply of the positive voltage signal from the positive voltage signal supply circuit is continuously cut off, the negative voltage signal is supplied from the negative voltage signal supply circuit to the second node, the third switch and the fourth switch are turned on and off, respectively, the first control device and the second control device are activated and inactivated, respectively, the first voltage control circuit and the second voltage control circuit are inactivated and activated, respectively, control is performed such that the reference power supply voltage is supplied from the third voltage control circuit to the back gate of the first PMOS transistor switch, control is performed such that a voltage obtained by shifting the level of the voltage of the source or the drain of the first NMOS transistor switch is supplied from the fourth voltage control circuit to the back gate of the first NMOS transistor switch, and thus the first PMOS transistor switch is turned off, the first NMOS transistor switch is turned on, the negative voltage signal is supplied to the first output terminal via the first NMOS transistor switch, and the reference power supply voltage is supplied to the first node via the third switch.