Patent ID: 11895845
Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 5:
6. The memory device according to claim 4, wherein the first dielectric layer in the stack is close to the vertical active region, and the second dielectric layer in the stack is close to the electrode structure; and
wherein the first dielectric layer and the charge trapping layer in the stack of the first gate dielectric layer are respectively arranged in same layers as the first dielectric layer and the charge trapping layer in the stack of the second gate dielectric layer, and
the first dielectric layer and the charge trapping layer both extend along a sidewall of the vertical active region, and the second dielectric layer in the stack of each of the first gate dielectric layer and the second gate dielectric layer extends along a sidewall, an upper surface and a lower surface of a corresponding electrode layer.