Patent ID: 11971992
Assignee: LATTICE SEMICONDUCTOR CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A secure programmable logic device (PLD) failure characterization system, comprising:
a secure PLD, wherein the secure PLD comprises a plurality of programmable logic blocks (PLBs) arranged in a PLD fabric of the secure PLD, and a configuration engine configured to program the PLD fabric according to a configuration image stored in a non-volatile memory (NVM) of the secure PLD and/or coupled through a configuration input/output (I/O) of the secure PLD to the configuration engine, wherein the secure PLD is configured to perform a computer-implemented method comprising:
receiving a failure characterization (FC) command from the PLD fabric or an external system coupled to the secure PLD through the configuration I/O;
executing the FC command, wherein the executing the FC command comprises erasing and/or nullifying at least a portion of the NVM of the secure PLD to remove customer data associated with the configuration image;
loading a debug configuration into the PLD fabric while the portion of the NVM remains erased and/or nullified; and
performing a debug process, wherein the performing the debug process comprises booting the debug configuration by the PLD fabric that is configured to identify and/or characterize failures in the operation of any one or combination of elements of the secure PLD.