Patent ID: 11900991
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. The integrated circuit of claim 14, wherein each write unit of the plurality of write units comprises a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor;
a source of the third NMOS transistor is grounded, a gate of the third NMOS transistor receives the write control signal, and a drain of the third NMOS transistor is electrically connected to a source of the fourth NMOS transistor;
a gate of the fourth NMOS transistor is electrically connected to one of the plurality of global data lines, and a drain of the fourth NMOS transistor is electrically connected to one of the plurality of complementary local data lines; and
a source of the fifth NMOS transistor is electrically connected to the one of the plurality of global data lines, a gate of the fifth NMOS transistor receives the write control signal, and a drain of the fifth NMOS transistor is electrically connected to one of the plurality of local data lines.