Patent ID: 11882708
Assignee: SK HYNIX INC.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 0:
1. A method of manufacturing an electronic device, the method comprising:
forming a plurality of line patterns on a substrate, each of the line patterns extending in a first direction and including a first conductive line and a memory pattern, which are sequentially stacked;
forming a first liner layer on sidewalls of each of the plurality of line patterns, the first liner layer including a plurality of layers having different energy band gaps;
forming an insulating interlayer on the substrate to fill spaces between the line patterns;
forming a plurality of second conductive lines on the line patterns and the insulating interlayer, the second conductive lines extending in a second direction intersecting the first direction;
etching the first liner layer, the insulating interlayer and the memory pattern using the second conductive lines as an etch barrier to expose the first conductive line to form a plurality of memory cells; and
forming a second liner layer on both sidewalls of each of the memory cells, the etched first liner layer and both sidewalls of the etched insulating interlayer, the second liner layer including a plurality of layers having different energy band gaps.