Patent ID: 11966736
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. The interconnect device of claim 1, wherein the read data circuitry further comprises:
an adder configured to, based on the control signal, add the data read from the memory and the data of the one sub-data circuitry to generate added data;
a first multiplexer (MUX) configured to output either one of the data read from the memory and the added data of the adder, based on the control signal;
a demultiplexer (DEMUX) configured to output, to the one sub-data circuitry, data output from the first MUX, based on the control signal; and
a second MUX configured to output the data of the one sub-data circuitry, based on the control signal.