Patent ID: 11973109
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of fabricating a semiconductor device, comprising:
forming a first fin pattern extending in a first direction;
forming a second fin pattern extending in the first direction and spaced apart from the first fin pattern in a second direction;
forming a pre gate structure disposed on the first fin pattern and the second fin pattern and extending in the second direction;
forming a gate insulating support separating the pre gate structure into a first gate structure and a second gate structure, the first gate structure intersecting the first fin pattern and the second gate structure intersecting the second fin pattern;
removing the second gate structure and a part of the second fin pattern; and
forming an element isolation structure at a position from which the second gate structure and the second fin pattern are removed,
wherein the first fin pattern includes a long side extending in the first direction and a short side extending in the second direction, and
wherein the pre gate structure overlaps an end of the first fin pattern including the short side of the first fin pattern.