Patent ID: 11960426
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. A multiprocessing (MP) system comprising:
a first pair of processing chips that are communicatively connected by a first data lane group comprised within a first cable that primarily communicatively connects the first pair of processing chips, the first cable further comprising a second data lane group that secondarily communicatively connects a second pair of processing chips;
a third data lane group that is complementary to the first data lane group and communicatively connects the first pair of processing chips and is comprised within a second cable that secondarily communicatively connects the first pair of processing chips, the second cable further comprising a fourth data lane group complementary to the second data lane group and that primarily communicatively connects the second pair of processing chips;
wherein the first data lane group and the fourth data lane group have more data lanes relative to the second data lane group and the third data lane group, respectively;
one or more first interfaces that prohibit communicative connection of the first pair of processing chips through the first cable and that prohibit communicative connection of the second pair of processing chips through the first cable, when the third data lane group and the fourth data lane group each comprise at least a threshold number of operational data lanes and when the first data lane group is operating in a degraded state, wherein the threshold number of data lanes is a smallest majority of data lanes within the fourth data lane group; and
one or more second interfaces that permit communicative connection of the first pair of processing chips through the second cable and that permit communicative connection of the second pair of processing chips through the second cable.