Patent ID: 11923410
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 18:
19. An integrated circuit comprising:
a nanowire comprising a semiconductor material, the nanowire having a bottommost surface;
a gate structure in contact with and wrapped around the nanowire the gate structure defining a channel region in the nanowire;
a source region in contact with the nanowire;
a drain region in contact with the nanowire such that the channel region of the nanowire is between the source region and the drain region;
a first isolation region under an entirety of the source region and having a top surface in contact with an entirety of a bottom surface of the source region laterally adjacent to the channel region, the first isolation region having an uppermost surface above the bottommost surface of the nanowire, wherein the nanowire is not vertically intervening between the first isolation region and the source region; and
a second isolation region under an entirety of the drain region and having a top surface in contact with an entirety of a bottom surface of the drain region laterally adjacent to the channel region, the second isolation region having an uppermost surface above the bottommost surface of the nanowire, wherein the nanowire is not vertically intervening between the second isolation region and the drain region.