Patent ID: 11948942
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An integrated circuit device, comprising:
a fin-type active area along a first horizontal direction on a substrate;
a nanosheet stack including at least one nanosheet on a fin top of the fin-type active area, the at least one nanosheet being spaced apart from the fin top in a vertical direction;
a gate structure along a second horizontal direction crossing the first horizontal direction, the gate structure surrounding the at least one nanosheet; and
a source/drain area on the fin-type active area, the source/drain area contacting the at least one nanosheet, and the source/drain area including an outer blocking layer, an inner blocking layer, and a main body layer sequentially stacked on the fin-type active area,
wherein each of the outer blocking layer and the main body layer includes a Si1-xGex layer, where x≠0, and the inner blocking layer includes a Si layer, and
wherein a level of a lowermost surface of the source/drain area is lower than a level of the fin top in the vertical direction.