Patent ID: 11923321
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor structure comprising a memory die, wherein the memory die comprises:
dielectric isolation rails embedded within a substrate semiconductor layer;
alternating stacks of insulating layers and electrically conductive layers located over the substrate semiconductor layer, wherein the alternating stacks are laterally spaced apart along a second horizontal direction by line trenches that laterally extend along a first horizontal direction;
arrays of memory stack structures vertically extending through the alternating stacks, wherein each of the memory stack structures comprises a respective vertical stack of memory elements and a respective vertical semiconductor channel; and
a metallic source contact layer located on a distal horizontal surface of the substrate semiconductor layer and contacting distal horizontal surfaces of the dielectric isolation rails.