Patent ID: 11928500
Assignee: CADENCE DESIGN SYSTEMS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. The device of claim 17, wherein the performing routing of the plurality of networks comprises:
while the tree data structure is not empty, periodically:
determining whether the task queue is empty; and
in response to determining that the task queue is not empty:
causing a select thread of the plurality of threads to process a next task, in the task queue, for routing all networks in a select group of networks;
determining when the next task has completed processing by the select thread; and
in response to determining that the next task has completed processing:
removing, from the tree data structure, a select leaf node associated with the select group of networks;
determining whether a parent node of the select leaf node has become a new leaf node; and
in response to determining that the parent node has become the new leaf node, adding a new task, to the task queue, for routing all networks in a particular group of networks associated with the parent node.