Patent ID: 11921641
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. An address-translation method for a data storage device, the method comprising:
mapping a plurality of superblocks of a nonvolatile memory of the data storage device to a plurality of zones, each of the plurality of zones being of a type requiring sequential write of host data, an erase block being a minimum erasable unit of the plurality of superblocks;
performing logical-to-physical (L2P) address translation using a controller coupled to the nonvolatile memory and further using a compacted L2P table having an erase-block granularity; and
obtaining, via the controller, a corresponding physical address for a logical address of a zone of the plurality of zones by:
retrieving a physical address of a corresponding erase block from the compacted L2P table based on the logical address;
calculating a corresponding word-line number, a corresponding string-line number, a corresponding page-type identifier, and a corresponding page offset based on the logical address; and
combining the physical address that is retrieved with the corresponding word-line number, the corresponding string-line number, the corresponding page-type identifier, and the corresponding page offset that are calculated.