Patent ID: 11915975
Assignee: RENESAS ELECTRONICS CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. The method of manufacturing the semiconductor device according to claim 1, further comprising, after the (e), steps of:
(e1) forming a first wiring layer on the interlayer insulating film; and
(e2) forming a second wiring layer on the first wiring layer,
wherein, in the (b), a third MISFET as a dummy MISFET composing the TEG is formed on the semiconductor layer in the second region,
wherein the second MISFET includes a first gate electrode,
wherein the third MISFET includes a second gate electrode,
wherein the plurality of second contact plugs includes:
a first gate plug electrically connected to the first gate electrode; and
a second gate plug electrically connected to the second gate electrode,

wherein the first wiring layer includes:
a first gate wiring electrically connected to the first gate plug; and
a second gate wiring electrically connected to the second gate plug,

wherein the first gate wiring and the second gate wiring are separated from each other, and
wherein the first gate wiring and the second gate wiring are electrically connected via a third gate wiring included in the second wiring layer.