Patent ID: 11881489
Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 2:
3. An EL display device, comprising:
a first EL display element;
a second EL display element;
a first pixel circuit; and
a second pixel circuit,
wherein the first EL display element comprises a first pixel electrode,
wherein the first EL display element is electrically connected to the first pixel electrode,
wherein the second EL display element comprises a second pixel electrode,
wherein the second EL display element is electrically connected to the second pixel electrode,
wherein the first EL display element and the second EL display element exhibit colors different from each other,
wherein the first pixel circuit is adjacent to the second pixel circuit,
wherein the first pixel circuit comprises a first transistor, a second transistor, a first capacitor, a first gate line, a first wiring, and a second wiring,
wherein the second pixel circuit comprises a third transistor, a fourth transistor, a second capacitor, a second gate line, the first wiring, and a third wiring,
wherein a gate of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein the gate of the first transistor is electrically connected to one electrode of the first capacitor,
wherein one of a source and a drain of the first transistor is electrically connected to the first pixel electrode,
wherein the other of the source and the drain of the first transistor is electrically connected to the first wiring,
wherein the first gate line comprises a region configured to be a gate of the second transistor,
wherein the other of the source and the drain of the second transistor is electrically connected to the second wiring,
wherein the other electrode of the first capacitor is electrically connected to the first wiring,
wherein a gate of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,
wherein the gate of the third transistor is electrically connected to one electrode of the second capacitor,
wherein one of a source and a drain of the third transistor is electrically connected to the second pixel electrode,
wherein the other of the source and the drain of the third transistor is electrically connected to the first wiring,
wherein the second gate line comprises a region configured to be a gate of the fourth transistor,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the third wiring,
wherein the other electrode of the second capacitor is electrically connected to the first wiring,
wherein the first pixel electrode comprises a region overlapping with a channel formation region of the first transistor,
wherein the second pixel electrode comprises a region overlapping with the first capacitor,
wherein the second pixel electrode does not overlap with a channel formation region of the fourth transistor,
wherein the second pixel electrode does not overlap with the channel formation region of the first transistor, and
wherein the second pixel electrode comprises a region overlapping with a channel formation region of the second transistor.