Patent ID: 11901005
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 4:
5. An apparatus, comprising:
a first memory cell comprising first and second dielectric capacitors configured to store first charges representing complementary logical values;
a second memory cell comprising first and second ferroelectric capacitors configured to store second charges representing complementary logical values, both the first and second ferroelectric capacitors coupled to a first plate line;
a first bit line selectably coupled to the first ferroelectric capacitor of the second memory cell and to the first dielectric capacitor of the first memory cell; and
a second bit line selectably coupled to the second ferroelectric capacitor of the second memory cell and to the second dielectric capacitor of the first memory cell;
a first word line selectably coupled to the first memory cell; and
a second word line selectably coupled to the second memory cell,
wherein, when the first and second word lines are driven to a same voltage, the first memory cell is further configured store the first charges to the first and second dielectric capacitors of the first memory cell and the second memory cell is configured to restore the second charges to the first and second ferroelectric capacitors.