Patent ID: 11967386
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 20:
21. An apparatus, comprising:
a memory device comprising a plurality of pages of memory; and
a processing device coupled to the memory device, the processing device to perform operations comprising:
performing a program verify operation on a plurality of memory cells in an array of memory cells, wherein the program verify operation indicates whether a voltage in a particular memory cell of the plurality of memory cells is below or equal to or exceeds a program verify voltage;
in response to at least one memory cell of the plurality of memory cells with a voltage below a corresponding program verify voltage, detecting a margin distance of the at least one memory cell to be less than a threshold margin distance;
setting touch-up parameters for the at least one memory cell;
causing a transfer of data from the at least one memory cell to a cache; and
reprogramming the at least one memory cell using the set touch-up parameters to increase the margin distance, wherein the increased margin distance reduces errors when reading out data from the plurality of memory cells.