Patent ID: 11893192
Assignee: SENSEL, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 21:
22. A system, comprising: a processor; and a memory that stores executable instructions that, when executed by the processor, facilitate performance of operations, wherein the operations comprise: dividing a first column electrode of a group of multiple column electrodes into a plurality of first column sub-electrodes and at least a second column electrode of the group of multiple column electrodes into a plurality of second column sub-electrodes; interleaving first column sub-electrodes of the plurality of first column sub-electrodes with second column sub-electrodes of the plurality of second column sub-electrodes in a first direction, resulting in a first layer; interleaving multiple row electrodes of a group of multiple row electrodes in a second direction, resulting in a second layer; overlapping the first layer and the second layer orthogonally; facilitating a bi-linear fall-off in sensitivity via a structure of the group of multiple column electrodes and the group of multiple row electrodes; dividing a first row electrode of the group of multiple row electrodes into a plurality of first row sub-electrodes and at least a second row electrode of the group of multiple row electrodes into a plurality of second row sub-electrodes; and interleaving first row sub-electrodes of the plurality of first row sub-electrodes with second row sub-electrodes of the plurality of second row sub-electrodes in the second direction.