Patent ID: 11875835
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A read and write method of a memory, wherein the memory comprises a storage unit; the storage unit comprises a storage element, a first selective transistor, a second selective transistor and a third selective transistor; the memory is configured to change a memory state of the storage element by a first current and a second current that are exist simultaneously; the memory further comprises a source line electrically connected to a first end of the storage element, a bit line and a write bit line; the first selective transistor is configured to electrically connect a second end of the storage element with the bit line in response to a first control signal; the second selective transistor is configured to electrically connect a first end of the source line with the write bit line in response to a second control signal; the third selective transistor is configured to transmit a high level or a low level to a second end of the source line in response to a third control signal; when performing a write operation on the memory, the method comprises:
simultaneously providing the first current and the second current to the memory during the write operation being performed;
wherein the first current flows through the storage element and the second current flows through the source line without flowing through the storage element, and the first selective transistor, the second selective transistor and the third selective transistor are all turned on; and
when performing a read operation on the memory, the method comprises:
providing a third current to the memory;
wherein the third current flows from the bit line to the second end of the source line through the storage element, the first selective transistor and the third selective transistor are both turned on, and the second selective transistor is turned off.