Patent ID: 11922992
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. The memory device of claim 17, wherein the sub word line driving signal encoder comprises:
a plurality of first AND circuits configured to output the plurality of first sub word line driving signals in a first order based on the odd main word line being driven by the plurality of main word line driving signals;
a plurality of second AND circuits configured to output the plurality of first sub word line driving signals in a second order based on the even main word line being driven by the plurality of main word line driving signals;
a plurality of first NOR circuits each configured to receive a first output among the plurality of first AND circuits and a second output among the plurality of second AND circuits and perform a NOR operation on the first output and the second output; and
a plurality of first inverters configured to perform an inverting operation on output values of the plurality of first NOR circuits.