Patent ID: 11961578
Assignee: NANYA TECHNOLOGY CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A test device, coupled to a memory device for testing an error correction and checking (ECC) counter, comprising:
a controller, being configured to:
select one of a plurality of memory rows of the memory device to be a selected memory row, and make the selected memory row of the memory device to be a victim row;
perform a plurality of error correction scrub (ECS) operations on the memory device;
read a plurality of mode registers to obtain an address of a recorded victim row after the ECS is performed;
compare the address of the recorded victim row with an address of the selected memory row to generate a test result; and
determine a function of the ECC counter works normally in response to the test result indicating that the address of the recorded victim row obtained from the plurality of mode register matches the address of the selected memory row.