Patent ID: 11948628
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A memory system comprising:
a group of memory cells including:
a first memory cell coupled between a first select line and a first bit line,
a second memory cell coupled between the first bit line and a second select line,
a third memory cell coupled between the second select line and a second bit line, and
a fourth memory cell coupled between the second bit line and a third select line, wherein the first to third select lines are in parallel with one another; and

a memory controller coupled to the group of memory cells, wherein the memory controller is to:
electrically float the first bit line and the second bit line, while electrically coupling the first select line and the third select line to determine a multi-level data stored by the group of memory cells.