Patent ID: 11943915
Assignee: SK HYNIX INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A three-dimensional memory device comprising:
a lower stack and an upper stack stacked in a vertical direction and each including a plurality of word lines stacked alternately with a plurality of interlayer dielectric layers in the vertical direction,
wherein each of the lower stack and the upper stack includes a first cell part, a second cell part, a coupling part that couples the first cell part and the second cell part, and a staircase part that extends parallel to the coupling part between the first cell part and the second cell part and that includes a plurality of pad areas, which are arranged in a stepwise manner and correspond to the plurality of word lines, and
wherein the coupling part of the upper stack is disposed to overlap with the staircase part of the lower stack in the vertical direction, and the staircase part of the upper stack is disposed to overlap with the coupling part of the lower stack in the vertical direction, and
wherein each of the first cell part, the second cell part, the coupling part and the staircase part includes the plurality of word lines and the plurality of interlayer dielectric layers alternately stacked in the vertical direction,
further comprising:
a plurality of first vertical vias passing vertically through the staircase part of the lower stack;
a plurality of second vertical vias passing vertically through the coupling part of the lower stack;
a plurality of third vertical vias passing vertically through the coupling part of the upper stack and coupling to the plurality of first vertical vias, respectively; and
a plurality of fourth vertical vias passing vertically through the staircase part of the upper stack and coupling to the plurality of second vertical vias, respectively,
wherein the plurality of first vertical vias correspond to the plurality of word lines, respectively, of the lower stack, pass through the plurality of pad areas of the plurality of word lines, and are electrically coupled to the plurality of corresponding word lines, and
wherein the plurality of fourth vertical vias correspond to the plurality of word lines, respectively, of the upper stack, pass through the plurality of pad areas of the plurality of word lines, and are electrically coupled to the plurality of corresponding word lines.