Patent ID: 11935590
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory circuit for performing a matrix-vector multiplication of a matrix with a vector,
the memory circuit comprising:
a memory crossbar array comprising:
a plurality of row lines;
a plurality of column lines; and
a plurality of junctions arranged between the plurality of row lines and the plurality

of column lines, wherein each junction comprises a programmable resistive element and
an access element for accessing the programmable resistive element; and
a readout circuit configured for performing bipolar read operations by applying either positive read voltages of one or more first amplitudes or negative read voltages of one or more second amplitudes, wherein the one or more first amplitudes of the positive read voltages and the corresponding one or more second amplitudes of the negative read voltages are each different from each other by a correction factor, thereby correcting polarity dependent output current asymmetricities.