Patent ID: 11955201
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A memory device, comprising:
a plurality of memory arrays each comprising a plurality of switches and a plurality of memory cells in a plurality of columns, wherein the plurality of switches are configured to be selectively turned on in response a control signal, wherein the plurality of memory arrays are separated from each other in a first direction,
a first word line extending along the first direction;
a second word line extending along a second direction,
wherein the first word line and the second word line are coupled to first memory cells that are arranged in N-th rows and M-th columns in each memory array of the plurality of memory arrays, wherein N and M are positive integers,
wherein control terminals of a first switch of the plurality of switches and a second switch of the plurality of switches are coupled together to a control line; and
a third word line coupled to a second memory cell arranged in the N-th row and a (M+1)-th column in a first memory array of the plurality of memory arrays, the third word line being different from the first and second word lines.