Patent ID: 11901237
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A device comprising:
a semiconductor fin over a substrate;
a gate structure over the semiconductor fin, wherein the gate structure comprises:
a gate dielectric layer over the semiconductor fin; and
a gate metal covering the gate dielectric layer;

gate spacers on opposite sides of the gate structure;
a dielectric feature over the substrate, wherein the dielectric feature is in contact with the gate metal, the gate dielectric layer, and the gate spacers, and an interface between the gate metal and the dielectric feature is substantially aligned with an interface between the dielectric feature and one of the gate spacers; and
an interlayer dielectric (ILD) layer laterally surrounding the gate structure, wherein the dielectric feature comprises:
a first portion in contact with the gate structure; and
a second portion embedded in the ILD layer, wherein a bottom surface of the first portion is lower than a bottom surface of the second portion.