Patent ID: 11942557
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 5:
6. A semiconductor device comprising:
a lower first layer on a substrate;
a second layer on the lower first layer;
an upper first layer on the second layer; and
a source drain region on the second layer between a first set of semiconductor channel layers vertically aligned and stacked one on top of another separated by a work function metal, and a second set of semiconductor channel layers vertically aligned and stacked one on top of another separated by the work function metal, wherein vertical side surfaces of the semiconductor channel layers are vertically aligned with vertical side surfaces of the upper first layer, in both the first set of semiconductor channel layers and the second set of semiconductor channel layers, wherein a combined thickness of the lower first layer, the second layer and the upper first layer is approximately the same as a thickness of the work function metal between the semiconductor channel layers in both the first set of semiconductor channel layers and the second set of semiconductor channel layers.