Patent ID: 11909236
Assignee: MAKITA CORPORATION
Field: nan (nan)
Classification: CPC nan | IPC B  H

Claim 15:
16. An electrical apparatus, comprising:
a housing;
first and second battery interfaces disposed on the housing and configured to electrically and mechanically connect to first and second battery packs, respectively, wherein a negative battery terminal of the first battery interface is electrically connected in series with a positive battery terminal of the second battery interface, the first battery pack contains a first microprocessor and a first signal terminal configured to transmit first communication signals from the first microprocessor, and the second battery pack contains a second microprocessor and a second signal terminal configured to transmit second communication signals from the second microprocessor;
a controller disposed within the housing and comprising a third microprocessor configured to receive the first and second communication signals respectively outputted from the first and second microprocessors via the first and second signal terminals, wherein in the state in which the first and second battery packs are respectively electrically connected to the first and second battery interfaces, the first microprocessor outputs the first communication signal via the first signal terminal in a first voltage range, the second microprocessor outputs the second communication signal via the second signal terminal in a second voltage range that is lower than the first voltage range and the third microprocessor outputs a third communication signal in the second voltage range;
a first signal communication path disposed within the housing and configured to communicate the first communication signal from the first microprocessor to the third microprocessor, the first signal communication path being configured to shift a voltage level of the first communication signal in the first voltage range to a voltage level that is in the second voltage range suitable for inputting into the third microprocessor;
a second signal communication path disposed within the housing and configured to communicate the third communication signal from the third microprocessor to the first microprocessor, the second communication path being configured to shift a voltage range of the third communication signal in the second voltage range to a voltage level that is in the first voltage range suitable for inputting into the first microprocessor; and
a third signal communication path disposed within the housing and configured to communicate the second communication signal in the second voltage range from the second microprocessor to the third microprocessor without shifting the second voltage range.