Patent ID: 11886352
Assignee: T-HEAD (SHANGHAI) SEMICONDUCTOR CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A computer-implemented method, comprising:
receiving a root node identifier corresponding to a root node in a graph for graph neural network (GNN) processing;
determining a plurality of node identifiers for a plurality of nodes in the graph according to locations of the plurality of nodes in the graph relative to the root node;
mapping the plurality of node identifiers respectively to physical memory addresses in a memory, wherein:
each of the physical memory addresses in the memory stores attribute data of the node identified by the corresponding node identifier, and
each of the physical memory addresses comprises a memory bank identifier of a memory bank, wherein each memory bank stores a plurality of rows, columns, or memory pages;

selecting, based on the memory bank identifiers of the physical memory addresses, a subset of the physical memory addresses that maximizes intra-memory-bank sequential memory access;
de-mapping the selected subset of the physical memory addresses into corresponding node identifiers to obtain one or more candidate node identifiers; and
sampling one or more graph node identifiers at least from the one or more candidate node identifiers for the GNN processing.