Patent ID: 11967367
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 10:
11. A nonvolatile memory device comprising:
a memory cell array including a plurality of memory cells arranged in rows and columns, wherein two or more of the memory cells are stacked in a direction perpendicular to a substrate;
a row decoder circuit connected with the rows of the memory cells through wordlines, and configured to select one wordline of the wordlines in a test operation including a first program operation and a second program operation as a target of the first and second program operations;
a page buffer circuit connected with the columns of the memory cells through bitlines, and configured to store first data to be written in the memory cells connected with the selected wordline in the first program operation and to store second data to be written in the memory cells connected with the selected wordline in the second program operation; and
a pass/fail check circuit connected with the page buffer circuit, and configured to determine a pass or a fail of each of the first program operation and the second program operation in the test operation,
wherein the pass/fail check circuit detects a first program speed from the memory cells connected with the selected wordline in the first program operation, detects a second program speed from the memory cells connected with the selected wordline in the second program operation, and determines a test fail based on the first program speed and the second program speed.