Patent ID: 11934685
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A system comprising:
a non-volatile memory device; and
a processing device, operatively coupled with the non-volatile memory device, to perform operations comprising:
maintaining, on a volatile memory device, a quad-to-single (Q2S) data structure comprising a plurality of Q2S mapping entries, wherein each Q2S mapping entry is identified by a physical address of a quad-level cell (QLC) block stripe of the non-volatile memory device and comprises a corresponding bit flag reflecting programming state of the QLC block stripe and a pointer to a linked list of SLC block stripes on the volatile memory device;
responsive to allocating the QLC block stripe, updating an entry of a logical-to-physical (L2P) data structure with the physical address of the QLC block stripe;
responsive to allocating a plurality of single-level cell (SLC) block stripes of the non-volatile memory device for programming of data to be programmed to the QLC block stripe, initializing the linked list to be stored in an entry of the Q2S data structure associated with the entry of the L2P data structure with the physical address of the QLC block stripe; and
for each SLC block of the plurality of SLC blocks, appending to the linked list a physical address of a respective SLC block stripe of the plurality of SLC block stripes.