Patent ID: 11869567
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 4:
5. The refresh control circuit of claim 1, further comprising:
a timeout selection sub-circuit, connected to an input end of the random output sub-circuit, and configured to: sequentially receive L row activation commands, L pre-charging commands, and the L single-row addresses corresponding to the L row activation commands, wherein each row activation command corresponds to a single-row address, the row activation command is configured to turn on a word line pointed to by the single-row address, and the pre-charging command is configured to turn off the word line; and when a single enabling duration of the n word lines is greater than the preset duration, output the n single-row addresses corresponding to the n word lines, wherein 0≤n≤L.