Patent ID: 11880687
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 2:
3. The system of claim 1, wherein the processor comprises:
a core control circuit comprising:
a thread control memory comprising a thread identifier register configured to store a plurality of thread identifiers, a program count register configured to store an initial program count, and a data cache configured to store a received argument or a general-purpose register configured to store the received argument;
an execution queue coupled to the thread control memory; and
a control logic and thread selection circuit coupled to the execution queue and to the thread control memory, the control logic and thread selection circuit configured, in response to a second work descriptor data packet having the initial program count and the received argument, to assign a thread identifier of the first plurality of thread identifiers to an execution thread and to place the thread identifier in the execution queue, the control logic and thread selection circuit further configured to select the thread identifier for execution of the execution thread;, and
a processor core coupled to the core control circuit, the processor core configured to execute at least one instruction using the received argument for the execution thread, the at least one instruction corresponding to the initial program count.