Patent ID: 11949593
Assignee: CISCO TECHNOLOGY, INC.
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC G  H

Claim 9:
10. A system comprising:
a memory storage; and
a processing unit coupled to the memory storage, wherein the processing unit is operative to:
receive, in an Autonomous System (AS) from outside the AS, a packet having an address destine for a host device inside the AS, the address comprising a network prefix and an interface identifier (ID);
determine a first cypher algorithm used to encode the address based on a cypher value in a predetermined cypher bit range in the network prefix;
decode the address, wherein decoding the address comprises applying the first cypher algorithm to decode an coding bit range in the address that is less significant than the cypher bit range; and
use the decoded address to send the data packet to the host device inside the AS.