Patent ID: 11871582
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. A method of forming integrated circuitry comprising a lower array comprising vertical transistors; the lower-array vertical transistors individually comprising a lower-array top source/drain region, a lower-array bottom source/drain region, a lower-array channel region vertically between the lower-array top and bottom source/drain regions, and a lower-array gate operatively laterally-adjacent the lower-array channel region; an upper array of vertical transistors spaced above the lower array of vertical transistors, the lower-array vertical transistors individually comprising an upper-array top source/drain region, an upper-array bottom source/drain region, an upper-array channel region vertically between the upper-array top and bottom source/drain regions, and an upper-array gate operatively laterally-adjacent the upper-array channel region; insulating material vertically between and spacing the lower and upper arrays relative one another; the method comprising:
in multiple time-spaced microwave annealing steps, microwave annealing at least the upper-array channel region; the multiple time-spaced microwave annealing steps reducing average concentration of elemental-form H in the upper-array channel region from what it was before start of the multiple time-spaced microwave annealing steps, the reduced average concentration of elemental-form H being 0.005 to less than 1 atomic percent.