Patent ID: 11946970
Assignee: TEKTRONIX, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 19:
20. The non-transitory computer-readable storage medium of claim 19 wherein the user-selectable options include one or more of:
a selectable option to choose one or more different high-speed I/O protocols with which to perform margin testing test based on the multi-lane high speed I/O link of the DUT;
a selectable option to test multiple ports of the DUT with mixed protocols simultaneously;
a selectable option to output run-to-run variation in margin over any number of margin test runs of the test device on the multi-lane high speed I/O link;
a selectable option to implement fixed Tx Equalization (EQ) on the DUT to test how much of margin variation is due to Tx EQ training variation;
a selectable option to use Fixed Continuous Time Linear Equalization (CTLE) in receivers of the test device to test impact of receiver equalization on margin of the multi-lane high speed I/O link of the DUT;
a selectable option to use Decision Feedback Equalization (DFE) in the receivers of the test device to test impact of receiver equalization on margin of the multi-lane high speed I/O link of the DUT;
a selectable option to calculate expected margins for the test device based on target channels;
a selectable option to automatically produce debug information when low margins are detected as a result of the assessment of the electrical margin of the multi-lane high speed I/O link;
a selectable option for the test device to switch to using variable Inter Symbol Interference (ISI) source to find how much ISI causes lanes of the multi-lane high speed I/O link to fail;
a selectable option for the test device to test each lane individually to identify an amount of margin loss to due to cross-talk of the multi-lane high speed I/O link of the DUT;
a selectable option to turn off DFE in the receivers of the test device to assess margin with and without DFE and an amount of non-linear discontinuities in each channel associated with the multi-lane high speed I/O link;
a selectable option for characterization data for the test device that shows expected margins with reference receivers and typical channels and allows lower than expected margin to be flagged even when the lower than expected margin is consistent across all lanes of the multi-lane high speed I/O link of the DUT and of multiple DUTs;
a selectable option to select from multiple speeds of the multi-lane high speed I/O link on which the assessment of the electrical margin is performed;
a selectable option for the test device to infer when errors have happened at the receivers of the DUT based on traffic traveling in an opposite direction on the multi-lane high speed I/O link by the test device using protocol specific knowledge to enable the test device to perform margin tests on production lines without software on the DUT;
a selectable option to automatically capture Time-Domain Reflectometry readings (TDRs) of low margin channels detected as a result of the assessment of the electrical margin of the multi-lane high speed I/O link;
a selectable option to perform an automated connection to an oscilloscope to automatically capture digitized waveforms when low margins are detected as a result of the assessment of the electrical margin of the multi-lane high speed I/O link; or
a selectable option to configure the one or more of the user-selectable options for the DUT by configuring DUT silicon to implement the one or more of the user-selectable options.