Patent ID: 11922132
Assignee: SHANGHAI CAMBRICON INFORMATION TECHNOLOGY CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. An information processing method applied to a computation circuit, wherein the computation circuit comprises a communication circuit and an operation circuit, and the method comprises:
controlling, by the computation circuit, the communication circuit to obtain a frame image to be processed, wherein the frame image has a first painting style;
controlling, by the computation circuit, the operation circuit to obtain and call an operation instruction to perform painting style conversion on the frame image to obtain a target image, wherein
the target image has a second painting style, the second style is different from the first style, and the operation instruction is a preset instruction for painting style conversion of an image,
wherein the operation circuit includes a primary operation module and a plurality of secondary operation modules, wherein the primary operation module is interconnected with the plurality of secondary operation modules by an interconnection module, and when the operation instruction is a convolution operation instruction,
wherein the calling the operation instruction to perform painting style conversion on the frame image includes:
controlling, by the computation circuit, the secondary operation modules to implement a convolution operation of input data and a convolution kernel in a convolutional neural network algorithm, wherein the input data is the frame image and the convolutional neural network algorithm corresponds to the convolution operation instruction,
controlling, by the computation circuit, the interconnection module to implement data transfer between the primary operation module and the secondary operation modules, before a forward operation of a neural network fully connected layer starts, transferring, by the primary operation module, the input data to each secondary operation module through the interconnection module, and after the computation of the secondary operation modules is completed, splicing, by the interconnection module, output scalars of the respective secondary operation modules stage by stage to obtain an intermediate vector, and sending the intermediate vector back to the primary operation module,
controlling, by the computation circuit, the primary operation module to splice intermediate vectors corresponding of all input data into an intermediate result for subsequent operations, and
controlling, by the computation circuit, the primary operation module to add bias data to the intermediate result, and then performing an activation operation.