Patent ID: 11937429
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. A method of forming an integrated structure, comprising:
forming a vertically-stack comprising conductive levels alternating with dielectric levels;
forming vertically-stacked NAND memory cells along the conductive levels within a memory array region;
forming a silicon nitride material over the memory array region, the silicon nitride material being separated by an uppermost of the conductive levels by an intervening insulative material; the silicon nitride material comprising silicon, nitrogen, and one or more substances selected from the group consisting of carbon, oxygen, boron and phosphorus;
forming a first opening within the memory array region extending through the silicon nitride material over the memory array region and through at least some of the vertically-stacked conductive levels;
forming a channel material within the first opening; and
forming a second opening spaced from the first opening by regions of the stack, the second opening having sidewalls comprising the silicon nitride material, the insulative material, conductive material of the conductive levels and dielectric material of the dielectric levels, the second opening subdividing the memory array region into programmable blocks.