Patent ID: 11923341
Assignee: SUNRISE MEMORY CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 16:
17. The memory device of claim 16, wherein the three dimensional array of NOR memory strings are arranged in parallel in a first direction and stacked in a second direction each NOR memory string including a plurality of storage transistors sharing a common source layer and a common drain layer, with each layer extending along a third direction, the array of NOR memory strings further comprising:
(i) a plurality of local word line structures formed between adjacent stacks of NOR memory strings, and
(ii) a plurality of word lines formed above the three dimensional array and extending in the first direction, each word line being connected to a respective subset of the local word line structures, wherein each storage transistor is formed at the junction of each NOR memory string and each local word line structure, each storage transistor comprising (i) a channel region formed between the common source layer and the common drain layer, (ii) a gate dielectric layer and (iii) the local word line structure as a gate conductor.