Patent ID: 11942477
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A semiconductor device, comprising:
a semiconductor substrate;
a first active region on the semiconductor substrate;
a second active region on the semiconductor substrate;
an isolation region on the semiconductor substrate, the isolation region including a region between the first active region and the second active region;
a first gate structure overlapping the first active region and the isolation region;
a second gate structure overlapping the second active region and the isolation region; and
a gate separation region between the first gate structure and the second gate structure,
wherein:
the first gate structure includes a first gate dielectric layer and a first gate electrode on the first gate dielectric layer,
the second gate structure includes a second gate dielectric layer and a second gate electrode on the second gate dielectric layer,
each of the first and second gate structures extends in a first direction,
the first gate structure and the second gate structure are spaced apart from each other in the first direction,
the first gate structure, the gate separation region, and the second gate structure are sequentially arranged in the first direction,
a lower end of the gate separation region is at a lower level than an upper surface of the isolation region and a lower surface of each of the first gate structure and the second gate structure,
the gate separation region includes:
a gap-fill pattern including a first portion and a second portion; and
a buffer liner on side surfaces of the gap-fill pattern in the first direction,

at least a portion of the first portion has a dielectric constant that is higher than a dielectric constant of at least a portion of the second portion,
the gate separation region has a first region and a second region below the first region,
the first region of the gate separation region is between the first gate structure and the second gate structure,
the second region of the gate separation region is at a lower level than lower surfaces of the first and second gate structures,
a maximum width of the second region of the gate separation region is greater than a minimum width of the first region of the gate separation region in the first direction, and
a lower surface of the gate separation region has a rounded shape.