Patent ID: 11967367
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 17:
18. A storage device comprising:
a nonvolatile memory device including a memory cell array including a plurality of memory cells connected with a plurality of wordlines and a plurality of bitlines, wherein two or more of the memory cells are stacked in a direction perpendicular to a substrate; and
a memory controller connected with the nonvolatile memory device to control the nonvolatile memory device,
wherein, when a test command is provided from the memory controller, the nonvolatile memory device detects a difference between program speeds of memory cells connected with a selected wordline of the plurality of wordlines by performing at least one program operation on the memory cells connected with the selected wordline based on test data and sends a program status fail signal to the memory controller when the difference between the program speeds is greater than a threshold, and
wherein the memory controller sends the test command to the nonvolatile memory device based on a number of program/erase cycles of the nonvolatile memory device, a temperature profile of the nonvolatile memory device, or when a program fail occurs in the nonvolatile memory device.