Patent ID: 11895833
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 8:
9. A semiconductor memory device comprising:
a substrate including a cell region, a core region, and a boundary region between the cell region and the core region;
a boundary element isolation layer in the boundary region;
a first gate structure on the core region and at least a part of the boundary element isolation layer;
a core element isolation layer in the core region, the core element isolation layer being in a core element isolation recess and including first and second core liner layers and a core element isolation filling layer; and
a second gate structure on the core region and at least a part of the core element isolation layer,
wherein the first gate structure does not overlap the substrate of the cell region in a direction perpendicular to the top surface of the substrate,
wherein the first core boundary liner layer extends along a bottom surface of the element isolation recess and sidewalls of the core element isolation recess,
wherein the second core boundary liner layer on the first core boundary liner layer, and comprises silicon nitride,
wherein the core element isolation filling layer is disposed on the second boundary liner layer,
wherein the first gate structure includes a first high dielectric layer and a first gate insulating pattern below the first high dielectric layer with a top surface of the substrate being a base reference level,
wherein the second gate structure includes a second high dielectric layer and a second gate insulating pattern below the second high dielectric layer with the top surface of the substrate being the base reference level,
wherein the second gate insulating pattern does not overlap a top surface of the first core liner layer, and overlaps a topmost surface of the second core liner layer and a top surface of the substrate of the core region in the direction perpendicular to the top surface of the substrate,
wherein a portion of the first gate insulating pattern directly contacts the top surface of the substrate of the core region, and
wherein a portion of the second gate insulating pattern directly contacts the top surface of the substrate of the core region.