Patent ID: 11874768
Assignee: XILINX, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 7:
8. The circuit arrangement of claim 1, further comprising:
a system-on-chip including a processor subsystem and a programmable logic subsystem;
wherein:
the processor subsystem includes one or more instruction processors and an on-chip memory that is a storage circuit of the plurality of storage circuits;
the programmable logic subsystem includes programmable logic circuitry and programmable logic RAM that is a storage circuit of the plurality of storage circuits;
the translator circuit is configured to:
map a first range of addresses of the flash memory device to RAM addresses of the programmable logic RAM,
map a second range of addresses of the flash memory device to RAM addresses of the on-chip memory; and

the input-output circuit, emulator circuit, and translator circuit are implemented in programmable logic circuitry of the programmable logic subsystem.