Patent ID: 11953936
Assignee: SILICON LABORATORIES INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 13:
14. A method comprising:
during a reset mode in which a reset flow occurs, opening a switch of an integrated circuit coupled between an oscillator and a reset pin of the integrated circuit, the oscillator to provide a clock signal, wherein the opened switch is a default configuration of the switch, the reset pin external to a die of the integrated circuit;
after opening the switch, performing a pre-boot sequence of the integrated circuit, in response to release of a logic low voltage at the reset pin; and
during a non-reset mode following the reset mode, closing the switch to cause an attenuated version of the clock signal to be superimposed on a reset signal output at the reset pin while the reset signal is maintained above a logic high threshold level, to indicate functionality of the integrated circuit.