Patent ID: 11868877
Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G

Claim 4:
5. A driving method of an arithmetic device comprising the steps of:
selecting one of a first central processing unit (CPU) core and a second CPU core to enter a first state of executing arithmetic processing,
wherein the non-selected one of the first CPU core or the second CPU core enters into a first power gating state;
one of a first graphics processing unit (GPU) core and a second GPU core to enter a second state of executing arithmetic processing,
wherein the non-selected one of the first GPU core or the second GPU core enters into a second power gating state,
wherein the first CPU core and the second CPU core each comprises a first data retention circuit,
wherein the first GPU core comprises a second data retention circuit capable of retaining an analog value and reading out the analog value as digital data of two or more bits,
wherein the second GPU core comprises a third data retention circuit capable of retaining a digital value and reading out the digital value as digital data of one bit,
wherein the first to third data retention circuits each comprises a first transistor and a capacitor,
wherein the first transistor is electrically connected to the capacitor, and
wherein a channel formation region of the first transistor comprises an oxide semiconductor.