Patent ID: 11876648
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A circuit comprising:
a decision feedback equalizer (DFE) comprising:
an N-bit parallel input adapted to be coupled to a communication channel and configured to receive consecutive communication symbols transmitted at a rate of one symbol per cycle during a current clock cycle and each of previous (N−1) clock cycles, wherein N is an integer 5 or greater;
a first DFE path including:
a first input configured to receive a first one of the communication symbols;
a first adder having a first adder input coupled to the first input, second adder inputs, and first adder outputs;
first DFE filter circuitry having first DFE filter inputs and having first DFE filter outputs coupled to the second adder inputs, and responsive to the first DFE filter inputs, each first DFE filter input has one of three values, and the first DFE filter outputs correspond to members of a set of possible combinations of the first DFE filter inputs;
first slicer circuitry having first slicer inputs coupled to the first adder outputs, and having first slicer outputs; and
a first multiplexer having first multiplexer inputs coupled to the first slicer outputs, and a first multiplexer output, the first multiplexer configured to connect one of the first multiplexer inputs to the first multiplexer output; and

a second DFE path including:
a second input configured to receive a second communication symbol;
a second adder having a third adder input coupled to the second input, fourth adder inputs, and second adder outputs;
second DFE filter circuitry having second DFE filter inputs and having second DFE filter outputs coupled to the fourth adder inputs, and responsive to the second DFE filter inputs, the second DFE inputs have one of the three values, and the second DFE filter outputs correspond to a member of a set of possible combinations of the second DFE filter inputs;
second slicer circuitry having second slicer inputs coupled to the second adder outputs, and having second slicer outputs; and
a second multiplexer having second multiplexer inputs coupled to the second slicer outputs, a second multiplexer output, and the second multiplexer configured to connect one of the second multiplexer inputs to the second multiplexer output.