Patent ID: 11967380
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 2:
3. The semiconductor memory device according to claim 2, wherein
the first memory cell array includes:
a first memory cell coupled to the first word line;
a first selection transistor coupled to the first selection gate line; and
a first semiconductor extending in the first direction, and coupled to the first memory cell and the first selection transistor,

the second memory cell array includes:
a second memory cell coupled to the first word line;
a second selection transistor coupled to the first selection gate line; and
a second semiconductor extending in the first direction, and coupled to the second memory cell and the second selection transistor,

the third memory cell array includes:
a third memory cell coupled to the second word line;
a third selection transistor coupled to the second selection gate line; and
a third semiconductor extending in the first direction, and coupled to the third memory cell and the third selection transistor, and

the fourth memory cell array includes:
a fourth memory cell coupled to the second word line;
a fourth selection transistor coupled to the second selection gate line; and
a fourth semiconductor extending in the first direction, and coupled to the fourth memory cell and the fourth selection transistor.