Patent ID: 11893390
Assignee: GRAPHCORE LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A method of debugging a processor while the processor executes vertices of a software application, each vertex being assigned to a respective programming thread of the processor, the method comprising:
inspecting a vertex identifier of a first one of the vertices when the first one of the vertices is allocated for execution by a first one of the threads;
comparing the vertex identifier with a vertex break identifier held in debug hardware on the processor;
determining that there is a match between an executing instruction address of the first one of the threads and an instruction break address held in the debug hardware to identify an instruction exception;
setting an enable bit which in one state enables raising an instruction exception event in response to the vertex identifier matching the vertex break identifier; and
with the enable bit set in the one state, filtering the instruction exception based on the vertex identifier to prevent the instruction exception event from being raised in response to the vertex identifier not matching the vertex break identifier in the debug hardware, wherein setting the enable bit in another state enables raising the instruction exception event responsive to all vertex identifiers being considered a match.