Patent ID: 11876085
Assignee: QUALCOMM INCORPORATED
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. A method for fabricating a package, comprising:
providing a substrate comprising:
at least one dielectric layer;
a plurality of interconnects comprising a first interconnect and a second interconnect; and
at least one cavity located in the substrate;

placing a capacitor at least partially in the cavity of the substrate, the capacitor comprising a first terminal and a second terminal,
wherein the capacitor is placed such that a part of the capacitor directly touches the at least one dielectric layer of the substrate,
wherein the first terminal includes a first top surface, a first bottom surface and a first side surface, and
wherein the second terminal includes a second top surface, a second bottom surface and a second side surface;

coupling a first solder interconnect to the first side surface of the first terminal and a first side wall of the first interconnect, wherein the first side surface of the first terminal faces the first side wall of the first interconnect;
coupling a second solder interconnect to the second side surface of the second terminal and a second side wall of the second interconnect, wherein the second side surface of the second terminal faces the second side wall of the second interconnect; and
coupling an integrated device to a first surface of the substrate, wherein the integrated device vertically overlaps with at least a portion of the capacitor.