Patent ID: 11923259
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A method of forming a package structure, comprising:
electrically bonding a first semiconductor package and a second semiconductor package to a package substrate;
forming an underfill material to fill a first space between the first semiconductor package and the package substrate and a second space between the second semiconductor package and the package substrate;
disposing a gap filling structure in a first gap between the first semiconductor package and the second semiconductor package, wherein the gap filling structure is in contact with the underfill material;
forming a thermal conductive layer on the first semiconductor package and the second semiconductor package; and
disposing a heat dissipation structure on the package substrate and the first and second semiconductor packages, wherein the heat dissipation structure is attached to the first and second semiconductor packages through the thermal conductive layer, and wherein a top surface of the gap filling structure is lower than top surfaces of the first semiconductor package and the second semiconductor package, and a second gap is existed between the top surface of the gap filling structure and the thermal conductive layer.