Patent ID: 11968819
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 15:
16. An integrated circuit (IC) structure, comprising:
a memory cell that includes a first p-type fin, a first n-type fin, a second n-type fin, and a second p-type fin disposed lengthwise along a first direction and spaced from each other along a second direction substantially perpendicular to the first direction,
wherein the first p-type fins includes a first plurality of vertically stacked channel layers having a width W1 measured along the second direction,
wherein the first n-type fin includes a second plurality of vertically stacked channel layers having a width W2 measured along the second direction, the width W2 being different than the width W1, and
wherein at least one of the first p-type fin, the first n-type fin, the second n-type fin, and the second p-type fin is continuous across a boundary of the memory cell;

a standard logic cell that includes a third n-type fin and a third p-type fin oriented lengthwise along the first direction and spaced from each other along the second direction,
wherein the third n-type fin includes a third plurality of vertically stacked channel layers having a width W3 measured along the second direction, and
wherein the third p-type fin includes a fourth plurality of vertically stacked channel layers having a width W4 measured along the second direction, the width W3 being different than or equal to the width W4.