Patent ID: 11869624
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. The memory of claim 11, wherein the drain of the first PMOS transistor and the drain of the first NMOS transistor are connected to a first node, and the drain of the second PMOS transistor and the drain of the second NMOS transistor are connected to a second node; and the sense amplifier further comprises:
a first switch, a first end of the first switch being connected to the first node, and a second end of the first switch being connected to the gate of the first NMOS transistor;
a second switch, a first end of the second switch being connected to the second node, and a second end of the second switch being connected to the gate of the second NMOS transistor; and
a third switch, a first end of the third switch being connected to a gate of the first PMOS transistor, and a second end of the third switch being connected to a gate of the second PMOS transistor,
wherein in the offset elimination stage of the sense amplifier, the first switch, the second switch and the third switch are all in a closed state.