Patent ID: 11893942
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. The gate on array circuit of claim 14, wherein the cascaded series is associated with four clock-signal lines; wherein, the gate on array unit circuit in (N−2)-th stage is configured to receive a first clock signal from a first one of the four clock-signal lines, a second clock signal from a second one of the four clock-signal lines, and a third clock signal from a fourth one of the four clock-signal lines;
the gate on array unit circuit in (N−1)-th stage is configured to receive a first clock signal from the second one of the four clock-signal lines, a second clock signal from a third one of the four clock-signal lines, and a third clock signal from the first one of the four clock-signal lines;
the gate on array unit circuit in N-th stage is configured to receive a first clock signal from the third one of the four clock-signal lines, a second clock signal from the fourth one of the four clock-signal lines, and a third clock signal from the second one of the four clock-signal lines; and
the gate on array unit circuit in (N+1)-th stage is configured to receive a first clock signal from the fourth one of the four clock-signal lines, a second clock signal from the first one of the four clock-signal lines, and a third clock signal from the third one of the four clock-signal lines.