Patent ID: 11860789
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A cache purge simulation system comprising:
a device under test comprising a cache skip switch circuit, the cache skip switch circuit comprising:
a configurable start address register comprising a start address that indicates a beginning storage location of a physical partition of an associated cache;
a configurable stop address register comprising a stop address that indicates a ending storage location of the physical partition of the associated cache;
a purge address register comprising a purge address of a storage location within the associated cache that is purged by the device under test; and
a multiplexer that outputs the purge address to the purge address register, wherein only the physical partition of the associated cache is purged upon receipt of a cache purge instruction from a verification system, and wherein the physical partition is smaller than the associated cache.