Patent ID: 11908507
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 2:
3. The semiconductor memory device according to claim 2, wherein the command and address generator is configured to decode the command and further generate a refresh command,
wherein the semiconductor memory device further comprises:
a hammer refresh address generator configured to receive the row address in response to the active command, to detect a corresponding row address as an aggressor row address in response to the same row address being applied at least a specific number of times, and to generate at least one victim row address adjacent to the aggressor row address as a hammer refresh row address together with a hammer refresh command;
a normal refresh address generator configured to a normal refresh row address in response to the refresh command;
a selection circuit configured to select the hammer refresh row address in response to the hammer refresh command or select the normal refresh row address in response to the refresh command, to generate a refresh row address; and
a row decoder configured to decode the row address in response to the active command and decode the refresh row address in response to the refresh command or the hammer refresh command, and to generate a plurality of main word line selection signals and a plurality of selection signals.