Patent ID: 11941248
Assignee: XILINX, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 18:
19. The circuit arrangement of claim 11, wherein the write compression circuit is configured to input bit vectors associated with the words, and each bit vector indicates ones of the data elements that are non-zero in the associated word of data elements, and the circuit arrangement further comprising:
a second RAM, wherein the write compression circuit is configured to write each bit vector in the second RAM at an address associated with the associated word of data elements and uncompressed block; and
a read decompression circuit configured to:
input uncompressed read addresses;
read bit vectors associated with the uncompressed read addresses from the second RAM;
determine compressed address ranges from the uncompressed read addresses;
determine compressed read addresses from the determined compressed address ranges and stored data that indicate offsets in the determined compressed address ranges; and
unpack data elements from packed words in the first RAM into uncompressed words associated with the uncompressed read addresses by performing operations including:
maintaining for each block, respective data that indicate a last-read compressed read address and a next-data-element position from which to extract a data element from a last-read packed word at the last-read compressed read address,
reading from the first RAM, a packed word at a compressed read address following the last-read compressed read address, in response to the associated bit vector indicating non-zero data elements of the uncompressed read address are greater in number than remaining data elements in the last-read packed word as indicated by the next-data-element position,
extracting from a packed word buffer, a number of non-zero data elements indicated by bit vector associated with the uncompressed read address from which the compressed read address was determined,
generating in a register, an uncompressed word having at data element positions indicated by the associated bit vector, zero-value data elements and values of the one or more non-zero data elements, and
outputting the uncompressed word.