Patent ID: 11941394
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. A computer system comprising:
an interconnect;
a processor coupled with the interconnect, the processor to receive an instruction, the instruction to indicate a source packed data operand that is to have a plurality of source data elements, to indicate a source packed indices operand that is to have a plurality of indices, and to have at least one field to specify a destination packed data register, wherein each of the indices is to correspond to a different one of the source data elements in a same relative position, the processor to perform the instruction to store a result packed data operand in the destination packed data register, the result packed data operand to include a plurality of result data elements that are each to have a value of one of the source data elements whose corresponding index specifies a data element position of the result data element in the result packed data operand, and the result packed data operand to have a replacement value in a given result data element when none of the indices indicate a data element position of the given result data element, wherein the replacement value is a zero value; and
a dynamic random access memory (DRAM) coupled with the interconnect.