Patent ID: 11899741
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 26:
27. A processor-implemented operation method of a memory device, the method comprising:
receiving at least a portion of data from among input data and filter data from a memory in response to a read command;
transforming, using one or more processor embedded inside the memory device, at least a first portion of the input data using a first transforming matrix and transforming, using the one or more processor, at least a second portion of the filter data using a second transforming matrix, respectively during a clock cycle corresponding to the read command, the first transforming matrix and the second transforming matrix being respectively based on a parameter of a convolution operation, and outputting a corresponding transformation result as transformed data, using a third transforming matrix; and
reduce information loss associated with the outputting by adjusting relationship between the second transforming matrix and the third transforming matrix.