Patent ID: 11928468
Assignee: ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITY
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 2:
3. The system of claim 1, wherein the step of generating a random schedule that schedules each node of the data flow graph to a random modulo timeslot further comprises:
schedule a node indicative of a current schedule operation of the plurality of nodes of the data flow graph at a randomly selected modulo timeslot between the lower bound modulo timeslot and the upper bound modulo timeslot;
consecutively displace one or more nodes that have resource conflicts with the node;
update the lower bound modulo timeslot and the upper bound modulo timeslot for the node based on the current schedule operation;
displace one or more previously-scheduled nodes having dependence conflicts with the node; and
add one or more displaced nodes to a queue of unscheduled nodes.