Patent ID: 11901027
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory system comprising:
a main controller configured to transmit main data having N bits through a main channel, where N is a positive integer;
memory devices configured to store sub-data constituting the main data and transmit the sub-data through sub-channels; and
a sub-controller configured to communicate with the main controller through the main channel and communicate with the memory devices through the sub-channels,
wherein the sub-controller is further configured to:
generate the sub-data each having n bits where n is a positive integer less than N, by dividing the main data,
generate sub-data strobe clocks with a lower frequency than a main data strobe clock synchronized with the main data, and
transmit/receive the sub-data to/from the memory devices in synchronization with the sub-data strobe clocks.