Patent ID: 11928578
Assignee: POSTECH RESEARCH AND BUSINESS DEVELOPMENT FOUNDATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A method of processing of a sparsity-aware neural processing unit, comprising:
receiving a plurality of input activations (IAs);
obtaining a plurality of weights having a non-zero value in each weight output channel;
storing the plurality of weights and the plurality of IAs in a memory, and obtaining input channel indices comprising a memory address location in which the plurality of weights and the plurality of IAs are stored; and
arranging the plurality of weights of each weight output channel according to a row size of an index matching unit (IMU) and matching the plurality of IAs to the plurality of weights in the IMU storing the input channel indices,
wherein the IMU comprises a comparator array and a buffer memory,
wherein the buffer memory comprises a weight buffer memory and an input activation (IA) buffer memory,
wherein, in a boundary of the comparator array, the IA buffer memory storing IA input channel indices is arranged in a columnar direction and the weight buffer memory storing weight input channel indices is arranged in a row direction so as to match the plurality of weights and the plurality of IAs, and
wherein, in the weight buffer memory, the plurality of weights of each weight output channel are arranged in ascending order, and the plurality of weights are arranged in a next weight output channel when a number of the plurality of weights exceeds an input channel size of a respective weight output channel.