Patent ID: 11886331
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. An apparatus, comprising:
a memory device comprising a plurality of access rows; and
a processing device coupled to the memory device, wherein the processing device is configured to:
write first data to a first set of contiguous partitions in a first access row among the plurality of access rows;
write a first portion of second data to a second set of contiguous partitions in the first access row among the plurality of access rows, wherein the first set of contiguous partitions in the first access row and the second set of contiguous partitions in the first access row are separated by a null partition; and
write a second portion of the second data to a first set of contiguous partitions in a second access row among the plurality of access rows.