Patent ID: 11923864
Assignee: SHAOXING YUANFANG SEMICONDUCTOR CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A system comprising:
a line card coupled to receive a data packet, said line card to re-time said data packet with reference to a selected clock, and to transmit a re-timed packet; and
a first timing card to generate a first clock,
wherein said line card comprises a phase-locked loop (PLL) coupled to receive said first clock, said PLL to generate an output clock based on said first clock as said selected clock, said output clock locked to said input clock at a frequency which is product of a first divisor and a frequency of said input clock in a normal mode of operation and to switch to a different frequency thereafter, wherein said different frequency is product of another divisor and said frequency of said input clock, wherein said PLL comprises:
a first phase detector coupled to receive said first clock on an input path and a feedback clock on a feedback path, said phase detector to generate an error signal representing a phase difference between said first input clock and said feedback clock;
a first low-pass filter with a first passband to generate a filtered error signal by filtering said error signal;
a first oscillator coupled to generate said output clock from said filtered error signal, wherein a frequency of said output clock is determined by a strength of said filtered error signal;
a first feedback divider to divide said output clock by said first divisor of a first value in said normal mode, and by said a second value corresponding to said different frequency in thereafter to generate said feedback clock,
wherein said first phase detector, said first low-pass filter, said first oscillator and said first feedback divider together operate as a first PLL having a first bandwidth,
wherein said first oscillator is implemented as a second PLL with a second bandwidth higher in magnitude compared to said first bandwidth, wherein said filtered error signal is provided as input signal to said second PLL and said second PLL provides said output clock,
wherein said first bandwidth is designed to cause said PLL to settle to said different frequency in a first duration upon a corresponding configuration change of only said first PLL; and
a control unit to control operation of said first PLL and said second PLL, wherein to switch to said different frequency of said output clock, said control unit changes, within an interval less than said first duration, a configuration of each of said first PLL and said second PLL to generate said output clock at said different frequency,

wherein changing said configuration of said first PLL comprises operating said first feedback divider based on said another divisor and/or changing said frequency of said input clock to effectively provide said output clock with said different frequency,
wherein said output clock changes to operate at said different frequency in a second duration determined by said interval and the higher second bandwidth of said second PLL.