Patent ID: 11948659
Assignee: REEXEN TECHNOLOGY CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G

Claim 4:
5. A bit-width reconfigurable mixed-signal in-memory computing module, comprising:
a multiply-accumulate (MAC) array, configured for performing MAC operations and comprising in-memory mixed-signal computing sub-cells configured for 1-bit multiplication, the in-memory mixed-signal computing sub-cell comprising a conventional six-transistor (6T) static random-access memory (SRAM) cell, a complementary transmission gate, a first NMOS transistor and a computing capacitor, wherein:
the conventional 6T SRAM cell consists of MOS transistors M1, M2, M3, M4, M5, M6, in which a complementary metal-oxide-semiconductor (CMOS) inverter consisting of the MOS transistors M1, M2 is cross-coupled to a CMOS inverter consisting of the MOS transistors M3, M4, the cross-coupled two CMOS inverters store a 1-bit filter parameter, and the MOS transistors M5, M6 serve as control switches for bit lines for reading and writing the filter parameter,
the CMOS inverter consisting of the MOS transistors M1, M2 in the conventional 6T SRAM cell comprises an output connected to an input of a complementary transmission gate, the complementary transmission gate comprising an output connected to a drain of the first NMOS transistor,
the first NMOS transistor has a source that is grounded, and a drain connected to a bottom plate of the computing capacitor,
the complementary transmission gate comprises an NMOS transistor having a gate connected to an input signal, and a PMOS transistor having agate connected to a complementary input signal at a same voltage level during a time-multiplexed activation of the sub-cell as a signal input to a gate of the first NMOS transistor,
a multiplication result of the input signal and the filter parameter is stored as a voltage on the bottom plate of the computing capacitor, and a plurality of said sub-cells are arranged to form a computing cell, the first NMOS transistor and the computing capacitor are shared among all the computing sub-cells in the computing cell
wherein the MAC array comprises a plurality of computing cells, in each of which the outputs of the complementary transmission gates of all the sub-cells are connected to the bottom plate of the shared computing capacitor, wherein top plates of the computing capacitors in all the computing cells of each column are connected to a respective accumulation bus, and wherein a voltage on each accumulation bus corresponds to an accumulated sum of multiplication operation results of the respective column of the MAC array and
wherein column-wise accumulation results of multiplication results in the MAC array are represented as analog voltages;

a filter/ifmap block, configured for providing filter parameters or activations from computation in a previous layer, which are written into and stored in the MAC array;
an ifmap/filter block, configured for providing an input to the MAC array, which is subject to MAC operations with the filter parameters or the activations from computation in the previous layer;
an analog-to-digital conversion (ADC) block, configured for converting the analog voltages from the MAC array to digital representations; and
a digital processing block, configured for performing at least multi-bit fusion, biasing, scaling or nonlinearity on an output of the ADC block, and wherein outputting results in a form of partial sums or activations are directly usable as an input to the next network layer.