Patent ID: 11961909
Assignee: RENESAS ELECTRONICS CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor device including a MISFET, the semiconductor device comprising:
a semiconductor substrate having a main surface, an element isolation region embedded in a trench of the main surface, and an active region surrounded by the element isolation region;
a well region of a first conductivity type, the well region being formed in the active region of the semiconductor substrate;
a gate electrode of the MISFET, the gate electrode being formed on the well region of the semiconductor substrate via a gate dielectric film and extending in a first direction; and
a source region of the MISFET and a drain region of the MISFET, each of the source region and the drain region being formed in the well region, having a second conductivity type opposite the first conductivity type and spaced from each other in a second direction perpendicular to the first direction,
wherein the source region includes:
a first semiconductor region; and
a first high concentration region adjacent to the first semiconductor region and having an impurity concentration higher than that of the first semiconductor region,

wherein the drain region includes:
a second semiconductor region; and
a second high concentration region adjacent to the second semiconductor region and having an impurity concentration higher than that of the second semiconductor region,

wherein the first semiconductor region and the second semiconductor region are spaced from each other in the second direction via a region directly below the gate electrode,
wherein a first region of the first conductivity type is formed in the well region and is in contact with the first semiconductor region and the element isolation region,
wherein a second region of the first conductivity type is formed in the well region and is in contact with the first semiconductor region and the element isolation region,
wherein the first region and the second region are spaced apart from each other in the first direction,
wherein a third region of the first conductivity type is formed in the well region and is in contact with the second semiconductor region and the element isolation region,
wherein a fourth region of the first conductivity type is formed in the well region and is in contact with the second semiconductor region and the element isolation region,
wherein the third region and the fourth region are spaced apart from each other in the first direction,
wherein the first region and the third region are spaced apart from each other in the second direction, and each has an impurity concentration higher than that of the well region,
wherein the second region and the fourth region are spaced from each other in the second direction, and each has an impurity concentration higher than that of the well region, and
wherein at least a portion of the first region and at least a portion of the second region are located under the gate electrode.