Patent ID: 11930590
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A method, comprising:
forming recesses, in a planar die mount surface of leads of a semiconductor package including a package substrate, in locations where solder joints will be formed, wherein the package substrate is a metal leadframe;
flip chip mounting a semiconductor device die to the package substrate using solder bumps on post connects, the post connects having a proximate end mounted on bond pads on an active surface of the semiconductor device die, and having a distal end extending away from the semiconductor device die, the solder bumps on the distal ends of the post connects;
forming solder joints between the solder bumps on the post connects and the package substrate within the recesses by a thermal reflow process to melt the solder bumps; and
covering the semiconductor device die, the solder joints, the post connects and a portion of the package substrate with mold compound.