Patent ID: 11966608
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. A memory controller for controlling a memory device comprising a plurality of blocks, the memory controller comprising:
a processor;
a working memory storing a flash translation layer (FTL) executed by the processor; and
a memory interface configured to communicate with the memory device,
wherein during a background operation of the memory device with respect to a plurality of pieces of user data and parity data corresponding to the plurality of pieces of user data, the plurality of pieces of user data and the parity data being stored in the memory device and constituting a redundant array of inexpensive disks (RAID), the memory interface is configured responsive to the processor to output a first address so that the plurality of pieces of user data are copied to a normal region of the plurality of blocks, and output a second address so that the parity data is copied to a deterioration region of the plurality of blocks.