Patent ID: 11923041
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A device, comprising:
a memory array having a plurality of bit cells arranged in rows and columns;
a plurality of word lines, each word line connected to a respective row of bit cells;
a word line decoder coupled with the plurality of word lines; and
a control signal generator coupled with a modulation circuit and the word line decoder, wherein the control signal generator is configured to produce a first control signal to the word line decoder for generating word line signals, and the control signal generator is configured to produce a second control signal to the modulation circuit in reference with a tracking wiring, a rising edge of the second control signal occurs before rising edges of the word line signals, a falling edge of the second control signal occurs after falling edges of the word line signals,
wherein the second control signal is maintained at a voltage level from a moment of a rising edge of a word line signal of the word line signals until a moment of a falling edge of the word line signal.