Patent ID: 11899686
Assignee: JPMORGAN CHASE BANK, N.A.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A computing device configured to implement an execution of a method for facilitating usage and storage of bi-temporal data, the computing device comprising:
a processor;
a memory; and
a communication interface coupled to each of the processor and the memory,
wherein the processor is configured to:
receive, via an application programming interface, at least one update request, the at least one update request relating to an update of at least one data object with a new data object;
identify at least one builder pattern that corresponds to the at least one data object based on a data type of the at least one data object,
wherein the at least one builder pattern relates to a design pattern that separates construction of the at least one data object from representation of the at least one data object;

automatically generate, by using the identified at least one builder pattern, at least one delta object based on the at least one request, the at least one delta object relating to a difference between the at least one data object and the new data object;
associate the at least one delta object with at least one axial value, the at least one axial value including a reported time and an effective time; and
persist the at least one delta object and the corresponding association as an event that represents the difference between the at least one data object and the new data object.