Patent ID: 11908535
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. A memory controller connected to a memory device comprising a plurality of normal word lines and at least one spare word line, wherein the memory controller is configured to: transmit a command to the memory device, detect at least one of the normal word lines as a weak word line, when an operation performed in response to the command fails, set memory cells connected to the weak word line to a single-level cell (SLC) operation mode, and set memory cells connected to the at least one spare word line to a multi-level cell (MLC) operation mode, wherein memory cells connected to the plurality of normal word lines are set to a third operation mode configured to write (n+m)-bit data, and wherein the first operation mode is configured to write n-bit data to the memory cells connected to the weak word line, the second operation mode is configured to write m-bit data to the memory cells connected to the at least one spare word line, and each of n and m is a natural number greater than or equal to 1 and m is greater than n.