Patent ID: 11910597
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. An integrated assembly, comprising:
a lower carrier-sink-structure;
first comparative digit lines over the lower carrier-sink-structure;
first source/drain regions over the first comparative digit lines and being coupled with the first comparative digit lines;
vertically-extending first pillars over the first source/drain regions; each of the first pillars comprising a first transistor body region and a second source/drain region;
capacitors coupled with the second source/drain regions;
vertically-extending second pillars over the capacitors; each of the second pillars comprising a third source/drain region and a second transistor body region over the third source/drain region; the third source/drain regions being coupled with capacitor nodes;
fourth source/drain regions over the second transistor body regions;
second comparative digit lines over the fourth source/drain regions and being coupled with the fourth source/drain regions; individuals of the first comparative digit lines being paired with individuals of the second comparative digit lines in a plurality of first/second comparative digit line sets; the first comparative digit lines and second comparative digit lines of each of the first/second comparative digit line sets extending to a sense amplifier configured to compare electrical properties of the first and second comparative digit lines within the first/second comparative digit line set;
an upper carrier-sink-structure over the second digit lines;
first extensions extending from the lower carrier-sink-structure to the first transistor body regions; the first extensions being configured to drain excess carriers from the first transistor body regions to the lower carrier-sink-structure;
second extensions extending from the upper carrier-sink-structure to the second transistor body regions; the second extensions being configured to drain excess carriers from the second transistor body regions to the upper carrier-sink-structure; and
gates having components adjacent the first and second transistor body regions.