Patent ID: 11863346
Assignee: APPLE INC.
Field: Digital communication (Electrical engineering)
Classification: CPC G  H | IPC H

Claim 15:
16. An electronic device comprising:
a first integrated circuit, comprising:
an interface circuit configured to:
receive timing packets over a multi-drop bus, and
determine delays in receiving the timing packets due to unsuccessful arbitration for transmitting the timing packets over the multi-drop bus; and
a synchronization generator circuit configured to generate one or more timing signals according to the received timing packets and the determined delays; and

a second integrated circuit communicating with the first integrated circuit over the multi-drop bus, the second integrated circuit configured to send the timing packets to the first integrated circuit, the timing packets indicating times at which periodic events occur at the second integrated circuit, the one or more timing signals indicating when one or more periodic events are expected to occur at the second integrated circuit.