Patent ID: 11908419
Assignee: LG DISPLAY CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. A display device comprising:
a display panel; and
a gate driver embedded in the display panel,
wherein the gate driver comprises:
a plurality of stages configured to individually drive a plurality of gate lines by a combination of a plurality of group signals, a plurality of block signals, and a plurality of clock signals,
wherein each of the plurality of stages driven independently includes:
an output buffer including a pull-up transistor configured to generate and output a gate-on level of a scan signal under control of a first node, and a pull-down transistor configured to generate and output a gate-off level of the scan signal under control of a second node;
a first controller configured to control the first node by the combination of the group signal supplied through a group line among the plurality of group signals, the block signal supplied through a block line among the plurality of block signals, and the clock signal supplied through a clock line among the plurality of clock signals; and
a second controller configured to control the second node to be opposite to an operation of the first node by the combination of the group signal, the block signal, and the clock signal,
wherein the first controller includes:
a first transistor controlled by the block signal and configured to output the clock signal;
a second transistor controlled by the group signal and configured to connect the first transistor to the first node; and
a third transistor controlled by a third gate-on voltage supplied through a third power line, and configured to connect a fifth power line supplied with a second gate-off voltage to the first node,
wherein:
the first controller outputs the clock signal to the first node through the first and second transistors when the block signal and the group signal are in the gate-on level, and
the first controller outputs the second gate-off voltage to the first node through the third transistor when at least one of the clock signal, the block signal, and the group signal is in the gate-off level.