Patent ID: 11894073
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 0:
1. A memory apparatus, comprising:
memory cells connected to one of a plurality of word lines including at least one edge word line and a plurality of other data word lines and arranged in strings and configured to retain a threshold voltage corresponding to one of a plurality of data states, wherein the strings are arranged in rows including full circle rows and semi-circle rows; and
a control means coupled to the plurality of word lines and the strings and configured to:
identify the at least one edge word line, and
periodically apply a program voltage to the at least one edge word line to reprogram the memory cells associated with the at least one edge word line without erasing the memory cells associated with the at least one edge word line, wherein periodically applying the program voltage includes applying an inhibiting bit line voltage to ones of a plurality of bit lines coupled to the strings of the full circle rows while reprogramming the memory cells associated with the at least one edge word line to inhibit reprogramming of the memory cells in the strings associated with the full circle rows.