Patent ID: 11923304
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An integrated circuit, comprising:
a conductive interconnect disposed on a dielectric over a substrate;
an interfacial layer arranged along an upper surface of the conductive interconnect;
a liner arranged along a lower surface of the conductive interconnect and vertically below a bottommost surface of the interfacial layer, wherein the liner and the interfacial layer completely surround the conductive interconnect;
a middle layer physically contacting the interfacial layer and having a bottommost surface over the dielectric, wherein the middle layer has a topmost surface that is directly over the conductive interconnect; and
wherein the bottommost surface of the interfacial layer and the bottommost surface of the middle layer are both above a top of the conductive interconnect.