Patent ID: 11900985
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 18:
19. A memory module comprising:
a memory device;
a data interface to receive write data for writing to the memory device in a write operation or read data read from the memory device in a read operation;
a command/address interface to receive an input data signal from a source device comprising command and address data associated with the read and write operations of the memory device;
a clock interface to receive an input clock from the source device, the input clock providing timing information associated with the input data signal;
a buffer circuit comprising:
an internal clock generator circuit to receive the input clock and an internal clock control specifying a first selected reference edge of the input clock, and to generate an internal clock signal locked to the first selected reference edge of the input clock;
an output clock generator circuit to receive the input clock and an output clock control signal specifying a second selected reference edge of the input clock, and to generate an output clock locked to the second selected reference edge of the input clock, wherein the output clock has a predefined phase relationship to the input clock that is independent of the first and the second selected reference edges;

a sampling circuit to receive the input data signal and to sample the input data signal based on the internal clock to generate an output data signal; and an output interface to output the output data signal and to output the output clock to the memory device to carry out the read operation or the write operation, wherein the output clock provides timing information associated with the output data signal.