Patent ID: 11862625
Assignee: NXP USA, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 19:
20. The method of claim 19, where forming the standard cell comprises:
obtaining a semiconductor substrate;
selectively implanting a single row standard cell area of the semiconductor substrate with the n-well and p-well regions;
selectively forming a plurality of semiconductor fins on the semiconductor substrate extending up from the n-well and p-well regions, where the plurality of semiconductor fins comprises:
P+ doped semiconductor fins formed over the n-well region in one or more defined P+ active areas of the dummy FinFET diode layout area,
N+ doped semiconductor fins formed over the n-well region in the tap area,
N+ doped semiconductor fins formed over the p-well region in one or more defined N+ active areas of the dummy FinFET diode layout area, and
P+ doped semiconductor fins formed over the p-well region in the tap area;

selectively forming one or more FinFET gate electrodes aligned perpendicularly to the plurality of semiconductor fins to define the first p-FinFET and first n-FinFET in the dummy FinFET diode layout area; and
selectively forming one or more metal interconnect layers over the substrate to connect the first p-FinFET as the first diode, to connect the first n-FinFET as the second diode, to tie the N+ doped semiconductor fins formed over the n-well region to the first supply voltage, and to tie the P+ doped semiconductor fins formed over the p-well region to the second supply voltage.