Patent ID: 11925037
Assignee: nan
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. The method of claim 13, wherein:
forming the stack structure comprises:
forming the tiers of a lower portion of the stack structure; and
forming the tiers of the upper portion of the stack structure above the lower portion; and

forming the pillar structures comprises, for each of the pillar structures:
after forming the tiers of the lower portion of the stack structure and before forming the tiers of the upper portion of the stack structure, forming a lower pillar opening through the lower portion of the stack structure;
forming materials of the pillar structure in the lower pillar opening to form a lower pillar portion of the pillar structure, the material comprising a first region of the at least one channel material;
after forming the tiers of the upper portion of the stack structure above the lower pillar portion of the pillar structure, forming an upper pillar opening through the upper portion of the stack structure to expose a surface of the lower pillar portion of the pillar structure; and
forming a second region of the at least one channel material in the upper pillar opening on the surface of the lower pillar portion,
wherein a diameter of the lower pillar opening is less than a diameter of the upper pillar opening.