Patent ID: 11966977
Assignee: CHICAGO MERCANTILE EXCHANGE INC.
Field: IT methods for management (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. Non-transitory machine-readable media including instructions stored thereon, the instructions configured to, when executed, cause a machine to:
generate a self-referencing risk (SRR) data structure in a memory storage via the instructions further configured to cause the processor to:
parse independent operations into a multiple-core processing scheme including operating multiple hardware processing cores in parallel, the multiple hardware processing cores include cores disposed on multiple separate hardware processors;
determine a margin requirement value based on a margin model, the margin model including a scenario model that is extensible to newly determined risk factors;
populate, using the multiple-core processing scheme, a residual vector of the SRR data structure by removing, for each of multiple participant units, the margin requirement value from an exposure value to determine a corresponding residual vector entry for the participant unit;
determine, based on the residual vector, at least a predetermined number of top-magnitude residual vector entries;
sum at least the predetermined number of top-magnitude residual vector entries to simulate an event corresponding to the predetermined number of jump-to-defaults occurring to generate a total event value;
populate, using the multiple-core processing scheme, a weight vector of the SRR data structure by determining, for each of the multiple participant units, a corresponding ratio value by dividing the corresponding residual vector entry for the participant unit by the total event value; and
populate, using the multiple-core processing scheme, a contribution vector of the SRR data structure by multiplying, for each of multiple participant units, the corresponding ratio value for that participant unit to a sum over an entirety of the residual vector, wherein:

the computation for each entry within any one of the vectors is independent of any computation for any other entry in that vector.