Patent ID: 11955155
Assignee: UIF (UNIVERSITY INDUSTRY FOUNDATION), YONSEI UNIVERSITY
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 12:
13. A latch configured to store data in a nonvolatile manner, comprising:
a first inverter;
a second inverter cross-coupled to the first inverter;
a nonvolatile memory circuit including a pull-up transistor, a pull-down transistor, and a ferroelectric field effect transistor of which a first electrode and a second electrode are respectively connected to the pull-up transistor and the pull-down transistor;
a third inverter configured to invert and output an output of the first inverter;
a first transmission gate connected to an input node of the first inverter; and, a second transmission gate connected to an output node of the second inverter and the input node of the first inverter, wherein when the ferroelectric field effect transistor is programmed to a low resistance state, an equivalent resistance of a current path including the pull-down transistor is smaller than an equivalent resistance of a current path including the pull-up transistor.