Patent ID: 11942162
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A memory device comprising:
a memory cell block connected between a common source line and a bit line and including a plurality of NAND strings, wherein the plurality of NAND strings includes a string selection transistor, a plurality of memory cells, and a ground selection transistor;
a voltage generating circuit generating a high voltage signal, a shielding signal, and a logic signal for the memory cell block;
a row decoder connected to the memory cell block through a word line;
a page buffer connected to the memory cell block through the bit line;
a peripheral circuit including a level shifter and a control logic circuit controlling the voltage generating circuit, the row decoder, and the page buffer;
a first wiring providing the high voltage signal to the memory cell block;
a second wiring providing the logic signal to the memory cell block; and
a third wiring providing the shielding signal to the memory cell block,
wherein the level shifter receives a first voltage including a negative voltage level, a second voltage including a positive voltage level, and a third voltage including a second positive voltage level different from the positive voltage level of the second voltage, applies the first voltage to the third wiring in response to a control signal including a first voltage level in a test mode, and applies the second voltage to the third wiring, in response to a control signal including a second voltage level in a user mode.