Patent ID: 11930645
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Measurement (Instruments)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A semiconductor structure, comprising:
a substrate;
a transistor region, comprising a gate over the substrate, and a first doped region and a second doped region at least partially in the substrate;
a first contact plug and a second contact plug over the transistor region, wherein the first contact plug and the second contact plug comprise a coplanar upper surface;
a first metal via and a magnetic tunneling junction (MTJ) structure over the first contact plug and the second contact plug, respectively, the first metal via is leveled with the MTJ structure; and
a metal interconnect over the first metal via and the MTJ structure, and the metal interconnect comprises at least two second metal vias in contact with an upper surface of the first metal via and an upper surface of the MTJ structure, respectively.