Patent ID: 11948917
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 18:
19. A packaged system, comprising:
a printed circuit board (PCB);
a semiconductor package coupled to the PCB via a plurality of interconnects, the semiconductor package comprising:
a substrate, the substrate having a first outermost sidewall laterally opposite a second outermost sidewall;
a first die on the substrate, the first die electrically coupled to the substrate, and the first die having a first sidewall laterally opposite a second sidewall;
a first molding compound encapsulating the first die on the substrate, the first molding compound in contact with the first sidewall and the second sidewall of the first die, and the first molding compound having a first outermost sidewall and a second outermost sidewall, the second outermost sidewall laterally opposite the first outermost sidewall, and the first outermost sidewall of the first molding compound in vertical alignment with the first outermost sidewall of the substrate;
a second die on the first molding compound, the second die having a portion electrically coupled to the substrate, the portion of the second die extending laterally beyond the second outermost sidewall of the first molding compound; and
a second molding compound encapsulating the second die and at least one portion of the first molding compound.