Patent ID: 11907005
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G  H

Claim 3:
4. The multi-core system of claim 1, wherein the clock management circuit includes:
a synchronization circuit configured to generate a clock gating signal that is activated to control a clock gating period when a frequency of at least one of the plurality of core clock signals is changed;
a plurality of clock switching circuits configured to generate a plurality of switching clock signals by selecting one of the first clock signal and the second clock signal;
a plurality of core clock gating circuits configured to generate the plurality of core clock signals respectively corresponding to the plurality of switching clock signals by deactivating the plurality of switching clock signals during the clock gating period based on the clock gating signal; and
an interface clock gating circuit configured to generate the interface clock signal by deactivating the second clock signal during the clock gating period based on the clock gating signal.