Patent ID: 11860671
Assignee: WINBOND ELECTRONICS CORP.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. The memory-control logic as claimed in claim 1, wherein the logic circuit comprises:
a first inverter coupled to the binary array;
a second inverter coupled to the binary array;
a first AND gate receiving an output of the first inverter and an output of the second inverter;
a second AND gate receiving the output the first inverter and an output of the first AND gate and providing a first output signal;
a third AND gate receiving the output of the first inverter and a second highest bit of the first redirected address signal and providing a second output signal;
a NAND gate coupled to the binary array; and
a fourth AND gate receiving a third highest bit of the first redirected address signal and an output of the NAND gate and providing a third output signal,
wherein the first output signal is provided as the first highest bit of the second redirected address signal, the second output signal is provided as the second highest bit of the second redirected address signal, and the third output signal is provided as the third highest bit of the second redirected address signal.