Patent ID: 11877447
Assignee: WINBOND ELECTRONICS CORP.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A manufacturing method of a flash memory, comprising:
providing a substrate having a memory region and a peripheral region;
forming a plurality of first isolation structures in the substrate in the peripheral region to define a first active area between the first isolation structures;
forming a memory structure on the substrate in the memory region, wherein the memory structure comprises:
a tunneling dielectric layer, disposed on the substrate in a second active area in the memory region;
a floating gate, located on the tunneling dielectric layer;
conductive spacers, located on sidewalls of the floating gate;
a control gate, covering the floating gate and the conductive spacers; and
an inter-gate dielectric layer, located between the control gate and the floating gate and between the control gate and the conductive spacers;

forming an oxide layer on the substrate in the first active area, wherein a top surface of the oxide layer is covered by the first isolation structures, and an opening is defined in the oxide layer and the first isolation structures covering the oxide layer and exposes a part of the substrate; and
forming a gate structure on the substrate in the first active area in the peripheral region, wherein a width of a bottom surface of the gate structure is less than a width of a top surface of the first active area in the peripheral region.