Patent ID: 11947462
Assignee: APPLE INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. A non-transitory computer readable storage medium having stored thereon design information that specifies a design of at least a portion of a hardware integrated circuit in a format recognized by a semiconductor fabrication system that is configured to use the design information to produce the circuit according to the design, wherein the design information specifies that the circuit includes:
execution circuitry configured to perform operations for instructions from multiple threads in parallel;
cache circuitry configured to store information operated on by threads executed by the execution circuitry;
tracking circuitry configured to determine one or more performance metrics for the cache circuitry; and
control circuitry configured to:
based on the one or more performance metrics meeting a threshold, reduce a limit on a number of threads concurrently executed by the execution circuitry over one or more time windows, to control a footprint of information stored by the cache circuitry; and
based on a bypass indicator for a thread, consider the thread for scheduling regardless of the limit on the number of threads, wherein the consideration allows the number of threads concurrently executed to exceed the limit on the number of threads during a portion of execution of the thread.