Patent ID: 11935888
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 9:
10. An integrated circuit, comprising
a first cell having an N-well in a substrate, and a first cell active area with a first gate electrode extending along a first longitudinal axis and a first cell drain region; and
a second cell having a second cell active area in the substrate with a second gate electrode extending along a second longitudinal axis and a second cell drain region, and
a shared source region between the first gate electrode and the second gate electrode, wherein the first cell active area and the second cell active area abut along a cell boundary extending through the shared source region along a third longitudinal axis parallel to the first and second longitudinal axes, and a boundary of the N-well is aligned with the cell boundary.