Patent ID: 11954493
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A system, comprising:
a first cache set;
a second cache set;
a logic circuit coupled to a processor to control the first cache set and the second cache set;
a plurality of registers, comprising a first register associated with the first cache set and a second register associated with the second cache set;
a connection to a speculation-status signal line from the processor identifying a status of a speculative execution of instructions by the processor;
wherein when an execution type identified by the processor changes from speculative execution to non-speculative execution, the logic circuit is configured to:
implement commands via the second cache set in response to a status of speculative execution indicating that a result of speculative execution is to be accepted; and
implement commands via the first cache set in response to the status of speculative execution indicating that a result of speculative execution is to be rejected;

a mapping circuit to map physical outputs of the first cache set to a first logical cache and the second cache set to a second logical cache;
and

wherein when the execution type changes from the speculative execution to a non-speculative execution, the logic circuit is configured to:
change the state of the first and second registers, if the status of speculative execution indicates that a result of speculative execution is to be accepted; and

maintain the state of the first and second registers without changes, if the status of speculative execution indicates that a result of speculative execution is to be rejected.