Patent ID: 11935890
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 0:
1. A method comprising:
forming a first inter-layer dielectric (ILD) layer over a semiconductor device that includes a first transistor structure;
forming a two-dimensional (2D) material layer over and in contact with the first ILD layer;
patterning the 2D material layer to form a channel layer of a second transistor structure;
forming a source electrode and a drain electrode of the second transistor structure over the patterned 2D material layer and laterally spaced apart from each other;
forming a gate dielectric layer of the second transistor structure over the patterned 2D material layer, the source electrode and the drain electrode; and
forming a gate electrode of the second transistor structure over the gate dielectric layer and laterally between the source electrode and the drain electrode.