Patent ID: 11929110
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 18:
19. A method of operating a memory circuit, the method comprising:
generating, by a global control circuit, a first set of global pre-decoder signals, a second set of global pre-decoder signals and a first set of local address signals in response to a memory address signal and a first clock signal;
generating, by a first clock pre-decoder circuit, a first set of clock signals and a second set of clock signals in response to the first set of local address signals and the first clock signal, the first clock pre-decoder circuit being coupled to the global control circuit;
generating, by a first set of repeater circuits, a first set of local pre-decoder signals in response to the first set of global pre-decoder signals, and generating a second set of local pre-decoder signals in response to the second set of global pre-decoder signals;
generating, by a first set of word line post-decoder circuits, a first set of word line signals in response to the first set of clock signals, the first set of local pre-decoder signals and the second set of local pre-decoder signals, the first set of word line post-decoder circuits being coupled to the first clock pre-decoder circuit and the first set of repeater circuits; and
storing a first set of data in a first set of memory cells in response to at least the first set of word line signals, the first set of memory cells being coupled to the first set of word line post-decoder circuits.