Patent ID: 11928025
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus, comprising:
a plurality of memory devices; and
a controller coupled to the plurality of memory devices via a plurality of respective channels, the controller configured to:
perform, using first error correction code (ECC) data, an error detection operation on host data read from a first portion of the plurality of memory devices; and
responsive to the error detection operation indicating a quantity of errors on the host data:
read, from a second portion of the plurality of memory devices, second ECC data different than the first ECC data and that was not read to the controller for the error detection operation; and
to perform, using the second ECC data, an error correction operation to correct the quantity of errors indicated through the error detection operation:
read other host data from a third portion of the plurality of memory devices; and
perform an XOR operation among the other host data and the second ECC data to recover the host data.