Patent ID: 11950434
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 17:
18. A method for forming an integrated chip, the method comprising:
depositing a first conductive layer;
depositing a second conductive layer over the first conductive layer;
depositing a switching layer over the second conductive layer;
depositing a third conductive layer over the switching layer;
depositing a phase change memory layer over the third conductive layer;
depositing a fourth conductive layer over the phase change memory layer;
etching the fourth conductive layer, the phase change memory layer, the third conductive layer, the switching layer, the second conductive layer, and the first conductive layer along a first direction to form a first line structure and a second line structure from the fourth conductive layer, the phase change memory layer, the third conductive layer, the switching layer, and the second conductive layer, and to form a first word line and a second word line from the first conductive layer, wherein the first line structure, the second line structure, the first word line, and the second word line are elongated in the first direction, wherein the first line structure is over the first word line, and wherein the second line structure is over the second word line;
depositing a first dielectric layer between the first line structure and the second line structure, wherein a first void is within the first dielectric layer between the first line structure and the second line structure, and wherein the first void is delimited by one or more surfaces of the first dielectric layer;
depositing a fifth conductive layer over the first line structure and the second line structure;
etching the fifth conductive layer, the first line structure, and the second line structure along a second direction, transverse to the first direction, to form a first memory stack and a fourth memory stack from the first line structure, to form a second memory stack and a third memory stack from the second line structure, and to form a first bit line and a second bit line from the fifth conductive layer, wherein the first bit line and the second bit line are elongated in the second direction, wherein the first memory stack and the second memory stack are under the first bit line, and wherein the third memory stack and the fourth memory stack are under the second bit line; and
depositing a second dielectric layer between the first memory stack and the fourth memory stack and between the second memory stack and the third memory stack, wherein a second void is within the second dielectric layer between the first memory stack and the fourth memory stack and between the second memory stack and the third memory stack, and wherein the second void is delimited by one or more surfaces of the second dielectric layer.