Patent ID: 11948640
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device comprising:
a first transistor;
a second transistor;
a plurality of memory cells electrically connected in series between the first transistor and the second transistor;
a source line electrically connected to the first transistor;
a hit line electrically connected to the second transistor;
a plurality of word lines electrically connected to gates of the plurality of memory cells, respectively;
a sense amplifier including
a first node,
a third transistor including a first end electrically connected to the bit line and a second end electrically connected to the first node,
a fourth transistor including a first end electrically connected to the second end of the third transistor and to the first node,
a fifth transistor including a gate electrically connected to the first node,
a sixth transistor including a first end electrically connected to a first end of the fifth transistor,
a seventh transistor including a first end electrically connected to the first end of the fifth transistor,
a first data latch electrically connected to a second end of the sixth transistor, and
a second data latch electrically connected to a second end of the seventh transistor, and

a controller configured to perform a read operation including
a first period,
a second period after the first period,
a third period after the second period,
a fourth period after the third period, and
a fifth period after the fourth period, and
at least during the second to fourth periods, a first voltage being applied to one of the plurality of word lines, and a second voltage higher than the first voltage being applied to another one of the word lines,
during the first period, a third voltage being applied to a gate of the fourth transistor to turn on the fourth transistor,
during the second period, a fourth voltage being applied to a gate of the fourth transistor to turn off the fourth transistor, and a fifth voltage being applied to a gate of the third transistor to turn on the third transistor,
after the second period, a sixth voltage being applied to a gate of the sixth transistor to turn on the sixth transistor,
during the third period, a seventh voltage being applied to the gate of the third transistor to turn off the third transistor,
during the fourth period, an eighth voltage being applied to the gate of the third transistor to turn on the third transistor, and
after the fourth period, a ninth voltage being applied to a gate of the seventh transistor to turn on the seventh transistor.