Patent ID: 11935957
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A method for semiconductor processing, the method comprising:
forming a first fin and a second fin protruding from a substrate and extending through a first isolation region, wherein the first fin has a greater height above the first isolation region than the second fin;
forming a first dummy gate structure over the first fin and a second dummy gate structure over the second fin;
forming a second isolation region on opposing sides of the first dummy gate structure and the second dummy gate structure;
removing the first dummy gate structure to expose the first fin and removing the second dummy gate structure to expose the second fin; and
forming a first replacement gate structure over the first fin and a second gate replacement structure over the second fin, wherein the first replacement gate structure has a first distance from an end of the first replacement gate structure to the first fin, wherein the second replacement gate structure has a second distance from an end of the second replacement gate structure to the second fin, wherein the first distance is different than the second distance, wherein the first fin is a closest first fin to the end of the first replacement gate structure, wherein the second fin is a closest second fin to the end of the second replacement gate structure.