Patent ID: 11880308
Assignee: APPLE INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 16:
17. A system comprising:
a cache subsystem, wherein the cache subsystem includes:
a tag array circuit configured to store tags corresponding to cache lines arranged in a plurality of ways of a cache memory circuit;
a prediction circuit configured to, in response to a request for access to the tag array circuit, generate a prediction of a particular one of the plurality of ways includes a particular cache line associated with the request; and
a comparison circuit configured to verify whether the prediction is correct by comparing an address tag associated with the particular cache line to a cache tag associated with the particular one of the plurality of ways;
wherein the prediction circuit is configured to cause a confirmation bit to be stored in a confirmation bit memory in response to the comparison circuit indicating that the prediction was correct; and
wherein, based on the confirmation bit the comparison circuit is configured to, for a subsequent request for access to the particular cache line, indicate a match of the address tag and the cache tag without reading the tag array circuit and without performing the comparing.