Patent ID: 11961575
Assignee: SAMBANOVA SYSTEMS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 2:
3. The IC of claim 1, wherein the first set of two or more storage elements consists of N storage elements respectively coupled to an Nth latch clock of the plurality of latch clocks, the IC further comprising:
a second set of N storage elements having inputs coupled to a second output of the second scan latch, an Nth storage element of the second set of N storage elements coupled to the Nth latch clock of the plurality of latch clocks and enabled to load data during a time that the Nth latch clock is in an active state, and outputs of the second set of N storage elements coupled to the selector circuit which is further configured to also output a second value from one output of the outputs of the second set of N storage elements on the selector output based on the second address input.