Patent ID: 11894421
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A device comprising:
a substrate having a first region, a second region and a third region, the second region extending from the first region to the third region;
a first channel feature disposed over the first region;
a first gate structure wrapping around the first channel feature;
a second channel feature disposed over the third region;
a second gate structure wrapping around the second channel feature;
a first source/drain feature disposed over the second region and associated with the first and second gate structures; and
a first electrically insulating layer disposed under and interfacing with the first source/drain feature, the first channel feature and the second channel feature such that the first electrically insulating layer extends continuously from the first channel feature to the second channel feature.