Patent ID: 11916551
Assignee: FLEX LOGIX TECHNOLOGIES, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of routing interconnects of an integrated circuit comprising a field programmable gate array including: (i) a plurality of logic tiles, wherein each logic tile includes a logic tile interconnect network having a plurality of switches and a plurality of logic tile interconnects, (ii) a tile-to-tile interconnect network, having a plurality of tile-to-tile interconnects, each having start/end points, to interconnect logic tile networks of the plurality of logic tiles, the method comprising:
routing a first plurality of tile-to-tile interconnects in a first plurality of logic tiles wherein: (i) the first plurality of logic tiles are a first subset of the plurality of logic tiles and (ii) the start/end point of each tile-to-tile interconnect in the first plurality of logic tiles is independent of the start/end point of the other tile-to-tile interconnects in the first plurality of logic tiles;
after routing the first plurality of tile-to-tile interconnects, routing a second plurality of tile-to-tile interconnects in a second plurality of logic tiles wherein: (i) the second plurality of logic tiles are a second subset of the plurality of logic tiles and (ii) the start/end point of each tile-to-tile interconnect in the second plurality of logic tiles is independent of the start/end point of the other tile-to-tile interconnects in the second plurality of logic tiles; and
wherein routing the second plurality of tile-to-tile interconnects in the second plurality of logic tiles includes connecting at least one start/end point of each tile-to-tile interconnect in the second plurality of logic tiles to at least one start/end point of each tile-to-tile interconnect in the first plurality of logic tiles that was routed in the first plurality of logic tiles.