Patent ID: 11899609
Assignee: NVIDIA CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A system comprising:
a first device comprising a transmitter and coupled with a link comprising one or more data lanes, the first device to:
transmit two or more frames to synchronize the one or more data lanes, wherein each frame comprises a quantity of bits; and

a second device coupled with the link and comprising a receiver, the second device to:
receive a first set of bits from each data lane corresponding to the quantity of bits in each frame of the two or more frames;
determine that the first set of bits received from a data lane of the one or more data lanes does not correspond to a frame boundary of the two or more frames;
synchronize each data lane of the one or more data lanes with respect to the frame boundary by shifting the first set of bits received at the data lane of the one or more data lanes by one or more unit intervals (UIs) responsive to determining the first set of bits does not correspond to the frame boundary;
receive a second set of frames on each data lane of the one or more data lanes, each frame of the second set of frames comprising a value;
determine that a value received at the data lane of the one or more data lanes is different than a value received at the remaining data lanes of the one or more data lanes; and
synchronize the second set of frames received on each data lane of the one or more data lanes by shifting the second set of frames by one burst unit interval (BUI) responsive to determining the second set of frames is not the same for each data lane.