Patent ID: 11923331
Assignee: nan
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. An integrated chip (IC), comprising:
a substrate;
a die disposed over the substrate;
a metal wire attached to a frontside of the die;
a plurality of die stopper bumps arranged as a plurality of groups of die stopper bumps, wherein each group of the plurality of groups of die stopper bumps is disposed along a backside of the die;
a first plurality of epoxy glue structures, each of the first plurality of epoxy glue structures enveloping sidewalls of each die stopper bump of a corresponding group of the plurality of groups of die stopper bumps to bond the backside of the die to the substrate;
a housing structure disposed over the die and surrounding sidewalls of the die;
a plurality of housing stopper bumps directly contacting and disposed between the housing structure and the substrate, wherein the plurality of housing stopper bumps contacts a bottom surface of the housing structure and the plurality of housing stopper bumps are arranged as a plurality of groups of housing stopper bumps;
a second plurality of epoxy glue structures, each of the second plurality of epoxy glue structures enveloping sidewalls of each housing stopper bump of a corresponding group of the plurality of groups of housing stopper bumps to bond the housing structure to the substrate; and
a cavity arranged directly between the housing structure and an uppermost surface of the die and separating the housing structure from the uppermost surface of the die.