Patent ID: 11949358
Assignee: RENESAS ELECTRONICS CORPORATION
Field: Electrical machinery, apparatus, energy (Electrical engineering)
Classification: CPC G  H | IPC H

Claim 0:
1. A semiconductor device comprising:
an arithmetic unit including a multiplier and an adder;
a memory configured to hold calculated data; and
a control circuit configured to control the arithmetic unit and the memory,
wherein the control circuit receives a command from outside and causes the arithmetic unit to perform arithmetic operation M times (M is an integer of 2 or more) by using input data from outside and the calculated data held in the memory, thereby making the arithmetic unit and the memory function as an IIR (Infinite Impulse Response) filter including a multiplication block, an addition block, and a delay block,
wherein the IIR filter is a filter capable of determining output data by arithmetic operation of K times out of the M times (K<M),
wherein the control circuit receives the command from outside and then causes the arithmetic unit to perform the arithmetic operation K times in advance, thereby determining the output data and outputting the output data to the outside at the time of the determination,
wherein the arithmetic operation performed M times in the IIR filter is divided into output data operation required for determining the output data and delay data operation required for determining the calculated data held in the memory serving as the delay block,
wherein the control circuit causes the arithmetic unit to perform the output data operation in advance and then perform the delay data operation, and
wherein the control circuit causes the arithmetic unit and the memory to function as the IIR filters at multiple stages connected in cascade, causes the arithmetic unit to sequentially perform the output data operations in the IIR filters at multiple stages from first stage to final stage after receiving the command from outside and then sequentially perform the delay data operations in the IIR filters at the multiple stages from first stage to final stage, and causes the arithmetic unit to output the output data of the IIR filter at the final stage to outside at the time when the output data operation in the IIR filter at the final stage is finished.