Patent ID: 11887952
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A package structure, comprising:
a first dielectric layer;
a first semiconductor device over the first dielectric layer;
a first redistribution line in the first dielectric layer;
a second dielectric layer over the first semiconductor device;
a second semiconductor device over the second dielectric layer;
a second redistribution line in the second dielectric layer;
a conductive through-via over the first dielectric layer, wherein the conductive through-via has a top at a position lower than a top surface of the first semiconductor device;
a conductive ball over the conductive through-via;
a molding material surrounding the first semiconductor device, the conductive through-via, and the conductive ball, wherein a top of the conductive ball is higher than a top surface of the molding material; and
a buffer layer on the top surface of the molding material, wherein the top of the conductive ball is higher than a top of the buffer layer.