Patent ID: 11871587
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 3:
4. A memory device, comprising:
a substrate including first select components, which include N-channel metal oxide semiconductor (NMOS) transistors, and a second select component, which includes P-channel metal oxide semiconductor (PMOS) transistors;
a plurality of decks each including a plurality of memory cells and stacked over the substrate in a vertical direction perpendicular to a surface of the substrate;
row lines coupled to the first select components, respectively, and coupled to the decks, respectively;
a connection structure coupling each of the row lines to a corresponding NMOS transistor among the NMOS transistors; and
column lines coupled in common to one of the PMOS transistors of the second select component, and coupled to the decks, wherein the column lines are stacked in the vertical direction,
wherein the connection structure comprises at least one via plug.