Patent ID: 11862960
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Electrical machinery, apparatus, energy (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. An electrostatic discharge (ESD) protection circuit, comprising:
a first diode in a semiconductor wafer, and being coupled to a first pad;
a second diode in the semiconductor wafer, and being coupled to the first diode and the first pad;
an input output (IO) circuit in the semiconductor wafer, and being coupled to the first diode, the second diode, and the first pad;
an internal circuit coupled to the IO circuit; and
an ESD clamp circuit in the semiconductor wafer, and being coupled to the first diode by a first node and coupled to the second diode by a second node, the ESD clamp circuit including a first signal tap region coupled to a voltage supply, and a second signal tap region coupled to a reference voltage supply,
wherein the first diode is coupled to and configured to share the first signal tap region with the ESD clamp circuit; and
the second diode is coupled to and configured to share the second signal tap region with the ESD clamp circuit.