Patent ID: 11973130
Assignee: X-FAB FRANCE SAS
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of manufacturing of a semiconductor device, comprising:
providing a semiconductor substrate having a first region, a second region and a third region;
on the first region, providing a first dielectric layer;
on the second region, providing a second dielectric layer;
on the third region, providing an ONO stack;
on each of the first, second and third regions, providing at least one gate structure;
performing an oxidation step so as to form an oxide layer on each of the gate structures of the first, second and third regions and exposed portions of the first and second dielectric layers;
providing a first tetraethyl orthosilicate, TEOS, layer across the third region to cover a part of the ONO stack extending laterally out from under the at least one gate structure on the third region, and across at least part of the second region;
blanket depositing a first silicon nitride, SiN, layer across the first, second and third regions; and
etching the first SiN layer leaving at least some of said first SiN layer on each gate structure of the first, second and third regions so as to form a first SiN sidewall spacer portion on each gate structure of the first, second and third regions, wherein the part of the ONO stack extending laterally out from under the at least one gate structure is protected from the etching by the first TEOS layer.