Patent ID: 11973112
Assignee: SILANNA ASIA PTE LTD
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 19:
20. The transistor tile of claim 14, wherein:
a horizontal distance between the base N+ region and the emitter P+ region controls a base-emitter maximum rating voltage of the transistor tile;
a horizontal distance between the base N+ region and a nearest edge of the first or second PLDD region controls a collector-base maximum rating voltage of the transistor tile;
a horizontal distance between the emitter P+ region and another nearest edge of the first or second PLDD region controls a collector-emitter maximum rating voltage of the transistor tile; and
a horizontal distance between the first or second collector P+ region and an outer edge of the first or second PLDD region controls a ratio of the collector-base maximum rating voltage to the collector-emitter maximum rating voltage of the transistor tile.