Patent ID: 11928027
Assignee: CADENCE DESIGN SYSTEMS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A method comprising:
receiving one or more fixed size error checking and correction data blocks and metadata at a memory controller;
performing data to symbol mapping based upon, at least in part, the one or more fixed size data blocks;
providing an output of the data to symbol mapping to a first encoder without metadata configured for full detection correction of single device error and to a second encoder with metadata configured for partial detection correction of single device error;
receiving data at a memory based upon, at least in part, an output from the first encoder and the second encoder;
receiving data from the memory at a first decoder without metadata configured for full detection correction of single device error and at a second decoder with metadata configured for partial detection correction;
re-mapping symbol data from the first decoder and the second decoder to actual data; and
generating one or more output data blocks and metadata.