Patent ID: 11966785
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. A processing system comprising:
a plurality of processor cores, the plurality of processor cores comprising a first processor core and a second processor core and the processing system being configured to support the first processor core processing a workload using borrowed hardware resource of the second processor core, wherein the processing system is configured to support a plurality of alternative hardware resource configurations corresponding to different amounts of inter-core borrowing of hardware resources between the plurality of processor cores;
performance monitoring circuitry configured to obtain performance monitoring data indicative of processing performance associated with workloads to be executed on the processing system, the performance monitoring data comprising a first set of performance monitoring data corresponding to a first workload to be executed on the first processor core and a second set of performance monitoring data corresponding to a second workload to be executed on the second processor core;
circuitry to generate, based on the first set of performance monitoring data corresponding to the first workload to be executed on the first processor core and the second set of performance monitoring data corresponding to the second workload to be executed on the second processor core, input data for a trained machine learning model, the trained machine learning model being arranged to output an inference identifying at least one of the plurality of alternative hardware resource configurations corresponding to an amount of inter-core borrowing of hardware resources that is suitable for executing the first workload on the first processor core and the second workload on the second processor core;
circuitry to provide the input data to the trained machine learning model; and
configuration control circuitry responsive to the inference output by the trained machine learning model in response to the input data, to control, based on the at least one hardware resource configuration identified by the inference, an amount of inter-core borrowing of hardware resource between the plurality of processor cores.