Patent ID: 11862588
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A device comprising:
a first passivation layer on a semiconductor substrate;
a first redistribution line on and extending along the first passivation layer, the first redistribution line having a first width in a first direction of a top-down view, the first redistribution line having a first length in a second direction of the top-down view, the second direction perpendicular to the first direction, the first length greater than the first width;
a second redistribution line on and extending along the first passivation layer, the second redistribution line having a second width in the first direction of the top-down view, the second redistribution line having a second length in the second direction of the top-down view, the second length greater than the second width, the second redistribution line separated from the first redistribution line by a first distance;
a first dielectric layer on the first redistribution line, the second redistribution line, and the first passivation layer;
an under bump metallization on the first dielectric layer, the under bump metallization coupled to the first redistribution line and the second redistribution line, the under bump metallization having a third width, the third width being greater than the sum of the first width, the second width, and the first distance;
a package substrate; and
a conductive connector bonding the package substrate to the under bump metallization.