Patent ID: 11956940
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 14:
15. A memory device, comprising:
a pair of bit lines;
a plurality of transistors stacked between the pair of bit lines in a first direction, wherein each transistor of the plurality of transistors comprises:
a source region;
a drain region;
a channel region stacked between the source region and the drain region in the first direction; and
a gate structure adjacent the channel region and extending lengthwise in a second direction perpendicular to the first direction; and

a capacitive device stacked between the plurality of transistors in the first direction, wherein the capacitive device comprises:
a first conductor extending between the plurality of transistors in the first direction;
a dielectric material on the first conductor; and
a second conductor on a side of the dielectric material opposite the first conductor, and extending lengthwise in a third direction perpendicular to the first direction and the second direction.