Patent ID: 11962320
Assignee: INTEL CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 12:
13. The semiconductor chip of claim 12, wherein the numerically controlled oscillator comprises:
a first input node for the frequency control data;
a second input for the signal propagation delay data;
a first combiner circuit configured to combine a sample of the frequency control data with a phase accumulation sample in order to generate an updated phase accumulation sample, wherein the phase accumulation sample is an accumulation of preceding samples of the frequency control data,
a delay circuit configured to delay the updated phase accumulation sample;
a second combiner circuit configured to combine a sample of the signal propagation delay data and the delayed updated phase accumulation sample in order to generate a control sample; and
a CORDIC circuit configured to generate the digital reference data based on the control sample.