Patent ID: 11888074
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A method for forming a flash memory cell, comprising:
forming a stack including a tunnel dielectric layer, a floating gate electrode, a control gate dielectric layer, and a control gate electrode over a semiconductor substrate, wherein each sidewall of the stack vertically extends from a top surface of the semiconductor substrate to an edge of a top surface of the control gate electrode within a respective vertical plane;
reducing a size of the control gate electrode by etching a portion of the control gate electrode to expose a surface of the control gate dielectric layer, wherein a lateral extent of the control gate electrode along a horizontal direction becomes less than a lateral extent of the control gate dielectric layer along the horizontal direction; and
forming a source region and a drain region in an upper portion of the semiconductor substrate, wherein the source region and the drain region are laterally spaced apart along the horizontal direction; and
forming an electrical contact on the exposed surface of the control gate dielectric layer, wherein the exposed surface of the control gate dielectric layer is over a channel region located between the source region and the drain region.