Patent ID: 11972979
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of fabricating an interconnect layer over a semiconductor die, comprising:
fabricating a grating comprising a plurality of parallel lines over an interlayer dielectric (ILD), wherein the plurality of parallel lines defines a plurality of channels;
depositing a mask layer over the grating;
depositing a hardmask over the mask layer, wherein the hardmask fills the plurality of channels;
patterning the hardmask to form an opening that spans between neighboring lines of the plurality of parallel lines, wherein the hardmask is cleared from a channel of the plurality of channels that is exposed under the opening;
recessing the hardmask, wherein a top surface of the hardmask is below a top surface of the mask layer; and
etching the mask layer with an isotropic etching process, wherein the isotropic etching process removes the mask layer from the exposed channel.