Patent ID: 11887674
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. The memory apparatus as set forth in claim 3, wherein the control means is further configured to:
apply a read voltage corresponding to each of the plurality of data states in a predetermined sequence of the plurality of data states to each of the plurality of word lines followed by a bit line settling time during the read operation;
determine which one of a plurality of word line bias impact groups each one of the plurality of data states being read belongs, the plurality of data states being grouped into one of the plurality of word line bias impact groups according to a quantity of the plurality of data states skipped from a previous one of the plurality of data states being read prior to the one of the plurality of data states during the read operation according to the predetermined sequence; and
offset the bit line settling time by a settling offset according the one of the plurality of word line bias impact groups each one of the plurality of data states being read belongs, the bit line settling time being comparatively longer in response to the quantity of the plurality of data states skipped being higher in magnitude and the bit line settling time being comparatively shorter in response to the quantity of the plurality of data states skipped being smaller in magnitude.