Patent ID: 11972732
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. The shift register unit according to claim 1, wherein the second clock signal terminal is inputted with a high level, the first clock signal terminal is inputted with a low level, the starting voltage is of a high level, a potential of the first node is of a low level, potentials of the second control node and the second node are both of high levels, the fourth control transistor, the fifth control transistor, the sixth control transistor, and the first output transistor are turned on, and the first gate drive signal output terminal is outputted with a high level;
the second clock signal terminal is inputted with a low level, the first clock signal terminal is inputted with a high level, the starting voltage is of a low level, a potential of the first node is of a low level, potentials of the second control node and the second node are both of low levels, the third control transistor, the second control transistor, the second output transistor, the first output pull-down transistor, and the sixth control transistor are turned on, and the first gate drive signal output terminal and the second gate drive signal output terminal are outputted with a high level;
the second clock signal terminal is inputted with a high level, the first clock signal terminal is inputted with a low level, the starting voltage is of a high level, a potential of the first node is of a high level, potentials of the second control node and the second node are both of low levels, the second control transistor, the fifth control transistor, the first output pull-down transistor, and the sixth control transistor are turned on, and the first gate drive signal output terminal is outputted with a low level;
the second clock signal terminal is inputted with a low level, the first clock signal terminal is inputted with a high level, the starting voltage is of a high level, a potential of the first node is of a low level, potentials of the second control node and the second node are both of high levels, the third control transistor, the first control transistor, the first output transistor, the fourth control transistor, and the sixth control transistor are turned on, and the first gate drive signal output terminal is outputted with a high level; and
the second clock signal terminal is inputted with a high level, the first clock signal terminal is inputted with a low level, the starting voltage is of a high level, a potential of the first node is of a low level, potentials of the second control node and the second node are both of high levels, the fourth control transistor, the fifth control transistor, the sixth control transistor, and the first output transistor are turned on, and the first gate drive signal output terminal is outputted with a high level.