Patent ID: 11943921
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An integrated circuit (IC) comprising:
a memory region and a logic region integrated in a substrate;
a plurality of memory cell structures disposed on the memory region, each memory cell structure of the plurality of memory cell structures comprising a control gate electrode disposed over the substrate, a select gate electrode disposed on one side of the control gate electrode, and a spacer between the control gate electrode and the select gate electrode;
a contact etch stop layer (CESL) disposed along an upper surface of the substrate, extending upwardly along the select gate electrode within the memory region; and
a lower inter-layer dielectric layer disposed on the CESL and fill between the plurality of memory cell structures within the memory region,
wherein the CESL is in direct contact with sidewalls of the select gate electrode and the lower inter-layer dielectric layer.