Patent ID: 11973023
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A structure, comprising:
a semiconductor die laterally encapsulated by an insulating encapsulant;
a first dielectric layer disposed on the semiconductor die and the insulating encapsulant;
a first conductive via embedded in the first dielectric layer, wherein the first conductive via is disposed over and electrically connected to the semiconductor die;
a first patterned seed layer covering he first conductive via and a portion of the first dielectric layer, wherein the first dielectric layer is in direct contact with the semiconductor die, the insulating encapsulant and sidewalls of the first conductive via;
a first redistribution wiring disposed on the first patterned seed layer, wherein the first patterned seed layer is interposed between the first conductive via and the first redistribution wirings;
a second dielectric layer disposed over the first dielectric layer and the first redistribution wiring; and
a second conductive via disposed over the first redistribution wiring, the second conductive via being electrically connected to the first redistribution wiring, wherein a first angle between a top surface of the first conductive via and a sidewall of the first conductive via is less than a second angle between a top surface of the second conductive via and a sidewall of the second conductive via.