Patent ID: 11929140
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A memory controller comprising:
a direct memory access (DMA) master device configured to provide a first data group to a non-volatile memory device;
a program buffer memory configured to temporarily store the first data group, before the DMA master device provides the first data group to the non-volatile memory device;
a buffer slave device including a first program recovery buffer memory, the first program recovery buffer memory configured to store a first recovery data generated by performing a computation on a plurality of data included in the first data group provided from the program buffer memory, after the DMA master device provides the first data group to the non-volatile memory device;
a SRAM including the program buffer memory and the first program recovery buffer memory; and
a processor configured to control the DMA master device, the buffer slave device, and the SRAM,
wherein the processor is further configured to designate a region in the SRAM that corresponds to the program buffer memory configured to store the first data group, and
the processor is further configured to designate a region in the SRAM that corresponds to the first program recovery buffer memory configured to store the first recovery data.