Patent ID: 11971776
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A host system to interface with a memory device, the host system comprising:
a processor configured to execute instructions stored on one or more components in the host system, which instructions, when executed by the processor, cause the host system to perform operations, the operations comprising:
detecting, within the host system, a number of an error conditions associated with the memory device;
comparing the number of error conditions with respect to one or more thresholds for allowable error conditions; and
transmitting, in response to the comparison of the error conditions, a trigger signal to the memory device to dump an error log in the memory device, using a standardized protocol including the trigger signal, using a format selected in the host system from three or more formats to handle the trigger signal.