Patent ID: 11935833
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 3:
4. The method of claim 1, wherein:
the forming the plurality of first vias includes:
forming a via at each location where the first metal segments of the plurality of first metal segments overlap the first power rail and at each location where the first metal segments of the plurality of first metal segments overlap the second power rail;

the forming the plurality of second metal segments includes:
forming each second metal segment to have a width wider than a predetermined minimum width for the second metal segment; and

the forming the IC structure further includes:
forming a plurality of third metal segments at a third metal level immediately above the second metal level, the plurality of third metal segments being oriented in the first metal level direction and including a first set of third metal segments alternating with a second set of third metal segments;

the forming the plurality of third metal segments includes:
forming each third metal segment of the plurality of third metal segments overlapping the first power rail and the second power rail and having a width corresponding to a predetermined minimum width for the third metal level; and
forming a plurality of third vias, the plurality of third vias electrically connecting the first set of third metal segments to at least one of the plurality of second metal segments overlapping the first power rail and electrically connecting the second set of third metal segments to at least one of the plurality of second metal segments overlapping the second power rail.