Patent ID: 11955184
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. The apparatus of claim 1, wherein the one or more control circuits are configured to:
program the group of the memory cells to multiple bits per memory cell together without verifying, wherein the first set of the memory cells is programmed to a first set of natural threshold voltage distributions, wherein the second set of the memory cells is programmed to a second set of natural threshold voltage distributions that have different threshold voltage ranges than corresponding distributions in the first set of natural threshold voltage distributions;
read the multiple bits per memory cell in the first set of the memory cells with the first set of read parameters; and
read the multiple bits per memory cell in the second set of the memory cells with the second set of read parameters, wherein the first set of read parameters are different from the second set of read parameters to compensate for different threshold voltage ranges in the first set and the second set of natural threshold voltage distributions.