Patent ID: 11901280
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A method of making a semiconductor package, comprising:
forming a package substrate having a first side and a second side opposite the first side, wherein forming the package substrate comprises:
forming a first layer of dielectric material adjacent the first side of the package substrate;
forming a second layer of dielectric material on the first layer of dielectric material, the first layer of dielectric material being between the second layer of dielectric material and the first side of the package substrate;
forming a ground solder ball pad adjacent the first side of the package substrate;
forming a first via above and electrically coupled to the ground solder ball pad, the first via being in the first layer of dielectric material of the package substrate;
forming a second via above and electrically coupled to the ground solder ball pad, the second via being in the first layer of dielectric material of the package substrate, the second via laterally spaced apart from the first via;
forming a third via above and electrically coupled to the first via and being in the second layer of dielectric material of the package substrate;
forming a fourth via above and electrically coupled to the second via and being in the second layer of dielectric material of the package substrate, the fourth via laterally spaced apart from the third via;
wherein a first line perpendicular to the first side of the package substrate intersects the ground solder ball pad, the first via, and the third via; and
wherein a second line perpendicular to the first side of the package substrate intersects the ground solder ball pad, the second via, and the fourth via;
coupling a die to the second side of the package substrate; and
disposing a solder ball on the ground solder ball pad.