Patent ID: 11915943
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. A semiconductor structure, comprising:
a via contact disposed in a first interlayer dielectric (ILD) layer, wherein the via contact includes a first etch-stop layer (ESL) disposed over a via bulk layer;
a second ESL disposed over the via contact, wherein the second ESL includes a first metal, and wherein the first and the second ESLs have different compositions;
a conductive line disposed over the second ESL, wherein the conductive line includes a second metal different from the first metal;
a second ILD layer disposed over the first ILD layer, wherein the second ILD layer directly contact sidewalls of the conductive line and the second ESL; and
a third ESL disposed over the second ILD layer.