Patent ID: 11887888
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Semiconductors (Electrical engineering)
Classification: CPC H  C | IPC H

Claim 14:
15. A method of fabricating an integrated circuit, the method comprising:
forming a trench in a dielectric layer;
depositing a barrier layer over surfaces of the trench;
forming a metal seed layer over the barrier layer;
electroplating a first copper layer over the metal seed layer;
first rinsing the first copper layer with water;
spin-drying the first copper layer after the first rinsing;
electroplating a second copper layer over the first copper layer;
second rinsing the second copper layer with water;
spin-drying the second copper layer after the second rinsing;
annealing the first copper layer only after electroplating the second copper layer; and
chemical-mechanical polishing the second copper layer after the annealing, thereby forming copper lines within the dielectric layer.