Patent ID: 11960884
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus comprising:
a decoder to decode a first instruction, the first instruction having a destination operand, a first source operand, and a second source operand;
wherein the first source operand is to specify a first source register to store a first plurality of packed complex numbers, the second source operand is to specify a second source register to store a second plurality of packed complex numbers, and each of the first plurality and the second plurality of packed complex numbers is composed of a 16-bit half-precision floating-point element in an even position corresponding to a real component and a 16-bit half-precision floating-point element in an odd position corresponding to an imaginary component; and

execution circuitry, coupled to the decoder, the execution circuitry to perform operations corresponding to the first instruction, including to, for at least one of the first plurality of packed complex numbers:
multiply an element in an even position and an element in an even position of a corresponding one of the second plurality of packed complex numbers to generate a first product,
multiply an element in an odd position and an element in an odd position of the corresponding one of the second plurality of packed complex numbers to generate a second product,
multiply the element in the odd position and the element in the even position of the corresponding one of the second plurality of packed complex numbers to generate a third product,
multiply the element in the even position and the element in the odd position of the corresponding one of the second plurality of packed complex numbers to generate a fourth product,
subtract the second product from the first product to generate a first result,
add the third product to the fourth product to generate a second result,
store the first result in an even position of a corresponding resulting packed complex number in a destination register, and
store the second result in an odd position of the corresponding resulting packed complex number in the destination register.