Patent ID: 11888064
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A method comprising:
depositing a contact etch stop layer (CESL) on a source/drain region;
depositing an inter-layer dielectric (ILD) layer on the CESL;
etching the ILD layer to form an opening through the ILD layer;
etching the CESL with a first etching process to extend the opening through the CESL;
etching the CESL with a second etching process to form an undercut between the ILD layer and the source/drain region, the second etching process different from the first etching process;
forming a silicide in the undercut and the opening, the silicide formed on the source/drain region; and
forming a source/drain contact in the undercut and the opening, the source/drain contact formed on the silicide.