Patent ID: 11902192
Assignee: FUJITSU LIMITED
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An apparatus for determining power, comprising:
a memory that stores a plurality of instructions;
a processor that couples to the memory and is configured to execute the instructions to:
select either a synchronization signal block (SSB) or a channel state information reference signal (CSI-RS) and determine whether to increase target received power according to a change of either of the selected SSB and the selected CSI-RS, wherein,
the selected CSI-RS is used for determining the random access resource, and the change of either of the selected SSB and the selected CSI-RS at least comprises, a second CSI-RS is selected for a last Random Access Preamble transmission; or a second SSB is selected for a last Random Access Preamble transmission; or
the selected SSB is used for determining the random access resource, and the change of either of the selected SSB and the selected CSI-RS at least comprises, a third CSI-RS is selected for a last Random Access Preamble transmission;

the target received power is used for determining transmitting power of a random access preamble.