Patent ID: 11935621
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 11:
12. A memory, comprising a calibration circuit, wherein the calibration circuit comprises:
a differential input circuit, configured to receive a first oscillation signal and a second oscillation signal, the first oscillation signal and the second oscillation signal having a same frequency and opposite phases, a duty cycle of the first oscillation signal and a duty cycle of the second oscillation signal being in a first preset range, and the differential input circuit configured to output a first internal signal and a second internal signal;
a comparison unit, connected to an output end of the differential input circuit, and configured to compare the duty cycle of the first internal signal and/or the duty cycle of the second internal signal; and
a logical unit, connected to the comparison unit and the differential input circuit, and configured to control the differential input circuit according to an output result of the comparison unit, such that the duty cycle of the first internal signal and/or the duty cycle of the second internal signal reaches a second preset range,
wherein the differential input circuit is further configured to receive a first external signal and a second external signal, and the first external signal and the second external signal have a same frequency and opposite phases.