Patent ID: 11868870
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 30:
31. A neuromorphic processor comprising:
an axon circuit;
a synaptic circuit connected to the axon circuit; and
a neuron circuit connected to the synaptic circuit and comprising an adder,
wherein the neuron circuit is configured to perform a multiplication operation between a multi-bit activation input input to the axon circuit and a multi-bit synaptic weight input input to the synaptic circuit through respective uses of the adder in a time-division manner, and
wherein one bit of the multi-bit activation input and one bit of the multi-bit synaptic weight that are to be assigned at each time period of different time periods are determined such that bits indicating a multi-bit neuromorphic operation result are sequentially obtained by the neuron circuit from a value of a least significant bit (LSB) to a value of a most significant bit (MSB).