Patent ID: 11960731
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A method, comprising:
performing, by interface (I/F) circuitry of a memory system comprising a first in first out (FIFO) memory, a first logical operation on first signaling and second signaling,
wherein the first signaling is indicative of a first value of a write pointer of the FIFO memory corresponding to a current cycle of a read clock of the memory system, and
wherein the second signaling is indicative of a read pointer of the FIFO memory corresponding to the current cycle of the read clock of the memory system;
performing, by the I/F circuitry, a second logical operation on the second and third signaling,
wherein the third signaling is indicative of a second value of the write pointer corresponding to a subsequent cycle of the read clock;
responsive to the first logical operation yielding a first particular result, providing, by the I/F circuitry, fourth signaling indicative of a potential overflow of the FIFO memory; and
responsive to the second logical operation yielding a second particular result, providing, by the I/F circuitry, fifth signaling indicative of a potential underflow of the FIFO memory.