Patent ID: 11923812
Assignee: QORVO US, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A power management integrated circuit (PMIC) comprising:
a target voltage circuit comprising:
an envelope detector circuit configured to detect a time-variant envelope of an analog signal, wherein the detected time-variant envelope is delayed from the time-variant envelope of the analog signal by a first temporal delay;
an analog look-up table (LUT) circuit configured to generate a target voltage based on the detected time-variant envelope of the analog signal, wherein the target voltage is delayed from the detected time-variant envelope of the analog signal by a second temporal delay; and
a voltage processing circuit configured to generate a modified target voltage that is time-adjusted relative to the time-variant envelope of the analog signal to thereby substantially offset at least the first temporal delay and the second temporal delay.