Patent ID: 11871552
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A memory device comprising:
an SRAM cell disposed on a substrate and including:
a first transistor;
a first Vss node component including a first conductive element on a first metallization layer;
a first via physically interfacing a bottom surface of the first metallization layer and coupling the first Vss node component and the first transistor, wherein the first via has an elongated shape having a length and a width, the length at least 1.5 times that of the width, wherein the length and width are measured on a plane parallel a top surface of the substrate;
an extended contact physically interfacing a bottom surface of the first via and extending to a source region of the first transistor;
a second Vss node component including a second conductive element on a second metallization layer, wherein a second via extends from the first conductive element to the second conductive element; and
a Vss line coupled to the second Vss node component by a third via extending from the second conductive element to the Vss line.