Patent ID: 11895832
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 16:
17. A memory integrated circuit, comprising:
a driving circuit, formed on a surface of a semiconductor substrate, and comprising sense amplifiers;
a first memory array and a second memory array, formed in a stack of interlayer dielectric layers lying over the semiconductor substrate, and are laterally spaced apart from each other at the same height, wherein each of the first and second memory arrays comprises:
memory cells, each comprising an access transistor and a storage capacitor;
bit lines, respectively coupled to a row of the memory cells; and
word lines, respectively coupled to a column of the memory cells; and

routing elements, formed in the stack of interlayer dielectric layers, and connecting the bit lines of the first and second memory arrays to input lines of the underlying sense amplifiers through portions of the interlayer dielectric layers extending in between the first and second memory arrays.