Patent ID: 11860786
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A system, comprising:
a first cache and a second cache; and
a logic circuit to control the first cache and the second cache based on a configurable data bit;
wherein when the configurable data bit is in a first state, the logic circuit is configured to:
implement commands received from a first command bus for accessing a memory system via the first cache, when an execution type is a non-speculative execution of instructions by a processor; and
implement commands received from the first command bus for accessing the memory system via the second cache, when the execution type is a speculative execution of instructions by the processor; and

wherein when the configurable data bit is in a second state, the logic circuit is configured to:
implement commands received from the first command bus for accessing the memory system via the second cache, when the execution type is the non-speculative execution of instructions by the processor; and
implement commands received from the first command bus for accessing the memory system via the first cache, when the execution type is the speculative execution of instructions by the processor.