Patent ID: 11928025
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. An apparatus, comprising:
a plurality of memory devices; and
a controller coupled to the plurality of memory devices via a plurality of respective channels, the controller configured to:
read, in response to a read command to access host data, the host data and first error correction code (ECC) data from a first memory device of the plurality of memory devices;
perform, using the first ECC data, a first error correction operation on the host data to correct a quantity of errors not exceeding a threshold quantity;
perform an error detection operation on the host data using cyclic redundancy check (CRC);
read, from a second memory device of the plurality of memory devices, second ECC data different than the first ECC data; and
to perform a second error correction operation using the second ECC data on the host data to correct a quantity of errors exceeding the threshold quantity and that were not correctable during the first error correction operation:
read other host data from a third memory device of the plurality of memory devices; and
perform an XOR operation among the other host data and the second ECC data to recover the host data.