Patent ID: 11950401
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G  B | IPC H

Claim 19:
20. The semiconductor structure of claim 17, wherein:
the write port of the first TP SRAM cell further includes a first Vdd conductor, a first write bit line bar (W_BLB), and a second W_WL landing pad,
the read port of the first TP SRAM cell includes a second Vss conductor and a first read bit line (R_BL),
the write port of the second TP SRAM cell further includes a second Vdd conductor, a second W_BLB, and a third W_WL landing pad,
the read port of the second TP SRAM cell includes a third Vss conductor and a second R_BL, and
the first and second Vdd conductors, the first and second W_BLB, the second and third W_WL landing pads, and the first and second R_BL are all located at the M1 layer.