Patent ID: 11966633
Assignee: CADENCE DESIGN SYSTEMS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. The system of claim 16, wherein:
the read command includes executing a first number of non-operations and a first value defining a number of clock cycles that are needed to read from one address of the NVM module, and the first value being based on an argument of a high constraint defined in a read arc of the Liberty file and on a period of a fuse clock;
the write command includes executing a second number of non-operations, and a second value defining a number of clock cycles that are needed to write to one address of the NVM module, and the second value being based on an argument of a high constraint defined in a program arc of the Liberty file and on the period of the fuse clock; and
the first number of non-operations and the second number of non-operations are based on the period of the fuse clock.