Patent ID: 11861223
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A memory controller, comprising:
a command storage including a first read command queue, a second read command queue, and a third read command queue, wherein the first read command queue is configured to store a first physical address and a first read command instructing a memory device to perform a read operation while a background operation is performed, and wherein the first physical address corresponds to a first plane number, a first block number, and a first page number;
a command generation controller coupled to the command storage and configured to translate, to a second physical address, a logical address and generate a second read command instructing the memory device to read data stored in the memory device, in response to a read request provided while the background operation is performed, and store the second read command and the second physical address in the second read command queue, wherein the second physical address corresponds to a second plane number, a second block number, and a second page number; and
a command schedule controller coupled to the command storage and configured to schedule the first physical address, the second physical address, and the second read command in the third read command queue according to whether the first page number equals the second page number.