Patent ID: 11887648
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 17:
18. The semiconductor memory device of claim 17, wherein the charge trap layer comprises a material having trap site density and permittivity higher than those of a material included in the gate insulating layer, and
the common source semiconductor layer comprises:
a cell source layer comprising an upper surface in contact with a lower surface of the channel layer in each of the plurality of channel holes; and
a base source layer connecting one of the cell source layers to an other one of the cell source layers next to the one of the cell source layers, the base source layer arranged between a lowermost insulating layer of the plurality of insulating layers and the etch stop layer, and having an upper surface at a vertical level lower than that of the upper surface of the cell source layer.