Patent ID: 11942183
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. A method, comprising:
performing one or more first write operations on a memory array according to a first pulse magnitude and a first pulse duration;
identifying that a quantity of access operations performed on the memory array satisfies a threshold; and
performing, based at least in part on identifying that the quantity of access operations performed on the memory array satisfies the threshold, one or more second write operations on the memory array according to a second pulse magnitude and a second pulse duration, wherein performing the one or more second write operations comprises applying, to a first target memory cell to write a first logic state, a first voltage having a first polarity, and applying, to a second target memory cell to write a second logic state, a second voltage having a second polarity.