Patent ID: 11868642
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A method comprising:
receiving, by a processing device, a trim command with respect to a memory device, wherein the trim command references a first range of logical block addresses (LBA);
identifying a second range of LBAs corresponding to one or more management units (MUs) of a group of memory cells;
updating a data structure associated with the group of memory cells to reference the trim command;
receiving a memory access command with respect to the group of memory cells;
responsive to determining that the data structure associated with the group of memory cells references the request the trim command, blocking the memory access command;
responsive to determining that the first range of LBAs referenced by the trim command does not include each LBA of the second range of LBAs corresponding to the one or more MUs of the group of memory cells, performing, on the group of memory cells, a trim operation specified by the trim command;
updating the data structure to indicate the completion of the trim operation; and
responsive to determining that the data structure indicates the completion of the trim operation, performing a memory access operation specified by the memory access command.