Patent ID: 11924008
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Digital communication (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 3:
4. The compensation circuit of claim 1, further comprising:
a pattern table configured to store the first pattern stream,
wherein the data analyzer is further configured to:
receive a second bit stream including (N+1)-th to 2N-th bits,
count a number of times of coincidence of each of the first to 2M-th patterns from the second bit stream, and to
generate a second pattern stream including (2M+1)-th to 2M+1-th count values, each count value of the (2M+1)-th to 2M+1-th count values corresponding to a number of times of coincidence of a corresponding pattern of the first to 2M-th patterns,
wherein the pattern table is further configured to store the second pattern stream and to generate an accumulated pattern stream including first to 2M-th accumulated count values based on the first and second pattern streams, and
wherein the compensation calculator is further configured to determine (2M+1)-th to 2M+1-th compensation values based on the accumulated pattern stream.