Patent ID: 11897539
Assignee: SEIKO EPSON CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC B  G  H | IPC B  G  H

Claim 0:
1. A circuit device comprising:
an integration period signal generation circuit configured to generate a first integration period signal which turns to an active state at a transition of a first signal, and is kept in the active state in a first integration period having a predetermined period length longer than a period of a reference clock signal;
a polarity switching signal generation circuit configured to generate a first integration polarity switching signal making a transition of a voltage level at a timing synchronized with the reference clock signal in the first integration period, and a second integration polarity switching signal making a transition of a voltage level a predetermined clock count of the reference clock signal after a transition timing of the first integration polarity switching signal in the first integration period;
a first integration circuit configured to perform a first integrating process in which an integration polarity is switched at a transition timing of the first integration polarity switching signal in the first integration period; and
a second integration circuit configured to perform a second integrating process in which an integration polarity is switched at a transition timing of the second integration polarity switching signal in the first integration period.