Patent ID: 11936927
Assignee: REALTEK SEMICONDUCTOR CORPORATION
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 12:
13. The receiver control circuit of claim 11, wherein the signal combination circuit comprises:
a multiplexer, coupled to the first input terminal and the second input terminal, and configured to receive the first input signal and the second input signal; and
a receiver counting circuit, configured to control, according to a vertical synchronization signal and a data enable signal, the multiplexer to provide one of the first input signal and the second input signal as the control signal to the display module, wherein an interval between two adjacent pulses of the vertical synchronization signal is a length of the video frame, and each pulse of the data enable signal is configured to control the display module to update a corresponding row of pixels of the display module.