Patent ID: 11900221
Assignee: AMAZON TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A system comprising:
quantum hardware configured to store logical data in data qubits of topological codes and perform quantum computations on the logical data stored in the topological codes via lattice surgery;
a memory storing program instructions for correcting errors for the quantum computations performed via lattice surgery; and
one or more processors, wherein the program instruction, when executed on or across, the one or more processors, cause the one or more processors to:
correct errors for the logical data stored in the topological codes via an error correcting code applied to repeated syndrome measurements of the topological codes; and
correct errors in logical multi-qubit Pauli measurements performed in relation to a lattice surgery operation,
wherein said correcting the errors in the logical multi-qubit Pauli measurements comprises:
correcting a wrong parity measurement for a tensor product of Pauli measurements for parity vertices, wherein parity vertices correspond to qubits in a region that connects two or more topological codes upon which a lattice surgery operation is being performed.