Patent ID: 11962308
Assignee: M31 TECHNOLOGY CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A successive-approximation register (SAR) analog-to-digital converter (ADC) circuit, comprising:
a comparator circuit, configured to compare an analog signal with a plurality of reference levels; and
a plurality of latch circuits, coupled to the comparator circuit and connected in series, the latch circuits being triggered sequentially in response to a plurality of trigger signals, respectively, to store a comparator output of the comparator circuit and accordingly generate a digital signal, wherein a first latch circuit and a second latch circuit of the latch circuits are triggered in response to a first trigger signal and a second trigger signal of the trigger signals, respectively; the first latch circuit is configured to generate the second trigger signal according to the comparator output stored in the first latch circuit;
wherein the first latch circuit comprises a first circuit terminal and a first set of input terminals different from the first circuit terminal, the first circuit terminal is arranged to receive the first trigger signal, and the first set of input terminals is coupled to the comparator output of the comparator circuit; the second latch circuit comprises a second circuit terminal and a second set of input terminals different from the second circuit terminal, the second circuit terminal is arranged to receive the second trigger signal outputted from the first latch circuit; and the second set of input terminals is coupled to the comparator output of the comparator circuit.