Patent ID: 11860812
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. A method for performing link training for one or more input/output links interconnecting an upstream port with a downstream port, the method comprising:
performing an initialization sequence of the one or more input/output links between the upstream port and the downstream port, the initialization sequence comprising link training the one or more input/output links;
determining equalization parameter values for the upstream port and downstream port for a plurality of data rates, the plurality of data rates comprising a first data rate and a second data rate;
storing one or more equalization parameter values for the upstream port and the downstream port in a nonvolatile memory for each of the plurality of data rates;
operating the one or more input/output links at the first data rate;
determining that the input/output link is to change from the first data rate to the second data rate;
determining that the upstream port and the downstream port support equalization bypass from information in a training set;
retrieving the stored equalization parameter values for the second data rate for the downstream port from the nonvolatile memory;
writing the stored equalization parameter values for the downstream port to a register associated with the downstream port; and
using the equalization parameter values as equalization parameters for the downstream port for operating the one or more links interconnecting the upstream port with the downstream port.