Patent ID: 11869955
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 7:
8. A method, comprising:
forming a plurality of first semiconductor nanosheets corresponding to channel regions of a first gate all around transistor;
forming a plurality of second semiconductor nanosheets corresponding to channel regions of a second gate all around transistor;
depositing an interfacial dielectric layer on the first and second semiconductor nanosheets;
depositing a high-K dielectric layer on the interfacial dielectric layer;
depositing a cap layer on the high-K dielectric layer;
removing the cap layer from the high-K dielectric layer on the second semiconductor nanosheets; and
diffusing metal atoms from the cap layer into the interfacial dielectric layer on the first semiconductor nanosheets by performing a thermal annealing process after removing the cap layer from the high-K dielectric layer on the second semiconductor nanosheets.