Patent ID: 11900875
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. The display substrate according to claim 4, wherein when the first connecting portion is a metal electrode and the second connecting portion is a transparent electrode, the drive structure layer comprises: a first insulating layer, a semiconductor layer, a second insulating layer, a first metal layer, a third insulating layer, a second metal layer, a fourth insulating layer, a third metal layer, a fifth insulating layer, a first planarization layer, a fourth metal layer, a second planarization layer, a fifth metal layer, a transparent conductive layer, and a third planarization layer that are sequentially stacked on the substrate;
the semiconductor layer comprises: active layers of multiple pixel transistors, active layers of multiple blank transistors, active layers of multiple scan transistors, and active layers of multiple light-emitting transistors; the first metal layer comprises: a light-emitting signal line, a scanning signal line, a reset signal line, a first plate of a first pixel capacitor, a second plate of a first scanning capacitor, a second plate of a second scanning capacitor, a first plate of a first light-emitting capacitor, a first plate of a second light-emitting capacitor, a second plate of a third light-emitting capacitor, control electrodes of the multiple pixel transistors, control electrodes of the multiple blank transistors, control electrodes of the multiple scan transistors, and control electrodes of multiple light-emitting transistors; the second metal layer comprises: an initial signal line, a second plate of the first pixel capacitor, a first plate of the first scanning capacitor, a first plate of the second scanning capacitor, a second plate of the first light-emitting capacitor, a second plate of the second light-emitting capacitor, and a first plate of the third light-emitting capacitor; the third metal layer comprises: a third power line, a fourth power line, a first scanning clock signal line, a second scanning clock signal line, a first light-emitting clock signal line, a second light-emitting clock signal line, a scanning initial signal line, a light-emitting initial signal line, first and second electrodes of the multiple pixel transistors, first and second electrodes of the multiple blank transistors, first and second electrodes of the multiple scan transistors, and first and second electrodes of the multiple light-emitting transistors; the fourth metal layer comprises: a data signal line and a first power line; the fifth metal layer comprises: the first connecting portion, and the transparent conductive layer comprises: the second connecting portion; and
an orthographic projection of the first power line on the substrate at least partially overlaps with an orthographic projection of the first pixel capacitor on the substrate.