Patent ID: 11862264
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. The memory circuit of claim 9, wherein the latch comprises:
a first NAND logic gate comprising a first input terminal, a second input terminal and a first output terminal, the first input terminal of the first NAND logic gate being coupled to the first sense amplifier, and being configured to receive the first output signal, and the first output terminal of the first NAND logic gate being configured to output a first NAND output signal; and
a second NAND logic gate comprising a first input terminal, a second input terminal and a first output terminal, the first input terminal of the second NAND logic gate being coupled to the second sense amplifier, and being configured to receive the second output signal, and the first output terminal of the second NAND logic gate being configured to output a second NAND output signal,
wherein the second input terminal of the first NAND logic gate is coupled to the first output terminal of the second NAND logic gate, and is configured to receive the second NAND output signal, and
the second input terminal of the second NAND logic gate is coupled to the first output terminal of the first NAND logic gate, and is configured to receive the first NAND output signal.