Patent ID: 11960810
Assignee: REALTEK SEMICONDUCTOR CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. A layout design system, comprising:
at least one memory circuit configured to store at least one program code, a temperature threshold value, and application data; and
at least one processor circuit configured to perform the at least one program code to:
select a plurality of first layout patterns and a plurality of second layout patterns according to the application data, wherein the plurality of first layout patterns correspond to a plurality of first circuits in a first circuitry, and the plurality of second layout patterns correspond to a plurality of second circuits in a second circuitry;
alternately arrange at least one of the plurality of first layout patterns and at least one of the plurality of second layout patterns, in order to generate first layout data corresponding to a chip;
determine whether an operating temperature of the chip is lower than the temperature threshold value according to the first layout data; and
if the operating temperature is lower than the temperature threshold value, output the first layout data, in order to fabricate the chip according to the first layout data.