Patent ID: 11916561
Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 1:
2. The method of claim 1, wherein generating the interpolated clock signal further comprises:
weighting the even-numbered first-level clock signal by a first weighting factor to produce a weighted even-numbered first-level clock signal;
weighting the odd-numbered first-level clock signal by a second weighting factor to produce a weighted odd-numbered first-level clock signal;
adding the weighted even-numbered first-level clock signal and the weighted odd-numbered first-level clock signal in vector form, wherein adding the vector forms of the even-numbered first-level clock signal and odd-numbered first-level clock signal are generated via respective digital-to-analog converters.