Patent ID: 11914716
Assignee: LATTICE SEMICONDUCTOR CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 10:
11. A secure programmable logic device (PLD) asset management system, comprising:
an external system comprising a processor and a memory and configured to be coupled to a secure PLD through a configuration input/output (I/O) of the secure PLD, wherein the memory comprises machine-readable instructions which when executed by the processor of the external system are adapted to cause the external system to perform a computer-implemented method comprising:
providing a secure PLD asset unlock request, corresponding to a secure PLD asset, to the secure PLD over the configuration I/O;
providing one or more device keys and/or a configuration image for a PLD fabric of the secure PLD to the secure PLD over the configuration I/O; and
providing a secure PLD lock request, corresponding to the secure PLD asset, to the secure PLD over the configuration I/O.