Patent ID: 11948926
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 3:
4. The device of claim 1 further comprising:
a second memory device directly face-to-back bonded to the first memory die by metal-to-metal bonds and by dielectric-to-dielectric bonds, the metallization patterns of the first redistribution structure electrically coupled to the second memory device;
a second dielectric layer laterally surrounding the second memory device;
a third memory device directly face-to-back bonded to the second memory device by metal-to-metal bonds and by dielectric-to-dielectric bonds, the metallization patterns of the first redistribution structure electrically coupled to the third memory device; and
a third dielectric layer laterally surrounding the third memory device,
wherein the first redistribution structure contacts a back side of the third memory device.