Patent ID: 11908866
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A method comprising:
forming a gate opening that extends lengthwise along a first direction and widthwise along a second direction, wherein the gate opening extends along the first direction and exposes a first semiconductor channel for a first transistor, a second semiconductor channel for a second transistor, and a dielectric structure, wherein the dielectric structure is between the first semiconductor channel and the second semiconductor channel, the first semiconductor channel extends between first source/drains along the second direction, and the second semiconductor channel extends between second source/drains along the second direction;
depositing a gate dielectric layer over the first semiconductor channel, the second semiconductor channel, and the dielectric structure;
depositing a first p-type work function layer over the first semiconductor channel, the second semiconductor channel, and the dielectric structure;
depositing a second p-type work function layer over the first semiconductor channel, the second semiconductor channel, and the dielectric structure;
depositing a third p-type work function layer over the first semiconductor channel, the second semiconductor channel, and the dielectric structure;
depositing an n-type work function layer over the first semiconductor channel, the second semiconductor channel, and the dielectric structure;
wherein the first p-type work function layer is removed from over the first semiconductor channel before the depositing the second p-type work function layer;
wherein the second p-type work function layer is removed from over the first semiconductor channel and the second semiconductor channel before depositing the third p-type work function layer; and
wherein:
over the first semiconductor channel, the gate dielectric layer, the third p-type work function layer, and the n-type work function layer fill the gate opening along the second direction,
over the second semiconductor channel, the gate dielectric layer, the first p-type work function layer, the third p-type work function layer, and the n-type work function layer fill the gate opening along the second direction, and
over a portion of the dielectric structure, the gate dielectric layer, the first p-type work function layer, the second p-type work function layer, and the third p-type work function layer fill the gate opening along the second direction.