Patent ID: 11903181
Assignee: FUJIAN JINHUA INTEGRATED CIRCUIT CO., LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 8:
9. A semiconductor structure, comprising:
a substrate;
a first dielectric layer disposed on the substrate;
a second dielectric layer disposed on the first dielectric layer;
an opening having a lower portion through the first dielectric layer and an upper portion through the second dielectric layer, wherein a width of the upper portion is larger than a width of the lower portion;
a contact structure disposed in the lower portion of the opening;
a passivation layer covering a top surface of the contact structure and a sidewall of the second dielectric layer; and
a plurality of bit lines disposed on the memory region of the substrate; and
a plurality of storage node contacts disposed on the substrate and between the bit lines, wherein the top surface of the contact structure is lower than top surfaces of the storage node contacts.