Patent ID: 11962926
Assignee: ALPSENTEK, GMBH.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. The method of claim 15, wherein each pixel circuit is configured to generate the logarithmic output signal and the method further comprises:
connecting the drain of the first additional transistor (MVB) to the drain of the reset transistor (MRST) using the second additional transistor (MS2),
maintaining the third additional transistor (MS3) in an open state, and
connecting the drain of the reset transistor (MRST) and the gate of the reset transistor (MRST) using the fourth additional transistor (MS4),
maintaining the row select transistor (MSEL) in a closed state,
connecting the common column output to ground, and
for each pixel circuit connecting an output (vlg_out) between the first additional transistor (MVB) and the source follower transistor (MSF).