Patent ID: 11934270
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A method, comprising:
receiving a first write command to write a first user data block corresponding to a first channel coupled to one of a number of memory devices, wherein the first user data block is one of a first set of data blocks that is a unit of read access and whose data blocks are grouped together for an error correction operation;
receiving a second write command to write a second user data block corresponding to a second channel coupled to one of the number of memory devices, wherein the second user data block is one of a second set of data blocks that is a unit of read access and whose data blocks are grouped together for an error correction operation; and
responsive to the first and second write commands:
retrieving a first parity data block corresponding to a third channel and grouped with the first user data block;
updating the first parity data block based at least in part on the first user data block; and
writing the first user data block, the second user data block, and the updated first parity data block simultaneously to memory devices that are respectively coupled to the first, second, and third channels independently of other user data blocks grouped with the first parity data block or the first user data block.