Patent ID: 11934537
Assignee: INTEGRITY SECURITY SERVICES LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A system for validating a state of a second processing device comprising:
a first processing device including at least one first processor and a first memory, the first memory including computer-readable instructions that, when executed by the at least one first processor, cause the first processing device to perform first operations comprising:
obtaining a first copy of software from a repository, the first copy of the software including first computer instructions and first data for indicating a running state of a device;
sending a validation request including a random number seed, a first algorithm identifier corresponding to an algorithm for random number generation, a number of random numbers to generate, and a nonce;
generating a first set of random numbers using the random number seed according to the algorithm corresponding to the first algorithm identifier, a quantity of the random numbers in the generated first set of random numbers being equal to the number of random numbers to generate;
mapping, based on a mapping model, the generated first set of random numbers to a set of memory blocks, the set of mapped memory blocks each including a first computer instruction or the first data;
concatenating contents of the set of mapped memory blocks to the nonce;
calculating a first hash of the contents of the set of mapped memory blocks concatenated to the nonce;
receiving, from the second processing device, a second hash in response to the sending of the validation request, the second hash having been calculated by the second processing device using information included in the validation request, the mapping model, a copy of the software on the second processing device, and the nonce;
comparing the first hash to the second hash; and
automatically performing an action when the first hash and the second hash do not match.