Patent ID: 11908701
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 18:
19. A manufacturing method of a semiconductor device, comprising:
providing a substrate;
forming a metal-oxide-semiconductor (MOS) transistor over the substrate;
forming an etch stop layer over the MOS transistor;
depositing a dielectric layer over the etch stop layer;
forming a first opening in the dielectric layer to expose the etch stop layer;
selectively forming a passivation layer on the dielectric layer to cover a top surface of the dielectric layer and sidewalls of the first opening, wherein a portion of the exposed etch stop layer is uncovered by the passivation layer;
performing a first etching process to remove the portion of the exposed etch stop layer that is uncovered by the passivation layer to form a second opening in the etch stop layer;
performing a second etching process to remove the passivation layer; and
filling a conductive material into the first opening and the second opening to form a conductive contact.