Patent ID: 11961577
Assignee: NXP USA, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 19:
20. An integrated circuit including built-in self-test (BIST) circuitry which performs on-chip testing of analog-to-digital converters (ADCs), the ADCs including a set of sigma delta ADCs (SDADCs) and a set of successive approximation register ADCs (SARADCs), the integrated circuit comprising:
on-chip memory;
an N-bit differential digital-to-analog converter (DAC) used in performing the on-chip testing of the ADCs;
calibration circuitry coupled to the N-bit differential DAC and configured to generate a pair of calibration codes corresponding to each possible N-bit DAC input code for the N-bit differential DAC;
a memory engine, coupled to the calibration circuitry and the on-chip memory;
control circuitry configured to:
direct the memory engine and calibration circuitry to generate and store the pairs of calibration codes for each possible N-bit DAC input code for the N-bit differential DAC, wherein the memory engine is configured to store each pair of calibration codes in a memory line of the on-chip memory addressed by upper significant bits of a corresponding N-bit DAC input code, wherein, after generating and storing all pairs of calibration codes, each memory line includes multiple pairs of calibration codes,
direct testing of the set of SDADCs using the pairs of calibration codes stored in the on-chip memory and a full N-bit resolution of the DAC, and
subsequently to the testing of the set of SDADCs, direct testing of the set of SARADCs using pairs of calibration codes corresponding to a reduced M-bit resolution of the DAC, wherein M and N are positive integers and M is less than N, wherein during the testing of the set of SARADCs, memory engine is configured to overwrite a portion of the calibration codes stored in the on-chip memory.