Patent ID: 11862219
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A memory cell, comprising:
a write bit line;
a read word line;
a write transistor coupled between the write bit line and a first node;
a read transistor coupled to the write transistor by the first node, the read transistor comprising:
a ferroelectric layer;
a drain terminal of the read transistor directly connected to the read word line; and
a source terminal of the read transistor coupled to a second node;

wherein the write transistor is configured to set a stored data value of the memory cell by a write bit line signal that adjusts a polarization state of the read transistor, the polarization state corresponding to the stored data value.