Patent ID: 11899584
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 6:
7. A method comprising:
determining a cache hit ratio for a cache memory configured to cache at least part of data that is to be stored in a random access memory; and
setting an operating frequency of the random access memory based on the cache hit ratio for the cache memory,
wherein the setting of the operating frequency of the random access memory based on the cache hit ratio for the cache memory comprises:
determining a size of data in the random access memory that is accessed by a processor based on a size of data in the random access memory and the cache memory that is accessed by the processor and the cache hit ratio for the cache memory; and
setting the operating frequency of the random access memory based on the size of the data in the random access memory that is accessed by the processor.