Patent ID: 11923869
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 9:
10. The method of claim 9, wherein the support circuitry further includes a plurality of memory buffers, and
wherein dynamically mapping the plurality of LDPC engines to the plurality of FCs further includes:
dynamically allocating the memory operations that are stored in the priority queue to the plurality of LDPC engines,
performing parity checking and error correction on the memory operations that have been dynamically allocated to the plurality of LDPC engines,
storing the memory operations that have been parity checked and error corrected in the plurality of memory buffers, each memory buffer corresponding to one of the plurality of FCs,
retrieving, with the each of the plurality of FCs, a memory operation that is stored in one of the plurality of memory buffers, and
performing, with the each of the plurality of FCs, the memory operation at the corresponding one of the plurality of memory dies.