Patent ID: 11879938
Assignee: NAGRAVISION SàRL
Field: Measurement (Instruments)
Classification: CPC G  H | IPC G

Claim 0:
1. A method for detecting perturbations in a logic circuit for processing data operations along a plurality of datapaths coordinated by a clock signal, at least one datapath having an operating propagation delay, said logic circuit further comprising at least one test circuit having a programmable length datapath for varying a test propagation delay, said at least one test circuit comprising first registers to be loaded with inputs, to be processed by a function configured to calculate a Boolean result from a computation using two operands to provide an output at an instant depending on the programmable length datapath, and an error generator for providing an error in case that the output is different than an expected output provided by the function for said inputs, wherein the expected outputs are stored in second registers and one of the first registers is connected to the programmable length datapath, and
said at least one test circuit being configured to operate in two modes, a calibration mode and a detection mode, so as repeatedly switching between said calibration and detection modes, said calibration mode comprising:
determining a critical propagation delay by varying the programmable length datapath until the error generator outputs an error,
adjusting the programmable length datapath to include therein a tolerance delay,
switching into detection mode,

said detection mode comprising:
detecting a perturbation in the logic circuit along the programmable length datapath in case the error generator outputs an error,

the method comprising:
entering into the calibration mode and executing the steps of the calibration mode;
entering into the detection mode and executing the steps of the detection mode; and
detecting the perturbation as the result of the detection mode.