Patent ID: 11942469
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. An integrated circuit comprising:
a first-type active-region structure and a second-type active-region structure extending in a first direction on a substrate;
a front-side first-layer conducting line in a first connection layer above the substrate;
a plurality of gate-conductors extending in a second direction below the first connection layer, and wherein two adjacent gate-conductors are separated by a pitch distance equal to a contacted poly pitch (“CPP”);
a circuit cell having a first vertical boundary and a second vertical boundary extending in the second direction perpendicular to the first direction, wherein each of the first vertical boundary and the second vertical boundary crosses at least one boundary isolation region, and wherein a distance between the first vertical boundary and the second vertical boundary along the first direction is less than or equal to three CPPs;
a backside horizontal conducting line extending in the first direction in a backside first conducting layer below the substrate, wherein the backside horizontal conducting line extends across the first vertical boundary of the circuit cell;
a backside vertical conducting line extending in the second direction in a backside second conducting layer below the backside first conducting layer, wherein the backside vertical conducting line is aligned with the first vertical boundary; and
a pin-connector for the circuit cell directly connected between the backside horizontal conducting line and the backside vertical conducting line.