Patent ID: 11934666
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device, comprising:
a memory array including a plurality of memory cells; and
a controller coupled to the memory array, the controller configured to:
determine a target profile including distribution targets, wherein each of the distribution targets represents a target distribution of program-verify levels for a logic value,
determine a feedback measure based on for processing data stored in the memory array, wherein the feedback measure represents a separation between adjacent distributions,
wherein the controller is further configured to determine the feedback measure based on error counts associated with a set of read-level voltages,
wherein the feedback measure is calculated based on a difference in a first error count and a second error count corresponding to different read-level voltages, and

dynamically adjust the target distribution of program-verify levels according to the feedback measure.