Patent ID: 11972130
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. An apparatus, comprising:
a processing device configured to:
determine that a ratio of invalid data portions of a block of memory cells meets an invalid data portion criterion;
cause, while refraining from causing performance of an operation involving a physical-to-logical mapping data structure or a logical-to-physical mapping data structure, or both, performance of a first media management operation to consolidate a quantity of valid data portions and a quantity of invalid data portions within the block of memory cells in response to determining that the invalid data portion criterion is met; and
cause performance of a second media management operation to consolidate the quantity of valid data portions within the block of memory cells or a quantity of invalid data portions within the block of memory cells, or both, in response to determining that the invalid data portion criterion is not met.