Patent ID: 11942390
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 7:
8. A method comprising:
forming a device layer on a semiconductor substrate, the device layer comprising a transistor;
forming a first interconnect structure over the device layer;
forming a second interconnect structure on an opposite side of the device layer as the first interconnect structure, wherein forming the second interconnect structure comprises:
depositing a first dielectric layer on a backside of the transistor;
forming a conductive line over the first dielectric layer and electrically connected to a source/drain region of the transistor; and
forming one or more layers of conductive features over the conductive line, wherein the one or more layers of conductive features comprises a dummy via thermally connected to the conductive line.