Patent ID: 11935592
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. An operating method of a resistive memory device, the operating method comprising:
receiving a write command for writing target data in a resistive memory cell connected between a first bit line and a first source line from a memory controller;
generating a write current in accordance with the write command;
activating a word line in the resistive memory cell by outputting a word line driving voltage from a level shifter connected to the word line, the word line driving voltage being higher than a power supply voltage of the resistive memory device;
receiving the write current and comparing previous data written in the resistive memory cell with the target data by comparing a voltage of the first source line with a voltage of a second source line or comparing a voltage of the first bit line with a voltage of a second bit line;
determining whether the target data is written in the resistive memory cell in accordance with a result of comparing the previous data with the target data;
outputting control signals to a pair of word line drivers connected to the memory cell; and
controlling at least one control signal of the control signals, the at least one control signal being output to a word line driver of the pair of word line drivers, the at least one control signal being controlled by a boosted capacitor configured to compensate for a variable resistance in the resistive memory cell,
wherein the second source line is a source line of a reference cell including a reference resistor and the second bit line is a bit line of the reference cell.