Patent ID: 11899532
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. A non-transitory, computer-readable medium storing code comprising instructions which, when executed by one or more processors of an electronic device, cause the electronic device to:
receive an indication of a timeout duration for a boot sequence of a host system;
determine an expected error rate for a set of memory cells of a plurality of memory cells based at least in part on a measured error rate for the set of memory cells, properties of a set of access lines corresponding to the set of memory cells, a sensing window of the set of memory cells, or any combination thereof;
select, based at least in part on the timeout duration, the set of memory cells based at least in part on the expected error rate of the set of memory cells being less than an error threshold;
store information for the boot sequence in the set of memory cells based at least in part on selecting the set of memory cells; and
access the information for the boot sequence that is stored in the set of memory cells based at least in part on an initialization of the boot sequence.