Patent ID: 11953988
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 7:
8. An apparatus, comprising:
an array of memory cells of a memory device that each comprise capacitive storage elements;
an interface configured to receive a read command from a host device external to the memory device;
a first circuit configured to read first data and an error control code corresponding to the first data from the array to a second circuit via a first data path and to a buffer via a second data path which bypasses the second circuit based at least in part on the read command; and
the second circuit coupled with the first circuit and configured to identify an error in the first data based at least in part on performing an error correction operation on the first data using the error control code,
wherein the interface is further configured to:
communicate, to the host device via the buffer, the first data corresponding to the error control code and comprising the error concurrent with the second circuit performing at least a portion of the error correction operation using the error control code; and
communicate, to the host device, an indicator of the error based at least in part on the error correction operation identifying the error in the first data.