Patent ID: 11901422
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A semiconductor device, comprising:
a substrate;
a first fin-type active pattern and a second fin-type active pattern, extended on the substrate in a first direction;
a first gate structure and a second gate structure extended on the substrate in a second direction different from the first direction, the first gate structure and the second gate structure intersecting the first fin-type active pattern and the second fin-type active pattern, respectively;
a first active area in the first fin-type active pattern, the first active area being adjacent to the first gate structure and serving as a first source/drain region;
a second active area in the second fin-type active pattern, the second active area being adjacent to the second gate structure and serving as a second source/drain region;
a third gate structure extended in the second direction between the first active area and the second active area;
an insulating layer on the substrate, the insulating layer covering the first fin-type active pattern, the second fin-type active pattern, and the first to third gate structures;
a shared contact plug penetrating through the insulating layer, the shared contact plug including:
a first lower portion and a second lower portion connected to the first active area and the second active area, respectively,
a third lower portion on the third gate structure, and
an upper portion connecting upper surfaces of the first to third lower portions;

a first silicon nitride film between the first lower portion and the third lower portion, the first silicon nitride film surrounding a sidewall of the first lower portion; and
a second silicon nitride film between the second lower portion and the third lower portion, the second silicon nitride film surrounding a sidewall of the second lower portion,
wherein the insulating layer includes a first portion between the first lower portion and the third lower portion, and a second portion between the second lower portion and the third lower portion,
wherein a bottom of the third lower portion has a flat area and is at a level higher than bottoms of the first and second lower portions, and
wherein the first and second silicon nitride films are only on sidewalls of the first and second lower portions, respectively, among all surfaces of each of the first and second lower portions, bottoms of the first and second lower portions being directly connected to the first and second source/drain regions, respectively.