Patent ID: 11967960
Assignee: ADVANCED MICRO DEVICES, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. An integrated circuit comprising:
a first-in first-out buffer (FIFO);
a memory controller configured to operate in a first clock domain and coupled to the FIFO, the first clock domain associated with a first clock signal;
a data fabric configured to operate in a second clock domain and coupled to the FIFO, the second clock domain associated with a second clock signal, a second frequency of the second clock signal being different from a first frequency of the first clock signal; and
a controller coupled to the FIFO and configured to:
generate a first offset based on a phase relationship between the first clock signal and the second clock signal, the first clock signal, and the second clock signal; and
send a first heads-up signal, based upon the first offset, to the memory controller.