Patent ID: 11868193
Assignee: MARVELL ASIA PTE LTD
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 6:
7. A system comprising:
a means for determining a half cycle of a clocking signal to determine a droop event;
a means for receiving a signal indicating whether a droop event has occurred;
a means for receiving the clocking signal;
a means for delaying the clocking signal by a first delay amount to form a first delayed clocking signal;
a means for outputting the first delayed clocking signal;
a means for receiving the first delayed clocking signal;
a means for delaying the first delayed clocking signal by a second delay amount to form a second delayed clocking signal; and
in response to receiving the signal indicating that the droop event has occurred, a means for selectively selecting rising edges and falling edges from the clocking signal, the first delayed clocking signal, and the second delayed clocking signal, wherein a selection of a rising edge or a falling edge from at least one of the first delayed clocking signal, the second delayed clocking signal, and the clocking signal is skipped to form a modified clocking signal,
wherein a first delay amount is programmable, and wherein the first delay amount is different from the second delay amount.