Patent ID: 11930696
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method comprising:
depositing an isolation layer over a substrate;
depositing an etch stop layer over the isolation layer;
depositing a dielectric layer over the etch stop layer;
forming carbon nanotubes on the dielectric layer;
forming a dummy gate stack on the carbon nanotubes;
forming gate spacers on opposing sides of the dummy gate stack;
removing the dummy gate stack to form a trench between the gate spacers, wherein the carbon nanotubes are exposed to the trench;
etching a portion of the dielectric layer underlying the carbon nanotubes, wherein the etching the portion of the dielectric layer is stopped on the etch stop layer, and wherein the carbon nanotubes are suspended;
forming a replacement gate dielectric surrounding the carbon nanotubes; and
forming a gate electrode surrounding the replacement gate dielectric.