Patent ID: 11940940
Assignee: GRAPHCORE LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 13:
14. A method implemented in a data processing device, the method comprising:
storing a first local program in a first processor and a second local program in a second processor, the first local program and second local program together providing at least part of a computer program,
transporting via a plurality of buses of a switching fabric, egress data packets that are output by the first processor and the second processor;
in dependence upon a schedule indicated in the first local program, sending a first message to a first of a plurality of interface circuits associated with a first of a plurality of interfaces of the data processing device, the first message identifying the second processor;
during a first phase of execution of the computer program, and in response to receipt of the first message, controlling switching circuitry associated with the first of the interfaces to connect to a first one of the buses so as to enable reception, at the first of the interfaces, of a first set of the egress data packets from the second processor, wherein the second processor is associated with the first one of the buses;
in dependence upon the schedule or a different schedule indicated in a further local program, sending a second message to a second of the interface circuits associated with a second of the plurality of interfaces, the second message identifying the second processor;
during a second phase of execution of the computer program, and in response to receipt of the second message, controlling switching circuitry associated with the second of the interfaces to connect to the first one of the buses so as to enable reception, at the second of the interfaces, of a second set of the egress data packets from the second processor,
wherein the first phase of execution and second phase of execution are exchange phases, wherein the plurality of processors are configured to alternate between operation in compute phases and the exchange phases, the compute phases and the exchange phases being separated by barrier synchronisations enforced between at least some of the processors.