Patent ID: 11955159
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 7:
8. The semiconductor memory device of claim 1, wherein the row hammer management circuit includes:
a counter configured to count a timing interval between the active command and a precharge command to output an interval counting value;
an adder configured to add the read count data from the target memory cell row and the interval counting value to output the updated count data;
a comparator configured to compare the read count data with the predetermined reference number of times to output a comparison signal; and
a hammer address queue configured to:
store a target access address designating the target memory cell row in response to the comparison signal indicating that the read count data is equal to or greater than the predetermined reference number of times, and
provide the refresh control circuit with the target access address as the hammer address.