Patent ID: 11887901
Assignee: SILICON WORKS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 16:
17. The test apparatus of claim 15, wherein
each of the plurality of external resistor circuits includes:
an external resistor structure including at least one of a diffusion layer, a polysilicon layer, and a wiring layer that are disposed in the outer region of the chip,
an external transistor, and
a test pad connected to the external transistor through the external resistor structure and disposed in a chip pad region, and

the external transistor includes:
a gate electrode configured to receive a first power signal from an internal circuit of the chip,
a first source or drain electrode configured to receive a second power signal lower than the first power signal from the internal circuit of the chip, and
a second source or drain electrode configured to receive an external power signal applied to the test pad through the external resistor structure.