Patent ID: 11922169
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. A method for performing a refactored multiply-and-accumulate operation, comprising:
generating, in a summing array including a plurality of non-volatile memory elements arranged in columns, a summed signal for each column based, at least in part, on a plurality of input signals, each non-volatile memory element in the summing array being programmed to a high resistance state or a low resistance state based on weights of a neural network; and
generating, in a multiplying array including a plurality of non-volatile memory elements, an output signal based, at least in part, on the summed signals from the summing array, each non-volatile memory element in the multiplying array being programmed to a different conductance level based on the weights of the neural network.