Patent ID: 11862264
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory circuit comprising:
a non-volatile memory cell;
a sense amplifier coupled to the non-volatile memory cell, and configured to generate a first output signal, the sense amplifier comprising:
a comparator comprising a first input terminal, a second input terminal and a first output terminal, the first input terminal being coupled to the non-volatile memory cell by a first node, and being configured to receive a first voltage, the second input terminal being configured to receive a second voltage, the first output terminal being configured to output the first output signal; and

a detection circuit coupled to the sense amplifier and the non-volatile memory cell, the detection circuit configured to latch the first output signal and disrupt a current path between the non-volatile memory cell and the sense amplifier, the detection circuit comprising:
a first inverter comprising a first input terminal of the first inverter coupled to the first output terminal of the comparator and configured to receive the first output signal, and a first output terminal of the first inverter configured to generate an inverted first output signal.