Patent ID: 11898916
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 15:
16. A semiconductor device comprising:
a plurality of active area structures;
a first active device and a second active device including portions of the plurality of active area structures, wherein the first active device and the second active device are arranged in a cascode configuration;
a first dummy gate layer;
a second dummy gate layer, wherein the first dummy gate layer and the second dummy gate layer are positioned between the first active device and the second active device; and
a metal layer overlying the plurality of active area structures and positioned between the first dummy gate layer and the second dummy gate layer, wherein the metal layer is configured to measure, due to a change of resistance in the metal layer, a temperature of the plurality of active area structures.