Patent ID: 11909396
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 16:
17. A method, comprising:
forming a plurality of first conductive lines in a first layer on a back side of an integrated circuit to transmit a first clock signal and a second clock signal inverted from the first clock signal;
forming a plurality of second conductive lines in a second layer, below the first layer, on the back side of the integrated circuit to transmit the first clock signal and the second clock signal between the plurality of first conductive lines, wherein the first layer is disposed between the second layer on the back side and a front side of the integrated circuit; and
forming a plurality of third conductive lines extending parallel to the plurality of second conductive lines in the second layer on the back side of the integrated circuit to transmit a first supply voltage, wherein the plurality of first conductive lines and the plurality of second conductive lines are interposed between the plurality of third conductive lines.