Patent ID: 11972951
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A semiconductor device, comprising:
a substrate;
a fin structure disposed on the substrate;
a source/drain (S/D) region disposed on a first portion of the fin structure;
a gate structure with a gate electrode layer disposed on a second portion of the fin structure;
a silicide layer disposed on the S/D region, wherein a top surface of the silicide layer is vertically higher than a bottom surface of the gate electrode layer, and wherein a bottom surface of the silicide layer is vertically lower than the bottom surface of the gate electrode layer; and
a nitride layer disposed on the silicide layer,
wherein sidewalls of the S/D region, the silicide layer, and the nitride layer are aligned with respect to each other.