Patent ID: 11880741
Assignee: D-WAVE SYSTEMS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. A hybrid computing system, comprising:
an analog processor into which a problem is embeddable, the problem representable as a problem graph and the analog processor representable as a hardware graph comprising chains of qubits communicatively coupled by couplers;
a digital processor in communication with the analog processor, wherein in operation the digital processor:
embeds the problem graph into the hardware graph of the analog processor to produce an embedded problem graph, the embedded problem graph containing at least one chain;
determines via the digital processor whether the at least one chain in the embedded problem graph is broken;
if the at least one chain is broken, determines via the digital processor a location of a break in the at least one chain; and
increases respective coupling strengths of one or more of the couplers in the analog processor at the location of the break by finding an upper-bound on a required chain strength by verifying that for each chain C of the embedded problem −J(e)>b(C, e) is respected for each edge e in C, wherein b(C, e) is defined as b(C, e):=min{b(C1(e)), b(C2(e))} and b(C):=ΣvϵC|h(v)|+ΣvϵCΣuϵUv|J(v, u)| and J(e) is the coupling strength applied to edge e.