Patent ID: 11862058
Assignee: LAPIS TECHNOLOGY CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 10:
11. The load driving circuit as claimed in claim 8,
wherein the output amplifier has an output end to which the load is connected,
in the first output-stage transistor of the output amplifier, a source receives the first power potential, a drain is connected to the output end, and in the second output-stage transistor, a source receives the first reference potential, and a drain is connected to the output end,
wherein the detection circuit comprises:
a first mirror current generation transistor, wherein a source receives the first power potential, a gate is connected to a gate of the first output-stage transistor, and a drain is connected to a third node;
a second mirror current generation transistor, wherein a source receives the first reference potential, a gate is connected to a gate of the second output-stage transistor, and a drain is connected to a fourth node;
a first folding transistor, wherein a source receives the second power potential, and a gate and a drain are connected to the fourth node; and
a second folding transistor, wherein a source receives the second reference potential, and a gate and a drain are connected to the third node,
the coupling circuit comprises:
a first transistor, generating the first current;
a second transistor, generating the second current;
a third transistor, generating the third current; and
a fourth transistor, generating the fourth current,
wherein in the first transistor, a source receives the second power potential, a gate is connected to the fourth node, and a drain is connected to the first output node,
in the second transistor, a source receives the second power potential, a gate is connected to the fourth node, and a drain is connected to the second output node,
in the third transistor, a source receives the second reference potential, a gate is connected to the third node, and a drain is connected to the first output node, and
in the fourth transistor, a source receives the second reference potential, a gate is connected to the third node, and a drain is connected to the second output node.