Patent ID: 11888479
Assignee: KEPLER COMPUTING INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 15:
16. A system comprising:
a processor circuitry to execute one or more instructions;
a communication interface communicatively coupled to the processor circuitry; and
a memory coupled to the processor circuitry, wherein the processor circuitry comprises a multiplier circuitry which includes:
a majority gate or a minority gate having non-linear polar material, wherein the majority gate or the minority gate is coupled to a NOR gate or a NAND gate; and
a reset mechanism to a reset a set of nodes coupled to the non-linear polar material during a reset phase separate from an evaluation phase, wherein a node from the set of nodes is coupled to the NOR gate or the NAND gate, and wherein the NOR gate or the NAND gate is controllable by the reset mechanism.