Patent ID: 11876127
Assignee: RENESAS ELECTRONICS CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A method of manufacturing a semiconductor device comprising:
a step of preparing a silicon substrate including an n-type emitter layer, a p-type base layer, a trench gate, a trench emitter, a p-type floating layer, an n-type hole barrier layer, a gate electrode and an emitter electrode that are formed in a region of its first main surface;
a first step of forming a p-type collector layer on a second main surface facing the first main surface of the silicon substrate;
a second step of forming a first dislocation suppressing layer inside the p-type collector layer, the first dislocation suppressing layer forming a hetero junction with the silicon substrate;
a third step of forming an n-type field stop layer on the p-type collector layer in the region of the first main surface; and
a fourth step of forming a collector electrode connected to the p-type collector layer.