Patent ID: 11955183
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. A non-volatile memory, comprising:
a memory cell region extending in a first horizontal direction and bounded on a first end by a first word line cut and bounded on a second end opposite the first end by a second word line cut;
a plurality of inner memory cell strings including first memory cells of the memory cell region that are connected to a plurality of inner pillars extending vertically upward through an inner region of the memory cell region;
a plurality of outer memory cell strings including second memory cells of the memory cell region that are connected to a plurality of outer pillars extending vertically upward through an outer region of the memory cell region, the outer region being adjacent to the first and second word line cuts than the inner region;
a plurality of first bit lines connected to the inner pillars and extending in a second horizontal direction crossing the first horizontal direction;
a plurality of second bit lines connected to the outer pillars and extending in the second horizontal direction;
a first page buffer circuit connected to the first bit lines and including a first latch storing data on the first memory cells based on a first read level voltage and a second latch storing data on the first memory cells based on a second read level voltage different from the first read level voltage; and
a second page buffer circuit connected to the second bit lines and including a third latch storing data on the second memory cells based on the first read level voltage and a fourth latch storing data on the second memory cells based on the second read level voltage,
wherein the first page buffer circuit is configured to output a first read data of the first memory cells using the first latch, and the second page buffer circuit is configured to output a second read data of the second memory cells using the fourth latch.