Patent ID: 11889688
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A semiconductor device, comprising:
a substrate including a cell array region and a key region;
a stack structure on the cell array region, wherein the stack structure includes a first stack structure on the substrate and a second stack structure on the first stack structure, each of the first and second stack structures including a vertically stacked and spaced apart electrodes;
a dummy structure on the key region, wherein the dummy structure includes a first dummy structure on the substrate and a second dummy structure on the first dummy structure;
a vertical channel structure penetrating the stack structure to connect the substrate;
a dummy pillar penetrating the first dummy structure, wherein an upper portion of the dummy pillar protrudes upwardly from an upper surface of the first dummy structure, and the second dummy structure conforms to the first dummy structure such that an upper surface of the second dummy structure includes an upwardly extending protrusion aligned over the dummy pillar;
an interlayer dielectric layer on the stack structure and the dummy structure, wherein an upper portion of the interlayer dielectric layer on the dummy structure includes a key pattern that vertically overlaps the upwardly extending protrusion of the second dummy structure; and
a capping layer on the key region and covering the key pattern.