Patent ID: 11942412
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A method, comprising:
providing an interposer, the interposer including a first portion configured to electrically connect to a top side of a circuit board, the interposer including a second portion adjacent to the first portion and configured to wrap around an edge of the circuit board, the interposer including a peripheral portion adjacent to the second portion and configured to electrically connect to a bottom side of the circuit board, the interposer including a board-facing side and a chip-facing side opposite the board-facing side, the board-facing side configured to electrically connect to the top side of the circuit board and electrically connect to the bottom side of the circuit board, the first portion of the interposer defining a cavity that extends from the board-facing side of the interposer to the chip-facing side of the interposer;
electrically connecting a package substrate of a chip package to the chip-facing side of the first portion of the interposer, the package substrate coupled to at least one electrical component that extends into the cavity;
electrically connecting the top side of the circuit board to the board-facing side of the first portion of the interposer;
wrapping the second portion of the interposer around the edge of the circuit board; and
electrically connecting the bottom side of the circuit board to the board-facing side of the peripheral portion of the interposer.