Patent ID: 11934675
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A storage device, comprising:
one or more communication channels suitable for connection with a computing device;
a plurality of memory devices within a memory array;
a controller configured to provide access to the plurality of memory devices within the memory array;
wherein the controller operates in a plurality of mixed modes, and wherein each mixed mode is associated with a different level of performance;
wherein the plurality of mixed modes comprises a single-level cell (SLC) mode, and one of: a double-level cell (MLC) mode, a triple-level cell (TLC) mode, or a quad-level cell (QLC) mode;
wherein the SLC mode is configured to store intermediate data;
wherein each block of a plurality of blocks of the storage device has a first counter to track SLC mode program/erase cycles and a second counter to track multiple bit per cell mode program/erase cycles;
wherein values of the first and second counters remain balanced until a maximum threshold number of program/erase cycles of the SLC mode is reached; and
wherein after the maximum threshold number of program/erase cycles of the SLC mode is reached, the block is retired from use in SLC mode and only operates in multiple bit per cell mode thereafter.