Patent ID: 11921642
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A cache memory, comprising:
cache lines on a die to store information associated with physical addresses, each physical address comprising at least first and second non-overlapping, distinct predefined portions;
separate from the cache lines, one or more tables, each table comprising table entries indexed by the first portions of respective physical addresses, wherein a respective table entry in each of the one or more tables is to store indications of whether any one or more of a plurality of cache lines have been allocated to store information;
logic circuitry coupled to the one or more tables, to output a cache hit signal upon determining that the one or more tables include a table entry, at a location within the one or more tables specified by the first portion of a specified physical address, that stores an indication that a cache line at a location in the cache lines specified by the second portion of the specified physical address, has been allocated to store information associated with the specified physical address; and
forwarding circuitry, coupled to the logic circuitry and the plurality of cache lines, to forward the information associated with the specified physical address stored in the cache line at a location in the cache lines specified by the second portion of the specified physical address after receiving the cache hit signal output by the logic circuitry.