Patent ID: 11948625
Assignee: WINBOND ELECTRONICS CORP.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. The memory circuit of claim 1, further comprising:
a plurality of first data registers on the first die and configured to hold input data for a write operation;
a plurality of second data registers on the first die and configured to hold output data for a read operation;
a write driver circuit coupled between the first data registers and the memory cell array, and configured to drive first data signals from the first data registers to be written into the memory cell array; and
a read sense amplifier circuit coupled between the second data registers and the memory cell array, and configured to sense and amplify second data signals from the memory cell array to be held by the second data registers,
wherein:
the external signal line comprises a first data signal line and a second data signal line;
the first data registers on the first die are configured to receive, via the I/O connection interface, a write strobe signal from the external memory controller on the second die, and receive the input data from the first data signal line; and
the second data registers on the first die are configured to receive, via the I/O connection interface, a read strobe signal from the external memory controller on the second die, and provide the output data based on the read strobe signal to the second data signal line.