Patent ID: 11916683
Assignee: LANDIS+GYR TECHNOLOGY, INC.
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. The node of claim 1, wherein the memory further comprises instructions that are executable by the processor to cause the processor to:
based on the determination that the destination node does not correspond to a neighbor node of the plurality of tracked neighbor nodes, request the channel hopping timing and the channel hopping sequence for the destination node;
receive the channel hopping timing and the channel hopping sequence for the destination node; and
update a list of the plurality of tracked neighbor nodes by adding the channel hopping timing and the channel hopping sequence for the destination node, wherein the list of the plurality of tracked neighbor nodes comprises the channel hopping timing and the channel hopping sequence for each of the plurality of tracked neighbor nodes.