Patent ID: 11901405
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for manufacturing a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises an array region and a peripheral region adjacent to each other, and the array region comprises a buffer region connected with the peripheral region;
forming a first dielectric layer, a first supporting layer, a second dielectric layer, a second supporting layer and a third dielectric layer, which are successively stacked onto one another, on the substrate, wherein the first supporting layer is arranged at least in the peripheral region and covers a top surface and a side wall of the first dielectric layer, the second dielectric layer covers the first supporting layer and the substrate, and the second supporting layer and the third dielectric layer are arranged in the array region and the peripheral region;
forming a groove-type lower electrode, which at least penetrates through the third dielectric layer and the second supporting layer, in the buffer region, wherein a bottom surface of the groove-type lower electrode is located in the first dielectric layer or located in the second dielectric layer;
removing the third dielectric layer through a wet etching process; and
etching the second supporting layer in the peripheral region after removing the third dielectric layer.