Patent ID: 11966290
Assignee: SIFIVE, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An integrated circuit for executing instructions comprising:
a processor core configured to execute instructions of an instruction set;
an outer memory system configured to store instructions and data;
a checker core configured to receive committed instruction packets from the processor core and check the committed instruction packets for errors, wherein the checker core is configured to utilize a memory pathway of the processor core to access the outer memory system by receiving instructions and data read from the outer memory system as portions of committed instruction packets from the processor core; and
an architectural state injection circuit configured to, responsive to detection of an error in a committed instruction packet from the processor core by the checker core, invoke a pipeline flush in the processor core and copy a corrected portion of an architectural state from the checker core to the processor core.