Patent ID: 11923234
Assignee: STMICROELECTRONICS (TOURS) SAS
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 18:
19. A method, comprising:
forming a plurality of metal pillars on metal pads of a plurality of integrated circuits at a first side of a semiconductor substrate;
attaching a first support film to the first side of the semiconductor substrate, the first support film covering the plurality of metal pillars;
thinning a second side of the semiconductor substrate that is opposite the first side;
removing the first support film;
attaching a second support film to the first side of the semiconductor substrate;
forming a plurality of trenches extending through the semiconductor substrate to the second support film, the plurality of trenches laterally delimiting a plurality of chips, each of the chips including at least one of the plurality of integrated circuits; and
depositing an electrically isolating layer on lateral surfaces of the semiconductor substrate exposed by the plurality of trenches.