Patent ID: 11942935
Assignee: STMICROELECTRONICS (ROUSSET) SAS
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. An integrated circuit, comprising a programmable logic array, the programmable logic array including:
an array of logic cells, a first logic cell of the array of logic cells including:
a first multiplexer configured to receive a plurality of input signals;
a programmable memory coupled to the first multiplexer and configured to provide a direct output based on the plurality of input signals; and
a flip-flop configured to provide a synchronized output signal;

an AND gate having an output coupled to a clock input terminal of the flip-flop, a first input that receives a global clock signal, and a second input that receives a selected input signal from the plurality of input signals; and
a second multiplexer coupled to receive a subset of the plurality of input signals and to output the selected input signal to the second input of the AND gate.