Patent ID: 11862637
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 19:
20. The method of claim 19, wherein the first and second transistors and the tie-off transistor are PMOS transistors, the method further comprising:
forming a second active area on the substrate, the second active area including the first VT region and the second VT region;
forming the first gate to further contact second active area to form a first NMOS transistor having the first VT;
forming the second gate to further contact the second active area to form a second NMOS transistor having the second VT;
forming the third gate to further contact the second active area to form an NMOS tie-off transistor positioned between the first NMOS transistor and the second NMOS transistor; and
connecting the third gate to a second power rail to maintain the NMOS tie-off transistor in an off state.