Patent ID: 11908695
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A device, comprising:
a first source/drain region and a second source/drain region formed in a substrate;
a gate structure over the substrate between the first source/drain region and the second source/drain region, wherein the gate structure comprises a gate dielectric layer and one or more conductive layers over the gate dielectric layer;
a first spacer on a sidewall of the gate structure; and
a second spacer on a first sidewall of the first spacer opposite the gate structure, wherein a second sidewall of the first spacer tapers at an angle greater than or equal to 3 degrees relative to a line perpendicular to a surface of the substrate in a cross-sectional view.