Patent ID: 11874682
Assignee: INFINEON TECHNOLOGIES AG
Field: Control (Instruments)
Classification: CPC G  H | IPC G  H

Claim 17:
18. The method of claim 17, wherein each of the first tapped delay line circuit and the second tapped delay line circuit comprises:
a tapped delay line having a plurality of taps at different delay locations along the tapped delay line; and
a multiplexer, wherein input terminals of the multiplexer are coupled to the plurality of taps of the tapped delay line, wherein the multiplexer is configured to output an input signal at one of the input terminals selected by a selection signal of the multiplexer,
wherein the control circuit comprises a logic gate, wherein a first input terminal of the logic gate is coupled to a leftmost tap of the second programmable delay circuit, and a second input terminal of the logic gate is coupled to a rightmost tap of the second programmable delay circuit.