Patent ID: 11880225
Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 2:
3. A slave device that is connected to a host device via at least a power supply line, a clock line, a command line, and a data line,
wherein
the slave device is supplied a power from the host device via the power supply line after being connected to the host device,
the slave device is supplied a first clock having a first frequency and a first voltage value from the host device via the clock line,
the command line at a high level is driven to a low level,
the supply of the first clock is stopped,
the slave device is supplied a second clock having a second frequency and a second voltage value from the host device via the clock line in a state where the data line is driven to a low level,
the slave device drives the data line to a high level within a first predetermined period after the supply of the second clock, and
the slave device transmits a plurality of tuning blocks to the host device via the data line within a second predetermined period at an interval of at least a third predetermined period, and
the third predetermined period is defined by a clock period between data blocks at a time of continuously transmitting the data blocks after activation of the slave device and by a clock period defined by a data structure of a block pattern included in the plurality of tuning blocks.