Patent ID: 11962328
Assignee: PHISON ELECTRONICS CORP.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 8:
9. A memory storage device, comprising:
a connection interface unit, used for coupling to a host system a rewritable non-volatile memory module, and
a memory control circuit unit, coupled to the connection interface unit and the rewritable non-volatile memory module,
wherein the memory control circuit unit supports a plurality of decoding modes, the decoding modes respectively correspond to a threshold value, and a distribution of the threshold value corresponds to error correction abilities of the decoding modes,
the memory control circuit unit is used for:
sending a read command sequence, which instructs to read first data from the rewritable non-volatile memory module;
performing a first decoding operation on the first data;
obtaining a decoding parameter according to an execution result of the first decoding operation; and
performing a second decoding operation on the first data based on a first decoding mode among the decoding modes according to a relative numerical relationship between the decoding parameter and the threshold value.