Patent ID: 11886581
Assignee: SECURITY TECHNOLOGY, LLC
Field: Digital communication (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A system, comprising:
a memory;
one or more processors coupled to the memory; and
a verifier configured to:
receive (1) a first checksum value generated by at least one processor of a target entity executing first checksum code, and (2) an identity value associated with the target entity, wherein the target entity is in communication with the verifier;
compute, at least in part by the verifier executing second checksum code, a second checksum value;
wherein the first checksum code and the second checksum code executed, respectively, by the target entity and the verifier each comprise an accumulator portion and a control portion, and wherein the accumulator portion comprises a non-linear accumulator that modifies a checksum state, and wherein the control portion performs an action based at least in part on the modified checksum state;
perform a security determination based on:
(1) a time elapsed between communication of a seed and communication of the first checksum value,
(2) the identity value, and
(3) a comparison between the first checksum value and the second checksum value; and

subsequent to completion of a verification based at least in part on one or more digital signatures, perform a set of security actions based at least in part on the security determination, wherein the set of security actions comprises (1) enabling the at least one processor of the target entity to access a resource, and (2) causing the at least one processor of the target entity to obtain access to a cryptographic key.