Patent ID: 11922990
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G  H

Claim 15:
16. A method for operating a memory system, comprising:
providing a supply voltage from a power supply to a memory device;
generating from the supply voltage, with a voltage regulator of the memory device, an output voltage;
providing the output voltage to one or more memories of the memory device; and
providing the output voltage to one or more connected devices external to the memory device,
wherein the one or more connected devices receive the output voltage from one or more external outputs and do not receive the supply voltage from the power supply,
wherein the voltage regulator comprises a power management integrated circuit (PMIC) that includes one or more registers configured to store information corresponding to the output voltage, wherein the output voltage comprises a plurality of output voltages, and wherein the information comprises a first order in which the plurality of output voltages are powered up, first delays corresponding to the first order, a second order in which the plurality of output voltages are powered down, and second delays corresponding to the second order.