Patent ID: 11894060
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 11:
12. A method, comprising:
maintaining, by a non-volatile memory device comprising an array having a plurality of blocks each of a plurality of non-volatile memory cells, an experience count for a number of program/erase cycles experienced by each of the blocks;
receiving at the non-volatile memory device one or more commands to write data to a first of the blocks;
determining for each of the one or more commands to write data to the first block whether the data is to be written according to a first programming algorithm or a second programming algorithm, the second programming algorithm being of a slower write speed than the first programming algorithm;
in response to determining that the data is to be written to the first block according to the first programming algorithm, writing the data to the first block using the first programming algorithm and incrementing the experience count maintained for the first block by a first amount; and
in response to determining that the data is to be written to the first block according to the second programming algorithm, writing the data to the first block using the first programming algorithm and incrementing the experience count maintained for the first block by a second amount, the second amount being less that first amount.