Patent ID: 11955409
Assignee: QUALCOMM INCORPORATED
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A substrate comprising:
a core layer;
a match structure located at least partially in the core layer, the match structure comprising:
a plurality of first match interconnects comprising:
a first match via extending vertically in the match structure; and
a first match trace extending horizontally in the match structure,
wherein the first match via and the first match trace are located laterally to the core layer;

at least one second match interconnect extending vertically in the match structure, wherein the plurality of first match interconnects and the at least one second match interconnect are configured for skew matching; and
at least one structure dielectric layer that is located at least laterally to the core layer;

at least one first dielectric layer coupled to a first surface of the core layer; and
at least one second dielectric layer coupled to a second surface of the core layer.