Patent ID: 11881509
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 11:
12. A semiconductor device, comprising:
a substrate including a PMOSFET region and an NMOSFET region, which are adjacent to each other in a first direction;
a first active pattern and a second active pattern on the PMOSFET region and the NMOSFET region, respectively;
a first source/drain pattern on the first active pattern and a second source/drain pattern on the second active pattern;
a first gate electrode and a second gate electrode crossing the first and second active patterns, respectively, and extending in the first direction;
a first channel pattern connected to the first source/drain pattern and a second channel pattern connected to the second source/drain pattern, each of the first and second channel patterns including a first semiconductor pattern, a second semiconductor pattern and a third semiconductor pattern, which are sequentially stacked to be spaced apart from each other; and
a pair of middle insulating patterns between the second source/drain pattern and the second active pattern, the pair of middle insulating patterns being at both sides of a bottom surface of the second source/drain pattern in contact with a top surface of the second active pattern, and being on the NMOSFET region.