Patent ID: 11950430
Assignee: FERROELECTRIC MEMORY GMBH
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G  B | IPC H

Claim 0:
1. A memory cell comprising:
a first electrode;
a second electrode; and
a memory structure disposed between the first electrode and the second electrode,
the first electrode, the second electrode, and the memory structure forming a memory capacitor, wherein at least one of the first electrode or the second electrode comprises a plurality of layers comprising:
a first electrode layer in direct contact with the memory structure, wherein the first electrode layer comprises a first material having a first microstructure comprising a first average grain size;
a functional layer in direct contact with the first electrode layer; and
a second electrode layer in direct contact with the functional layer, the second electrode layer contacting, from among the plurality of layers, only the functional layer, wherein the second electrode layer comprises a second material having a second microstructure different from the first microstructure for reducing a leakage current of the memory capacitor, wherein the second microstructure comprises a second average grainsize that differs from the first average grain size, a second crystallographic texture that differs from the second crystallographic texture, and a second grain size distribution that differs from the second grain size distribution, wherein the first electrode layer, the functional layer, and the second electrode layer form a planar electrode layer stack of the memory capacitor, wherein the functional layer is disposed between the first layer and the second layer in the planar electrode layer stack.