Patent ID: 11875056
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A controller for controlling a memory device, comprising:
a write queue configured to store a plurality of commands for operating the memory device that are generated based on a plurality of requests received from a host, a plurality of zone identifications of the plurality of commands each indicating a memory region in the memory device, and a plurality of write pointers of the plurality of commands each indicating an order that the plurality of requests are output from the host, wherein the plurality of commands are stored in the write queue regardless of an order of the plurality of write pointers; and
a queue controller comprising a plurality of buffers allocated to one of the plurality of zone identifications, and the queue controller configured to:
receive the plurality of commands, the plurality of zone identifications, and the plurality of write pointers from the write queue,
select a command corresponding to the one of the plurality of zone identifications among the plurality of commands,
store the selected command in a selected buffer allocated to the one of plurality of zone identifications such that an order of write pointers of commands stored in the selected buffer is consecutive, and
output the commands stored in the selected buffer based on a number of the commands stored in the selected buffer.