Patent ID: 11861483
Assignee: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A spike neural network circuit comprising:
a synapse configured to generate an operation signal based on an input spike signal and a weight; and
a neuron configured to generate an output spike signal using a comparator configured to compare a voltage of a threshold signal with a voltage of a membrane signal generated based on the operation signal,
wherein the comparator includes a bias circuit configured to conditionally supply a bias current of the comparator depending on the voltage of the membrane signal,
wherein the bias current is supplied to the comparator when the voltage of the membrane signal is higher than the voltage of the threshold signal, and the supplying of the bias current to the comparator is blocked when the voltage of the membrane signal is lower than the voltage of the threshold signal, and
wherein the comparator includes:
a first transistor and a second transistor that are connected to a first power supply voltage and configured to form a current mirror;
a third transistor connected between a first node connected to the current mirror and a third node and receiving the threshold signal through its gate terminal;
a fourth transistor connected between a second node connected to the current mirror and the third node and receiving the membrane signal through its gate terminal;
a fifth transistor connected between the third node and a fourth node and configured to generate the bias current based on a bias signal; and
a sixth transistor connected between the fourth node and a second power supply voltage and configured to be turned on or turned off depending on the voltage of the membrane signal, wherein the bias circuit includes the fifth transistor and the sixth transistor.