Patent ID: 11861489
Assignee: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A convolutional neural network on-chip learning system based on a non-volatile memory, characterized in comprising:
a central processing unit (CPU), configured to execute an input module, an output module and a weight update module; and
a memristor array;
wherein the input module converts an input signal into an input voltage pulse signal required by the memristor array, and then transmits the input voltage pulse signal to the memristor array;
the memristor array performs a layer-by-layer calculation and conversion on the input voltage pulse signal corresponding to the input signal to complete an on-chip learning to obtain an output signal, the on-chip learning implements a synaptic function by using a conductance modulation characteristic that a conductance of a memristor changes according to an applied pulse, network convolution kernel values or synaptic weight values adopted in the on-chip learning process are stored in the memristor;
the output module converts and sends an output signal generated by the memristor array to the weight update module;
the weight update module calculates an error signal and adjusts the conductance value of the memristor according to a result of the output module, so as to update the network convolution kernel values or the synaptic weight values;
the memristor array adopts the memristor to simulate the network convolution kernel values and the synaptic weight values, and a resistance of the memristor changes according to an applied electrical signal;
the memristor array comprises a convolution layer circuit unit, a pooling layer circuit unit, and a fully connected layer circuit unit, the convolution layer circuit unit and the pooling layer circuit unit are composed by using the memristor array as convolution kernels, and the fully connected layer circuit unit is composed by using the memristor array as synapses;
the convolutional layer circuit unit receives the input voltage pulse signal output by the input module, and the input voltage pulse signal is processed through the layer-by-layer calculation and conversion performed by the convolutional layer circuit unit, the pooling layer circuit unit, and the fully connected layer circuit unit, and a calculation result is transmitted to the output module as an output signal;
the convolutional layer circuit unit is composed of a convolution operation circuit and an activation function part, the convolution operation circuit is composed of the memristor array;
the convolution operation circuit adopts two rows of memristor arrays as a convolution kernel to realize positive and negative convolution kernel values, when an initial convolution kernel value corresponds to a memristor conductance value, the convolution kernel value is mapped to a matrix capable of performing a matrix multiplication operation with the entire input signal, the convolution kernel is expanded into two large sparse matrices K+ and K−, which are respectively the positive and negative convolution kernel values corresponding to a neuron node, and correspondingly a characteristic that the memristor is capable of being applied with positive and negative read voltage pulses is utilized to convert the input signal into two one-dimensional matrices with positive input X and negative input −X;
the convolution operation circuit performs a convolution operation on the input voltage pulse signal and the convolution kernel value stored in a memristor unit, and collects currents of the same column to obtain a convolution operation result; the convolution operation process is y=f((X⊗K+)+(−X⊗K−)+b), wherein y is a result of the convolution operation, ⊗ is a convolution operator, X is an input voltage signal of a front synapse of the neuron node, K+ and K− are respectively the positive and negative convolution kernel values corresponding to the neuron node, b is a bias term corresponding to a convolutional layer network, and f(.) is the activation function;
the convolutional layer circuit unit transmits the convolution operation result to the pooling layer circuit unit; and
the activation function activates the convolution operation result and obtains two opposite output values, y and −y, and simultaneously converts the two opposite output values y and −v into a voltage pulse signal to serve as an input of the pooling layer circuit unit.