Patent ID: 11972831
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 19:
20. A receiver configured to receive a multi-level signal having a first voltage level, a second voltage level, a third voltage level and a fourth voltage level that are different from each other, comprising:
a pre-amplifier circuit configured to generate a first intermediate data signal, a second intermediate data signal and a third intermediate data signal based on an input data signal, a first reference voltage, a second reference voltage and a third reference voltage, the input data signal being the multi-level signal, the first reference voltage having a voltage level between the first and second voltage levels, the second reference voltage having a voltage level between the second and third voltage levels, the third reference voltage having a voltage level between the third and fourth voltage levels;
a slicer circuit configured to generate a first decision signal, a second decision signal and a third decision signal based on the first, second and third intermediate data signals and a clock signal; and
a decoder circuit configured to generate output data based on the first, second and third decision signals, the output data including a first bit and a second bit,
wherein the pre-amplifier circuit includes:
a first level shifter configured to generate the first intermediate data signal by level-shifting the input data signal based on the first reference voltage;
a second level shifter configured to generate the second intermediate data signal by level-shifting the input data signal based on the second reference voltage; and
a third level shifter configured to generate the third intermediate data signal by level-shifting the input data signal based on the third reference voltage,

wherein one of the first, second and third level shifters has a structure different from the remaining first, second and third level shifters, or all of the first, second and third level shifters have different structures, and
wherein the structures of the first, second and third level shifters are determined based on a number, a type, or a connection structure of transistors included in the first, second and third level shifters.