Patent ID: 11869562
Assignee: KEPLER COMPUTING INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus comprising:
a memory organized in a plurality of memory banks, wherein the plurality of memory banks comprises memory bit-cells, wherein the plurality of memory banks includes a first memory bank and a second memory bank, and wherein an individual memory bit-cell includes a non-volatile material which includes one of: a non-linear polar material, a magnet, or a resistive material; and
a memory controller coupled to the memory, wherein the memory controller includes one or more circuitries configured to improve memory endurance of the memory via wear leveling, wherein the memory controller is to apply the wear leveling to the first memory bank and the second memory bank in a round-robin fashion, wherein the first memory bank has a first gap word, and wherein the second memory bank has a associated second gap word, wherein the memory controller is to request a write to an address of an individual memory bank or a read to an address of the individual memory bank of the first memory bank, and wherein the one or more circuitries are configured to swap the first gap word with an adjacent cache line or word in response to the request.