Patent ID: 11877440
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 0:
1. A buried bit line, formed in a bit line slot in a substrate, comprising:
a first bit line layer, formed in the bit line slot, wherein a top of the first bit line layer is lower than a surface of the substrate;
a first blocking layer, at least partially formed between the first bit line layer and an inner wall of the bit line slot;
a second bit line layer, formed in the bit line slot and configured to communicate the first bit line layer with a drain region in the substrate;
a second blocking layer, at least partially formed between the second bit line layer and the inner wall of the bit line slot; and
a third blocking layer, formed between the second bit line layer and the first bit line layer;
wherein a contact metal layer is formed between the third blocking layer and the first bit line layer, and the contact metal layer and the third blocking layer form an ohmic contact.