Patent ID: 11929713
Assignee: QORVO US, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 7:
8. A voltage processing circuit comprising:
a first group delay circuit configured to receive a time-variant target voltage and generate a first time-variant target voltage having a first group delay relative to the time-variant target voltage;
a second group delay circuit configured to receive the time-variant target voltage and generate a second time-variant target voltage having a second group delay relative to the time-variant target voltage; and
a maximum signal detector circuit comprising:
a signal selector circuit comprising:
a plurality of signal inputs configured to receive the first time-variant target voltage and the second time-variant target voltage; and
a signal output configured to generate a windowed time-variant target voltage higher than or equal to a highest one of the first time-variant target voltage and the second time-variant target voltage in a plurality of group delay tolerance windows each having a duration that is equal to an absolute value of the first group delay plus an absolute value of the second group delay.