Patent ID: 11963364
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 1:
2. The semiconductor device of claim 1, further comprising:
a second stacked structure including a plurality of fourth insulating patterns and a plurality of second semiconductor patterns alternately stacked on the substrate, the second stacked structure being spaced apart from the first stacked structure in the third direction, and extending in the first direction, each of a second semiconductor pattern of the plurality of second semiconductor patterns including a third impurity region, a second channel region, and a fourth impurity region arranged in sequential order along the first direction;
a second conductive pattern on a second side surface of the second stacked structure, the second conductive pattern extending in the second direction; and
a second ferroelectric layer between the second stacked structure and the second conductive pattern, the second ferroelectric layer extending in the second direction,
wherein each of the plurality of first wiring patterns is connected to the third impurity region of each of the plurality of second semiconductor patterns, and
wherein each of the plurality of second wiring patterns is connected to the fourth impurity region of each of the plurality of second semiconductor patterns.