Patent ID: 11862647
Assignee: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. An artificial neural network device comprising:
a substrate;
a neuron block configured to perform substantive computing functions, the neuron block arranged in direct contact with a partial area on one surface of the substrate; and
a synapse block arranged in direct contact with a remaining area on the surface of the substrate, the synapse block extending in a parallel arrangement with the neuron block, the synapse block electrically connected to the neuron block and configured to transmit signals from the neuron block;
wherein the neuron block and the synapse block respectively further comprise:
a first channel element arranged on the surface of the substrate, the first channel element of the neuron block being separate and spaced apart from the first channel element of the synapse block;
a second channel element stacked on the first channel element, the second channel element of the neuron block being separate and spaced apart from the second channel element of the synapse block; and
connecting elements electrically connecting the first channel element of the neuron block and the second channel element of the neuron block, and electrically connecting the first channel element of the synapse block and the second channel element of the synapse block, respectively;

wherein the first channel element of the neuron block and the first channel element of the synapse block respectively further comprise:
a first active layer;
a first insulating layer placed on one surface of the first active layer;
a first gate electrode placed on the opposite side of the first active layer with the first insulating layer interposed therebetween;
a first source electrode contacting one side of the first active layer, and separated from the first gate electrode; and

a first drain electrode contacting the other side of the first active layer, and separated from the first gate electrode;
wherein the second channel element of the neuron block and the second channel element of the synapse block respectively further comprise:
a second active layer;
a second insulating layer placed on one surface of the second active layer;
a second gate electrode placed on the opposite side of the second active layer with the second insulating layer interposed therebetween;
a second source electrode contacting one side of the second active layer, and separated from the second gate electrode; and
a second drain electrode contacting the other side of the second active layer, and separated from the second gate electrode,

wherein the connecting elements extend between the first channel element and the second channel element of the neuron block on opposing sides of the first insulating layer, and between the first channel element and the second channel element of the synapse block on opposing sides of the first insulating layer, respectively,
wherein the connecting elements electrically connect the first source electrode and the second source electrode, and electrically connect the first drain electrode and the second drain electrode, respectively,
wherein the neuron block and the synapse block respectively further comprise:
an insulating element interposed between the first channel element and the second channel element, and separating the first channel element and the second channel element from each other,

wherein the connecting elements penetrate the insulating element,
wherein the first insulating layer of the neuron block and the first insulating layer of the synapse block are formed of different material, and the first insulating layer of the neuron block is thinner than the first insulating layer of the synapse block,
wherein the second insulating layer of the neuron block and the second insulating layer of the synapse block are formed of different material, and the second insulating layer of the neuron block is thinner than the second insulating layer of the synapse block,
wherein, in both of the neuron block and the synapse block, the first active layer, the first insulating layer, the first gate electrode, the second active layer, the second insulating layer, and the second gate electrode are placed in order, in a direction of stacking the first and second channel elements of the neuron block and the synapse block.