Patent ID: 11868259
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A cache coherent computing system, comprising:
a plurality of boards, each board comprising a plurality of processors,
wherein a first core in a first processor on a first board of the plurality of boards is configured to request cached data that is not stored in a cache assigned to the first core;
upon determining that another core on the first processor does not have the requested cached data, the first processor is configured to:
broadcast a request to the other processors on the first board to determine whether one of the other processors is an intervention master (IM) of the requested cached data;
receive partial responses (PRESPs) from the other processors on the first board;
determine, based on the PRESPs, which of the other processors are still participating in the request, wherein a first one of the other processors indicates in its PRESP that it is the IM, and a second one of the other processors indicates in its PRESP that it is not the IM but it is still participating in the request so it can forward the request to a second board of the plurality of boards; and
transmit a combined response (CRESP) to only the other processors that indicate in their PRESPs that they are still participating in the request.