Patent ID: 11861455
Assignee: D-WAVE SYSTEMS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  B | IPC B  G

Claim 0:
1. A method of operation of a hybrid computer, the hybrid computer comprising an analog processor and a digital processor, the method performed by the digital processor, the method comprising:
determining, for a first interval of a normalized evolution coefficient, a first evolution schedule and a second evolution schedule, each of the first evolution schedule and the second evolution schedule defining a respective time dependence of the normalized evolution coefficient, the first interval bounded by a first value of the normalized evolution coefficient and a second value of the normalized evolution coefficient;
programming the analog processor using the first evolution schedule;
causing the analog processor to evolve in accordance with the first evolution schedule in a direction of increasing normalized evolution coefficient from the first value of the normalized evolution coefficient to the second value of the normalized evolution coefficient;
causing the analog processor to evolve in accordance with the first evolution schedule in a direction of decreasing normalized evolution coefficient from the second value of the normalized evolution coefficient to the first value of the normalized evolution coefficient;
programming the analog processor using the second evolution schedule;
causing the analog processor to evolve in accordance with the second evolution schedule in the direction of increasing normalized evolution coefficient from the first value of the normalized evolution coefficient to the second value of the normalized evolution coefficient;
causing the analog processor to evolve in accordance with the second evolution schedule in the direction of decreasing normalized evolution coefficient from the second value of the normalized evolution coefficient to the first value of the normalized evolution coefficient;
determining whether an exit condition has been met, and upon determining an exit condition has been met:
determining, for a second interval of the normalized evolution coefficient, a third evolution schedule, the third evolution schedule defining a time dependence of the normalized evolution coefficient, the second interval bounded by the second value of the normalized evolution coefficient and a third value of the normalized evolution coefficient; and
programming the analog processor using the third evolution schedule; and
causing the analog processor to evolve in accordance with the third evolution schedule in the direction of increasing normalized evolution coefficient from the second value of the normalized evolution coefficient to the third value of the normalized evolution coefficient.