Patent ID: 11923317
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 19:
20. A semiconductor device, comprising:
a substrate comprising a plurality of chip regions and a scribe line between the plurality of chip regions;
a lower pattern group on the scribe line, wherein the lower pattern group comprises a photolithography key pattern and a plurality of lower test patterns that are horizontally spaced apart from the photolithography key pattern; and
an upper pattern group on the lower pattern group, wherein the upper pattern group comprises a first pad and a plurality of upper test patterns that are horizontally spaced apart from the first pad,
wherein the first pad is electrically connected to the plurality of upper test patterns and the plurality of lower test patterns, and
wherein the first pad vertically overlaps the photolithography key pattern.