Patent ID: 11869597
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. A semiconductor storage device comprising:
a plurality of planes each including a memory cell array configured by a plurality of memory cells, word lines connected to gates of the plurality of memory cells, and bit lines electrically connected to one ends of the plurality of memory cells via selection gate transistors respectively connected to the one ends of the plurality of memory cells;
a voltage generation circuit provided in each of the plurality of planes, capable of generating a voltage supplied to the memory cell array, and including a limit circuit configured to limit a program voltage supplied to a writing target selected word line to a specified value, the voltage generation circuit supplying a program voltage to the selected word line in a program period and applying a first intermediate voltage to an adjacent word line adjacent to the selected word line in a former half of the program period and applying a second intermediate voltage higher than the first intermediate voltage to the adjacent word line in a latter half of the program period; and
a control circuit configured to set, according to a level of the program voltage, a current amount flowing to the limit circuit.