Patent ID: 11955527
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 16:
17. A method comprising:
forming a multi-layer stack comprising:
forming a plurality of sandwich structures, wherein upper ones of the plurality of sandwich structures overlap corresponding lower ones of the plurality of sandwich structures, and each of the plurality of sandwich structures comprises:
a first isolation layer;
a two-dimensional material over the first isolation layer; and
a second isolation layer over the two-dimensional material; and

forming a plurality of sacrificial layers, wherein the plurality of sandwich structures and the plurality of sacrificial layers are located alternatingly;

removing the plurality of sacrificial layers to form recesses, wherein bottom surfaces of the first isolation layers and top surfaces of the second isolation layers in the plurality of sandwich structures are revealed to the recesses;
forming a gate stack extending into the recesses, wherein the gate stack encircles each of the plurality of sandwich structures; and
forming a metal source/drain region on a side of the plurality of sandwich structures, wherein the metal source/drain region is in contact with sidewalls of the plurality of sandwich structures.