Patent ID: 11908858
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A semiconductor device, comprising:
a substrate including a first region, and a second region;
a first gate structure and a second gate structure on the substrate of the first region, the first gate structure and the second gate structure being spaced apart by a first distance;
a third gate structure and a fourth gate structure on the substrate of the second region, the third gate structure and the fourth gate structure being spaced apart by a second distance lower than the first distance;
a first liner along and contacting a sidewall of the first gate structure, continuing along and contacting an upper surface of the substrate, and continuing along and contacting a sidewall of the second gate structure, the first liner not being formed on an upper surface of the first gate structure and an upper surface of the second gate structure;
a second liner along a sidewall of the third gate structure, the upper surface of the substrate, and a sidewall of the fourth gate structure, the second liner not being formed on an upper surface of the third gate structure and an upper surface of the fourth gate structure;
a first interlayer insulating film on the first liner and surrounding the sidewall of the first gate structure and the sidewall of the second gate structure;
a second interlayer insulating film on the second liner and surrounding the sidewall of the third gate structure and the sidewall of the fourth gate structure;
a first contact between the first gate structure and the second gate structure and within the first interlayer insulating film, the first contact having a first width; and
a second contact between the third gate structure and the fourth gate structure and within the second interlayer insulating film, the second contact having a second width lower than the first width,
the first width being correlated to a width of the upper surface of the first gate structure, and the second width being correlated to a width of the upper surface of the third gate structure.