Patent ID: 11972806
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A memory device, comprising:
a memory block that includes a plurality of memory cells arranged in a plurality of word lines, the memory cells being programmed to multiple bits per memory cell, and the memory block including a voltage driver that is located on one side of the word lines;
control circuitry that is configured to read the memory cells of a selected word line of the plurality of word lines, the control circuitry being configured to:
separate the memory cells of the selected word line into a first group of memory cells that are located on a side of the word line are near the voltage driver and a second group of memory cells that are located on an opposite side of the word line from the voltage driver, and
read the memory cells of the first group of memory cells using a first read mode and read the memory cells of the second group using a second read mode that is different than the first read mode to reduce a fail bit count.