Patent ID: 11862272
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. A chip, comprising:
a normal unit region, comprising a plurality of local regions; and
a redundancy unit region, comprising Global Redundancy (GR) circuits and Local Redundancy (LR) circuits, the GR circuits being configured to repair a fail bit in any of the local regions, the LR circuits being configured to repair the fail bit in a designated local region of the local regions, wherein the GR circuits and the LR circuits are constructed to repair a fail bit in the local regions by:
determining a local region to be repaired comprising the fail bit, and determining a preliminary repair LR circuit for repairing the local region to be repaired;
acquiring a number of available GR circuits other than any replacement GR circuit configured for replacing the preliminary repair LR circuit and a number of available LR circuits designated for repairing the local region to be repaired;
determining, according to the number of available GR circuits other than the any replacement GR circuit and the number of available LR circuits, a region level of the local region to be repaired; and
according to the region level of the local region to be repaired, controlling repair of the fail bit by the any replacement GR circuit in place of the preliminary repair LR circuit, or controlling repair of the fail bit by the preliminary repair LR circuit.