Patent ID: 11923294
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  C  G | IPC H

Claim 17:
18. A method of forming an interconnect structure, comprising:
forming a via on a substrate;
forming an etching stop layer on the via;
forming an insert layer on the etching stop layer;
forming a dielectric layer on the insert layer, wherein the insert layer is between the etching stop layer and the dielectric layer, and a material of the insert layer is different from the dielectric layer and the etching stop layer;
forming a trench in the dielectric layer, the insert layer and the etching stop layer; and
forming a conductive line in the trench,
wherein a bottom surface of the insert layer is higher than a top surface of the via.