Patent ID: 11862253
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 6:
7. The data output control circuit of claim 1, wherein the control signal generating circuit includes:
a plurality of logic gates configured to selectively mask the multiple phase clock signals based on the plurality of timing signals to generate a plurality of corrected clock signals;
a first driver configured to drive an output terminal to a power voltage level or a ground voltage level based on a first corrected clock signal and a third corrected clock signal, among the plurality of corrected clock signals, to generate a first data output control signal, among the data output control signals; and
a second driver configured to drive an output terminal to a power voltage level or a ground voltage level based on a second corrected clock signal and a fourth corrected clock signal, among the plurality of corrected clock signals, to generate a second data output control signal, among the data output control signals.