Patent ID: 11959964
Assignee: SEMITRONIX CORPORATION
Field: Measurement (Instruments)
Classification: CPC G | IPC G

Claim 0:
1. A test system comprising:
a probe card;
a test apparatus; and
a test path coupling an addressable test chip with the test apparatus through the probe card; and said address register is integrated in one of said probe card or the addressable test chip;
wherein:
the test apparatus includes a function generator, a source measurement unit, and a programmable logic device;

the programmable logic device is configured to acquire the trigger signal of the test algorithm and transmits it to the function generator and the source measurement unit, synchronously triggers the function generator and the source measurement unit to generate CLK signals and DF signals respectively;
the address register connected to the function generator switches addresses according to the CLK signal;
the source measurement unit continuously samples according to the DF signal triggered synchronously; and
each address corresponds to multiple sampling data.