Patent ID: 11886272
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 14:
15. A memory device, comprising:
circuitry to enter a first mode of operation;
circuitry to, while in the first mode of operation, transfer data from a memory array via each of a first plurality of links;
circuitry to enter a second mode of operation;
circuitry to, while in the second mode of operation, transfer data via each of a second plurality of links, the second plurality of links being a proper subset of the first plurality of links;
steering circuitry coupled to the memory array and the first plurality of links to, while in the second mode of operation, loop-back data via at least one link of the first plurality of links that is not one of the second plurality of links; and
circuitry to, while in the second mode of operation, update a first timing adjustment parameter for at least one link of the first plurality of links that is not one of the second plurality of links.