Patent ID: 11893122
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A system, comprising:
a plurality of processing Cores;
a Package Interconnect communicatively coupled with the plurality of processing Cores;
a Configurable LFSR PRV Generator Hardware Array means communicatively coupled with the Package Interconnect and configured to provide a plurality of LFSRs whose length, feedback polynomial, jitter value, warm up cycle count, and algorithmic feedback discard method are configurable through a register-interface accessible by the Cores through the Package Interconnect;
a Galois Multiplication Hardware Accelerator means communicatively coupled with the Package Interconnect and configured to accelerate Galois Finite Field multiplication of two multiplicands and primitive polynomial modulus division operations necessary to identify Galois Finite Field multiplicative product values;
an Extended Euclidian Algorithm Hardware Accelerator means communicatively coupled with the Package Interconnect and configured to provide Extended Euclidian Algorithm acceleration; and
a Fischer-Yates Shuffle Algorithm Hardware Accelerator means communicatively coupled with the Package Interconnect and configured to provide fragments both fixed- size and variable-sized mince shuffling and random bit blending hardware acceleration.