Patent ID: 11862722
Assignee: INNOSCIENCE (SUZHOU) TECHNOLOGY CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A method for manufacturing a semiconductor device structure, comprising:
providing a substrate;
forming a first nitride semiconductor layer on the substrate;
forming a second nitride semiconductor layer on the first nitride semiconductor layer, wherein the second nitride semiconductor layer has a bandgap greater than that of the first nitride semiconductor layer;
forming a third nitride semiconductor layer on the second nitride semiconductor layer;
forming a barrier layer on the third nitride semiconductor layer, wherein the barrier layer has a bandgap greater than that of the second nitride semiconductor layer;
forming a gate structure on the third nitride semiconductor layer; and
forming a source electrode and a drain electrode on the second nitride semiconductor layer,
wherein the source electrode and drain electrode contact with an upper surface of the second nitride semiconductor layer, and
wherein the barrier layer is in contact with the drain electrode, and is spaced away from the source electrode.