Patent ID: 11869442
Assignee: LG DISPLAY CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 1:
2. The display device according to claim 1,
wherein the output buffer circuit includes:
a first output transistor controlled by the first control node and configured to output the clock signal supplied to a clock line to the output line;
a second output transistor controlled by the first control node and configured to output the clock signal, which is supplied to the clock line, to the scan output line;
a third output transistor controlled by the second control node and configured to output the high potential power supply voltage, which is supplied to a first power line, to the output line; and
a fourth output transistor controlled by the second control node and configured to output the low potential power supply voltage, which is supplied to a second power line, to the scan output line.