Patent ID: 11929292
Assignee: KIOXIA CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A semiconductor memory device comprising:
a substrate including first and second active block areas and first and second dummy block areas arranged in a first direction;
a plurality of first conductive layers stacked above the substrate and spaced apart from each other, the first conductive layers being disposed in the first and second active block areas and in the first and second dummy block areas;
a plurality of insulating members extending in a second direction intersecting both the first direction and a stacking direction of the first conductive layers on both sides of the first dummy block area in the first direction and on both sides of the second dummy block area in the first direction, the insulating members being arranged above the substrate and partitioning the first conductive layers in the first direction;
a plurality of first pillars extending in the stacking direction through the first conductive layers in the first active block area, intersections of the first pillars with at least one of the first conductive layers functioning as memory cells; and
a plurality of second pillars extending in the stacking direction through the first conductive layers in the first dummy block area, wherein
the substrate further includes an interconnect connection area in which a first contact electrically connecting an upper interconnect above the first conductive layers and a circuit disposed under the first conductive layers is provided, the first dummy block area being disposed between the first active block area and the interconnect connection area in the first direction, the second dummy block area being disposed between the second active block area and the interconnect connection area in the first direction, and the interconnect connection area being disposed between the first dummy block area and the second dummy block area in the first direction, and
the insulating members include a first insulating member on a first side of the first dummy block area facing the first active block area and a second insulating member on a second side of the first dummy block area facing the interconnect connection area, the first conductive layers being further disposed in a first adjacent area close to the second insulating member on an opposite side of the first dummy block area.