Patent ID: 11973040
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for forming an integrated circuit (IC) chip package structure, comprising:
providing an interposer including a substrate, the interposer having a front surface and a back surface and comprising:
routing regions having conductive interconnect structures in and on the substrate for connecting to a group of IC dies facing the front surface of the interposer; and
non-routing regions without the conductive interconnect structures;

forming a first plurality of warpage-reducing trenches in a first non-routing region of the interposer, the first plurality of warpage-reducing trenches characterized by a first trench width, first trench spacing, and first trench length, wherein the first plurality of warpage-reducing trenches do not extend to the back surface of the interposer;
depositing a first warpage-relief material in the first plurality of warpage-reducing trenches;
forming a second plurality of warpage-reducing trenches in a second non-routing region of the interposer, the second plurality of warpage-reducing trenches characterized by a second trench width, a second trench spacing, and a second trench length, wherein the second plurality of warpage-reducing trenches do not extend to the back surface of the interposer, wherein the second trench width is different from the first trench width, the second trench spacing is different from the first trench spacing, and the second trench length is different from the first trench length;
depositing a second warpage-relief material in the second plurality of warpage-reducing trenches; and
bonding the group of IC dies to the front surface of the interposer to form an IC chip package.