Patent ID: 11862626
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An apparatus comprising:
a field effect transistor (FET) formed on a semiconductor substrate in a front-end-of-line (FEOL);
a metal interconnect layer formed on top of the FEOL layer,
wherein the metal interconnect layer comprises a plurality of interconnects configured to interconnect the FET to a plurality of components formed on the semiconductor substrate;
a power delivery network (PDN) formed under the semiconductor substrate in a backside layer; and
a through substrate resistive component formed between the FEOL layer and a B-BEOL layer,
wherein a first contact of the through substrate resistive component is connected to a drain terminal of the FET and second contact of the through substrate resistive component is connected, through the PDN, to a power supply rail.