Patent ID: 11881284
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
performing a first read operation on a first set of memory cells addressable by a first wordline (WL) of a first plurality of WLs and a second read operation on a second set of memory cells addressable by a second WL of the first plurality of WLs, wherein the first set of memory cells and the second set of memory cells are comprised by an open translation unit (TU) of memory cells;
identifying a first threshold voltage offset bin associated with the first WL;
identifying a second threshold voltage offset bin associated with the second WL;
determining, based on at least one of the first threshold voltage offset bin and the second threshold voltage offset bin, respective threshold voltage offset bins for each WL of a second plurality of WLs coupled to respective sets of memory cells comprised by the open TU; and
updating, based on the respective threshold voltage offset bins for each WL of the second plurality of WLs, respective default threshold voltages for each WL of the first plurality of WLs and the second plurality of WLs.