Patent ID: 11943083
Assignee: MARVELL ASIA PTE LTD
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. The physical layer transceiver claimed in claim 11, wherein the digital timing loop comprises:
 a timing error detector configured to detect a timing error based on a non-equalized signal received at the physical layer transceiver via a communication channel; and
 a phase interpolator configured to adjust a sample clock phase of an analog-to-digital converter sample clock to compensate for the timing error;
wherein the matching filters are configured to generate a filtered signal based on the non-equalized signal received at the physical layer transceiver; and
wherein the physical layer transceiver further comprises:
a Differential Manchester Encoding (DME) decoder configured to generate a decoded signal based on the filtered signal;
peak search circuitry configured to detect peak values in the filtered signal;
peak tracking circuitry configured to track the peak values to identify an optimal value among the peak values; and
data select circuitry configured to utilize a sample phase synchronized based on the identified optimal value to select a logic zero or a logic one based on the decoded signal.