Patent ID: 11954043
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. The method according to claim 11, wherein
the nonvolatile memory includes a plurality of blocks, each of the plurality of blocks being a unit for an erase operation,
the plurality of namespaces includes at least a first namespace and a second namespace, and
the method further comprises:
allowing the host to select a first addressing method for the first namespace to issue a first write command associated with the first namespace, in the first addressing method, first data that is target data of the first write command is specified using a logical address associated with the first data but not specified using an identifier of a block to which the first data is to be written, and
allowing the host to select a second addressing method for the second namespace to issue a second write command associated with the second namespace, in the second addressing method, second data that is target data of the second write command is specified using at least an identifier of a block to which the second data is to be written.