Patent ID: 11901402
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A packaged electronic device, comprising:
a first semiconductor die, having a first conductive feature;
a second semiconductor die, having a second conductive feature;
a capacitor die, including:
a first dielectric layer above a semiconductor layer;
a lower-bandgap dielectric layer above the first dielectric layer, the lower-bandgap dielectric layer having a bandgap energy less than a bandgap energy of the first dielectric layer;
a conductive first capacitor plate above the lower-bandgap dielectric layer in a first plane of orthogonal first and second directions;
a second dielectric layer above the first capacitor plate;
a conductive second capacitor plate above the second dielectric layer in a second plane of the first and second directions, the first and second capacitor plates spaced apart from one another along a third direction to form a first capacitor, the third direction orthogonal to the first and second directions; and
a conductive third capacitor plate above the second dielectric layer in the second plane, the third capacitor plate spaced apart from the second capacitor plate in the second plane, and the first and third capacitor plates spaced apart from one another along the third direction to form a second capacitor in series with the first capacitor;

a first electrical connection that couples the first conductive feature of the first semiconductor die to the second capacitor plate of the capacitor die;
a second electrical connection that couples the second conductive feature of the second semiconductor die to the third capacitor plate of the capacitor die;
a package structure that encloses the first semiconductor die, the second semiconductor die, the capacitor die, and the first and second electrical connections; and
conductive leads exposed along one or more sides of the package structure.