Patent ID: 11894432
Assignee: STMICROELECTRONICS S.R.L.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 17:
18. A method, comprising:
forming a first structure on a first side of a substrate, the first structure including at least one current-conduction region; and
forming a second structure on a second side, opposite the first side, of the substrate, the second structure being electrically coupled to the substrate, the forming of the second structure including:
forming a first conductive layer and a silicide region on the second side of the substrate, the silicide region being between the second side of the substrate and the first conductive layer, the silicide region being electrical coupled to the substrate, the forming of the first conductive layer being performed at a temperature that triggers the forming of the silicide region; and
forming a second conductive layer on the first conductive layer.