Patent ID: 11869988
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for building an integrated circuit (IC), comprising:
forming a first series of trenches on a first side of a substrate, and forming a first deep trench capacitor (DTC) stack within the first series of trenches;
after the first DTC stack has been formed, bonding the first side of the substrate to a first metal interconnect structure disposed on a carrier wafer;
thinning down a second side of the substrate opposite the first side; and
etching a second series of trenches into the second side of the substrate, and forming a second DTC stack within the second series of trenches;
after the first side of the substrate is bonded to the first metal interconnect structure, forming a through-substrate via (TSV) through the substrate, wherein forming the TSV comprises:
etching a first trench into the substrate that extends from a first surface of the substrate to a second surface of the substrate;
forming a dielectric layer within the first trench and over the first surface of the substrate;
etching a second trench that extends from the second surface of the substrate to a top surface of the first metal interconnect structure; and
forming the TSV within the first and second trenches such that the TSV directly contacts the first metal interconnect structure; and

forming a second metal interconnect structure over the second side of the substrate and over the TSV, such that the TSV directly connects the first metal interconnect structure to the second metal interconnect structure.