Patent ID: 11893239
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A logic circuit comprising:
a first interface coupled to a command/address bus and a data bus; and
a second interface;
the logic circuit receiving a first command and a second command from a host device through the first interface, wherein the first command has a first type and the second command has a second type; and
converting the first command to a first processing-in-memory (PIM) command according to a first PIM protocol based on the first type;
converting the second command to a second PIM command according to a second PIM protocol based on the second type; and
initiating transmission of the first PIM command and the second PIM command to a high-bandwidth memory (HBM) device using the second interface, and the logic circuit further sending information relating to a number of credits indicating an estimated completion time of an execution of a PIM operation associated with the first PIM command to the host device and receives a third command from the host device using the first interface, based on the estimated completion time.