Patent ID: 11942404
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 20:
21. An apparatus, comprising:
a first memory device, comprising:
a device substrate comprising a semiconductor material and bond pads coupled with an active surface of the device substrate;
a package substrate secured to the device substrate, the device substrate secured to the package substrate by a direct chip attach, the package substrate configured to route signals to and from the bond pads; and
a first ball grid array supported on, and electrically connected to, the package substrate, the first ball grid array comprising an odd number of columns, such that the first ball grid array comprises a central column having equal numbers of other columns on opposite sides of the central column;

a second memory device comprising a second ball grid array; and
a printed circuit board interposed between, and secured to, each of the first ball grid array of the first memory device and the second ball grid array of the second memory device, the second ball grid array of the second memory device being rotationally symmetrical across the printed circuit board relative to the first ball grid array of the first memory device;
wherein each ball of the first ball grid array of the first memory device positioned and configured to carry a clock signal or a strobe signal is located in the central column of the ball grid array;
wherein a total number of balls in the ball grid array is between about 115 and about 120.