Patent ID: 11934945
Assignee: CEREBRAS SYSTEMS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 1:
2. The system of claim 1, wherein:
each compute engine is configured to perform a predefined set of basic operations in response to receiving a corresponding basic instruction selected from a predefined native instruction set of codes; and further comprising
a training workload comprising
a first set of machine codes selected from the native instruction set for performing a mapping of at least a part of a neuron onto the compute engine of the processor element, the mapping comprising managing at least one partial-neuron weight,
a second set of machine codes selected from the native instruction set for performing a forward pass to propagate activations in a forward logical direction based at least in part on the at least one partial-neuron weight, the forward pass initiated responsive to an input sample,
a third set of machine codes selected from the native instruction set for performing a delta pass in a backward logical direction to generate deltas, the delta pass initiated responsive to completion of the forward pass,
a fourth set of machine codes selected from the native instruction set for performing a chain pass to calculate gradients based on the deltas, and
a fifth set of machine codes selected from the native instruction set for performing a selective update of the at least one partial-neuron weight in accordance with a predetermined learning rule and based at least in part on the deltas; and

wherein each compute engine comprises storage for the at least one partial-neuron weight.