Patent ID: 11942364
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 19:
20. The method of claim 15, further comprising:
performing a planarization process on the conductive material to form an interconnect, wherein the interconnect has a first pair of opposing sidewalls as viewed from a first cross-sectional view extending along a first direction and a second pair of opposing sidewalls as viewed from a second cross-sectional view extending along a second direction perpendicular to the first direction, the first direction and the second direction being both parallel to a top surface of the etch stop structure;
wherein the protective layer continuously extends from the etch stop structure to a top of the interconnect along the first pair of opposing sidewalls; and
wherein the protective layer continuously extends from the etch stop structure to an upper surface that is a non-zero distance below the top of the interconnect along the second pair of opposing sidewalls.