Patent ID: 11886709
Assignee: PARALLELS INTERNATIONAL GMBH
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A method, comprising:
receiving, by a processing device, a set of sequential memory access requests, each memory access request identifying a memory block by a memory block identifier;
identifying a sequence counter in dependence upon a predictive model and the memory block identifiers of the set of sequential memory access requests; and
performing an action; wherein
the predictive model comprises a memory access tracking data structure comprising a multi-dimensional array storing a plurality of sequence counters where a number of dimensions of the multi-dimensional array is established by the number of memory access requests within the set of sequential memory access requests, each sequence counter corresponding to a memory access sequence identified by an index vector, where the elements of the index vector are established by applying a pre-defined transformation to each memory block identifier of each memory block accessed by a memory access request within the set of sequential memory access requests; and
the number of sequential memory access requests within the set of sequential memory access requests is equal to or greater than 2.