Patent ID: 11928580
Assignee: GOOGLE LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 8:
9. A system, comprising:
one or more processing devices;
one or more non-transitory machine-readable storage devices for storing instructions that are executable by the one or more processing devices to cause performance of operations comprising:
generating multiple requests, each request having a respective transaction type indicating whether to read data from a memory or write data to a memory, wherein the memory includes one or more memory bank groups, each of the one or more memory bank groups including a plurality of memory banks;
for each request of two requests of the multiple requests that share a same transaction type of the multiple requests, generating a plurality of sub-requests;
generating a sequence of interleaved sub-requests that includes respective sub-requests of a first request of the two requests interleaved among respective sub-requests of a second request of the two requests wherein the sequence of interleaved sub-requests are generated to mitigate idle cycles of the memory by avoiding any two consecutive sub-requests in the sequence of interleaved sub-requests being routed to a same memory bank group, wherein generating the sequence of interleaved sub-requests comprises:
determining that a first sub-request in the sequence is a sub-request of the first request corresponding to a first memory bank group; and
in response to determining that the first sub-request corresponds to the first memory bank group, selecting, as a second sub-request that follows the first sub-request in the sequence, a sub-request from the second request corresponding to a second memory bank group different from the first memory bank group; and

performing data operations in the memory according to the sequence of interleaved sub-requests.