Patent ID: 11967366
Assignee: NUMEM INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 17:
18. A method, comprising:
storing data in pairs of rows of memory cells in an array, wherein each pair of rows comprises a first row of memory cells and a second row of memory cells;
providing the stored data to respective pluralities of logic gates in the array, wherein:
each plurality of logic gates is embedded in a respective pair of rows of memory cells,
respective logic gates of each plurality of logic gates are embedded in the respective pair of rows between successive memory cells along the first and second rows of the respective pair of rows, and
each logic gate of a respective plurality of logic gates comprises a first input coupled to a respective memory cell of the first row of the respective pair of rows, a second input coupled to a respective memory cell of the second row of the respective pair of rows, and an output; and

performing a computation, comprising:
selecting at least two rows of memory cells in the array, and
obtaining results of a logic operation provided by outputs of respective logic gates having inputs coupled to respective memory cells of the selected rows.