Patent ID: 11881255
Assignee: NVIDIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 18:
19. A multi-rank machine memory system comprising a plurality of memory ranks ganged on a shared IO channel, and further comprising:
a pair of selectors each coupled to input a plurality of multi-bit digital codes on separate busses;
a single 2:1 selector coupled to receive both of the digital codes output by the pair of selectors;
switching logic to select one of the digital codes output by the pair of selectors to an input of the 2:1 selector in advance of switching the memory ranks on the shared IO channel, and to select one of the digital codes to an IO control circuit coupled to an output of the 2:1 multiplexer in conjunction with switching the memory ranks; and
wherein the digital code configures a reference voltage or a reference current for an IO circuit.