Patent ID: 11892506
Assignee: MEDIATEK SINGAPORE PTE. LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 12:
13. A system comprising:
first and second circuits coupled to each other and operating with first and second clock signals in a multicycle phase relationship;
a first on-chip clock controller configured to modulate an on-chip clock signal to provide the first and second clock signals to the first and second circuits; and
a second on-chip clock controller configured to provide the on-chip clock signal to the first on-chip clock controller based on a scan clock signal,
wherein the first on-chip clock controller comprises
a first pulse shaper that receives the on-chip clock signal and outputs a first test clock enable signal, and
a second pulse shaper that receives the on-chip clock signal and outputs a second test clock enable signal.