Patent ID: 11901892
Assignee: MEDIATEK INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 1:
2. The level shifter as claimed in claim 1, wherein:
the first input transistor has a gate terminal controlled by the input signal, and a source terminal coupled to a ground;
the second input transistor has a gate terminal controlled by the inverse input signal, and a source terminal coupled to the ground;
the first series of transistors comprises a first transistor and a second transistor;
the first transistor has a source terminal coupled to a drain terminal of the first input transistor, and a gate terminal biased by a first voltage;
the second transistor has a source terminal coupled to a drain terminal of the first transistor, and a drain terminal coupled to the first voltage-drop circuit;
in response to the low-level state of the input signal, a gate terminal of the second transistor is biased by a voltage of the drain terminal of the second transistor;
the second series of transistors comprises a third transistor and a fourth transistor;
the third transistor has a source terminal coupled to a drain terminal of the second input transistor, and a gate terminal biased by the first voltage;
the fourth transistor has a source terminal coupled to a drain terminal of the third transistor, and a drain terminal coupled to the second voltage-drop circuit; and
in response to the high-level state of the input signal, a gate terminal of the fourth transistor is biased by a voltage of the drain terminal of the fourth transistor.