Patent ID: 11862561
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 8:
9. A method of forming a semiconductor device, the method comprising:
forming a first fin and a second fin over a first side of a substrate;
forming an isolation region adjacent the second fin;
etching the first fin to form a first recess;
etching the second fin to form a second recess;
depositing a sacrificial material in a portion of the second recess;
forming a first epitaxial region in the first recess and a second epitaxial region in the second recess;
forming a first contact plug over and electrically connected to the first epitaxial region;
forming a first interconnect structure over and electrically connected to the first contact plug;
etching a second side of the substrate to expose the sacrificial material;
planarizing the sacrificial material to be level with the isolation region and the first fin;
etching the sacrificial material to expose the second epitaxial region;
forming a first back-side via over and electrically connected to the second epitaxial region; and
forming a second interconnect structure over and electrically connected to the first back-side via.