Patent ID: 11948919
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 5:
6. The semiconductor package of claim 1, further comprising:
a plurality of second semiconductor structures stacked on an uppermost one of the plurality of first semiconductor structures and is offset from the plurality of first semiconductor structures in a second direction opposite to the first direction; and
a plurality of second adhesive layers disposed between pairs of second semiconductor structures of the plurality of second semiconductor structures,
wherein each of the plurality of second semiconductor structures includes a third sub-chip and a fourth sub-chip partially overlapping a top surface of the third sub-chip,
wherein for each pair of second semiconductor structures of the plurality of second semiconductor structures, there is a top semiconductor structure and a bottom semiconductor structure with a respective second adhesive layer disposed therebetween and the third sub-chip of the top semiconductor structure and the third sub-chip of the bottom semiconductor structure each contact the respective second adhesive layer and the fourth sub-chip of the top semiconductor structure and the fourth sub-chip of the bottom semiconductor structure are each spaced apart from the respective second adhesive laver, and
wherein a thickness of each of the plurality of second adhesive layers is less than a thickness of the fourth sub-chip.