Patent ID: 11894068
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 5:
6. The non-volatile memory device of claim 5, wherein, to perform the third hard bit read operation and to perform the second soft bit read operation on the first selected memory cell, the control circuit configured to:
bias the first selected memory cell at a second voltage level;
pre-charge the sense node to a second level;
discharge the sense node pre-charged to the second level through the first selected memory cell biased at the second voltage level for a third sensing interval;
determine the third hard bit value for the first selected memory cell based on an amount that the sense node discharges during the second sensing interval;
subsequent to discharging the sense node for the second sensing interval, continue discharging the sense node pre-charged to the second level through the first selected memory cell biased at the second voltage level for a second additional sensing interval; and
determine the second soft bit value for the first selected memory cell based on an amount that the sense node discharges during the combined second sensing interval and second additional sensing interval.