Patent ID: 11902192
Assignee: FUJITSU LIMITED
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. An apparatus for determining power, comprising:
a memory that stores a plurality of instructions;
a processor that couples to the memory and is configured to execute the instructions to:
configure UE with a counter related to power ramping commonly used by a synchronization signal block (SSB) and a channel state information reference signal (CSI-RS);
wherein the processor is further configured to:
configure the UE with a rule that whether a quasi co-location relationship between the CSI-RS and the SSB is taken into account in determining whether a selected CSI-RS is changed, and/or configure the UE with a rule for determining whether a selected CSI-RS is changed when the quasi co-location relationship between the CSI-RS and the SSB is taken into account and/or the quasi co-location relationship between the CSI-RS and the SSB.