Patent ID: 11948629
Assignee: MOSAID TECHNOLOGIES INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A non-volatile memory device comprising:
a plurality of memory banks, each memory bank comprising a plurality of blocks, each block comprising a plurality of pages, each page comprising a plurality of non-volatile memory cells;
a first input configured to receive a clock signal;
a second input configured to receive a chip select signal;
at least one common data interface configured to transfer at least one of command data, address data, write data, and read data when the chip select signal is at an active logic state, wherein the at least one of command data, address data, write data, and read data is transferred in synchronization with both rising and falling edges of the clock signal;
control circuitry configured to perform a concurrent bank operation in the plurality of memory banks, the concurrent bank operation comprises one of a concurrent page program operation, a concurrent page read operation, and a concurrent block erase operation; and
a status register configured to provide a status of the non-volatile memory device in response to the common data interface receiving a read status command set comprising a read status command data and a target device address data matching a device address of the non-volatile memory device;
wherein the status of the non-volatile memory device comprises a ready/busy status and a pass/fail status.