Patent ID: 11881457
Assignee: TAHOE RESEARCH, LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 18:
19. A semiconductor package comprising:
a substrate comprising:
alternating conducting layers and dielectric layers;
a first active electronic component disposed on an external surface of the substrate;
a second active electronic component at least partially embedded within the substrate;
a first interconnect region formed from a plurality of interconnects between the first active electronic component and the second electronic component;
a second interconnect region formed from a plurality of interconnects between the first active electronic component and the substrate; and
a third interconnect region formed from a plurality of interconnects between the second active electronic component and the substrate, the third interconnect region including an interposer which is distinct from the first active electronic component and spaced from the first active electronic component such that a gap, which extends an entire height of the interposer, exists between the interposer and the first active electronic component, wherein
the interconnects of the first region have a pitch ranging from about 20 microns to about 80 microns;
the interconnects of the second region have a pitch ranging from about 85 microns to about 350 microns; and
the interconnects of the third region have a pitch ranging from about 85 microns to about 350 microns.