Patent ID: 11923040
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A system comprising:
a plurality of memories, wherein each of the memories is configured to receive a plurality of multilevel command and address signals that represent a command structure including a command operand and memory addresses, the multilevel command and address signals having respective voltages corresponding to a non-binary value, wherein each of the plurality of memories includes:
a means of decoding the multilevel command and address signals into binary values;
a means of latching the binary values;
a means for providing internal command signals representing the command operand based on the binary values latched;
a means of decoding the binary values;
a means for providing internal address signals representing the memory addresses, the memory addresses including a plurality of bits based on the binary values decoded; and
a means for performing memory operations based on the internal command signals on memory locations based on the internal address signals.