Patent ID: 11972193
Assignee: SYNOPSYS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A system, comprising:
a memory storing instructions; and
at least one processor coupled with the memory to execute the instructions, the instructions when executed cause the processor to:
generate a plurality of commands for a physical verification job of a design, wherein the plurality of commands are related by a dependency graph;
allocate an initial amount of computing resources to execute the plurality of commands;
queue a subset of the plurality of commands for execution based on the dependency graph;
add an estimated amount of computing resources to the initial amount based on the number of the queued subset of commands and an estimated time to complete the queued subset of commands, wherein the estimated time is determined according to one or more of a length of a command chain for each command and a number of input layers that each command operates on in the queued subset of commands; and
release a portion of the estimated amount of computing resources in response to the portion of the estimated amount of computing resources being idle for an amount of time greater than a target time.