Patent ID: 11934480
Assignee: MACRONIX INTERNATIONAL CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 18:
19. The circuit of claim 17, wherein a multi-member set of bit lines in the plurality of bit lines is coupled to each NAND block in the plurality of NAND blocks, and
wherein a NAND block in the plurality of NAND blocks includes:
a plurality of NAND strings between its multi-member set of bit lines and its source line, the NAND strings having string select cells to selectively connect the NAND strings to corresponding bit lines in its multi-member set of bit lines, and a plurality of memory cells arranged in series, wherein bit lines in its multi-member set of bit lines are coupled to respective sets of NAND strings in the plurality of NAND strings;
word lines coupled to gates of memory cells in corresponding word line levels of the NAND block; and
string select lines coupled to gates of string select cells in corresponding rows of NAND strings in the plurality of NAND strings.