Patent ID: 11972111
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device comprising:
a memory cell array comprising a plurality of memory cells;
a voltage generator configured to generate voltages for one or more program operations and a verify operation, the one or more program operations and the verify operation being performed on the plurality of memory cells;
a control logic configured to perform a control operation on the plurality of memory cells so that a first program loop, and a second program loop are performed, the first program loop comprising a first program operation among the one or more program operations and a first verify operation, the second program loop comprising a second program operation among the one or more program operations, the second program operation being performed based on a compensation voltage level determined based on a result of the first verify operation; and
a plurality of bit lines connected to the memory cell array,
wherein the first verify operation comprises first even sensing and second even sensing on even-numbered bit lines among the plurality of bit lines, and first odd sensing and second odd sensing on odd-numbered bit lines among the plurality of bit lines;
wherein the control logic is further configured to
set a difference value between an on-cell number of the first even sensing and an on-cell number of the second even sensing as a first count value, and
set a difference value between an on-cell number of the first odd sensing and an on-cell number of the second odd sensing as a second count value,

the first count value corresponds to a first number of memory cells having a threshold voltage greater than a first voltage level of the first even sensing and less than a second voltage level of the second even sensing, and
the second count value corresponds to a second number of memory cells having a threshold voltage greater than the second voltage level of the first odd sensing and less than a third voltage level of the second odd sensing.