Patent ID: 11894372
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A method of fabricating a device, the method comprising:
forming a first semiconductor fin;
forming a first source-drain epitaxial region adjacent a first portion of the first semiconductor fin;
forming a second source-drain epitaxial region adjacent a second portion of the first semiconductor fin;
forming a first gate conductor above the first semiconductor fin;
forming a gate spacer covering the sides of the gate conductor;
forming a second semiconductor fin below the first semiconductor fin;
forming a second gate conductor on a first side of the second semiconductor fin and a third gate conductor on a second side of the second semiconductor fin;
forming a third source-drain epitaxial region adjacent a first portion of the second semiconductor fin;
forming a fourth source-drain epitaxial region adjacent a second portion of the second semiconductor fin; and
forming a dielectric isolation structure below the first semiconductor fin and above the second semiconductor fin and separating the first semiconductor fin and the second semiconductor fin.