Patent ID: 11869972
Assignee: INVENTION AND COLLABORATION LABORATORY PTE. LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. A transistor structure comprising:
a gate structure based on a semiconductor substrate, wherein the semiconductor substrate includes a semiconductor surface and is made of a first semiconductor material;
a channel region under the semiconductor surface, the channel region including a first terminal and a second terminal;
a drain region independent from the semiconductor substrate, the drain region including a first predetermined physical boundary directly connected to the first terminal of the channel region;
a source region independent from the semiconductor substrate, the source region including a second predetermined physical boundary directly connected to the second terminal of the channel region;
a first etched concave having a first side barrier to reveal a first side seed portion of the first semiconductor material, wherein a first isolator is positioned above a bottom of the first etched concave and the drain region is above the first isolator, a lower portion of the drain region is selectively grown from the first side seed portion and without grown from any bottom seed portion, and there is no isolation layer exists in the drain region; and
a second etched concave having a second side barrier to reveal a second side seed portion of the first semiconductor material, wherein a second isolator is positioned above a bottom of the second etched concave and the source region is above the second isolator, and a lower portion of the source region is selectively grown from the second side seed portion without grown from any bottom seed portion.