Patent ID: 11950454
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G  H | IPC H

Claim 18:
19. A display panel, comprising:
a base substrate; and
pixel circuits arranged in an array on the base substrate, wherein each row of pixel circuits comprises a gate line extending in a row direction, each column of pixel circuits comprises a data line extending in a column direction, the gate line and the data line are disposed on different layers,
wherein the display panel comprises a light transmittance region and a display region around the light transmittance region, the pixel circuits are disposed in the display region, the gate line of each row of m rows of pixel circuits is divided into a first gate line portion and a second gate line portion by the light transmittance region, the first gate line portion is connected to the second gate line portion by an auxiliary gate line, at least part of the auxiliary gate line extends along an edge of the light transmittance region, wherein m is a natural number and m≥2,
wherein the data line of each column of n columns of pixel circuits is divided into a first data line portion and a second data line portion by the light transmittance region, the first data line portion is connected to the second data line portion by an auxiliary data line, wherein n is a natural number and n≥2,
wherein the auxiliary gate line comprises an auxiliary gate line sub-portion, the auxiliary gate line sub-portion and the auxiliary data line have an overlapped region,
wherein the m rows of pixel circuits comprise at least two rows of pixel circuits, an overlapped area of the auxiliary gate line sub-portion of the auxiliary gate line for connecting the first gate line portion and the second gate line portion in one row of the at least two rows of pixel circuits and the auxiliary data line is different from an overlapped area of the auxiliary gate line sub-portion of the auxiliary gate line for connecting the first gate line portion and the second gate line portion in the other one row of the at least two rows of pixel circuits and the auxiliary data line,
wherein each row of pixel circuits further comprises a light emitting control line extending in the row direction, the light emitting control line and the gate line are disposed in the same layer and parallel to each other, the light emitting control line of each row of the m rows of pixel circuits is divided into a first light emitting control line portion and a second light emitting control line portion by the light transmittance region, end portions of the first light emitting control line portion and the second light emitting control line portion close to the light transmittance region are suspended.