Patent ID: 11936387
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A method of operating a duty-cycle correcting and phase shifting circuit, comprising:
receiving a clock input signal by a delay-controlled delay line (DCDL) circuit;
adjusting, by a duty-cycle corrector (DCC) circuit operably connected to an output of the DCDL circuit, a duty cycle of the clock input signal;
controlling, by an output signal of a control circuit operably connected to an input of the DCDL circuit, an amount of delay generated by the DCDL circuit; and
controlling an output of the control circuit through an output signal of a lock detector circuit operably connected between a first input of the control circuit and a first output of a comparator circuit.