Patent ID: 11916022
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 16:
17. A processing system, comprising:
a bonding apparatus configured to bond a first wafer to a second wafer, wherein a plurality of first alignment marks is disposed on the first wafer and a plurality of second alignment marks is disposed on the second wafer;
a thinning apparatus configured to perform a trimming process on the first wafer, wherein before the trimming process the first wafer comprises a first notch on a circumferential edge of the first wafer and the second wafer comprises a second notch on a circumferential edge of the second wafer, wherein the thinning apparatus is configured to remove the first notch while leaving the second notch in place; and
a photolithography tool configured to perform one or more photolithography processes to form patterned layers on the first wafer, wherein the photolithography tool adjusts a location of one or more photomasks based on locations of the first and second alignment marks during the one or more photolithography processes.