Patent ID: 11894262
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A method of fabricating an integrated circuit, the method comprising:
forming a first fin comprising semiconductor material and having an upper portion and a lower portion;
forming a first spacer adjacent and in contact with opposing sidewalls of the lower portion of the first fin, the first spacer having an uppermost surface and a bottommost surface;
forming a second fin comprising semiconductor material and having an upper portion and a lower portion;
forming a second spacer adjacent and in contact with opposing sidewalls of the lower portion of the second fin, the second spacer having an uppermost surface and a bottommost surface; and
forming an insulation structure between the first spacer and the second spacer, the insulation structure being distinct from the first and second spacers, the insulation structure having an uppermost surface above the uppermost surface of the first spacer and above the uppermost surface of the second spacer, and the insulation structure having a bottommost surface co-planar with the bottommost surface of the first spacer and co-planar with the bottommost surface of the second spacer.