Patent ID: 11881243
Assignee: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G  H

Claim 7:
8. A semiconductor device comprising:
a memory cell array including a multiplicity of memory cells coupled between a plurality of word lines and one or more bit lines; and
an operation circuit configured to perform a multiplication and accumulation (MAC) operation with one or more first multi-bit data provided from the one or more bit lines and one or more second multi-bit data,
wherein a plurality of memory cells is coupled to each of the one or more bit lines, and the plurality of memory cells store a plurality of bits included in a corresponding one of the one or more first multi-bit data,
wherein the memory cell array sequentially provides the plurality of bits included in the corresponding first multi-bit data to the operation circuit,
wherein the operation circuit includes one or more unit operation circuits respectively corresponding to the one or more bit lines, and
wherein each of the one or more unit operation circuits includes a unit capacitor and a unit accumulation capacitor selectively coupled to the unit capacitor for charge redistribution.