Patent ID: 11948981
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A method comprising:
forming a source/drain region on a side of a semiconductor region; and
forming a gate stack over the semiconductor region, the forming the gate stack comprising:
forming a gate dielectric;
forming a work-function layer over the gate dielectric, wherein the work-function layer comprises:
a bottom portion over the gate dielectric;
a first sidewall portion and a second sidewall portion over and connecting to opposite ends of the bottom portion, wherein the first sidewall portion and the second sidewall portion grow toward each other and merge with each other at a point; and

after the first sidewall portion and the second sidewall portion are merged, filling a silicon-containing layer into the work-function layer, the silicon-containing layer comprising:
a first sidewall contacting the first sidewall portion; and
a second sidewall contacting the second sidewall portion.