Patent ID: 11908508
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device, comprising:
a memory array including a first memory region and a second memory region,
wherein:
the memory device is configured to write first data to the memory array in accordance with a programming sequence by writing the first data to volatile memory cells of the first memory region before volatile memory cells of the second memory region,
the programming sequence is defined prior to the memory device writing the first data to the volatile memory cells of the first memory region,
the programming sequence defines an order of memory locations in the memory device to which the memory device sequentially writes the first data, the first memory region being positioned ahead of the second memory region in the order of the memory locations; and
the memory device is configured to update the programming sequence after writing the first data, such that the memory device is configured to write second data to volatile memory cells of the second memory region before writing the second data to volatile memory cells of the first memory region.