Patent ID: 11954585
Assignee: ZJU-HANGZHOU GLOBAL SCIENTIFIC AND TECHNOLOGICAL INNOVATION CENTER
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 3:
4. The multi-mode array structure for in-memory computing according to claim 3, wherein the first memristor, the second memristor, the first transistor, and the second transistor are prepared through an integrated process, the first memristor is provided on a drain electrode surface of the first transistor, the second memristor is provided on a drain electrode surface of the second transistor, and a shallow trench isolation region is further provided between the first transistor and the second transistor, wherein the process for preparing the first memristor, second memristor, first transistor, and second transistor comprises:
forming the shallow trench isolation region, and an n-well region corresponding to the first transistor and a p-well region corresponding to the second transistor, respectively, on both sides of the shallow trench isolation region on the basis of a complementary-metal-oxide-semiconductor (CMOS) front-end process; forming a gate electrode, a source electrode, and a drain electrode corresponding to the first transistor on a surface of and inside the n-well region, and forming a gate electrode, a source electrode, and a drain electrode corresponding to the second transistor on a surface of and inside the p-well region, so as to obtain the first transistor and the second transistor;
forming a dielectric layer on surfaces of the first transistor and the second transistor, forming a first contact hole perpendicular to the drain electrode surface of the first transistor and a second contact hole perpendicular to the drain electrode surface of the second transistor, respectively, in a dielectric region through an etching process, depositing a first oxide layer and a second oxide layer, respectively, in the first contact hole and the second contact hole, filling the first contact hole and the second contact hole with a metal filler to form a first metal filler layer on a surface of the first oxide layer and a second metal filler layer on a surface of the second oxide layer, so as to obtain the first memristor positioned on the drain electrode surface of the first transistor and comprising the first oxide layer and the first metal filler layer, and a second memristor positioned on the drain electrode surface of the second transistor and comprising the second oxide layer and the second metal filler layer; and
completing the preparation on the basis of a complementary-metal-oxide-semiconductor (CMOS) back-end process.