Patent ID: 11961821
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A semiconductor device assembly, comprising:
a package substrate having an upper surface with an upper surface area;
a first shingled stack including a plurality of first semiconductor dies, each first semiconductor die of the plurality having a first length and a first width, the first shingled stack overlying a first area of the package substrate;
a second shingled stack including a plurality of second semiconductor dies, each second semiconductor die of the plurality having a second length and a second width, the second shingled stack overlying a second area of the package substrate different from the first area; and
an encapsulant at least partially encapsulating the package substrate, the first shingled stack and the second shingled stack,
wherein the first length is different than the second length and the second width.