Patent ID: 11972139
Assignee: PHISON ELECTRONICS CORP.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. A memory storage device, comprising:
a connection interface unit, configured to couple to a host system;
a rewritable non-volatile memory module, comprising a plurality of physical units; and
a memory control circuit unit, coupled to the connection interface unit and
the rewritable non-volatile memory module, wherein
the memory control circuit unit is configured to use a first read voltage level as an initial read voltage level to perform a first data read operation on a first physical unit among the physical units to obtain a second read voltage level used to successfully read the first physical unit,
the memory control circuit unit is further configured to record association information between the first read voltage level and the second read voltage level in a transient look-up table,
the memory control circuit unit is further configured to perform a second data read operation according to a read level tracking table and the association information recorded in the transient look-up table, wherein
the read level tracking table records a plurality of optimal read voltage levels of the physical units, wherein the plurality of optimal read voltage levels are the read voltage levels which are used to read the data of the physical unit and decode successfully, and
wherein in the operation of recording the association information between the first read voltage level and the second read voltage level in the transient look-up table,
the memory control circuit unit is further configured to count a number of times that the first read voltage level and the second read voltage level are associated to generate a count value, and the memory control circuit unit is further configured to record the count value in the transient look-up table.