Patent ID: 11886622
Assignee: UNIVERSITY OF CINCINNATI
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A THx2 threshold gate cell comprising:
a mode-independent PMOS configuration;
an NMOS configuration configured to operate in one of a TH12 mode and a TH22 mode, wherein x is a threshold of 1 for the TH12 mode and x is a threshold of 2 for the TH22 mode;
a memory cell configured to transmit a signal M and a logical inverse signal Mb; and
a base cell configured to receive the signal M and the logical inverse signal Mb, wherein:
the NMOS is configuration configured to operate in one of the TH12 mode and the TH22 mode based on an NMOS programmed configuration;
the NMOS programmed configuration is programmed such that (i) a value of 1 on the signal M and a value of 0 on the logical inverse signal Mb from the memory cell is configured to operate the base cell in the TH12 mode and (ii) a value of 0 on the signal M and a value of 1 on the logical inverse signal Mb from the memory cell is configured to operate the base cell in the TH22 mode;
two NMOS transistors in the base cell are configured to receive the value of 1 on the signal M such that a pair of NMOS transistors in the base cell are configured to receive respective inputs and be connected in parallel in the TH12 mode; and
one NMOS transistor in the base cell is configured to receive the value of 1 on the logical inverse signal Mb such that the pair of NMOS transistors in the base cell configured to receive respective inputs are configured to be connected in series in the TH22 mode.