Patent ID: 11942468
Assignee: CIRRUS LOGIC INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 18:
19. A method, comprising:
forming a plurality of dies on a wafer by performing steps comprising:
forming a first high-voltage circuit configured to amplify a first input signal and output a first output signal;
forming a second high-voltage circuit configured to amplify a second input signal and output a second output signal,
wherein the first high-voltage circuit and the second high-voltage circuit are positioned symmetrically around an axis; and
forming a low-voltage circuit positioned between the first high-voltage circuit and the second high-voltage, wherein the low-voltage circuit comprises circuitry organized in columns oriented along the axis;

packaging the plurality of dies on the wafer, wherein the packaging comprises:
forming a package terminal array for each of the plurality of dies;
coupling the first high-voltage circuit to a first terminal for outputting the first signal; and
coupling the second high-voltage circuit to a second terminal for outputting the second signal,
wherein the first terminal and the second terminal are located at an edge of the package terminal array.