Patent ID: 11861012
Assignee: MACRONIX INTERNATIONAL CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A memory device, comprising:
a plurality of non-volatile registers storing address information for a first copy boot code and at least one redundant copy boot code stored in a memory array;
a non-volatile storage area that keeps a hash digest;
an input/output interface for posting internal status register states to I/O data units;
data path circuits connected between non-volatile registers, the memory array, the non-volatile storage area, and the input/output interface; and
logic circuitry that examines integrity of the first copy boot code stored in the memory array by implementing (i) a first tier hash for determining an initial integrity of the first copy boot code and (ii) a second tier hash using a message digest algorithm for integrity checking an entirety of the first copy boot code and comparing a hash calculation of the first copy boot code and a stored hash calculation determined and stored in the non-volatile storage area holding the hash digest and providing as output one selected from the first copy boot code or the redundant copy boot code in accordance with an integrity examination result.