Patent ID: 11923287
Assignee: KIOXIA CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for manufacturing a semiconductor device, comprising:
forming a release layer, a first barrier layer, a conductive layer, and a second barrier layer on a support substrate;
forming a first insulating layer on the second barrier layer, a first opening being formed in the first insulating layer;
forming a second opening in the second barrier layer by etching using the first insulating layer as a mask, the second opening communicating with the first opening;
forming a first electrode inside the second opening and inside a lower portion of the first opening;
forming a third barrier layer on an inner surface of an upper portion of the first opening;
forming a first via inside an upper portion of the first opening and forming an interconnect on the first insulating layer, a resistivity of the interconnect being lower than a resistivity of the third barrier layer;
forming a second insulating layer on the interconnect, a third opening being formed in the second insulating layer;
forming a second via inside the third opening, the second via being connected to the interconnect;
forming a second electrode on the second via, the second electrode being connected to the second via;
connecting a chip to the second electrode;
removing the support substrate by removing the release layer; and
removing the first barrier layer, the conductive layer, and the second barrier layer.