Patent ID: 11955481
Assignee: STMICROELECTRONICS (CROLLES 2) SAS
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A microelectronic device that includes a PNP transistor and an NPN transistor, comprising:
a semiconductor substrate that is P-type doped;
an N+ doped isolating well for the PNP transistor in the semiconductor substrate;
a first epitaxial semiconductor layer on the semiconductor substrate and extending over the N+ doped isolating well;
a P+ doped region including a first portion in the N+ doped isolating well and a second portion in the first epitaxial semiconductor layer;
an N+ doped well of the NPN transistor passing through the first epitaxial semiconductor layer and extending partially into the semiconductor substrate;
a second epitaxial semiconductor layer on and in contact with both the first epitaxial semiconductor layer and the N+ doped well of the NPN transistor;
a P doped region including a third portion in the second epitaxial semiconductor layer and a fourth portion in the first epitaxial semiconductor layer, wherein the P doped region provides a collector of the PNP transistor, and wherein said fourth portion of the P doped region is in electrical contact with the P+ doped region in the N+ doped isolating well;
a base region for the PNP transistor in contact with the P doped region;
an N doped region in the second epitaxial semiconductor layer that provides a collector of the NPN transistor, wherein the N doped region is in electrical contact with the N+ doped well; and
a base region for the NPN transistor in contact with the N doped region.