Patent ID: 11942558
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. A method of forming a semiconductor device, the method comprising:
forming sacrificial layers and first semiconductor layers alternately and repeatedly on a transistor region on a substrate including first, second, and third transistor regions;
patterning the sacrificial layers and the first semiconductor layers to form first, second and third preliminary channel regions on the first, second, and third transistor regions respectively, the first, second and third preliminary channel regions each including first semiconductor patterns and preliminary sacrificial patterns;
forming dummy gates on the first, second and third preliminary channel regions;
patterning the first, second and third preliminary channel regions to forma first channel portion, second channel portions, third channel portions and sacrificial patterns;
forming source and drain regions on opposite sidewalls of the dummy gates;
removing the dummy gates and the sacrificial patterns to form first, second, and third trenches on the first, second, and third transistor regions;
forming a gate insulation layer and a gate electrode in each of the first, second, third trenches,
wherein a second width of the second channel portions is greater than a first width of the first channel portion,
wherein a third width of the third channel portions is greater than the second width of the second channel portions,
wherein the first channel portion is connected to the substrate and has a shape of a fin protruding from an upper surface of the substrate,
wherein the second channel portions are spaced apart from each other in a first direction, perpendicular to the upper surface of the substrate, and
wherein the third channel portions are spaced apart from each other in the first direction.