Patent ID: 11882706
Assignee: SANDISK TECHNOLOGIES, INC.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 18:
19. A memory array comprising: a first memory level comprising a plurality of first memory cells each comprising a corresponding magnetic memory element coupled in series with a corresponding selector element, each first memory cell coupled to and disposed above or below a corresponding one of a plurality of first vias each having four concave vertical sidewalls; and a second memory level disposed above the first memory level, the second memory level comprising a plurality of second memory cells each comprising a corresponding magnetic memory element coupled in series with a corresponding selector element, each second memory cell coupled to and disposed above or below a corresponding one of a plurality of second vias each having four concave vertical sidewalls, wherein each memory cell comprises a half-pitch F, and comprises an area between 2F2 and 4F2.