Patent ID: 11908866
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A method comprising:
forming a gate dielectric layer in a gate opening, wherein the gate opening exposes a first transistor region, a second transistor region, and a boundary region between the first transistor region and the second transistor region;
depositing a first work function layer in the gate opening, wherein the first work function layer is disposed over the gate dielectric layer in the first transistor region, the second transistor region, and the boundary region;
after removing the first work function layer from the first transistor region, depositing a second work function layer in the gate opening, wherein the second work function layer is disposed over the gate dielectric layer in the first transistor region and the first work function layer in the second transistor region and the boundary region;
after removing the second work function layer from the first transistor region and the second transistor region, depositing a third work function layer in the gate opening, wherein the third work function layer is disposed over the gate dielectric layer in the first transistor region, the first work function layer in the second transistor region, and the second work function layer in the boundary region; and
depositing a fourth work function layer in the gate opening, wherein the fourth work function layer is disposed over the third work function layer in the first transistor region and the third work function layer in the second transistor region; and
performing a planarization process to remove excess of the first work function layer, the second work function layer, the third work function layer, and the fourth work function layer.