Patent ID: 11893276
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. An apparatus comprising:
a plurality of memory blocks;
a first data bus coupled to the plurality of memory blocks;
a second data bus coupled to the plurality of memory blocks and configured to transfer fuse data from a fuse array in a power-up sequence;
a controller configured to perform memory read and write operations on the plurality of memory blocks via the first data bus, and further configured to provide a data transfer command responsive to at least a memory full alert signal; and
a non-volatile storage (NVS) data transfer circuit configured to transfer data in a first memory block of the plurality of memory blocks to a NVS device via the second data bus, and further configured to transfer the data in the first memory block responsive to the data transfer command from the controller.