Patent ID: 11908526
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 12:
13. The method according to claim 11, wherein
the semiconductor memory device includes:
a semiconductor substrate;
a first conductive layer arranged above the semiconductor substrate;
a second conductive layer arranged above the first conductive layer;
a first insulating layer arranged above the semiconductor substrate, extending in a first direction parallel to the semiconductor substrate, dividing the first conductive layer, and dividing the second conductive layer;
a second insulating layer arranged above the first conductive layer, extending in the first direction, not dividing the first conductive layer, and dividing the second conductive layer; and
a first pillar and a second pillar that are provided above the semiconductor substrate and penetrate the first conductive layer and the second conductive layer,

wherein the first pillar includes the first memory cell, and the second pillar includes the second memory cell, and
in a second direction parallel to the semiconductor substrate and perpendicular to the first direction, the second pillar is farther from the first insulating layer than the first pillar is.