Patent ID: 11861181
Assignee: BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory system comprising:
a redundancy comparator configured to detect differences between data stored redundantly in a first memory, a second memory, and a third memory, the redundancy comparator further configured to identify a memory error based on the detected differences;
an error collection buffer configured to store a memory address associated with the memory error;
a memory scrubber circuit configured to overwrite, at the memory address associated with the memory error, erroneous data with corrected data, the corrected data generated based on a majority vote performed among the first memory, the second memory, and the third memory; and
a priority arbitrator configured to arbitrate between the overwriting performed by the memory scrubber and a functional memory access associated with software execution performed by a processor configured to utilize the memory system.