Patent ID: 11875844
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. The memory device of claim 1, wherein the second inverter includes a first transistor and a second transistor,
wherein the first transistor includes a first end to which a first voltage is applied through a fourth wire, a gate to which the second signal is applied, and a second terminal connected with the second transistor,
wherein the second transistor includes a first end connected with the second end of the first transistor, a gate to which the second signal is applied, and a second end connected with a ground terminal,
wherein the fourth wire is similar to the plurality of bit lines,
wherein a length of the fourth wire is n % of a length of the memory cell array in a column direction,
wherein the “n” is a positive integer of 100 or less, and
wherein the first transistor is a PMOS transistor, and the second transistor is an NMOS transistor.