Patent ID: 11967595
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC B  H

Claim 7:
8. A semiconductor device comprising:
a substrate;
a plurality of nanowires extending in a first direction and spaced apart from each other on the substrate, the plurality of nanowires including a first nanowire that is an uppermost nanowire of the plurality of nanowires;
a gate insulating layer surrounding each of the plurality of nanowires;
a gate electrode extending in a second direction intersecting the first direction and surrounding each of the plurality of nanowires, on the gate insulating layer;
a source/drain on a sidewall of the gate electrode;
a gate spacer between the gate electrode and the source/drain,
wherein the gate spacer includes:
a first inner spacer on a bottom surface the first nanowire;
a second inner spacer on a top surface of the first nanowire; and
an outer spacer on a top surface of the second inner spacer,

wherein the outer spacer includes a first insulating material, and
wherein the first inner spacer and the second inner spacer include a second insulating material different from the first insulating material.