Patent ID: 11907007
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. A method, comprising:
forming a circuit region over a substrate, the circuit region comprising:
a plurality of active regions extending along a first axis, and
a plurality of gate regions extending across the plurality of active regions and along a second axis transverse to the first axis; and

forming a plurality of metal patterns over the circuit region, and electrically coupling the plurality of metal patterns to form a clock mesh structure, wherein
the clock mesh structure comprises, in a first metal layer over the circuit region,
at least one first metal pattern among the plurality of metal patterns,
the at least one first metal pattern is oblique to both the first axis and the second axis, and
said method further comprises forming, in the first metal layer,
at least one first signal metal pattern extending along one of the first axis and the second axis, and
a first keep-out region which is elongated along the at least one first metal pattern, within which an entirety of the at least one first metal pattern is arranged, and within which the at least one first signal metal pattern is not arranged.