Patent ID: 11923840
Assignee: NXP B.V.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 17:
18. A circuit, comprising:
a power down signal generator configured to generate a power down signal, the power down signal generator comprising:
a detection transistor configured to receive a first supply voltage in a first voltage domain;
a protection transistor that is coupled in series with the detection transistor, and configured to receive (i) a target current and (ii) a first bias voltage that is derived from a second supply voltage in a second voltage domain, wherein the first bias voltage is such that a drain voltage of the detection transistor is maintained within a tolerance limit thereof;
a first resistor coupled in series with the detection transistor, wherein the first resistor has a control voltage generated thereacross based on a first part of the target current; and
a compensation transistor that is coupled in parallel to the first resistor, and configured to (i) receive a second bias voltage that is derived from the second supply voltage and (ii) sink, based on the second bias voltage, a second part of the target current to maintain the control voltage within a first predefined range,
wherein a variation in the second supply voltage results in a variation in the target current and the second bias voltage, and based on the variation in the target current and the second bias voltage, a magnitude of the second part of the target current sunk by the compensation transistor is controlled such that the control voltage is maintained within the first predefined range,
wherein an operational state of the detection transistor is controlled based on the first supply voltage and the control voltage, and
wherein the generation of the power down signal is controlled based on the operational state of the detection transistor.