Patent ID: 11862588
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. A method comprising:
depositing a first passivation layer on a semiconductor substrate;
forming a first redistribution line and a second redistribution line on and extending lengthwise along the first passivation layer in a same direction of a top-down view;
forming a first dielectric layer on the first redistribution line and the second redistribution line;
patterning a first opening and a second opening in the first dielectric layer, the first opening exposing the first redistribution line, the second opening exposing the second redistribution line;
forming an under bump metallization in the first opening and the second opening, the under bump metallization overlapping the first redistribution line and the second redistribution line; and
bonding a package substrate to the under bump metallization with a conductive connector.