Patent ID: 11915057
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. An apparatus comprising:
a first, interconnection network;
a processor coupled to the first, interconnection network;
a second, packet network;
a third, synchronous network;
a network interface circuit coupled to the first, interconnection network; and
a plurality of configurable circuits arranged in an array and coupled through the network interface circuit to the first, interconnection network, each configurable circuit of the plurality of configurable circuits coupled to the first, synchronous network and to the second, packet network, each configurable circuit of the plurality of configurable circuits comprising:
a configurable computation circuit;
a configuration memory coupled to the configurable computation circuit, the configuration memory comprising:
a first instruction memory configured to store a first plurality of configuration instructions to configure the configurable computation circuit; and
a second instruction memory configured to store a second plurality of configuration instructions or instruction indices for selection of a configuration instruction of the first plurality of configuration instructions from the first instruction memory and for selection of a network input from the third, synchronous network for receipt of the configuration instruction or a configuration instruction index from another configurable circuit of the plurality of configurable circuits of the array;, and
a dispatch interface circuit coupled to the plurality of configurable circuits through the second, packet network, the dispatch interface circuit configured to partition the plurality of configurable circuits of the array into a plurality of partitions of configurable circuits and to load one or more computation kernels into one or more configurable circuits of the plurality of partitions of configurable circuits.