Patent ID: 11960758
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. In a storage system comprising a memory comprising a plurality of single-level cell (SLC) blocks and a quad-level cell (QLC) block, a method comprising:
determining how many SLC blocks are available for folding; and
in response to determining that two SLC blocks are available for folding:
determining whether lower and middle pages of the QLC block have been programmed;
in response to determining that the lower and middle pages of the QLC block have not been programmed;
programming the lower and middle pages of the QLC block with the two SLC blocks; and then
in response to the lower and middle pages of the QLC block being programmed successfully:
releasing the two SLC blocks; and then programming upper and top pages of the QLC block; and

in response to determining that the lower and middle pages of the QLC block have been programmed, programming the upper and top pages of the QLC block with the two SLC blocks.