Patent ID: 11869570
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A semiconductor memory comprising a refresh counter circuit, wherein the refresh counter circuit comprises:
a first signal generator, configured to generate a first carry signal according to each of refresh pulse signals generated by a received refresh command;
a second signal generator, configured to generate a second carry signal according to a last refresh pulse signal generated by the received refresh command;
a first counter, configured to perform signal inversion according to the first carry signal and generate a first output signal;
a second counter, configured to count the received refresh command according to the second carry signal and generate a second output signal; and
an output unit, configured to output a third output signal according to the first output signal and the second output signal, the third output signal representing a count of the refresh pulse signals;
wherein the received refresh command generates at least two refresh pulse signals;
the received refresh command is an all bank refresh command or a per bank refresh command,
each of the refresh pulse signals generated by the all bank refresh command is used to refresh all banks simultaneously;
each of the refresh pulse signals generated by the per bank refresh command is used to refresh all banks one by one before repeating refresh of any bank; and
the second signal generator is specifically configured to generate the second carry signal according to a last refresh pulse signal generated by the received refresh command of a last bank; wherein for each of the per bank refresh commands, when a bank counter counts to the last bank, the second signal generator generates the second carry signal according to the last refresh pulse signal generated by the per bank refresh command of the last bank.