Patent ID: 11961824
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A semiconductor package comprising:
a package substrate including an upper surface with a bonding pad;
a first lower semiconductor chip disposed on the upper surface of the package substrate, wherein an upper surface of the first lower semiconductor chip includes a connect edge region including a connection pad and an open edge region including a dam structure;
a bonding wire having a first height above the upper surface of the first lower semiconductor chip and connecting the bonding pad and the connection pad;
an upper semiconductor chip disposed on the upper surface of the first lower semiconductor chip using an inter-chip bonding layer; and
a molding portion on the package substrate and substantially surrounding the first lower semiconductor chip and the upper semiconductor chip,
wherein the dam structure includes dummy bumps disposed in the open edge region, and dummy wires extending between adjacent ones of the dummy bumps and having a second height above the upper surface of the first lower semiconductor chip.