Patent ID: 11903210
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 9:
10. A semiconductor memory device, comprising:
a first chip having a first bonding surface extending in a first direction and a second direction crossing the first direction, the first chip including:
a plurality of word lines each extending in the first direction and the second direction and stacked in a third direction alternately with a plurality of insulating films, the third direction crossing the first direction and the second direction, the word lines including:
a first word line, the first word line having a first end at one side in the first direction,
a second word line provided at one side of the first word line in the third direction, the second word line having a second end at the one side in the first direction,
a third word line provided at the one side of the second word line in the third direction, the third word line having a third end at the one side in the first direction,
a fourth word line provided at the one side of the third word line in the third direction, the fourth word line having a fourth end at the one side in the first direction,
a fifth word line provided at the one side of the fourth word line in the third direction, the fifth word line having a fifth end at the one side in the first direction, and
a sixth word line provided at the one side of the fifth word line in the third direction, the sixth word line having a sixth end at the one side in the first direction, the first word line and the second word line neighboring each other in the third direction, the third word line and the fourth word line neighboring each other in the third direction, the fifth word line and the sixth word line neighboring each other in the third direction, a first distance from the first end of the first word line to the second end of the second word line in the first direction being smaller than a second distance from the third end of the third word line to the fourth end of the fourth word line in the first direction, and the second distance from being larger than a third distance from the fifth end of the fifth word line to the sixth end of the sixth word line in the first direction,

a semiconductor pillar piercing the word lines in the third direction,
a charge storage member provided between the semiconductor pillar and the word lines,
a plurality of first pads having first pad faces, respectively, aligned with the first bonding surface, and
a plurality of contact plugs each extending in the third direction to reach a corresponding one of the word lines and being electrically connected to a corresponding one of the first pads; and

a second chip having a second bonding surface extending in the first direction and the second direction, the second chip including:
a semiconductor substrate,
a plurality of transistors formed in the semiconductor substrate and aligned along the first direction, each of the transistors having a source, a drain, and a gate electrode, and the source, the gate electrode, and the drain of each of the transistors being aligned along the second direction, the transistors including:
a first transistor at least partially overlapping with the sixth word line when viewed in the third direction, and
a second transistor at least partially overlapping with the sixth word line when viewed in the third direction, and

a plurality of second pads having second pad faces, respectively, aligned with the second bonding surface, and each being electrically connected to the source or the drain of a corresponding one of the transistors, wherein

the first pads of the first chip and the second pads of the second pads are bonded, respectively, and
a distance between a geometric center of the first transistor and a geometric center of the second transistor in the first direction is longer than each of the first distance and the third distance and shorter than the second distance.