Patent ID: 11899970
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. An electronic device comprising:
processors, memory devices, and a switch configured to connect the processors and the memory devices,
wherein at least one of the memory devices includes: a first memory of a first type;
a second memory different of a second type different from the first type; and
a memory controller configured to
receive a plurality of access requests from at least one of the processors through the switch,
receive workload information from the at least one of the processors, wherein the workload information includes at least one latency/throughput requirement associated with the plurality of access requests,
process the plurality of access requests using the workload information, and
access at least one of the first memory and the second memory using the plurality of access requests,

wherein the memory controller outputs latency/busy information for at least one of the processors, and at least one of the processors performs scheduling of work using the latency/busy information, and
wherein the memory controller is further configured to count elapsed latencies after receipt of the plurality of access requests.