Patent ID: 11869766
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 16:
17. A method, comprising:
forming a transistor over a substrate;
forming a first conductive via electrically coupled to the transistor;
depositing a seed layer having an amorphous crystal phase over the first conductive via;
treating a surface of the seed layer, wherein after the treating the seed layer includes an oxide form of a first element and having at least one of a tetragonal crystal phase and an orthorhombic crystal phase;
depositing a stack of dielectric layers over the seed layer;
depositing a capping layer over the stack of dielectric layers;
performing a thermal operation on the stack of dielectric layers at a temperature at which the first conductive via functions properly; and
cooling the stack of dielectric layers to thereby cause the stack of dielectric layers to be a ferroelectric layer.