Patent ID: 11955547
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. An integrated circuit device comprising:
a first high-k/metal gate stack disposed between first raised source/drain epitaxy features, wherein the first high-k/metal gate stack and the first raised source/drain epitaxy features are disposed over a substrate;
a second high-k/metal gate stack disposed between second raised source/drain epitaxy features, wherein the second high-k/metal gate stack and the second raised source/drain epitaxy features are disposed over the substrate;
a shallow trench isolation structure disposed within the substrate;
first L-shaped spacer liners disposed along sidewalls of the first high-k/metal gate stack and second L-shaped spacer liners disposed along sidewalls of the second high-k/metal gate stack, wherein each of the first L-shaped spacer liners and the second L-shaped spacer liners has a first sidewall surface interfacing with a respective sidewall of the first high-k/metal gate stack or the second high-k/metal gate stack, a second sidewall surface that opposes the first sidewall surface and extends to a same height as the first sidewall surface, a first top surface extending from the first sidewall surface to the second sidewall surface, a second top surface extending orthogonally from the second sidewall surface to a respective one of the first raised source/drain epitaxy features or the second raised source/drain epitaxy features, and a third sidewall surface extending from the second top surface to the substrate, wherein the second sidewall surface extends from the first top surface to the second top surface;
a dielectric layer disposed over the substrate, wherein the dielectric layer directly contacts the first raised source/drain epitaxy features, the second raised source/drain epitaxy features, the first L-shaped spacer liners, the second L-shaped spacer liners, and the shallow trench isolation structure, wherein the first top surfaces of the first L-shaped spacer liners and the second L-shaped spacer liners are free of the dielectric layer and the dielectric layer covers an entirety of the second sidewall surfaces of the first L-shaped spacer liners and the second L-shaped spacer liners and an entirety of the second top surfaces of the first L-shaped spacer liners and the second L-shaped spacer liners;
wherein first portions of the dielectric layer fill first gaps between the first L-shaped spacer liners and the first raised source/drain epitaxy features;
wherein second portions of the dielectric layer fill second gaps between the second L-shaped spacer liners and the second raised source/drain epitaxy features;
wherein the first have a first depth and a first width, the first depth is between top surfaces of the first raised source/drain epitaxy features and the second top surfaces horizontal portions of the first L-shaped spacer liners, and the first width is between sidewall surfaces of the first raised source/drain epitaxy features and the second sidewall surfaces of the first L-shaped spacer liners;
wherein the second gaps have a second depth and a second width, the second depth is between top surfaces of the second raised source/drain epitaxy features and the second top surfaces of the second L-shaped spacer liners, and the second width is between sidewall surfaces of the second raised source/drain epitaxy features and the second sidewall surfaces of the second L-shaped spacer liners; and
wherein a first ratio of the first depth to the first width of the first gaps is different than a second ratio of the second depth to the second width of the second gaps.