Patent ID: 11966739
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus comprising:
a register file comprising a plurality of data registers; and
frontend circuitry responsive to an issued instruction, to control processing circuitry to perform a processing operation to process an input data item to generate an output data item,
wherein:
the processing circuitry is responsive to a first encoding of the issued instruction specifying a data register of the plurality of data registers, to at least one of:
read the input data item for the processing operation from the data register; and
write the output data item generated in the processing operation to the data register; and

the processing circuitry is responsive to a second encoding of the issued instruction specifying a buffer-region of the register file for storing a queue of data items, to perform the processing operation and at least one of:
perform a dequeue operation to dequeue the input data item for the processing operation from the queue; and
perform an enqueue operation to enqueue the output data item generated in the processing operation to the queue.