Patent ID: 11869825
Assignee: QORVO US, INC.
Field: nan (nan)
Classification: CPC nan | IPC H

Claim 12:
13. The method of claim 11 wherein forming the device wafer comprises:
providing a Si—SiGe—Si wafer that includes a common silicon epitaxial layer, a common interfacial layer over the common silicon epitaxial layer, and the silicon handle substrate over the common interfacial layer, wherein the common interfacial layer is formed of SiGe;
performing a complementary metal-oxide-semiconductor (CMOS) process to provide a precursor wafer that includes a plurality of device regions, wherein:
the isolation sections extend through the common silicon epitaxial layer and the common interfacial layer, and extend into the silicon handle substrate, such that the common interfacial layer separates into the plurality of interfacial layers individually, and the common silicon epitaxial layer separates into a plurality of individual silicon epitaxial layers, wherein:
each active layer of the plurality of device regions is formed from a corresponding individual silicon epitaxial layer; and
each of the plurality of interfacial layers directly resides over a top surface of a corresponding active layer, and the silicon handle substrate resides directly over the plurality of interfacial layers; and

forming the plurality of first bump structures at the bottom surface of each BEOL portion to complete the plurality of device dies from the plurality of device regions.