Patent ID: 11862234
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. The memory system of claim 7, wherein the input data received through the first data line is first input data and the input data received through the second data line is second input data, and the first sampler is further configured to:
when a first previous bit value of the first bit values is a first logical value, determine a first current bit value of the first bit values by comparing the first upper reference voltage with the first input data; and
when a previous bit value of the first input data is a second logical value different from the first logical value, compare the first lower reference voltage with the first input data to determine a current bit value of the first input data, and
the second sampler is further configured to:
when a previous bit value of the second input data is the first logical value, compare the second upper reference voltage with the second input data to determine a current bit value of the second input data; and
when a previous bit value of the second input data is the second logical value different from the first logical value, compare the second lower reference voltage with the second input data to determine a current bit value of the second input data.