Patent ID: 11971992
Assignee: LATTICE SEMICONDUCTOR CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 9:
10. The secure PLD failure characterization system of claim 1, further comprising:
an external system comprising a processor and a memory and configured to be coupled to the secure PLD through the configuration input/output (I/O) of the secure PLD, wherein the memory comprises machine-readable instructions which when executed by the processor of the external system are adapted to cause the external system to:
generate or receive a protected configuration for the secure PLD; and
program the secure PLD according to the protected configuration;
wherein the protected configuration comprises an application configuration and a feature configuration, each signed by an application private key associated with a secure PLD customer and encrypted by an application encryption key associated with the secure PLD customer, and a programming key digest comprising an encrypted and signed combination of an application public key, the application encryption key, and a programming secret associated with the secure PLD customer.