Patent ID: 11879939
Assignee: NXP B.V.
Field: Measurement (Instruments)
Classification: CPC G  H | IPC G  H

Claim 18:
19. A method for testing a clocking system in an integrated circuit (IC), the method comprising:
determining, by a testing system of the IC, at least one of a group consisting of (i) a first count of clock pulses of a first clock signal between an activation of a capture phase of an at-speed testing mode of the IC and a transition of a first clock enable signal, and (ii) a second count of clock pulses of the first clock signal between a first clock pulse of a second clock signal and a second clock pulse of the second clock signal,
wherein the first clock signal, the first clock enable signal, and the second clock signal are generated by the clocking system,
wherein the first clock enable signal enables division of the first clock signal,
wherein the first clock enable signal is de-asserted based on the activation of the capture phase, and during the capture phase, the first clock enable signal transitions to an asserted state based on a pipeline delay associated with the clocking system, and
wherein the second clock signal is generated based on the first clock signal and the first clock enable signal such that during the capture phase, the second clock signal is a gated version of the first clock signal and comprises the first clock pulse and the second clock pulse; and

detecting, by the testing system, a fault in the clocking system based on at least one of a group consisting of the first count and the second count.