Patent ID: 11923016
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. A computing system comprising:
a system on chip (SoC); and
a storage device coupled to the SoC, the storage device including control logic and a NAND memory coupled to the control logic, the control logic to:
resume a program operation with respect to the NAND memory during a first tier in response to a suspension counter reaching a first threshold,
resume the program operation with respect to the NAND memory during a second tier in response to the suspension counter reaching a second threshold,
resume the program operation with respect to the NAND memory during a third tier in response to the suspension counter reaching a third threshold, and
service one or more read operations with respect to the NAND memory until the suspension counter reaches the first threshold during the first tier, until the suspension counter reaches the second threshold during the second tier, and until the suspension counter reaches the third threshold during the third tier.