Patent ID: 11955978
Assignee: BLUE CHEETAH ANALOG DESIGN, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 2:
3. The circuit of claim 1, wherein the first transistor comprises a first PMOS transistor, the second transistor comprises a second PMOS transistor, the third transistor comprises a third PMOS transistor, the fourth transistor comprises a first NMOS transistor, and the fifth transistor comprises a second NMOS transistor, wherein the first PMOS transistor comprises a first PMOS transistor source terminal connected to a supply voltage, the first NMOS transistor comprises a first NMOS transistor drain terminal connected to ground, and the second NMOS transistor comprises a second NMOS transistor drain terminal connected to ground.