Patent ID: 11934271
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 40:
41. A method for memory controller controlling a memory device including a plurality of memory blocks including memory cells, respectively, the method comprising:
providing a user read command;
receiving first data and second data, which are acquired by read operations on a selected page among the plurality of memory blocks, using first read voltages and second read voltages, in response to the user read command;
counting numbers of memory cells of the selected page respectively included in a plurality of threshold voltage regions divided by the first read voltages and the second read voltages;
reordering a read retry set among a plurality of read retry sets based on the numbers of memory cells; and
controlling the memory device to perform a read retry operation selecting the read retry set having higher priority.