Patent ID: 11862271
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. A method, comprising:
identifying memory having an array of bitcells;
selecting a column in the array of bitcells for error correction;
writing a first column data sequence to the column;
reading a second column data sequence from the column after writing the first column data sequence to the column;
checking the second column data sequence for a number of errors by comparing the first column data sequence to the second column data sequence;
accumulating a column error count by increasing a column error counter by the number of errors;
writing a third column data sequence to the column;
reading a fourth column data sequence from the column after writing the third column data sequence to the column;
checking the fourth column data sequence for the number of errors by comparing the third column data sequence to the fourth column data sequence;
accumulating the column error count by increasing the column error counter by the number of errors; and
storing a column address associated with the column in a repair register for repair using column redundancy if the number of errors in the column error count is greater than or equal to a predetermined number of errors.