Patent ID: 11910733
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 10:
11. A method comprising:
forming a plurality of bottom electrodes in a first dielectric layer;
forming a second dielectric layer over and contacting the plurality of bottom electrodes and the first dielectric layer;
forming a Phase-Change Random Access Memory (PCRAM) layer over a top surface of the second dielectric layer;
patterning the PCRAM layer in an etching process to form a plurality of PCRAM elements, wherein the etching process is performed using the second dielectric layer as an etch stop layer; and
forming a plurality of filaments in the second dielectric layer, wherein the plurality of filaments are formed sequentially, and wherein the plurality of filaments belong to different Resistive Random-Access Memory (ReRAM) cells.