Patent ID: 11971821
Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 29:
30. The method as claimed in claim 23, wherein:
after providing the first last-level cache with the write-back and invalidation request, the first in-core cache module is switched to a waiting state for synchronization;
after all matched cache lines within the first last-level cache are invalidated, the first last-level cache returns a first synchronization signal to the first in-core cache module;
the first in-core cache module in the waiting state is awakened by the first synchronization signal returned from the first last-level cache, to search itself to determine which cache lines within the first in-core cache module match the designated key identification code, wherein: if a matched cache line has been modified, the first in-core cache module writes back the matched cache line to the system memory; and, whether modified or not, all matched cache lines within the first in-core cache module are invalidated.