Patent ID: 11963347
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A memory device comprising:
an anti-fuse element over a substrate and comprising:
a first fin structure over the substrate; and
a first gate structure across the first fin structure and extending in a first direction in a top view;

a transistor over the substrate and comprising:
the first fin structure;
a second gate structure across the first fin structure; and
a first source/drain region and a second source/drain region on the first fin structure and on opposite sides of the second gate structure, wherein the first source/drain region is between the first gate structure and the second gate structure;

a source/drain contact connected to the second source/drain region;
a first gate via connected to the first gate structure; and
a second gate via connected to the second gate structure, wherein a lateral distance between the first gate via and the source/drain contact along the first direction is less than a lateral distance between the second gate via and the source/drain contact along the first direction in the top view.