Patent ID: 11870441
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: nan (nan)
Classification: CPC nan | IPC G  H

Claim 14:
15. The clock gating circuit of claim 8, wherein the transmission gate comprises:
a first transistor of the first type, the first transistor including a second gate terminal, a second drain terminal and a second source terminal, the second gate terminal being coupled to at least the output node, and being configured to receive the clock output signal, the second source terminal being coupled to the first node and the NOR logic gate, and the second drain terminal being coupled to the second node; and
a second transistor of a second type different from the first type, the second transistor including a third gate terminal, a third drain terminal and a third source terminal, the third gate terminal being configured to receive the inverted clock input signal, the third source terminal being coupled to the second source terminal, the first node and the NOR logic gate, and the third drain terminal being coupled to the second node and the second drain terminal.