Patent ID: 11908795
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 4:
5. The structure of claim 1 further comprising:
a dielectric layer on the top surfaces of the first conductive via, the encapsulant, and the second integrated circuit die;
a first via in the dielectric layer and on the first conductive via;
a second conductive via over the first integrated circuit die and adjacent the first conductive via;
a second via in the dielectric layer and on the second conductive via;
a first metallization pattern on the first via and the dielectric layer;
a second metallization pattern on the second via and the dielectric layer; and
a third metallization pattern on the dielectric layer between the first metallization pattern and the second metallization pattern, the third metallization pattern being spaced apart from the first and second metallization patterns.