Patent ID: 11935616
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A comparison system comprising at least one comparison circuit, each of the at least one comparison circuit comprising:
a common module, connected to a power supply signal and a ground signal, and configured to control output of the power supply signal or the ground signal based on a first signal and a second signal which are inverted;
a first logical unit, connected to the common module, and configured to receive a third signal and a fourth signal which are inverted, and output a first operation signal which is an exclusive OR (XOR) of the first signal and the third signal; and
a second logical unit, connected to the common module, and configured to receive the third signal and the fourth signal, and output a second operation signal which is a not exclusive OR (XNOR) of the first signal and the third signal,
wherein the comparison system is applied to a memory system which is configured to write or read, during a read operation or a write operation, a plurality of data, and the plurality of data are divided into M bytes, each having N data,
wherein the comparison system is configured to receive the plurality of data, each used as the first signal or the third signal, and perform a first encoding operation based on a subset of the N data in each of the M bytes to generate X first check codes, each based on a subset of the N data at fixed bits among all the M bytes, and perform a second encoding operation based on all data in a subset of the M bytes to generate Y second check codes, wherein the X first check codes are configured for at least one of error detection or error correction on the N data in each of the M bytes, and the Y second check codes are configured for at least one of error detection or error correction on the M bytes; and each of M, N, X and Y is a positive natural number,
wherein the comparison system further comprises:
a second comparison module formed by a plurality of comparison circuits and configured to, during the read operation of the memory system, receive the plurality of data, the X first check codes and the Y second check codes, wherein one of the X first check codes, the Y second check codes or the plurality of data is used as the first signal or the third signal, and

wherein the second comparison module configured to perform a third encoding operation on a second subset of the N data in each of the M bytes and the X first check codes to generate X first operation codes, each corresponding to a respective one of the X first check codes, and perform a fourth encoding operation on all data in a second subset of the M bytes and the Y second check codes to generate Y second operation codes, each corresponding to a respective one of the Y second check codes, wherein the third encoding operation is an XNOR or XOR operation, and the fourth encoding operation is an XNOR or XOR operation.