Patent ID: 11900459
Assignee: CBOE EXCHANGE, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. An exchange computer system configured to minimize technological advantages possessed by some market participants over others by deemphasizing importance of order entry speed in trading, the exchange computer system comprising:
one or more processors; and
one or more memory elements including instructions that, when executed, cause the one or more processors to perform operations including:
receiving, from a user device, a security transaction order;
receiving a first matching order from a first device, wherein the first device is configured for high-speed algorithmic trading;
determining a first randomized period of time for a delay timer based on a signal obtained by the exchange computer system;
initiating the delay timer that runs for the first randomized period of time;
determining that the first randomized period of time has expired;
responsive to determining that the first randomized period of time has expired, initiating (i) an auction associated with the security transaction order and the first matching order and (ii) an auction timer that limits the auction to run for a second period of time;
notifying a plurality of market participants of the auction;
receiving, during the second period of time, one or more additional matching orders from one or more additional devices, wherein each of the one or more additional matching orders includes a request for participation in the auction, and wherein each of the one or more additional devices are not configured for high-speed algorithmic trading;
determining that the second period of time has expired;
determining a price of the first matching order;
determining a price of each of the one or more additional matching orders received during the second period of time;
determining a best-priced matching order based on the price of the first matching order and the price of each of the one or more additional matching orders; and
facilitating, by the one or more processors, a transaction based on the security transaction order and the best-priced matching order, thereby ensuring that the security transaction order trades with the best-priced matching order, and that the first device that is configured for high-speed algorithmic trading does not have, with respect to the transaction, a speed-based advantage over the one or more additional devices that are not configured for high-speed algorithmic trading.