Patent ID: 11935835
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of manufacturing a semiconductor device, the method comprising:
forming transistors on a substrate such that each of the transistors includes a gate structure and a source/drain layer adjacent thereto;
forming a first insulating interlayer on the substrate to cover the transistors;
forming first contact plugs and a second contact plug through the first insulating interlayer to contact the source/drain layers, respectively;
forming a second insulating interlayer on the first insulating interlayer, and the first and second contact plugs;
forming first and second openings through the first and second insulating interlayers such that the first opening exposes one of the gate structures and the second opening commonly exposes at least one of the gate structures and the second contact plug adjacent thereto;
forming a first insulating spacer on a sidewall of the first opening; and
forming third and fourth contact plugs in the first and second openings, respectively.