Patent ID: 11955157
Assignee: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 3:
4. The PUF apparatus according to claim 1,
wherein the PUF apparatus further includes:
a precharge block having a plurality of column precharge blocks which are connected in parallel to a corresponding first sense amplifier between a corresponding bit line pair among the plurality of bit line pairs and the voltage line, and which supply a voltage applied to the voltage line to a corresponding bit line pair according to an inactivated read enable signal; and
an initialization block having a plurality of column initialization blocks which are connected in parallel with a corresponding second sense amplifier between a corresponding source line pair among the plurality of source line pairs and the ground line, and which supply a voltage applied to the ground line to a corresponding source line pair according to an inactivated inverted initialization signal.