Patent ID: 11923426
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 14:
15. A semiconductor device comprising:
a gate structure on a substrate, the gate structure comprising a gate electrode and a gate capping pattern on the gate electrode;
a source/drain pattern;
a source/drain contact electrically connected to the source/drain pattern;
a gate contact electrically connected to the gate electrode; and
a wiring structure electrically connected to the source/drain contact and the gate contact,
wherein the wiring structure comprises a first via plug electrically connected to the source/drain contact, a second via plug, and a wiring line electrically connected to the first via plug and the second via plug,
wherein an upper face of the gate capping pattern is coplanar with an upper face of the gate contact,
wherein the first via plug comprises a single conductive film structure,
wherein an upper face of the first via plug has a convex curved face,
wherein the second via plug further comprises a via barrier film, a lower via filling film on the via barrier film, and an upper via filling film on the lower via filling film,
wherein the upper via filling film overlaps an upper face of the via barrier film in a direction perpendicular to the substrate, and
wherein an upper surface of the via barrier film is lower than an upper surface of the lower via filling film with respect to the substrate.