Patent ID: 11942326
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A process of forming an electronic device comprising:
forming a barrier layer;
forming a gate electrode layer over the barrier layer, wherein forming the gate electrode layer comprises:
forming a first film of the gate electrode layer, wherein the first film includes a first III-V material;
forming a first dopant region of the gate electrode layer, wherein the first dopant region has a first conductivity type;
forming a second film of the gate electrode layer overlying the first film of the gate electrode layer, wherein the second film includes a second III-V material and is formed after forming the first dopant region; and
forming a second dopant region of the gate electrode layer, wherein the second dopant region overlies the first dopant region and has the first conductivity type;

merging the first dopant region and the second dopant region together to form a diffused doped region by diffusing a dopant from each of the first dopant region and the second dopant region;
patterning the gate electrode layer to form a gate electrode; and
forming a gate interconnect over the gate electrode,
wherein after forming the gate interconnect, a first portion of the gate electrode contacts the barrier layer and is undoped or has an average dopant concentration of the first conductivity type that is at most 5×1016 atoms/cm3.