Patent ID: 11917814
Assignee: MICRON TECHNOLOGY, INC.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 12:
13. An apparatus, comprising:
a semiconductor substrate;
a memory mat arranged on the semiconductor substrate and having a rectangular shape,
a plurality of storage capacitors arranged in the memory mat;
a plurality of dummy capacitors arranged to surround the plurality of storage capacitors; and
a landing pad surrounding the plurality of storage capacitors;
wherein the plurality of dummy capacitors are located above the landing pad,
wherein the apparatus further comprises:
a plurality of channel pillars arranged in the memory mat, each of the plurality of channel pillars being electrically connected to a corresponding one of the plurality of storage capacitors;
a plurality of peripheral pillars surrounding the plurality of channel pillars; and
a shield structure surrounding each of the plurality of channel pillars and each of the plurality of peripheral pillars in a mesh pattern, the shield structure comprising a conductive material.