Patent ID: 11940915
Assignee: SANECHIPS TECHNOLOGY CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A cache allocation method, comprising:
accessing, by a core, a level 3 cache in response to detecting a miss response from each of a level 1 cache and a level 2 cache, wherein the level 1 cache and the level 2 cache are accessed by the core through sending instruction fetching instructions; wherein the instruction fetching instructions are configured to request the level 1 cache and the level 2 cache that are accessed to return an instruction and data, the level 1 cache is a private cache of the core, the level 2 cache is a common cache corresponding to a core set including the core, the level 3 cache is a common cache shared by a plurality of core sets, and the miss response from the level 2 cache carries network slice information;
allocating, by a planning unit disposed in the level 3 cache, the plurality of core sets to a plurality of network slices and configuring, by the planning unit, corresponding caches for the plurality of network slices according to the network slice information; and
sending, by the planning unit, a hit response to the core, wherein the hit response is configured to return data in a cache of a network slice corresponding to the core set including the core.