Patent ID: 11961824
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 18:
19. A semiconductor package comprising:
a package substrate including an upper surface including bonding pads;
a lower semiconductor chip disposed on the upper surface of the package substrate, wherein an upper surface of the lower semiconductor chip includes a connect edge region including connection pads and an open edge region including a dam structure;
a spacer chip disposed on the upper surface of the package substrate;
an upper semiconductor chip disposed on the upper surface of the lower semiconductor chip and an upper surface of the spacer chip;
an inter-chip bonding layer between the upper semiconductor chip and the lower semiconductor chip and the spacer chip;
bonding wires respectively connecting the bonding pads and the connection pads; and
a molding portion on the package substrate and substantially surrounding the lower semiconductor chip, the spacer chip and the upper semiconductor chip,
wherein the dam structure includes at least two dummy bumps and at least one dummy wire connecting the at least two dummy bumps.