Patent ID: 11915755
Assignee: WINBOND ELECTRONICS CORP.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 5:
6. The layout of the semiconductor memory device of claim 5, further comprising:
a plurality of first plugs, disposed on the source and drain regions and the gate of the first transistor, and disposed on the source and drain regions of the first reading transistors and the source and drain regions of the second reading transistors;
a first metal layer, disposed on the plurality of first plugs to be electrically connected to the first plugs, wherein a first portion of the first metal layer is disposed on the gate of the second transistor, and the first portion of the first metal layer extends from above the gate of the first transistor to above the gate of one of the second reading transistors, and a second portion of the first metal layer is disposed on the source and drain regions of the first reading transistors; and
a plurality of second plugs, disposed on the first metal layer to be electrically connected to the first metal layer.