Patent ID: 11901338
Assignee: XILINX, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC G  H

Claim 11:
12. An integrated circuit (IC) device comprising:
a first wafer having a plurality of IC dies formed thereon separated by scribe lanes, the first wafer having an active side having a first front side bond pad and a back side having a first back side bond pad, the plurality of IC dies formed on the first wafer including a first IC die;
a second wafer having a plurality of IC dies formed thereon separated by scribe lanes, the second wafer having an active side having a second front side bond pad, and a back side having a second back side bond pad, the plurality of IC dies formed on the second wafer including a second IC die;
a third wafer having a plurality of IC dies formed thereon separated by scribe lanes, the third wafer having an active side having a third front side bond pad, and a back side having a third back side bond pad, the plurality of IC dies formed on the third wafer including a third IC die that is stacked in alignment with the first and second IC dies;
a first test key, a second test key, and a third test key formed in one of the scribe lanes of the first wafer;
a first hybrid bond interface layer coupling the first wafer to the second wafer, the first hybrid bond interface layer having a first U-turn connection that couples the first back side bond pad of the first wafer to the first test key;
a first test key, a second test key, and a third test key formed in one of the scribe lanes of the second wafer, the test keys of the first wafer vertically aligned with the test keys of the second wafer;
a second hybrid bond interface layer coupling the second wafer to the third wafer, the second hybrid bond interface layer having a second U-turn connection that couples the second back side bond pad of the second wafer to the second test key of the second wafer, the second U-turn connection not aligned with the first U-turn connection disposed in the first hybrid bond interface layer; and
a first test key, a second test key, and a third test key formed in one of the scribe lanes of the third wafer, the test keys of the third wafer vertically aligned with the test keys of the second wafer; and
a third hybrid bond interface layer formed on the third wafer, the third hybrid bond interface layer having a third U-turn connection that couples the third back side bond pad of the third wafer to the third test key of the third wafer,
wherein a different one of the test keys of each wafer is coupled to a front side bond pad of the first wafer.