Patent ID: 11947462
Assignee: APPLE INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. An apparatus, comprising:
execution circuitry configured to perform operations for instructions from multiple threads in parallel;
scheduling circuitry configured to arbitrate among threads to schedule threads for execution by the execution circuitry and select threads based on thread priority;
cache circuitry configured to store information operated on by threads executed by the execution circuitry;
tracking circuitry configured to determine one or more performance metrics for the cache circuitry; and
control circuitry configured to:
based on the one or more performance metrics meeting a threshold, reduce a limit on a number of threads concurrently executed by the execution circuitry over one or more time windows, to control a footprint of information stored by the cache circuitry, wherein, to reduce the limit on the number of threads concurrently executed, the control circuitry is configured to limit the number of threads considered for arbitration by the scheduling circuitry; and
based on an indication that a set of threads should synchronize, consider a greater number of threads than indicated by the limit for arbitration, based on one or more threads in the set of threads having a thread priority that meets a priority threshold.