Patent ID: 11874792
Assignee: GOWIN SEMICONDUCTOR CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 17:
18. A method of providing a high-speed (“HS”) data communication between a host and field-programmable gate array (“FPGA”) comprising:
coupling an FPGA to a host via a bus capable of supporting HS network data transmission;
activating a drive block of FPGA to negotiate transmission speed between the host and FPGA regarding data rate of serial data transmission over the bus;
sampling, by a first input deserializer, first two samples of data signals carried by a P-channel in accordance with first clock cycles clocking twice as fast as the data rate at the P-channel; and
sampling, by a second input deserializer, second two samples of data signals transmitted by an N-channel in accordance with second clock cycles running twice as fast as the data rate at the N-channel with a ninety (90) degree phase shift.