Patent ID: 11941545
Assignee: THE MATHWORKS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 3:
4. The system of claim 1, wherein the processor, when performing the transformation, is further configured to perform one or more of the following:
delay the first type-1 MF by a first value between 0 and 1, inclusive;
multiply a membership value of the first type-1 MF by a second value that is less than or equal to 1 to scale down the first type-1 MF;
subtract a first offset value from a plurality of membership values of the first type-1 MF to vertically shift the first type-1 MF; or
horizontally shift the first type-1 MF with a second offset value to produce a shifted type-1 MF and selecting minimum values of the first type-1 MF and the shifted type-1 MF.