Patent ID: 11910601
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A method of forming a microelectronic device, the method comprising:
forming a lower stack structure comprising a vertically alternating sequence of insulative structures and sacrificial structures arranged in tiers;
forming a lower array of pillar openings extending through the lower stack structure;
forming, above the lower stack structure and in at least upper portions of the pillar openings of the lower array, at least one sacrificial material;
forming, above the at least one sacrificial material, an upper stack structure comprising an additional vertically alternating sequence of additional insulative structures and additional sacrificial structures arranged in additional tiers;
forming an upper array of pillar openings extending through the upper stack structure;
removing the at least one sacrificial material to form extended openings, the extended openings comprising:
the pillar openings of the upper array,
the pillar openings of the lower array, and
a cavity formed by removing the at least one sacrificial material;

conformally forming cell material in the extended openings;
removing the cell material from the cavity, leaving the cell material in the pillar openings of the upper array to form an upper array of pillars, and leaving the cell material in the pillar openings of the lower array to form a lower array of pillars; and
forming at least one conductive material in the cavity to form an interdeck source region vertically interposed between the upper array of pillars and the lower array of pillars; and
replacing the sacrificial structures of the lower stack structure and of the upper stack structure with conductive structures,, the method forming a microelectronic device comprising:
a pair of stack structures, the pair comprising:
the lower stack structure; and
the upper stack structure overlying the lower stack structure,
the lower stack structure and the upper stack structure each comprising a respective group of the vertically alternating sequence of the insulative structures and the conductive structures arranged in the tiers;

the interdeck source region vertically interposed between the lower stack structure and the upper stack structure, the interdeck source region comprising at least one conductive material comprising, along a lower surface thereof, an array of V-shaped extensions;
the upper array of pillars extending, through the upper stack structure, from proximate the interdeck source region toward a first drain region above the upper stack structure; and
the lower array of pillars extending, through the lower stack structure, from proximate the interdeck source region toward a second drain region below the lower stack structure.