Patent ID: 11863187
Assignee: SYNOPSYS, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A circuit, comprising:
a first master stage comprising a data input line;
a second master stage comprising an inverse data input line;
a first slave stage coupled to an output of the first master stage; and
a second slave stage coupled to an output of the second master stage, wherein the first slave stage is configured to generate an output signal during a rising edge of a clock cycle of a clock signal and the second slave stage is configured to generate an inverted output signal during the rising edge of the clock cycle and wherein the output signal and the inverted output signal are available concurrently; and
a cross-coupled circuit, wherein the cross-coupled circuit is coupled between an output of the first master stage and the output of the second master stage, wherein the cross-coupled circuit comprises a transistor gated by the clock signal.