Patent ID: 11972825
Assignee: SK HYNIX INC.
Field: nan (nan)
Classification: CPC nan | IPC G  H

Claim 16:
17. A method of performing a wafer level test on an integrated circuit chip having no cell array by utilizing a repair circuit configured to repair defective through electrodes to generate a test signal during the wafer level test, the method comprising:
generating a toggling signal based on a read data strobe signal;
providing two through electrodes coupled with two latch circuits configured to store test data from the coupled through electrodes;
providing the toggling signal to a through electrode repair circuit as a selection signal, wherein the repair circuit is configured to select one of the two through electrodes in response to the logic level of the toggling signal; and
during the wafer level test, generating the test signal by outputting the logic levels of the two latch circuits in response to the toggling signal.