Patent ID: 11899978
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. A system for aborting a command for a Peripheral Component Interconnect express (PCIe) based Non-Volatile Memory express (NVMe) Solid-State Drive (SSD), the system comprising:
a processor; and
a memory communicatively coupled to the processor,
wherein the memory stores processor-executable instructions, which on execution, cause the processor to:
receive an abort command in an Admin submission queue of a host to abort a target command in an Input/Output (I/O) submission queue of the host or in an I/O queue of the NVMe SSD, wherein the abort command comprises slot information of the target command to be aborted;
update a tail doorbell of NVMe doorbell registers of the NVMe SSD after receiving the abort command in the Admin submission queue;
place the abort command into an Admin queue of the NVMe SSD after updating the tail doorbell of the NVMe doorbell registers by the host;
execute the abort command, wherein the execute comprises:
determining whether the target command has been received in the NVMe SSD;
aborting the target command in response to determining that the target command has been received in the NVMe SSD;
using the slot information of the target command to be aborted for updating an I/O completion queue of the host with the target command to be aborted in response to determining that the target command has not been received;

update a head doorbell of the NVMe doorbell registers of the NVMe SSD after completing execution of the abort command; and
placing information in an Admin completion queue of the host after the update of the head doorbell that indicates the aborting of the target command has completed.