Patent ID: 11881830
Assignee: REALTEK SEMICONDUCTOR CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A filter circuit, comprising:
a plurality of registers, each being configured to store an input;
a switch circuit, coupled to the registers and configured to receive the inputs from the registers as a series of registered inputs and adjust arrangement of the inputs of the series of registered inputs to generate a series of rearranged inputs according to a count value, wherein the count value is accumulated in response to reception of a new input of the filter circuit;
a plurality of multipliers, coupled to the switch circuit, wherein the inputs of the series of rearranged inputs are sequentially provided to the multipliers and each multiplier is configured to generate a multiplication result according to received input and a coefficient; and
a summation circuit, coupled to the multipliers and configured to sum up the multiplication results to generate an output;
wherein when the filter circuit receives the new input, the new input is written in one of the registers to replace the oldest input among the inputs currently being stored in the registers.