Patent ID: 11963357
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A nonvolatile memory device comprising:
a mold structure including a first surface and a second surface opposite to each other, the mold structure including a plurality of gate electrodes stacked sequentially in a first direction from the first surface toward the second surface;
a source structure extending along the first surface of the mold structure, and formed on the first surface of the mold structure;
a channel hole extending from the second surface toward the first surface, and penetrating the mold structure;
an impurity pattern connected to the source structure, and formed in the channel hole;
a semiconductor pattern extending from the impurity pattern toward the second surface of the mold structure, and formed in the channel hole;
a bit line connected to the semiconductor pattern, and formed on the second surface of the mold structure;
a first inter-wiring insulation film which covers the bit line, and is formed on the second surface of the mold structure;
a substrate facing the second surface of the mold structure;
a peripheral circuit element formed on the substrate; and
a second inter-wiring insulation film which covers the peripheral circuit element, and is interposed between the substrate and the first inter-wiring insulation film,
wherein the impurity pattern includes a first region adjacent to the source structure and a second region adjacent to the semiconductor pattern, and
an impurity concentration of the impurity pattern increases as the impurity pattern goes away from the semiconductor pattern.