Patent ID: 11972142
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A data processing apparatus comprising:
first data processing circuitry;
second data processing circuitry;
interconnect circuitry to provide a data connection at least for the transmission of data communication packets between the first data processing circuitry and the second data processing circuitry; and
data storage circuitry comprising a set of two or more candidate storage devices associated with one or both of the first data processing circuitry and the second data processing circuitry, each of the set of two or more candidate storage devices being addressable by a target address belonging to a particular address space;
in which at least one of the first data processing circuitry and the second data processing circuitry is configured to operate as sending circuitry comprising configuration reception circuitry to receive configuration data from recipient circuitry, the configuration data identifying a set of two or more candidate storage devices and corresponding persistence characteristics of the two or more candidate storage devices; generator circuitry configured to generate a data communication packet comprising at least payload data and the target address for storage, by another of the first data processing circuitry and the second data processing circuitry acting as recipient circuitry, of the payload data; control circuitry configured to determine, based on an indication of a required storage classification at the recipient circuitry, a storage classification for the payload data of the data communication packet, the determined storage classification indicating a degree of persistence to be applied to that payload data by the recipient circuitry; and packet transmission circuitry configured to transmit the data communication packet with a predetermined data field specifying a data placement attribute corresponding to the determined storage classification to the recipient circuitry;
and in which at least one of the first data processing circuitry and the second data processing circuitry is configured to operate as recipient circuitry comprising configuration provision circuitry to provide the configuration data to another of the first data processing circuitry and the second data processing circuitry acting as sending circuitry; packet reception circuitry configured to receive the data communication packet with from the sending circuitry, the packet reception circuitry configured to detect the storage classification in the received data communication packet based on the predetermined data field specifying the data placement attribute; and storage control circuitry configured to control writing of the payload data of the data communication packet by one or more storage devices selected from the set of two or more candidate storage devices sharing the particular address space such that each of the two or more candidate storage devices are addressable by the target address, the storage control circuitry being responsive to the storage classification detected by the packet reception circuitry and to respective persistence properties associated with the set of two or more candidate storage devices.