Patent ID: 11908857
Assignee: GLOBALFOUNDRIES U.S. INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A method comprising:
forming a first cavity, a second cavity, and a third cavity in a semiconductor fin, wherein the third cavity is laterally positioned between the first cavity and the second cavity;
forming a first gate structure and a second gate structure extending over the semiconductor fin;
forming a first section of a semiconductor layer in the first cavity and a second section of the semiconductor layer in the second cavity;
forming a shallow trench isolation region positioned in the semiconductor fin adjacent to the second gate structure; and
forming an isolation structure laterally positioned between the first section and the second section of the semiconductor layer,
wherein the first gate structure is adjacent to the second gate structure, the first section of the semiconductor layer is laterally positioned between the third cavity and the first gate structure, the second section of the semiconductor layer is laterally positioned between the third cavity and the second gate structure, the isolation structure includes a dielectric layer and a sidewall spacer, the sidewall spacer has a first section and a second section, the dielectric layer includes a first portion in the third cavity and a second portion between the first section and the second section of the sidewall spacer, the semiconductor fin includes a first portion laterally between the first cavity and the first portion of the dielectric layer, the semiconductor fin includes a second portion laterally between the second cavity and the second portion of the dielectric layer, the second gate structure extends across a third portion of the semiconductor fin, the third cavity extends to a depth relative to a top surface of the semiconductor fin that is greater than the depth of the first cavity and the second cavity, and the second section of the semiconductor layer, the second portion of the semiconductor fin, and the third portion of the semiconductor fin are positioned between the isolation structure and the shallow trench isolation region.