Patent ID: 11948625
Assignee: WINBOND ELECTRONICS CORP.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. An integrated circuit, comprising:
a memory circuit comprising a memory cell array on a first die; and
a system-on-chip (SoC) circuit on a second die, coupled to the memory circuit through interconnectors, and configured to:
transmit a transistor-level operation signal and a transistor-level address signal through a first plurality of the interconnectors to the memory circuit on the first die, the transistor-level operation signal corresponding to a read or write operation and being transmitted for communication from a transistor of the SoC circuit on the second die to a transistor of the memory circuit on the first die; and
transmit to or receive from the memory circuit on the first die a transistor-level data signal through a second plurality of the interconnectors.