Patent ID: 11894087
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. The test circuit according to claim 10,
wherein the first logic control sub-circuit includes a first P-type transistor, a first N-type transistor, a second N-type transistor, a third N-type transistor, and a fourth N-type transistor;
wherein a control terminal of the first P-type transistor is connected to an output terminal of the control logic circuit, wherein a first terminal of the first P-type transistor is connected to a power terminal, and wherein a second terminal of the first P-type transistor is connected to an input terminal of the first latch group and a first terminal of the first N-type transistor;
wherein a control terminal of the first N-type transistor, a control terminal of the second N-type transistor, and a control terminal of the third N-type transistor are all connected to an output terminal of the test decoding circuit;
wherein a second terminal of the first N-type transistor is connected to a first terminal of the second N-type transistor, wherein a second terminal of the second N-type transistor is connected to a first terminal of the third N-type transistor, wherein a second terminal of the third N-type transistor is connected to a first terminal of the fourth N-type transistor;
wherein a control terminal of the fourth N-type transistor is connected to an output terminal of the control logic circuit, therein a first terminal of the fourth N-type transistor is connected to a second terminal of the third N-type transistor, and
wherein a second terminal of the fourth N-type transistor is connected to the ground terminal.