Patent ID: 11960392
Assignee: AMAZON TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. The integrated circuit of claim 6, wherein the integrated circuit further comprises a third address decoder communicatively coupled between the first interconnect fabric and the second interconnect fabric, the third address decoder configured with a third address mapping table that maps a third set of address ranges to the second set of target nodes coupled to the second interconnect fabric, wherein the third address decoder corresponds to a third target node in the first set of target nodes, and wherein the first address decoder is further configured to:
receive another transaction from the source node that includes a destination address targeted to a fourth target node in the second set of target nodes;
determine that the destination address maps to the third target node; and
provide a third target node ID identifying the third target node to the first interconnect fabric to route the transaction to the third address decoder.