Patent ID: 11971847
Assignee: XDL TECHNOLOGIES INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. A processor, comprising:
a plurality of processing elements (PEs) arranged in a plurality of columns with each column including at least one PE, each of the plurality of PEs including a plurality of arithmetic logic units (ALUs) configured to execute a same instruction in parallel threads, wherein the plurality of columns are coupled for data to flow from a preceding column to a succeeding column in a direction from a first column to a last column of the plurality of columns;
a sequencer coupled to the plurality of PEs and configured to distribute decoded instructions packaged as configurations to the plurality of PEs;
a temporary data storage configured to store data received from the last column and to provide the data stored to the first column;
a plurality of switch boxes (SBs) arranged in the plurality of columns with each SB associated with one of the plurality of PEs for the plurality of switch boxes to collectively provide data switching for the plurality of PEs; and
a memory unit and a plurality of memory ports (MPs), wherein each MP is arranged in a respective column of the plurality of columns, and coupled between the memory unit and a SB of the respective column for the plurality of PEs to access the memory unit.