Patent ID: 11922108
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 5:
6. The method of claim 5, wherein the generating the set of resistive switching element layout patterns comprises:
generating a bottom electrode element layout pattern corresponding to fabricating a bottom electrode element, the bottom electrode element layout pattern being located on a third layout level;
generating a resistive switching material layout pattern corresponding to fabricating a resistive switching material, the resistive switching material layout pattern being located on a fourth layout level different from the first layout level, the second layout level and the third layout level; and
generating a top electrode element layout pattern corresponding to fabricating a top electrode element, the top electrode element layout pattern being located on a fifth layout level different from the first layout level the second layout level, the third layout level and the fourth layout level.