Patent ID: 11908739
Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. An apparatus comprising:
a first substrate comprising a first bonding surface that comprises a first conductive layer-filled cavity, wherein a conductive layer of the first conductive layer-filled cavity has a width of at least 10 microns, wherein a grain size of a conductor within the first conductive layer-filled cavity is more than 5% of the width of the first conductive layer-filled cavity; and
a second substrate comprising a second bonding surface that comprises a second conductive layer-filled cavity, wherein a width of a conductive layer of the second conductive layer-filled cavity is 2-10 times the width of the conductive layer of the first conductive layer filled cavity,
wherein the first bonding surface is bonded to the second bonding surface.