Patent ID: 11888486
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 2:
3. The phase correcting circuit of claim 1,
wherein the first fine tuning circuit includes a first NAND gate, and the second fine tuning circuit includes a second NAND gate;
wherein the first terminal corresponds to a first input terminal of the first NAND gate, the second terminal corresponds to a second input terminal of the first NAND gate, and the third terminal corresponds to a first output terminal of the first NAND gate; and
wherein the fourth terminal corresponds to a third input terminal of the second NAND gate, the fifth terminal corresponds to a fourth input terminal of the second NAND gate, and the sixth terminal corresponds to a second output terminal of the second NAND gate.