Patent ID: 11972340
Assignee: KWANGWOON UNIV INDUSTRY-ACADEMIC COLLABORATION FDN
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 6:
7. The weight memory device of claim 1, wherein:
the capacitance between the input terminal and the common output terminal is quantified based on capacitance-voltage characteristics between the common output terminal and the input terminal and based on a second bias voltage in a state in which the second bias voltage has been applied between the input terminal and the common output terminal; and
when an input signal is applied to the input terminal in the state in which the second bias voltage has been applied, a change in a voltage or amount of charge of the common output terminal is generated as an output signal of the common output terminal based on the capacitance between the input terminal and the common output terminal and the input signal.