Patent ID: 11929418
Assignee: WINBOND ELECTRONICS CORP.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 1:
2. The gate structure of claim 1, further comprising:
a second N-type gate structure disposed within the N-type transistor region, wherein the second N-type gate structure comprises:
a third trench embedded in the interlayer dielectric;
a third gate electrode disposed in the third trench, wherein the third gate electrode has a second mushroom-shaped profile under a cross-sectional view;
the gate dielectric layer contacting the third trench;
the N-type work function layer disposed between the gate dielectric layer and the third gate electrode;
a second P-type work function layer disposed between the gate dielectric layer and the N-type work function layer;

a second P-type gate structure disposed within the P-type transistor region, wherein the second P-type gate structure comprises:
a fourth trench embedded in the interlayer dielectric;
a fourth gate electrode disposed in the fourth trench, wherein the fourth gate electrode has a third mushroom-shaped profile under a cross-sectional view;
the gate dielectric layer contacting the fourth trench;
the N-type work function layer disposed between the gate dielectric layer and the fourth gate electrode; and
a third P-type work function layer disposed between the gate dielectric layer and the N-type work function layer, wherein a thickness of the third P-type work function layer is greater than a thickness of the first P-type work function layer, and the thickness of the first P-type work function layer is greater than a thickness of the second P-type work function layer.