Patent ID: 11893476
Assignee: KABUSHIKI KAISHA TOSHIBA
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. The inference system according to claim 8, wherein,
if the ith input signal is applied to the recurrent neural network circuit and the recurrent neural network circuit causes a jth intermediate signal, for which j is an integer of 1 or more and N or less, among the N intermediate signals to be fired, the control circuit adjusts, according to a first delay time period from timing for applying the M input signals until timing for firing the N intermediate signals, a relative relationship between a target coefficient among a plurality of coefficients set to the recurrent neural network circuit and a coefficient group other than the target coefficient, and
the target coefficient is a coefficient that is multiplied by the ith input signal among the M coefficients set to a product-sum operation circuit that outputs the jth output signal among the N product-sum operation circuits included in the recurrent neural network circuit.