Patent ID: 11915009
Assignee: ZTE CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 2:
3. The method of claim 1, wherein identifying an external device connected to an interface according to states of pins of the interface comprises at least one of following steps:
determining that the external device is an external storage device, in response to identifying that a CC1 signal on a pin A5 or a CC2 signal on a pin B5 of the interface is pulled down to ground;
determining that the external device is an earphone, in response to identifying that a CC1 signal on a pin A5 or a CC2 signal on a pin B5 of the interface is an earphone detection (DET) signal;
determining that the external device is a device supporting High-Definition Multimedia Interface (HDMI) input, in response to identifying a CC2 signal on a pin B5, a RX1+ signal on a pin B11, a RX1−signal on a pin B10, a TX2+ signal on a pin B32, a TX2-signal on a pin B3, a Vbus3 signal on a pin B4 and a Vbus4 signal on a pin B9, of the interface, or in response to identifying a CC1 signal on a pin A5, a RX2+ signal on a pin A11, a RX2−signal on a pin A10, a TX1+ signal on a pin A2, a TX1− signal on a pin A3, a Vbus1 signal on a pin A4 and a Vbus2 signal on a pin A9, of the interface;
determining that the external device is a charging device, in response to identifying that a CC1 signal on a pin A5, a Vbus1 signal on a pin A4, a Vbus2 signal on a pin A9, a GND1 signal on a pin A1 and a GND2 signal on a pin A12, of the interface, are charging signals, or in response to identifying that a CC2 signal on a pin B5, a Vbus3 signal on a pin B4, a Vbus4 signal on a pin B9, a GND3 signal on a pin B1 and a GND4 signal on a pin B12, of the interface, are charging signals; and
determining that the external device is a data transmission device, in response to identifying a CC1 signal on a pin A5, a D1+ signal on a pin A6, a D1− signal on a pin A7, a SBU1 signal on a pin A8, a Vbus1 signal on a pin A4 and a Vbus2 signal on a pin A9, of the interface, or in response to identifying a CC2 signal on a pin B5, a D2+ signal on a pin B6, a D2− signal on a pin B7, a SBU2 signal on a pin B8, a Vbus3 signal on a pin B4 and a Vbus4 signal on a pin B9, of the interface.