Patent ID: 11881771
Assignee: NXP USA, INC.
Field: Electrical machinery, apparatus, energy (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 14:
15. The method of claim 14, further comprising:
during the rising phase of the half-bridge voltage, the controller circuit comparing a value of the multi-bit status signal with a first upper limit value corresponding to a first upper limit voltage, to determine whether the half-bridge voltage is higher than the first upper limit voltage; and
the high-side delay circuit generating the high-side control signal using the delay control signal to add a predetermined delay time into the current first delay time in response to the half-bridge voltage being higher than the first upper limit voltage;
and wherein the method further comprises:
during the rising phase of the half-bridge voltage, the low-side delay circuit generating the low-side control signal using the delay control signal to reduce a predetermined delay time from a current second delay time in response to the half-bridge voltage being higher than the first upper limit voltage.