Patent ID: 11860229
Assignee: ADVANTEST CORPORATION
Field: Measurement (Instruments)
Classification: CPC G | IPC G

Claim 12:
13. A method for testing devices under test (DUTs), the method comprising:
receiving instructions from a system controller at a tester processor, wherein a tester board comprising a field programmable gate array (FPGA) and the tester processor are coupled to the system controller, and wherein the tester processor is operable to coordinate testing of a device under test (DUT);
generating commands and data for testing the DUT;
routing signals associated with the commands and the data in the FPGA based on a physical communication interface type of the DUT;
transmitting, to connection hardware operable to physically connect to different physical communication interface types implemented for the DUTs, the signals via a socket over lanes corresponding to a set of pins on the DUT, wherein the set of pins is associated with a first physical communication interface type of DUT, wherein the connection hardware comprises a connector module communicatively coupled to the FPGA, and wherein the connector module comprises the socket operable to receive and to connect to the DUT; and
for a second physical communication interface type of DUT, re-routing the signals via the socket to a different set of pins on the DUT, wherein the different set of pins is associated with the second physical communication interface type of DUT which is different from the first physical communication interface type of DUT.