Patent ID: 11864367
Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A method for forming a semiconductor device, comprising:
forming a plurality of first semiconductor structures on a first wafer, wherein at least one of the first semiconductor structures comprises a processor, an array of static random-access memory (SRAM) cells, a first bonding layer comprising a plurality of first bonding contacts, and a first interconnect layer vertically between the first bonding layer and the processor, a word line driver of an array of NAND memory cells, and a page buffer of the array of NAND memory cells, wherein the first interconnect layer is configured to transfer electrical signals between the processor and one or more of the array of SRAM cells, the word line driver of the array of NAND memory cells, or the page buffer of the array of NAND memory cells;
forming a plurality of second semiconductor structures on a second wafer, wherein at least one of the second semiconductor structures comprises the array of NAND memory cells and a second bonding layer comprising a plurality of second bonding contacts;
bonding the first wafer and the second wafer in a face-to-face manner, such that the at least one of the first semiconductor structures is bonded to the at least one of the second semiconductor structures, wherein the first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure at a bonding interface, and wherein the first bonding layer and the second bonding layer are configured to transfer electrical signals between the array of NAND memory cells and one or more of the processor, the array of SRAM cells, the word line driver of the array of NAND memory cells, or the page buffer of the array of NAND memory cells; and
dicing the bonded first and second wafers into a plurality of dies, wherein at least one of the dies comprises the bonded first and second semiconductor structures.