Patent ID: 11956944
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor structure formation method, comprising:
providing a substrate, the substrate comprising a contact region and a dummy region arranged adjacent to each other, a first bitline structure and a first dielectric layer arranged discretely and being formed on the substrate, an extension direction of the first dielectric layer intersecting with that of the first bitline structure, and the first bitline structure and the first dielectric layer defining discrete capacitor contact openings;
forming a first sacrificial layer filling the capacitor contact openings;
removing, in the dummy region, part of height of the first bitline structure, part of height of the first dielectric layer and part of height of the first sacrificial layer to form a first opening located at top of a second bitline structure, a second dielectric layer and a second sacrificial layer, wherein a remaining portion of the first bitline structure forms the second bitline structure, a remaining portion of the first dielectric layer forms the second dielectric layer, and a remaining portion of the first sacrificial layer forms the second sacrificial layer;
forming an insulation layer filling the first opening;
removing, in the contact region, the first sacrificial layer to form a second opening; and
forming a capacitor contact structure located in the second opening.