Patent ID: 11956162
Assignee: BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC.
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An asynchronous medium access control (AMAC) scheduler comprising:
at least one time slot including a first time slot;
at least two sub-slots within each at least one time slot;
a transmit packet block occupying at least one sub-slot within the first time slot; and
a receiver packet block including at least one sub-slot independent from the transmit packet block of at least one sub-slot, both the transmit packet block and the receiver packet block occupying at least one sub-slot and the receiver packet block being offset by a non-negative integer value of sub-slots from the transmit packet block from the first time slot and at least one sub-slot from a second time slot that is adapted to free a transceiver during the other sub-slot in the first time slot to perform a different operation;
wherein a ratio of sub-slots to slots is in a range from 2:1 to 20:1.