Patent ID: 11861782
Assignee: IMAGINATION TECHNOLOGIES LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A control stream decoder for decoding a control stream for a tile group comprising at least two tiles of a rendering space, the control stream decoder comprising:
a fetch module configured to fetch the control stream for the tile group from memory, the control stream comprising one or more fixed length primitive block entries, each primitive block entry identifying a location in memory of a control data block for a corresponding primitive block; and
a primitive block entry analyser configured to receive at least one of the one or more primitive block entries, and for each received primitive block entry:
(a) determine whether a current tile of the tile group is a valid tile for the corresponding primitive block, a tile being a valid tile for a primitive block if at least one primitive in the primitive block intersects that tile,
(b) in response to determining that the current tile is a valid tile for the corresponding primitive block, retrieve the control data block for the corresponding primitive block from the identified location in memory,
(c) identify, from the retrieved control data block, an address of the corresponding primitive block in memory and primitives of that primitive block relevant for rendering the current tile, and
(d) output information identifying the address of the corresponding primitive block in memory and the primitives of that primitive block relevant for rendering the current tile.