Patent ID: 11908820
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A method, comprising:
providing, between a first bond pad of a die and a second bond pad of an integrated circuit (IC) package, a first structure comprising a first solder metallurgy and, between the first structure and one of the first bond pad or the second bond pad, a second structure comprising a second solder metallurgy;
reflowing, prior to underfill, the first structure at a first temperature below a liquidus temperature of the second structure to form a first solder joint between the first bond pad and the second bond pad;
forming an underfill material between the die and the IC package and adjacent the first solder joint; and
reflowing, after said forming the underfill material, the first and second structures at a second temperature above the liquidus temperature of the second structure to form a second solder joint between the first bond pad and the second bond pad.