Patent ID: 11871589
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. An apparatus comprising:
a first pillar extending in a direction perpendicular to a substrate;
a second pillar extending in the direction perpendicular to the substrate;
a first memory cell including a first material located in a first level of the apparatus, the first material coupled to the first pillar;
a second memory cell including a first additional material located in the first level, the first additional material coupled to the second pillar;
a first conductive region located in the first level of the apparatus, the conductive region coupled to the first material and the first additional material; and
a second conductive region located in a second level of the apparatus, the second conductive region being separated from the first pillar by a first dielectric located in the second level and separated from the second pillar by a second dielectric located in the second level.