Patent ID: 11948851
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor package comprising:
a wiring structure;
a first semiconductor chip on the wiring structure;
a plurality of internal terminals between the wiring structure and the first semiconductor chip;
a high thermal conductivity layer between the wiring structure and the first semiconductor chip; and
an encapsulator on the high thermal conductivity layer and contacting the first semiconductor chip,
wherein sidewalls of at least the wiring structure and the encapsulator are substantially coplanar,
at least one sidewall of the high thermal conductivity layer is coplanar to at least one of the coplanar sidewalls of the wiring structure and the encapsulator,
the high thermal conductivity layer contacts a side surface of the first semiconductor chip,
a maximum contact height between the high thermal conductivity layer and the first semiconductor chip is a first length,
a height of the first semiconductor chip is a second length,
the first length is greater than half of the second length, and
an upper surface of the encapsulator includes a flat portion substantially parallel to an upper surface of the wiring structure and an inclined portion between the flat portion and the first semiconductor chip.