Patent ID: 11922997
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 14:
15. A non-volatile memory device comprising:
a memory cell region including first channel structures, second channel structures, first bit lines connected to the first channel structures, the first bit lines extending in a first direction, and the first bit lines being adjacent to each other in a second direction, second bit lines connected to the second channel structures, the second bit lines extending in the first direction, and the second bit lines being adjacent to each other in the second direction, a metal pattern extending in the first direction between the first bit lines and the second bit lines, and a first metal pad; and
a peripheral circuit region including a second metal pad, and connected to the memory cell region in a vertical direction by the first metal pad and the second metal pad,
wherein the peripheral circuit region includes a page buffer circuit region,
wherein the page buffer circuit region includes a page buffer circuit including;
first transistors arranged below the first bit lines in the vertical direction and electrically connected to the first bit lines;
second transistors arranged below the second bit lines in the vertical direction and electrically connected to the second bit lines; and
a first guard ring arranged below and overlapped the metal pattern in the vertical direction and extending in the first direction, and
wherein the first guard ring is arranged in the page buffer circuit region and applied with a bias voltage.