Patent ID: 11868870
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A neuromorphic apparatus configured to process a multi-bit neuromorphic operation, the neuromorphic apparatus comprising:
a single axon circuit configured to receive, as a first input, an i-th bit of an n-bit axon;
a single synaptic circuit configured to store, as a second input, a j-th bit of an m-bit synaptic weight and output a synaptic operation value between the first input and the second input;
a single neuron circuit configured to obtain each bit value of a multi-bit neuromorphic operation result between the n-bit axon and the m-bit synaptic weight, based on the output synaptic operation value; and
a controller configured to respectively determine the i-th bit and the j-th bit to be sequentially assigned for each time period of different time periods to the single axon circuit and the single synaptic circuit, to obtain the multi-bit neuromorphic operation result from a lower bit value to an upper bit value,
wherein n and m are each a natural number, i is a natural number between 1 and n, and j is a natural number between 1 and m, and
wherein the controller is further configured to determine the first input and the second input that are to be assigned at each time period such that bits indicating the multi-bit neuromorphic operation result are sequentially obtained by the single neuron circuit from a value of a least significant bit (LSB) to a value of a most significant bit (MSB).