Patent ID: 11935922
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 0:
1. A semiconductor device comprising:
a substrate;
a 1st transistor formed above the substrate, the 1st transistor comprising a 1st channel set of a plurality of 1st nanosheet layers, a 1st gate structure surrounding the 1st nanosheet layers, and 1st and 2nd source/drain regions at both ends of the 1st channel set; and
a 2nd transistor formed above the 1st transistor in a vertical direction, the 2nd transistor comprising a 2nd channel set of a plurality of 2nd nanosheet layers, a 2nd gate structure surrounding the 2nd nanosheet layers, and 3rd and 4th source/drain regions at both ends of the 2nd channel set;
wherein the 2nd source/drain region has a greater width than the 4th source/drain region in a channel width direction so that the 4th source/drain region vertically overlaps only a part of the 2nd source/drain region, the channel width direction being perpendicular to a channel length direction in which the 1st and 2nd source/drain regions are connected though the 1st channel set and the 3rd and 4th source/drain regions are connected though the 2nd channel set, and
wherein a sum of effective channel widths of the 1st nanosheet layers is substantially equal to a sum of effective channel width of the 2nd nanosheet layers.