Patent ID: 11923201
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of manufacturing a semiconductor device, the method comprising:
removing a first dummy gate and a second dummy gate from an interlayer dielectric layer;
depositing a gate dielectric layer over the interlayer dielectric layer;
depositing a work function tuning layer over the gate dielectric layer;
protecting a first portion of the work function tuning layer;
removing a second portion of the work function tuning layer with an etchant, wherein the etchant additionally forms a protective layer by reacting with an exposed surface of the gate dielectric layer;
blanket depositing a second work function tuning layer over the first portion of the work function tuning layer;
removing a first portion of the second work function tuning layer; and
depositing a fill material.