Patent ID: 11941402
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. A system, comprising:
a processor;
an arithmetic logic unit;
an operand vector register configured to store a list of elements; and
a vector index register configured to store a plurality of indices identifying respectively a plurality of elements from the list of elements stored in the operand vector register;
wherein during a first vector operation, the processor is configured to generate an output vector using an input vector and the arithmetic logic unit, the input vector having the plurality of elements identified by the vector index register;
wherein the processor is configured to perform, as part of the first vector operation, a compress or expand operation, wherein for each respective index stored in the vector index register, the compress operation or expand operation adds the respective index to an effective address for accessing a corresponding position in the operand vector register.