Patent ID: 11961577
Assignee: NXP USA, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 17:
18. The integrated circuit of claim 13, further comprising control circuitry configured to:
direct the memory engine and calibration circuitry to generate and store the pairs of calibration codes for each possible N-bit DAC input code for the N-bit differential DAC,
subsequently direct testing of the first set of ADCs using the pairs of calibration codes stored in the on-chip memory and a full N-bit resolution of the DAC, and
subsequently to the testing of the first set of ADCs, direct testing of the second set of ADCs using pairs of calibration codes corresponding to a reduced M-bit resolution of the DAC, wherein M and N are positive integers and M is less than N, wherein during the testing of the second set of ADCs, memory engine is configured to overwrite a portion of the calibration codes stored in the on-chip memory.