Patent ID: 11925011
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. A memory structure comprising:
a p-well and an n-well disposed in a semiconductor substrate;
first p-type fin channels extending from the p-well, wherein the first p-type fin channels extend lengthwise along a first direction and widthwise along a second direction, wherein the first p-type fin channels have a first width along the second direction;
second p-type fin channels extending from the p-well, wherein the second p-type fin channels extend lengthwise along the first direction and widthwise along the second direction, wherein the second p-type fin channels have a second width along the second direction;
first n-type fin channels extending from the n-well, wherein the first n-type fin channels extend lengthwise along the first direction and widthwise along the second direction, wherein the first n-type fin channels have a third width along the second direction;
second n-type fin channels extending from the n-well, wherein the second n-type fin channels extend lengthwise along the first direction and widthwise along the second direction, wherein the second n-type fin channels have a fourth width along the second direction;
wherein a memory area of the memory structure includes at least one n-type FinFET formed from the first p-type fin channels extending from the p-well and first n-type source/drains disposed on the first p-type fin channels;
wherein the memory area of the memory structure includes at least one p-type FinFET formed from the first n-type fin channels extending from the n-well and first p-type source/drains disposed on the first n-type fin channels;
wherein a first well strap area of the memory structure includes at least one dummy n-type FinFET formed from the second p-type fin channels extending from the p-well and second p-type source/drains disposed on the second p-type fin channels;
wherein a second well strap area of the memory structure includes at least one dummy p-type FinFET formed from the second n-type fin channels extending from the n-well and second n-type source/drains disposed on the second n-type fin channels; and
wherein the second width is greater than the first width and the fourth width is greater than the third width.