Patent ID: 11960769
Assignee: MACRONIX INTERNATIONAL CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. A method for performing a high performance secure read of information from a memory array of a memory chip, including:
detecting by the memory chip that a first command received from a host includes a secure memory read request command; and in response triggering performing of operations including:
inputting a specific context to be used to encrypt information to be read out from the memory array; and

detecting by the memory chip that a second command received from a host includes a command code field and a payload, wherein the command code field includes an op code indicating a continuous secure memory read response command, in which information read from the memory array is encrypted by a security engine prior to output, and wherein the payload includes: an address pointing to at least one address of a plurality of addresses indicating a security region within the memory array from which information is to be read; and a configurable dummy cycle in which the specific context is to be output; and in response triggering performing of operations to output encrypted data continuously, including substantially contemporaneously:
(i) outputting a first set of information read from the memory array and encrypted by an on-chip security engine, using the specific context;
(ii) using the on-chip security engine to perform encryption upon a second set of information read from the memory array; and
(iii) reading a third set of information from the memory array into a buffer to be encrypted by the on-chip security engine.