Patent ID: 11860716
Assignee: KABUSHIKI KAISHA TOSHIBA
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. A non-transitory computer-readable storage medium including computer executable instructions, wherein the instructions, when executed by a processor, cause the processor to perform a method comprising:
calculating a first input/output error related to normal data and a second input/output error related to pseudo abnormal data different from the normal data, for each autoencoder of a plurality of autoencoders, each autoencoder having a different network structure, wherein the normal data is data output by a factory machine or an inspection device of the factory machine when the factory device normally operates, and the pseudo abnormal data is data output by the factory machine or the inspection device when the factory device abnormally operates; and
for each autoencoder, outputting a relation between the network structure of the autoencoder and the first input/output error and the second input/output error,
wherein the method further comprises
calculating first output data by applying the normal data to each of the plurality of autoencoders, and calculating the first input/output error based on the first output data and the normal data; and
calculating second output data by applying the pseudo abnormal data to each of the plurality of autoencoders, and calculating the second input/output error based on the second output data and the normal data.