Patent ID: 11869597
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. A semiconductor storage device comprising:
a plurality of planes each including a memory cell array configured by a plurality of memory cells, word lines connected to gates of the plurality of memory cells, and bit lines electrically connected to one ends of the plurality of memory cells via selection gate transistors respectively connected to the one ends of the plurality of memory cells;
a voltage generation circuit capable of generating a voltage supplied to one or more of the memory cell arrays respectively included in the plurality of planes, the voltage generation circuit supplying a program voltage to a writing target selected word line in a program period and applying a first intermediate voltage to an adjacent word line adjacent to the selected word line in a former half of the program period and applying a second intermediate voltage higher than the first intermediate voltage to the adjacent word line in a latter half of the program period; and
a control circuit configured to set a level of the second intermediate voltage according to a number of the planes to which the program voltage is simultaneously supplied from the voltage generation circuit.