Patent ID: 11955159
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 10:
11. The semiconductor memory device of claim 9, wherein:
the normal cell array includes a plurality of sub array blocks arranged in a first direction and a second direction crossing the first direction,
each of the plurality of sub array blocks includes a first region and a second region,
the first region of each of the plurality of sub array blocks is configured to store the user data,
the second region of each of the plurality of sub array blocks is configured to store the count data and meta data,
the redundancy cell array includes a first region and a second region,
the first region of the redundancy cell array is configured to store the parity data, and
the second region of the redundancy cell array is configured to store the count parity data.