Patent ID: 11928176
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. The computer-based method of claim 11, where each PE includes a data selection circuit, a data selector, a multiplier circuit coupled to the data selector, and an accumulator circuit, and the computer-based method further comprises:
at the data selection circuit:
receiving the bitmap, and
generating a data selection signal based on the bitmap;

at the data selector:
receiving a row of the second matrix, the row having a plurality of elements, and
selectively outputting one row element of the plurality of elements of the row based on the data selection signal;

at the single multiplier circuit:
receiving a column element of a column of the compressed first matrix,
receiving the row element selectively output by the data selector,
multiplying the column element and the row element to generate an intermediate product, and
outputting the intermediate product; and

at the accumulator circuit:
receiving the intermediate product from the single multiplier circuit,
accumulating the intermediate product into an element of the output matrix, and
outputting the element of the output matrix after a last column element has been received by the single multiplier circuit.