Patent ID: 11901185
Assignee: KABUSHIKI KAISHA TOSHIBA
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. An etching method comprising:
forming a mask layer on a substrate, the substrate containing a semiconductor material and having a main surface, the main surface including a first region and a second region adjacent to each other, the mask layer including a first portion and a second portion, the first portion covering the first region and being provided with a plurality of openings or one or more openings defining a plurality of island-shaped portions, the second portion being a continuous layer covering the second region, and a height of the second portion at a position adjacent to a boundary between the first region and the second region with reference to the main surface being higher than a height of the first portion with reference to the main surface;
forming a catalyst layer containing a noble metal on a portion(s) of the main surface exposed in the plurality of openings or the one or more openings by a plating method; and
etching the substrate with an etching agent containing an oxidizer and hydrogen fluoride in a presence of the catalyst layer and the mask layer.