Patent ID: 11868280
Assignee: MICRON TECHNOLOGY, INC.
Field: nan (nan)
Classification: CPC nan | IPC G

Claim 0:
1. A system, comprising:
a plurality of sequencers each configured to provide a number of sequenced output signals responsive to assertion of a respective sequencer enable signal provided thereto; and
chaining circuitry coupled to the plurality of sequencers and comprising logic to:
responsive to assertion of a primary enable signal received thereby, assert respective sequencer enable signals provided to the plurality of sequencers; and

wherein the chaining circuitry comprises:
a first logic gate configured to receive the primary enable signal as a first input and output a first sequencer enable signal to a first sequencer of the plurality of sequencers and to a different sequencer; and
a last logic gate configured to receive an output signal of the different sequencer as a first input and output a second sequencer enable signal to a last sequencer of the plurality of sequencers.