Patent ID: 11907141
Assignee: QUALCOMM INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 18:
19. A memory controller configured to:
receive a first memory access command and a first address at which to implement the first memory access command in a logical rank;
generate a first signal configured to indicate to a first memory device of the logical rank to implement the first memory access command via a first partial channel;
send the first signal to the first memory device;
generate a second signal configured to indicate to a second memory device of the logical rank that is different from the first memory device to implement the first memory access command via a second partial channel; and
send the second signal to the second memory device; and
determine whether the first address at which to implement the first memory access command in the logical rank is at the logical rank; and
generate the first signal, sending the first signal, generate the second signal, and send the second signal occur in response to determining that the first address at which to implement the first memory access command in the logical rank is at the logical rank.