Patent ID: 11940926
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. The non-transitory computer-readable medium of claim 10, wherein the instructions are further executable by the one or more processors to:
determine whether a second subset of logical addresses of the set of logical addresses is sequential;
generate a second set of entries associated with the first level of the mapping information based at least in part on the determining, each entry of the second set of entries indicating a second mapping between a logical address of the second subset of logical addresses and a physical address of a second set of physical addresses; and
update the entry in the second level of the mapping information based at least in part on the generating, the updated entry comprising an exception pointer indicating the second mapping between the subset of logical addresses and the second set of physical addresses based at least in part on the second subset of logical addresses not being sequential.