Patent ID: 11862236
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 16:
17. The integrated-circuit memory component of claim 11 wherein the command/address interface is further to receive a row command/address value a second command/address value that specifies a memory write access, and wherein the control circuitry comprises circuitry that:
in response to specification of the first operating mode, receives first write data via the fixed-width data interface over Q successive data reception intervals and decodes a third column address constituted by N bits of the second command/address value to store the first write data within a second one of the 2N independently accessible regions of the page buffer; and
in response to specification of the first operating mode, receives second write data via the fixed-width data interface over R successive data reception intervals and decodes a fourth column address constituted by M bits of the second command/address value to store the second write data within a second one of the 2M independently accessible regions of the page buffer.