Patent ID: 11910620
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 13:
14. A method for fabricating a semiconductor structure, comprising:
forming a metal line;
forming a magnetic tunneling junction (MTJ) layer over the metal line, wherein the MTJ layer comprises a first material;
forming a top electrode layer over the MTJ layer;
patterning the top electrode layer with a first mask, thereby forming a top electrode and exposing a top surface of the MTJ layer;
forming a first dielectric layer over a sidewall of the top electrode; and
partially removing the MTJ layer to form an MTJ after forming the first dielectric layer, thereby generating residue over an outer sidewall of the first dielectric layer, wherein the residue comprises the first material;
forming a second dielectric layer over the first dielectric layer to encapsulate the residue; and
forming an insulation layer surrounding the second dielectric layer.