Patent ID: 11923297
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 15:
16. A semiconductor structure, comprising:
a plurality of gate structures;
a plurality of first metal lines formed in a first dielectric layer below the plurality of gate structures, wherein the plurality of first metal lines is at a back side of an integrated circuit (IC) with a plurality of input/output (I/O) pins;
at least one first via formed in a second dielectric layer that is between the plurality of gate structures and the first dielectric layer, wherein each of the at least one first via is electrically connected to the plurality of gate structures and a corresponding one of the plurality of first metal lines;
a plurality of second metal lines formed in a third dielectric layer over the plurality of gate structures, wherein the plurality of second metal lines is at a front side of the IC, wherein:
at least one first pin of the plurality of I/O pins is routed from the back side of the IC, wherein the at least one first pin toggles between a power supply voltage level and a ground voltage level when the IC is powered on, and
at least one second pin of the plurality of I/O pins is routed from the front side of the IC, wherein the at least one second pin toggles between the power supply voltage level and the ground voltage level when the IC is powered on; and

at least one second via formed in a fourth dielectric layer that is between the plurality of gate structures and the third dielectric layer, wherein each of the at least one second via is electrically connected to the plurality of gate structures and a corresponding one of the plurality of second metal lines.