Patent ID: 11862267
Assignee: NETLIST, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 22:
23. The memory module of claim 22, wherein the data module includes first and second data handlers in first and second integrated circuit packages, respectively, and wherein:
during the normal memory read or write operation, the first integrated circuit package is configurable to propagate first data signals between a first n-bit-wide portion of the memory devices and a first n-bit-wide segment of the system memory bus, and the second integrated circuit package is configurable to propagate second data signals between a second n-bit-wide portion of the memory devices and a second n-bit-wide segment of the system memory bus independently of and concurrently with the first integrated circuit package propagating the first data signals; and
during testing of the memory module, the first integrated circuit package is configurable to write first test data into at least one first memory device by outputting first test data signals, and the second integrated circuit package is configurable to write second test data into at least one second memory device by outputting second test data signals independently of and concurrently with the first integrated circuit package outputting the first test data signals.