Patent ID: 11921537
Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. An integrated circuit, comprising:
a clock phase generator configured to receive a first clock signal and to output a plurality of phase signals;
a phase selector configured to receive the plurality of phase signals and a second clock signal, to compare the phase signals to the second clock signal, and to select one of the phase signals based on the comparison;
data output circuitry including:
a first clock terminal configured to receive the selected phase signal; and
a data output terminal configured to output data; and

data input circuitry including:
a first clock terminal configured to receive the second clock signal; and
a data input terminal coupled to the data output terminal and configured to receive the data.