Patent ID: 11935607
Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. A method of testing an integrated circuit die that includes a plurality of memory sectors, with each memory sector including a memory array, the method comprising:
generating an output voltage based upon a difference between a constant current and a leakage current;
driving a first transistor with the output voltage to produce a gate voltage, the gate voltage being a regulated voltage;
connecting the gate voltage to a selected one of the plurality of memory sectors;
driving a second transistor with the output voltage to thereby generate a copy voltage based upon a difference between a variable current and a replica of the constant current;
increasing the variable current in response to the copy voltage being greater than the gate voltage; and
asserting a leakage detection signal in response to the copy voltage being less than the gate voltage, the leakage detection signal indicating excess leakage within the memory array of the selected one of the memory sectors.