Patent ID: 11868163
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G  H

Claim 0:
1. A configurable circuit, comprising:
a configurable computation circuit;
an asynchronous network input queue coupled to an asynchronous packet network;
an asynchronous network output queue coupled to the asynchronous packet network; and
a control circuit coupled to the configurable computation circuit, the control circuit comprising:
a plurality of control registers configured to store a completion table having a plurality of thread identifiers and a loop count of an active number of loop threads, the plurality of control registers further configured to store a thread identifier pool having a predetermined number of thread identifiers of the plurality of thread identifiers; and
a thread control circuit configured, in response to receipt of an asynchronous packet network message returning a thread identifier of the plurality of thread identifiers to the thread identifier pool, to decrement the loop count and, when the loop count reaches zero, to generate an asynchronous packet network completion message for transmission on the asynchronous packet network from the asynchronous network output queue.