Patent ID: 11868661
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A memory device, comprising:
rows of memory cells addressable via row addresses, each having a plurality of segments;
counters corresponding to sub-addresses in the plurality of segments, wherein the counters are configured to count activation commands applied to row addresses having the sub-addresses corresponding to the counters;
a logic circuit configured to:
determine, for each respective segment in the plurality of segments, whether at least one first sub-address in the respective segment have been applied a count of activation commands that is more than a threshold according to a counter corresponding to the first sub-address among the counters;
determine whether each of the plurality of row address segments has at least one sub-address having been applied more activation commands than the threshold; and
generate an alert in response to a determination that each of the plurality of row address segments has at least one sub-address having been applied more activation commands than the threshold.