Patent ID: 11887892
Assignee: MAGNACHIP SEMICONDUCTOR, LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A method for forming a semiconductor die, the method comprising:
forming a first interlayer dielectric layer on a substrate having a die region and a scribe line region;
forming a second interlayer dielectric layer on the first interlayer dielectric layer;
forming a metal pad in the die region and a test pad in the scribe line region, respectively, on the second interlayer dielectric layer;
forming a passivation dielectric layer on the second interlayer dielectric layer, the metal pad, and the test pad;
performing a first etching process on the passivation dielectric layer and the first and second interlayer dielectric layers formed on both sides of the test pad using a plasma etching process to expose a surface of the substrate;
performing a second etching process on the passivation dielectric layer formed on the metal pad and the test pad to expose the metal pad and the test pad;
forming a bump on the metal pad; and
dicing the substrate while removing the scribe line region using a blade dicing process.