Patent ID: 11860225
Assignee: RENESAS ELECTRONICS CORPORATION
Field: Measurement (Instruments)
Classification: CPC G | IPC G

Claim 0:
1. A method of manufacturing a semiconductor device, comprising:
(a) preparing a test apparatus provided with following (a1), (a2) and (a3):
(a1) a test board having a terminal,
(a2) a unit having a first surface and a second surface opposite the first surface, the unit being arranged such that the second surface faces the test board, and
(a3) a probe pin including a first tip portion and a second tip portion having the same shape as the first tip portion, the second tip portion being located on opposite side of the first tip portion, and the probe pin being housed in the unit such that the first tip portion protrudes from the first surface and such that the second tip portion protrudes from the second surface;

(b) preparing a first semiconductor package having a first external terminal;
(c) after the (a) and the (b), bringing the first external terminal of the first semiconductor package into contact with the first tip portion of the probe pin and bringing the second tip portion of the probe pin into contact with the terminal of the test board, thereby performing an electrical test of the first semiconductor package;
(d) after the (c), in the test apparatus, removing the unit, and rearranging the unit such that the first surface faces the test board;
(e) preparing a second semiconductor package having a second external terminal; and
(f) after the (d) and the (e), bringing the second external terminal of the second semiconductor package into contact with the second tip portion of the probe pin and bringing the first tip portion of the probe pin into contact with the terminal of the test board, thereby performing an electrical test of the second semiconductor package.