Patent ID: 11936179
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An electrostatic discharge protection circuit in a chip, wherein the chip comprises a power pad, a ground pad, and an input/output (I/O) pad, and the electrostatic discharge protection circuit comprises:
a discharge unit, connected to the power pad, the ground pad, and the I/O pad, wherein the discharge unit is configured to discharge an electrostatic charge when an electrostatic pulse appears on any of the power pad, the ground pad, and the I/O pad; and
the discharge unit comprises a first discharge unit and a second discharge unit, the first discharge unit is connected to the second discharge unit, the power pad, and the I/O pad, and the second discharge unit is connected to the ground pad and the I/O pad,
wherein the first discharge unit comprises:
a first discharge transistor having an emitter connected to the power pad;
a second discharge transistor having a base connected to a collector of the first discharge transistor and an emitter connected to the I/O pad; and
a third discharge transistor having an emitter connected to the power pad and a base connected to a base of the first discharge transistor.