Patent ID: 11894840
Assignee: PSEMI CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 11:
12. The invention of claim 8, further including a slow charge circuit including:
(a) a first resistor coupled to the first pin;
(b) a second resistor coupled to the second pin;
(c) a slow charge transistor having a conduction channel coupled between the first resistor and the second resistor, and having a gate; and
(d) a logic gate having an output coupled to the gate of the slow charge transistor, and an input configured to be coupled to a control signal;
wherein the slow charge transistor is selectively settable to a conductive state in response to the application of the control signal to the input of the logic gate so as to convey charge from an input/output line coupled to one of the first or second pins to the storage capacitor coupled to the other of the first or second pins; and
wherein the resistance of the first and second resistors is sufficient to limit a charging rate of the storage capacitor to below a specified level.