Patent ID: 11894096
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory system comprising:
a memory device including a memory area configured to store data and an input/output (I/O) buffering part configured to store data outputted from the memory area; and
a memory controller configured to control read operations of the memory device,
wherein the memory device is configured to store data of all columns in a selected row designated by a first row address among a plurality of rows in the memory area into the I/O buffering part in response to an external command outputted from the memory controller and is configured to output data of a selected column designated by a first column address among the data stored in the I/O buffering part, and
wherein the memory controller is configured to perform a scheduling operation for successively executing read request commands having the same row address among a plurality of read request commands for performing read operations of the memory device.