Patent ID: 11894260
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC B  H

Claim 11:
12. A semiconductor structure comprising:
a first transistor comprising:
a first plurality of nanostructures over a substrate, and
a first gate structure wrapping around the first plurality of nanostructures;

a second transistor comprising:
a second plurality of nanostructures over the substrate, and
a second gate structure wrapping around the second plurality of nanostructures;

and
an isolation structure disposed between the first transistor and the second transistor and configured to provide isolation between the first and second gate structures,
wherein the isolation structure comprises a work-function layer on sidewalls of the first and second gate structures, and a dielectric layer wrapped by the work-function layer, and
wherein the isolation structure extends into the substrate.