Patent ID: 11963348
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A method of manufacturing an integrated circuit structure, comprising:
forming a first transistor comprising a first gate electrode, a first channel, a first source, a first source conductive line over the first source, a first drain, and a first drain conductive line over the first drain;
forming a second transistor comprising a second gate electrode, a second channel, a second drain, the first source, and a second drain conductive line over the second drain;
removing a portion of the second gate electrode and an underlying portion of the second channel to form a trench separating the first source and the second drain;
depositing a dielectric material to fill the trench and isolate the first source and the second drain; and
forming a bit line that electrically connects the first drain conductive line to the second drain conductive line.