Patent ID: 11908515
Assignee: HEFEI RELIANCE MEMORY LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. The apparatus of claim 1, wherein:
the first word line is electrically coupled to a gate of the second transistor of the first memory cell and a gate of the second transistor of the third memory cell;
the second word line is electrically coupled to a gate of the second transistor of the second memory cell and a gate of the second transistor of the fourth memory cell;
the third word line is electrically coupled to a gate of the first transistor of the first memory cell and a gate of the first transistor of the third memory cell; and
the fourth word line is electrically coupled to a gate of the first transistor of the second memory cell and a gate of the first transistor of the fourth memory cell.