Patent ID: 11955448
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An electronic package, comprising:
a package substrate;
a bridge substrate embedded in the package substrate;
first pads over the package substrate, wherein the first pads have a first pitch;
second pads over the bridge substrate, wherein the second pads have a second pitch that is smaller than the first pitch;
a barrier layer over individual ones of the second pads; and
a reflown solder over individual ones of the first pads and over individual ones of the second pads, wherein a first standoff height of the reflown solder over the first pads is equal to a second standoff height of the reflown solder over the second pads, and wherein a bottommost surface of the reflown solder over the first pads is below a bottommost surface of the reflown solder over the second pads.