Patent ID: 11963370
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 12:
13. A memory device comprising:
an array of memory cells arranged in a plurality of decks;
a plurality of access lines comprising at least a first plurality of access lines arranged in a first level, a second plurality of access lines arranged in a second level, and a third plurality of access lines arranged in a third level between the first level and the second level, the third plurality of access lines being arranged between two decks of the plurality of decks;
a plurality of drivers configured to drive signals to the access lines; and
connection elements configured to electrically connect the access lines to the respective drivers;
wherein the connections elements and the access lines are arranged so that a single driver of the plurality of drivers is configured to drive at least one access line of each level of the at least three levels, and
wherein the drivers of the plurality of drivers are substantially identical.