Patent ID: 11900994
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 17:
18. A method for operating a device that includes: an array of memory cells and a plurality of edge cells, comprising:
applying a logic high power to a sleep signal to generate an activated sleep signal;
shifting a first word line, coupled to a power header edge cell of the plurality of edge cells, from a logic low power to a logic high power based on the activated sleep signal;
turning off a pair of first transistors in the power header edge cell in response to shifting the first word line;
shifting a second word line, coupled to a power footer edge cell of the plurality of edge cells, from a logic high power to a logic low power based on the activated sleep signal;
turning off a pair of second transistors in the power footer edge cell in response to shifting the second word line; and
switching the array of memory cells from a normal power mode to a power down mode based on turning off the first and second transistors.