Patent ID: 11923457
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A method comprising:
forming one or more semiconductor material layers over a substrate;
forming a high-k dielectric layer on the one or more semiconductor material layers;
patterning the high-k dielectric layer and the one or more semiconductor material layers to form a fin structure with the patterned high-k dielectric layer covering a top surface of the fin structure;
forming an interlevel dielectric layer over the fin structure;
forming a trench through the interlevel dielectric layer, wherein a first portion of the patterned high-k dielectric layer is exposed within the trench;
removing the first portion of the patterned high-k dielectric layer to expose a first portion of the top surface of the fin structure;
forming a gate dielectric layer on the first portion of the top surface of the fin structure, wherein the gate dielectric layer interfaces with a second portion of the patterned high-k dielectric layer; and
forming a gate electrode layer on the gate dielectric layer.