Patent ID: 11972188
Assignee: NVIDIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 24:
25. A system, comprising:
a memory that stores power density values for a plurality of cells in an initial cell placement for an integrated circuit layout, wherein the initial cell placement is subdivided into multiple regions, and wherein at least a first region of the multiple regions includes multiple power supply rails and a first portion of the cells of the plurality of cells in the initial cell placement; and
a processor that is connected to the memory, wherein the processor is configured to:
compute a per-rail power density value for each power supply rail within the first region based on the power density values of the first portion of the cells
for each of a plurality of cell placements of the first portion of the cells, evaluate an objective function based on the per-rail power density values to generate a result value;
select a cell placement of the plurality of cell placements, in response to the result values, wherein the steps of obtaining, computing, and evaluating are executed for at least one additional region of the multiple regions to produce an optimized cell placement for the integrated circuit layout; and
subdivide the optimized cell placement into multiple second regions and repeating the computing, evaluating, and selecting for the second regions to produce a further optimized cell placement for the integrated circuit layout.