Patent ID: 11894274
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A method comprising:
forming dielectric isolation regions extending into a semiconductor substrate, with a first semiconductor strip and a second semiconductor strip being between the dielectric isolation regions;
replacing the second semiconductor strip with a dielectric strip;
recessing the dielectric isolation regions, so that top portions of the first semiconductor strip and the dielectric strip protrude higher than top surfaces of the recessed dielectric isolation regions to form a semiconductor fin and a dummy fin, respectively; and
after the dielectric isolation regions are recessed, recessing a first portion of the dummy fin and a first portion of the semiconductor fin in a common etching process, wherein a first top surface the first semiconductor strip is recessed to be lower than a second top surface of the first portion of the dummy fin by the common etching process.