Patent ID: 11921641
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A data storage device, comprising:
a nonvolatile memory having a plurality of superblocks mapped to a plurality of zones, each of the plurality of zones being of a type requiring sequential write of host data, an erase block being a minimum erasable unit of the plurality of superblocks; and
a controller coupled to the nonvolatile memory and configured to perform logical-to-physical (L2P) address translation using a compacted L2P table having an erase-block granularity; and
wherein, for a logical address of a zone of the plurality of zones, the controller is configured to obtain a corresponding physical address by:
retrieving a physical address of a corresponding erase block from the compacted L2P table based on the logical address;
calculating a corresponding word-line number, a corresponding string-line number, a corresponding page-type identifier, and a corresponding page offset based on the logical address; and
combining the retrieved physical address with the corresponding word-line number, the corresponding string-line number, the corresponding page-type identifier, and the corresponding page offset that are calculated to obtain the corresponding physical address.