Patent ID: 11903192
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. An integrated chip, comprising:
a first gate structure over a substrate;
a first sidewall spacer arranged along opposing sides of the first gate structure, wherein the first gate structure protrudes outward from a top of the first sidewall spacer;
a conductive contact disposed on the first gate structure, wherein the top of the first sidewall spacer is a non-zero distance below a bottom of the conductive contact;
a second gate structure over the substrate;
a second sidewall spacer arranged along opposing sides of the second gate structure, wherein the second gate structure protrudes outward from a top of the second sidewall spacer; and
wherein lines extending along substantially linear segments of the first sidewall spacer and the second sidewall spacer intersect to define a “V” shape as viewed in a cross-sectional view.