Patent ID: 11862218
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A memory device, comprising:
a memory cell array comprising a plurality of magnetic tunnel junction (MTJ) memory cells arranged in columns and rows;
a read bias circuit connected to the memory cell array and configured to provide a reading bias for a MTJ memory cell of the memory cell array, wherein the MTJ memory cell comprises a selector transistor;
a first non-linear resistance device connected in series and between the MTJ memory cell and the read bias circuit, wherein the first non-linear resistance device is configured to provide a first resistance when conducting a first current and a second resistance greater than the first resistance when conducting a second current smaller than the first current; and
a pull-down circuit connected to one terminal of the selector transistor and configured to pull the MTJ cell to a lower voltage potential, wherein the pull-down circuit is different from the read bias circuit, the first non-linear resistance device, and the selector transistor.