Patent ID: 11876070
Assignee: MITSUI MINING & SMELTING CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for producing a semiconductor package, the method comprising:
(a) providing a tacky sheet comprising a substrate sheet, and a soluble tacky layer provided in an intermittent pattern on at least one surface of the substrate sheet;
(b) making a first laminate comprising a redistribution layer on a first support substrate;
(c) using the tacky sheet to obtain a second laminate having a second support substrate bonded to a surface on the redistribution layer side of the first laminate with the soluble tacky layer interposed therebetween;
(d) peeling off the first support substrate from the second laminate to obtain a third laminate wherein a surface of the redistribution layer away from the second support substrate is exposed;
(e) mounting a semiconductor chip on a surface on the redistribution layer side of the third laminate and sealing the semiconductor chip with a resin to obtain a fourth laminate comprising an outer peripheral end surface composed of an upper end surface, a lower end surface, a right end surface, and a left end surface;
(f) sealing the right end surface and the left end surface of the fourth laminate with a pair of sealing members and immersing the lower end surface of the fourth laminate selectively in a solution with an angle to allow the lower end surface to face downward and allow the upper end surface to face upward;
(g) giving a pressure difference between an internal space, which is between the second support substrate and the redistribution layer of the fourth laminate, and the solution to allow the solution to penetrate into the internal space by the pressure difference, thereby dissolving or softening the soluble tacky layer; and
(h) peeling off the second support substrate from the fourth laminate in a state where the soluble tacky layer is dissolved or softened to obtain the semiconductor package.