Patent ID: 11894348
Assignee: HITACHI ASTEMO, LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 4:
5. A manufacturing method of a power semiconductor device including:
a first submodule including a first power semiconductor element;
a second submodule including a second power semiconductor element;
a positive electrode side conductor portion and a negative electrode side conductor portion;
a first intermediate substrate and a second intermediate substrate that sandwich the first submodule and the second submodule; and
a plurality of signal terminals that transmit a signal for controlling the first power semiconductor element or the second power semiconductor element, the manufacturing method comprising:
a first step of disposing the first submodule and the second submodule on the first intermediate substrate side by side with a soldering material interposed therebetween such that directions of an electrode surface of the second power semiconductor element and an electrode surface of the first power semiconductor element are inverted;
a second step of disposing the second intermediate substrate on the first submodule and the second submodule with a soldering material interposed therebetween on a side opposite to a side on which the first intermediate substrate is disposed in a manner that a non-stacked portion that does not overlap with the second intermediate substrate or the first intermediate substrate is provided;
a third step of joining the first submodule, the second submodule, the first intermediate substrate, and the second intermediate substrate by melting the soldering material; and
a fourth step of connecting a wire provided on the non-stacked portion and a plurality of signal terminals via a bonding wire.