Patent ID: 11947409
Assignee: XILINX, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An integrated circuit (IC) device comprising:
a plurality of registers; and
parity checking circuitry coupled to the plurality of registers and comprising:
a first parity circuit configured to receive first register values from the plurality of registers and determine a first value from the first register values, wherein the first register values correspond to first bits of two or more of the plurality of registers, and wherein the first register values have fewer bits than the plurality of registers;
a second parity circuit configured to receive second register values from the plurality of registers and determine a second value from the second register values, wherein the second register values correspond to second bits of the two or more of the plurality of registers; and
error detection circuitry configured to:
compare the first value and the second value to detect a first error within the plurality of registers; and
output an error signal indicating the first error.