Patent ID: 11894380
Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Field: nan (nan)
Classification: CPC nan | IPC G  H

Claim 0:
1. A semiconductor device comprising:
a plurality of circuits arranged in matrix,
wherein each of the plurality of circuits comprises a first transistor, a second transistor, first to sixth conductive layers, first and second insulating layers, and a capacitor,
wherein the first transistor comprises a first channel formation region,
wherein the second transistor comprises a second channel formation region formed in an oxide semiconductor layer,
wherein the first channel formation region comprises silicon,
wherein the second channel formation region comprises an oxide semiconductor,
wherein a gate electrode of the first transistor is electrically connected to the capacitor,
wherein the first conductive layer comprises a region configured to function as the gate electrode of the first transistor, the region being over the first channel formation region,
wherein the first conductive layer is electrically connected to one of the second conductive layer and the third conductive layer,
wherein the first insulating layer comprises a region in contact with a side surface of the first conductive layer,
wherein the second conductive layer comprises a region configured to function as one of a source electrode and a drain electrode of the second transistor, the region being over the first insulating layer,
wherein the third conductive layer comprises a region configured to function as the other of the source electrode and the drain electrode of the second transistor, the region being over the first insulating layer,
wherein the oxide semiconductor layer comprises a region over the second conductive layer, a region in contact with a side surface of the second conductive layer, a region in contact with a side surface of the third conductive layer, and a region over the third conductive layer,
wherein the fourth conductive layer comprises a region configured to function as a gate electrode of the second transistor, the region being over the second channel formation region,
wherein the fifth conductive layer comprises a region configured to function as an electrode of the capacitor,
wherein the fifth conductive layer is positioned at a same layer as the fourth conductive layer,
wherein the second insulating layer comprises a region over the fourth conductive layer and a region over the fifth conductive layer,
wherein the sixth conductive layer comprises a region over the second insulating layer, the sixth conductive layer being electrically connected to one of a source region and a drain region of the first transistor through a contact hole provided in the second insulating layer,
wherein the sixth conductive layer comprises a region overlapping with the capacitor with the second insulating layer therebetween, a region overlapping with the oxide semiconductor layer with the second insulating layer therebetween in a region between the fourth conductive layer and the fifth conductive layer, and a region overlapping with the second channel formation region with the second insulating layer and the fourth conductive layer therebetween,
wherein in a plan view of the plurality of circuits, a channel width direction of the second transistor is a first direction,
wherein in the plan view of the plurality of circuits, a width of the fourth conductive layer in the first direction is greater than a width of the fourth conductive layer in a second direction intersecting the first direction, and
wherein in the plan view of the plurality of circuits, a width of the fifth conductive layer in the first direction is greater than a width of the fifth conductive layer in the second direction.