Patent ID: 11942953
Assignee: ATI TECHNOLOGIES ULC
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 17:
18. A data processing system, comprising:
an integrated circuit including at least two processor tiles each comprising digital logic, a local DFLL providing a clock signal for synchronizing the digital logic, and a local power supply monitor for monitoring a respective monitored local supply voltage, each power supply monitor comprising:
a reference signal generator that receives a digital value and produces a pulse-density modulated signal based on the digital value;
a droop detection circuit that converts the pulse-density modulated signal to an analog signal, compares the analog signal to the respective monitored local supply voltage, and responsive to detecting a droop of the respective monitored local supply voltage below a designated value relative to the analog signal, produces a droop detection signal; and
a DFLL control circuit that, responsive to receiving the droop detection signal, causes the local DFLL to slow the clock signal.