Patent ID: 11897539
Assignee: SEIKO EPSON CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC B  G  H | IPC B  G  H

Claim 1:
2. The circuit device according to claim 1 further comprising:
a second integration period signal generation circuit configured to generate a second integration period signal which turns to the active state in a second integration period having the predetermined period length after a second signal makes a transition;
a second polarity switching signal generation circuit configured to generate a third integration polarity switching signal making a transition of a voltage level at a timing synchronized with the reference clock signal in the second integration period after the second signal makes a transition, and a fourth integration polarity switching signal making a transition of a voltage level the predetermined clock count of the reference clock signal after a transition timing of the third integration polarity switching signal in the second integration period;
a third integration circuit configured to perform a third integrating process in which an integration polarity is switched at a transition timing of the third integration polarity switching signal;
a fourth integration circuit configured to perform a fourth integrating process in which an integration polarity is switched at a transition timing of the fourth integration polarity switching signal; and
a measurement circuit configured to obtain a digital value corresponding to a time difference in transition timing between the first signal and the second signal based on results of the first integrating process, the second integrating process, the third integrating process, and the fourth integrating process.