Patent ID: 11894087
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 18:
19. The test circuit according to claim 16,
wherein the control logic circuit comprises a first NAND gate, a first inverter, a second NAND gate, a second inverter, a third NAND gate, and a third inverter;
wherein an output terminal of the first NAND gate is connected with an input terminal of the first inverter, an output terminal of the second NAND gate is connected with an input terminal of the second inverter, and an output terminal of the third NAND gate is connected to an input terminal of the third inverter;
wherein the first NAND gate receives the first internal delay address and outputs a first signal;
wherein the first inverter receives the first signal and outputs a second signal;
wherein the second NAND gate receives the first signal and the test mode command, and outputs a third signal;
wherein the second inverter receives the third signal and outputs the test mode enable active signal;
wherein the third NAND gate receives the second signal and the test mode command, and outputs a fourth signal; and
wherein the third inverter receives the fourth signal and outputs the test mode enable slave signal.