Patent ID: 11907715
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A system, comprising:
a processor; and
a resistive processing unit coupled to the processor, the resistive processing unit comprising an array of cells, the cells respectively comprising resistive devices, a least a portion of the resistive devices being tunable to encode entries of a preconditioning matrix storable in the array of cells;
wherein, when the preconditioning matrix is stored in the array of cells, the processor is configured to apply the preconditioning matrix to a plurality of residual vectors by executing a process which comprises performing analog matrix-vector multiplication operations on the preconditioning matrix and respective ones of the plurality of residual vectors to generate a plurality of output vectors used in one or more subsequent operations,
wherein in a first iteration of at least a portion of the process, the processor is configured to:
input a first residual vector of the plurality of residual vectors to the array of cells;
utilize the resistive processing unit to perform a first matrix-vector multiplication operation by multiplying the first residual vector with the preconditioning matrix in the array of cells to generate a first output vector of the plurality of output vectors;
combine a given matrix with the first output vector to generate a first augmented matrix which is output from the array of cells;
perform a second matrix-vector multiplication operation; and
compute a second residual vector of the plurality of residual vectors based at least in part on the product of the second matrix-vector multiplication operation.