Patent ID: 11869604
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 4:
5. An apparatus, comprising:
a controller is configured to, for each dummy row of an array of memory cells:
responsive to a power-up of the array of memory cells coupled to the controller, determine whether a particular pattern is stored in at least one of the dummy rows, wherein the at least one of the dummy rows is associated with an address space that is outside of an address space of the array of memory cells, wherein a determination that the particular pattern is not stored in the at least one of the dummy rows is indicative of an incomplete erase of the array of memory cells;
responsive to determining that the particular pattern is not stored in the at least one of the dummy rows, execute an erase phase on the array of memory cells; and
responsive to a completion of the execution of the erase phase on the array of memory cells, store, in the at least one of the dummy rows, parameters of the completed erase phase as the parameters of an erasing operation on a subsequent execution of the erase phase.