Patent ID: 11899936
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A data transmission circuit, comprising:
a delay module generating a delayed read command after a first preset time delay when a mode register read command is received;
a mode register data processing unit, connecting to the delay module, wherein the mode register data processing unit reads setting parameters from the mode register in response to the mode register read command, and outputs the setting parameters in response to the delayed read command;
a command decoding circuit, wherein a first output terminal of the command decoding circuit is connected to an input terminal of the delay module and an input terminal of the mode register data processing unit, wherein the command decoding circuit receives a read command, decodes the read command, and determines whether the read command is the mode register read command; when the read command is the mode register read command, the command decoding circuit outputs the mode register read command, otherwise, the command decoding circuit generates an array area data read command; and
a data processing unit of the array area, wherein an input terminal of the data processing unit of the array area is connected to a second output terminal of the command decoding circuit and a storage unit array, wherein the data processing unit of the array area reads an array area data from the storage unit array in response to the array area data read command;
wherein a difference between an operation delay of the data processing unit in the array area and the first preset time is a preset threshold.