Patent ID: 11869933
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A method of forming an integrated circuit, comprising, comprising:
forming a metal terminal over a semiconductor substrate, the metal terminal being separated from the semiconductor substrate by a dielectric layer;
forming a first junction diode within the semiconductor substrate, the first junction diode having an anode-to-cathode direction oriented toward the metal terminal;
forming a second junction diode within the semiconductor substrate, the second junction diode having an anode-to-cathode direction oriented toward the metal terminal;
forming a third junction diode between the first and second junction diodes, the third junction diode sharing a first anode region with the first junction diode and sharing a cathode region with the second junction diode, the first anode region including a p-type region between a first n-type buried layer and an n-type well; and
forming a second anode region between the first n-type buried layer and a second n-type buried layer, the first n-type buried layer between the second n-type buried layer and the n-type well, and a fourth junction diode sharing the second anode region with the second junction diode.