Patent ID: 11907685
Assignee: GLOBALFOUNDRIES U.S. INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 15:
16. The method of claim 12, wherein the forming of the array of devices comprises forming an array of field effect transistors according to a specific design, with each corresponding region of the semiconductor layer of each field effect transistor including a channel region positioned laterally between a source region and a drain region,
wherein each corresponding region of the semiconductor layer of each first device is devoid of any junctions between the source region, the channel region, and the drain region therein and any of the randomly patterned dopant implant regions,
wherein each corresponding region of the semiconductor layer of each second device has a junction between at least one of the source region, the channel region, and the drain region therein and at least one of the randomly patterned dopant implant regions,
wherein the performance parameter values comprises threshold voltage values,
wherein the predetermined range comprises a predetermined threshold voltage range based on the specific design, and
wherein the randomly patterned dopant implant regions cause the threshold voltage values of the second devices to fall outside the predetermined threshold voltage range.