Patent ID: 11863304
Assignee: UNM RAINFOREST INNOVATIONS
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for a countermeasure to a side-channel attack to a computer system, the method comprising steps of:
performing by a field programmable gate array (FPGA) dynamic partial reconfiguration (DPR) to remove a correlation in power transient signals of an encryption algorithm implemented on an encryption hardware engine, the encryption hardware engine including one or more redundant locations, wherein the encryption algorithm embeds a randomization component of the encryption hardware engine that changes constantly implementation characteristics of one or more hardware components or hardware sub-components of the encryption hardware engine by disconnecting the one or more hardware components or hardware sub-components from the encryption hardware engine within the FPGA using the one or more redundant locations producing replicated components, wherein the replicated components change a corresponding path delay that changes behavior of a corresponding power trace of the FPGA to provide the countermeasure to the side-channel attack which introduces diversity and uncertainty to the power transient signals, wherein the one or more redundant locations allow the encryption hardware engine to run without stalls while DPR is performed on the one or more redundant locations disconnected from the FPGA, and
running the one or more hardware components or the hardware sub-components simultaneously and in parallel with the replicated components.