Patent ID: 11950425
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor memory device comprising:
a mold structure including gate electrodes stacked on a first substrate;
a channel structure that penetrates a first region of the mold structure;
a first through structure that penetrates a second region of the mold structure; and
a second through structure that penetrates a third region of the mold structure,
wherein the mold structure further includes:
memory cell blocks extending in a first direction and spaced apart in a second direction; and
a dummy block extending in the first direction and disposed between the memory cell blocks, wherein each of the memory cell blocks and the dummy block includes a cell region and an extension region arranged in the first direction, the first region is a cell region of one of the memory cell blocks, the second region is an extension region of the one of the memory cell blocks, and the third region is an extension region of the dummy block.