Patent ID: 11962308
Assignee: M31 TECHNOLOGY CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. The SAR ADC circuit of claim 1, wherein the second latch circuit is configured to generate a least significant bit of the digital signal according to the comparator output; the second latch circuit comprises:
a data latch, coupled to the second circuit terminal and the second set of input terminals, configured to, when triggered in response to the second trigger signal, store the comparator output to generate a data signal; and
a signal detector, coupled to the data latch, the signal detector being configured to detect the data signal to generate a valid signal indicating if the data signal is valid;
wherein when the valid signal indicates that the data signal is valid, the comparator circuit is configured to reset the comparator output according to the valid signal.