Patent ID: 11966329
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A method, comprising:
storing, in non-volatile media of a memory system having a quantity of memory units, an address map, the address map defining logical addresses in terms of physical addresses of the memory units in the non-volatile media;
loading, by a cache manager of the memory system, a first portion of the address map in a volatile memory of the memory system;
processing, by a controller of the memory system, requests from a host system to store data in the non-volatile media or retrieve data from the non-volatile media, the host system having a memory connected to the memory system via a communication channel;
loading, by the cache manager, a second portion of the address map in the memory of the host system;
changing or updating, during first operations involving logical addresses defined in the first portion of the address map stored in the volatile memory of the memory system, the first portion of the address map stored in the volatile memory of the memory system;
after the changing or updating of the first portion of the address map stored in the volatile memory of the memory system, and in response to an operation that uses a logical address defined in the second portion, the cache manager is configured to swap the first portion of the address map and the second portion of the address between the volatile memory of the solid-state drive memory system and the memory of the host system by:
retrieving the second portion of the address map from the memory of the host system through the communication channel and storing the second portion of the address map in the volatile memory of the memory system;
transmitting, by the cache manager, the first portion of the address map from the volatile memory of the memory system through the communication channel to the memory of the host system; and
identifying, during the powering up, the memory of the host system via a base address register;

after the second portion of the address map is swapped into the volatile memory of the memory system, changing or updating, during second operations involving logical addresses defined in the second portion of the address map, the second portion of the address map;
receiving, at the cache manager a request to shut down the memory system; and
after the second portion of the address map is swapped into the volatile memory of the memory system, storing, in the non-volatile media of the memory system by the cache manager in response to the request, the second portion of the address map from the volatile memory of the memory system that has been changed or updated during the second operations; and
after the first portion of the address map is swapped into the memory of the host system, storing, in the non-volatile media of the memory system by the cache manager in response to the request, the first portion of the address map from the memory of the host system that has been changed or updated during the first operations;
wherein the memory of the host system is accessible to the controller at a speed greater than accessing the non-volatile media;
wherein the non-volatile media includes a flash memory and the memory system is a solid-state drive;
performing, by the controller in response to a first request associated with the first operations, a real time analysis of data stored in the memory of the memory system, wherein the data stored in the memory of the memory system comprises sensor data collected from a plurality of sensors, and wherein the plurality of sensors are real time sensors connected to the memory system;
determining, by the controller based on the real time analysis, a reduced data set responsive to the first request; and
communicating, by the controller, the reduced data set to the host system.