Patent ID: 11916067
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A method of manufacturing an integrated circuit, comprising:
providing a semiconductor substrate comprising a first doped layer of a first conductivity type and a first dopant concentration;
forming a second doped layer of the first conductivity type within the first doped layer, the second doped layer having first and second layer portions with a greater dopant concentration than the first doped layer, the first layer portion spaced apart from the second layer portion laterally with respect to a top surface of the substrate, wherein a lightly doped portion of the first doped layer is located between the first and second layer portions;
forming one or more deep wells having an opposite second conductivity type that extend from the top surface to a buried layer having the second conductivity type, the one or more deep wells touching the second doped layer; and
forming a dielectric isolation structure between the first and second layer portions and directly contacting the lightly doped portion.