Patent ID: 11943915
Assignee: SK HYNIX INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A three-dimensional memory device comprising:
a lower stack and an upper stack stacked in a vertical direction and each including a plurality of word lines stacked alternately with a plurality of interlayer dielectric layers in the vertical direction, with a surface of word line extending in first and second directions that are substantially orthogonal to the vertical direction,
wherein the plurality of word lines and the plurality of interlayer dielectric layers of each of the lower stack and the upper stack are disposed in
a first cell part and a second cell part spaced apart in the first direction;
a coupling part extending in the first direction to couple the first cell part and the second cell part; and
a staircase part, adjacent to the coupling part in the second direction and extending parallel to the coupling part in the first direction, that includes a plurality of word lines, each word line having a pad area, with the plurality of pad areas of the plurality of word lines arranged in a stepwise manner between the first cell part and the second cell part,
wherein each word line in the staircase part having a pad area is electrically connected to one of a plurality of first vias extending through the pad area in the vertical direction, and the plurality of first vias extend vertically through the staircase part to contact, respectively, a plurality of second vias extending vertically through the coupling part.