Patent ID: 11877522
Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 7:
8. A system comprising:
a processor; and
a memory having instructions, when executed by the processor, configured to:
receive a selection of a first sink terminal having a minimum of a maximum rise time values for single flux quantum (SFQ) pulses from among a plurality of sink terminals associated with a target logic gate selected from among a plurality of logic gates associated with a superconducting circuit design,
receive an assignment of a phase to the target logic gate,
if the first sink terminal is not reachable within a predetermined range of arrival time, then insert a first Josephson transmission line (JTL) between a source terminal associated with the target logic gate and the first sink terminal,
upon determining that the first sink terminal is reachable, after an insertion of the first JTL, within the predetermined range of arrival time, remove the first sink terminal from among the plurality of sink terminals as being associated with a critical timing path, and
upon determining that the first sink terminal is not reachable, even after an insertion of the first JTL, within the predetermined range of arrival time, insert a second JTL between the source terminal associated with the target logic gate and the first sink terminal.