Patent ID: 11973112
Assignee: SILANNA ASIA PTE LTD
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. A transistor tile comprising:
a first NLDD region formed as a first collector region longitudinally spanning a first side of the transistor tile;
a second NLDD region formed as a second collector region longitudinally spanning a second side of the transistor tile;
a P-well formed as a base region located laterally between the first and second NLDD regions;
a base P+ region formed in the P-well; and
an emitter N+ region formed as an emitter region located laterally between the first and second collector regions and in the P-well;
wherein:
the base region and emitter region are both centered on a longitudinally extending, laterally located midline of the transistor tile; and
the base P+ region and the emitter N+ region are separated by a portion of the P-well.