Patent ID: 11862547
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. The substrate of claim 10, further comprising a third conductive layer in the body, wherein the third conductive layer is between the first and second conductive layers, wherein the third conductive layer is proximately below the first conductive layer, wherein the first interconnect has a first via, a second via, a first conductive line, and a second conductive line, wherein the second interconnect has a third via, a fourth via, a third conductive line, and a fourth conductive line, wherein the swapped structure is directly between the first conductive layer and the third conductive layer, and wherein the swapped structure is comprised of the second via, the first and second conductive lines, and the second conductive pad of the first interconnect, and comprised of the fourth via, the third and fourth conductive lines, and the fourth conductive pad of the second interconnect.