Patent ID: 11966683
Assignee: WUHAN UNIVERSITY
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 2:
3. The method for comprehensively evaluating the reliability of the multi-chip parallel IGBT module according to claim 2, wherein the linear correlation PPMCCC=r({right arrow over (x)}, {right arrow over (y)}l) between the gate-emitter voltage in the chip fatigue failure state and the healthy state is obtained from, PPMCC
      C
    
    =
    
      
        r
        ⁡
        
          (
          
            
              x
              →
            
            ,
            
              
                y
                →
              
              l
            
          
          )
        
      
      =
      
        
          
            ∑
            
              j
              =
              1
            
            h
          
          ⁢
          
            
              (
              
                
                  x
                  j
                
                -
                
                  x
                  -
                
              
              )
            
            ⁢
            
              (
              
                
                  y
                  ij
                
                -
                
                  
                    y
                    -
                  
                  i
                
              
              )
            
          
        
        
          
            
              ∑
              
                j
                =
                1
              
              h
            
            ⁢
            
              
                
                  (
                  
                    
                      x
                      j
                    
                    -
                    
                      x
                      -
                    
                  
                  )
                
                2
              
              ⁢
              
                
                  
                    ∑
                    
                      j
                      =
                      1
                    
                    h
                  
                  ⁢
                  
                    
                      (
                      
                        
                          y
                          ij
                        
                        -
                        
                          
                            y
                            -
                          
                          i
                        
                      
                      )
                    
                    2
                  
                
              
            
          
        
      
    
  
  ,

where h represents a number of selected samples, xj represents an observed value of a point j corresponding to the gate-emitter voltage eigenvector {right arrow over (x)} without chip failure, x represents a mean of observed values of the eigenvector {right arrow over (x)}, yij represents an observed value of the point j corresponding to the gate-emitter voltage eigenvector {right arrow over (y)}i when i chips fail, and yi represents a mean of observed values of the eigenvector {right arrow over (y)}i.