Patent ID: 11910619
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 15:
16. A method for forming a memory device, the method comprising:
forming a memory cell over a substrate;
forming a sidewall spacer structure on sidewalls of the memory cell, wherein the sidewall spacer structure comprises a first spacer layer, a second spacer layer, and a third spacer layer, wherein the second spacer layer is between the first and third spacer layers, wherein the first spacer layer comprises a first material and the second spacer layer comprises a second material different from the first material; and
forming an upper conductive structure on the memory cell, wherein the upper conductive structure abuts a sidewall of the third spacer layer and contacts the second spacer layer, wherein the second spacer layer contacts a bottom surface of the upper conductive structure and a first sidewall of the sidewalls of the memory cell.