Patent ID: 11944019
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 17:
18. A method of forming a memory device, comprising:
providing a substrate having a transistor thereon;
forming an interconnect structure over and electrically connected to the transistor; and
forming a memory stack disposed between two adjacent metallization layers of the interconnect structure, wherein the memory stack comprises:
a bottom electrode disposed over the substrate and serving as a bit line extending in a first direction;
a top electrode disposed over the bottom electrode and serving as a word line extending in a second direction different from the first direction; and
a selector structure and a memory layer provided between the bottom electrode and the top electrode,
wherein the selector structure comprises a first material and at least one second material in direct contact with each other, the first material is a nitrogen-containing layer, and the at least one second material is a nitrogen-free layer.