Patent ID: 11935882
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 9:
10. A memory device, comprising:
first and second peripheral circuits;
first array comprising a first plurality of bit cells and second array comprising a second plurality of bit cells disposed between the first and second peripheral circuits, wherein bit lines of the first plurality of bit cells are electrically connected to the first peripheral circuit and bit lines of the second plurality of bit cells are electrically connected to the second peripheral circuit; and
a plurality of abutting dummy cells disposed between the first and second arrays, wherein:
the plurality of abutting dummy cells comprise:
a plurality of dummy gate electrode layers having a length extending in a first direction;
a plurality of dummy contacts having a length extending in the first direction and parallel to the plurality of dummy gate electrode layers,
wherein at least one of the plurality of dummy contacts extends, in the first direction, continuously across the plurality of abutting dummy cells;
wherein a length of an abutting dummy cell in the first direction is equal to a length of a bit cell in the first direction, and
a width of an abutting dummy cell in a second direction perpendicular to the first direction is equal to or less than two times a width of a bit cell in the second direction.