Patent ID: 11928018
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. The apparatus of claim 13, wherein the logic comprises:
first logic comprising a first AND gate, wherein a first input of the first AND gate is configured to receive an inverted version of the indication and a second input of the first AND gate is configured to receive an inverted version of the result of the second error management procedure,
second logic comprising a second AND gate, wherein a first input of the second AND gate is configured to receive the indication and a second input of the second AND gate is configured to the inverted version of the result of the second error management procedure,
third logic comprising a third AND gate, wherein a first input of the third AND gate is configured to receive the inverted version of the indication and a second input of the third AND gate is configured to receive the result of the second error management procedure, and
fourth logic comprising a fourth AND gate, wherein a first input of the fourth AND gate is configured to receive the indication and a second input of the fourth AND gate is configured to receive the result of the second error management procedure.