Patent ID: 11967394
Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. The memory system of claim 13, further comprising:
a plurality of first word lines (WLs) each coupled a first memory row circuit of the plurality of first memory row circuits;
a plurality of second WLs each coupled to a second memory row circuit of the plurality of second memory row circuits;
a plurality of third WLs each coupled a third memory row circuit of the plurality of third memory row circuits;
a plurality of fourth WLs each coupled to a fourth memory row circuit of the plurality of fourth memory row circuits; and
a memory driver circuit coupled to the plurality of first WLs, the plurality of second WLs, the plurality of third WLs and the plurality of fourth WLs;
the memory driver circuit configured to:
receive a memory access request comprising a memory address corresponding to one of the first memory sub-bank and the second memory sub-bank; and
in response to the memory access request to the first memory sub-bank:
activate one of a first WL of the plurality of first WLs and a second WL of the plurality of second WLs, in response to the memory address corresponding to a respective one of:
the first memory row circuit of the plurality of first memory row circuits coupled to the activated first WL; and
the second memory row circuit of the plurality of second memory row circuits coupled to the activated second WL; and

in response to the memory access request to the second memory sub-bank:
activate one of a third WL of the plurality of third WLs and a fourth WL of the plurality of fourth WLs, in response to the memory address corresponding to a respective one of:
 the third memory row circuit of the plurality of third memory row circuits coupled to the activated third WL; and
 the fourth memory row circuit of the plurality of fourth memory row circuits coupled to the activated fourth WL.