Patent ID: 11879942
Assignee: MICRON TECHNOLOGY, INC.
Field: Measurement (Instruments)
Classification: CPC G | IPC G

Claim 18:
19. A method, comprising:
loading test data into at least one of:
a plurality of input scan flip-flops of a first integrated circuit, wherein the plurality of input scan flip-flops are arranged in a plurality of input scan flip-flop stages,
a plurality of output scan flip-flops of the first integrated circuit, wherein the plurality of output scan flip-flops are arranged in a plurality of output scan flip-flop stages, or
a plurality of core scan flip-flops of the first integrated circuit,
wherein a first stage of core scan flip-flops, included in the plurality of core scan flip-flops, are connected to a final input scan flip-flop stage of the plurality of input scan flip-flop stages, and
wherein a second stage of core scan flip-flops, included in the plurality of core scan flip-flops, are connected to an initial output scan flip-flop stage of the plurality of output scan flip-flop stages;

executing a test associated with the first integrated circuit based on loading the test data into at least one of the plurality of input scan flip-flops, the plurality of output scan flip-flops, or the plurality of core scan flip-flops; and
obtaining test results of executing the test.