Patent ID: 11869886
Assignee: SEIKO EPSON CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. The ESD protection circuit according to claim 1, further comprising:
a fourth diode which is disposed between a first terminal of the protection target circuit and a fifth line configured to supply a fifth potential as a potential higher than the second potential, and an anode and a cathode of which are coupled respectively to the first terminal and the fifth line, the protection target circuit having the first terminal and a second terminal with a transmission gate;
a fifth diode which is disposed between the second line and the first terminal, and an anode and a cathode of which are coupled respectively to the second line and the first terminal;
a sixth diode which is disposed between the second terminal and the fifth line, and an anode and a cathode of which are coupled respectively to the second terminal and the fifth line;
a seventh diode which is disposed between the second line and the second terminal, and an anode and a cathode of which are coupled respectively to the second line and the second terminal; and
an eighth diode which is disposed between the third line and the fifth line, and an anode and a cathode of which are coupled respectively to the third line and the fifth line.