Patent ID: 11948053
Assignee: MEGH COMPUTING, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. A method for use with a computing system, the method comprising:
at development time:
receiving a machine learning model topology including a plurality of layers; and
generating an internal representation graph of the machine learning model topology, wherein the internal representation graph includes a plurality of internal representation layers; and
at least in part by performing one or more modifications to the internal representation graph, generating an inferencer graph including a plurality of inferencer layer blocks, wherein each inferencer layer block indicates an input buffer size, a logic function, and an output buffer size; and

at deployment time, transmitting, to a plurality of processing devices, instructions to implement the machine learning model topology with the respective input buffer sizes, logic functions, and output buffer sizes indicated in the plurality of inferencer layer blocks of the inferencer graph.