Patent ID: 11960358
Assignee: NXP B.V.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. A memory controller configured to read data from a memory array, comprising:
an error correction code (ECC) encoder configured to encode data stored in the memory array;
an ECC decoder configured to decode first data read from the memory array based upon a first read request and detect errors in the first data read from the memory array; and
a fault controller configured to:
command the memory controller to read other data from the memory array when the ECC decoder detects a correctable error;
command the memory controller to re-read the first data from the memory array;

when the ECC decoder detects a correctable error;
compare the re-read first data to the read first data;
signal a fault attack when the re-read first data is different from the read first data; and
signal a fault attack when the ECC decoder detects an uncorrectable error

wherein the memory controller returns the first data read from the memory array when the re-read first data is the same as the read first data, and
wherein the memory controller returns the first data read from the memory array when the ECC decoder detects no error in the first data read from the memory array.