Patent ID: 11881521
Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 0:
1. A semiconductor device, comprising:
a structure having N gate electrode layers and (N−1) channel formation region layers (where N≥3) alternately juxtaposed on an insulating material layer of a base in which the insulating material layer is formed on a surface of a conductive substrate,
wherein the structure has a bottom surface, a top surface opposing the bottom surface, a first side surface, a second side surface, a third side surface opposing the first side surface, and a fourth side surface opposing the second side surface,
wherein the channel formation region layers each have a bottom surface, a top surface, a first side surface, a second side surface, a third side surface, and a fourth side surface opposing the second side surface,
wherein the gate electrode layers each have a bottom surface, a top surface, a first side surface, a second side surface, a third side surface, and a fourth side surface opposing the second side surface,
wherein the second side surface of a first layer of the gate electrode layers forms at least a portion of the second side surface of the structure,
wherein the fourth side surface of an Nth layer of the gate electrode layers forms at least a portion of the fourth side surface of the structure,
wherein the second side surface of an nth (where n=1, 2, . . . , (N−1)) layer of the channel formation region layers faces the fourth side surface of an nth gate electrode layer,
wherein the fourth side surface of the nth layer of the channel formation region layers faces the second side surface of a (n+1)th layer of the gate electrode layers,
wherein one of an odd-numbered layer of the gate electrode layers and an even-numbered layer of the gate electrode layers is connected to a first contact portion and the other is connected to a second contact portion,
wherein an insulating film is on the first and third side surfaces of each of the gate electrode layers,
wherein an insulating portion is on the second side surface of each of the channel formation region layers, and
wherein an insulating portion is on the fourth side surface of each of the channel formation region layers.