Patent ID: 11901297
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. The method of claim 1, further comprising:
forming a plurality of gate lines on the peripheral area of the substrate;
forming a plurality of logic bit lines on the plurality of gate lines; and
forming a second wiring contact plug electrically connecting at least another one of the plurality of wiring lines to at least one of the plurality of logic bit lines,
wherein a height of the second wiring contact plug is greater than a height of the first wiring contact plug,
wherein the filling insulation layer further has a second wiring contact hole, and the second wiring contact plug fills the second wiring contact hole, and
wherein the second wiring contact plug extends through the filling insulation layer to inside the at least one of the plurality of logic bit lines.