Patent ID: 11973113
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor device, comprising:
a substrate having a lower portion and an upper portion on the lower portion;
an isolation region disposed on the lower portion of the substrate and surrounding the upper portion of the substrate in a closed path;
a gate structure disposed on and across the upper portion of the substrate;
source and/or drain (S/D) regions disposed in the upper portion of the substrate at opposite sides of the gate structure; and
a channel region disposed below the gate structure and abutting between the S/D regions, wherein the channel region and the S/D regions have different conductivity types, and the channel region and the substrate have the same conductivity type, wherein the isolation region comprises:
a dielectric material extending from a top surface of the upper portion to a top surface of the lower portion; and
a doped region wrapping a sidewall and a bottom surface of the dielectric material, wherein the doped region and the S/D regions have different conductivity types.