Patent ID: 11894063
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A semiconductor memory device comprising:
a substrate;
a plurality of first conductive layers arranged in a first direction intersecting with a surface of the substrate;
a second conductive layer disposed at a position overlapping with the plurality of first conductive layers viewed from the first direction;
a third conductive layer disposed at a position overlapping with the plurality of first conductive layers viewed from the first direction, the third conductive layer being arranged with the second conductive layer in a second direction intersecting with the first direction;
a plurality of first semiconductor column rows arranged in the second direction;
a plurality of first electric charge accumulating layers disposed between each of a plurality of first semiconductor columns included in the plurality of first semiconductor column rows and the plurality of first conductive layers;
a plurality of second semiconductor column rows arranged in the second direction;
a plurality of second electric charge accumulating layers disposed between each of a plurality of second semiconductor columns included in the plurality of second semiconductor column rows and the plurality of first conductive layers;
a fourth conductive layer disposed between the second conductive layer and the third conductive layer, the fourth conductive layer extending in a third direction intersecting with the first direction and the second direction;
a first insulating layer disposed between the second conductive layer and the fourth conductive layer; and
a second insulating layer disposed between the third conductive layer and the fourth conductive layer, wherein
the plurality of first semiconductor column rows each include the plurality of first semiconductor columns arranged in the third direction,
the plurality of first semiconductor columns are each opposed to the plurality of first conductive layers and the second conductive layer,
the plurality of second semiconductor column rows each include the plurality of second semiconductor columns arranged in the third direction,
the plurality of second semiconductor columns are each opposed to the plurality of first conductive layers and the third conductive layer, and
assuming that a cross-section extending in the second direction and the third direction and including one of the plurality of first conductive layers is a first cross-section, and
a distance in the second direction between center positions on the first cross-section of two first semiconductor column rows adjacent in the second direction is a first distance,
the fourth conductive layer has a length in the second direction smaller than a length of the second conductive layer in the second direction, a length of the third conductive layer in the second direction, and the first distance.