Patent ID: 11934867
Assignee: NVIDIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A system comprising:
a memory to store an application; and
an execution scheduler configured to:
generate at least one warp for the application, the at least one warp comprising a plurality of threads; and
relinquish control from a first thread of the warp to a second thread of the warp on condition that:

the first thread encounters a long stall hint instruction inserted in the first thread, triggering a run-time test;
the run-time test detects a long stall;
the first thread and the second thread are divergent threads; and
wherein the long stall hint instruction is inserted in the first thread between a long-latency producer instruction and a consumer instruction that utilizes a result of the long-latency producer instruction.