Patent ID: 11922992
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 4:
5. The memory device of claim 4, wherein the sub word line driving signal encoder comprises:
a plurality of first AND circuits configured to commonly receive the odd signal, receive the plurality of first sub word line driving signals in the first order, and output an AND operation result on the odd signal and the plurality of first sub word line driving signals in the first order;
a plurality of second AND circuits configured to commonly receive the even signal, receive the plurality of first sub word line driving signals in the second order, and output an AND operation result on the even signal and the plurality of first sub word line driving signals in the second order;
a plurality of first NOR circuits each configured to receive one AND operation result among the plurality of first AND circuits and one AND operation result among the plurality of second AND circuits and perform a NOR operation on the received AND operation results; and
a plurality of first inverters configured to perform an inverting operation on output values of the plurality of first NOR circuits.