Patent ID: 11966740
Assignee: GRAPHCORE LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A processor comprising:
at least one register file comprising a group of operand registers for holding data values loaded from memory or to be stored back to memory, each operand register being a fixed number of bits in length for holding a respective data value of the length; and
processing logic comprising floating point logic for performing floating point operations on data values in the at least one register file, wherein the floating point logic is configured to perform each of the floating point operations in response to execution of a single instance of a respective type of machine code instruction in an instruction set of the processor, whereby for a respective data value held in each operand register upon which one of the floating point operations is to be performed, the floating point logic is configured to process the fixed number of bits in the respective data value according to a floating point number format comprising a set of mantissa bits and a set of exponent bits;
wherein the processing logic is operable to select a selected variant of the floating point number format from among a plurality of different variants of the floating point number format, at least some of the variants having different size sets of mantissa bits and exponent bits relative to one another;
wherein a same one of the floating point operations, performed in response to execution of a same, single instance of a same one of said types of machine code instruction, operates on a first one of the data values from a first of the group of operand registers and on a second one of data values from a second of the group of operand registers other than the first operand register, and wherein the floating point logic is operable to apply first of the plurality of different variants of the floating point number format to the first data value in the first operand register and a second of the plurality of different variants of the floating point number format to the second data value in the second operand register as operated on by the same floating point operation;
wherein the processor further includes a first control register for holding a first programmable setting and a second control register for holding a second programmable setting, the first programmable setting in the first control register and the second programmable setting in the second control register being programmable by one or more earlier instructions executed on the processor,
wherein the first variant of the floating point number format applied to the first data value in the first operand register is programmable via the first programmable setting in the first control register and the second variant of the floating point number format applied to the second data value in the second programmable register is via the second programmable setting in the second control register, and
wherein the first and second programmable settings in the first and second control registers, respectively, are programmable independently of one another, thereby enabling the first and second variants to be selected independently of one another for the same floating point operation.