Patent ID: 11899609
Assignee: NVIDIA CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 8:
9. The system of claim 2, wherein the second device is further to:
compare the shifted first set of bits with a stored pattern;
determine the shifted first set of bits does not correspond to the stored pattern based on comparing the shifted first set of bits with the stored pattern;
shift the shifted first set of bits by an additional one or more UIs to receive a second shifted first set of bits responsive to determining the shifted first set of bits does not correspond to the stored pattern;
compare the second shifted first set of bits with the stored pattern; and
determine the second shifted first set of bits is associated with the stored pattern; and
transmit an indication the one or more data lanes are synchronized with respect to the frame boundary is responsive to determining the second shifted first set of bits is associated with the stored pattern.