Patent ID: 11961812
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 18:
19. A semiconductor package comprising:
a lower package comprising:
a lower redistribution layer including an insulating pattern having an opening and a via in the opening;
a first semiconductor chip on the lower redistribution layer, the first semiconductor chip including a chip pad, a passivation layer, and a pad bump, the pad bump extending through the passivation layer and being connected to the chip pad;
a connection member on the lower redistribution layer adjacent to the first semiconductor chip;
a first encapsulant on the lower redistribution layer and the first semiconductor chip; and
an upper redistribution layer on an upper surface of the first encapsulant and electrically connected to the connection member,
wherein the via physically contacts a portion of the outer side surface of the pad bump,
wherein the insulating pattern physically contacts a remaining portion of the outer side surface of the pad bump, and
wherein the via includes a central protrusion in physical contact with the lower surface of the pad bump; a first portion in physical contact with a lower surface of the passivation layer and the outer side surface of the pad bump; and a second portion spaced apart from the passivation layer.