Patent ID: 11881278
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. A redundant circuit assigning device, comprising:
a memory storing processor-executable instructions; and
a processor configured to execute the processor-executable instructions to perform operations of:
executing a first test item and acquiring first test data, wherein the first test data comprises position data of fail bits acquired during execution of the first test item;
determining a first redundant circuit assigning result according to the first test data, wherein the first redundant circuit assigning result comprises a number of assigned local redundant circuits and position data of the assigned local redundant circuits;
executing a second test item and acquiring second test data, wherein the second test data comprises position data of fail bits acquired during execution of the second test item; and
when the fail bits acquired during execution of the second test item comprise one or more fail bits beyond a repair range of the assigned local redundant circuits and assigned global redundant circuits, and the number of the assigned local redundant circuits is equal to a number of assignable local redundant circuits, acquiring target position data of fail bits in a target subdomain and a related subdomain based on the first test data and the second test data, and determining a second redundant circuit assigning result according to the target position data, wherein the target subdomain is a subdomain where the fail bits beyond the repair range are located.