Patent ID: 11942161
Assignee: NUVOTON TECHNOLOGY CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G  H

Claim 5:
6. The memory device as defined in claim 5, wherein either one of the first sub-memory and the second sub-memory further comprises:
a multiplexer, selecting either one of a first sub erase control signal and the first erase completion signal for use as an intermediate signal according to the first-security control signal, or selecting either one of a second sub erase control signal and the second erase completion signal for use as the intermediate signal according to the second security control signal; and
a flip-flop, outputting the intermediate signal for use as the first erase completion signal according to a clock signal, or outputting the intermediate signal for use as the second erase completion signal according to the clock signal.