Patent ID: 11863328
Assignee: INTEL CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A Multiple Access Management Service (MAMS) receiver (Rx), comprising:
processor circuitry coupled with interface circuitry, wherein the processor circuitry is arranged to:
receive one or more bursts of packets from a MAMS transmitter (Tx) via the interface circuitry;
detect a lost packet from at least one burst of the one or more of bursts of packets;
generate a packet loss report (PLR) message to include an acknowledgement (ACK) number field and a number of lost bursts field, wherein:
the ACK number field is to include a next in-order sequence number (SN) that the MAMS Rx is expecting, wherein the next in-order SN is based on the detected lost packet, and
the number of lost bursts field is to include, for each lost burst of a one or more bursts of packets, an SN of a first lost multi-access (MX) Service Data Unit (SDU) in a burst and a number of consecutive lost MX SDUs in the burst; and

transmit the PLR message to the MAMS Tx via the interface circuitry.