Patent ID: 11899597
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. A memory module comprising:
a circuit board having contacts along an edge of the circuit board;
a plurality of memory devices disposed on the circuit board, the plurality of memory devices being arranged in a plurality of module ranks, each module rank of the plurality of module ranks comprising a plurality of sub-ranks;
a registering clock driver (RCD) disposed on the circuit board;
a plurality of primary chip select (CS) traces respectively connecting the contacts to the RCD; and
a plurality of secondary CS traces coupled between the RCD and the plurality of memory devices, wherein the RCD is to:
receive a chip select (CS) signal group on the primary CS traces;
determine a subset of a plurality of CS signal outputs to assert on the plurality of secondary CS traces based at least in part on a number of memory modules inserted into a plurality of module slots and the CS signal group, wherein each of the plurality of CS signal outputs selects less than a half-rank of the plurality of memory devices; and
assert a CS signal on the subset of the plurality of CS signal outputs.