Patent ID: 11881274
Assignee: EMEMORY TECHNOLOGY INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. The program control circuit as claimed in claim 17, wherein the current mirror comprises:
a seventh transistor, wherein a drain terminal of the seventh transistor receives the reference program current, and a gate terminal of the seventh transistor receives the second bias voltage;
an eighth transistor, wherein a drain terminal of the eighth transistor is connected to a source terminal of the seventh transistor, a gate terminal of the eighth transistor is connected to the drain terminal of the seventh transistor, and a source terminal of the eighth transistor is connected to the ground terminal;
a ninth transistor, wherein a drain terminal of the ninth transistor is connected to the second terminal of the first switch, and a gate terminal of the ninth transistor receives the second bias voltage; and
a tenth transistor, wherein a drain terminal of the tenth transistor is connected to a source terminal of the ninth transistor, a gate terminal of the tenth transistor is connected to the gate terminal of the eighth transistor, and a source terminal of the tenth transistor is connected to the ground terminal.