Patent ID: 11862264
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A memory circuit comprising:
a first non-volatile memory cell configured to store a first value;
a second non-volatile memory cell configured to store a second value inverted from the first value;
a first sense amplifier coupled to the first non-volatile memory cell, and configured to generate a first output signal, the first sense amplifier comprises:
a first comparator comprising a first input terminal, a second input terminal and a first output terminal, the first input terminal of the first comparator being coupled to the first non-volatile memory cell by a first node, and being configured to receive a first voltage, the second input terminal of the first comparator being configured to receive a reference voltage, the first output terminal of the first comparator being configured to output a first intermediate signal;
a first detection circuit coupled to the first comparator, the first detection circuit configured to latch the first intermediate signal and disrupt a first current path between the first non-volatile memory cell and the first sense amplifier, the first detection circuit comprising:
a first flip-flop comprising a first input terminal of the first flip-flop coupled to the first output terminal of the first comparator and configured to receive the first intermediate signal, a second input terminal of the first flip-flop configured to receive a first data signal, a third input terminal of the first flip-flop configured to receive a first reset signal, a first output terminal of the first flip-flop configured to generate the first output signal, and a second output terminal of the first flip-flop configured to generate an inverted first output signal;

a second sense amplifier coupled to the second non-volatile memory cell, and configured to generate a second output signal; and
a latch coupled to the first sense amplifier and the second sense amplifier, and configured to latch the first output signal and the second output signal.