Patent ID: 11923351
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 17:
18. A stacked-chip package comprising:
a first chip; and
a second chip stacked on the first chip,
wherein the first chip includes
a first substrate having a first surface and a second surface opposite to the first surface,
a first cell array region on the first surface of the first substrate,
a first core circuit region adjacent to the first cell array region, the first core circuit region including a first core terminal,
a first peripheral circuit region adjacent to the first core circuit region, the first peripheral circuit region including a first peripheral circuit terminal, and
a first through via penetrating the first substrate and connected to the first peripheral circuit terminal, and

wherein the second chip includes
a second substrate having a third surface and a fourth surface opposite to the third surface,
a second cell array region on the third surface of the second substrate, the second cell array region being on the first cell array region,
a second core circuit region on the first core circuit region, the second core circuit region including a second core terminal, and
a second through via on the first peripheral circuit region, the second through via penetrating the second substrate, the second through via electrically connected to the first peripheral circuit terminal.