Patent ID: 11887648
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A semiconductor memory device, comprising:
a semiconductor substrate;
a common source semiconductor layer doped with impurities of a first conductivity type and arranged on the semiconductor substrate;
a plurality of insulating layers and a plurality of word line structures alternately stacked on the common source semiconductor layer;
a memory cell dielectric layer penetrating the plurality of insulating layers and the plurality of word line structures and covering an internal wall of a channel hole, the channel hole extending in a vertical direction, and a memory cell structure filling the channel hole; and
an etch stop layer arranged directly between the semiconductor substrate and the common source semiconductor layer, the etch stop layer including an oxynitride,
wherein the memory cell structure comprises a channel layer and a drain layer, wherein the channel layer disposed on the memory cell dielectric layer and fills at least a portion of the channel hole, and the drain layer covering an upper surface of the channel layer, doped with impurities of a second conductivity type, and filling some of an upper portion of the channel hole,
the memory cell dielectric layer comprises a gate insulating layer covering the internal wall of the channel hole, and a charge trap layer arranged between the gate insulating layer and the channel layer, and
the channel hole penetrates the plurality of insulating layers, the plurality of word line structures, and the etch stop layer.