Patent ID: 11942364
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of forming an interconnect, comprising:
forming an etch stop layer (ESL) over a lower conductive structure;
forming one or more dielectric layers over the ESL;
performing a first patterning process on the one or more dielectric layers to form interconnect opening;
performing a second patterning process on the one or more dielectric layers to increase a depth of the interconnect opening and expose an upper surface of the ESL;
selectively forming a protective layer on sidewalls of the one or more dielectric layers forming the interconnect opening;
performing a third patterning process to remove portions of the ESL that are uncovered by the one or more dielectric layers and the protective layer and to expose the lower conductive structure; and
forming a conductive material within the interconnect opening.