Patent ID: 11908532
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A memory device, comprising:
a memory cell array including a plurality of memory cells;
a peripheral circuit configured to perform a program operation including a plurality of program loops for storing data in selected memory cells among the plurality of memory cells; and
a control logic circuit configured to control the peripheral circuit to perform a program verify operation including a main verify operation and a pre-verify operation, the program verify operation verifying whether the selected memory cells form threshold voltage distributions corresponding to target program states corresponding to the data to be stored in the selected memory cells, respectively,
wherein the control logic circuit, when the pre-verify operation for any one of the target program states of the selected memory cells in any one of the plurality of program loops has passed, controls the peripheral circuit to skip the pre-verify operation for the any one of the target program states in next program loop of the any one of the plurality of program loops.