Patent ID: 11887656
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 2:
3. A memory, comprising:
a first cell array including a plurality of row lines, a plurality of first column lines, and a plurality of first memory cells, each of which is coupled to one row line among the row lines and one column line among the first column lines;
a second cell array arranged adjacent to the first cell array, sharing the row lines with the first cell array, and including a plurality of second column lines and a plurality of second memory cells, each of which is coupled to one row line among the row lines and one column line among the second column lines;
a third cell array arranged adjacent to the second cell array, sharing the row lines with the second cell array, and including a plurality of third column lines and a plurality of third memory cells, each of which is coupled to one row line among the row lines and one column line among the third column lines;
a first even bit line sense amplifier array positioned on one side of the first cell array and suitable for amplifying data of the first memory cells corresponding to a selected row line and even first column lines among the first column lines;
a first odd bit line sense amplifier array positioned on another side of the first cell array and suitable for amplifying data of the first memory cells corresponding to the selected row line and odd first column lines among the first column lines;
a second even bit line sense amplifier array positioned on one side of the second cell array and suitable for amplifying data of the second memory cells corresponding to the selected row line and even second column lines among the second column lines;
a second odd bit line sense amplifier array positioned on another side of the second cell array and suitable for amplifying data of the second memory cells corresponding to the selected row line and odd second column lines among the second column lines;
a third even bit line sense amplifier array positioned on one side of the third cell array and suitable for amplifying data of the third memory cells corresponding to the selected row line and even third column lines among the third column lines; and
a third odd bit line sense amplifier array positioned on another side of the third cell array and suitable for amplifying data of the third memory cells corresponding to the selected row line and odd third column lines among the third column lines,
wherein the first even bit line sense amplifier array, the first odd bit line sense amplifier array, the second even bit line sense amplifier array, the second odd bit line sense amplifier array, the third even bit line sense amplifier array, and the third odd bit line sense amplifier array are further suitable for performing respective data amplification operations simultaneously.