Patent ID: 11934825
Assignee: MONTANA SYSTEMS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. An integrated circuit (IC) comprising:
an instruction memory storing a plurality of groups of instructions;
an event manager circuit configured to (i) maintain a pending events table, each bit of the pending events table indicating absence or presence of a pending event at an input of an instruction in the plurality of groups of instructions, (ii) select a group of instructions by identifying an instruction having a pending input event in the pending events table, and (iii) update the pending events table by clearing bits in the pending events table that correspond to inputs of the selected group and setting bits in the pending events table that correspond to inputs of destination instructions; and
a set of processing units configured to execute the selected group of instructions to produce outputs to serve as inputs for the destination instructions.