Patent ID: 11934480
Assignee: MACRONIX INTERNATIONAL CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. A method for in-memory computation of a sum-of-products, comprising:
in a NAND block comprising B bit lines (BLs), S string select lines (SSLs), and one source line output,
storing coefficient data w(i.j) for a product term X(i)*W(i) in cells on a level L(k) of the NAND block in a column C(i) of NAND strings on string select lines SSL(j) coupled to bit line BL(i), for I going from 1 to B, for j going from 1 to S and for k equal to a selected word line level:
simultaneously applying inputs X(i) to bit lines BL(1) to BL(B), and string select voltages to string select lines SSL(1) to SSL(S), and a word line compute voltage to cells in the selected word line level;
combining currents through the columns C(1) to C(B) of NAND strings connected to bit lines BL(1) to BL(B) on the source line for the NAND block; and
sensing a current magnitude on the source line for the NAND block using a current sense amplifier connected directly to the source line for the NAND block to generate an output signal representing the sum-of-products; and
delivering the sum-of-products output signal from the current sense amplifier to an inter-tile bus system for routing among tiles comprising NAND blocks.