Patent ID: 11880933
Assignee: IMAGINATION TECHNOLOGIES LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. A system for processing primitive fragments in a rasterization phase of a graphics processing system wherein a rendering space is subdivided into a plurality of tiles, the system comprising:
a priority queue for storing primitive fragments;
a non-priority queue for storing primitive fragments;
logic circuitry configured to:
receive a plurality of primitive fragments, each primitive fragment corresponding to a pixel sample in a tile,
determine whether a depth buffer read is to be performed for full resolution depth testing of one or more of the primitive fragments, and
sort the primitive fragments into the priority queue and the non-priority queue based on the depth buffer read determinations; and

the hidden surface removal logic circuitry as set forth in claim 1;
wherein the primitive fragment received by the hidden surface removal logic circuitry is a primitive fragment selected by the hidden surface removal logic circuitry from one of the priority queue and the non-priority queue in a manner in which priority is given to the primitive fragments in the priority queue.