Patent ID: 11948632
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device comprising:
a first phase change memory cell connected between a first bit line and a first word line;
an X-decoder configured to provide a selection word line voltage to the first word line during a reset write operation for changing a state of the first phase change memory cell from a set state to a reset state;
a Y-decoder configured to provide a selection bit line voltage to the first bit line during the reset write operation; and
a voltage bias circuit configured to:
generate the selection word line voltage and the selection bit line voltage based on a first voltage bias during a first period of the reset write operation,
generate the selection word line voltage and the selection bit line voltage based on a second voltage bias greater than the first voltage bias during a second period of the reset write operation, and
generate the selection word line voltage and the selection bit line voltage based on a third voltage bias smaller than the first voltage bias and the second voltage bias during a third period of the reset write operation.