Patent ID: 11960921
Assignee: ALTERA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A method comprising:
providing one or more central processing units (CPUs);
receiving, from a respective central processing unit (CPU) of the one or more CPUs, a sequence of calls to a field programmable gate array corresponding to a first function and a second function;
receiving data from the respective CPU;
providing, via the field programmable gate array, a first hardware accelerator based on stored custom logic data, wherein the first hardware accelerator performs the first function on the data based on a set of conditions and provides corresponding first output data; and
providing, via the field programmable gate array, a second hardware accelerator based on the custom logic data, wherein the second hardware accelerator receives the first output data from the first hardware accelerator, performs the second function on the first output data without routing the first output data external to the field programmable gate array, and provides corresponding second output data.