Patent ID: 11928248
Assignee: MARVELL ASIA PTE LTD
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. The semiconductor device of claim 8, wherein the plurality of bitcells are arranged in a plurality of bitline columns and in a plurality of wordline rows, wherein each of the plurality of bitline columns includes a bitline, a bitline complement, first damage-inducing circuitry coupled to the bitline, second damage-inducing circuitry coupled to the bitline complement, sense amplifier circuitry, and respective bitcells, wherein each of the first damage-inducing circuitry and the second damage-inducing circuitry includes a first transistor and a second transistor arranged in series, a first switch operable to select from a plurality of voltages to apply to a gate terminal of the first transistor, and a second switch operable to select from the plurality of voltages to apply to a gate terminal of the second transistor, wherein a terminal of the second transistor is coupled to one of the bitline or the bitline complement, and wherein the plurality of voltages includes a damage-inducing voltage that is higher than an operating voltage of the second transistor.