Patent ID: 11901290
Assignee: ARM LIMITED
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A device comprising:
a bitcell having a physical layout of transistors arranged in a bitcell structure, wherein the transistors include first transistors and second transistors;
a first wordline coupled to the first transistors, wherein the first wordline is formed with a frontside metal rail; and
a second wordline coupled to one of the second transistors, wherein the second wordline is formed with a buried metal rail,
wherein the transistors include passgate transistors and a read transistor,
wherein the first wordline includes a write wordline coupled to the passgate transistors, and the write wordline is formed with the frontside metal rail, and
wherein the second wordline includes a read wordline coupled to the read transistor, and the read wordline is formed with the buried metal rail.