Patent ID: 11915787
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An integrated circuit (IC) device, comprising:
a substrate;
a memory array layer over the substrate, the memory array layer comprising a plurality of transistors;
first through fourth gate contacts arranged along a first axis, and coupled to underlying gates of the plurality of transistors;
first through fifth source/drain contacts in the memory array layer, extending along a second axis transverse to the first axis, and coupled to underlying source/drains of the plurality of transistors, wherein the gate contacts and the source/drain contacts are alternatingly arranged along the first axis;
a source line extending along the first axis, and coupled to the first and fifth source/drain contacts; and
first and second word lines extending along the first axis, the first word line coupled to the first and third gate contacts, the second word line coupled to the second and fourth gate contacts.