Patent ID: 11901462
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A method of fabricating an integrated circuit, the method comprising:
providing a semiconductor-on-insulator (SOI) substrate that includes a buried insulator layer;
forming an N-type well (NWELL) region and a sacrificial NWELL ring in a semiconductor layer of the SOI substrate, the sacrificial NWELL ring at a first side of the NWELL region and separated from the NWELL region by a first gap;
forming a P-type well (PWELL) region in a white space region of the semiconductor layer at the first side of the NWELL region;
forming a dielectric over the NWELL region; and
forming a polysilicon plate over the dielectric.