Patent ID: 11929366
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 7:
8. A semiconductor device, comprising:
a substrate including a first active region;
a first active pattern on the first active region;
a first source/drain pattern on an upper portion of the first active pattern;
at least one gate electrode across the first active pattern;
an interlayer dielectric layer covering the first source/drain pattern and the at least one gate electrode;
a first connection line in the interlayer dielectric layer, the first connection line having a first width; and
a second connection line in the interlayer dielectric layer, the second connection line having a second width greater than the first width, and the second connection line including:
a first metal layer on an inner sidewall of a trench of the interlayer dielectric layer,
a barrier layer on a bottom surface of the trench of the interlayer dielectric layer, and
a second metal layer directly on the first metal layer and the barrier layer,
wherein the first connection line and the first metal layer include a first metal, and the second metal layer includes a second metal different from the first metal, and
wherein the barrier layer is spaced apart from the inner sidewall of the trench.