Patent ID: 11887668
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. The memory device of claim 19, wherein the control logic is to perform further operations comprising:
applying, during a third time period of the program operation, the ramping wordline voltage to the set of wordlines associated with the memory array;
floating, at a second set of different times during the third time period, the respective pillar of the set of pillars associated with the plurality of memory cells, wherein each pillar voltage, when floated, is boosted in accordance with each increase of the ramping wordline voltage; and
causing, during a fourth time period, a second programming pulse to be applied to the set of memory cells, wherein the second programming pulse programs each programming level of the set of programming levels associated with the set of memory cells.