Patent ID: 11868870
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 22:
23. A neuromorphic processor, comprising:
a controller configured, for each time period of time periods, to sequentially determine:
one bit of n-bits to assign to a single axon circuit;
one bit of m-bits to assign to a single synaptic circuit configured to output a synaptic operation value as a function of the one bit of n-bits and the one bit of m-bits;
one of each bit value of a multi-bit neuromorphic operation result between the one bit of n-bits and the one bit of m-bits based on the output synaptic operation value for a single neuron circuit,

wherein the controller accumulates the multi-bit neuromorphic operation result for each time period of time periods of n-bits and of m-bits in a byte order, and n and m are each a natural number, and
wherein the controller is further configured to determine the first input and the second input that are to be assigned at each time period such that bits indicating the multi-bit neuromorphic operation result are sequentially obtained by the single neuron circuit from a value of a least significant bit (LSB) to a value of a most significant bit (MSB).