Patent ID: 11879939
Assignee: NXP B.V.
Field: Measurement (Instruments)
Classification: CPC G  H | IPC G  H

Claim 13:
14. The IC of claim 13, wherein the testing system further comprises:
a fifth clock gate that is configured to generate a seventh clock signal based on the first clock signal and a first pipeline enable signal, wherein the first pipeline enable signal is asserted based on the activation of the capture phase, and during the capture phase, the first pipeline enable signal is de-asserted based on the transition of the first clock enable signal, and wherein the seventh clock signal is de-asserted based on the de-assertion of the first pipeline enable signal, and the seventh clock signal is same as the first clock signal based on the assertion of the first pipeline enable signal; and
a latch that is coupled to the first comparator and the fifth clock gate, and configured to receive the first output signal and the seventh clock signal, and generate a second output signal, wherein the second output signal is same as the first output signal based on an assertion of the seventh clock signal, and wherein the second output signal is a latched version of the first output signal based on the de-assertion of the first pipeline enable signal.