Patent ID: 11968289
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 17:
18. The clock data recovery circuit of claim 17, wherein the phase detector further includes:
a fourth flip-flop, wherein an input terminal of the fourth flip-flop is configured to receive the input signal, and a control terminal of the fourth flip-flop is configured to receive an inverted clock signal;
a fifth flip-flop, wherein an input terminal of the fifth flip-flop is electrically connected to an output terminal of the fourth flip-flop, and a control terminal of the fifth flip-flop is configured to receive the clock signal; and
a second XOR gate, wherein a first input terminal of the second XOR gate is electrically connected to an output terminal of the fifth flip-flop, a second input terminal of the second XOR gate is electrically connected to the output terminal of the fourth flip-flop, and an output terminal of the second XOR gate is configured to output a second portion of the phase adjustment signal.