Patent ID: 11908838
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A three-dimensional device structure comprising:
a first die comprising a first semiconductor substrate;
second dies disposed on and electrically connected to the first die, each of the second dies comprising a respective second semiconductor substrate;
a dielectric encapsulation (DE) layer disposed on the first die and surrounding the second dies;
a redistribution layer structure disposed on the second dies and the DE layer;
through dielectric via (TDV) structures extending from an upper surface of the first die through the DE layer to electrically connect the first die and the redistribution layer structure; and
deep trench capacitors (DTC) disposed in respective trenches formed in the DE layer and electrically connected to the first die and the redistribution layer structure, wherein the DTCs are each disposed between one of the TDV structures and an adjacent one of the second dies, and each DTC comprises:
a first conductive layer electrically connected to the first die;
a second conductive layer electrically connected to the redistribution layer structure; and
a first dielectric layer disposed between the first conductive layer and the second conductive layer.