Patent ID: 11923416
Assignee: SK HYNIX INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor device, comprising:
a substrate;
a first source/drain region and a second source/drain region spaced apart from each other by a trench in the substrate; and
a gate structure in the trench,
wherein the gate structure includes:
a gate dielectric layer formed on a bottom and sidewalls of the trench;
a first gate electrode positioned in a bottom portion of the trench over the gate dielectric layer;
a second gate electrode positioned over the first gate electrode;
a capping layer disposed over the second gate electrode; and
a dipole inducing layer formed between the first gate electrode and the second gate electrode and between sidewalls of the second gate electrode and the gate dielectric layer,
wherein the dipole inducing layer extends between the capping layer and the gate dielectric layer, and
wherein a top surface of the dipole inducing layer is at a same level as a top surface of the first and second source/drain regions.