Patent ID: 11921626
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A memory access apparatus, comprising:
a memory device comprising an internal processor, a memory, and a register;
a memory controller; and
a memory management unit (MMU),
wherein the memory device is configured to receive offset information,
wherein the memory controller is configured to receive a processor-in-memory (PIM) instruction,
wherein the MMU is configured to receive a reference virtual address,
wherein the MMU is configured to convert the reference virtual address into a reference physical address of the memory, and transmit the reference physical address to the memory controller,
wherein the register is configured to store the received offset information, and
wherein the internal processor is configured to:
receive the instruction and the reference physical address from the memory controller;
determine an offset physical address of the memory based on the received offset information;
determine a target physical address of the memory based on the reference physical address and the offset physical address; and
perform the instruction by accessing the target physical address.