Patent ID: 11966738
Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A processor with a translation lookaside buffer flushing capability performed based on a designated key identification code, comprising:
a memory order buffer, configured to be a communication interface between the processor and a system memory;
a translation lookaside buffer, having a plurality of entries cached therein, to be searched by the processor to access the system memory; and
a decoder, in response to an instruction that is in an instruction set architecture and provided to flush the translation lookaside buffer based on the designated key identification code, decoding the instruction to provide at least one microinstruction;
wherein:
the at least one microinstruction includes a flushing microinstruction;
by executing the flushing microinstruction:
the designated key identification code is provided to a control logic circuit of the translation lookaside buffer through the memory order buffer; and
the control logic circuit flushes matched entries in the translation lookaside buffer, wherein the matched entries match the designated key identification code.