Patent ID: 11863190
Assignee: nan
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. The compound sequential circuit of claim 15, wherein the first differential sub-circuit of the latch comprises a first reduction transistor configured to reduce a first charge sharing between the first output of the latch and the third shared clock node, and wherein the second differential sub-circuit of the latch comprises a second reduction transistor configured to reduce a second charge sharing between the second output of the latch and the third shared clock node, and wherein each flip-flop of the plurality of flip-flops further comprises:
a first delay electrical element positioned between the first output of the latch and the first sequence detector;
a second delay electrical element positioned between the second output of the latch and the second sequence detector; and
wherein the latch further comprises:
a third keeper sub-circuit electrically coupled to the first sequence detector and the second sequence detector, wherein the third keeper sub-circuit is activated when the input signal is different than the first output of the latch and deactivated when the input signal is at same level as the first output of the latch, wherein the third keeper sub-circuit is electrically coupled to the second shared clock node, and wherein the third keeper sub-circuit is further electrically coupled to the first keeper sub-circuit and the second keeper sub-circuit.