Patent ID: 11973037
Assignee: POWERTECH TECHNOLOGY INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A package structure of claim 1, comprising:
a redistribution circuit layer;
a first die, disposed on the redistribution circuit layer and having a first active surface;
a second die, having a second active surface, the second die being disposed on the first die with the second active surface facing the first active surface;
a dielectric body, disposed on the redistribution circuit layer and covering the first die;
a conductive terminal, disposed on the redistribution circuit layer and opposite to the second die;
a first circuit layer, comprising a seed layer and a plating layer disposed on the seed layer, wherein a portion of the seed layer and a portion of the plating layer disposed thereon constitute a first circuit portion and, another portion of the seed layer and another portion of the plating layer disposed thereon constitute a second circuit portion, wherein:
the first circuit portion penetrates the dielectric body, and the first die is electrically connected to the conductive terminal through the first circuit portion and the redistribution circuit layer;
the second circuit portion is embedded in the dielectric body, and the second die is electrically connected to the first die through the second circuit portion; and
a portion of the first circuit portion is embedded in the redistribution circuit layer; and

a first patterned insulating layer, covering the first circuit layer and being embedded in the dielectric body, wherein the redistribution circuit layer comprising:
a second circuit layer, disposed on a dielectric bottom surface of dielectric body, the conductive terminal being electrically connected to the first circuit portion through the second circuit layer, wherein the seed layer of the first circuit layer directly contact the second circuit layer.