Patent ID: 11948629
Assignee: MOSAID TECHNOLOGIES INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A non-volatile memory device comprising:
a plurality of memory blocks, each memory block comprising a plurality of pages, each page comprising a plurality of non-volatile memory cells;
a clock input port configured to receive a clock input signal;
a clock output port configured to transmit a clock output signal;
a control input port configured to receive a chip select signal;
a plurality of common data interfaces configured to transfer command data, address data, write data, and read data when the chip select signal is at an active low logic state, wherein, when the non-volatile memory device is configured as a double data rate configuration, the command data, address data, and write data are transferred in synchronization with both rising and falling edges of the clock input signal, and the read data is transferred in synchronization with both rising and falling edges of the clock output signal;
a control circuitry configured to perform a program operation to program the write data on a selected page according to the command data and address data, and to perform a read operation to retrieve the read data from a different page other than the selected page before completion of the program operation; and
a status register configured to provide a status of the program operation.