Patent ID: 11925024
Assignee: KIOXIA CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. The semiconductor memory device according to claim 6, wherein
the substrate has a seventh region, and the seventh region is arranged with the sixth region in the first direction,
each of the plurality of third word line layers includes a seventh word line part provided over the seventh region,
each of the plurality of third interlayer insulating layers includes a ninth interlayer insulating part provided over the seventh region and a tenth interlayer insulating part provided over the seventh region,
all ninth interlayer insulating parts of the plurality of third interlayer insulating layers are laminated in the third direction alternately with all seventh word line parts of the plurality of third word line layers,
the semiconductor memory device comprises:
a plurality of third insulating layers provided over the seventh region and laminated in the third direction alternately with all tenth interlayer insulating parts of the plurality of third interlayer insulating layers that are arranged with all seventh word line parts of the plurality of third word line layers in the second direction; and
a fourth contact that is provided over the seventh region and extends in the third direction, the fourth contact having an outer peripheral surface abutting at least some of the plurality of third insulating layers,

each of the plurality of third insulating layers has a side surface in the first direction abutting each of the plurality of third word line layers.