Patent ID: 11895827
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 4:
5. A nonvolatile memory device, comprising:
a substrate having a main chip area thereon, said main chip area including a first memory cell layer and second memory cell layer stacked on the first memory cell layer, said first memory cell layer including a first vertical channel layer, a first interlayer insulating layer, and a first gate electrode layer, and said second memory cell layer including: (i) a second vertical channel layer vertically aligned with the first vertical channel layer, (ii) a second interlayer insulating layer, and (iii) a second gate electrode layer;
an outer chip area on the substrate, which at least partially surrounds the main chip area in a portion of the substrate devoid of active devices, said outer chip layer including a first photolithographic alignment key therein that comprises an alignment vertical channel layer with a top surface that is recessed relative to the top surface of the first vertical channel layer; and
a mold structure on the first photolithographic alignment key, said mold structure having a contoured upper surface thereon, which sufficiently replicates upper surface contours of the first photolithographic alignment key that the contoured upper surface operates as a second photolithographic alignment key during formation of the second vertical channel layer;
wherein the first photolithographic alignment key further comprises an electrically insulating recessed portion, which abuts the alignment vertical channel layer; and
wherein the alignment vertical channel layer protrudes from the electrically insulating recessed portion such that the top surface of the alignment vertical channel layer is spaced farther from an underlying surface of the substrate relative to a top surface of the electrically insulating recessed portion.