Patent ID: 11899941
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. A storage device comprising:
a non-volatile memory including a plurality of memory segments; and
a storage controller connected to the non-volatile memory through a plurality of channels, each of the plurality of channels connected to a respective one of the plurality of memory segments such that each of the plurality of channels has a respective associated memory segment,
wherein the storage controller configured to receive speed information from a host and generate parity according to the speed information;
a host interface configured to receive first data to be written to the non-volatile memory from the host and transfer second data read from the non-volatile memory to the host; and
a memory interface configured to transfer third data to be written to the non-volatile memory or receive fourth data read from the non-volatile memory, wherein
the host interface and the memory interface are configured such that as a speed change included in the speed information increases, an amount of data transferred and received by the memory interface increases more than an amount of data transferred and received by the host interface.