Patent ID: 11881851
Assignee: HRL LABORATORIES, LLC
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. The signal processing circuit of claim 1, wherein:
the first series switch comprises a first field effect transistor connected in parallel with a second field effect transistor;
the second series switch comprises a first field effect transistor connected in parallel with a second field effect transistor; and
the first output of the clock circuit is connected:
through a first inverter and a second inverter, connected in cascade, to:
the gate of the first field effect transistor of the first series switch, and
the gate of the first field effect transistor of the second series switch; and

through a third inverter to:
the gate of the second field effect transistor of the first series switch, and
the gate of the second field effect transistor of the second series switch.