Patent ID: 11910618
Assignee: KEPLER COMPUTING INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 18:
19. A system comprising:
a processor circuitry to execute one or more instructions;
a memory circuitry to store the one or more instructions; and
a communication interface to allow the processor circuitry to communicate with another device, wherein the memory circuitry includes a plurality of bit-cells organized in a memory array, and wherein an individual bit-cell of the plurality of bit-cells includes:
a first transistor having a first gate terminal coupled to a word-line, a first source terminal coupled to a bit-line, and a first drain terminal coupled to a storage node;
a second transistor coupled to the first transistor, wherein the second transistor includes a second gate terminal coupled to the storage node, a second source terminal coupled to a sense line, and a second drain terminal coupled to a bias; and
a plurality of capacitors having a first terminal coupled to the storage node, wherein a second terminal of an individual capacitor of the plurality of capacitors is coupled to an individual plate-line, and wherein the plurality of capacitors are non-planar capacitors that are arranged in a stacked and folded configuration.