Patent ID: 11962295
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 9:
10. A multiplexer, comprising:
a charging circuit including a capacitor charged in response to a first clock signal;
a plurality of sampling switches configured to receive a plurality of input signals; and
a plurality of boosting circuits connected between the plurality of sampling switches and the charging circuit, and configured to share the charging circuit and operate in response to a second clock signal having a phase opposite to the first clock signal, wherein, when a selected sampling switch and non-selected sampling switches are determined among the sampling switches, a selected boosting circuit among the plurality of boosting circuits, connected to the selected sampling switch, is electrically connected to the charging circuit, and non-selected boosting circuits among the plurality of boosting circuits, connected to the non-selected sampling switches are electrically disconnected from the charging circuit,
wherein each of the plurality of boosting circuits is connected to or is disconnected from the charging circuit in response to an output signal of a NAND gate receiving the second clock signal and one of a plurality of selection signals.