Patent ID: 11935790
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 26:
27. A method of manufacturing a field effect transistor, the method comprising:
alternately stacking sacrificial layers and gate electrodes on a substrate to provide a stack structure;
patterning the stack structure using a mask to provide a patterned stack structure;
forming gate support electrodes on both sides of the patterned stack structure, the gate support electrodes being connected to the gate electrodes;
removing the sacrificial layers, the removing the sacrificial layers leaving the gate electrodes suspended between the gate support electrodes and separated from each other in a direction perpendicular to the substrate;
depositing a gate insulating layer on the gate electrode;
forming channels by depositing a channel material on the gate insulating layers; and
depositing a source electrode and a drain electrode, the source electrode and the drain electrode being connected to the channels.