Patent ID: 11909403
Assignee: INTEL CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. A system comprising:
a crystal oscillator to generate a first clock having a first frequency;
a memory;
a processor coupled to the memory; and
a wireless interface to allow the processor to communicate with another device, wherein the processor includes:
a duty cycle correction (DCC) circuit to receive the first clock to generate an output which is corrected for duty cycle error; and
a multiplier circuitry coupled to the output of the DCC circuit, wherein the multiplier circuitry is to generate a second clock having a second frequency higher than the first frequency, wherein the multiplier circuitry includes:
a delay line to delay the output of the DCC circuit, and to generate a phase shifted signal; and
a comparator to compare the output of the DCC circuit and the phase shifted signal, wherein the delay line is a first delay line, the phase shifted signal is a first phase shifted signal, and the multiplier circuitry comprises a second delay line to delay the first phase shifted signal and generate a second phase shifted signal, an inverter to invert the second phase shifted signal, and a phase detector to receive an output of the inverter, and the output of the DCC circuit.