Patent ID: 11961548
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device comprising:
a memory cell array including a plurality of memory cell rows;
a control logic circuit configured to monitor access addresses for the memory cell array to detect a first hammer address and a second hammer address; and
a refresh control circuit configured to refresh a memory cell row physically adjacent to a memory cell row corresponding to the first hammer address,
wherein the first hammer address includes a row hammer address of memory cell rows having the number of accesses equal to or more than a predetermined number of times or having a relatively higher number of accesses as compared with other access addresses during a first row hammer monitoring time frame,
wherein the second hammer address includes a malicious row hammer address of memory cell rows accessed at random sampling time points during a second row hammer monitoring time frame, and being the same as the row hammer address,
wherein the control logic circuit is configured to count the number of malicious row hammer addresses, and
wherein the refresh control circuit is configured to refresh a memory cell row physically adjacent to a memory cell row corresponding to the malicious row hammer address when the counted number of malicious row hammer addresses exceeds a threshold value.