Patent ID: 11881176
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 16:
17. The display substrate according to claim 1, further comprising: a plurality of data signal lines and a plurality of reset voltage lines arranged on the base substrate,
wherein the second transistor comprises a first gate electrode and a second gate electrode,
the plurality of data signal lines comprise a plurality of data signal line groups, the plurality of data signal line groups comprise a first data signal line group, the first data signal line group comprises a first data signal line and a second data signal line that are adjacent and are respectively connected with a pixel circuit of a first sub-pixel and a pixel circuit of a second sub-pixel, and the first sub-pixel and the second sub-pixel are two adjacent sub-pixels of the plurality of sub-pixels;
an orthographic projection of a reset voltage line of the plurality of reset voltage lines on the base substrate is located between an orthographic projection of the first data signal line on the base substrate and an orthographic projection of the second data signal line on the base substrate;
the first data signal line, the reset voltage line, and the second data signal line extend in the first direction and are arranged in the second direction,
an orthographic projection of a first gate electrode of a first transistor in the pixel circuit of the first sub-pixel, an orthographic projection of a second gate electrode of the first transistor in the pixel circuit of the first sub-pixel, an orthographic projection of a first gate electrode of a second transistor in the pixel circuit of the first sub-pixel, an orthographic projection of a second gate electrode of the second transistor in the pixel circuit of the first sub-pixel on the base substrate all are located between the orthographic projection of the first data signal line on the base substrate and the orthographic projection of the reset voltage line on the base substrate; and
an orthographic projection of a first gate electrode of a first transistor in the pixel circuit of the second sub-pixel, an orthographic projection of a second gate electrode of the first transistor in the pixel circuit of the second sub-pixel, an orthographic projection of a first gate electrode of a second transistor in the pixel circuit of the second sub-pixel, an orthographic projection of a second gate electrode of the second transistor in the pixel circuit of the second sub-pixel on the base substrate all are located between the orthographic projection of the second data signal line on the base substrate and the orthographic projection of the reset voltage line on the base substrate.