Patent ID: 11871626
Assignee: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 19:
20. A display panel, comprising:
a base substrate comprising a display area and a peripheral area surrounding the display area;
a plurality of sub-pixels located at the display area, wherein each of the plurality of sub-pixels comprises an anode located on one side of the base substrate and a light-emitting function layer located on one side of the anode away from the base substrate;
a driving circuit located at the peripheral area, and configured to output a gate driving signal and a light-emitting control scanning signal to the plurality of sub-pixels;
a power line located on one side of the driving circuit away from the display area;
a connection layer electrically connected to the power line and located on one side of the driving circuit and the power line away from the base substrate, wherein an orthographic projection of the connection layer on the base substrate partially overlaps with an orthographic projection of the driving circuit on the base substrate, and a minimum distance between an edge of the orthographic projection of the connection layer on the base substrate close to the display area and an edge of an orthographic projection of the anode, which is closest to an edge of the display area of a plurality of anodes of the plurality of sub-pixels, the base substrate ranges from 150 microns to 250 microns; and
a cathode electrically connected to the connection layer located at the display area and the peripheral area, and located on one side of the light-emitting function laver and the connection layer away from the base substrate, wherein:
the driving circuit comprises: a gate driving circuit located between the display area and the power line, and configured to output the gate drive signal to the plurality of sub-pixels; and a light-emitting control driving circuit located between the power line and the gate driving circuit, and configured to output the light-emitting control scanning signal to the plurality of sub-pixels, wherein the edge of the orthographic projection of the connection layer on the base substrate close to the display area is at least partially located within an orthographic projection of the gate driving circuit on the base substrate;
the display panel further comprises a first planarization layer located at the display area and the peripheral area, and comprising a first planarization portion located between the driving circuit and the connection layer, wherein the connection laver comprises a plurality of first openings spaced apart from each other, wherein orthographic projections of the plurality of first openings on the base substrate at last partially overlap with an orthographic projection of the first planarization portion on the base substrate;
the first planarization layer comprises a second opening located at the peripheral area and extending along a periphery of the display area, and the display panel further comprises:
a first conductive portion located in the second opening, located between the power line and the connection layer, and in contact with the power line and the connection layer, and
a pixel defining layer located on one side of the connection layer away from the base substrate, and comprising a first pixel defining portion located at the peripheral area, wherein the first pixel defining portion comprises a plurality of filling portions spaced apart from each other, and located in the plurality of first openings in a one-to-one correspondence, and the cathode is in contact with a portion of the connection laver not covered by the pixel defining layer; and
the gate driving circuit comprises a first clock signal line and a second clock signal line located on one side of the first clock signal line away from the display area, the first planarization portion comprises a third opening located above the first clock signal line and a fourth opening located above the second clock signal line, and the display panel further comprises:
a second conductive portion located in the third opening and in contact with the first clock signal line,
a third conductive portion located in the fourth opening and in contact with the second clock signal line, and
a second planarization layer located on one side of the first planarization layer away from the base substrate, and comprising:
a second planarization portion located between the first planarization portion and the connection laver, and covering the second conductive portion and the third conductive portion, and
a third planarization portion spaced apart from the second planarization portion, located on one side of the light-emitting control driving circuit away from the display area, and comprising a fifth opening located above the first conductive portion, wherein the connection layer is partially located in the fifth opening, and a portion of the connection laver located between the third planarization portion and the second planarization portion is at least partially in contact with the first planarization layer.