Patent ID: 11948635
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. A method, comprising:
sending, via a closed loop bias generator comprising third and fourth cascode connected NMOS transistors, an output comprising a column select signal to a memory array including a plurality of memory cells arranged in rows and columns;
receiving the output of the closed loop bias generator at a current limiter coupled to a plurality of the columns of the memory array and comprising a cascode of first and second connected NMOS transistors; and
receiving a feedback signal at an operational amplifier and generating a column select signal; and
outputting the column select signal to a column MUX, wherein the output of the operational amplifier is connected to a gate of the first NMOS transistor, and a source of the third NMOS transistor is connected to a gate of the second NMOS transistor.