Patent ID: 11861189
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory system, comprising:
a memory device including a plurality of memory blocks, each memory block including memory cells capable of storing multi-bit data; and
a controller configured to allocate the plurality of memory blocks for plural zoned namespaces input from an external device and access a memory block allocated for one of the plural zoned namespaces in response to a data input/output request input from the external device,
wherein, in response to a first request input from the external device, the controller adjusts a number of bits of data stored in a memory cell included in a memory block which is allocated for at least one zoned namespace among the plural zoned namespaces,
wherein the controller is configured to, when memory blocks allocated for the at least one zoned namespace include memory cells storing n-bit data before the first request is input, adjust the memory blocks to store 1-bit data in each of the memory cells included therein and deactivate (n−1) zoned namespaces among the plural zoned namespaces to maintain a storage capacity of the at least one zoned namespace, wherein the n is an integer greater than 1.