Patent ID: 11956960
Assignee: SK HYNIX INC.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor device, comprising:
a gate stack with conductive layers and insulating layers that are stacked alternately with each other;
channel layers passing through the gate stack, the channel layers protruding past a top surface of the gate stack, wherein a width of each of the channel layers passing through the gate stack is greater than a width of each of the channel layers protruding past the top surface of the gate stack;
a gate liner having a first portion and second portions, wherein the first portion covers the top surface of the gate stack except portions surrounded by the channel layers, and the second portions surround sidewalls of protruding portions of the channel layers; and
an isolation insulating layer formed on the gate stack and passing through the first portion of the gate liner,
wherein at least one second portion among the second portions protrudes farther into the isolation insulating layer than the first portion, and
wherein an inner diameter of each of the second portions surrounding the sidewalls of the protruding portions of the channel layers is narrower than an inner diameter of each of open areas of the first portion surrounding the channel layers.