Patent ID: 11935959
Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A semiconductor device comprising:
a glass substrate;
a gate electrode over the glass substrate;
a gate insulating film over the gate electrode, the gate insulating film comprising a first insulating layer and a second insulating layer;
an oxide semiconductor film over the second insulating layer;
a source electrode and a drain electrode over and electrically connected to the oxide semiconductor film;
an oxide insulating film over the oxide semiconductor film, the source electrode, and the drain electrode;
a nitride insulating film over the oxide insulating film; and
a pixel electrode over the nitride insulating film,
wherein the oxide semiconductor film comprises a first oxide semiconductor layer, comprising a nanocrystal having a size greater than or equal to 1 nm and less than 10 nm, and a second oxide semiconductor layer, comprising a plurality of crystals whose c-axes are aligned in a direction substantially perpendicular to a formation surface of the second oxide semiconductor layer,
wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises indium, gallium, and zinc,
wherein one of the source electrode and the drain electrode is in contact with a side surface of the oxide semiconductor film,
wherein the pixel electrode is electrically connected to the one of the source electrode and the drain electrode via an opening provided in the oxide insulating film and the nitride insulating film,
wherein the oxide insulating film is in contact with the oxide semiconductor film,
wherein the oxide insulating film comprises a void region, and
wherein the nitride insulating film is in contact with the oxide insulating film and covers the void region of the oxide insulating film.