Patent ID: 11928443
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. A circuit system comprising:
a memory block; and
first and second processing circuits, wherein first and second transpose engines operating on the first and the second processing circuits store a matrix in the memory block by the first transpose engine writing a first row or column of the matrix to a first region of storage in the memory block concurrently with the second transpose engine writing a second row or column of the matrix to a second region of storage in the memory block, and
wherein the first and the second transpose engines transpose the matrix to generate a transposed matrix by the first transpose engine reading a first row or column of the transposed matrix from a third region of storage in the memory block concurrently with the second transpose engine reading a second row or column of the transposed matrix from a fourth region of storage in the memory block.