Patent ID: 11968819
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 6:
7. The IC structure of claim 1, wherein the memory cell further includes:
a first gate stack disposed on the first active region to provide a first pass-gate device;
a second gate stack disposed on the second active region, the third active region and the fourth active region to provide a first isolation device, a first pull-up device and a first pull-down device, respectively,
a third gate stack disposed on the first active region, the second active region, and the third active region to provide a second pull-down device, a second pull-up device and a second isolation device, respectively, and
a fourth gate stack disposed on the fourth active region to provide a second pass-gate device.