Patent ID: 11862238
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. An apparatus comprising:
a first deck located over the substrate, the first deck including first memory cell strings;
a second deck located over the first deck, the second deck including second memory cell strings;
first data lines located between the first and second decks and coupled to the first memory cell strings;
second data lines located over the second deck and coupled to the second memory cell strings, the first and second data lines extending in a direction from a first side of the first deck to a second side of the first deck;
memory cell blocks, each of the memory cell blocks including a first portion and a second portion, the first portion including a respective portion of the first memory cell strings, the second portion including a respective portion of the second memory cell strings;
first conductive paths located on the first side of the first deck and coupled to the first data lines, the first conductive paths extending in a direction from the first deck to the second deck;
first buffer circuitry coupled to the first conductive paths;
second conductive paths located on the second side of the first deck and coupled to the second data lines, the second conductive paths extending in the direction from the first deck to the second deck;
second buffer circuitry coupled to the second conductive paths;
driver circuits adjacent the first and second buffer circuitries, each of the driver circuits coupled to a respective memory cell block of the memory cell blocks;
first access lines located on the first deck, wherein the respective portion of the first memory cell strings of each of the blocks is coupled to a respective portion of the first access lines; and
second access lines located on the second deck, wherein the respective portion of the second memory cell strings of each of the blocks is coupled to a respective portion of the second access lines, wherein the memory cell blocks include a first memory block and a second memory cell block, and wherein:
the respective portion of the first access lines coupled to the respective portion of the first memory cell strings of the first memory block is separated from the respective portion of the first access lines coupled to the respective portion of the first memory cell strings of the second memory cell block; and
the respective portion of the second access lines coupled to the respective portion of the second memory cell strings of the first memory block is separated from the respective portion of the second access lines coupled to the respective portion of the second memory cell strings of the second memory cell block.