Patent ID: 11908523
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device comprising:
a memory array comprising a set of memory cells configured as a multi-level cell (MLC) memory; and
control logic, operatively coupled with the memory array, to perform operations comprising:
initiating an express programming operation to program the set of memory cells to a target programming level of a set of programming levels;
storing, in a cache register, a set of data associated with the express programming operation;
at a first time during execution of the express programming operation, executing a prediction operation to determine a prediction result corresponding to a programming status of the set of memory cells;
comparing the prediction result to a threshold level to determine whether a condition is satisfied; and
causing a release of the set of data associated with the express programming operation from the cache register in response to the condition being satisfied.