Patent ID: 11894091
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A computer system for processing synchronized memory repairs comprising:
a memory array comprising:
a plurality of memory rows, the plurality of memory rows comprising a plurality of functioning memory rows, at least one faulty memory row, and a plurality of memory repair rows; and
a plurality of wordlines, wherein each wordline of the plurality of wordlines:
is communicatively and operably coupled to one memory row of the plurality of memory rows; and

an integrated memory decoder communicatively and operably coupled to the memory array, the integrated memory decoder comprising logic circuitry configured to execute operation of the plurality of functioning memory rows, the integrated memory decoder further configured to:
execute memory row repair operations directed toward the faulty memory row, comprising:
identifying a memory repair row from the plurality of memory repair rows to operationally replace the faulty memory row;
creating a multiple hot state within the integrated memory decoder;
activating a wordline of the identified memory repair row through the multiple hot state; and
executing one or more memory operations on the identified memory repair row through the integrated memory decoder.