Patent ID: 11928176
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 4:
5. The system of claim 4, where each PE includes:
a data selection circuit configured to receive the bitmap and generate a data selection signal based on the bitmap;
a data selector, coupled to the data selection circuit, configured to:
receive a row of the second matrix, the row having a plurality of elements, and
selectively output one row element of the plurality of elements of the row based on the data selection signal;

the single multiplier circuit, coupled to the data selector, configured to:
receive a column element of a column of the compressed first matrix,
receive the row element selectively output by the data selector,
multiply the column element and the row element to generate an intermediate product, and
output the intermediate product; and

an accumulator circuit, coupled to the single multiplier circuit, configured to:
receive the intermediate product from the single multiplier circuit,
accumulate the intermediate product into an element of the output matrix, and
output the element of the output matrix after a last column element has been received by the single multiplier circuit.