Patent ID: 11894066
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 12:
13. The semiconductor memory device of claim 10, wherein each of the plurality of page buffers further comprises a cache latch connected to the sense out node, and the control logic performs a sensing operation on each of the plurality of memory cells using a first read voltage, stores first bit data generated as a result of the sensing operation in a corresponding sensing latch, generates first target bit data by applying masking of the target state to the first bit data, stores the first target bit data in corresponding cache latches, respectively, performs a sensing operation on each of the plurality of memory cells using a second read voltage different from the first read voltage, stores second bit data generated as a result of the sensing operation in a corresponding sensing latch, generates second target bit data by applying masking of the target state to the second bit data, and controls each of the plurality of page buffers to respectively store a result of an exclusive OR (XOR) operation on the first target bit data and the second target bit data in the cache latch.