Patent ID: 11862286
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 7:
8. The data transmission circuit of claim 7, wherein the write drive circuit comprises:
a first switch circuit, configured to be electrically connected to the complementary local data line and the global data line according to the inverted write enable signal;
a second switch circuit, having a control terminal configured to be electrically connected to the global data line, a first terminal configured to be electrically connected to the local data line, and a second terminal configured to be electrically connected to a first node;
a third switch circuit, configured to be electrically connected to the first node and a ground according to the inverted write enable signal;
a fourth switch circuit, configured to be electrically connected to the local data line and the global data line according to the write enable signal;
a fifth switch circuit, having a control terminal configured to be electrically connected to the global data line, a first terminal configured to be electrically connected to the complementary local data line, and a second terminal configured to be electrically connected to a second node; and
a sixth switch circuit, configured to be electrically connected to the second node and the ground according to the write enable signal.