Patent ID: 11961813
Assignee: QORVO US, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. The method of claim 1 wherein providing the precursor wafer comprises:
providing a starting wafer that includes a common strained silicon epitaxial layer, a common interfacial layer over the common strained silicon epitaxial layer, and the silicon handle substrate over the common interfacial layer, wherein:
the common interfacial layer is formed of SiGe with a uniform concentration of germanium greater than 15%, wherein the common interfacial layer is not strained by the silicon handle substrate, and has a lattice constant greater than 5.461 at a temperature of 300K; and
a lattice constant of silicon in the common strained silicon epitaxial layer is strained by the common interfacial layer and is greater than 5.461 at a temperature of 300K; and

performing a complementary metal-oxide-semiconductor (CMOS) process to provide the precursor wafer, wherein:
the isolation sections extend through the common strained silicon epitaxial layer and the common interfacial layer, and extend into the silicon handle substrate, such that the common interfacial layer is separated into the plurality of individual interfacial layers, and the common strained silicon epitaxial layer is separated into a plurality of individual strained silicon epitaxial layers;
each active layer of the plurality of device regions is formed from a corresponding strained silicon epitaxial layer; and
each of the plurality of individual interfacial layers resides over a top surface of a corresponding active layer, and the silicon handle substrate resides over the plurality of individual interfacial layers.