Patent ID: 11875842
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 10:
11. A non-transitory computer readable storage medium configured to store instructions that, when executed by a processor includes a controller of a memory system, cause the memory system to carry out steps to:
access, by a first row decoder coupled to a first sub-block of a first memory block, the first sub-block of the first memory block at a first time; and
access, by a second row decoder separate from the first row decoder and coupled to a second sub-block of the first memory block, the second sub-block of the first memory block at a second different from the first time,
wherein the second time defines a time delay that is chronologically after the first time, and
wherein the time delay is determined based upon a word line voltage ramp rate control.