Patent ID: 11903193
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 19:
20. The method of claim 13, further comprising:
forming a first sidewall spacer on the first control gate dielectric layer and the first control gate electrode; and
forming a source region and a drain region each in the substrate using the first sidewall spacer as a mask, wherein a channel region continuously extends between the source region and the drain region underneath the first floating gate trench, a first p-n junction between the channel region and the source region has a first top edge that is aligned to, and adjoined to, a bottom edge a first outer sidewall of the first sidewall spacer, and a second p-n junction between the channel region and the drain region has a second top edge that is aligned to, and adjoined to, a bottom edge a second outer sidewall of the first sidewall spacer.