Patent ID: 11908891
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A method of forming an integrated chip, comprising:
forming a plurality of isolation structures within a substrate, the plurality of isolation structures being separated from one another along a first direction;
etching an upper surface of the substrate to form a gate base recess having a first depth within the substrate;
etching the plurality of isolation structures to form a plurality of gate extension trenches having a second depth less than the first depth, wherein the plurality of gate extension trenches extend outward from the gate base recess in a second direction that is perpendicular to the first direction;
forming a gate electrode within the gate base recess and the plurality of gate extension trenches, wherein the gate electrode is formed to have a part that is below a top of the plurality of isolation structures and that continuously extends from within the gate base recess to within the plurality of gate extension trenches; and
forming a source region and a drain region on opposing sides of the gate electrode.