Patent ID: 11948798
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A method for manufacturing an integrated circuit, the method comprising:
forming a first patterned mask over a substrate, the first patterned mask having a first pattern feature, a second pattern feature, and a third pattern feature;
forming a first masking layer over the first patterned mask;
forming a second patterned mask over the first masking layer, the second patterned mask having an opening exposing a portion of the first masking layer between the first pattern feature and the second pattern feature of the first patterned mask;
forming a first material layer along sidewalls of the opening;
forming a second material layer over the first material layer;
removing the second patterned mask;
removing the first masking layer from an upper surface of the first pattern feature and the second pattern feature, wherein remaining portions of the first masking layer remains along sidewalls of the first pattern feature and the second pattern feature;
removing the first pattern feature and the second pattern feature; and
etching the substrate using at least the second material layer, remaining portions of the first masking layer, and the third pattern feature as part of a mask.