Patent ID: 11935599
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A memory circuit, comprising:
a memory array comprising a plurality of programmable memory cells;
a plurality of wordlines (WLs);
a plurality of bitlines (BLs);
a page buffer configured to receive and store page data;
one or more data latches; and
one or more charge pumps,
wherein the one or more charge pumps are charged to one or more target voltage levels responsive to receipt of a first program command associated with first page data, and
wherein the one or more charge pumps are configured to maintained a charged state during a transition from a first program operation during which the first page data is programmed into the memory array to a second program operation during which second page data associated with a second program command is programmed into the memory array, the second program operation occurring subsequent to the first program operation.