Patent ID: 11930631
Assignee: FUJIAN JINHUA INTEGRATED CIRCUIT CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor memory device, comprising:
a substrate;
a plurality of bit lines, separately disposed on the substrate;
a plurality of plugs, disposed on the substrate, the plugs and the bit lines are alternately arranged with each other;
a spacer structure, disposed on the substrate between each of the bit lines and each of the plugs, wherein the spacer structure comprises a first air gap layer, a first spacer and a second air gap layer, and the first air gap layer, the first spacer and the second air gap layer are sequentially stacked between sidewalls of the bit lines and the plugs; and
an insulating layer, disposed on the bit lines, the plugs and the spacer structure, a portion of the insulating layer disposed on the bit lines surrounds a cavity.