Patent ID: 11881244
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A semiconductor memory system comprising:
a semiconductor memory apparatus configured to detect row hammering on a plurality of word lines to generate a row hammering detection signal and a row hammering address according to an address signal, generate a first refresh target address and a second refresh target address by performing operations on the row hammering address, performs a first addition operation on the first refresh target address and the second refresh target address and a second addition operation on the row hammering address and the row hammering address and configured to generate an address matching information by comparing results of the first addition operation with the second addition operation; and
a system control apparatus configured to provide the address signal to the semiconductor memory apparatus based on the row hammering detection signal and the address matching information.