Patent ID: 11925021
Assignee: SK HYNIX INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A method of manufacturing a semiconductor device, the method comprising:
forming first stack structures separated from each other by a first slit and including first interlayer insulating layers and first conductive patterns which enclose first channel structures, respectively, and alternately stacked on each other;
forming a first vertical conductive pattern having a sidewall covered by a first slit insulating layer in the first slit;
forming a second stack structure including second interlayer insulating layers and sacrificial layers which enclose second channel structures coupled to the first channel structures and which are alternately stacked on each other, and exposing an end portion of each of the first stack structures, on the first stack structures;
forming a second slit by etching a first region of the second stack structure which overlaps the first slit; and
forming a second vertical conductive pattern having a sidewall covered by a second slit insulating layer and extending to be coupled to the first vertical conductive pattern, in the second slit.