Patent ID: 11915764
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. The memory of claim 9, wherein the array operation is a first array operation, wherein the indication of temperature is a first indication of temperature, and wherein the controller is further configured to cause the memory to:
initiate a second array operation different than the first array operation on the array of memory cells;
indicate the unavailability to initiate a next array operation on the array of memory cells;
determine a duration of a delay interval for the second array operation in response to a second indication of temperature;
initiate the delay interval for the second array operation in response to a completion of an array access portion of the second array operation; and
indicate the availability to initiate a next array operation on the array of memory cells in response to a completion of the delay interval for the second array operation.