Patent ID: 11868269
Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. A processor-based device, comprising:
a processing element (PE), comprising:
an access count table, wherein the access count table is a packed table comprising a plurality of access count values that each correspond to a memory block of a plurality of memory blocks; and
an access-track table, wherein the access-track table is a packed table comprising a plurality of access-track indicators each corresponding to a memory block of the plurality of memory blocks;

the PE is configured to:
detect a memory access operation directed to a memory block of the plurality of memory blocks that results in at least one of a cache miss and a translation lookaside buffer (TLB) miss; and
responsive to detecting the memory access operation, increment an access count value of the plurality of access count values, wherein the access count value corresponds to the memory block;
detect a memory access operation directed to the memory block that results in a cache hit or a TLB hit; and
responsive to detecting the memory access operation to the memory block that results in the cache hit or the TLB hit, set an access-track indicator corresponding to the memory block; and
responsive to an accounting interval being triggered, clear the access-track indicator corresponding to the memory block.