Patent ID: 11900995
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A method comprising:
accessing a bitcell in an array of bitcells with a wordline and a bitline;
performing a precharge operation on the bitline with a bitline precharge signal that precharges the bitline after a read cycle and before a write cycle; and
extending precharge time of the precharge operation between the read cycle and the write cycle by modulating a wordline signal on the wordline with early cut-off of the wordline signal on the wordline during the read cycle,
wherein modulating the wordline signal is based on an early reset signal and a delayed clock signal,
wherein extending the precharge time of the precharge operation provides for early precharge of the bitline after the read cycle and before the write cycle,
wherein a falling edge at a beginning of the early reset signal triggers a falling edge of the wordline signal during the read cycle,
wherein the falling edge of the wordline signal triggers a falling edge of the bitline precharge signal, and
wherein a rising edge of the delayed clock signal triggers a rising edge of the wordline signal during the write cycle.