Patent ID: 11936387
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A correcting and phase shifting circuit, comprising:
a delay-controlled delay line (DCDL) circuit operable to receive a clock input signal;
a duty-cycle corrector (DCC) circuit operably connected to an output of the DCDL circuit and operable to adjust a duty cycle of the clock input signal;
a control circuit operably connected to an input of the DCDL circuit, an output signal of the control circuit operable to control an amount of delay generated by the DCDL circuit;
a lock detector circuit operably connected between a first input of the control circuit and a first output of a comparator circuit, an output signal of the lock detector circuit operable to control the output of the control circuit;
a counter circuit operably connected between a second input of the control circuit and a second output of the comparator circuit;
a first DC sampler circuit operably connected to a first input of the comparator circuit; and
a second DC sampler circuit operably connected to a second input of the comparator circuit.