Patent ID: 11862255
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. A memory device comprising:
a memory array; and
control logic, operatively coupled with the memory array, to perform operations comprising:
causing a voltage of a wordline to be maintained at a second voltage corresponding to a maximum threshold voltage (Vt) for a particular valley of a Vt distribution;
causing a second voltage ramp down process to be initiated;
causing a second current to be sampled with respect to cells of the wordline during the second voltage ramp down process; and
detecting an existence of charge loss by determining whether the second current has a value that is proportional to a value of a first current based on a ratio between an index number of the particular valley of the Vt distribution and a total number of valleys of the Vt distribution.