Patent ID: 11887682
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. An anti-fuse memory array circuit, comprising:
at least one control module;
a plurality of anti-fuse memory cell circuits, wherein each of the plurality of anti-fuse memory cell circuits comprises:
an anti-fuse device;
a switch module, coupled to the anti-fuse device;
a selection module, coupled to the switch module; and
a control module coupled respectively to the anti-fuse device and the switch module of each of the plurality of anti-fuse memory cell circuits, wherein the control module is configured to switch the on-off mode of the switch module according to the breakdown state of the anti-fuse device;
wherein the control module is a master control module, which is respectively coupled to the anti-fuse device of each of the plurality of anti-fuse memory cell circuits and the switch module;
wherein the master control module comprises a control unit, wherein the control unit has an input terminal and an output terminal, wherein the input terminal of the control unit is respectively coupled to the first end of the anti-fuse device of each of the plurality of the anti-fuse memory cell circuits, a write enable signal, a read enable signal, and a read enable delay signal of each of the plurality of anti-fuse memory cell circuits; and
wherein the output terminal of the control unit is respectively coupled to the switch module of each of the plurality of anti-fuse memory cell circuits.