Patent ID: 11922240
Assignee: CEREMORPHIC, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 7:
8. A multiplier-accumulator comprising:
an analog charge bus comprising a plurality of analog charge lines;
a plurality of unit elements, each unit element accepting a digital A input and a digital B input;
each said unit element comprising:
a plurality of product generators, each product generator comprising a plurality of AND gates, each AND gate of each product generator having one input coupled to a unique one of the bits of the digital A input and the other AND gate inputs commonly coupled to one of the bits of the B digital input, an output of each AND gate of each product generator coupled to a particular analog charge line through a charge transfer capacitor of value C;

a charge summing block comprising a plurality of charge scaling capacitors, each charge scaling capacitor having one terminal coupled to a respective analog charge line and the other terminal connected to an input of an analog to digital converter generating a multiplication result;
each charge scaling capacitor having a value Cs*2n where n is the order of the respective analog charge line;
and where the charge transfer capacitor value is at least 10 times greater than the largest charge scaling capacitor.