Patent ID: 11862291
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device comprising:
a memory cell array in which memory cells are connected to word lines and bit lines in a matrix form; and
a control circuit configured to control an operation of programming or reading the memory cells according to a start address, a burst length, a latency length and a program or reading instruction transmitted from a host,
wherein the control circuit comprises:
a pulse generator configured to a register pulse and a counter pulse in synchronization with an operation clock; and
a counter configured to set the start address in synchronization with the register pulse, increase a count value until the burst length, then reset the count value, and increase the count value until the latency length again in synchronization with the counter pulse, and increase an address by adding the count value to the start address while counting a number of counter pulses corresponding to the burst length, wherein the pulse generator is configured to generate the register pulse in synchronization with a rising edge of the operation clock, and generate the counter pulse in synchronization with a falling edge of the operation clock.