Patent ID: 11886719
Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A FIFO memory circuit for storing parsimonious data, said circuit being configured to receive an input data vector of size Iz at least equal to 1, and comprising:
an encoder,
a memory block comprising a first memory region dedicated to encoder information and a second memory region dedicated to the data, the second memory region being divided into a number Iz of FIFO memories, each FIFO memory being associated with one component of the input vector, only non-zero data being saved in the FIFO memories,
a decoder,
the encoder being configured to generate an indicator of non-zero data (Cn) for each component of the input vector,
the memory circuit being configured to write the non-zero data of the input data vector to the respective FIFO memories and to write the indicator of non-zero data (Cn) to the first memory region,
the decoder being configured to read the outputs of the FIFO memories and the associated indicator (Cn) in the first memory region to reconstruct the data vector,
the encoder further being configured to rearrange the order of the non-zero data in the data vector so as to balance the number of non-zero data saved in each FIFO memory and the decoder further being configured to apply the inverse operation of the encoder to the outputs of the FIFO memories.