Patent ID: 11967574
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A memory device, comprising:
a first structure; and
a second structure on the first structure, wherein:
the first structure includes:
a first substrate;
a first transistor and a second transistor on the first substrate;
a first insulating layer covering the first substrate, the first transistor, and the second transistor;
a first bonding pad on the first insulating layer and connected to the first transistor; and
a second bonding pad on the first insulating layer and connected to the second transistor,

the second structure includes:
a second substrate;
a memory cell array including a plurality of gate layers stacked on a first surface of the second substrate and a plurality of channel structures respectively penetrating the plurality of gate layers;
a second insulating layer directly contacting and covering the first surface of the second substrate and the memory cell array;
a conductive pattern on a second surface of the second substrate or extending at least partially from the second surface of the second substrate into the second substrate and spaced apart from the second insulating layer;
a third bonding pad on the second insulating layer and connected to the conductive pattern; and
a fourth bonding pad on the second insulating layer and connected to the conductive pattern,

the first bonding pad is in contact with the third bonding pad, and
the second bonding pad is in contact with the fourth bonding pad.