Patent ID: 11915769
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A method, comprising:
performing one or more program-verify steps to verify whether non-volatile memory cells have reached target memory states and generating corresponding pass/fail bits;
storing a first plurality of pass/fail bits for a first plurality of non-volatile memory cells connected to a bit line in a first plurality of latches that are connected to a first local data bus;
storing a second plurality of pass/fail bits for a second plurality of non-volatile memory cells connected to the bit line in a second plurality of latches that are connected to a second local data bus; and
selectively blocking pass/fail bits of the first plurality of pass/fail bits and the second plurality of pass/fail bits according to an indicator bit stored in a shared isolation latch.