Patent ID: 11887968
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of manufacturing a semiconductor package, the method comprising:
providing a substrate including a plurality of basic structures, each of the plurality of basic structures having a first pad on a lower surface thereof, and a second pad on an upper surface thereof;
stacking a plurality of first semiconductor chips on the substrate, each of the plurality of first semiconductor chips having:
a first connection pad directly bonded to the second pad, and
a first through-electrode inside each of the plurality of first semiconductor chips, the first through-electrode being electrically connected to the first connection pad;

after stacking the plurality of first semiconductor chips, grinding the plurality of first semiconductor chips to form a ground surface in each of the plurality of first semiconductor chips, the first through-electrode having a tip protruding above the ground surface of each of the plurality of first semiconductor chips;
forming a first upper insulating layer on the plurality of first semiconductor chips to cover the protruding tip of the first through-electrode;
grinding the first upper insulating layer to expose an upper surface of the first through-electrode, such that an upper surface of the first insulating layer is substantially coplanar with the upper surface of the first through-electrode;
forming a second upper insulation layer on the first upper insulation layer and a first bonding pad connected to the first through-electrode, an upper surface of the second upper insulating layer being substantially coplanar with an upper surface of the first bonding pad;
stacking a plurality of second semiconductor chips on the plurality of first semiconductor chips, respectively, each of the plurality of second semiconductor chips having a second connection pad directly bonded to the first bonding pad and a second lower insulation layer directly bonded to the second upper insulation layer;
forming a molding member surrounding the stacked first and second semiconductor chips on the substrate; and
after forming the molding member, cutting the substrate to obtain a plurality of semiconductor packages, each of the plurality of semiconductor packages having a basic structure and the stacked first and second semiconductor chips on the basic structure, and each of the plurality of semiconductor packages including a dummy insulation portion having a side surface that is coplanar with a side surface of the molding member.