Patent ID: 11925012
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for forming a capacitor array structure, comprising the following steps:
providing a substrate, a capacitor contact being exposed on a surface of the substrate, the substrate comprising an array region and a peripheral region, and the capacitor contact being located at the array region;
forming a bottom supporting layer covering the substrate and the capacitor contact, the bottom supporting layer having a gap therein;
forming a filling layer filling the gap and covering the capacitor contact and the surface of the bottom supporting layer, a thickness of the filling layer located at the peripheral region being larger than that of the filling layer located at the array region;
forming supporting layers and sacrificial layers alternately stacked in a direction perpendicular to the substrate;
forming a capacitor hole at least penetrating through the supporting layer and the sacrificial layer and exposing the capacitor contact; and
sequentially forming a lower electrode layer on an inner wall of the capacitor hole, a dielectric layer on a surface of the lower electrode layer and an upper electrode layer on a surface of the dielectric layer to form a capacitor.