Patent ID: 11955421
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. The method of claim 12, further comprising:
depositing a second interlevel dielectric layer over the first interlevel dielectric layer;
patterning a second mask on the second interlevel dielectric layer;
irradiating a first region of the second interlevel dielectric layer exposed by the second mask;
preventing irradiation of a second region of the second interlevel dielectric layer with the second mask;
forming first trenches in the first region of the first interlevel dielectric layer;
forming second trenches in the second region of the first interlevel dielectric layer; and
forming first metal signal lines in the first trenches and first and second electrodes of a capacitor in the second trenches by depositing a metal in the first and second trenches.