Patent ID: 11923411
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. An integrated chip, comprising:
an isolation structure disposed within a substrate and defining an active region in the substrate;
a first doped region disposed within the active region;
a second doped region disposed within the active region and separated from the first doped region by a middle region of the active region along a first direction,
a gate structure extending over the active region along a second direction perpendicular to the first direction, the gate structure comprising a first gate electrode region having a first work function and a second gate electrode region having second work functions different from the first work function, the second gate electrode region having discrete segments separated by a center portion of the first gate electrode region along the second direction; and
a first divot and a second divot of the isolation structure disposed on opposite sides of the middle region of the active region along the second direction, the first divot and the second divot recessed below an uppermost surface of the isolation structure;
wherein the first gate electrode region fills in the first divot and the second divot, and the second gate electrode region is disposed above and between the first divot and the second divot.