Patent ID: 11928015
Assignee: NATIONAL TECHNOLOGY & ENGINEERING SOLUTIONS OF SANDIA, LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. The system of claim 7, wherein the ordered set of rules comprises a second rule, wherein the FPGA executes the second rule, wherein the second rule is one of:
a delay rule that causes the FPGA not to evaluate signals received by the transceiver for a period of time defined by the delay rule;
an origin reset rule that causes the FPGA to reset an address counter that specifies an execution position in the ordered set of rules;
a skip rule that causes the FPGA to fail to evaluate a bit against a rule in the ordered set of rules; or
an origin specification rule that causes the FPGA to modify an origin position for the address counter.