Patent ID: 11862996
Assignee: NAVITAS SEMICONDUCTOR LIMITED
Field: Semiconductors (Electrical engineering)
Classification: CPC H  Y | IPC H

Claim 0:
1. A circuit comprising:
a first transistor having a first gate terminal, a first source terminal and a first drain terminal; and
a second transistor having a second gate terminal, a second source terminal and a second drain terminal;
wherein the first drain terminal is coupled to the second source terminal;
wherein the first transistor is a gallium nitride (GaN)-based lateral high electron mobility transistor (HEMT) and the second transistor is a GaN-based lateral HEMT;
wherein the first transistor is disposed on a first GaN-based substrate and the second transistor is disposed on a second GaN-based substrate; and wherein the first GaN-based substrate contains only the first transistor, and the second GaN-based substrate only contains the second transistor.