Patent ID: 11923243
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for manufacturing a semiconductor structure, comprising:
preparing a dielectric structure which is formed with trenches respectively defined by lateral surfaces of the dielectric structure;
forming spacer layers on the lateral surfaces of the dielectric structure;
filling an electrically conductive material into the trenches to form electrically conductive features;
selectively depositing a blocking layer on the dielectric structure in such a manner that the electrically conductive features are exposed from the blocking layer;
selectively depositing a dielectric material on the exposed electrically conductive features to form a capping layer such that the electrically conductive features are covered by the capping layer and the spacer layers;
removing the blocking layer and the dielectric structure to form a plurality of recesses defined by the spacer layers;
filling a sacrificial material into the recesses so as to form sacrificial features;
forming a sustaining layer to cover the sacrificial features; and
removing the sacrificial features to form air gaps confined by the sustaining layer and the spacer layers.