Patent ID: 11955079
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. A pixel electrically connected to each of a first scan line, a second scan line, a third scan line, an emission control line, a data line, a power line, a first voltage line, a second voltage line, and a third voltage line, the first scan line being configured to transfer a first scan signal, the second scan line being configured to transfer a second scan signal, the third scan line being configured to transfer a third scan signal, the emission control line being configured to transfer an emission control signal, the data line being configured to transfer a data voltage, the power line being configured to transfer a driving voltage, the first voltage line being configured to transfer a reference voltage, the second voltage line being configured to transfer an initialization voltage, the third voltage line being configured to transfer a bias voltage, the pixel comprising:
a display element including an anode and a cathode;
a storage capacitor including a first electrode and a second electrode, the second electrode being electrically connected to the anode of the display element;
a first transistor including a first gate, a second gate, a drain, and a source, wherein the first gate is electrically connected to the first electrode of the storage capacitor;
a second transistor configured to connect the data line to the source of the first transistor in response to the first scan signal;
a third transistor configured to connect the first gate of the first transistor to the drain of the first transistor in response to the first scan signal;
a fourth transistor configured to connect the first voltage line to the first gate of the first transistor in response to the second scan signal;
a fifth transistor configured to connect the power line to the drain of the first transistor in response to the emission control signal;
a sixth transistor configured to connect the anode of the display element to the source of the first transistor in response to the emission control signal;
a seventh transistor configured to connect the second voltage line to the anode of the display element in response to the third scan signal;
an eighth transistor configured to connect the second gate of the first transistor to the anode of the display element in response to the emission control signal; and
a ninth transistor configured to connect the third voltage line to the second gate of the first transistor in response to the third scan signal.