Patent ID: 11956968
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A memory device, comprising:
a layer stack disposed on a substrate, wherein the layer stack at least comprises two metal layers separated from each other;
a first gate structure comprising a first conductive pillar, a first ferroelectric layer, and a first channel layer;
a second gate structure comprising a second conductive pillar, a second ferroelectric layer, and a second channel layer, wherein the first and second gate structures penetrate through the layer stack, and the two metal layers laterally surround the first and second gate structures; and
an isolation structure, disposed between the first and second gate structures, wherein the first conductive pillar and the second conductive pillar are divided into two individual conductive pillars by the isolation structure, the first ferroelectric layer and the second ferroelectric layer are divided into two individual ferroelectric layers by the isolation structure, and the first channel layer and the second channel layer are divided into two individual channel layers by the isolation structure,
wherein the first gate structure is a mirror image of the second gate structure with respect to the isolation structure.