Patent ID: 11960752
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A solid state device comprising:
a plurality of three-dimensional NAND flash memory chips including a memory cell array including three-dimensional memory cells; and
a memory controller including a volatile memory and configured to receive temperature information including a plurality of entries through NVMe protocol from a host, and to store the temperature information in the volatile memory, the plurality of entries including a first entry and a second entry, and the temperature information including performance level information,
wherein the first entry includes a first temperature and a corresponding first performance level, and the second entry includes a second temperature and a corresponding second performance level, wherein the second temperature is higher than the first temperature, and wherein the first entry and the second entry are defined by the host,
the memory controller is further configured to detect an internal temperature of the solid state device,
when the detected internal temperature is between the first temperature and the second temperature, the memory controller is further configured to perform a first throttling operation to cause the solid state device to operate at the first performance level without intervention from the host,
when the detected internal temperature is greater than the second temperature, the memory controller is further configured to perform a second throttling operation to cause the solid state device to operate at the second performance level that is lower than the first performance level without intervention from the host,
the memory controller is further configured to automatically change from the first throttling operation to the second throttling operation based on the detected internal temperature and the first and second entries,
wherein the second performance level has a level that causes the internal temperature to be lowered below the second temperature included in the second entry, and
wherein the first and second performance levels are lower than a normal performance level.