Patent ID: 11955516
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 17:
18. A method for manufacturing a semiconductor device, the method comprising:
forming a first lower pattern extending in a first direction;
forming a plurality of first sheet patterns on the first lower pattern;
forming a second lower pattern extending in the first direction and spaced apart from the first lower pattern in a second direction;
forming a plurality of second sheet patterns on the second lower pattern;
forming a field insulating film between the first lower pattern and the second lower pattern;
forming a pre-gate structure extending in the second direction and intersecting the first and second lower patterns, the pre-gate structure including a pre-gate electrode surrounding the plurality of first sheet patterns and the plurality of second sheet patterns, a pre-gate spacer on sidewalls of the pre-gate electrode, and a pre-gate capping pattern on the pre-gate electrode;
forming a gate separation trench by partially removing the pre-gate electrode, the pre-gate spacer, and the pre-gate capping pattern, such that the gate separation trench exposes the field insulating film;
forming a connecting spacer by removing a portion of the pre-gate spacer, such that the connecting spacer is disposed between the gate separation trench and the filed insulating film; and
forming a gate separation structure filling the gate separation trench,
wherein the gate separation structure includes a gate separation liner and a gate separation filling film on the gate separation liner,
wherein a topmost surface of the gate separation liner and a top surface of the pre-gate capping pattern are on a same plane,
wherein the connecting spacer protrudes from a top surface of the field insulating film, and the gate separation liner of the gate separation structure contacts the connecting spacer and extends along a top surface and sidewalls of the connecting spacer and along the top surface of the field insulating film, and
wherein a height from a top surface of the gate separation structure to a lowermost part of the gate separation structure is greater than a depth from the top surface of the gate separation structure to a bottom surface of the connecting spacer.