Patent ID: 11935583
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 26:
27. An integrated assembly, comprising:
a memory array over a base;
vertically-extending digit lines associated with the memory array;
sense amplifiers under the memory array and coupled with the digit lines;
routing structures coupled to each of the digit lines and extending to Mux components; the Mux components being in one-to-one correspondence with the digit lines; each of the Mux components comprising a first transistor and a second transistor; the first transistors having first gates, first source/drain regions and second source/drain regions; the first gates gatedly coupling the first and second source/drain regions with one another; the second transistors having second gates, third source/drain regions and fourth source/drain regions; the second gates gatedly coupling the third and fourth source/drain regions with one another; the routing structures being coupled with the second and third source/drain regions; the first source/drain regions being coupled with second sense-amplifier-circuitry; the fourth source/drain regions being coupled with a voltage source; the first and second gates being coupled with Mux-Driver-circuitry configured to selectively activate/deactivate the first and second gates; and
wherein the sense amplifiers are local sense amplifiers, wherein the second sense-amplifier-circuitry comprises global sense amplifiers, and wherein at least 500 of the local sense amplifiers are associated with each of the global sense amplifiers.