Patent ID: 11944021
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 9:
10. An integrated circuit (IC) comprising:
a logic device disposed over a logic region of a semiconductor substrate and including a logic interconnect structure thereover, wherein the logic interconnect structure includes a via arranged between a lower metal interconnect layer and an upper metal interconnect layer;
one or more memory cells disposed over a memory region of the semiconductor substrate and arranged between the lower metal interconnect layer and the upper metal interconnect layer, wherein a memory cell comprises:
a bottom electrode coupled to the lower metal interconnect layer;
a non-magnetic data storage layer disposed over the bottom electrode; and
a top electrode disposed over the non-magnetic data storage layer; and
wherein a height of the memory cell over the memory region between a lower surface of the bottom electrode and an upper surface of the top electrode is equal to a height of the via.