Patent ID: 11923340
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor package, comprising:
a package substrate;
a base chip disposed on the package substrate;
a first semiconductor chip disposed on the base chip;
a second semiconductor chip disposed on the first semiconductor chip;
an inner mold layer surrounding an upper surface of the base chip and respective side surfaces of the first semiconductor chip and the second semiconductor chip;
a first outer mold layer interposed between the package substrate and the base chip while covering at least a portion of a side surface of the base chip; and
a second outer mold layer disposed on the first outer mold layer while covering at least a portion of a side surface of the inner mold layer, the second outer mold layer being spaced apart from the package substrate,
wherein the first outer mold layer and the second outer mold layer have different viscosities, respectively,
wherein an under surface of the first outer mold layer is in contact with the package substrate,
wherein an upper surface of the first outer mold layer is in contact with an under surface of the second outer mold layer,
wherein an outer surface of the first outer mold layer extends from the upper surface of the first outer mold layer to the under surface of the first outer mold layer,
wherein the upper surface of the first outer mold layer and the under surface of the second outer mold layer are flat, and
wherein the upper surface of the first outer mold layer is in contact with the under surface of the second outer mold layer.