Patent ID: 11942182
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An integrated buffer circuit for buffering signals on a first memory to and from an integrated controller circuit, the integrated buffer circuit comprising:
a first timing port to receive a timing signal from the integrated controller circuit;
a second timing port to transmit the timing signal received on the first timing port to a second memory;
a third timing port to receive the timing signal transmitted from the second timing port back from the second memory;
a first read port to receive first read signals from the second memory timed to the timing signal on the third timing port;
a fourth timing port to transmit the timing signal received on the third timing port to the integrated controller circuit;
a bidirectional port to receive second read signals from the first memory; and
a second read port to transmit the first read signals and the second read signals to the integrated controller circuit and timed to the timing signal on the fourth timing port.