Patent ID: 11894236
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. The method for manufacturing the semiconductor structure of claim 8, wherein, the isolation layer comprises: a bottom support layer, a first sacrificial layer, an intermediate support layer, a second sacrificial layer and a top support layer which are stacked; and
the capacitor holes penetrate through the bottom support layer, the first sacrificial layer, the intermediate support layer, the second sacrificial layer and the top support layer; and
after forming the lower electrodes, the method further comprises: removing parts of the top support layer and parts of the intermediate support layer, and removing the first sacrificial layer and the second sacrificial layer, so as to expose the lower electrodes;
forming a dielectric layer covering surfaces of the lower electrodes;
forming an upper electrode covering the dielectric layer, wherein the upper electrode, the lower electrodes and the dielectric layer are configured to form capacitors; and
forming a cover layer located on a surface of the upper electrode.