Patent ID: 11908735
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A device comprising:
two gate structures disposed over a substrate, wherein one of the two gate structures is disposed between a first epitaxial source/drain feature and a second epitaxial source/drain feature;
a cobalt-containing contact disposed directly on the first epitaxial source/drain feature, wherein the cobalt-containing contact includes a first cobalt-containing bulk layer, the cobalt-containing contact is disposed in a first interlayer dielectric layer, and the cobalt-containing contact extends below top surfaces of the two gate structures, such that the cobalt-containing contact is sandwiched by the two gate structures;
a cobalt-containing via disposed directly on the cobalt-containing contact, wherein the cobalt-containing via is disposed in a second interlayer dielectric layer and the cobalt-containing via includes:
a second cobalt-containing bulk layer disposed on the cobalt-containing contact, and
a titanium-and-nitrogen-containing barrier layer disposed along a sidewall of the second cobalt-containing bulk layer; and

a copper-containing feature disposed directly on the cobalt-containing via, wherein the copper-containing feature is disposed in a third interlayer dielectric layer.