Patent ID: 11886987
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. An architecture for performing multiply-accumulate computation in a neural network, comprising:
a plurality of networks arranged in one or more tiled columns, each network including a plurality of selectable parallel elements and each parallel element having a predetermined conductance value;
logic configured to digitally program the equivalent conductance of individual networks among the plurality of networks, where:
said digitally programming includes, for each individual network, selecting one or more of the parallel elements of the individual network to map the equivalent conductance of the individual network to a single weight of a partial selection of weights of the neural network,
said digitally programming enables computation of multiply-and-accumulate operations by mixed-signal computation when a voltage bias is applied across networks in the one or more tiled columns, and
said digitally programming not alter the predetermined conductance values of the plurality of selectable parallel element; and, where the architecture is configured to compute multiply-and-accumulate operations for a plurality of programmed partial weight selections until computations for the neural network are completed.