Patent ID: 11894326
Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method comprising:
providing a substrate having a recess or opening extending from a first surface of the substrate, at least a portion of the first surface of the substrate having a planarized topography;
disposing a first conductive material having a first melting point within the recess or opening and forming a first portion of an interconnect structure of the substrate; and
disposing a second conductive material having a second melting point different from the first melting point within the recess or opening and at least partially surrounded by the first conductive material, the second conductive material forming a second portion of the interconnect structure of the substrate, the second portion of the interconnect structure comprising a plurality of conductive portions extending normal to the plane of the substrate; and
providing a barrier layer between the substrate and the first conductive material.