Patent ID: 11900984
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory module, comprising:
a first integrated circuit to detect a secure shutdown event and to provide an indicator of the secure shutdown event;
a plurality of memory components comprising blocks of memory cells, a first memory component of the plurality of memory components comprising a first sense amplifier circuit and a first block of memory cells, the first block of memory cells coupled to a plurality of wordlines and a plurality of bitlines of a memory array, the plurality of bitlines including a first bitline coupled to a plurality of memory cells respectively coupled to the plurality of wordlines and the first bitline;
the first memory component to, based on the indicator of the secure shutdown event, erase the block of memory cells by causing activations of the plurality of wordlines of the first block of memory cells to occur concurrently, concurrent activation of the plurality of wordlines to cause a sharing, with the first bitline, of a plurality of charges held by the plurality of memory cells; and
the first sense amplifier circuit is to amplify a voltage difference resulting from the sharing of the plurality of charges held by the plurality of memory cells to a writeback voltage that is written to each of the plurality of memory cells.