Patent ID: 11886359
Assignee: D-MATRIX CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. A chiplet device, the chiplet comprising:
a plurality of tiles, each of the tiles comprising:
a plurality of slices,
a reduced instruction set computer (RISC) central processing unit (CPU) coupled to the plurality of slices and a dispatch engine, and
a hardware dispatch device coupled to the RISC CPU;
a plurality of die-to-die (D2D) interconnects coupled to each of the RISC CPUs in each of the tiles, the plurality of D2D interconnects being configured with single-ended signaling;
a peripheral component interconnect express (PCIe) bus coupled to each of the RISC CPUs in each of the tiles;
a dynamic random access memory (DRAM) interface coupled to each of the RISC CPUs in each of the tiles; and
a global RISC CPU coupled to each of the RISC CPUs in each of the tiles;
wherein each of the slices includes a digital in memory compute (DIMC) device coupled to a clock and configured to allow for a first throughput of one or more matrix computations provided in the DIMC device such that a second throughput of a plurality of multiply accumulates per clock cycle is achieved;
wherein each of the slices includes a single input multiple data (SIMD) processor coupled to an output of the DIMC device and configured to process one or more non-linear operations and one or more linear operations on a vector process;
wherein the plurality of tiles is configured to process a workload of a transformer;
wherein the transformer includes a plurality of transformer layers, each of the transformer layers having an attention layer associated with a portion of the workload;
wherein each attention layer is mapped on to one of the plurality of slices using the global RISC CPU to communicate with the CPU of the tile associated with the slice to process the portion of the workload associated with the attention layer;
wherein the mapping between the attention layers and the slices comprises a tiling attention process; and
wherein each of the slices includes a data reshape engine (DRE) device coupled to the DIMC device and the SIMD processor and configured to be operable with a transpose process and other data layout changes.