Patent ID: 11948616
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 14:
15. The manufacturing method of a semiconductor structure according to claim 13, wherein while the second interconnecting hole is formed in the second dielectric layer, a fifth interconnecting hole is further formed in the second dielectric layer; while the second interconnecting structure is formed in the second interconnecting hole, a fifth interconnecting structure is further formed in the fifth interconnecting hole;
while a pair of bottom electrodes spaced apart are formed on the second dielectric layer, a second conductor layer is further formed between the bottom electrodes, wherein the second conductor layer is connected to the first conductor layer through the fifth interconnecting structure, a gap exists between the second conductor layer and the bottom electrode, and the gap between the second conductor layer and the bottom electrode is filled with the third dielectric layer;
while the fourth interconnecting hole is formed in the fifth dielectric layer and the fourth dielectric layer, a sixth interconnecting hole is further formed in the fifth dielectric layer and the fourth dielectric layer, and a seventh interconnecting hole is formed in the fifth dielectric layer, wherein the sixth interconnecting hole exposes the second conductor layer, and the seventh interconnecting hole exposes the top electrode of the second magnetic memory structure; while the third interconnecting structure is formed in the third interconnecting hole and the fourth interconnecting structure is formed in the fourth interconnecting hole, a sixth interconnecting structure is further formed in the sixth interconnecting hole, and a seventh interconnecting structure is formed in the seventh interconnecting hole; while the first bit line and the second bit line are formed on the fifth dielectric layer, a third conductor layer is further formed on the fifth dielectric layer, wherein the third conductor layer is connected to the second conductor layer through the sixth interconnecting structure, and is connected to the top electrode of the second magnetic memory structure through the seventh interconnecting structure.