Patent ID: 11915741
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. A system, comprising:
a logic component; and
a plurality of memory components coupled with the logic component; and
wherein each of the plurality of memory components comprise a plurality of partitioned banks, each bank comprising:
an array of memory cells;
respective sensing circuitry coupled to the array and configured to perform operations on the respective bank; and
respective timing circuitry coupled to the array and the respective sensing circuitry and responsible for conflict free access to the array of memory cells; and

wherein the logic component comprises:
a first partitioned logic coupled to:
a plurality of timing circuitries from a first number of different respective memory components of the plurality of memory components; and
a plurality of sensing circuitries from the first number of different respective memory components of the plurality of memory components, wherein the first number of different memory components form one or more processing in memory (PIM) devices;

a second partitioned logic coupled to:
a plurality of timing circuitries from a second number of different respective memory components of the plurality of memory components; and
a plurality of sensing circuitries from the second number of different respective memory components of the plurality of memory components, wherein the second number of different memory components form one or more PIM devices; and

wherein the logic component further comprises switching circuitry coupled to the first and second partitioned logics, the switching circuitry configured to:
route received memory array requests; and
route received PIM requests to perform a logical operation using at least one of the plurality of the sensing circuitries.