Patent ID: 11869622
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 3:
4. The apparatus of claim 1, wherein:
the first memory array includes a first input/output (I/O) circuit coupled with a first through-silicon via (TSV), the first I/O circuit positioned at a first column position and the first TSV positioned at a second column position;
the first memory array including a conductive path configured to route a second TSV of the first memory array at a third column position to a third TSV of the second memory array positioned at the second column position; and
the second memory array including a second I/O circuit coupled with the third TSV, the second I/O circuit positioned at the first column position and the second TSV positioned at the second column position.