Patent ID: 11908764
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A package comprising:
a redistribution layer having a first surface and a second surface opposite to the first surface;
a molded structure disposed on the first surface of the redistribution layer, wherein the molded structure includes a first die and a second die laterally surrounded by a molding compound, and the first and second dies are electrically connected with the redistribution layer;
a circuit substrate connected with the second surface of the redistribution layer, wherein the circuit substrate includes a dielectric material, a cavity concave into the dielectric material and having metal-free dielectric surfaces, and a floor plate embedded in the dielectric material with both top and bottom surfaces of the floor plate being fully covered by the dielectric material and located below the cavity, wherein the floor plate includes multiple parallel arranged metallic plates, and a vertical projection of the cavity overlaps the multiple parallel arranged metallic plates;
a third die, disposed on the second surface of the redistribution layer, located in the cavity and electrically connected with the redistribution layer; and
an underfill, disposed between the third die and the cavity and between the circuit substrate and the redistribution layer.