Patent ID: 11934834
Assignee: AMPERE COMPUTING LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. A method of tracking operation source parent information in a processor, comprising:
establishing a first scheduler entry of a plurality of scheduler entries, the first scheduler entry comprising first operation source parent information;
providing the first operation source parent information to a parent selection circuit;
selecting a compare source parent from a plurality of source parents based on the first operation source parent information, wherein each of the plurality of source parents is associated with an execution pipeline of a plurality of execution pipelines; and
performing a dependency comparison associated with the first scheduler entry using the compare source parent;
wherein performing the dependency comparison comprises:
selecting, using the first operation source parent information, an associated execution pipeline from among the plurality of execution pipelines on which to perform the dependency comparison;
selecting, using the first operation source parent information, information from the associated execution pipeline; and
performing the dependency comparison only against the information from the associated execution pipeline.