Patent ID: 11886335
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 2:
3. The memory system according to claim 1, wherein
the controller is configured to:
in response to a change in the first number of blocks included in the first block set or the second number of blocks included in the second block set,
calculate the first rewrite speed based on the first remaining time and the first number of blocks included in the first block set;
calculate the second rewrite speed based on the second remaining time and the sum of i) the first number of blocks and ii) the second number of blocks included in the second block set;
determine the maximum rewrite speed among the first rewrite speed and the second rewrite speed; and
perform, at the determined maximum rewrite speed, the rewrite operation on i) the first number of blocks included in the first block set and ii) the second number of blocks included in the second block set.