Patent ID: 11868697
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A base layout cell, comprising:
first and second metal layer patterns extending in a first direction;
a plurality of active area layer patterns between the first metal layer pattern and the second metal layer pattern, wherein the plurality of active area layer patterns extends in the first direction;
a plurality of conductive gate layer patterns extending in a second direction perpendicular to the first direction and traversing over the first and second metal layer patterns and over the plurality of active area layer patterns;
a plurality of metal-layer patterns extending in the second direction between two conductive gate layer patterns of the plurality of conductive gate layer patterns, wherein at least one metal-layer pattern of the plurality of metal-layer patterns traverses over at least one active area layer pattern of the plurality of active area layer patterns; and
a cut metal layer extending in the first direction between two active area layer patterns of the plurality of active area layer patterns,
wherein the cut metal layer is between at least two conductive gate layer patterns and separated from the plurality of metal-layer patterns, and
wherein the base layout cell comprises one or more layout patterns common to a plurality of non-identical functional cell layouts.