Patent ID: 11888494
Assignee: NUVOTON TECHNOLOGY CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. The semiconductor circuit according to claim 10, wherein in the first set test mode, the self-diagnostic code generation circuit:
sets, for the first element group, a first bit signal to 1 or 0, the first bit signal being for controlling the single correction element selected as the test target;
causes a second correction bit signal group to have an inverted logical value of the first bit signal, the second correction bit signal being for controlling a correction element included in the correction element group and having an adjustment weight smaller than an adjustment weight of a first correction element included in the correction element group;
causes a test bit signal to have the inverted logical value of the first bit signal, the test bit signal being for controlling the one or more test elements;
outputs other bit signals as predetermined fixed signals; and
outputs, to the second element group, the optimum correction code so that the quantization error of the quantizer becomes minimum,
in the first set test mode, the digital circuit:
generates a first error signal, based on the error signal from the error detection circuit;
causes, for a control code for the first element group, the first bit signal to have an inverted logical value of a bit signal at a first step;
causes the second correction bit signal group to have the inverted logical value of the bit signal at the first step;
causes the test bit signal to have the inverted logical value of the bit signal at the first step;
outputs other bit signals as predetermined fixed signals;
outputs the optimum correction code continuously to the second element group;
generates a second error signal as an output of the error detection circuit; and
determines magnitudes of the first error signal and the second error signal at a transition point of the quantizer at which the quantization error is minimum, to test whether a weight is smaller than or equal to a predetermined value, and
in the second set test mode, the digital circuit performs a process which is similar to a process in the first set test mode and in which the first element group and the second element group are interchanged in the first set test mode.