Patent ID: 11875861
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 18:
19. A memory, comprising:
a first data line;
a second data line;
an array of memory cells comprising a first string of series-connected memory cells selectively connected to the first data line and a second string of series-connected memory cells selectively connected to the second data line;
a common source selectively connected to the first string of series-connected memory cells and selectively connected to the second string of series-connected memory cells;
a first sensing device selectively connected to the first data line;
second sensing device selectively connected to the second data line;
a controller for access of the array of memory cells, wherein the controller is configured to cause the memory to:
precharge the first data line and precharge the second data line;
selectively connect the first data line to the common source through a selected memory cell of the first string of series-connected memory cells while applying a verify voltage level to a control gate of the selected memory cell of the first string of series-connected memory cells, and while the common source is configured to receive a first voltage level;
selectively connect the second data line to the common source through a selected memory cell of the second string of series-connected memory cells while applying the verify voltage level to a control gate of the selected memory cell of the second string of series-connected memory cells;
connect the first data line to a first voltage node through a first p-type field-effect transistor (pFET), wherein the first voltage node is configured to receive a second voltage level lower than the first voltage level;
connect the second data line to a second voltage node through a second pFET, wherein the second voltage node is configured to receive the second voltage level;
determine whether the selected memory cell of the first string of series-connected memory cells has an intended threshold voltage for the selected memory cell of the first string of series-connected memory cells in response to a voltage developed on the first data line while connected to the first voltage node and selectively connected to the common source; and
determine whether the selected memory cell of the second string of series-connected memory cells has an intended threshold voltage for the selected memory cell of the second string of series-connected memory cells in response to a voltage level developed on the second data line while connected to the second voltage node and selectively connected to the common source;

wherein the controller being configured to cause the memory to determine whether the selected memory cell of the second string of series-connected memory cells has the intended threshold voltage for the selected memory cell of the second string of series-connected memory cells comprises the controller being configured to cause the memory to determine whether the selected memory cell of the second string of series-connected memory cells has the intended threshold voltage for the selected memory cell of the second string of series-connected memory cells concurrently with causing the memory to determine whether the selected memory cell of the first string of series-connected memory cells has the intended threshold voltage for the selected memory cell of the first string of series-connected memory cells;
wherein the intended threshold voltage for the selected memory cell of the first string of series-connected memory cells corresponds to a particular data state of a plurality of data states, and wherein the intended threshold voltage for the selected memory cell of the second string of series-connected memory cells corresponds to a different data state of the plurality of data states; and
wherein the particular data state and the different data state are adjacent data states of the plurality of data states.