Patent ID: 11922240
Assignee: CEREMORPHIC, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A unit element having a digital A input and a digital B input, the unit element comprising:
a plurality of AND-groups, each AND-group comprising a plurality of AND gates, each AND gate of each AND-group having one input coupled to a unique digital bit of the A input and the other AND gate inputs commonly coupled to a digital bit of the B input;
a plurality of analog charge lines, each analog charge line coupled to a respective output of an AND gate of each AND-group through a charge transfer capacitor of value C;
a charge summing unit comprising a plurality of charge summing capacitors, one terminal of each charge summing capacitor coupled to a respective analog charge line, the other terminals of the charge summing capacitors coupled to an input of an analog to digital converter;
each charge summing capacitor of the charge summing unit having a value Cs*2n where n is the order of the respective analog charge line and a value Cs is smaller than the value C;
and where the largest value of Cs is smaller than ⅛th of an accumulated capacitance of charge transfer capacitors associated with AND gates coupled to an associated analog charge line.