Patent ID: 11929116
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A memory device, comprising:
a memory cell;
a bit line connected to the memory cell;
a first write path connected to the bit line, wherein the first write path comprises a negative voltage generator circuit, wherein the negative voltage generator circuit, when enabled, is operative to provide a negative voltage to the bit line;
a second write path comprising a pull down transistor connected between the bit line and ground; and
a pull down circuit comprising a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the pull down circuit is operative to receive data signal to be written to the memory cell, wherein the second input terminal of the pull down circuit is directly connected to the negative voltage generator circuit and is operative to receive a write assist enable signal that is being provided to the negative voltage generator circuit, wherein the output terminal of the pull down circuit is connected to a gate of the pull down transistor, wherein the pull down circuit is operative to enable the pull down transistor in response to the write assist enable signal attaining a second value, and wherein when enabled the pull down transistor provides the second write path.