Patent ID: 11862098
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. The shift register according to claim 8, wherein the driving output circuit comprises: a second transistor, a third transistor, a fourth transistor, and a fifth transistor; the cascade output circuit comprises a sixth transistor and a seventh transistor; and the input control circuit comprises an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor and a twelfth transistor;
wherein a grid electrode of the second transistor is coupled with the cascade signal end, a first electrode of the second transistor is coupled with the second reference signal end, and a second electrode of the second transistor is coupled with a grid electrode of the fifth transistor;
a grid electrode of the third transistor is coupled with the first noise reduction clock signal end, a first electrode of the third transistor is coupled with the first reference signal end, and a second electrode of the third transistor is coupled with the grid electrode of the fifth transistor;
a grid electrode of the fourth transistor is coupled with the cascade signal end, a first electrode of the fourth transistor is coupled with the second reference signal end, and a second electrode of the fourth transistor is coupled with the driving signal end;
a first electrode of the fifth transistor is coupled with the first reference signal end, and a second electrode of the fifth transistor is coupled with the driving signal end;
a grid electrode of the sixth transistor is coupled with the second pull-up node, a first electrode of the sixth transistor is coupled with the second control clock signal end, and a second electrode of the sixth transistor is coupled with the cascade signal end;
a grid electrode of the seventh transistor is coupled with the pull-down node, a first electrode of the seventh transistor is coupled with the second reference signal end, and a second electrode of the seventh transistor is coupled with the cascade signal end;
a grid electrode of the eighth transistor is coupled with the first control clock signal end, a first electrode of the eighth transistor is coupled with the input signal end, and a second electrode of the eighth transistor is coupled with the first pull-up node;
a grid electrode of the ninth transistor is coupled with the first control clock signal end, a first electrode of the ninth transistor is coupled with the first reference signal end, and a second electrode of the ninth transistor is coupled with the pull-down node;
a grid electrode of the tenth transistor is coupled with the first pull-up node, a first electrode of the tenth transistor is coupled with the first control clock signal end, and a second electrode of the tenth transistor is coupled with the pull-down node;
a grid electrode of the eleventh transistor is coupled with the pull-down node, a first electrode of the eleventh transistor is coupled with the second reference signal end, and a second electrode of the eleventh transistor is coupled with a first electrode of the twelfth transistor; and
a grid electrode of the twelfth transistor is coupled with the second control clock signal end, and a second electrode of the twelfth transistor is coupled with the first pull-up node;
wherein a width-to-length ratio of a channel region of an active layer of at least one of the fourth transistor, the fifth transistor, the sixth transistor or the seventh transistor is greater than a width-to-length ratio of a channel region of an active layer of at least one of the first transistor, the second transistor, the third transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor or the twelfth transistor.