Patent ID: 11962301
Assignee: NVIDIA CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. The SERDES system of claim 10, further comprising a receiver device comprising:
a time-interleaved analog-to-digital converter (TI-ADC); and
a clock data recovery (CDR) circuit coupled to the TI-ADC, the CDR circuit to provide a second set of N phase signals to the TI-ADC, wherein the CDR circuit comprises:
a second ring oscillator comprising a second set of M delay stages, each stage to output a phase signal; and
a second phase selector circuit coupled to the second ring oscillator, wherein the second phase selector circuit is to:
receive a second set of M phase signals from the second ring oscillator; and
generate the second set of N phase signals based on the second set of M phase signals.