Patent ID: 11869895
Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 1:
2. A display panel, comprising:
a glass substrate;
an insulating layer formed on the glass substrate;
a polysilicon layer formed on the insulating layer;
a gate insulating layer formed on the polysilicon layer;
a gate layer formed on the gate insulating layer;
an interlayer insulating layer formed on the gate layer;
a source-drain contacting layer formed on the interlayer insulating layer; and
a light shielding layer formed on the glass substrate;
wherein the insulating layer covers the light shielding layer, the light shielding layer comprises a first light shielding portion and a second light shielding portion, and the first light shielding portion and the second light shielding portion are spaced apart from each other and disposed on the glass substrate;
wherein the polysilicon layer is defined with a first doped region, a second doped region, and a third doped region; the source-drain contacting layer contacts the first doped region and the third doped region;
wherein a doping type of the first doped region and a doping type of the third doped region are different so that the first doped region and the third doped region form a PN structure located above the first light shielding portion;
wherein the doping type of the first doped region and a doping type of the second doped region are same;
wherein a projection of the third doped region projected on the glass substrate overlaps a projection of the first light shielding portion of the light shielding layer projected on the glass substrate, and a projection of the second light shielding portion of the light shielding layer projected on the glass substrate overlaps a projection of the second doped region projected on the glass substrate;
wherein the first doped region is formed with two N-type heavily doped regions configured to be an N+-type layer, and the third doped region is formed with a P-type doped region configured to be a P-type layer;
wherein the polysilicon layer is further defined with a non-doped region;
wherein the second doped region is formed with two N-type lightly doped regions, and the N-type lightly doped regions are located two opposite sides of the non-doped region, respectively;
wherein the two N-type lightly doped regions of the second doped region are located at two opposite sides of the non-doped region; and
wherein each of the two N-type heavily doped regions of the first doped region is adjacent to a side of a corresponding one of the two N-type lightly doped regions of the second doped region away from the non-doped region, and the third doped region is overlapped on one of the N-type heavily doped regions of the first doped region.