Patent ID: 11934863
Assignee: MARVELL ASIA PTE LTD
Field: nan (nan)
Classification: CPC nan | IPC G

Claim 0:
1. A system, comprising:
an array-based inference engine comprising a plurality of processing tiles, wherein each processing tile comprises at least one or more of
an on-chip memory (OCM) configured to load and maintain data for local access by components in the processing tile;
one or more processing units configured to perform one or more computation tasks of an operation on data in the OCM by executing a set of task instructions; and

an instruction engine configured to
distribute said set of task instructions to corresponding processing tiles of the inference engine to control operations of the corresponding processing tiles via a tile mask having an indicator associated therewith, wherein the tile mask indicates which processing tiles the instructions should be delivered to;
synchronize said set of task instructions to be executed by each processing tile of the plurality of processing tiles, respectively, to wait current task at each processing tile to finish before changing the indicator to a different indicator and distributing a new set of task instructions based on the different indicator.