Patent ID: 11914938
Assignee: MURATA MANUFACTURING CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 1:
2. The simulation method of the multilayer capacitor according to claim 1, wherein
the simulation model of the multilayer capacitor further includes a plate-shaped third internal electrode model between the third input/output port and the fourth input/output port, and a plate-shaped fourth internal electrode model between the third input/output port and the fourth input/output port;
a capacitance, an equivalent series resistance, and an equivalent series inductance obtained from an actually measured value of an impedance characteristic of the multilayer capacitor are set for the third internal electrode model, and the fourth internal electrode model;
the third internal electrode model faces the two side surfaces of the multilayer capacitor;
the fourth internal electrode model faces the two main surfaces of the multilayer capacitor;
the first internal electrode model is adjacent to or in a vicinity of one side surface among the two side surfaces, and the third internal electrode model is adjacent to or in a vicinity of another side surface among the two side surfaces;
the second internal electrode model is adjacent to or in a vicinity of one main surface among the two main surfaces, and the fourth internal electrode model is adjacent to or in a vicinity of another main surface among the two main surfaces; and
the providing further includes providing the simulation model of the multilayer capacitor adjacent to the simulation model of the multilayer inductor, and the first internal electrode model and the third internal electrode model, or the second internal electrode model and the fourth internal electrode model intersect a magnetic field from the simulation model of the multilayer inductor.