Patent ID: 11888498
Assignee: ANALOG DEVICES INTERNATIONAL UNLIMITED COMPANY
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A successive approximation registers (SAR) analog-to-digital converter (ADC) comprising:
an analog input to receive an analog input voltage;
sample-and-hold circuitry coupled to the analog input;
a digital-to-analog converter (DAC);
a comparator coupled to an output of the sample-and-hold circuitry and an output of the DAC; and
SAR logic circuitry comprising:
a shift register;
a first digital path comprising:
first detection circuitry to receive one of a first positive output or a first negative output of the comparator, an output of the shift register, and a first digital feedback associated with a second digital path; and
latching circuitry coupled to an output of the first detection circuitry;

the second digital path comprising:
second detection circuitry to receive the other one of the first positive output or the first negative output of the comparator, the output of the shift register, and a second digital feedback associated with the first digital path, wherein the second digital feedback corresponds to an output downstream of the latching circuitry; and

wherein:
the first positive output and the first negative output of the comparator are associated with a current bit trial; and
at least one of a second positive output or a second negative output of the comparator are associated with a previous bit trial.