Patent ID: 11961902
Assignee: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A method for manufacturing a semiconductor device, comprising:
forming a semiconductor heterostructure layer, comprising alternatively forming first semiconductor material layers and second semiconductor material layers, wherein a two-dimensional electron gas (2DEG) can be generated between each first semiconductor material layer and its adjacent second semiconductor material layer; and
patterning a surface of the semiconductor heterostructure layer to form a plurality of openings in a first direction substantially parallel to the surface of the semiconductor heterostructure layer; and
etching the semiconductor heterostructure layer from the plurality of openings so as to form a plurality of trenches in the semiconductor heterostructure layer, wherein depths of the plurality of trenches progressively increase in the first direction, the etching stops in different second semiconductor material layers, and a bottom of each trench is not in contact with the 2DEG;
depositing a conductive material in the plurality of trenches so as to form a conductive structure; and
performing annealing at an annealing temperature;
wherein cross areas of the plurality of openings progressively increase in the first direction.