Patent ID: 11972790
Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 6:
7. A semiconductor device comprising:
a first transistor comprising silicon in a channel formation region;
a first insulating layer over the channel formation region of the first transistor;
a first gate electrode of the first transistor over the first insulating layer;
a plurality of second transistors over the first transistor, the plurality of second transistors overlapping each other in a cross-sectional view;
a plurality of third transistors over the first transistor, two transistors of the plurality of third transistors being arranged adjacent to each other in a top view; and
a plurality of fourth transistors over the first transistor, the plurality of fourth transistors overlapping each other in the cross-sectional view,
wherein one of the plurality of the second transistors and one of the plurality of third transistors are provided adjacent to each other,
wherein one of a source electrode and a drain electrode of a fifth transistor of the plurality of second transistors is electrically connected to one of a source electrode and a drain electrode of the first transistor,
wherein a first conductor extending in a first direction perpendicular to a top surface of a substrate is configured to be electrically connected to the one of the source electrode and the drain electrode of the fifth transistor of the plurality of second transistors and one of a source electrode and a drain electrode of a sixth transistor of the plurality of second transistors, and
wherein the other of the source electrode and the drain electrode of the fifth transistor of the plurality of second transistors, a first electrode of a capacitor, and a gate electrode of a seventh transistor of the plurality of fourth transistors are electrically connected to each other.