Patent ID: 11973050
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A method for forming an integrated chip, the method comprising:
forming an interconnect structure over a semiconductor substrate, wherein the interconnect structure comprises a conductive wire;
forming an upper dielectric structure on the interconnect structure;
depositing a first conductive layer on the upper dielectric structure and a dielectric layer on the first conductive layer; and
forming a second conductive layer on the dielectric layer, wherein the second conductive layer comprises a middle conductive segment extending through the first conductive layer, the dielectric layer, and the upper dielectric structure to contact the conductive wire, wherein the middle conductive segment comprises a first sidewall that directly contacts an inner sidewall of the first conductive layer and an inner sidewall of the dielectric layer, wherein the inner sidewall of the first conductive layer is aligned with the inner sidewall of the dielectric layer.