Patent ID: 11868650
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A memory system, comprising:
a memory device including:
a first memory chip having a first set of performance measures that include at least a first type and a second type;
a second memory chip having a second set of performance measures that include the first and second types, wherein
the second memory chip is configured to increase the second type of performance measure in comparison to the first memory chip, and
the first memory chip is configured to increase the first type of performance measure in comparison to the second memory chip;

a shared interface connecting the first and second memory chips, wherein the shared interface provides a common input, a common output, or both for the first and second memory chips; and

a memory controller electrically coupled to the shared interface of the memory device, the memory controller configured to:
generate a Chip Select (CS) signal based on a Quality of Service (QoS) indicator provided by a host device, wherein the CS signal is for selecting either the first memory chip or the second memory chip to process a read operation or a write operation commanded by the host device.