Patent ID: 11862267
Assignee: NETLIST, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A method, comprising:
at a memory module operable in a computer system including a system memory controller coupled to a system memory bus having a bit width N, the memory module including: a printed circuit board (PCB) including a connector that fits into a corresponding slot connector of the computer system whereby the memory module is operatively coupled to the system memory controller of the computer system via the system memory bus; memory devices mounted on the PCB and organized in one or more N-bit-wide ranks, where N is a positive integer, the memory devices having address and control ports and data ports; a data module coupled to the data ports of the memory devices and to the connector, the data module including a plurality of data handlers in respective physically separate integrated circuit packages mounted on respective portions of the PCB and coupled to respective n-bit-wide segments of the memory devices, where n is a positive integer smaller than N; and a control circuit mounted on the PCB and coupled to the connector, the data module, and address and control ports of the memory devices;
performing normal memory read or write operations, including: receiving, at the control circuit, system address and control signals from the system memory controller via the connector; outputting, from the control circuit, registered memory address and control signals for the normal memory read or write operation; propagating, by each respective data handler of the data module, respective read data signals or respective write data signals associated with the normal memory read or write operation between a respective n-bit-wide segment of the memory devices and a respective n-bit-wide segment of the system memory bus; and
outputting or receiving, by at least one memory device in the respective n-bit-wide segment of the memory devices, the respective read data signals or the respective write data signals in response to the registered memory address and control signals; and
performing testing operations, including: outputting, from the control circuit, test address and control signals; isolating, at the each respective data handler of the data module, respective data paths from the memory controller to the respective n-bit-wide segment of the memory devices; outputting, from the each respective data handler of the data module, respective test data signals to the respective segment of the memory devices based on information received from the control circuit; receiving, by one or more memory devices in the respective segment of the memory devices, test data included in the respective test data signals in response to the test address and control signals from the control circuit.