Patent ID: 11881244
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. An operating method of a semiconductor memory apparatus, the operating method comprising:
detecting row hammering on a plurality of word lines;
detecting a row hammering address that corresponds to a word line, among the plurality of word lines, in which the row hammering has occurred;
generating a first refresh target address and a second refresh target address corresponding to word lines adjacent to the word line in which the row hammering has occurred by performing operations on the row hammering address;
performing a first addition operation on the first refresh target address and the second refresh target address and a second addition operation on the row hammering address and the row hammering address; and
determining whether the refresh target address has been correctly generated by comparing results of the first addition operation with the second addition operation.