Patent ID: 11881266
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A memory apparatus, comprising:
memory cells connected to one of a plurality of word lines and disposed in memory holes organized in rows grouped in a plurality of strings and configured to retain a threshold voltage corresponding to one of a plurality of data states, the rows include full circle rows and semi-circle rows, wherein the memory holes of the semi-circle rows are partially cut by a slit half etch, the memory holes of the semi-circle rows each coupled to one of a plurality of semi-circle bit lines and the memory holes of the full circle rows each coupled to one of a plurality of full circle bit lines; and
a control means coupled to the plurality of word lines, the plurality of semi-circle bit lines, and the plurality of full circle bit lines, wherein the control means is configured to:
erase the memory cells in an erase operation, and
during the erase operation, create a capacitive coupling between each of the plurality of semi-circle bit lines and at least one neighboring one of the plurality of full circle bit lines adjacent to each of the plurality of semi- circle bit lines to increase a semi-circle erase voltage applied to each of the plurality of semi-circle bit lines.