Patent ID: 11963299
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 2:
3. The CA buffer device of claim 1, further comprising:
a first flip-flop coupled to the first terminal;
a second flip-flop coupled to an output of the first flip-flop, wherein an output of the second flip-flop is coupled to the first set of one or more of the plurality of device sites;
an input buffer coupled to the second terminal; and
a third flip-flop coupled to an output of the input buffer, wherein an output of the third flip-flop is coupled to the second set of one or more of the plurality of device sites, wherein the first flip-flop, second flip-flop, and third flip-flop are clocked by a timing signal.