Patent ID: 11935941
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor structure, comprising:
a substrate having a first surface;
a conductive region in the substrate;
a first insulation layer over the first surface;
a second insulation layer over the first insulation layer;
a gate structure over the first surface of the substrate and surrounded by the first insulation layer;
a low-k spacer between a sidewall of the gate structure and an etch stop layer, the etch stop layer between the low-k spacer and the first insulation layer, wherein the low-k spacer has a first dielectric constant, the etch stop layer has a second dielectric constant, and the first insulation layer has a third dielectric constant, wherein the first dielectric constant is smaller than the second dielectric constant and the third dielectric constant, wherein the low-k spacer comprises SiOCN and has a concentration of silicon (Si) in the SiOCN is between about 25% and 35%, wherein a concentration of oxygen (O) in the SiOCN is between about 4% and 6%, wherein a concentration of carbon (C) in the SiOCN is between about 35% and 45%, and wherein a concentration of nitrogen (N) is in the range from about 15% to about 25%;
a gate contact landed on a top surface of the gate structure; and
a conductive region contact over the conductive region and surrounded by the first insulation layer and the second insulation layer, a top surface of the conductive region contact being leveled with a top surface of the second insulation layer;
wherein a proximity distance between a sidewall of the gate contact and the conductive region contact along the top surface of the second insulation layer is in a range of from about 4 nm to about 7 nm.