Patent ID: 11942376
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A method for manufacturing a semiconductor structure, comprising:
receiving a substrate including a first conductive region of a first transistor and a first gate structure, and a second conductive region and a second gate structure of a second transistor, wherein the first transistor and the second transistor have different conductive types;
removing a portion of a first spacer of the first gate structure and a portion of a second spacer of the second gate structure, thereby reducing a thickness of the first spacer on a vertical surface of the first gate structure and reducing a thickness of the second spacer on a vertical surface of the second gate structure;
depositing a liner layer covering the first spacer and the second spacer after the removal of the portion of the first spacer and the portion of the second spacer;
impacting a first substance over the first conductive region and the second conductive region;
implanting a second substance into the first conductive region;
depositing a third substance over the first conductive region and the second conductive region, wherein only the first substance is introduced into the second conductive region prior to the deposition of the third substance, and only the first substance and the second substance are introduced into the first conductive region prior to the deposition of the third substance; and
increasing crystalline densities of the first conductive region and the second conductive region by a laser anneal.