Patent ID: 11948628
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A method comprising:
individually setting resistances of a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell, wherein the first memory cell and the second memory cell are coupled to each other in series between a first line and a second line, and wherein the third memory cell and the fourth memory cell are coupled to each other in series between the second line and a third line, wherein the first to third select lines are in parallel with one another; and
reading a multi-level data stored by the first memory cell, the second memory cell, the third memory cell, and the fourth memory cell, according to a parallel resistance of i) a first series resistance of the first memory cell and the second memory cell, and ii) a second series resistance of the third memory cell and the fourth memory cell.