Patent ID: 11908545
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device for computing in memory (CIM), comprising:
a plurality of memory banks, each of the plurality of memory banks comprising:
a first memory array;
a first latch circuit, coupled to the first memory array, configured to latch a first data from the first memory array in a first read cycle;
a second latch circuit, coupled to the first memory array, configured to latch a second data from the first memory array in a second read cycle; and
a local multiply accumulate (MAC) circuit, coupled to the first latch circuit and the second latch circuit, configured to perform a first stage CIM operation on at least one of a first latched data latched in the first latch circuit and a second latched data latched in the second latch circuit to provide a first stage CIM result; and

a global MAC circuit, coupled to the plurality of memory banks, configured to perform a second stage CIM operation on a plurality of first stage CIM results from the plurality of memory banks.