Patent ID: 11972140
Assignee: APPLE INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 17:
18. A system comprising:
a plurality of memory controllers coupled to a plurality of memory devices of a memory system, wherein the plurality of memory controllers are logically divided into a plurality of subsets of memory controllers, and wherein each physical page of a plurality of physical pages is mapped to a given subset of the plurality of subsets;
one or more processors coupled to the plurality of memory controllers; and
a non-transitory computer readable storage medium storing a plurality of instructions which, when executed by the one or more processors, cause the system to perform operations comprising:
detecting that a first subset or the plurality of subsets of memory controllers are to be disabled based on detecting one or more factors in the system that indicate a reduction in power consumption; and
based on detecting that the first subset is to be disabled:
disabling, in a virtual memory page mapper, additional mappings of virtual pages to physical pages in the first subset;
monitoring existing virtual page to physical page mappings in the first subset;
remapping virtual pages having an access rate greater than a threshold during the monitoring to physical pages in other subsets of the plurality of subsets;
copying at least some data corresponding to the remapped virtual pages from the physical pages in the first subset to the physical pages in the other subsets; and
disabling the first subset.