Patent ID: 11887912
Assignee: SHANGHAI INTEGRATED CIRCUIT MANUVACTURING INNOVATION CENTER CO., LTD
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 5:
6. A through silicon via structure for three-dimensional integrated circuit packaging, comprising:
a through silicon via penetrating a substrate;
an insulating medium covering a sidewall of the through silicon via and upper and lower surfaces of the substrate;
a copper diffusion barrier layer and a seed layer, wherein the copper diffusion barrier layer covers a surface of the insulating medium on the sidewall of the through silicon via, and the seed layer covers a surface of the copper diffusion barrier layer;
conductive metal material and contact pads, wherein the conductive metal material completely fills the through silicon via, extends upward and downward, and protrudes from upper and lower surfaces of the insulating medium; and the contact pads are disposed on the top and bottom of the conductive metal material,
wherein the conductive metal material is in direct contact with the seed layer, and the conductive metal material is not in direct contact with the sacrificial layer;
wherein the insulating medium disposed on the sidewall of the through silicon via is covered by the copper diffusion barrier layer, the upper and lower surfaces of the insulating medium are not covered by the copper diffusion barrier layer, and the copper diffusion barrier layer disposed on the sidewall of the through silicon via is covered by the seed layer.