Patent ID: 11886727
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A method of controlling a nonvolatile memory including a plurality of dies operable in parallel or a plurality of planes operable in parallel, each of the plurality of dies or the plurality of planes including a plurality of blocks each of which is a unit for a data erase operation, the method comprising:
constructing, from the plurality of dies or the plurality of planes, a plurality of block groups each including a plurality of blocks; and
in response to receiving a write command for writing data to one block group among the plurality of block groups from a host, writing data associated with the received write command to the one block group, wherein
the plurality of block groups includes at least a first block group configured using a first type block group and a second block group configured using a second type block group, wherein
the first type block group includes a plurality of non-defective blocks obtained by selecting one or more non-defective blocks in an equal number from each of the plurality of dies or each of the plurality of planes, and wherein
the second type block group includes a plurality of non-defective blocks selected from part of the plurality of dies or part of the plurality of planes, the number of the non-defective blocks included in the second type block group being equal to the number of the non-defective blocks included in the first type block group, and the number of non-defective blocks per die or per plane included in the second type block group is different between a first die and a second die of the part of the plurality of dies or between a first plane and a second plane of the part of the plurality of planes.