Patent ID: 11869573
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 11:
12. The semiconductor memory of claim 1, wherein the voltage regulation unit comprises a first resistor, a second resistor, a PMOS transistor, and a mirror current source, wherein:
one end of the first resistor is coupled to one end of the second resistor and the other end of the first resistor is coupled to a drain of the PMOS transistor;
the other end of the second resistor is coupled to a ground;
a positive input end of the operational amplifier is coupled to an electrical connection point formed between the first resistor and the second resistor;
a negative input end of the operational amplifier is coupled to a reference voltage;
an output end of the operational amplifier is coupled to a gate of the PMOS transistor;
a supply end of the operational amplifier is coupled to the external input first voltage;
a first input end of the image current source is coupled to the external input first voltage;
a second input end of the mirror current source is coupled to the output end of the operational amplifier;
an output end of the mirror current source generates an output current to regulate a bias current of the operational amplifier;
a source of the PMOS transistor is coupled to the external input first voltage and
an electrical connection point formed between the drain of the PMOS transistor and the first resistor outputs the second voltage.