Patent ID: 11967973
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 17:
18. The decoder of claim 12, wherein a space of 2q values of the q-bit original values is divided into a plurality of groups, each group comprising 2r different consecutive q-bit original values,
wherein the first encoder value D1 and the second encoder value D2 share q−r most significant bits, and
wherein the processing circuit is configured to decode the first encoder value D1 and the second encoder value D2 from the key by:
reading an 2r−1 bit least significant bits code from the header;
decoding the least significant bits code to first least significant bits and second least significant bits;
reading q−r most significant bits from a portion of the header;
concatenating the q−r most significant bits with the first least significant bits to decode the first encoder value D1; and
concatenating the q−r most significant bits with the second least significant bits to decode the second encoder value D2.