Patent ID: 11864378
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 5:
6. A semiconductor device, comprising:
a semiconductor substrate, having active regions and trench isolation structures located between the active regions;
buried word line structures, located in the active regions, the buried word line structures comprise: gate oxide layers, gate block layers, gate conductive layers and insulating filling layers, the gate block layers being located on surfaces of the gate conductive layers, the insulating filling layers being located on the gate conductive layers and the gate block layers, and the gate oxide layers being located on surfaces of both the gate block layers and the insulating filling layers; and
inversion polysilicon layers, located on side faces of the buried word line structures and inversely doped with the active regions, upper surfaces of the inversion polysilicon layers are flush with upper surfaces of the gate oxide layers, a thickness of each of the inversion polysilicon layers is 5 nm to 25 nm, and a height of each of the inversion polysilicon layers is 20 nm to 150 nm.