Patent ID: 11862708
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A device comprising:
a semiconductor region;
a gate stack on the semiconductor region, wherein the gate stack comprises;
a gate dielectric; and
a metal-containing layer, wherein the gate dielectric comprises a first portion on a sidewall of the metal-containing layer, and a second portion overlapped by the metal-containing layer;

a laminate low-k liner on a first sidewall of the gate stack;
a gate spacer comprising a sub layer, wherein the sub layer comprises:
an inner sidewall in direct contact with the laminate low-k liner; and
an outer sidewall opposite to the inner sidewall, wherein a bottom end of the outer sidewall is in direct contact with the semiconductor region;

a source/drain region adjacent to the gate stack;
a source/drain contact plug over and electrically coupling to the source/drain region;
a high-k dielectric contact spacer encircling the source/drain contact plug; and
a source/drain silicide region between the source/drain region and the source/drain contact plug, wherein the high-k dielectric contact spacer extends lower than a top surface of the source/drain silicide region.