Patent ID: 11968911
Assignee: WINBOND ELECTRONICS CORP.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 1:
2. The method of claim 1, wherein the substrate comprises a magnetic random access memory (MRAM) region and a logic region, the method comprising:
forming a first inter-metal dielectric (IMD) layer on the substrate;
forming a first metal interconnection in the first IMD layer on the MRAM region;
forming the MTJ stack on the first IMD layer and the first metal interconnection;
forming the first SOT layer on the MTJ stack;
forming the first hard mask on first SOT layer;
forming a second hard mask on the first hard mask;
performing a first etching process to pattern the second hard mask for exposing the first hard mask; and
performing a second etching process to pattern the first hard mask, the first SOT layer, and the MTJ stack to form the MTJ on the first metal interconnection.