Patent ID: 11862619
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of making a multi-die patch, the method comprising:
forming a first patterned conductive layer defining multiple contact pads on a first carrier structure;
placing a first die on a first plurality of contact pads of the multiple contact pads;
placing a second die on a second plurality of contact pads of the multiple contact pads;
embedding the first die and the second die in a dielectric disposed on the first patterned conductive layer;
attaching a second carrier structure to the dielectric on a surface of the dielectric opposite the first carrier;
removing the first carrier structure;
forming routing traces, the routing traces configured to electrically couple the first and second die with one or more surface die;
forming first terminals connected with a first plurality of routing traces of the routing traces, the first terminals exposed at a first side of the dielectric, wherein the forming first terminals includes replacing at least a portion of the first patterned conductive layer with a second patterned conductive layer; and
forming second terminals connected with a second plurality of routing traces of the routing traces, the second terminals exposed at a second side of the dielectric, the second side opposite the first side.