Patent ID: 11915746
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. A memory device, comprising:
a memory array including a plurality of memory cells;
a word line (WL), connected to one of the plurality of memory cells, that is configured to provide a first WL pulse;
a first tracking WL, formed adjacent to the memory array, that is configured to provide, via a bit line (BL) configured to write a logic state to the memory cell, a second WL pulse;
a first tracking BL, coupled to the first tracking WL, that is configured to emulate the BL and increase a width of the first WL pulse based on the second WL pulse;
wherein a voltage of the first tracking BL is configured to transition to a low logic state in response to a rising edge of the second WL pulse, and wherein a falling edge of the first WL pulse occurs in response to the voltage of the tracking BL being dropped by a predefined voltage;
at least one tracking WL bit cell coupled to the first tracking WL;
wherein the tracking WL bit cell includes first and second transistors, respective gates of the first and second transistors connected to the first tracking WL, respective sources of the first and second transistors being floated, one of respective drains of the first and second transistors directly connected to the BL; and
wherein the first tracking WL and the at least one tracking WL bit cell are formed within the memory array.