Patent ID: 11901345
Assignee: SK HYNIX INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. The semiconductor package according to claim 2, wherein the first internal channel pad includes a plurality of first internal channel pads arranged along a first side surface of the first buffer chip facing the first memory chip,
wherein the first memory chip pad includes a plurality of first memory chip pads arranged along a first side surface of the first memory chip facing the first buffer chip,
wherein the first redistribution line includes a plurality of first redistribution lines connecting the plurality of first memory chip pads and the plurality of first internal channel pads, respectively,
wherein at least one of the plurality of first redistribution lines includes horizontal portions substantially parallel to the first side surface of the first buffer chip and the first side surface of the first memory chip, and
wherein, when a number of the horizontal portions disposed between the first internal channel pad and the first memory chip pad is N, where N is a natural number equal to or greater than 2, a width of the first redistribution line is W1, and a distance between adjacent horizontal portions is S1, a distance between the first internal channel pad and the first memory chip pad has a value greater than N*W1+(N+1)*S1.