Patent ID: 11917803
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 0:
1. A method, comprising:
receiving a workpiece comprising:
a substrate having a first area and a second area, and
a stack disposed on the substrate, the stack comprising a plurality of channel layers interleaved by a plurality of sacrificial layers,

forming, over the first area, a first fin structure from the stack and a first portion of the substrate and, over the second area, a second fin structure from the stack and a second portion of the substrate, wherein the first fin structure has a channel region and a source/drain region and the second fin structure has a channel region and a source/drain region;
forming a first dummy gate stack over the channel region of the first fin structure and a second dummy gate stack over the channel region of the second fin structure;
forming a first source/drain recess over the source/drain region of the first fin structure and a second source/drain recess over the source/drain region of the second fin structure;
forming a first source/drain feature in the first source/drain recess and a second source/drain feature in the second source/drain recess;
after the forming of the first source/drain feature and the second source/drain feature, depositing a contact etch stop layer and a dielectric layer over the first source/drain feature and the second source/drain feature;
removing the first dummy gate stack and the second dummy gate stack;
after the removing, forming a first mask layer over the second area;
with the first mask layer covering the second area, selectively removing the plurality of sacrificial layers in the channel region of the first fin structure to release the plurality of channel layers in the channel region of the first fin structure as channel members;
removing the first mask layer from over the second area; and
forming a first gate structure to wrap around each of the channel members and a second gate structure over the channel region of the first fin structure.