Patent ID: 11967380
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 12:
13. The semiconductor memory device according to claim 3, wherein
the first memory cell array further includes:
a fifth memory cell coupled to the first word line;
a fifth selection transistor coupled to the first selection gate line;
a fifth semiconductor extending in the first direction, and coupled to the fifth memory cell and the fifth Selection transistor;
a first interconnect layer included in the first word line and coupled to the first memory cell and the fifth memory cell;
a contact plug coupled to the first interconnect Layer;
a first region in which the first memory cell provided;
a second region in which the contact plug provided; and
a third region in which the fifth memory cell is provided, and

the second region is arranged between the first region and the third region.