Patent ID: 11880590
Assignee: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A system comprising:
a heterogeneous memory system comprising a memory module and a high bandwidth memory (HBM), the HBM including a processing-in-memory (PIM) circuit and configured to store data;
a host processor configured to:
execute arithmetic operations of the system, and
allocate one or more of the arithmetic operations to the PIM circuit to be executed by the PIM circuit; and

a memory controller configured to detect a data array from the memory module or the HBM based on a border index value,
wherein the border index indicates a criterion to determine which memory, among the memory module and the HBM, stores the data array required for the one or more of the arithmetic operations, based on the one or more of the arithmetic operations corresponding to a kernel offloaded by the host processor being performed in the PIM circuit of the HBM.