Patent ID: 11925032
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 18:
19. The method of claim 18, wherein the forming of the memory cell comprises:
forming a bottom electrode material layer on the dielectric layer;
forming the memory element on the bottom electrode material layer;
forming the sidewall spacer on the sidewall of the memory element;
forming an etch stop layer on the sidewall spacer and the bottom electrode material layer;
removing a first portion of the etch stop layer to expose a portion of the bottom electrode material layer; and
etching the exposed portion of the bottom electrode material layer to form the bottom electrode of the memory cell, such that the peripheral portion of the bottom electrode extends beyond the sidewall spacer and the etch stop layer contacts an upper surface of the bottom electrode at the peripheral portion of the bottom electrode.