Patent ID: 11948832
Assignee: APPLIED MATERIALS, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 8:
9. A method of manufacturing a semiconductor device, comprising:
providing a semiconductor substrate, the semiconductor substrate comprising a positively doped region and a negatively doped region and a lattice layer disposed on a top surface of the semiconductor substrate;
etching the lattice layer to form a trench in the lattice layer exposing the top surface of the semiconductor substrate at a bottom of the trench;
depositing an oxide liner on sidewalls and the bottom of the trench;
etching away the oxide liner on the bottom of the trench;
removing a portion of the semiconductor substrate below the trench to form an airgap in the semiconductor substrate;
coating inner walls of the airgap and filling the trench with a dielectric, wherein the dielectric is formed over the oxide liner on the sidewalls of the trench; and
removing the lattice layer and forming an upper semiconductor device structure on the top surface of the semiconductor substrate.