Patent ID: 11875838
Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A memory device comprising:
a first layer and a second layer,
wherein the second layer is positioned above the first layer,
wherein the first layer comprises a reading circuit,
wherein the second layer comprises a first memory cell and a second memory cell,
wherein a transistor included in the reading circuit comprises silicon in a channel formation region,
wherein a transistor included in the first memory cell and a transistor included in the second memory cell each comprise a metal oxide in a channel formation region,
wherein the first memory cell is electrically connected to the reading circuit through a first wiring,
wherein the second memory cell is electrically connected to the reading circuit through a second wiring, and
wherein when a first current corresponding to first data retained in the first memory cell flows from the reading circuit to the first memory cell and a second current corresponding to second data retained in the second memory cell flows from the reading circuit to the second memory cell, the reading circuit is configured to read the first data in accordance with an amount relationship between the first current and the second current.