Patent ID: 11948995
Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A capacitor comprising:
a silicon substrate having a principal surface including a capacitance generation region and a non-capacitance generation region, the silicon substrate including a porous part provided in a thickness direction in the capacitance generation region;
a conductor layer including:
a surface layer part at least covering part of a surface of the capacitance generation region and
a filling part filled in at least part of the porous part; and

a dielectric layer provided between an inner surface of the porous part and the filling part,
the porous part including:
a macroporous part having macro pores, and
a nanoporous part formed in at least part of inner surfaces of the macro pores and having nano pores smaller than the macro pores,

the nanoporous part being on an entirety of the inner surfaces of the macro pores.