Patent ID: 11915946
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. A semiconductor device comprising:
semiconductor nanostructures over a substrate, the semiconductor nanostructures extending between a first source/drain region and a second source/drain region, wherein the first source/drain region and the second source/drain region extend into the substrate, the semiconductor nanostructures comprising:
a first semiconductor nanostructure at a first distance from the substrate;
a second semiconductor nanostructure at a second distance from the substrate, wherein the second distance is greater than the first distance; and
a third semiconductor nanostructure at a third distance from the substrate, wherein the third distance is greater than the second distance, wherein thicknesses of the semiconductor nanostructures progressively increase as separation distances between the substrate and the semiconductor nanostructures increase, and a difference in thickness between one nanostructure and an adjacent nanostructure is in a range from 0.5 nm to 3 nm;

gate dielectric layers encircling the semiconductor nanostructures along longitudinal axes of the semiconductor nanostructures, wherein a bottom surface of the first source/drain region is below an interface between the gate dielectric layers and the substrate; and
a gate electrode encircling the semiconductor nanostructures along the longitudinal axes of the semiconductor nanostructures, wherein the gate dielectric layers separate the gate electrode from the semiconductor nanostructures, wherein a first portion of the gate electrode and a second portion of the gate electrode is separated by the third nanostructure, wherein a first spacer extends along a first sidewall of the first portion of the gate electrode, wherein a first gate dielectric layer of the gate dielectric layers extends between the first spacer and the first portion of the gate electrode, wherein a second spacer extends along a first sidewall of the second portion of the gate electrode, wherein a second gate dielectric layer of the gate dielectric layers extends between the second spacer and the second portion of the gate electrode, and wherein the first spacer and the second spacer comprise different materials.