Patent ID: 11908921
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 0:
1. A structure, comprising:
a substrate:
a pair of source/drain (S/D) epitaxial structures formed on the substrate;
nanostructure elements between the pair of S/D epitaxial structures, wherein the nanostructure elements are separated from each other by layers of a gate structure and by spacer structures interposed between the layers of the gate structure and each S/D epitaxial structure of the pair of S/D epitaxial structures, and wherein each of the spacer structures comprises an air gaps; and
an etch stop layer on top surfaces of the nanostructure elements, wherein the etch stop layer is between the nanostructure elements and the gate structure.