Patent ID: 11899944
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. An apparatus, comprising:
a non-volatile memory comprising one or more clocks, one or more command and address buffers, and one or more memory banks;
a volatile memory configured to operate as a cache for the non-volatile memory; and
an interface controller coupled with the non-volatile memory and the volatile memory, the interface controller operable to cause the apparatus to:
receive, from a host device, a command indicating that the apparatus is to transition from a power state in which the apparatus operates the volatile memory in a power mode for the volatile memory and the non-volatile memory in a power mode for the non-volatile memory;
transition, based at least in part on the command, the volatile memory from the power mode for the volatile memory to an idle power mode for the volatile memory; and
transition, based at least in part on the command, the non-volatile memory from the power mode for the non-volatile memory to an idle power mode for the non-volatile memory, wherein the transition is delayed until after receipt of an access command, from the host device, associated with data stored in the non-volatile memory instead of the volatile memory, wherein the one or more clocks and the one or more command and address buffers are powered up in the idle power mode and the one or more memory banks are powered down in the idle power mode.