Patent ID: 11908866
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 1:
2. The method of claim 1, wherein the forming the p-type work function layer in the gate trench over the gate dielectric layer in the first transistor region, the second transistor region, and the boundary region includes:
depositing a first p-type work function layer over the gate dielectric layer in the first transistor region, the second transistor region, and the boundary region;
removing the first p-type work function layer from the first transistor region;
depositing a second p-type work function layer over the gate dielectric layer in the first transistor region, the first p-type work function layer in the second transistor region, and the first p-type work function layer in the boundary region;
removing the second p-type work function layer from the first transistor region and the second transistor region; and
depositing a third p-type work function layer over the gate dielectric layer in the first transistor region, the first p-type work function layer in the second transistor region, and the second p-type work function layer in the boundary region.