Patent ID: 11922025
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. An apparatus, comprising:
a memory device comprising a plurality of memory dice; and
a controller couplable to the memory device, wherein the controller is configured to:
receive a memory access command from a host and determine that a criteria involving the plurality of memory dice is met, wherein the criteria includes a number of program-erase cycles (PECs) for at least one memory die of the plurality of memory dice of the memory device is above a threshold quantity;
write test data to the at least one memory die in response to the determination that the criteria is met;
read, after a threshold period of time has elapsed, the test data from the at least one memory die; and
compare the test data read from the at least one memory die to the test data written to the at least one memory die to determine whether the at least one memory die has experienced degradation; and
responsive to determine at the at least one memory die has experienced degradation, refraining from fulfilling the memory access command to read data written to the at least one memory die that has experienced the degradation, performing a recovery operation for user data on the at least one memory die requested by the memory access command, and transfer the recovered user data to a host to fulfill the memory access command.