Patent ID: 11961572
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 3:
4. The memory apparatus as set forth in claim 3, wherein the rows include full circle rows and semi-circle rows comprising memory holes forming the strings being partially cut by the shallow hole etch extending vertically into the stack, and wherein the controller is further configured to:
apply each of a plurality of program pulses to the plurality of other data word lines progressively increasing in magnitude in each of a plurality of loops during the program operation until the memory cells being programmed to the highest data state and associated with the full circle rows reach a first highest verify voltage level for the highest data state;
apply each of the plurality of program pulses to the at least one edge word line progressively increasing in magnitude in each of the plurality of loops during the program operation until the memory cells being programmed to the highest data state associated with the semi-circle rows and the at least one edge word line reach a second highest verify voltage level for the highest data state, the second highest verify voltage level being higher than the first highest verify voltage level; and
simultaneously apply an inhibiting bit line voltage to ones of the plurality of bit lines coupled to the strings of the full circle rows while programming the memory cells associated with the at least one edge word line to discourage programming of the memory cells in the strings associated with the full circle rows while applying a select bit line voltage to ones of the plurality of bit lines coupled to the strings of the semi-circle rows while programming the memory cells associated with the at least one edge word line to encourage programming of the memory cells in the strings associated with the semi-circle rows.