Patent ID: 11922031
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. An apparatus, comprising:
a memory array including a plurality of memory cells configured to store data;
a command decoder coupled to the memory array and configured to process an externally-provided command corresponding to a precharging operation and includes an indication for a commanded refresh operation, both operations associated with a target address, wherein the command decoder process the command by (1) initiating the precharging operation and (2) passing an internal capture command with the target address for downstream processing; and
a refresh control circuit coupled to and between the memory array and the command decoder, the refresh control circuit configured to:
receive the internal capture command;
identify whether a memory bank associated with the target address is in an opened state or a closed state; and
controlling propagation of the internal capture command based on the opened or closed state of the memory bank, wherein propagation of the internal capture command corresponds to storing the target address for use during subsequent implementation of the commanded refresh operation.