Patent ID: 11901318
Assignee: WINBOND ELECTRONICS CORP.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A method for forming an integrated circuit structure, comprising:
providing a substrate comprising thereon a logic core circuit region and an embedded memory area;
forming a copper interconnect structure on the substrate, wherein the copper interconnect structure comprises an uppermost copper layer covered by a dielectric layer;
forming an aluminum shield layer comprising concentric aluminum routing patterns on the uppermost copper layer in the embedded memory area; and
forming an aluminum pad layer on the dielectric layer, wherein the aluminum shield layer has a thickness that is thinner than that of the aluminum pad layer, wherein the aluminum pad layer comprises a first pad pattern within the logic core circuit region and a second pad pattern within the embedded memory area; and
forming a passivation layer covering the first pad pattern within the logic core circuit region and the second pad pattern within the embedded memory area.