Patent ID: 11971821
Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. The computing system as claimed in claim 16, wherein:
the first core and the second core each include one level 1 cache to implement the first in-core cache module and the second in-core cache module;
the first processor includes a level 2 cache which is shared by the first core and the second core;
the first last-level cache is a level 3 cache;
the write-back and invalidation request is transferred from the level 1 cache of the first core to the level 2 cache shared by the first core and the second core, and then passed to the level 3 cache by the level 2 cache;
the level 3 cache provides the first synchronization signal to the level 2 cache shared by the first core and the second core;
in response to the first synchronization signal, the level 2 cache in the waiting state is awakened to search itself to determine which cache lines within the level 2 cache match the designated key identification code, wherein: if a matched cache line has been modified and does not exist in any upper-level cache, the level 2 cache writes back the matched cache line to the system memory; and, whether modified or not, all matched cache lines within the level 2 cache are invalidated;
after all matched cache lines within the level 2 cache are invalidated, the level cache returns a second synchronization signal to the level 1 cache of the first core and the level 1 cache of the second core; and
in response to the second synchronization signal, the level 1 cache of the first core in the waiting state is awakened to search itself to determine which cache lines within the level 1 cache of the first core match the designated key identification code, wherein: if a matched cache line has been modified, the level 1 cache of the first core writes back the matched cache line to the system memory; and, whether modified or not, all matched cache lines within the level 1 cache of the first core are invalidated; and
in response to the second synchronization signal, the level 1 cache of the second core in the waiting state is awakened to search itself to determine which cache lines within the level 1 cache of the second core match the designated key identification code, wherein: if a matched cache line has been modified, the level 1 cache of the second core writes back the matched cache line to the system memory; and, whether modified or not, all matched cache lines within the level 1 cache of the second core are invalidated.