Patent ID: 11894101
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. The sense amplifier of claim 7, wherein the control circuit comprises:
a first delay circuit, wherein an input end of the first delay circuit is connected to the column selection line, an output end of the first time-day circuit is connected to a control end of the eleventh transistor, and the first delay circuit is configured to obtain a first control signal for controlling the eleventh transistor after performing a delay process on a column selection signal;
a second delay circuit, wherein an input end of the second delay circuit is connected to the column selection line, an output end of the second delay circuit is connected to a control end of the twelfth transistor, and the second delay circuit is configured to obtain a second control signal for controlling the twelfth transistor after performing the delay process on the column selection signal; and
a delay time of the first delay circuit is less than a delay time of the second delay circuit.