Patent ID: 11973108
Assignee: RENAULT S.A.S.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A method of manufacturing a semiconductor device comprising:
a step of selectivity forming on a main surface of a substrate, a first-conductivity-type drift region that has a higher impurity concentration than the substrate;
a step of forming a second-conductivity-type first well region above the main surface in a remaining region of the main surface other than a region in which the drift region is arranged, such that the first well region is connected to the drift region;
a step of forming a second-conductivity-type second well region having a higher impurity concentration than the first well region in the remaining region in such a way as to face the drift region, the second well region being adjacent to the first well region;
a step of forming a first-conductivity-type source region that is connected to the first well region and the second well region in such a way as to face the drift region via the first well region;
a step of forming a first-conductivity-type drain region that is connected to the drift region at a position separated from the first well region and the second well region;
a step of forming a gate insulating film on surfaces of the drift region, the first well region, and the source region; and
a step of forming a gate electrode that faces the drift region, the first well region, and the source region via the gate insulating film, wherein
a distance between the source region and the drift region is greater than a distance between the second well region and the drift region, in a direction parallel to the main surface of the substrate, and
a depletion layer extending from the second well region reaches the drift region.