Patent ID: 11948639
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A method used in forming a memory array comprising strings of memory cells, comprising:
forming a stack comprising vertically-alternating first tiers and second tiers comprising laterally-spaced memory-block regions having horizontally-elongated trenches there-between, two of the first tiers having different vertical thicknesses relative one another, channel-material strings of memory cells extending through the first tiers and the second tiers;
through the horizontally-elongated trenches, forming first conductive material in void space in the two first tiers, the first conductive material filling the first tier of the two first tiers that has a smaller of the different vertical thicknesses in individual of the memory-block regions, the first conductive material less-than-filling the first tier of the two first tiers that has a larger of the different vertical thicknesses in the individual memory-block regions;
through the horizontally-elongated trenches, isotropically etching the first conductive material from the first tier having the larger vertical thickness in the individual memory-block regions to leave the first conductive material in the first tier having the smaller vertical thickness in the individual memory-block regions; and
after the isotropically etching of the first conductive material and through the horizontally-elongated trenches, forming second conductive material in the first tier having the larger vertical thickness in the individual memory-block regions.