Patent ID: 11908511
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 0:
1. A semiconductor memory device comprising:
a memory string that includes a plurality of memory transistors connected in series;
a plurality of first wirings connected to gate electrodes of the plurality of memory transistors;
a plurality of second wirings electrically connected to the plurality of first wirings;
a plurality of transistors electrically connected between the plurality of first wirings and the plurality of second wirings; and
a third wiring connected to gate electrodes of the plurality of transistors in common, wherein
a first read operation is executed in response to an input of a first command set,
a second read operation is executed in response to an input of a second command set,
a first voltage that turns the plurality of transistors ON is applied to the third wiring from an end of the first read operation to a start of the second read operation,
a third voltage is applied to the plurality of second wirings from the end of the first read operation to the start of the second read operation,
a fourth voltage is applied to the plurality of second wirings after the second read operation ends, and
the third voltage is larger than the fourth voltage.