Patent ID: 11880308
Assignee: APPLE INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. An apparatus comprising:
a tag array circuit configured to store tags corresponding to cache lines arranged in a plurality of ways of a cache memory circuit;
a prediction circuit configured to, in response to a request for access to the tag array circuit, generate a prediction of a particular one of the plurality of ways includes a particular cache line associated with the request; and
a comparison circuit configured to verify the prediction based on a comparison of a first tag associated with the particular cache line and a second tag associated with the particular one of the plurality of ways;
wherein the prediction circuit is further configured to store a confirmation bit indicating that the prediction was correct in response to the comparison indicating a match of the first tag and the second tag; and
wherein, based on the confirmation bit, the comparison circuit is configured to, for a subsequent request for access to the particular cache line, indicate a match of the first tag and the second tag without reading the tag array circuit and without performing the comparison.