Patent ID: 11935749
Assignee: NANYA TECHNOLOGY CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of manufacturing a semiconductor structure, comprising:
forming a first patterned layer over a substrate;
forming a second patterned layer over the substrate and alternately arranged with the first patterned layer;
performing an etching, thereby forming an arched surface of the first patterned layer and an arched surface of the second patterned layer;
forming a sacrificial layer over the first patterned layer and the second patterned layer, wherein a plurality of air gaps are defined by the substrate, the first patterned layer, the second patterned layer and the sacrificial layer;
removing the sacrificial layer above the plurality of air gaps, thereby forming a planar top surface of the first patterned layer and a planar top surface of the second patterned layer; and
patterning the substrate using the first patterned layer and the second patterned layer as a mask.