Patent ID: 11894300
Assignee: SK HYNIX INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A semiconductor memory device, comprising:
a source structure;
a stacked conductive layer overlapping with the source structure;
a first select conductive layer and a second select conductive layer disposed between the source structure and the stacked conductive layer;
a stacked insulating layer disposed between the first select conductive layer and the stacked conductive layer and between the second select conductive layer and the stacked conductive layer; and
a separation insulating structure passing through the source structure,
wherein the separation insulating structure is disposed between the first and second select conductive layers, and
wherein the stacked conductive layer comprises a first conductive extension that overlaps with the first select conductive layer, a second conductive extension that overlaps with the second select conductive layer, and a conductive connector that overlaps with the separation insulating structure.