Patent ID: 11972829
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A semiconductor apparatus comprising:
a cell array region including normal word lines, redundant word lines, normal bit lines and redundant bit lines; and
a first repair circuit configured to selectively activate the redundant bit lines by comparing first repair information and first address information,
wherein each of the redundant bit lines is divided into at least two parts which are selectively activated,
wherein the first repair circuit is configured to repair a first failed cell with a part of the each of the redundant bit lines when a specific bit of the first address information has a first value and repair a second failed cell with another part of the each of the redundant bit lines when the specific bit of the first address information has a second value, and wherein the first repair circuit comprises:
a plurality of unit repair circuits configured to generate a column redundant control signal by comparing a most significant bit of a row address, a next significant bit of the row address and a column address with the first repair information;
an OR logic configured to perform an OR logic function on the column redundant control signal and output an output; and
a switching circuit configured to block the first address information from being supplied to the column main decoder, depending on the output of the OR logic.