Patent ID: 11942132
Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G  H

Claim 0:
1. A semiconductor device comprising:
a processor; and
a memory circuit comprising a first memory cell array and a second memory cell array,
wherein the first memory cell array comprises a plurality of first memory cells arranged in a matrix,
wherein each of the plurality of first memory cells comprises a first transistor and a first capacitor electrically connected to the first transistor,
wherein the second memory cell array comprises a plurality of second memory cells arranged in a matrix,
wherein each of the plurality of second memory cells comprises a second transistor and a second capacitor electrically connected to the second transistor,
wherein the first memory cell array is configured to store data for executing a start-up routine of the processor while power supply to the semiconductor device is stopped, and
wherein the second memory cell array is configured to be used as a work area for arithmetic operation when the processor is in normal operation.