Patent ID: 11922178
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. An apparatus to load data into an accelerator, the apparatus comprising:
memory;
processor circuitry including:
a central processing unit, a graphic processing unit or a digital signal processor, the central processing unit, the graphic processing unit or the digital signal processor having control circuitry to control data movement within the processor circuitry, arithmetic and logic circuitry to perform one or more first operations corresponding to instructions, and one or more registers to store a result of the one or more first operations and the instructions in the apparatus,
a Field Programmable Gate Array (FPGA), the FPGA including logic gate circuitry, a plurality of configurable interconnections, and storage circuitry, the logic gate circuitry and the plurality of configurable interconnections to perform one or more second operations, the storage circuitry to store a result of the one or more second operations, or
Application Specific Integrate Circuitry (ASIC) including logic gate circuitry to perform one or more third operations;

the processor circuitry to perform at least one of the one or more first operations, the one or more second operations or the one or more third operations to instantiate:
data provider circuitry to load compressed machine learning parameter data into a cache accessible by processor engine circuitry, the loaded data including first operable data, and
compressed local data re-user circuitry to identify that second operable data is present in the loaded data in the cache; and, the processor engine circuitry to:
decompress the first operable data into first decompressed data,
execute a first machine learning operation using the first decompressed data,
decompress the second operable data into second decompressed data, the compressed local data re-user circuitry to identify the second operable data based on a comparison of bits in a sparsity bitmap to bits in the first decompressed data and the second decompressed data, and
execute a second machine learning operation using the second decompressed data.