Patent ID: 11940931
Assignee: APPLE INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A data processing system comprising:
a memory device to store instructions;
one or more processors coupled to the memory device, wherein the one or more processors are to execute the instructions stored on the memory device and the instructions, when executed, cause the one or more processors to:
instantiate a synchronization primitive to control access to a resource, the synchronization primitive comprising a user mode primitive;
acquire the synchronization primitive at a first thread, the first thread having a first user mode priority and a first kernel mode priority;
in response to an attempt to acquire the synchronization primitive at a second thread while the synchronization primitive is held by the first thread, add the second thread to a wait queue of a first turnstile object associated with the synchronization primitive; and
signal the second thread when the synchronization primitive is available to be acquired.