Patent ID: 11966675
Assignee: THE MATHWORKS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. An apparatus comprising:
one or more memories storing a model including a first co-simulation component and a second co-simulation component, where
the first co-simulation component outputs data to the second co-simulation component via a connection, and
the connection is declared as a continuous connection for input of the data into the second co-simulation component; and

one or more processors coupled to the one or more memories, the one or more processors configured to run one or more technical computing environments (TCEs) including a first solver for solving the first co-simulation component and a second solver for solving the second co-simulation component where the first and second solvers are different, where the one or more TCEs:
present the model on a User Interface (UI);
analyze the model;
determine a modeled sample rate for the connection being declared as the continuous connection based on the analyzing the model;
determine the data is communicated from the first co-simulation component to the second co-simulation component via the connection at a discrete-time communication rate that is different from the modeled sample rate for the connection declared as the continuous connection based on the analyzing the model;
identify that an error is introduced into execution of the model based on the data being communicated via the connection at the discrete-time communication rate that is different from the modeled sample rate for the connection declared as the continuous connection; and
visually distinguish on the UI an appearance of a first line included in the model and representing the connection from an appearance of a second line included in the model, based on the data being communicated via the connection at the discrete-time communication rate and the connection declared as the continuous connection.