Patent ID: 11955977
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 13:
14. A method of adjusting a clock signal provided to a memory device, the method comprising:
adjusting a duty cycle of a clock signal of a memory device with a duty cycle adjuster based on a plurality of lookahead duty codes stored in a mode register, wherein the adjusting is performed concurrently with access operations of the memory device;
monitoring the duty cycle of the adjusted clock signal;
selecting one of the plurality of lookahead duty codes based on the monitoring; and
adjusting an operation of a duty cycle adjustor of the memory device based on the selected lookahead duty code, wherein the selecting comprises selecting a first duty code based on monitoring at a first polarity and selecting a second duty code based on monitoring at a second polarity.