Patent ID: 11868253
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 8:
9. A memory device, comprising:
a buffer die coupled to a substrate, the buffer die including a host device interface, and a DRAM interface, wherein the host device interface includes at least one memory channel, and wherein the DRAM interface includes at least two sub-channels;
a stack of DRAM dies supported by the substrate;
multiple through silicon via (TSV) interconnections coupling multiple die in the stack of DRAM dies with the buffer die; and
circuitry in the buffer die, configured to operate the host interface at a first data speed, and to operate the DRAM interface at a second data speed, slower than the first data speed, the circuitry configured to map the at least one memory channel to the at least two sub-channels.