Patent ID: 11887951
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A three-dimensional semiconductor memory device, comprising:
a first substrate including a cell array region and a cell array contact region;
a peripheral circuit structure on the first substrate; and
a cell array structure including a stack, first vertical channel structures, second vertical channel structures, and a second substrate,
the stack being on the peripheral circuit structure,
the first vertical channel structures and the second vertical channel structures being on the cell array region and penetrating the stack, and
the second substrate being connected to the first vertical channel structures and the second vertical channel structures,
the stack between the peripheral circuit structure and the second substrate,
the second substrate including a first portion, a second portion, and a third portion,
the first portion being in contact with the first vertical channel structures and doped to have a first conductivity type,
the second portion being in contact with the second vertical channel structures and doped to have a second conductivity type different from the first conductivity type, and
the third portion being on the cell array contact region and doped to have the second conductivity type.