Patent ID: 11907572
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 4:
5. A method comprising:
receiving, at an interface of a memory sub-system and from a host, a write command addressed to a first address and a read command addressed to a second address;
storing the write command and the read command in a command buffer of the interface;
determining, using a comparator of the interface, whether the first address matches the second address while the write command and the read command are stored in the command buffer;
determining, using the comparator of the interface, whether the write command was inserted into the command buffer prior to insertion of the read command into the command buffer by comparing a write identifier (ID) of the write command and a read ID of the read command, wherein the write ID and the read ID are assigned sequentially based on an order in which commands are received from the host;
determining whether data stored in a write buffer of the interface and corresponding to the write command is corrupt;
responsive to determining that the first address matches the second address, that the data is not corrupt, and that the write command was inserted into the command buffer prior to inserting the read command into the command buffer:
dropping, at the interface, the read command and the second address from the command buffer by sending a signal from the comparator to error correction circuitry of the interface to cause the error correction circuitry to mark the read command as being erroneous without regard to performing an error check on the read command and without regard to whether the read command passes an error check if performed, wherein a memory sub-system controller is configured to delete the read command responsive to the read command being marked by the error correction circuitry;
forwarding the data from the write buffer directly to a read buffer of the interface via lines that couple the write buffer to the read buffer; and
providing the data to the host from the read buffer; and

responsive to determining that the first address does not match the second address or that the data is corrupt, providing the read command and the second address to a processing device coupled to a memory device of the memory sub-system and configured to control cache memory for the memory device to store data prior to storing the data on the memory device.