Patent ID: 11901415
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 15:
16. A method, comprising:
forming an epitaxial layer on a substrate, wherein the epitaxial layer comprises dopants;
forming a stack of alternating first and second nano-sheet layers on the epitaxial layer;
patterning the stack and the epitaxial layer to form a fin structure;
forming a sacrificial gate structure on the fin structure;
removing portions of the fin structure not covered by the sacrificial gate structure;
etching portions of the first nano-sheet layers;
forming spacer structures on the etched portions of the first nano-sheet layers;
forming source/drain (S/D) epitaxial structures on the epitaxial layer abutting the second nano-sheet layers, wherein the S/D epitaxial structures comprise dopants of an opposite type to that of the epitaxial layer;
removing the sacrificial gate structure;
removing the first nano-sheet layers; and
forming a gate structure around the second nano-sheet layers.