Patent ID: 11894331
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A chip structure, comprising:
a substrate;
an interconnect layer over the substrate;
a conductive pad over the interconnect layer;
a conductive bump over the conductive pad, wherein the conductive bump has a first portion, a second portion, and a neck portion between the first portion and the second portion, the first portion is between the neck portion and the conductive pad, and the neck portion is narrower than the first portion and narrower than the second portion; and
an alloy layer between the conductive bump and the conductive pad, wherein a first composition of the alloy layer is different from a second composition of the conductive bump, and the alloy layer has a first width decreasing toward the conductive bump.