Patent ID: 11916133
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor structure, comprising:
a first gate structure sandwiched between and in contact with a first spacer feature and a second spacer feature;
a second gate structure sandwiched between and in contact with a third spacer feature and a fourth spacer feature;
a first gate self-aligned contact (SAC) dielectric feature over the first spacer feature, the first gate structure, and the second spacer feature;
a second gate SAC dielectric feature over the third spacer feature, the second gate structure, and the fourth spacer feature;
a source/drain contact sandwiched between the second spacer feature and the third spacer feature;
a source/drain SAC dielectric feature over the source/drain contact;
a contact etch stop layer disposed over the first gate SAC dielectric feature, the second gate SAC dielectric feature and the source/drain SAC dielectric feature;
a first gate contact feature extending through the contact etch stop layer and the first gate SAC dielectric feature, and between the first spacer feature and the second spacer feature to be in contact with the first gate structure; and
a liner disposed along a sidewall of the first spacer feature, a top surface of the first gate structure, and a sidewall of the second spacer feature,
wherein a portion of the first gate SAC dielectric feature extends between the first spacer feature and the second spacer feature,
wherein the first gate SAC dielectric feature is in direct contact with top surfaces of the first spacer feature and the second spacer feature.