Patent ID: 11955483
Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor device, comprising:
a base substrate, the base substrate including a substrate and a plurality of fins on the substrate, and the plurality of fins including a sparse region and a dense region;
a gate structure disposed on the substrate and crosses the plurality of fins, wherein the gate structure includes a first portion in a first region and a second portion in a second region, a length of the first portion of the gate structure in the first region is larger than a length of the second portion of the gate structure in the second region, the length of the first portion of the gate structure is a distance of the first portion of the gate structure across corresponding adjacent fins of the plurality of fins along a direction perpendicular to an extending direction of the plurality of fins, the length of the second portion of the gate structure is a distance of the second portion of the gate structure across corresponding adjacent fins of the plurality of fins along the direction perpendicular to the extending direction of the plurality of fins, the first portion of the gate structure in the first region is located between the plurality of fins in the sparse region, and the second portion of the gate structure in the second region is located between the plurality of fins in the dense region;
a separation section in the first portion of the gate structure in the first region, wherein a top surface of the separation section is higher than a top surface of the gate structure, and a width of the entire separation section along the direction perpendicular to the extending direction of the plurality of fins is uniform;
a dielectric layer on the top surface of the gate structure, on sidewalls of the separation section that are higher than the gate structure, and on the top surface of the separation section; and
a metal layer in the dielectric layer, a first bottom surface of the metal layer being in contact with the top surface of the gate structure at a side of the separation section, and a second bottom surface of the metal layer being in contact with the top surface of the separation section.