Patent ID: 11907141
Assignee: QUALCOMM INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 24:
25. The method of claim 24, further comprising:
receiving, at the first partial channel interface, a first signal configured to cause the first memory device of the logical rank to implement a first memory access command via the first partial channel;
receiving, at the second partial channel interface, a second signal configured to cause the second memory device of the logical rank to implement a second memory access command via the second partial channel;
implementing, via the first partial channel, the first memory access command at the first memory device following implementing the refresh operation at the second memory device in parallel with implementing the refresh operation at the first memory device; and
implementing, via the second partial channel, the second memory access command at the second memory device following implementing the refresh operation at the second memory device in parallel with implementing the refresh operation at the first memory device.