Patent ID: 11916002
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A semiconductor package, comprising:
a package substrate;
an interposer substrate on the package substrate, the interposer substrate including a first redistribution substrate, a second redistribution substrate below a bottom surface of the first redistribution substrate, and an interposer molding layer between the first redistribution substrate and the second redistribution substrate;
a connection semiconductor chip in the interposer molding layer and on the bottom surface of the first redistribution substrate, the connection semiconductor chip having a first surface facing the second redistribution substrate; and
a first semiconductor chip on the interposer substrate,
wherein the interposer molding layer covers an upper surface and bottom surface of the connection semiconductor chip and is between the second redistribution substrate and the first surface of the connection semiconductor chip.