Patent ID: 11936791
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 7:
8. The method of claim 1, wherein the assertion-related instructions are received from a first state that an image of the instructions may take, wherein the method further comprises:
identifying a feature flag and/or configuration in the instructions;
detecting a second state that the image of the instructions may take based on the feature flag and/or configuration;
comparing the assertion-related instructions received from the first state that the image of the instructions may take with instructions of the second state that the image of the instructions may take;
identifying the assertion-related instructions in the instructions of the second state that the image of the instructions may take;
receiving the CAT and the assertion-related instructions of the second state; and
generating a third code verification ERR based at least in part on the CAT and the assertion-related instructions of the second state.