Patent ID: 11934076
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Optics (Instruments)
Classification: CPC G  H | IPC G

Claim 11:
12. A method for manufacturing an array substrate, comprising:
providing a first substrate;
forming a first reflecting layer on the first substrate;
forming a first light absorbing layer on the first reflecting layer; and
forming at least one marking member and/or at least one bonding lead on the first light absorbing layer, such that the first reflecting layer and the first light absorbing layer are in at least one marking sub-region and/or in at least one bonding sub-region in a peripheral region of the array substrate, the at least one marking member is on the first light absorbing layer in the at least one marking sub-region, the at least one bonding lead is on the first light absorbing layer in the at least one bonding sub-region, wherein the array substrate further comprises a display region, and the peripheral region at least partially surrounds the display region;
the method further comprises:
forming a second light absorbing layer and at least one driving signal line, wherein forming a second light absorbing layer and at least one driving signal line comprises: forming the second light absorbing layer in a same process as forming the first light absorbing layer, forming the at least one driving signal line in a same process as forming the at least one marking member and/or the at least one bonding lead, such that the second light absorbing layer is in at least one driving sub-region in the peripheral region and the display region of the array substrate, and the at least one driving signal line is on a side of the second light absorbing layer distal to the first substrate; and
forming a third light absorbing layer and at least one signal connection line, wherein forming a third light absorbing layer and at least one signal connection line comprises: forming the third light absorbing layer in a same process as forming the first light absorbing layer, forming the at least one signal connection line in a same process as forming the at least one marking member and/or the at least one bonding lead, such that the at least one signal connection line is in at least one fan-out sub-region in the peripheral region of the array substrate, and the third light absorbing layer is between the at least one bonding lead and the first substrate at connection positions of the at least one bonding lead and the at least one signal connection line.