Patent ID: 11886881
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. Apparatus comprising:
instruction fetch circuitry to retrieve a sequence of instructions;
instruction processing circuitry comprising decoupled access-execute processing circuitry comprising an access portion and an execute portion, wherein the access portion is arranged to execute load-related instructions of the sequence of instructions and to cause data items to be retrieved from memory as a result of the load-related instructions to be locally stored for access by the execute portion,
and the execute portion is arranged to execute data processing instructions of the sequence of instructions comprising accessing locally stored operands of the data processing instructions;
and memory access circuitry comprising:
a data cache for temporary storage of data items retrieved from memory by the instruction processing circuitry;
prefetch circuitry responsive to an identified pattern of data retrieval by the instruction processing circuitry to extrapolate the identified pattern and cause data items from predicted addresses to be retrieved from memory and stored in the data cache based on the extrapolated pattern,
wherein the apparatus is arranged to carry out at least one of:
control of the access portion in dependence on a performance metric of the prefetch circuitry; and
control of the prefetch circuitry in dependence on a performance metric of the access portion.