Patent ID: 11894359
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. An apparatus, comprising:
a first plurality of conductors on an upper surface of a base semiconductor die;
a second plurality of conductors on the upper surface of the base semiconductor die, wherein:
each of the first plurality of conductors is disposed on the upper surface of the base semiconductor die and is spaced apart from the remaining first plurality of conductors;
each of the second plurality of conductors is disposed on the upper surface of the base semiconductor die and is spaced apart from the remaining second plurality of conductors; and
each of the first plurality of conductors intersects and conductively couples to at least one of the second plurality of conductors on the upper surface of the base semiconductor die, the first plurality of conductors and the second plurality of conductors conductively coupled to circuitry included in the base semiconductor die; and

each of a plurality of cores conductively coupled to a node formed by an intersection of one of the first plurality of conductors with one of the second plurality of conductors, wherein each of the plurality of cores comprises processor core circuitry.