Patent ID: 11936791
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 12:
13. A method for verifying reliability of instructions for a device, the method performed by a computing system comprising a processor and a memory, the method comprising:
displaying, via a user interface, a reliability requirement associated with instructions for a device;
receiving, from a user via the user interface, an assertion in relation to the reliability requirement;
generating a cryptographic assertion tracer (CAT) based at least in part on the received assertion;
receiving, from the user, an identification of assertion-related instructions in a first copy of the instructions for the device to associate with the CAT;
generating a first code verification encrypted reproducible record (ERR) based at least in part on the CAT and the identified assertion-related instructions in the first copy of the instructions for the device;
receiving a second copy of the instructions for the device;
generating a second code verification ERR based at least in part on the CAT and the identified assertion-related instructions in the second copy of the instructions for the device;
comparing the first and second code verification ERRs; and
when the first and second code verification ERRs do not match, based on the comparison, reporting that the reliability requirement is not addressed.