Patent ID: 11936384
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 12:
13. The multi-bit flip-flop of claim 1, further comprising a third bit flip-flop,
the third bit flip-flop comprising:
a third input multiplexer configured to receive a twelfth data bit as a data input, receive the eleventh data bit as a scan input, and output one of the twelfth data bit and the eleventh data bit as a thirteenth data bit;
a fifth transmission circuit configured to output a fourteenth data bit in response to the thirteenth data bit in synchronization with the clock signal and the inverse clock signal;
a fifth latch configured to store the fourteenth data bit in synchronization with the clock signal and the inverse clock signal;
a sixth transmission circuit configured to output a fifteenth data bit in response to the fourteenth data bit in synchronization with the clock signal and the inverse clock signal; and
a sixth latch configured to store the fifteenth data bit and output a sixteenth data bit as a third output data bit in response to the fifteenth data bit.