Patent ID: 11967380
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 0:
1. A semiconductor memory device comprising
a first memory cell array;
a second memory cell array arranged above the first memory cell array in a first direction;
a third memory cell array arranged adjacent to the first memory cell array it a second direction intersecting with the first direction;
a fourth memory cell array arranged above the third memory cell array in the first direction and arranged adjacent to the second memory cell array in the second direction;
a first word line coupled to the first memory dell array and the second memory cell array;
a second word line coupled to the this memory cell array and the fourth memory cell array;
a first bit line coupled to the first memory cell array and the fourth memory cell array; and
a second bit line coupled to the second memory cell array and the third memory cell array.