Patent ID: 11902070
Assignee: INTEL CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. An apparatus comprising:
Enhanced Directional Multi-Gigabit (DMG) (EDMG) Physical Layer (PHY) circuitry configured to:
provide a plurality of Orthogonal Frequency Division Multiplexing (OFDM) Training (TRN) sequences in a frequency domain, the plurality of OFDM TRN sequences corresponding to a plurality of transmit chains to transmit a TRN field of an EDMG OFDM PHY Protocol Data Unit (PPDU) over a channel bandwidth of 4.32 Gigahertz (GHz), the plurality of OFDM TRN sequences comprising a first OFDM TRN sequence corresponding to a first transmit chain, and a second OFDM TRN sequence corresponding to a second transmit chain,
wherein the first OFDM TRN sequence comprises a sequence TRN-BASIC1−386,386=[Seq1left, 385, 0, 0, 0, Seq1right, 385],
wherein Seq1left, 385={−1 −1 +j −1 +1 +1 −1 +j +1 +j +j +j −j −j −1 −j +j +j −j +1 −j +1 +1 +1 −1 −1 +j −1 +1 +1 −1 +j +1 +j +j +j −j +j +1 +j −j −j +j −1 +j −1−1 −1 +1 +1 −j +1 −1 −1 +1 −j −1 −j −j −j +j +j +1 +j −j −j +j −1 +j −1−1 −1 +1 −1 +j −1 +1 +1 −1 +j +1 +j +j +j −j +j +1 +j −j −j +j −1 +j −1 −1 −1 +1 −1 +j −1 +1 +1 −1 +j +1 +j +j +j −j −j −1 −j +j +j −j +1 −j +1 +1 +1 −1 −1 +j −1 +1 +1 −1 +j +1 +j +j +j −j +j +1 +j −j −j +j −1 +j −1 −1 −1 +1 −1 +j −1 +1 +1 −1 +j +1 +j +j +j −j −j −1 −j +j +j −j +1 −j +1 +1 +1 −1 +1 −j +1 −1 −1 +1 −j −1 −j −j −j +j −j −1 −j +j +j −j +1 −j +1 +1 +1 −1 −j −1 −j +j +j −j −1 +j −1−1 −1 +1 +1 −j +1 −1 −1 +1 +j +1 +j +j +j −j −j −1 −j +j +j −j −1 +j −1−1 −1 +1 −1 +j −1 +1 +1 −1 −j −1 −j −j −j +j +j +1 +j −j −j +j +1 −j +1 +1 +1 −1 −1 +j −1 +1 +1 −1 −j −1 −j −j −j +j −j −1 −j +j +j −j −1 +j −1 −1 −1 +1 −1 +j −1 +1 +1 −1 −j −1 −j −j −j +j +j +1 +j −j −j +j +1 −j +1 +1 +1 −1 −1 +j −1 +1 +1 −1 −j −1 −j −j −j +j +j +1 +j −j −j +j +1 −j +1 +1 +1 −1 +1 −j +1 −1 −1 +1 +j +1 +j +j +j −j +j +1 +j −j −j +j +1 −j +1 +1 +1 −1 −1 +j −1 +1 +1 −1 −j −1 −j −j −j +j −j −1 −j +j +j −j −1 +j −1−1 −1 +1 −1 +j −1 +1 +1 −1 −j −1 −j −j −j +j},
and Seq1right, 385={+1 −j +1 −1 −1 +1 −j −1 −j −j −j +j +j +1 +j −j −j +j −1 +j −1 −1 −1 +1 +1 −j +1 −1 −1 +1 −j −1 −j −j −j +j −j −1 −j +j +j −j +1 −j +1 +1 +1 −1 −1 +j −1 +1 +1 −1 +j +1 +j +j +j −j −j −1 −j +j +j −j +1 −j +1 +1 +1 −1 +1 −j +1 −1 −1 +1 −j −1 −j −j −j +j −j −1 −j +j +j −j +1 −j +1 +1 +1 −1 +1 −j +1 −1 −1 +1 −j −1 −j −j −j +j +j +1 +j −j −j +j −1 +j −1 −1 −1 +1 +1 −j +1 −1 −1 +1 −j −1 −j −j −j +j −j −1 −j +j +j −j +1 −j +1 +1 +1 −1 +1 −j +1 −1 −1 +1 −j −1 −j −j −j +j +j +1 +j −j −j +j −1 +j −1 −1 −1 +1 −1 +j −1 +1 +1 −1 +j +1 +j +j +j −j +j +1 +j −j −j +j −1 +j −1−1 −1 +1 −j −1 −j +j +j −j −1 +j −1 −1 −1 +1 +1 −j +1 −1 −1 +1 +j +1 +j +j +j −j −j −1 −j +j +j −j −1 +j −1−1 −1 +1 −1 +j −1 +1 +1 −1 −j −1 −j −j −j +j +j +1 +j −j −j +j +1 −j +1 +1 +1 −1 −1 +j −1 +1 +1 −1 −j −1 −j −j −j +j −j −1 −j +j +j −j −1 +j −1−1 −1 +1 −1 +j −1 +1 +1 −1 −j −1 −j −j −j +j +j +1 +j −j −j +j +1 −j +1 +1 +1 −1 −1 +j −1 +1 +1 −1 −j −1 −j −j −j +j +j +1 +j −j −j +j +1 −j +1 +1 +1 −1 +1 −j +1 −1 −1 +1 +j +1 +j +j +j −j +j +1 +j −j −j +j +1 −j +1 +1 +1 −1 −1 +j −1 +1 +1 −1 −j −1 −j −j −j +j −j −1 −j +j +j −j −1 +j −1 −1 −1 +1 −1 +j −1 +1 +1 −1 −j −1 −j −j −j +j +j},

wherein the second OFDM TRN sequence comprises a sequence TRN-BASIC2−386,386=[Seq2left, 385, 0, 0, 0, Seq2right, 385],
wherein Seq2left, 385={−j +1 −1 −1 −1 +j −1 −j +j +j +j +1 +j +j −j −j +j +1 +j −1 +1 +1 −1 +j −1 −1 +1 +1 +1 −j +1 +j −j −j −j −1 −j −j +j +j −j −1 −j +1 −1 −1 +1 −j +1 +1 −1 −1 −1 +j −1 −j +j +j +j +1 +j +j −j −j +j +1 +j −1 +1 +1 −1 +j −1 +1 −1 −1 −1 +j −1 −j +j +j +j +1 +j +j −j −j +j +1 +j −1 +1 +1 −1 +j −1 +1 −1 −1 −1 +j −1 −j +j +j +j +1 +j +j −j −j +j +1 +j −1 +1 +1 −1 +j −1 +1 −1 −1 −1 +j −1 −j +j +j +j +1 +j +j −j −j +j +1 +j −1 +1 +1 −1 +j −1 +1 −1 −1 −1 +j −1 −j +j +j +j +1 +j +j −j −j +j +1 +j −1 +1 +1 −1 +j −1 −1 +1 +1 +1 −j +1 +j −j −j −j −1 −j −j +j +j −j −1 −j +1 −1 −1 +1 −j +1 +j −j −j −j −1 −j −1 +1 +1 +1 −j +1 −1 +1 +1 −1 +j −1 +j −j −j +j +1 +j −j +j +j +j +1 +j +1 −1 −1 −1 +j −1 +1 −1 −1 +1 −j +1 −j +j +j −j −1 −j +j −j −j −j −1 −j −1 +1 +1 +1 −j +1 −1 +1 +1 −1 +j −1 +j −j −j +j +1 +j +j −j −j −j −1 −j −1 +1 +1 +1 −j +1 −1 +1 +1 −1 +j −1 +j −j −j +j +1 +j −j +j +j +j +1 +j +1 −1 −1 −1 +j −1 +1 −1 −1 +1 −j +1 −j +j +j −j −1 −j −j +j +j +j +1 +j +1 −1 −1 −1 +j −1 +1 −1 −1 +1 −j +1 −j +j +j −j −1 −j −j +j +j +j +1 +j +1 −1 −1 −1 +j −1 +1 −1 −1 +1 −j +1 −j +j +j −j −1 −j +j −j −j −j −1 −j −1 +1 +1 +1 −j +1 −1 +1 +1 −1 +j −1 +j −j −j +j +1 +j},
and Seq2right, 385={−1 +1 +1 +1 −j +1 +j −j −j −j −1 −j −j +j +j −j −1 −j +1 −1 −1 +1 −j +1 +1 −1 −1 −1 +j −1 −j +j +j +j +1 +j +j −j −j +j +1 +j −1 +1 +1 −1 +j −1 +1 −1 −1 −1 +j −1 −j +j +j +j +1 +j +j −j −j +j +1 +j −1 +1 +1 −1 +j −1 +1 −1 −1 −1 +j −1 −j +j +j +j +1 +j +j −j −j +j +1 +j −1 +1 +1 −1 +j −1 −1 +1 +1 +1 −j +1 +j −j −j −j −1 −j −j +j +j −j −1 −j +1 −1 −1 +1 −j +1 −1 +1 +1 +1 −j +1 +j −j −j −j −1 −j −j +j +j −j −1 −j +1 −1 −1 +1 −j +1 +1 −1 −1 −1 +j −1 −j +j +j +j +1 +j +j −j −j +j +1 +j −1 +1 +1 −1 +j −1 −1 +1 +1 +1 −j +1 +j −j −j −j −1 −j −j +j +j −j −1 −j +1 −1 −1 +1 −j +1 −j +j +j +j +1 +j +1 −1 −1 −1 +j −1 +1 −1 −1 +1 −j +1 −j +j +j −j −1 −j +j −j −j −j −1 −j −1 +1 +1 +1 −j +1 −1 +1 +1 −1 +j −1 +j −j −j +j +1 +j +j −j −j −j −1 −j −1 +1 +1 +1 −j +1 −1 +1 +1 −1 +j −1 +j −j −j +j +1 +j +j −j −j −j −1 −j −1 +1 +1 +1 −j +1 −1 +1 +1 −1 +j −1 +j −j −j +j +1 +j +j −j −j −j −1 −j −1 +1 +1 +1 −j +1 −1 +1 +1 −1 +j −1 +j −j −j +j +1 +j +j −j −j −j −1 −j −1 +1 +1 +1 −j +1 −1 +1 +1 −1 +j −1 +j −j −j +j +1 +j −j +j +j +j +1 +j +1 −1 −1 −1 +j −1 +1 −1 −1 +1 −j +1 −j +j +j −j −1 −j +j −j −j −j −1 −j −1 +1 +1 +1 −j +1 −1 +1 +1 −1 +j −1 +j −j −j +j +1 +j −j}; and

generate a plurality of TRN transmit waveforms in a time domain based on the plurality of OFDM TRN sequences, wherein the plurality of TRN transmit waveforms comprises a first TRN transmit waveform based on the first OFDM TRN sequence corresponding to the first transmit chain, and a second TRN transmit waveform based on the second OFDM TRN sequence corresponding to the second transmit chain; and memory circuitry to store information processed by the EDMG PHY circuitry.