Patent ID: 11895851
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 11:
12. An apparatus, comprising:
a plurality of tiles of a memory array, each tile of the plurality of tiles comprising a plurality of sub-blocks and a plurality of decks, wherein each sub-block of the plurality of sub-blocks comprises a plurality of memory cells of the memory array addressable via a plurality of word lines and a plurality of bit lines, each of the plurality of bit lines coupled with one or more decks of the plurality of decks, the plurality of bit lines comprising a first bit line, a second bit line, and a third bit line; and
a plurality of bit line decoders positioned beneath the memory array, wherein a first bit line decoder of the plurality of bit line decoders is coupled with the first bit line using a first configuration of sockets within a first subset of the plurality of sub-blocks, a second bit line decoder of the plurality of bit line decoders is coupled with the second bit line using a second configuration of sockets within a second subset of the plurality of sub-blocks, and a third bit line decoder of the plurality of bit line decoders is coupled with the third bit line using a third configuration of sockets within a third subset of the plurality of sub-blocks.