Patent ID: 11910594
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 19:
20. A semiconductor device comprising:
a substrate including:
a chip region; and
a scribe lane region surrounding the chip region;

a bit line structure on the chip region of the substrate;
a first spacer structure on a sidewall of the bit line structure;
a plurality of key structures on the scribe lane region of the substrate, each of the plurality of key structures having an upper surface substantially coplanar with an upper surface of the bit line structure;
a second spacer structure on a sidewall of each of the plurality of key structures;
a trench disposed between two adjacent key structures of the plurality of key structures, wherein the two adjacent key structures are spaced apart from each other in a first direction substantially parallel to an upper surface of the substrate;
a filling pattern in a lower portion of the trench, the filling pattern including a first conductive material; and
a conductive structure on an upper surface of the filling pattern, an upper sidewall of the trench, and the upper surface of each of the plurality of key structures, the conductive structure including a second conductive material.