Patent ID: 11962485
Assignee: ARISTA NETWORKS, INC.
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A network device comprising:
at least one processor; and
a memory communicatively coupled to the at least one processor, the memory storing instructions executable by the at least one processor to perform a method, the method comprising:
A) identifying a plurality of groups, each group comprising routes that are associated with a same set of next hops;
B) for each group, pairing sets of resilient adjacencies corresponding to the routes in the group to produce pairs of resilient adjacencies for the group;
C) identifying a pair of resilient adjacencies from among a plurality of pairs of resilient adjacencies across all the groups;
D) selecting a first resilient adjacency from the identified pair;
E) programming one or more routes in a forwarding table that refer to the first resilient adjacency in the identified pair to refer to a second resilient adjacency in the identified pair; and
F) removing the first resilient adjacency from a hardware table that stores the first resilient adjacency.