Patent ID: 11967375
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 9:
10. A memory device, comprising:
at least one memory cell, wherein each of the at least one memory cell is coupled to a bit line and a word line, each of the at least one memory cell comprising:
a memory element, configured to store data of the at least one memory cell; and
a selector element, coupled to the memory element in series, configured to select the memory element for a read operation and amplify the data stored in the memory element in the read operation, wherein the selector element of a memory cell among the at least one memory cell is located inside the memory cell, wherein

the memory cell includes a stack of a metal pad layer, a memory element layer and a selector element layer,
the memory element layer is sandwiched between the metal pad layer and the selector element layer,
the stack of the metal pad layer, the memory element layer and the selector element layer is sandwiched between a metal bit line layer and a metal word line layer, and
the metal bit line layer directly contacts the metal pad layer,
the selector element includes an ovonic threshold switch that has a threshold voltage and a holding voltage, and
when the voltage in the range from the holding voltage to the threshold voltage is applied to the memory cell being in a second logic state, the current flowing through the memory element is less than the operating current of the selector element, and the selector element is in a non-conductive state.