Patent ID: 11929961
Assignee: QUALCOMM INCORPORATED
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 23:
24. An apparatus for wireless communication, comprising:
a processor;
memory coupled with the processor; and
instructions stored in the memory and executable by the processor to cause the apparatus to:
receive downlink control information scheduling an uplink shared channel transmission in a slot, wherein the uplink shared channel transmission overlaps with multiple scheduled transmission acknowledgement messages;
determine that a plurality of timing thresholds are satisfied by an earliest of the multiple scheduled transmission acknowledgement messages and the uplink shared channel transmission with respect to a latest downlink data transmission acknowledged by one of the multiple scheduled transmission acknowledgement messages and with respect to the downlink control information scheduling the uplink shared channel transmission;
generate a plurality of acknowledgement codebooks for transmission of the multiple scheduled transmission acknowledgement messages, comprising separately encoding the multiple scheduled transmission acknowledgement messages to corresponding sets of coded bits; and
multiplex, based at least in part on the plurality of timing thresholds being satisfied, the corresponding sets of coded bits with the uplink shared channel transmission.