Patent ID: 11894062
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 4:
5. The memory apparatus as set forth in claim 4, wherein the control means, during a neutralization period of time, is further configured to simultaneously:
apply an inhibiting voltage to unselected ones of the plurality of bit lines associated with the ones of the memory cells connected to the at least one dummy word line having the threshold voltage not being below the predetermined detection voltage threshold following the erase operation to inhibit programming;
ground selected ones of the plurality of bit lines associated with the ones of the memory cells connected to the at least one dummy word line having the threshold voltage being below the predetermined detection voltage threshold following the erase operation to encourage programming; and
apply the at least one programming pulse of the maintenance program voltage to the at least one dummy word line to program the ones of the memory cells connected to the at least one dummy word line having the threshold voltage being below the predetermined detection voltage threshold.