Patent ID: 11887648
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 10:
11. A semiconductor memory device, comprising:
a semiconductor substrate;
a plurality of memory cell structures each comprising a cell source layer, a channel layer, and a drain layer sequentially stacked from the semiconductor substrate in a vertical direction, and each having a vertical pillar shape extending in the vertical direction;
a plurality of word line structures being apart from each other in the vertical direction and surrounding the plurality of memory cell structures;
a plurality of memory cell dielectric layers each interposed between the channel layer of a corresponding one of the plurality of memory cell structures and a corresponding one of the plurality of word line structures; and
a plurality of bit lines each electrically connected to the drain layer of each of the plurality of memory cell structures, respectively, extending in a first horizontal direction on the plurality of word line structures, and having a certain distance from each other in a second horizontal direction orthogonal to the first horizontal direction,
wherein the drain layer is doped with impurities of a first conductivity type,
the cell source layer is doped with impurities of a second conductivity type different from the first conductivity type,
each of the plurality of memory cell dielectric layers comprises:
a gate insulating layer covering the plurality of word line structures; and
a charge trap layer arranged between the gate insulating layer and the channel layer, and

each of the plurality of memory cell structures comprises a volatile memory device having a thyristor structure.