Patent ID: 11863284
Assignee: KRATOS INTEGRAL HOLDINGS, LLC
Field: Telecommunications (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 15:
16. A system for combining a plurality of downlink signals representative of a communication signal, the system comprising:
a plurality of antennas configured to receive the plurality of downlink signals; and
one or more processors communicatively coupled to the plurality of antennas, the one or more processors having a plurality of processing blocks and operable to:
receive samples of the plurality of downlink signals from a plurality of antenna feeds;
generate first symbols for a first signal of the plurality of downlink signals based on performing a first timing recovery operation on first samples of the first signal;
generate second symbols for a second signal of the plurality of downlink signals based on performing a second timing recovery operation on second samples of the second signal;
generate time and phase offset information based on performing a correlator operation on the first and second symbols; and
combine the first signal and the second signal based on (i) the first and second symbols, (ii) aligning timing and phase of the first symbols with the second symbols based on the time and phase offset information, and (iii) performing a weighted combiner operation that applies scaling to each of the first and second signals based on corresponding signal quality,
wherein at least one of the first timing recovery operation, the second timing recovery operation, the correlator operation, and the combing are performed in a plurality of processing blocks in one or more processors, wherein the first and second processing block operate in parallel.