Patent ID: 11886884
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A processor comprising:
decoder circuitry to decode a branch instruction associated with coherence-based prediction, the branch instruction including a first operand to specify a target address and a second operand to specify a snoop address, wherein coherence-based prediction comprises branch prediction based on one or more coherence operations, wherein each coherence operation comprises a request to maintain coherency among copies of data elements included in a plurality of processing engines of the processor; and
branch prediction circuitry to, in response to an execution of the branch instruction associated with coherence-based prediction, populate a first entry of a tracking data structure based on the target address and the snoop address specified in the branch instruction, the tracking data structure for coherence-based prediction.