Patent ID: 11875843
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. A method of operating a memory device, comprising:
receiving an input enable signal at an input of a logic gate and generating a first enable signal at an output of the logic gate;
receiving the first enable signal at an input of an inverter and generating a second enable signal at an output of the inverter;
providing the first enable signal to a column selection circuit and the second enable signal to a sense amplifier circuit, wherein the column selection circuit is coupled directly to the input of the inverter;
using the column selection circuit to generate a column selection signal to a memory array based upon the first enable signal; and
receiving a data signal from the memory array at the sense amplifier in response to the second enable signal.