Patent ID: 11953980
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. The method of claim 16, wherein:
the at least one offset read voltage includes (1) a positive offset voltage greater than the read level voltage and (2) a negative offset voltage less than the read level voltage, wherein the positive and negative offset voltages correspond to a shared offset magnitude;
the set of error rates includes (1) a positive offset rate corresponding to the positive offset voltage, (2) a negative offset rate corresponding to the negative offset voltage, and (3) a center rate corresponding to the read level voltage; and
dynamically calibrating the read level voltage includes (1) increasing the read level voltage when the positive offset rate is the lowest error rate or (2) decreasing the read level voltage when the negative offset rate is the lowest error rate.