Patent ID: 11971842
Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A communication device comprising:
communication circuitry configured to transmit a first serial signal group to a communication partner device as a batch of data blocks within one frame period of a predetermined communication protocol, or to the communication partner device as a plurality of data blocks divided according to a plurality of frame periods, the first serial signal group conforming to a serial peripheral interface (SPI), the first serial signal group being transmitted from a master in synchronization with a clock;
a memory configured to store the first serial signal group, and store a second serial signal group conforming to the SPI, the second serial signal group being transmitted from a slave in synchronization with the clock; and
a packet encoder configured to convert the first serial signal group stored in the memory into a first packet of the predetermined communication protocol, wherein the first packet includes frequency information of the clock with respect to a data signal of the first serial signal group conforming to the SPI.