Patent ID: 11889413
Assignee: NEW YORK UNIVERSITY
Field: Telecommunications (Electrical engineering)
Classification: CPC H  Y | IPC H

Claim 15:
16. An apparatus according to claim 1, wherein the processor is further configured to selectively reconfigure as a joint processor, configured to further include in the plurality of different conversion architectures a joint first QR-second QR architecture, comprising the first QRA receive CS enabled and the second QRA receive CS enabled, and to
selectively preform a joint processor interference cancellation process, comprising:
switching the switchable architecture receive conversion system to the joint first QR-second QR architecture, by operations that include:
enabling the first QRA receive CS causing a corresponding output from the enabled first QRA receive CS, to the joint processor, of first QR samples of the first signals, concurrent with

enabling the second QRA receive CS causing corresponding output from the enabled second QRA receive CS, to the joint processor, of second QR samples of the second signals;

detect, using the output from the first QRA receive CS of first QR samples of the first signals, an interfering signal; and
obtain a desired signal by operations comprising a subtracting, a canceling, and/or a removing of the detected interfering signal from the second QR samples received from the second QRA receive CS.