Patent ID: 11973025
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A three-dimensional semiconductor memory device, comprising:
a peripheral circuit structure; and
a cell array structure on the peripheral circuit structure,
wherein the peripheral circuit structure includes
a lower wiring on a substrate,
a stopping insulating layer on an upper surface of the lower wiring,
a contact via on the lower wiring and contacting the lower wiring through a via hole in the stopping insulating layer,
a support via on the stopping insulating layer, such that a bottom surface of the support via is on an upper surface of the stopping insulating layer, the support via not contacting the lower wiring, and
an upper wiring on the contact via, the upper wiring contacting the contact via.