Patent ID: 11967362
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. A memory device, comprising:
one or more memory cells configured to store data;
a pair of digit lines coupled to the one or more memory cells; and
a sense amplifier coupled to the pair of digit lines and comprising:
cross-coupled transistors coupled to a supply voltage;
a first gut node coupled to a first transistor of the cross-coupled transistors, wherein the first gut node corresponds to a first digit line of the pair of digit lines;
a second gut node coupled to a second transistor of the cross-coupled transistors, wherein the second gut node corresponds to a second digit line of the pair of digit lines;
a third transistor coupled to the first gut node, wherein a gate of the third transistor is coupled to the second digit line;
a fourth transistor coupled to the second gut node, where a gate of the fourth transistor is coupled to the first digit line;
a first isolating transistor coupled between the first digit line and the first gut node to selectively decouple the first digit line from the first gut node when amplifying a difference in voltages between the first and second gut nodes; and
a second isolating transistor coupled between the second digit line and the second gut node to selectively decouple the second digit line from the second gut node when amplifying the difference in voltages between the first and second gut nodes.