Patent ID: 11909565
Assignee: CADENCE DESIGN SYSTEMS, INC.
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. The integrated circuit of claim 8, wherein the control circuitry is further configured to:
adjust a reference voltage of the slicer from a first value used during measurements of the first eye height and the second eye height to a second value;
measure, at the first sample timing, while using the second value, and by varying the DFE coefficient of the receiver circuit, a third eye height while receiving the first data pattern;
measure, at the first sample timing, while using the second value, and by varying the DFE coefficient, a fourth eye height while receiving the second data pattern; and
determine whether a first difference between the first eye height and the second eye height is greater than a second difference between the third eye height and the fourth eye height.