Patent ID: 11942164
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. A method comprising;
providing, using a compensation circuit, a number of different bias signals to each of multiple signal lines of an array of memory cells, each signal line configured to provide access to a group of memory cells of the array of memory cells, each bias signal having an overdrive voltage above a target voltage by a selected increment and an overdrive period;
determining, using the compensation circuit, settling times of each of the multiple signal lines to the target voltage for the number of different bias signals;
determining, using the compensation circuit, a functional compensation profile for the array of memory cells comprising a relationship between the different bias signals and the determined settling times across the multiple signal lines, including:
determining the functional compensation profile across the array of memory cells in a number of separate linear segments, greater than one but less than N/2, wherein N is the number of multiple signal lines; or
determining the functional compensation profile across the array of memory cells in a number of segments, wherein at least one of the number of segments includes a polynomial segment, wherein the number of segments is greater than one but less than N/3, and wherein N is the number of multiple signal lines; and

storing, using the compensation circuit, a representation of the determined functional compensation profile to compensate for variance in an electrical parameter across the signal lines of the array of memory cells.