Patent ID: 11948640
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A method of controlling a memory device,
the memory device including:
a first transistor,
a second transistor,
a plurality of memory cells,
a source line,
a bit line,
a plurality of word lines, and
a sense amplifier, the sense amplifier including:
a first node,
a third transistor including a first end electrically connected to the bit line and a second end electrically connected to the first node,
a fourth transistor including a first end electrically connected to the second end of the third transistor and to the first node,
a fifth transistor including a gate electrically connected to the first node,
a sixth transistor including a first end electrically connected to a first end of the fifth transistor,
a seventh transistor including a first end electrically connected to the first end of the fifth transistor,
a first data latch electrically connected to a second end of the sixth transistor, and
a second data latch electrically connected to a second end of the seventh transistor,

the method comprising:
in a read operation including
a first period,
a second period after the first period,
a third period after the second period,
a fourth period after the third period, and
a fifth period after the fourth period,
applying a first voltage to one of the word lines, and applying a second voltage higher than the first voltage to another one of the word lines, at least during the second to fourth periods,
applying a third voltage to a gate of the fourth transistor to turn on the fourth transistor during the first period,
applying a fourth voltage to the gate of the fourth transistor to turn off the fourth transistor, and applying a fifth voltage to a gate of the third transistor to turn on the third transistor during the second period,
applying a sixth voltage to a gate of the sixth transistor to turn on the sixth transistor after the second period,
applying a seventh voltage to the gate of the third transistor to turn off the third transistor during the third period,
applying an eighth voltage to the gate of the third transistor to turn on the third transistor during the fourth period, and
applying a ninth voltage to a gate of the seventh transistor to turn on the seventh transistor, after the fourth period.