Patent ID: 11869972
Assignee: ETRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 5:
6. A transistor structure comprising:
a fin structure with a top surface;
a gate structure coupled to the fin structure and the top of the gate structure is higher than the top surface of the fin structure;
a first etched concave, and a bottom of the first concave being lower than the top surface of the fin structure, wherein the first etched concave has a first side barrier to reveal a first seed portion and has a second side barrier opposite to the first side barrier;
a first isolator formed in the first concave and above the bottom of the first concave, and all top surface of the first isolator being lower than the top surface of the fin structure, wherein the first isolator is limited within the first concave;
a first conductive region on the first isolator, wherein at least a portion of the first conductive region is a first single-crystalline region, the first single-crystalline region is laterally grown from the first seed portion and accommodated by the first etched concave, a top surface of the first conductive region is higher than the top surface of the fin structure, and the first conductive region is a semiconductor drain region;
a second etched concave and a bottom of the second concave being lower than the top surface of the fin structure, wherein the second etched concave has a third side barrier to reveal a second seed portion and has a fourth side barrier opposite to the third side barrier;
a second isolator being formed in the second concave and above the bottom of the second concave, wherein all top surface of the second isolator is lower than the top surface of the fin structure, and the second isolator is limited within the second concave; and
a second conductive region on the second isolator, wherein at least a portion of the second conductive region is a second single-crystalline region, and the second single-crystalline region is laterally grown from the second seed portion and accommodated by the second etched concave, and the second conductive region is a semiconductor source region;
wherein no other isolator is extended underneath the gate structure.