Patent ID: 11954465
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 3:
4. An apparatus comprising:
at least one interface configured to read one or more assembly code instructions; and
at least one processor configured to
determine indications for atomic operations in the one or more assembly code instructions, and
detect atomic operations based on the one or more assembly code instructions and the indications for the atomic operations in the assembly code instructions,
wherein the one or more assembly code instructions are translated from one or more high-level code instructions, and the atomic operations are indicated in the one or more assembly code instructions based on atomic operations in the one or more high-level code instructions,
wherein the indications for atomic operations in the one or more assembly code instructions are provided using information that is ignored by a processor architecture for which the assembly code instructions are translated,
wherein the indications for atomic operations in the one or more assembly code instructions are provided by:
i) using meta information, wherein the meta information is ineffective on a result of an execution of the assembly code instructions;
ii) using instruction prefixes that do not affect a result of an instruction execution;
iii) using distinguishable code patterns to mark atomic memory operations;
iv) using excessive segment prefixes;
v) using a one-byte prefix before an atomic instruction in the assembly code instructions; or
vi) using a duplicated segment prefix that atomic operations use or imply.