Patent ID: 11870247
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 5:
6. A failsafe electrostatic discharge (ESD) circuit, comprising:
a plurality of cells extending along a first direction and arranged along a second direction transverse to the first direction,
a first diode in an input/output (I/O) cell of the plurality of cells,
a second diode in an ESD cell of the plurality of cells,
a third diode, and
a fourth diode,
the first diode and the second diode configured in series from an I/O pin to an input of the third diode and an input of the fourth diode,
the third diode connected from an output of the second diode to a VDD line, and
the fourth diode connected from the output of the second diode to a VSS line.