Patent ID: 11908515
Assignee: HEFEI RELIANCE MEMORY LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. The apparatus of claim 1, wherein the multiple memory cells further comprise fifth, sixth, seventh, and eighth memory cells, and wherein:
the source line is a first source line;
a first transistor of the fifth memory cell is electrically coupled to a first transistor of the sixth memory cell and a second source line;
a first transistor of the seventh memory cell is electrically coupled to a first transistor of the eight memory cell and the second source line;
the resistive memory element of the fifth memory cell is coupled to the resistive memory element of the sixth memory cell and a third bit line;
the resistive memory element of the seventh memory cell is coupled to the resistive memory element of the eighth memory cell and a fourth bit line;
the first word line is electrically coupled to a second transistor of the fifth memory cell and a second transistor of the seventh memory cell;
the second word line is electrically coupled to a second transistor of the sixth memory cell and a second transistor of the eighth memory cell;
the third word line is electrically coupled to the first transistor of the fifth memory cell and the first transistor of the seventh memory cell; and
the fourth word line is electrically coupled to the first transistor of the sixth memory cell and the first transistor of the eighth memory cell.