Patent ID: 11907772
Assignee: GRAPHCORE LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A device comprising:
a processing unit comprising at least one processor configured to:
participate in barrier synchronisations, each of which separates a compute phase of the at least one processor from an exchange phase for the at least one processor; and
exchange sync messages with a sync controller hardware unit so as to co-ordinate each of the barrier synchronisations; and
sync trace circuitry configured to:
receive one or more of the sync messages; and
in response to each of the one or more of the sync messages, provide sync trace information for output from the device, the sync trace information comprising timing information associated with the respective sync message,
wherein for a first of the one or more of the sync messages, the respective sync trace information comprises identification of a sync group for one of the barrier synchronisations that is associated with the first of the one or more of the sync messages, and
wherein the sync controller hardware unit comprises a plurality of interfaces, each of which is associated with a different sync group, wherein the sync trace circuitry is configured to, for the first of the one or more of the sync messages, determine the identification of the sync group in dependence upon which of the plurality of interfaces the first of the one or more of the sync messages is issued or received on.