Patent ID: 11876522
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A duty-cycle (DC) corrector circuit, comprising:
a delay-locked loop (DLL) circuit; and
a duty-cycle correction (DCC) circuit connected to the DLL circuit, wherein the DCC circuit comprises:
a duty adjusting (DA) circuit operable to receive a clock_in signal and output a delayed first signal, the DA circuit further operable to adjust a duty cycle of the delayed first signal based on receipt of a duty control signal;
a pulse generator (PG) circuit operably connected to the DA circuit, the PG circuit operable to receive the delayed first signal and a delayed second signal and output a first pulse signal and a second pulse signal.