Patent ID: 11942334
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A microelectronic assembly, comprising:
a package substrate having a layer;
a first conductive feature having a first thickness and a first width in the layer of the package substrate, wherein the first conductive feature is rectilinear; and
a second conductive feature having a second thickness and a second width in the layer of the package substrate, wherein:
the first and second conductive features each have straight top, bottom, and side surfaces, wherein the side surfaces are at a 90 degree angle to the top and bottom surfaces;
the bottom surface of the second conductive feature is coplanar with the bottom surface of the first conductive feature;
the second conductive feature is rectilinear, wherein the first thickness is greater than the second thickness and the first width is greater than the second width, and wherein the first width is between 5 um and 50 millimeters (mm) and the second width is between 1 um and 75 um;
the first conductive feature is electrically coupled to a power plane; and
the second conductive feature is electrically coupled to a data signal or a data transmission line.