Patent ID: 11880426
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A processor-implemented method comprising:
obtaining a first integer matrix with dimensions m×k and a second integer matrix with dimensions k×n for matrix multiplication within a processor, wherein the first integer matrix and the second integer matrix employ a two's complement variable radix point data representation;
distilling the first integer matrix and the second integer matrix into (j×j) submatrices;
configuring dynamically both a variable radix point format and an initial value for an accumulator register;
executing multiply-accumulate (MAC) operations in a pipelined architecture on the (j×j) submatrices of the first integer matrix and the second integer matrix, wherein a third variable radix point format is configured for the result; and
using the executed MAC operations to process data in a data-flow architecture.