Patent ID: 11888030
Assignee: IDEAL POWER INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. The switch assembly of claim 6 further comprising:
a lower-control input coupled to the controller; and
wherein for a second applied voltage across the upper terminal and lower terminal, the second applied voltage having a polarity opposite the first applied voltage, the controller is further configured to:
assert the gate of the lower-main FET to make the lower-main FET conductive, arrange the transistor for conduction, and assert the gate of the upper-main FET to make the upper-main FET conductive such that a second load current flows from the lower terminal to the upper terminal;
sense de-assertion of the lower-control input; and responsive to de-assertion of the lower-control input
de-assert the gate of the upper-main FET to interrupt the second load current and commutate a second shutoff current through the upper-control lead to the upper terminal; and
arrange the transistor to block current flow from the lower terminal to the upper terminal.