Patent ID: 11882689
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A manufacturing method of a memory, comprising:
providing a substrate, on which first fins and second fins are separately disposed, wherein at least two first fins are disposed between adjacent second fins, a spacing between the adjacent first fins is smaller than a spacing between the first fin and the second fin; a surface of the substrate is provided with an isolating structure comprising a first isolating structure and a second isolating structure, the first isolating structure is disposed between the adjacent first fins, and the second isolating structure is disposed between the first fin and the second fin;
forming a dielectric layer on tops of the first fins, side wall surfaces exposed by the isolating structure, tops of the second fins and side wall surfaces exposed by the second isolating structure;
forming work function layers on a surface of the dielectric layer, wherein in a direction parallel to an arrangement direction of the first fins and the second fins, the work function layers on side walls where the at least two first fins are opposite are provided with a first thickness, the work function layers on side walls where the first fins face towards the second fins are provided with a second thickness, and the first thickness is greater than the second thickness; and
forming a conductive layer on surfaces of the work function layers.