Patent ID: 11923252
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 0:
1. A method for manufacturing a semiconductor device, comprising:
alternatingly stacking first epitaxial layers and second epitaxial layers over a substrate in a vertical direction;
patterning the first epitaxial layers and the second epitaxial layers to form a fin structure;
removing the first epitaxial layers of the fin structure thereby forming nanostructures from the second epitaxial layers of the fin structure;
recessing middle portions of the nanostructures to form recessed middle portions of the nanostructures;
forming silicon germanium layers around the recessed middle portions of the nanostructures; and
forming a gate structure around the silicon germanium layers.