Patent ID: 11928414
Assignee: INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 18:
19. The pin line-out design method for the chip according to claim 1, wherein determining the total number of the low-speed pins according to the position information of all low-speed pins, and determining the number of the second line-out layers required by all low-speed pins according to the total number of the low-speed pins comprises:
allocating two line-out layers for the low-speed pins on the chip;
when the two line-out layers are not sufficient for the wiring design of all the low-speed pins on the chip, connecting the remaining low-speed pins not suffered by the wiring design to an idle position of the remaining line-out layers through via holes to carry out a line-out design in the idle position.