Patent ID: 11928523
Assignee: GRAPHCORE LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 22:
23. A non-transitory computer readable medium storing a computer program comprising a plurality of sets of computer readable instructions, which when executed by a plurality of processors of a processing unit cause a method to be performed for synchronising a first processing device with a second processing device and a third processing device, the first processing device comprising the processing unit, and the plurality of processors comprising a first set of processors and a second set of processors, the method comprising:
the first set of processors participating in a first barrier synchronisation enforced between the first set of processors and a third set of processors belonging to the second processing device, wherein the first barrier synchronisation separates a first compute phase from a first exchange phase;
the first set of processors, during the first exchange phase, exchanging data with the third set of processors;
the second set of processors participating in a second barrier synchronisation enforced between the second set of processors and a fourth set of processors belonging to the third processing device, wherein the second barrier synchronisation separates a second compute phase from a second exchange phase;
the second set of processors, during the second exchange phase, exchanging data with the fourth set of processors,
wherein the first exchange phase overlaps in time with the second exchange phase; and
wherein the first processing device comprises an external sync controller comprising circuitry configured to:
coordinate the first barrier synchronisation between the first set of processors and the third set of processors by exchanging first sync messages with the second processing device; and
coordinate the second barrier synchronisation between the second set of processors of the and the fourth set of processors by exchanging second sync messages with the third processing device.