Patent ID: 11915135
Assignee: ZHEJIANG LAB
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. The graph compiling and optimization method for neural network computation according to claim 1, wherein the step S5 specifically comprises the following sub-steps:
S51: defining that a node V1 rigorously dominates a node V2, wherein the node V1 dominates the node V2, the node V1 is a predecessor node of the node V2, and V1≠V2; and
S52: defining a dominating edge of the node V1, the dominating edge comprising a set of all nodes Vi that satisfy the following conditions: the node V1 dominates a predecessor node of the node Vi, and the node V1 does not rigorously dominate the node Vi.