Patent ID: 11901410
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 0:
1. A method comprising:
forming an opening through a multilayer stack and into a substrate;
depositing a first semiconductor material, the first semiconductor material comprising a first percentage volume of germanium;
depositing a second semiconductor material adjacent to the first semiconductor material, the second semiconductor material being deposited below a bottommost surface of the first semiconductor material, the second semiconductor material comprising a second percentage volume of germanium that is greater than the first percentage volume of germanium;
removing sacrificial layers of the multilayer stack, the second semiconductor material being electrically coupled to a stack of nanostructures;
prior to the depositing the first semiconductor material, depositing a dielectric material in the opening;
forming an inner spacer between a first nanostructure and a second nanostructure of the stack of nanostructures from the dielectric material; and
after the depositing the first semiconductor material, removing excess dielectric material at the bottom of the opening using the first semiconductor material to protect the inner spacer.