Patent ID: 11880052
Assignee: APPLIED MATERIALS, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A semiconductor structure comprising:
a semiconductor substrate;
a metal layer overlying the semiconductor substrate;
a spacer layer defining a via, wherein the via is characterized by:
a sloped sidewall extending to the metal layer; and
a floor comprising an upper surface of the metal layer;

a mirror layer overlying the spacer layer, the sloped sidewall, and the floor, the mirror layer defining a recess at a position of the via; and
an oxide inclusion filling the recess;
a distributed Bragg Reflector (DBR) overlying the mirror layer and the oxide inclusion; and
a metal pixel via extending between an upper surface of the DBR and the metal layer, the metal pixel being electrically isolated from the mirror layer.