Patent ID: 11954347
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory system comprising:
a plurality of memory devices including first and second memory devices, wherein each of the first and second memory devices includes a plurality of memory blocks, and memory blocks of the first and second memory devices form superblocks, and wherein the superblocks include a first superblock that includes memory blocks of the first and second memory devices and a second superblock that includes memory blocks of the first and second memory devices; and
a controller coupled to the plurality of memory devices to control operations performed on the plurality of memory devices, wherein the controller includes:
a first core unit configured to perform a first search operation for searching for a first unstable memory region in a first memory block in the first memory device; and
a second core unit configured to perform a second search operation for searching for a second unstable memory region in a second memory block in the second memory device,
wherein the first search operation and the second search operation are performed in parallel,
wherein the first unstable memory region is a memory region on which a last write operation is performed in the first memory block before an abnormal event occurs, and
wherein the second unstable memory region is a memory region on which a last write operation is performed in the second memory block before the abnormal event occurs.