Patent ID: 11888056
Assignee: FAST SIC SEMICONDUCTOR INCORPORATED
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A silicon carbide MOS-gated semiconductor device, comprising:
a silicon carbide substrate;
a drift layer of a first conductivity type disposed on the substrate, the drift layer has a main surface;
a first doped region of a second conductivity type opposite to the first conductivity type disposed in the drift layer, the first doped region forms a plurality of first p-n junctions and a plurality of JFET regions with the drift layer, wherein the first doped region comprises a plurality of first extending portions, a plurality of body portions and a plurality of first connecting portions, the first extending portions are extended along a second horizontal direction and arranged side by side and spaced apart, the body portions and the first connecting portions are extended along a first horizontal direction and arranged alternatively between two of the first extending;
a second doped region of the first conductivity type disposed within the first doped region, the second doped region forms a plurality of second p-n junctions with the first doped region, a plurality of channel regions are defined between the first p-n junctions and the second p-n junctions along the main surface;
a plurality of third doped regions of the second conductivity type disposed in the body portions of the first doped region and surrounded by the second doped region;
a gate insulating layer formed on the main surface;
a gate electrode being formed on the gate insulating layer and comprising a gate bus region and an active region, wherein the active region of the gate electrode comprises a plurality of gate electrode openings and a minimum width (WO of the gate electrode between two adjacent gate electrode openings is satisfied the following formula:

Wg>Wjfet+2×Lch+2×Lx 

 wherein Lch represents a channel length of the channel regions, Wjfet represents a minimum width of the JFET regions, and Lx represents a minimum overlapping length between the gate electrode and the second doped region;
an interlayer dielectric layer formed on the gate electrode; and
a metal layer, formed on the interlayer dielectric, comprising a first portion of the metal layer and a second portion of the metal layer electrically being isolated from each other, the first portion of the metal layer disposed above the active region of the gate electrode and the second portion of the metal layer disposed above the gate bus region of the gate electrode, wherein the first portion of the metal layer being electrically coupled to the second doped region and the third doped regions through a plurality of source contacts formed through the plurality of gate electrode openings, and the second portion of the metal layer being electrically coupled to the gate electrode through a gate contact.