Patent ID: 11972953
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 1:
2. The semiconductor structure manufacturing method of claim 1, wherein the sixth patterns further cover a sub-active area at an end of the continuous active area at the edge of the array area, the sub-active area having a length less than that of the discrete active area, and wherein performing layer-by-layer etching to transfer the first patterns, the second patterns, and the third patterns to the substrate to form an array of discrete active areas comprises:
transferring, using the first mask layer, the second mask layer, the third mask layer, and the fourth mask layer as masks, the first patterns, the second patterns, the third patterns, and the sixth patterns to the substrate to form the array of the discrete active areas, wherein there is no sub-active area at the edge of the array area.