Patent ID: 11936386
Assignee: SK HYNIX INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 4:
5. The clock transfer circuit of claim 4, wherein the bias control circuit includes a first bias control subcircuit configured to provide the first bias control signal and a second bias control subcircuit configured to provide the second bias control signal,
wherein the first bias control subcircuit comprises:
a first MOS transistor;
a first plurality of resistors generating gate voltage of the first MOS transistor by dividing the power supply voltage; and
a first resistor coupled to a drain of the first MOS transistor, and
wherein the first bias control signal is provided from the drain of the first MOS transistor, and

wherein the second bias control subcircuit comprises:
a second MOS transistor;
a second plurality of resistors generating gate voltage of the second MOS transistor by dividing the power supply voltage; and
a second resistor coupled to a drain of the second MOS transistor, and
wherein the second bias control signal is provided from the drain of the second MOS transistor.