Patent ID: 11923199
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method, comprising:
forming a structure over a substrate;
forming a spacer layer on the structure, wherein the spacer layer has a recess;
forming a mask layer over the spacer layer and in the recess, the mask layer comprising a first layer, a second layer over the first layer, and a third layer over the second layer;
patterning the third layer of the mask layer;
etching the first layer and the second layer of the mask layer to form an opening to expose the recess of the spacer layer, wherein the opening in the second layer has a first width; and
removing the second layer using a wet etchant, wherein the opening in the third layer has a second width, and the second with is greater than the first width.