Patent ID: 11955463
Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 26:
27. An apparatus comprising:
a substrate;
a die stack on the substrate, the die stack comprising a plurality of dies including:
a first integrated device die comprising a first integrated circuit;
a second integrated device die comprising a second integrated circuit, the first integrated device die hybrid bonded to a first bonding layer on the second integrated device die; and
a dummy die directly bonded to a second bonding layer on an underlying die of the die stack without an intervening adhesive;

a first lateral die support layer disposed along at least a portion of a sidewall of the first integrated device die, an entirety of the first lateral die support layer disposed laterally outside a footprint of the first integrated device die; and
a second lateral die support layer disposed laterally adjacent at least a portion of the first lateral die support layer, an entirety of the second lateral die support layer disposed laterally outside the die stack.