Patent ID: 11973044
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. The apparatus of claim 16, wherein:
the memory die has a first end and a second end opposite the first end;
the memory die has a middle that is between the first end of the memory die and the second end of the memory die;
the control die has a first end corresponding in location to the first end of the memory die;
the control die has a second end corresponding in location to the second end of the memory die;
the control die has a middle that is between the first end of the control die and the second end of the control die;
the first top metal layer runs from the first end of the memory die to the second end of the memory die;
the first top metal layer connects to I/O pads at the first end of the memory die;
the first metal interlayer segment is positioned at and connects to the first top metal layer at the middle of the memory die; and
the first electrical pathway runs from the second interface to the second middle metal layer and then to at least one electrical circuit of the plurality of electrical circuits at the middle of the control die.