Patent ID: 11901237
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A device comprising:
a first semiconductor fin and a second semiconductor fin over a substrate;
an isolation dielectric over the substrate and surrounding bottom portions of the first semiconductor fin and the second semiconductor fin;
a gate structure over the first semiconductor fin and the isolation dielectric;
a dielectric feature between the first semiconductor fin and the second semiconductor fin and directly over the isolation dielectric;
a helmet layer wrapping the dielectric feature; and
an interlayer dielectric (ILD) layer laterally surrounding the gate structure, wherein the dielectric feature comprises:
a first portion in contact with the gate structure; and
a second portion embedded in the ILD layer, wherein a bottom surface of the first portion is lower than a bottom surface of the second portion.