Patent ID: 11928497
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A computer-implemented method, comprising:
receiving a request to perform a transaction in persistent memory at a first node having a central processing unit, the persistent memory having no fixed block size, the persistent memory being directly load/store addressable by the central processing unit;
implementing the transaction within a volatile transaction cache at the first node, the volatile transaction cache having a shadow copy of data stored in persistent memory at the first node, wherein write modifications made during the transaction are made directly on the shadow copy;
determining parity data for the transaction;
sending the parity data to a parity node; and
transferring results of the transaction from the volatile transaction cache to the persistent memory at the first node,
wherein each row within the persistent memory has an associated transaction ID,
wherein shadow writes happen concurrently, and parity updates within the same row occur serially.