Patent ID: 11881177
Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 6:
7. A display device comprising:
a display portion comprising:
a first transistor comprising:
a first gate electrode over a substrate;
a fourth insulating layer over the first gate electrode, the fourth insulating layer having a region which functions as a first gate insulating layer; and
a first semiconductor layer over the fourth insulating layer, the first semiconductor layer having a channel formation region of the first transistor;

a second transistor over the first transistor, the second transistor comprising:
a second gate electrode over the first semiconductor layer;
a fifth insulating layer over the second gate electrode, the fifth insulating layer having a region which functions as a second gate insulating layer;
a second semiconductor layer over the fifth insulating layer, the second semiconductor layer having a channel formation region of the second transistor;
a third conductive layer over the second semiconductor layer, the third conductive layer having a region which functions as a source electrode; and
a fourth conductive layer over the second semiconductor layer, the fourth conductive layer having a region which functions as a drain electrode; and

a light-emitting element over the second transistor, the light-emitting element comprising:
a first conductive layer over the third conductive layer and the fourth conductive layer;
an EL layer over the first conductive layer; and
a second conductive layer over the EL layer; and

a scan line driver circuit comprising a third transistor, the third transistor comprising:
a third gate electrode over the substrate;
the fourth insulating layer over the third gate electrode; and
a third semiconductor layer over the fourth insulating layer,

wherein the display device further comprises:
a first insulating layer over the first semiconductor layer;
a second insulating layer over the second semiconductor layer; and
a third insulating layer over the second insulating layer,

wherein the second insulating layer has a region in contact with each of the second semiconductor layer, the third conductive layer, the fourth conductive layer, and the fifth insulating layer, and
wherein the second semiconductor layer comprises an oxide semiconductor.