Patent ID: 11962309
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G  Y | IPC H

Claim 4:
5. The phase adjusting circuit of claim 4, wherein the first detection sub-circuit comprises a first inverter, a first transmission gate, and a first NAND gate; and the second detection sub-circuit comprises a second inverter, a second transmission gate, and a second NAND gate;
an input terminal of the first inverter is configured to receive the second clock signal, an input terminal of the first transmission gate is configured to receive the first clock signal, and two input terminals of the first NAND gate are connected to an output terminal of the first inverter and an output terminal of the first transmission gate respectively, and an output terminal of the first NAND gate is configured to output the first detection signal; and
an input terminal of the second inverter is configured to receive the third clock signal, an input terminal of the second transmission gate is configured to receive the second clock signal, and two input terminals of the second NAND gate are connected to an output terminal of the second inverter and an output terminal of the second transmission gate respectively, and an output terminal of the second NAND gate is configured to output the second detection signal.