Patent ID: 11900995
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A method comprising:
accessing a bitcell in an array of bitcells with a wordline and a bitline;
performing a precharge operation on the bitline with a bitline precharge signal that precharges the bitline after a read cycle and before a write cycle; and
extending precharge time of the precharge operation between the read cycle and the write cycle by modulating a wordline signal on the wordline with early cut-off of the wordline signal on the wordline during the read cycle,
wherein modulating the wordline signal is based on an early reset signal having a falling edge at a beginning of the early reset signal that triggers a falling edge of the wordline signal during the read cycle, and
wherein the falling edge of the wordline signal triggers a falling edge of the bitline precharge signal.