Patent ID: 11962313
Assignee: ATI TECHNOLOGIES ULC
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A method of clock frequency adjustment in an oscillator circuit comprising:
connecting a first delay line to a regulated supply voltage and causing the first delay line to transmit a first delayed signal at a first delay proportional to the regulated supply voltage;
connecting a second delay line to a droopy supply voltage and causing the second delay line to transmit a second delayed signal at a second delay proportional to the droopy supply voltage;
connecting the first and second delay lines to first and second inputs of an edge detector that generates an output clock, the output clock exhibiting a voltage dependent frequency performance curve having a slope dependent at least on the second delay and a delay characteristic of the edge detector;
feeding the output clock as an input to the first and second delay lines; and
adjusting the slope by altering the delay characteristic of the edge detector relative to at the one of the first and second delays and compensating for a change in frequency of the oscillator circuit due to the slope adjustment.