Patent ID: 11869892
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. The semiconductor device structure of claim 10, further comprising:
a second source/drain epitaxial feature disposed in a P-type region;
a second conductive feature disposed over the second source/drain epitaxial feature;
a second fin in contact with the second source/drain epitaxial feature, wherein the second fin comprises a second semiconductor layer;
a second gate dielectric layer in contact with the second fin;
a second gate electrode layer disposed over the second gate dielectric layer; and
a second spacer in contact with the second fin, wherein the bottom of the second portion and the first fin define a first interface, and the second spacer and the second fin define a second interface, and each of the first and second interfaces has a slope.