Patent ID: 11901432
Assignee: GENESIC SEMICONDUCTOR INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method comprising:
obtaining a Silicon Carbide (SiC) wafer comprising a first conductivity type drift layer on a first conductivity type substrate;
forming a first mask layer and patterning the first mask layer on the SiC wafer;
implanting ions of a second conductivity type to form a first well region;
depositing a second mask layer over the first mask layer;
etching the second mask layer to form a sidewall spacer over the first mask layer;
subsequently implanting ions of a first conductivity type to form a source region; and
subsequently removing the first mask layer and the second mask layer; and
wherein the method further comprises: patterning a gate metal layer in a peripheral region to result in a segmented pattern and disjointed gate fingers, wherein the disjointed gate fingers comprise an electrical connection at selected locations.