Patent ID: 11886372
Assignee: CADENCE DESIGN SYSTEMS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. A system comprising:
a processor; and
a protocol stack configured to: receive first and second messages from the processor; generate first and second transaction layer (TL) packets based on respective first and second messages; evaluate message channel information identifying a message channel for the first TL packet relative to channel type data to determine a channel type of TL packet for the first TL packet, wherein the message channel information identifies the channel type of TL packet for the first TL packet as a cache channel type or as a memory channel type;
identify a set of slot formats for the respective slot in response to determining that the first TL packet is a respective type of TL packet;
select a respective slot format of the set of slot formats for a respective slot for packing the first and second TL packets during flit generation based on a message type of the first and second TL packets;
generate a single flit comprising a set of slots, wherein the set of slots include the respective slot having the respective slot format and is packed with the first and second TL packets, wherein packing the first TL packet and the second TL packet into the respective slot causes the single flit to include both the first TL packet and the second TL packet; and
transmit the flit cross a lane of a lock to a receiving device.