Patent ID: 11971821
Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. The computing system as claimed in claim 12, further comprising:
a second processor fabricated on a second die, including a third core and a second last-level cache, wherein the third core includes a third in-core cache module;
wherein:
the write-back and invalidation request is further provided to the third core through the memory ordering buffer of the first core and a channel between the first die and the second die, and then passed to the second last-level cache through the third in-core cache module of the third core; and
in response to the write-back and invalidation request, the second last-level cache searches itself to determine which cache lines within the second last-level cache match the designated key identification code, wherein: if a matched cache line has been modified and does not exist in any upper-level cache, the second last-level cache writes back the matched cache line to the system memory; and, whether modified or not, all matched cache lines within the second last-level cache are invalidated;
after all matched cache lines within the second last-level cache are invalidated, the second last-level cache returns a third synchronization signal to the third in-core cache module; and
in response to the third synchronization signal, the third in-core cache module in the waiting state is awakened to search itself to determine which cache lines within the third in-core cache module match the designated key identification code, wherein: if a matched cache line has been modified, the third in-core cache module writes back the matched cache line to the system memory; and, whether modified or not, all matched cache lines within the third in-core cache module are invalidated.