Patent ID: 11880597
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. The read operation circuit according to claim 1, wherein the data buffer module comprises:
a plurality of logic NAND gates, two input terminals of each of the plurality of logic NAND gates being configured to receive the enable signal and the current read data respectively;
a plurality of fifth inverters, an input terminal of each of the plurality of fifth inverters being configured to receive the enable signal;
a plurality of logic NOR gates, two input terminals of each of the plurality of logic NOR gates being configured to receive the current read data and connected to each of the plurality of fifth inverters respectively;
a plurality of PMOS transistors, a gate of each of the plurality of PMOS transistors being connected to an output terminal of each of the plurality of logic NAND gates, and a drain of each of the plurality of PMOS transistors being connected to the global bus; and
a plurality of NMOS transistors, a gate of each of the plurality of NMOS transistors being connected to an output terminal of each of the plurality of logic NOR gates, and a drain of each of the plurality of NMOS transistors being connected to the global bus and the drain of each of the plurality of PMOS transistors.