Patent ID: 11961787
Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A method for manufacturing a semiconductor device, comprising:
stacking a plurality of element layers vertically, wherein each element layer of the plurality of element layers comprises a plurality of semiconductor elements and a metallization layer for the plurality of semiconductor elements;
providing a vertical stack comprising the plurality of element layers on a carrier substrate, and forming an interconnection structure laterally adjoined the vertical stack on the carrier substrate, wherein the interconnection structure comprises an electrical isolation layer and a conductive structure in the electrical isolation layer,
wherein the method further comprises: controlling a height of the conductive structure in the interconnection structure so that at least a part of a conductive structure in the metallization layer of the each element layer is in contact with and electrically connected to the conductive structure at a corresponding height in the interconnection structure in a lateral direction.