Patent ID: 11900979
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 21:
22. A probabilistic in-memory computing system, comprising:
a plurality of p-bit arrays, wherein each p-bit array of the plurality of p-bit arrays is connected to at least one other p-bit array of the plurality of p-bit arrays, and each p-bit array comprises:
a plurality of input lines configured to receive respective input voltages,
a plurality of accumulation lines intersecting the plurality of input lines, and
a plurality of probabilistic bit devices (p-bits), each p-bit of the plurality of p-bits includes a first terminal coupled to an input line of the plurality of input lines, a second terminal coupled to an accumulation line of the plurality of accumulation lines, and at least one bias terminal capable of receiving a bias voltage, wherein the bias voltage applied to the at least one bias terminal of each p-bit is to cause a time-varying resistance of each p-bit to have a probabilistic resistance value based on a probability distribution of a stochastic neural network (SNN); and

processor circuitry communicatively coupled to the plurality of p-bit arrays to provide data for modulation of the respective input voltages,
wherein the respective input voltages to be applied to individual input lines of the plurality of input lines is to cause current to flow through p-bits of the plurality of p-bits connected to the individual input lines and is accumulated on corresponding accumulation lines of the plurality of accumulation lines.