Patent ID: 11942696
Assignee: ANOKIWAVE, INC.
Field: Telecommunications (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 9:
10. An RFIC chip comprising:
a common interface circuit including a first common interface and a second common interface;
a plurality of element interface circuits coupled to the common interface circuit, each element interface circuit including a first element interface including a first 180 degree phase shifter and a second element interface including a second 180 degree phase shifter;
programmable channel swapping circuitry configured to selectively switch between a first channel configuration and a second channel configuration based on a channel swap parameter, the first channel configuration coupling the first common interface to the first element interface of each element interface circuit and coupling the second common interface to the second element interface of each element interface circuit, the second channel configuration coupling the first common interface to the second element interface of each element interface circuit and coupling the second common interface to the first element interface of each element interface circuit;
programmable phase rotation circuitry configured to selectively enable or disable the 180 degree phase shifter of each element interface based on a corresponding element rotation parameter;
at least one memory storing a set of gain and phase parameters for each element interface circuit including at least a first set of gain and phase parameters for a first element interface circuit and a second set of gain and phase parameters for a second element interface circuit; and
programmable element swapping circuitry configured selectively switch between a first element configuration and a second element configuration based on an element swap parameter, the first element configuration providing the first set of gain and phase parameters to the first element interface circuit and providing the second set of gain and phase parameters to the second element interface circuit, the second element configuration providing the first set of gain and phase parameters to the second element interface circuit and providing the second set of gain and phase parameters to the first element interface circuit.