Patent ID: 11914439
Assignee: ROHM CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A synchronous reset signal generation circuit configured to generate a synchronous reset signal by synchronizing an asynchronous reset signal with a clock signal, the synchronous reset signal generation circuit comprising:
a synchronous reset signal output circuit
having L flip-flops connected in a cascade arrangement and
configured to output the synchronous reset signal from a final-stage flip-flop among the L flip-flops;

a first error determination signal output circuit
having M flip-flops connected in a cascade arrangement and
configured to output a first error determination signal from a final-stage flip-flop among the M flip-flops;

a second error determination signal output circuit
having N flip-flops connected in a cascade arrangement and
configured to output a second error determination signal from a final-stage flip-flop among the N flip-flops; and

a fault determination circuit configured to determine presence or absence of a fault in the synchronous reset signal generation circuit based on the synchronous reset signal, the first error determination signal, and the second error determination signal,
wherein
the first error determination signal is input to an initial-stage flip-flop among the N flip-flops,
the clock signal and the asynchronous reset signal are commonly input to the L, M, and N flip-flops, and
L, M, and N are integers fulfilling M≥2, L≥M+1, and M+N≥L+1 simultaneously.