Patent ID: 11915736
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 15:
16. A memory system, comprising:
a plurality of memory cells arranged in rows and columns, each of the plurality of memory cells having a gate, a drain, a source, channel material situated adjacent the drain and the source, and ferroelectric material situated between the gate and the channel material;
a plurality of word lines, each of the word lines having a corresponding row, wherein each of the word lines is coupled to the gates of the memory cells in the corresponding row;
a plurality of bit lines and a plurality of source lines, each of the bit lines and each of the source lines having a corresponding column, wherein each of the bit lines is connected to the drain of the memory cells in the corresponding column and each of the source lines is connected to the source of the memory cells in the corresponding column;
wherein in an erase operation, a first word line connected to a selected memory cell is configured to receive a negative voltage and a second word line connected to a first unselected memory cell is configured to receive a ground voltage, and a first bit line and a first source line of the selected memory cell and of the first unselected memory cell are configured to receive a positive voltage.