Patent ID: 11861279
Assignee: KEPLER COMPUTING INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A non-transitory machine-readable storage media having machine-readable instructions stored thereon that when executed cause one or more machines to perform a method comprising:
receiving one or more inputs describing a functionality or circuit connectivity of an electrical circuit;
determining whether majority gates or minority gates are to be used in synthesizing the electrical circuit, wherein the majority gates or the minority gates have a variety of fan-ins;
determining whether a number of input bits for the electrical circuit comprising the majority gates or minority gates is less than or equal to a first threshold, where the electrical circuit comprises the majority gates or the minority gates;
synthesizing the electrical circuit using a truth table, binary integer programming, or satisfiability formulation if it is determined that the number of input bits for the electrical circuit having the majority gates or the minority gates is less than or equal to the first threshold;
minimizing a number of inverters after synthesizing the electrical circuit to generate a synthesized majority or minority graph, wherein minimizing the number of inverters comprises:
receiving a majority or minority inverter graph, wherein the electrical circuit is associated with the majority or minority inverter graph;
collecting a list of majority or minority gates, for an individual depth, in an order, wherein the list of majority or minority gates includes ‘r’ majority or minority gates;
for the individual depth, selecting the ‘r’ majority or minority gates;
generating a function of ‘r’ new majority or minority inverter graphs from the majority or minority inverter graph at the individual depth;
simplifying the function of the ‘r’ new majority or minority inverter graphs to generate a simplified function of the ‘r’ new majority or minority inverter graphs; and
determining a second majority or minority inverter graph, that results in a smallest delay in the individual depth, based on the simplified function of the ‘r’ new majority or minority inverter graphs.