Patent ID: 11927625
Assignee: POWERCHIP SEMICONDUCTOR MANUFACTURING CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 9:
10. A voltage contrast defect analysis system, comprising:
an electron beam inspection machine configured to perform a voltage contrast defect detection on a die to be tested to find out a defect address of a voltage contrast defect;
a scanning electron microscope configured to obtain a first scanning electron microscope image at the defect address of the die to be tested; and
an electronic apparatus coupled to the electron beam inspection machine and the scanning electron microscope, and comprising:
a memory configured to store modules; and
a processor coupled to the memory, wherein the processor is configured to read and execute the modules to perform following operations,
wherein the processor measures a first critical dimension of the first scanning electron microscope image at the defect address of the die to be tested,
wherein the processor compares the first critical dimension on the die to be tested with a corresponding second critical dimension on a reference die where no voltage contrast defect occurs at the defect address to determine whether the first critical dimension and the second critical dimension are the same, and
wherein the scanning electron microscope is configured to obtain a second scanning electron microscope image at the defect address of the die to be tested, an image quality of the first scanning electron microscope image is higher than an image quality of the second scanning electron microscope image, and
the processor determines whether there is a physical defect according to the second scanning electron microscope image.