Patent ID: 11860803
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 8:
9. A memory device comprising:
a buffer die configured to receive first and second broadcast commands, a processing command and external data from an external device, transmit the first and second broadcast commands and the processing command to a common command and address bus, and transmit the external data to a common data input/output bus; and
a plurality of core dice stacked on the buffer die, wherein the plurality of core dice comprise:
a first core die comprising a first memory cell array, a first command decoder configured to decode the first broadcast command transmitted through the common command and address bus, and a first data input/output circuit configured to output first data of the first memory cell array to the common data input/output bus under control of the first command decoder; and
a second core die comprising a processing circuit, a second memory cell array, a second command decoder configured to decode the second broadcast command transmitted through the common command and address bus, and a second data input/output circuit configured to receive the first data of the first memory cell array from the common data input/output bus under control of the second command decoder,

wherein the processing circuit is configured to decode the processing command and generate second data by performing a processing operation on the first data and the external data.