Patent ID: 11917749
Assignee: MARVELL ISRAEL (M.I.S.L) LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A method of fabricating an electronic device, the method comprising:
providing an integrated circuit device package having a plurality of differential signal pin pairs and a plurality of ground pins, each differential signal pin pair and ground pin extending in a first direction orthogonal to a surface of the integrated circuit device package, each differential signal pin pair of the plurality of differential signal pin pairs comprising a positive signal pin and a negative signal pin, wherein each of a first subset of differential signal pin pairs is arranged relative to each other differential signal pin pair of the first subset in a first orientation at a vertex of a regular array of orthogonal rows and columns and along a line parallel to rows of the array, and each of a second subset of differential signal pin pairs is arranged relative to each other differential signal pin pair of the second subset in a second orientation at a vertex of the array and along a line parallel to columns of the array, and wherein at least one ground pin of the plurality of ground pins is arranged between a first differential signal pin pair and a second differential signal pin pair, the at least one ground pin being disposed (a) along a line connecting a first vertex of the regular array of rows and columns at which the first differential signal pin pair is located to a second vertex of the regular array of rows and columns at which the second differential signal pin pair is located, and (b) along a line connecting a first differential signal pin in the first differential signal pin pair to a first differential signal pin in the second differential signal pin pair, and (c) along a line connecting a second differential signal pin in the first differential signal pin pair to a second differential signal pin in the second differential signal pin pair, to shield at least one differential signal pin in the first differential signal pin pair from signals in the second differential signal pin pair, or to shield at least one differential signal pin in the second differential signal pin pair from signals in the first differential signal pin pair;
for each respective differential signal pin pair of the plurality of differential signal pin pairs, forming, on a surface of a substrate, a pair of signal pads being configured in a pattern to accept the corresponding pair of pins, each pair of pads configured to accept a differential signal pin pair positioned at a vertex of the array; and
forming, on the surface of the substrate, ground pads configured in a pattern to accept the corresponding ground pins.