Patent ID: 11863190
Assignee: nan
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. A compound sequential circuit comprising:
a first clock-activated transistor electrically coupled to a first shared clock node;
a second clock-activated transistor coupled to a second shared clock node;
a third clock-activated transistor coupled to a third shared clock node;
a plurality of flip-flops, wherein each flip-flop of the plurality of flip-flops comprise:
a latch electrically coupled to the second shared clock node and the third shared clock node;
a first buffer electrically coupled to the first shared clock node;
a second buffer electrically coupled to the first shared clock node;
a first keeper sub-circuit electrically coupled to the third shared clock node and at least one of a first output or a second output of the latch;
a second keeper sub-circuit electrically coupled to the third shared clock node and the second output of the latch, wherein first keeper sub-circuit is electrically coupled to the first output of the latch;
a first sequence detector comprising the first buffer and electrically couples to the first output of the latch and to an inverted input signal;
a second sequence detector comprising the second buffer and electrically couples to the second output of the latch and to an input signal; and
wherein the first keeper sub-circuit is gated by the first output of the latch and the inverted input signal, and wherein the second keeper sub-circuit is gated by the second output of the latch and the input signal.