Patent ID: 11935607
Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An integrated circuit die including a plurality of memory sectors, each memory sector including a memory array, the integrated circuit die comprising:
a voltage regulator including a first transistor driven by an output voltage to thereby generate a gate voltage, the output voltage being generated based upon a difference between a constant current and a leakage current;
a selection circuit configured to selectively couple the gate voltage to a selected one of the plurality of memory sectors; and
a leakage detector circuit configured to:
drive a second transistor with the output voltage to thereby generate a copy voltage based upon a difference between a variable current and a replica of the constant current;
increase the variable current in response to the copy voltage being greater than the gate voltage; and
assert a leakage detection signal in response to the copy voltage being less than the gate voltage, the leakage detection signal indicating excess leakage within the memory array of the selected one of the memory sectors.