Patent ID: 11874786
Assignee: BYD COMPANY LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 9:
10. A front end processor (FEP), comprising a primary FEP and a secondary FEP, wherein
the primary FEP comprises:
a primary memory, configured to store data transmitted by at least one external device;
at least one primary driver, configured to transmit a control instruction to the at least one external device, to acquire data from the at least one external device; and
a primary IO manager, configured to: control the at least one primary driver according to a communication management instruction, and receive status information of the at least one external device; and
the secondary FEP comprises:
a secondary memory, configured to synchronize data from the primary memory of the primary FEP;
at least one secondary driver, configured to receive a diagnosis packet transmitted by the at least one external device, to diagnose, according to the diagnosis packet, whether there is a fault in a communication link between the primary FEP and the at least one external device and a communication link between the secondary FEP and the at least one external device; and
a secondary IO manager, configured to: control the at least one secondary driver according to a channel diagnosis instruction, and transmit the channel diagnosis instruction to the at least one external device by using at least one of the at least one primary driver and the at least one secondary driver, wherein the at least one external device generates a diagnosis packet according to the channel diagnosis instruction, and the secondary IO manager is further configured to: receive status information of the at least one external device, and synchronize data with the primary IO manager.