Patent ID: 11966749
Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 4:
5. A processor, comprising:
at least two sockets, one of which comprises:
a first die, receiving a boot-enable signal and an internal boot-enable signal to execute a boot procedure, and outputting a first boot-completion signal after completing the boot procedure;
a second die, receiving the boot-enable signal and the first boot-completion signal from the first die to execute the boot procedure, and outputting a second boot-completion signal after completing the boot procedure; wherein the second die is electrically connected to the first die through a first communication bus;
the other one of the at least two sockets, comprising:
a third die, receiving the second boot-completion signal from the second die and the internal boot-enable signal to execute the boot procedure, and outputting a third boot-completion signal after completing the boot procedure;
a fourth die, receiving the second boot-completion signal from the second die and the third boot-completion signal from the third die to execute the boot procedure; wherein the fourth die is electrically connected to the third die through a second communication bus;
a memory, electrically connected to the second die and the fourth die;
wherein when the first die executes the boot procedure, the first die accesses the memory through the first communication bus and the second die.