Patent ID: 11955989
Assignee: NANYA TECHNOLOGY CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC H

Claim 15:
16. The test method according to claim 10, wherein in a test scheme for testing a syndrome decoder and a data corrector of an ECC circuit, comprising:
entering the third test mode during a first time period, and generating the parity information according to the normal data and write the parity information into the parity array by the parity/syndrome generator;
entering the first test mode during a second time period after the first time period, updating the normal data with 1 bit error to obtain updated data, writing the updated data to the data array and keeping the parity information unchanged by the parity/syndrome generator; and
re-entering the third test mode during a third time period after the second time period, reading the updated data in the data array to obtain readout data, and generating a test result by comparing the readout data with an expectation data.