Patent ID: 11921843
Assignee: CEREMORPHIC, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. A fault-detecting pipeline processor configured for multi-thread operation, the pipeline processor comprising a plurality of sequential stages, at least one stage operating on a branch instruction to generate branch status including at least one: of a branch direction, branch taken/not_taken, and branch target;
a plurality of execution threads including:
a first thread having an associated first thread_id and execution instructions including control instructions, branch control instructions as a subset of the control instructions, and data instructions;
a second thread having an associated second thread_id and execution instructions comprising only control instructions;

the branch control instructions including at least one of: conditional branch instructions, unconditional branch instructions, no operation (NOP) instructions, branch variable initialization instructions, and branch variable modification instructions associated with a conditional branch instruction;
a fault detector receiving branch status from the pipeline processor accompanied by associated first thread_id and second thread_id;
the fault detector comparing the branch status of the first thread_id and second thread_id to generate a match, the fault detector asserting a fault output when a match is not found.