Patent ID: 11967529
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A semiconductor chip comprising:
a semiconductor substrate comprising an active surface and an inactive surface opposite to each other;
an integrated circuit region on the active surface, the integrated circuit region being sectioned by a cut region;
metal patterns of N levels on the cut region, wherein N is an natural number greater than or equal to 2;
a vertical via connecting one of the metal patterns at a (K−1)th level to one of the metal patterns at a Kth level; and
a low-k dielectric material film surrounding the metal patterns,
wherein upper surfaces of the metal patterns at respective levels are spaced apart from each other,
a number of the metal patterns per unit area at the Kth level is less than a number of the metal patterns per unit area at the (K−1)th level, and K is a natural number between 2 to N, and
an upper surface of the one of the metal patterns at the (K−1)th level contacts the vertical via.