Patent ID: 11889705
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. An integrated chip, comprising:
a first interconnect within a first inter-level dielectric (ILD) layer over a substrate;
a memory device disposed over the first interconnect and surrounded by a second ILD layer;
a second interconnect extending from a top of the second ILD layer to an upper surface of the memory device, wherein the second interconnect comprises a conductive core and a barrier layer, the barrier layer having a horizontally extending surface contacting the conductive core along an interface that is vertically below the upper surface of the memory device; and
sidewall spacers arranged along opposing sides of the memory device, each of the sidewall spacers having a top rectangular portion between and the barrier layer and the memory device and having a vertical side surface in direct contact with the barrier layer.