Patent ID: 11955200
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An integrated circuit (IC) memory device, comprising:
a first command/address (C/A) interface to receive from a memory controller first and second read commands directed to a first bank group of memory for first and second read data;
a second command/address (C/A) interface to receive from the memory controller third and fourth read commands directed to a second bank group of memory for third and fourth read data;
transmit circuitry to transmit the first and second read data via a first data link interface and to transmit the third and fourth read data via a second data link interface;
wherein for a first operating mode, the first and second data are transmitted at a first serialization ratio; and
wherein for a second operating mode, the first and second data are transmitted at a second serialization ratio that is different than the first serialization ratio.