Patent ID: 11879939
Assignee: NXP B.V.
Field: Measurement (Instruments)
Classification: CPC G  H | IPC G  H

Claim 0:
1. An integrated circuit (IC), comprising:
a clocking system configured to generate (i) a first clock signal, (ii) a first clock enable signal that enables division of the first clock signal, and (iii) a second clock signal, wherein the second clock signal is generated based on the first clock signal and the first clock enable signal, wherein during a capture phase of an at-speed testing mode of the IC, the second clock signal is a gated version of the first clock signal and comprises a first clock pulse and a second clock pulse, and wherein the first clock enable signal is de-asserted based on an activation of the capture phase, and during the capture phase, the first clock enable signal transitions to an asserted state based on a pipeline delay associated with the clocking system; and
a testing system that is coupled to the clocking system, and configured to:
determine at least one of a group consisting of (i) a first count of clock pulses of the first clock signal between the activation of the capture phase and the transition of the first clock enable signal, and (ii) a second count of clock pulses of the first clock signal between the first clock pulse and the second clock pulse; and
detect a fault in the clocking system based on at least one of a group consisting of the first count and the second count.