Patent ID: 11960722
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 3:
4. A memory device comprising:
an array of memory cells comprising a plurality of blocks of memory cells; and
a controller configured to access the plurality of blocks of memory cells,
wherein the controller is further configured to:
program a first block of memory cells of the plurality of blocks of memory cells as a multi-level cell (MLC) block;
program a second block of memory cells of the plurality of blocks of memory cells as a triple-level cell (TLC) block; and
following a period after programming the second block of memory cells, merge the first block of memory cells to the second block of memory cells without erasing the second block of memory cells such that the second block of memory cells is programmed as a penta-level cell (PLC) block; and
prior to merging the first block of memory cells to the second block of memory cells, perform a touch up programming operation on one or more memory cells of the second block of memory cells to increase a threshold voltage of each of the one or more memory cells towards a respective desired threshold voltage of each of the one ore more memory cells, and

an error correction code (ECC) engine configured to monitor the second block of memory cells an instruct the controller to perform the touch up programming operation on the one or more memory cells of the second block of memory cells in response to the second block of memory cells comprising a raw bit error rate greater than or equal to a threshold raw bit error rate.