Patent ID: 11947888
Assignee: APPLIED MATERIALS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G  H

Claim 6:
7. A method of baselining a chamber executing a semiconductor manufacturing process, comprising:
running a limited design of experiment (DoE) of wafers with external metrology to baseline chamber performance;
adding wafer outcomes and metrology data from the limited DoE to a hybrid model as a calibration data set, wherein the hybrid model comprises:
a statistical model; and
a physical model, wherein the physical model is generated from a simulation of physical and chemical interactions within a processing tool across a plurality of different processing parameters;

adjusting the model's predictions to account for specific chamber conditions and/or wafer conditions identified by the limited DoE;
predicting optimized process parameters to achieve a desired wafer outcome for wafers processed in the chamber and to provide optimized process parameters;
applying the optimized process parameters to a wafer;
executing the recipe on a plurality of first wafers;
obtaining wafer data from the plurality of first wafers;
obtaining process data from the processing tool relating to the execution of the recipe on the plurality of first wafers; and
providing the wafer data and the process data from the processing of the plurality of first wafers to the hybrid model to generate an updated hybrid model.