Patent ID: 11961822
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 7:
8. The display device of claim 5, wherein the array layer further comprises:
a first power wiring configured to apply a first power voltage to the plurality of pixel drivers;
a second power wiring configured to apply a second power voltage to the plurality of pixel drivers;
a third power wiring configured to supply a third power voltage to the plurality of cathodes;
a scan write wiring configured to transmit a scan write signal to the plurality of pixel drivers;
a scan initialization wiring configured to transmit a scan initialization signal to the plurality of pixel drivers;
a sweep signal wiring configured to transmit a sweep signal to the plurality of pixel drivers;
a first data wiring configured to apply a first data voltage to the plurality of pixel drivers; and
a second data wiring configured to apply a second data voltage to the plurality of pixel drivers, and
a pixel driver of the plurality of pixel drivers corresponding to the emission area comprises:
a first pixel driving circuit unit configured to generate a control current according to the first data voltage of the first data wiring;
a second pixel driving circuit unit configured to generate a driving current supplied to the anode according to the second data voltage of the second data wiring; and
a third pixel driving circuit unit configured to control a period during which the driving current is supplied to the anode according to the control current of the first pixel driving circuit unit,
wherein the first pixel driving circuit unit comprises:
a first transistor configured to generate the control current according to the first data voltage;
a second transistor configured to apply the first data voltage of the first data wiring to a first electrode of the first transistor according to the scan write signal;
a third transistor configured to apply an initialization voltage of an initialization voltage wiring to a gate electrode of the first transistor according to the scan initialization signal;
a fourth transistor connecting the gate electrode of the first transistor and a second electrode of the first transistor according to the scan write signal; and
a first capacitor located between the sweep signal wiring and the gate electrode of the first transistor.