Patent ID: 11960408
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. The semiconductor memory device of claim 1, wherein:
the first upper sub-latch blocks and the first lower sub-latch blocks intersect a first bit line set,
the second upper sub-latch blocks and the second lower sub-latch blocks intersect a second bit line set,
the third upper sub-latch blocks and the third lower sub-latch blocks intersect a third bit line set,
the fourth upper sub-latch blocks and the fourth lower sub-latch blocks intersect a fourth bit line set,
the fifth upper sub-latch blocks and the fifth lower sub-latch blocks intersect a fifth bit line set,
the sixth upper sub-latch blocks and the sixth lower sub-latch blocks intersect a sixth bit line set,
the seventh upper sub-latch blocks and the seventh lower sub-latch blocks intersect a seventh bit line set,
the eighth upper sub-latch blocks and the eighth lower sub-latch blocks intersect an eighth bit line set,
the ninth upper sub-latch blocks and the ninth lower sub-latch blocks intersect a ninth bit line set,
the tenth upper sub-latch blocks and the tenth lower sub-latch blocks intersect a tenth bit line set,
the eleventh upper sub-latch blocks and the eleventh lower sub-latch blocks intersect an eleventh bit line set,
the twelfth upper sub-latch blocks and the twelfth lower sub-latch blocks intersect a twelfth bit line set, and
each of the first to twelfth bit line sets includes eight bit lines extending in the column direction.