Patent ID: 11869859
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 17:
18. A method of forming a die stack, comprising:
forming a first bonding layer, first metal die interconnect structures, and first dummy metal features on a first die comprising a first semiconductor substrate;
forming a second bonding layer, second metal die interconnect structures, and second dummy metal features on a second die comprising a second semiconductor substrate;
aligning the first die and the second die, such that the first metal die interconnect structures contact the second metal die interconnect structures, and the first dummy metal features contact the second dummy metal features; and
bonding the first die and the second die, such that the first metal die interconnect structures are fusion bonded to the second metal die interconnect structures and interconnect the first die and the second die, the first dummy metal features are fusion bonded to the second dummy metal features and form a bonding dummy pattern (BDP), and the first bonding layer is bonded to the second bonding layer and form a bonding dielectric structure (BDS), wherein,
the BDP is electrically floated,
the first bonding layer, the second bonding layer, or both the first bonding layer and the second bonding layer comprise a dielectric bonding polymer, and
a pattern density of the BDP in the BDS is from 80% to 40%.