Patent ID: 11961569
Assignee: WINBOND ELECTRONICS CORP.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 7:
8. The clock-generating circuit as claimed in claim 5, wherein the voltage regulator further comprises a second P-type transistor,
wherein a gate and a drain of the second P-type transistor is connected to the output terminal of the voltage regulator, and a source of the second P-type transistor is connected to the external voltage,
wherein when the enable signal is in the high-logic state and the temporary reference voltage is higher than or equal to the reference voltage, the feedback path allows the second P-type transistor to be turned on, so that the oscillation power-supply voltage at the output terminal of the voltage regulator is maintained at the external voltage, and then gradually decreases with a falling slope of the temporary reference voltage,
wherein when the enable signal is in the high-logic state and the temporary reference voltage is lower than the reference voltage, a gate of the second P-type transistor generates a stable bias voltage via the feedback path to allow the second P-type transistor to be turned on, and the output terminal of the voltage regulator generates the oscillation power-supply voltage correspondingly.