Patent ID: 11916009
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A semiconductor package, comprising:
an interposer having a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces, wherein the interposer has a flange portion;
semiconductor dies, disposed on the first surface of the interposer and electrically connected with the interposer;
a circuit substrate, disposed below the interposer and connected to the second surface of the interposer, wherein the semiconductor dies are electrically connected with the circuit substrate through the interposer;
a molding compound, disposed over the interposer and laterally encapsulating the semiconductor dies, wherein the molding compound laterally wraps around the interposer and a portion of the molding compound physically contacts the sidewalls of the interposer; and
an underfill filled between the interposer, the molding compound and the circuit substrate.