Patent ID: 11870394
Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Field: Telecommunications (Electrical engineering)
Classification: CPC H | IPC H

Claim 2:
3. The demodulator according to claim 2, wherein
the second control signal generator includes an ADPLL (ALL-Digital Phase Locked Loop) circuit, and is configured to generate a digital signal as the second control signal,
the second input section has a configuration in which a least a same number of signal input sections as a bit number of the second control signal are coupled in parallel to each other, the signal input sections each including a capacitive element having a fixed capacitance,
the frequency variable oscillator is configured to generate the oscillation signal on a basis of the first control signal that is analog and is inputted to the first input section, and the second control signal that is digital and is inputted to the second input section, and
the digital demodulation signal generator is configured to demodulate the digital modulation signal on a basis of a signal obtained by subtracting the second phase difference signal from the second control signal that is digital.