Patent ID: 11875045
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. A semiconductor memory, comprising:
a target bank, comprising at least two storage regions;
an address processing circuit, configured to output an address of the target bank, wherein an output terminal of the address processing circuit is connected to the target bank;
a code obtaining circuit, configured to receive a target code, wherein the target code corresponds to at least one storage region to be trimmed in the target bank;
a region selection signal generation circuit, configured to generate, based on the target code, a region selection signal configured to select the storage region to be trimmed in the target bank, wherein an output terminal of the region selection signal generation circuit is connected to an input terminal of a trim circuit; and
the trim circuit, configured to trim the storage region to be trimmed based on the region selection signal to configure a density of the target bank, wherein an output terminal of the trim circuit is connected to the target bank.