Patent ID: 11870452
Assignee: NXP USA, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 9:
10. The method of claim 1, further comprising:
determining a sign of the first input value and a sign of a second input value; and
adjusting the phase value base on the signs of the first input value and the second value by:
providing the phase value as a first quadrant phase value in response to both the first input value and the second input value being positive;
subtracting the phase value from π to provide a second quadrant phase value in response to the first input value being negative and the second input value being positive;
adding π to the phase value to provide a third quadrant phase value in response to both the first input value and the second input value being negative; and
subtracting the phase value from 2 π to provide a fourth quadrant in response to the first input value being positive and the second input value being negative.