Patent ID: 11962441
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A decision feedforward equalizer (DFFE), comprising:
a plurality of precursor taps configured to sample a received signal by time delay amounts;
a cursor tap configured to sample the received signal by a time delay amount;
a plurality of postcursor taps configured to sample the received signal by different time delay amounts;
a plurality of tentative decision slicers corresponding with outputs of the plurality of precursor taps, the cursor tap and the plurality of postcursor taps and configured to receive delayed signals from the plurality of precursor taps, the cursor tap and the plurality of postcursor taps, and to quantize the delayed signals to generate quantized sampled signals;
multipliers configured to multiply the quantized sampled signals with tap coefficients to reduce noise; and
a summation element configured to combine the multiplied quantized sample signals to compensate precursor and postcursor inter-symbol interference.