Patent ID: 11880332
Assignee: NUVOTON TECHNOLOGY CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A bus system, comprising:
a master device;
an enhanced serial peripheral interface (eSPI) bus; and
a plurality of slave devices electrically connected to the master device via the eSPI bus, and comprising a first slave device and a plurality of second slave devices,
wherein each of the slave devices has a pin, and the pins of the slave devices are electrically connected together via a control line,
wherein the first slave device is configured to provide a first clock signal to each of the second slave devices via the control line, so that a second clock signal of each of the second slave devices is synchronized with the first clock signal,
wherein after the second clock signals are synchronized with the first clock signal, each of the second slave devices is configured to adjust a phase of the second clock signal in a clock phase shift stage, so that the second clock signal has a phase difference with the first clock signal,
wherein the phase differences between the second clock signals of the second slave devices and the first clock signal are different.