Patent ID: 11894382
Assignee: STMICROELECTRONICS FRANCE
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. The integrated circuit according to claim 7, further comprising another set of a first additional standard cell framed by two second additional standard cells, the three additional cells being adjoined and each including at least one NMOS transistor having a silicon channel and at least one PMOS transistor having a channel containing silicon and germanium, the active areas of all PMOS transistors forming a continuous semiconductor area, the threshold voltage of the at least one PMOS transistor of the first additional standard cell being different in absolute value from the threshold voltage of the at least one PMOS transistors of the second additional standard cells and the integrated circuit further including two polysilicon lines configured to be biased at a supply voltage and respectively disposed above the border between the active area of the at least one PMOS transistor of the first additional standard cell and the at least one PMOS transistor of each second additional standard cell.