Patent ID: 11943728
Assignee: BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC.
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for clock synchronization for use in high speed asynchronous serial interfaces, comprising:
on a first device:
receiving an ingress traffic from a second device;
decoding the ingress traffic using 8B10B;
splitting, via a traffic splitter, the ingress traffic in to an ingress regular traffic and a calibration feedback traffic;
processing the calibration feedback traffic via a calibration message receiver;
tuning a clock frequency based on the calibration feedback;
encoding a signal comprising at least one active message and an idle traffic using 8B10B to form a stream of K28.5 characters;
transmitting to the second device a signal comprising the encoded at least one active message and the idle traffic with an adjusted frequency; and
repeating preceding for a plurality of sample intervals, thereby reducing a probability of data sampling failure for high speed asynchronous serial interfaces.