Patent ID: 11972819
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. The non-volatile storage apparatus of claim 1, wherein:
the plurality of non-volatile memory cells are arranged as NAND strings to form a block having three sub-blocks, each NAND string includes memory cells in each of the three sub-blocks;
the three sub-blocks include a top sub-block, middle sub-block and bottom sub-block;
the selected word line is connected to memory cells only in the middle sub-block; and
the control circuit is configured to perform the concurrently lowering of the voltage applied to the selected word line and voltages applied to word lines on the first side of the selected word line and successively lowering voltages applied to groups of one or more word lines on the second side of the selected word line at the conclusion of the program-verify portion of the program loop when memory cells of the top sub-block and the bottom sub-block are programmed.