Patent ID: 11936409
Assignee: KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. The data transceiving system as claimed in claim 11, wherein the internal operating clock performs transition between a first clock level and a second clock level,
in response to the internal operating clock that is the first clock level, one ends of the second to fourth capacitors are all opened, the other end of the second capacitor is connected with the second compensation node, the other end of the third capacitor is connected with the third compensation node, the other end of the fourth capacitor is connected with the fourth compensation node to allow the second to fourth capacitors to store charges based on second to fourth compensation voltages of the second to fourth compensation nodes respectively connected thereto, and
in response to the internal operating clock that is the second clock level, only one of one ends of the second to fourth capacitors is connected to the output node of the amplifier and the other ends of the second to fourth capacitors are opened such that any one of the second to fourth capacitors connected to the output node of the amplifier receives the charges stored in the amplifier to output the output voltage.