Patent ID: 11967630
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 17:
18. A semiconductor device comprising:
a first p-type transistor formed in a first region of a substrate and having a first threshold voltage; and
a second p-type transistor formed in a second region of the substrate and having a second threshold voltage less than the first threshold voltage,
wherein the first p-type transistor comprises:
first and second nanowires sequentially disposed on the substrate;
a first gate insulating layer formed along a periphery of the first nanowire and a periphery of the second nanowire; and
a first gate electrode which surrounds the first nanowire and the second nanowire on the first gate insulating layer,

wherein the first gate electrode comprises a first titanium nitride layer and a first titanium silicon nitride layer sequentially formed along the periphery of the first nanowire and the periphery of the second nanowire, and a first upper electrode on the first titanium silicon nitride layer,
wherein the second p-type transistor comprises:
third and fourth nanowires sequentially disposed on the substrate;
a second gate insulating layer formed along a periphery of the third nanowire and a periphery of the fourth nanowire; and
a second gate electrode which surrounds the third nanowire and the fourth nanowire on the second gate insulating layer,

wherein the second gate electrode comprises a second gate electrode comprising a second titanium nitride layer and a second titanium silicon nitride layer, wherein the second titanium nitride layer and the second titanium silicon nitride layer are formed along the periphery of the third nanowire and the periphery of the fourth nanowire, and
wherein a ratio of a thickness of the first titanium silicon nitride layer to a thickness of the first titanium nitride layer is in a range of about 5/3 to about 7.