Patent ID: 11874734
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A memory, comprising:
a memory core;
an error correction circuit suitable for correcting an error of data that are read from the memory core based on an error correction code that is read from the memory core;
an error check operation control circuit suitable for checking an error in data stored in the memory core by using the error correction circuit during an error check operation;
a bad region classification circuit suitable for classifying a bad region based on errors detected during the error check operation; and
an address generation circuit suitable for
generating an error check address to be used in the error check operation,
changing the error check address whenever the error check operation is performed, and
generating again previous N error check addresses during error check operations performed N times after the bad region is newly detected, where N is an integer equal to or greater than 1.