Patent ID: 11901333
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 19:
20. A method to form a semiconductor package, comprising:
disposing a plurality of dies on a substrate, the substrate comprising silicon, the substrate having semiconductor structures, and the substrate having through substrate vias (TSVs);
disposing a plurality of dummy silicon dies on the substrate, wherein the plurality of dummy silicon dies are coupled onto the substrate with an adhesive layer, and wherein the plurality of dummy silicon dies are disposed adjacent to the plurality of dies;
disposing an encapsulation layer over and around the plurality of dies, the plurality of dummy silicon dies, and the substrate, wherein the encapsulation layer surrounds the plurality of dies; and
singulating the plurality of dummy silicon dies and the substrate to form the semiconductor package with a plurality of dummy silicon regions, and to form the substrate having a first straight edge laterally opposite to a second straight edge, wherein the plurality of dummy silicon regions have a top surface that is substantially coplanar to a top surface of the plurality of dies, and wherein the plurality of dummy silicon regions comprises a first dummy silicon die and a second dummy silicon die, the second dummy silicon die discontinuous with the first dummy silicon die, the first dummy silicon die proximate to the first straight edge of the substrate, and the second dummy silicon die proximate to the second straight edge of the substrate.