Patent ID: 11881283
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 16:
17. A memory system comprising:
a memory controller configured to send a request for an input or an output of data;
an input/output buffer configured to input or output the data in response to the request;
first and second memory cell arrays configured to store the data and configured to input the data to or output the data from the input/output buffer, wherein the first and second memory cell arrays are spaced apart from each other in a first direction;
a plurality of column selection transistors in a second direction which intersects the first direction, wherein the plurality of column selection transistors are between the first and second memory cell arrays, and wherein at least two of the column selection transistors comprise respective portions of a central gate pattern that intersects a central line extending in the first direction at a center of the first memory cell array and has a closed loop shape; and
first and second local input/output lines configured to provide electric potential through the first memory cell array to a local sense amplifier based on operations of the column selection transistors,
wherein the first and second local input/output lines extend in the second direction and are electrically connected to the central gate pattern, and
wherein the center line is spaced apart from, and does not intersect the first and second local input/output lines in a plan view.