Patent ID: 11875056
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory system, comprising:
a storage device including a plurality of memory blocks each grouped into one of a plurality of zones corresponding to a plurality of zone identification; and
a controller including:
a command manager configured to, based on requests and write pointers received from a host, generate commands allocated to the write pointers, and store the commands based on operating states of the storage device, each of the write pointers indicating an order that the requests are output from the host; and
a zone manager configured to:
in response to the commands being received from the command manager, store the commands in a write queue regardless of an order of the write pointers,
select a command corresponding to a selected zone identification among the commands stored in the write queue,
store the selected command in a selected buffer allocated to the selected zone identification such that an order of write pointers of commands stored in the selected buffer is consecutive, and
output the commands stored in the selected buffer, based on a number of the commands stored in the selected buffer.