Patent ID: 11962303
Assignee: STEVE DAO
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A flip-flop circuit, comprising:
a first latch operating in a first voltage domain, wherein the first latch comprises:
four clock-activated transistors,
a first output node,
a second output node,
a first intermediate node,
a second intermediate node,
a first p-type transistor electrically coupled to the first intermediate node to form a first inverter sub-circuit, and
a second p-type transistor electrically coupled to the second intermediate node to form a second inverter sub-circuit;

a second latch operating in the first voltage domain, wherein the second latch comprises:
a first keeper pull-up sub-circuit coupled to the second intermediate node;
a second keeper pull-up sub-circuit;
a first keeper pull-down sub-circuit coupled to the first intermediate node;
a first pull-down network; and
a second pull-down network,

wherein the first intermediate node is an output of the first inverter sub-circuit and the second intermediate node is an output of the second inverter sub-circuit.