Patent ID: 11947841
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. An apparatus, comprising:
amplifier components configured to sense, from a memory array and based at least in part on a command for an address of the memory array, a first set of tag bits that indicate access information for a set of addresses that includes the address;
a decoder configured to decode the address of the memory array based at least in part on the command and configured to generate a second set of tag bits based at least in part on the command and the decoded address, the generated second set of tag bits indicating updated access information for the decoded address;
a first error correction code (ECC) engine configured to generate a codeword based at least in part on the first set of tag bits and the generated second set of tag bits, wherein the first ECC engine is different than a second ECC engine configured to perform ECC operations on data bits stored in the memory array; and
latching components configured to latch the codeword for storage at the memory array.