Patent ID: 11915740
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 3:
4. The apparatus of claim 1, further comprising:
a plurality of third word lines each coupled with a respective memory cell of each pillar of a third subset of the plurality of pillars, the third subset arranged in a two-dimensional array of the first quantity of pillars along the first direction and the third quantity of pillars along the second direction;
a third word line driver operable to bias one of the plurality of third word lines;
a plurality of fourth word lines each coupled with a respective memory cell of each pillar of a fourth subset of the plurality of pillars, the fourth subset arranged in a two-dimensional array of the first quantity of pillars along the first direction and the third quantity of pillars along the second direction; and
a fourth word line driver operable to bias one of the plurality of fourth word lines.