Patent ID: 11875044
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. An apparatus, comprising:
a system-on-chip (SoC) device comprising a plurality of electrical interconnections;
a memory component having a number of electrical interconnections coupled to the plurality of electrical interconnections of the a memory array of the memory component comprising a plurality of independently addressable sub arrays;
sense amplifiers coupled to corresponding outputs of the sub arrays and coupled to a communication channel of the SoC device; and
a scan chain comprising Joint Test Action Group (JTAG) cells coupled in parallel between an output of the sense amplifiers and the communication channel to perform read operations in a direct memory access, wherein the apparatus is configured to fill the communication channel with an enlarged memory page including data, corresponding address bits, and ECC bits of each sub array of the plurality of sub arrays.