Patent ID: 11948656
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. A memory system, comprising:
one or memory devices; and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
initiate, by the memory system comprising a first row of memory cells that includes a set of memory cells for storing a value of a counter, a first testing operation on a first subset of the set of memory cells, wherein the set of memory cells comprises a second subset and the value of the counter is associated with the first row of memory cells;
activate the first row of memory cells a first quantity of times based at least in part on initiating the first testing operation;
outputting, by circuitry couple with the first row of memory cells that comprises a plurality of multiplexers, at least one bit of the first subset from a first multiplexer of the plurality of multiplexers to a second multiplexer of the plurality of multiplexers based at least in part on activating the first row of memory cells the first quantity of times;
generate a first flag indicating an error condition of the first subset based at least in part on outputting the at least one bit from the first multiplexer to the second multiplexer; and
configure the plurality of multiplexers to use the second subset to store the value of the counter and to refrain from using the first subset to store the value of the counter based at least in part on the first flag.