Patent ID: 11940921
Assignee: CENTAUR TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. A microprocessor, comprising:
an L1 cache;
an L2 cache comprising a bounding box prefetch unit and an L2 fill queue, the bounding box prefetch unit configured to allocate an entry in the L2 fill queue based on a miss in the L2 cache; and
an L3 cache;
wherein, based on the allocation, the bounding box prefetch unit is configured to:
issue all prefetches remaining for a memory block as L3 prefetches based on a set of conditions; and
issue L2 prefetches for plural cache lines corresponding to the L3 prefetches upon the plural cache lines obtained from the L3 prefetches reaching an end of the memory block.