Patent ID: 11950420
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A memory device comprising:
a plurality of gate electrode layers stacked on a substrate and disposed in a cell array region and a cell contact region;
a plurality of channel structures penetrating the plurality of gate electrode layers and connected to a plurality of bit lines in the cell array region;
a plurality of first wordline cuts extending in a first direction parallel to an upper surface of the substrate to divide the plurality of gate electrode layers into first and second blocks, the first and second blocks separated from each other in a second direction parallel to the upper surface of the substrate and perpendicular to the first direction;
a plurality of second wordline cuts within each of the first and second blocks, the second wordline cuts in each block extending in the first direction between a pair of the first wordline cuts, among the plurality of the first wordline cuts, and being spaced apart from each other in the second direction, wherein the gate electrode layers within each block are separated by the second wordline cuts into unit areas extending lengthwise in the first direction and separated from each other in the second direction; and
a plurality of dummy channel structures penetrating at least a portion of the plurality of gate electrode layers of each unit area and isolated from the plurality of bit lines, wherein:
each of the plurality of second wordline cuts is divided into a first cut line and a second cut line aligned in the first direction and spaced apart in the first direction, wherein a space between the first cut line and the second cut line of each second wordline cut is shifted in the first direction relative to the space between the first cut line and the second cut line of each adjacent second wordline cut,
a plurality of cell contacts are disposed in the cell contact region and at least a portion of the plurality of cell contacts are disposed between a pair of the first cut lines in the second direction,
at least one of the plurality of dummy channel structures is aligned in the first direction in a space extending between the first cut line and the second cut line of one of the plurality of second wordline cuts, and
the plurality of gate electrode layers of the unit areas have a step-wise structure in both of the first direction and the second direction in each of the first and second blocks in the cell contact region.