Patent ID: 11869886
Assignee: SEIKO EPSON CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 5:
6. The ESD protection circuit according to claim 5, further comprising:
a second MOS transistor disposed between the fifth node and the first line defining the MOS transistor as a first MOS transistor;
a sixth resistor disposed between the fifth node and the second MOS transistor;
a fourth line supplied with a fourth potential different from the third potential; and
a seventh resistor and a second capacitor coupled in series between a sixth node coupled to the fourth line and the first line, wherein
when defining a junction between the seventh resistor and the second capacitor as a seventh node, a gate of the second MOS transistor is coupled to the seventh node, and
the fourth potential is a potential between the first potential and the second potential.