Patent ID: 11869931
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A semiconductor structure, comprising:
a substrate, wherein a plurality of capacitive contacts are provided in the substrate, and a plurality of electrically conductive contact pads are provided at a surface of the substrate to be correspondingly connected to a plurality of capacitive contacts on a one to one basis;
a filling layer, sandwiched between adjacent electrically conductive contact pads;
a stacked structure, wherein the stacked structure includes a plurality of supporting layers stacked one on another along a direction perpendicular to the substrate, the filling layer is in contact with the one supporting layer disposed at a bottom of the stacked structure, and an etching selection ratio between the filling layer and the supporting layer in contact therewith is greater than a preset value; and
a capacitance hole, running through the stacked structure and exposing the electrically conductive contact pads.