Patent ID: 11871587
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A memory device, comprising:
first to nth decks respectively coupled to first to nth row lines which are stacked over a substrate in a vertical direction perpendicular to a surface of the substrate, n being a positive integer;
a first connection structure extending from the substrate in the vertical direction to be coupled to the first row line;
even-numbered connection structures extending from the substrate in the vertical direction and respectively coupled to ends of even-numbered row lines among the second to nth row lines; and
odd-numbered connection structures extending from the substrate in the vertical direction and respectively coupled to ends of odd-numbered row lines among the second to nth row lines,
wherein the even-numbered connection structures are spaced apart from the odd-numbered connection structures with the first row line and the first connection structure that are interposed between the even-numbered connection structures and the odd-numbered connection structures,
wherein the first row line, the even-numbered row lines, and the odd-numbered row lines are stacked in the vertical direction,
wherein each of the first to nth decks includes a memory cell, which is coupled to a corresponding connection structure among the first connection structure and the even-numbered and odd-numbered connection structures via a corresponding row line among the first to nth row lines, and
wherein each of the even-numbered and odd-numbered connection structures comprises at least one via plug.