Patent ID: 11887690
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. The apparatus of claim 5, wherein:
each first memory cell of the first set of memory cells is associated with a respective first cell selection transistor, wherein a channel portion of each first cell selection transistor comprises a respective set of one or more fifth semiconductor pillars in contact with the first digit line and overlapping, along a height dimension relative to the substrate, with the set of one or more first semiconductor pillars; and
each second memory cell of the second set of memory cells is associated with a respective second cell selection transistor, wherein a channel portion of each second cell selection transistor comprises a respective set of one or more sixth semiconductor pillars in contact with the second digit line and overlapping, along the height dimension relative to the substrate, with the set of one or more second semiconductor pillars.