Patent ID: 11877455
Assignee: NANYA TECHNOLOGY CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for preparing a vertical memory structure, comprising:
providing a substrate;
forming an impurity layer at an upper portion of the substrate;
forming a semiconductor stack including a lower semiconductor pattern structure filling a recess on the substrate and protruding from an upper surface of the substrate in a first direction substantially perpendicular to the upper surface of the substrate;
forming a plurality of gate electrodes surrounding a sidewall of the semiconductor stack, the plurality of gate electrodes being at a plurality of levels, respectively, so as to be spaced apart from each other in the first direction;
forming a plurality of air gap structures disposed at outer sides of the plurality of gate electrodes respectively, wherein the plurality of air gap structures comprise a liner layer enclosing an air gap;
forming a conductive line, and the plurality of air gap structures separate the conductive line from the plurality of gate electrodes, wherein the lower semiconductor pattern structure comprises a first undoped semiconductor pattern, a doped semiconductor pattern, and a second undoped semiconductor pattern sequentially stacked in the first direction;
forming an upper semiconductor pattern extends in the first direction on the lower semiconductor pattern structure, wherein a lower surface of the doped semiconductor pattern is lower than the upper surface of the substrate, wherein an upper surface of the doped semiconductor pattern of the lower semiconductor pattern is higher than a lower surface of a lowermost one of the plurality of gate electrodes and lower than an upper surface thereof; and
forming a first diffusion prevention pattern between the first undoped semiconductor pattern and the doped semiconductor pattern; and forming a second diffusion prevention pattern between the doped semiconductor pattern and the second undoped semiconductor pattern.