Patent ID: 11916067
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 7:
8. A method of forming an integrated circuit, comprising:
forming a buried layer within an epitaxial layer having a top surface and a first conductivity type and located over a semiconductor substrate, the buried layer having a second opposite conductivity type; and
forming one or more deep wells having the second conductivity type and extending from the top surface to the buried layer; and
forming a lightly doped region having the first conductivity type, the lightly doped region surrounded by the buried layer and the one or more deep wells;
forming a shallow well having the first conductivity type within the lightly doped region and touching the one or more deep wells; and
forming a dielectric isolation structure abutting the shallow well having the first conductivity type, the dielectric isolation structure touching the lightly doped region.