Patent ID: 11922988
Assignee: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 19:
20. An operating method of a DRAM device, the method comprising:
accessing the DRAM device including a channel region formed on a substrate, a gate insulating film region formed on the channel region, a floating gate region formed on the gate insulating film region the floating gate region having a lower surface in contact with the gate insulating film region and an opposing upper surface, a transition layer region formed on the upper surface of the floating gate region, wherein an area of the transition layer that is in contact with the floating gate region is smaller than a total area of the upper surface of the floating gate region, and a control gate region formed on the transition layer region;
generating a potential difference with the floating gate region in response to a fact that a potential that is not less than a reference potential is applied; and
performing a memory operation by generating a transition current due to the potential difference,
wherein the performing of the memory operation includes one of:
releasing at least one charge stored in the floating gate region; or
storing the at least one charge into the floating gate region.