Patent ID: 11893249
Assignee: CEREMORPHIC, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. A process operative on a Central Processing Unit (CPU) coupled to a flash memory containing portable code modules, the CPU also coupled to a Random Access Memory (RAM), the process comprising:
the CPU executing powersave code from a region of flash memory to a region of RAM, the CPU thereafter executing the powersave code from the region of RAM;
the CPU copying portable code modules from a region of flash memory to a region of RAM;
the CPU initializing pointers in a region of RAM indicating whether each portable code module is to be executed from a region of flash memory or from a region of RAM;
the CPU allocating transient RAM memory for the storage of data;
the CPU periodically examining a ratio of a size of the transient RAM memory in use to a total RAM size;
if the ratio is greater than a first threshold:
deallocating a region of the RAM used for portable code modules, updating associated pointers to point to corresponding portable code modules in the flash memory, and also allocating the deallocated region of RAM used for portable code modules to transient RAM memory.