Patent ID: 11929363
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 5:
6. A semiconductor device, comprising:
a first well of a first conductivity type surrounding a first doped region of a second conductivity type in a layout view, wherein the first doped region is coupled to an input/output (I/O) pad; and
a second well of the second conductivity type surrounding a second doped region of the first conductivity type in the layout view, wherein the second doped region is coupled to a first voltage terminal, and
an isolation region is interposed between the first and second doped regions,
wherein the first to second doped regions and the first to second wells are configured to form a first electrostatic discharge (ESD) path between the I/O pad and the second doped region.