Patent ID: 11887644
Assignee: FERROELECTRIC MEMORY GMBH
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 18:
19. A method for operating a memory cell, the method comprising:
writing, via a first write operation, a first memory capacitor structure of a plurality of memory capacitor structures comprised in a selected memory cell of a memory cell arrangement and writing, via a second write operation, a second memory capacitor structure of the plurality of memory capacitor structures comprised in the selected memory cell of the memory cell arrangement,
wherein the first write operation comprises:
applying a first control voltage to a first control node of the selected memory cell connected to the first memory capacitor structure; and

wherein the second write operation comprises:
applying a second control voltage to a second control node of the selected memory cell connected to the second memory capacitor structure;

wherein the first memory capacitor structure comprises:
a first electrode connected to the first control node, a second electrode connected to a gate region of a field-effect transistor structure of the selected memory cell, and a spontaneous-polarizable region disposed between the first electrode and the second electrode; and

wherein the second memory capacitor structure comprises:
a further first electrode connected to the second control node, a further second electrode connected to the gate region of the field-effect transistor structure, and a further spontaneous-polarizable region disposed between the further first electrode and the further second electrode.