Patent ID: 11886341
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus, comprising:
a memory system comprising memory configured as a first cache, the first cache comprising a plurality of entries; and
a controller coupled with the memory system, wherein the controller is configured to:
remove an entry from the first cache based at least in part on receiving a read request, wherein the entry is configured to store a mapping between logical addresses and physical addresses for a respective region of the memory system;
store, to a second cache of the memory system, an index associated with the entry removed from the first cache, wherein the index identifies a region of the memory system associated with the entry removed from the first cache; and
transmit a mapping of the region associated with the entry removed from the first cache based at least in part on storing the index to the second cache of the memory system.