Patent ID: 11862726
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. An integrated circuit, comprising:
a substrate;
a first transistor over the substrate; and
an interconnect structure disposed on the substrate, comprising;
dielectric layers; and
at least one second transistor embedded in one of the dielectric layers, comprising:
an insulating layer;
a source region and a drain region extending along a first direction, wherein the source region and the drain region are respectively disposed on and in physical contact with two opposite sidewalls of the insulating layer, and a top surface of the source region, a top surface of the drain region, and a top surface of the insulating layer are substantially coplanar;
a channel layer, an interfacial layer, a storage layer, and a gate electrode sequentially stacked on the insulating layer, the source region, and the drain region, wherein the channel layer, the interfacial layer, the storage layer, and the gate electrode extend along a second direction perpendicular to the first direction, the interfacial layer is sandwiched between the channel layer and the storage layer, and the storage layer is a ferroelectric layer.