Patent ID: 11914439
Assignee: ROHM CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 3:
4. The synchronous reset signal generation circuit according to claim 3,
wherein each flip-flop, when the asynchronous reset signal in an active state is input thereto, outputs from the data output terminal a signal with a first logic value and each flip-flop, when the asynchronous reset signal in a non-active state is input thereto, holds a logic value of an input signal to the data input terminal in response to a predetermined level change in the clock signal and outputs from the data output terminal a signal with the held logic value,
the predetermined logic value is a second logic value, and
the synchronous reset signal with the first logic value is a signal for resetting a logic circuit configured to operate in synchronization with the clock signal.