Patent ID: 11881283
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 5:
6. The semiconductor memory device of claim 4, further comprising:
a first outer bitline of a plurality of bitlines, wherein the first outer bitline extends in the first direction over the first memory cell array and is a farthest one of the plurality of bitlines from the center line in the second direction; and
a second outer bitline of the plurality of bitlines, wherein the second outer bitline extends in the first direction over the first memory cell array and is a farthest one of the plurality of bitlines from the first outer bitline in the second direction,
wherein the central column selection transistors further comprise a first outer column selection transistor configured to control electric potential between the first outer bitline and the local sense amplifier, and a second outer column selection transistor configured to control electric potential between the second outer bitline and the local sense amplifier.