Patent ID: 11950423
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 9:
10. A semiconductor device comprising:
a cell area comprising a memory cell array; and
a peripheral circuit area having the cell area stacked thereon in a vertical direction, the peripheral circuit area comprising a peripheral circuit substrate and a plurality of circuits on the peripheral circuit substrate and electrically connected to the memory cell array,
wherein the plurality of circuits comprise:
a plurality of planar channel transistors respectively configured to form a channel along a top surface of the peripheral circuit substrate; and
at least one recess channel transistor configured to form a channel along a surface of a recess trench in the peripheral circuit substrate,
wherein the at least one recess channel transistor comprises:
a first recess channel transistor comprising a first gate electrode or a first source/drain region that has a first depth in the vertical direction relative to the top surface of the peripheral circuit substrate; and
a second recess channel transistor comprising a second gate electrode or a second source/drain region that has a second depth, which is greater than the first depth, in the vertical direction relative to the top surface of the peripheral circuit substrate.