Patent ID: 11961582
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A shift register unit, comprising:
an input circuit configured to provide a signal of an input signal terminal to a first node in response to a signal of a first clock signal terminal; and provide a signal of a first reference signal terminal to a second node in response to the signal of the first clock signal terminal;
a node control circuit, connected with the first node, the second node and the first clock signal terminal respectively, wherein the node control circuit is configured to provide the signal of the first clock signal terminal to the second node in response to a signal of the first node;
a first control output circuit configured to control a signal of a third node according to a signal of a first control signal terminal and a signal of the second node;
a second control output circuit configured to provide a signal of a second reference signal terminal to a signal output terminal according to a signal of a second control signal terminal and the signal of the second node; and
an output circuit configured to provide a signal to the signal output terminal according to the signal of the first node;
wherein the output circuit comprises a ninth transistor, a tenth transistor and a first capacitor, the ninth transistor has a gate electrode coupled to the first reference signal terminal, a first electrode coupled to the first node, and a second electrode coupled to a gate electrode of tenth transistor; the tenth transistor has a first electrode coupled to the second clock signal terminal, and a second electrode coupled to the signal output terminal; and the first capacitor is coupled between the gate of the tenth transistor and the signal output terminal;
or,
wherein the output circuit comprises an eleventh transistor, a twelfth transistor, a thirteenth transistor and a second capacitor; wherein the eleventh transistor has a gate electrode coupled to the first control signal terminal, a first electrode coupled to the first node, and a second electrode coupled to a gate electrode of the thirteenth transistor; the twelfth transistor has a gate coupled to the second control signal terminal, a first electrode coupled to the first node, and a second electrode coupled to the gate of the thirteenth transistor; the thirteenth transistor has a first electrode coupled to the second clock signal terminal, and a second electrode coupled to the signal output terminal; and the second capacitor is coupled between the gate of the thirteenth transistor and the signal output terminal.