Patent ID: 11941249
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device comprising:
a plurality of storage units configured to store data; and
at least one device controller configured to,
provide at least one host device with a response command,
receive a read command from the at least one host device,
the read command including at least one of mapping information and indexing information associated with the read command retrieved from a first HPB (high performance boosting) entry storage region of a plurality of HPB entry storage regions included in the at least one host device, and additional information related to the read command from a second HPB entry storage region included in the plurality of HPB entry storage regions included in the at least one host device, the mapping information indicating a mapping between a logical address associated with a memory operation and a physical address associated with the memory operation, and the indexing information indicating a location of the second HPB entry storage region associated with the memory operation, and the additional information related to operation of the device controller, and

read data stored in the plurality of storage units based on at least one of the mapping information, and the indexing information, and the additional information in response to the read command,
wherein the response command indicates an activation or deactivation of the plurality of HPB entry storage regions, and the response command includes HPB entry type information which indicates a HPB entry type of the plurality of HPB entry storage regions.