Patent ID: 11925024
Assignee: KIOXIA CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor memory device comprising:
a substrate having a first region, a second region, a third region, and a fourth region, the second region being arranged with the first region in a first direction, the third region being arranged with the first region in a second direction intersecting with the first direction, the fourth region being arranged with the third region in the first direction, the fourth region being arranged with the second region in the second direction;
a plurality of first word line layers and a plurality of first interlayer insulating layers laminated in a third direction intersecting with a surface of the substrate,
each of the plurality of first word line layers including a first word line part provided over the first region and a second word line part provided over the second region,
each of the plurality of first interlayer insulating layers including a first interlayer insulating part provided over the first region, a second interlayer insulating part provided over the second region, and a third interlayer insulating part provided over the second region,
all first interlayer insulating parts of the plurality of first interlayer insulating layers being laminated in the third direction alternately with all first word line parts of the plurality of first word line layers, and
all second interlayer insulating parts of the plurality of first interlayer insulating layers being laminated in the third direction alternately with all second word line parts of the plurality of first word line layers;

a first semiconductor layer that is provided over the first region and extends in the third direction, the first semiconductor layer having an outer peripheral surface opposed to all first word line parts of the plurality of first word line layers;
a first electric charge accumulating film provided over the first region and disposed between all first word line parts of the plurality of first word line layers and the first semiconductor layer;
a plurality of first insulating layers provided over the second region and laminated in the third direction alternately with all third interlayer insulating parts of the plurality of first interlayer insulating layers that are arranged with all second word line parts of the plurality of first word line layers in the second direction;
a first contact that is provided over the second region and extends in the third direction, the first contact having an outer peripheral surface abutting at least some of the plurality of first insulating layers;
a plurality of second word line layers and a plurality of second interlayer insulating layers laminated in the third direction,
each of the plurality of second word line layers including a third word line part provided over the third region and a fourth word line part provided over the fourth region,
each of the plurality of second interlayer insulating layers including a fourth interlayer insulating part provided over the third region, a fifth interlayer insulating part provided over the fourth region, and a sixth interlayer insulating part provided over the fourth region,
all fourth interlayer insulating parts of the plurality of second interlayer insulating layers being laminated in the third direction alternately with all third word line parts of the plurality of second word line layers, and
all fifth interlayer insulating parts of the plurality of second interlayer insulating layers being laminated in the third direction alternately with all fourth word line parts of the plurality of second word line layers;

a second semiconductor layer that is provided over the third region and extends in the third direction, the second semiconductor layer having an outer peripheral surface opposed to all third word line parts of the plurality of second word line layers;
a second electric charge accumulating film provided over die third region and disposed between all third word line parts of the plurality of second word line layers and the second semiconductor layer;
a plurality of second insulating layers provided over the fourth region and laminated in the third direction alternately with all sixth interlayer insulating parts of the plurality of second interlayer insulating layers that are arranged with all fourth word line parts of the plurality of second word line layers in the second direction; and
a second contact that is provided over the fourth region and extends in the third direction, the second contact having an outer peripheral surface abutting at least some of the plurality of second insulating layers, wherein
each of the plurality of first insulating layers has a side surface in the first direction attached to a first word line part of a corresponding first word line layer,
each of the plurality of second insulating layers has a side surface in the first direction attached to a third word line part of a corresponding second word line layer, and
the plurality of first insulating layers and the plurality of second insulating layers are provided between all second word line parts of the plurality of first word line layers and all fourth word line parts of the plurality of second word line layers.