Patent ID: 11910619
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 9:
10. A method for forming a semiconductor structure, the method comprising:
forming a memory cell over a substrate;
forming a sidewall spacer structure on the memory cell, wherein the sidewall spacer structure comprises a first spacer layer disposed along sidewalls of the memory cell, a second spacer layer disposed on an upper surface of the memory cell and sidewalls of the first spacer layer, and a third spacer layer on the second spacer layer;
performing a first etching process on the sidewall spacer structure and the memory cell, wherein the first etching process removes the second and third spacer layers from over the memory cell and exposes the upper surface of the memory cell;
depositing a first dielectric layer over and around the memory cell;
performing a second etching process on the first dielectric layer and the second spacer layer to define an opening over the memory cell; and
forming an upper conductive structure in the opening, wherein the upper conductive structure abuts an upper surface of the second spacer layer.