Patent ID: 11916100
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An integrated chip, comprising:
a dielectric structure over a substrate;
a lower conductive wire within the dielectric structure;
a first capacitor disposed between sidewalls of the dielectric structure and over the lower conductive wire, wherein the first capacitor includes a first electrode between the sidewalls of the dielectric structure, a second electrode between the sidewalls of the dielectric structure and over the first electrode, and a first insulative layer between the first electrode and the second electrode;
a second capacitor disposed between the sidewalls of the dielectric structure, wherein the second capacitor includes the second electrode, a third electrode between the sidewalls of the dielectric structure and over the second electrode, and a second insulative layer between the second electrode and the third electrode;
a third capacitor disposed between the sidewalls of the dielectric structure, wherein the third capacitor includes the third electrode, a fourth electrode between the sidewalls of the dielectric structure and over the third electrode, and a third insulative layer between the third electrode and the fourth electrode; and
an upper conductive wire over the fourth electrode,
wherein the first capacitor, the second capacitor, and the third capacitor are coupled in parallel by a first contact arranged on a first side of the first capacitor and a second contact arranged on a second side of the first capacitor, opposite the first side,
wherein the first electrode and the third electrode are electrically coupled to the lower conductive wire and electrically isolated from the upper conductive wire, and wherein the second electrode and the fourth electrode are electrically coupled to the upper conductive wire and electrically isolated from the lower conductive wire.