Patent ID: 11955170
Assignee: UNTETHER AI CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 2:
3. A static random-access memory comprising:
a word line circuit for generating a word line signal on a word line;
a plurality of six-transistor memory cells arranged between a first bitline, a second bitline and the word line for simultaneously selecting one of either all or a portion of the plurality of six-transistor memory cells for data reading or writing, and wherein each memory cell comprises:
a first inverter;
a second inverter, the first inverter and the second inverter configured to operate at a power supply voltage (Vdd);
a first n-channel transistor having a gate for receiving the word line signal on the word line and in response connecting a first output of the first inverter to the first bitline;
a second n-channel transistor having a gate for receiving the word line signal on the word line and in response connecting a second output of the second inverter to the second bitline; and, a bitline precharge circuit for precharging the first bitline and second bitline to a voltage of Vdd/2 prior to the first and second n-channel transistors receiving the word line signal, wherein the word line circuit selects all of the plurality of six transistor memory cells along a selected word-line for simultaneous data reading or writing, and wherein the amplitude of the word line signal when reading said memory cells is at Vdd, and the amplitude of the word line signal when writing to said memory cells is boosted larger than Vdd, and the rise time of the word line signal when reading said memory cells and writing to said memory cells is slower than the fall time to reduce a peak of low data stored in the bit cells when the word line signal is less than 20% of the Vdd/2 precharge voltage, and wherein the slower rise time is slow enough to raise the first bitline voltage to more than 50 mV with a split between the first and second bitline voltages when the word line signal reaches more than 90% of its maximum amplitude, and wherein the
word line circuit includes a monitoring circuit having resistance and capacitance to detect when the low data bit line signal reaches less than 10% of its precharge amplitude.