Patent ID: 11899969
Assignee: AMAZON TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An integrated circuit, comprising:
completer devices including a first completer device;
requester devices coupled to the completer devices through an interconnect fabric, wherein the requester devices include a first requester device configured to generate a first write transaction to be executed by the first completer device and a second write transaction to be executed by the first completer device; and
a write re-order buffer (WROB) configured to:
receive the first write transaction followed by the second write transaction;
assign a first group identifier (ID) to the first write transaction;
determine that the second write transaction depends on a result of the first write transaction;
assign the first group ID to the second write transaction in response to determining that the second write transaction depends on the result of the first write transaction; and
forward the first write transaction followed by the second write transaction to the interconnect fabric for routing, wherein the interconnect fabric is configured to route transactions such that transactions assigned to a same group ID are sequentially executed according to order of arrival at the interconnect fabric, but transactions that are assigned to different group IDs are permitted to be executed out of order.