Patent ID: 11949414
Assignee: INTEL CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 2:
3. The apparatus of claim 2, wherein the row is a first row, the column of the LUT is a first column and:
the second multiplexer is to return third values representative of a second column of the LUT based on a second element of the second operand received at the second select terminals;
the first multiplexer is to return fourth values from an intersection of a second row and the second column of the LUT based on a second element of the first operand received at the first select terminals;
the shift and adder logic is to shift the fourth values based on at least one of the second element of the first operand or the second element of the second operand; and
the accumulation storage is to store a sum of the shifted second values and the shifted fourth values.