Patent ID: 11929134
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. A system, comprising:
a memory device configured to:
read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device;
identify, based on the one or more bits, that the memory built-in self-test is enabled for one or more memory sections of the memory device; and
set a data mask inversion (DMI) bit of the memory device to a first value or a second value and selectively perform the memory built-in self-test based on identifying that the memory built-in self-test is enabled for the one or more memory sections of the memory device,
wherein the DMI bit of the memory device indicates a status of the memory built-in self-test while the memory built-in self-test is enabled for the one or more memory sections of the memory device, and indicates a status of a data masking function or a data inversion function of the memory device while the memory built-in self-test is disabled for all memory sections of the memory device; and

a host device configured to:
write to the one or more bits, that are stored in the mode register of the memory device, to indicate that the memory built-in self-test is enabled; and
identify, based on the DMI bit of the memory device having the first value or the second value, whether the memory device is currently performing the memory built-in self-test or is not currently performing the memory built-in self-test.