Patent ID: 11863741
Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
Field: Audio-visual technology (Electrical engineering)
Classification: CPC H | IPC H

Claim 1:
2. A decoder comprising:
processing circuitry;
a memory coupled to the processing circuitry,
wherein, using the memory, the processing circuitry is configured to:
change values of luma pixels in a first block and a second block to filter a first boundary between the first block and the second block, by performing multiplication for the first block using each of first luma filter coefficients as a multiplier, and by performing multiplication for the second block using each of second luma filter coefficients as a multiplier; and
change values of chroma pixels in a third block and a fourth block to filter a second boundary between the third block and the fourth block, by performing multiplication for the third block using each of first chroma filter coefficients as a multiplier, and by performing multiplication for the fourth block using each of second chroma filter coefficients as a multiplier,
wherein the first luma filter coefficients and the second luma filter coefficients are selected to be asymmetrical with respect to the first boundary, and
wherein the first chroma filter coefficients and the second chroma filter coefficients are selected to be symmetrical with respect to the second boundary.