Patent ID: 11916010
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 17:
18. A method of forming an integrated circuit (IC) structure, the method comprising:
providing a stack of a first insulator material, a first conductive material, a second insulator material, and a sacrificial material;
patterning the sacrificial material to form an opening for a first conductive line;
patterning the second insulator material through the opening for the first conductive line to form an opening for a via,
filling the opening for the first conductive line and the opening for the via with a further material, and
removing portions of the sacrificial material and the second insulator material that are not covered by the further material,
removing portions of the first conductive material that are not covered by the further material to form the first conductive line;
providing the via over the first conductive line; and
providing a second conductive line over the via, where:
the via has a first portion and a second portion, the first portion is between the first conductive line and the second portion, the second portion is between the first portion and the second conductive line, and a width of the second portion is smaller than a width of the first portion.