Patent ID: 11909852
Assignee: ZAINAR, INC.
Field: Telecommunications (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. The transceiver of claim 7, wherein the processor is further configured to:
calculate a timestamping noise of the second clock relative to the first clock based on the residual of the first regression;
calculate the adjusted calibration period based on a target precision and the timestamping noise;
transmit a fifth calibration signal at a fifth time-of-departure measured by the first clock and succeeding transmission of the fourth calibration signal by the adjusted calibration period;
receive access a fifth time-of-arrival of the fifth calibration signal received at the second transceiver measured by the second clock adjusted by the first frequency offset;
define a third calibration point in a second set of calibration points, the third calibration point representing the third time-of-departure and the third time-of-arrival;
define a fourth calibration point in the second set of calibration points, the fourth calibration point representing the fourth time-of-departure and the fourth time-of-arrival;
define a fifth calibration point in the second set of calibration points, the fifth calibration point of the second set of calibration points comprising the fifth time-of-departure and the fifth time-of-arrival; and
calculate the second frequency offset between the first clock and the second clock by calculating the second frequency offset between the first clock and the second clock based on the second set of calibration points.