Patent ID: 11914524
Assignee: QUALCOMM INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. An electronic device, comprising one or more processors configured to execute one or more virtual machines, wherein a respective processor is configured to perform:
receiving a request for initiating a synchronization event; and
in response to the request:
identifying a subset of speculative memory access requests in one or more memory access request queues;
automatically, in accordance with the identifying, purging translations associated with the subset of speculative memory access requests; and
initiating the synchronization event,

wherein the respective processor includes a memory management unit (MMU) configured to manage the one or more memory access request queues, and is configured to:
in response to the request, generating by the respective processor a purge instruction to purge translations of the subset of speculative memory access requests, wherein the MMU identifies the subset of speculative memory access requests in the one or more memory access queues and purges the translations associated with the subset of speculative memory access requests.