Patent ID: 11928358
Assignee: PHISON ELECTRONICS CORP.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. A memory storage device, comprising:
a connection interface unit configured to be coupled to a host system;
a rewritable non-volatile memory module;
a memory control circuit unit coupled to the connection interface unit and the rewritable non-volatile memory module,
wherein the memory control circuit unit comprises a buffer memory, and the memory control circuit unit is configured to:
obtain a plurality of commands from a memory of the host system;
store the plurality of commands in a first buffer region of the buffer memory;
put a first command and a second command in the first buffer region in a first command queue of the buffer memory in response to the first command and the second command in the first buffer region meeting a pairing condition;
obtain the second command from the memory of the host system in response to a presence of the first command and an absence of the second command in the first buffer region;
store the second command in a second buffer region of the buffer memory;
put the first command in the first buffer region and the second command in the second buffer region in the first command queue; and
continuously execute the first command and the second command in the first command queue.