Patent ID: 11864431
Assignee: LG DISPLAY CO., LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 0:
1. A light emitting display device comprising:
a lower substrate;
a transistor positioned on the lower substrate, the transistor including a semiconductor layer, a gate electrode, a source electrode, and a drain electrode;
a light shield layer covering a lower surface, an upper surface, and a side surface of the semiconductor layer;
an insulator layer covering the upper-surface light shield layer;
an organic light emitting diode on the insulating layer, the organic light emitting diode including a lower electrode, an emissive layer, and an upper electrode which are sequentially stacked,
a dummy lower electrode connected to the upper-surface light shield layer spaced apart from the lower electrode at a same layer level as the lower electrode; and
a bank layer positioned on the insulator layer and covering a portion of the lower electrode;
wherein the light shield layer is electrically connected to the upper electrode,
wherein the light shield layer includes a lower-surface light shield layer positioned below the semiconductor layer, a side-surface light shield layer positioned on at least one side surface of the semiconductor layer, and an upper-surface light shield layer positioned on the semiconductor layer,
wherein the side-surface light shield layer and the upper-surface light shield layer are in physical contact with each other,
wherein the upper-surface light shield layer entirely covers the upper surface of the semiconductor layer,
wherein the upper electrode is electrically connected to the voltage line through the dummy lower electrode and the upper-surface light shield layer,
wherein the insulator layer includes a contact hole through which the upper-surface light shield layer positioned below the insulator layer is exposed,
wherein the bank layer includes a one-side bank layer and another-side bank layer that are separated from each other to expose a surrounding portion of the contact hole,
wherein a partition is positioned between the one-side bank layer and the other-side bank layer, and
wherein the upper electrode and the dummy lower electrode are electrically connected to each other in an internal space of the one-side bank layer and the other-side bank layer.