Patent ID: 11861486
Assignee: DEEPX CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A neural processing unit of a binarized neural network (BNN), the neural processing unit comprising:
a plurality of circuits, wherein the plurality of circuits are connected in a form of pipeline and comprise a first circuitry comprising:
a first sub-circuitry including a NOT logic gate and configured to perform a NOT logic gate operation by using a binarized feature map with a binarized weight,
a second sub-circuitry including a pop-count performing unit and configured to perform an accumulation, and
a third sub-circuitry configured to perform batch-normalization,

wherein the first circuitry is configured to:
determine whether the binarized weight is zero (0) or one (1),
select the first sub-circuitry including the NOT logic gate to which an input value is inputted when the binarized weight is zero (0), and
bypass the input value, thereby directly delivering the input value to the second sub-circuitry including the pop-count performing unit, when the binarized weight is one (1), and
wherein the NOT logic gate of the first sub-circuitry removes or replaces a XNOR logic gate thereby reducing a size of the neural processing unit.