Patent ID: 11907578
Assignee: KOREA ELECTRONICS TECHNOLOGY INSTITUTE
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. A processing-in-memory computing device for efficient instruction processing in a processing-in-memory, the device comprising:
an instruction interpretation processor configured to determine the number of operands required for instruction processing;
a first memory read processor configured to be performed when the number of required operands is either one or two by instruction interpretation;
a read response processor configured to be performed when the number of required operands is one and the instruction is a READ instruction;
a second memory read processor configured to be performed when the number of required operands is two;
an n-th memory read processor configured to be performed when the number of required operands is three (here, n is a natural number of three or greater);
an instruction processor configured to be performed when the number of required operands is one and the instruction is not a READ operation or when the number of required operands is two or more; and
a memory write processor configured to be performed when the number of required operands is one except for a READ operation.