Patent ID: 11901025
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 2:
3. The semiconductor memory device of claim 2, wherein the access storage controller includes:
a first address comparator configured to compare a target row address of a target access address with respective one of first row addresses stored in the access storage to generate a first matching signal, the target access address designating a memory cell row which is currently accessed among from the plurality of memory cell rows;
a counter circuit including a plurality of counters configured to generate the counting value based on the first matching signal and second matching signals provided from the first repair controllers and configured to store the counting values in the access storage; and
a monitor logic connect to the access storage, the monitor logic configured to:
selectively store the target row address in the access storage based on the first matching signal and the second matching signals; and
determine the hammer address based on comparing with a counting value of the target row address with a reference number.