Patent ID: 11900987
Assignee: KATHOLIEKE UNIVERSITEIT LEUVEN
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A non-volatile static random-access memory (NV-SRAM) device including a plurality of bit-cells, each bit-cell comprising:
an SRAM bit-cell;
a first bit-line connected via a first access element to the SRAM bit-cell;
a non-volatile bit-cell comprising a pair of nonvolatile memory elements connected to the SRAM bit-cell through a pair of first transistors,
wherein the pair of first transistors are directly connected to each other through a first restore-line, and
wherein the nonvolatile memory elements have respective first terminals connected to the pair of first transistors and respective second terminals that are electrically shorted to each other through a second restore-line; and
a pair of second bit-lines, wherein each second bit-line is independently connected to one of the nonvolatile memory elements via a respective one of a pair of second transistors,
wherein each of the pair of second transistors is different from the first access element and each of the pair of second bit-lines is different from the first bit-line,
wherein each of the pair of second bit-lines is electrically connected to the SRAM bit-cell via one of the pair of second transistors in series with one of the pair of first transistors,
wherein a drain of each of the pair of second transistors is directly connected to a source of a respective one of the first transistors in series therewith, and further directly connected to the first terminal of the nonvolatile memory element connected to the respective one of the first transistors,
wherein the NV-SRAM device is configured to independently write data from the first bit-line into the SRAM bit-cell through the first access element, and from each second bit-line into a respective one of the nonvolatile memory elements through a respective one of the pair of second transistors,
wherein writing from the each second bit-line comprises switching the respective one of the pair of second transistors by actively biasing a source thereof connected directly to the each second bit-line, and
wherein actively biasing the source of the respective one of the pair of second transistors causes a drain voltage thereof that defines a voltage at the first terminal of the respective one of the nonvolatile memory elements.