Patent ID: 11922619
Assignee: KLA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. An inspection system comprising:
one or more controllers including one or more processors to execute program instructions stored in a memory, the one or more program instructions configured to cause the one or more processors to:
receive empirical data acquired from a sample from a characterization sub-system;
receive design decomposition data from a design decomposition database;
generate one or more probabilistic context maps based on the received empirical data and the received data from the design database prior to inspection runtime;
store the generated one or more probabilistic context maps in the memory;
receive one or more reference images;
receive one or more test images of the sample, the one or more test images including one or more defects of interest (DOIs);
retrieve the stored one or more probabilistic context maps from the memory;
provide the one or more probabilistic context maps to a supervised classifier; and
apply the supervised classifier to the received one or more test images to identify the one or more DOIs on the sample.