Patent ID: 11955200
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A method of operation in an integrated circuit (IC) memory device, the method comprising:
operating first and second command/address (C/A) interfaces independently from one another;
for a first operating mode,
receiving a first read command for first read data via the first C/A interface and receiving a second read command for second read data via the second C/A interface;
transmitting the first and second read data at a first serialization ratio;

for a second operating mode,
receiving the first read command for the first read data via the first C/A interface and receiving the second read command for the second read data via the second C/A interface; and
transmitting the first and second read data at a second serialization ratio that is different than the first serialization ratio.