Patent ID: 11907035
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 15:
16. A system comprising:
a first device comprising a first interface; and
a second device comprising a second interface, wherein the first and second devices are coupled via the first and second interfaces, each of the first and second interfaces comprise respective data pins to support lanes of a data link based on an interconnect protocol, each of the first and second interfaces further comprise a respective auxiliary pin to support a clock power management signal, and the auxiliary pin of the first device is connected to the auxiliary pin of the second device to form an auxiliary connection,
wherein the second device further comprises auxiliary sideband circuitry to:
generate hint data; and
send the hint data as a sideband signal to the first device over the auxiliary connection, wherein the sideband signal is distinct from the clock power management signal.