Patent ID: 11972817
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 3:
4. The memory apparatus as set forth in claim 3, wherein the first status bit and the second status bit define a plurality of latch states each corresponding to one of a plurality of bit line voltages, the plurality of latch states include, in order if increasing magnitude, a first latch state associated with the one of the plurality of bit line voltages being approximately zero volts and a second latch state associated with the one of the plurality of bit line voltages being a quick pass write bit line voltage and a third latch state associated with the one of the plurality of bit line voltages being the quick pass write bit line voltage plus a state look ahead quick pass write bit line voltage and a fourth latch state associated with the one of the plurality of bit line voltages being a fully inhibited bit line voltage and the control means is configured to apply the one of the plurality of bit line voltages to each of the plurality of bit lines coupled to the memory cells being programmed in the program-verify operation depending on which of the plurality of latch states corresponds to the first status bit and the second status bit to adjust a programming speed of the memory cells being programmed while applying one of a plurality of program pulses of the program-verify operation.