Patent ID: 11929326
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A method, comprising:
receiving a workpiece comprising a first contact feature in a first dielectric layer;
depositing an etch stop layer over the workpiece;
depositing a second dielectric layer over the etch stop layer;
forming a via opening through the second dielectric layer and the etch stop layer to expose a portion of the first contact feature;
depositing a seed metal layer in the via opening and over the second dielectric layer;
patterning the seed metal layer to expose a portion of the second dielectric layer;
depositing a third dielectric layer over the patterned seed metal layer and the exposed portion of the second dielectric layer;
depositing a carbon layer over the seed metal layer and the third dielectric layer; and
annealing the workpiece to form a graphene layer between the seed metal layer and the third dielectric layer, between the seed metal layer and the second dielectric layer, between the seed metal layer and the etch stop layer, and between the seed metal layer and the first contact feature.