Patent ID: 11869886
Assignee: SEIKO EPSON CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. The ESD protection circuit according to claim 1, further comprising:
a first diode which is disposed between an N-channel open drain terminal provided to the protection target circuit and a fifth line configured to supply a fifth potential as a potential higher than the second potential, and an anode and a cathode of which are coupled respectively to the N-channel open drain terminal and the fifth line;
a second diode which is disposed between the second line and the N-channel open drain terminal, and an anode and a cathode of which are coupled respectively to the second line and the N-channel open drain terminal; and
a third diode which is disposed between the third line and the fifth line, and an anode and a cathode of which are coupled respectively to the third line and the fifth line.