Patent ID: 11862545
Assignee: nan
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. An integrated substrate structure for coupling a fine-pitched chip, comprising:
a coarse redistribution structure comprising a coarse dielectric layer and a coarse circuitry embedded in the coarse dielectric layer;
a plurality of fine redistribution segments disposed over the coarse redistribution structure and coupled to the fine-pitched chip, the plurality of fine redistribution segments being disposed side by side and spatially apart from one another, each of the plurality of fine redistribution segments comprising:
a fine dielectric layer being thinner than the coarse dielectric layer; and
a fine circuitry embedded in the fine dielectric layer, the fine circuitry comprising a dimension and a pitch finer than those of the coarse circuitry of the coarse redistribution structure, and a layout density of the fine circuitry being denser than a layout density of the coarse circuitry;
a plurality of conductive connectors interposed between the coarse redistribution structure and the plurality of fine redistribution segments, and the coarse circuitry being electrically coupled to the fine circuitry through the plurality of conductive connectors, wherein each of the plurality of conductive connectors comprises a solder joint;
an underfill layer interposed between the coarse redistribution structure and one of the plurality of fine redistribution segments, wherein the underfill layer surrounds and directly contacts the corresponding plurality of conductive connectors located between the coarse redistribution structure and the one of the plurality of fine redistribution segments; and
an embedded chip interposed between the coarse redistribution structure and the one of the plurality of fine redistribution segments, and the embedded chip being physically and electrically connected to the fine circuitry of the one of the plurality of fine redistribution segments,
wherein the embedded chip and the conductive connectors surrounding the embedded chip being embedded in the underfill layer and the underfill layer encloses side surfaces and a bottom surface of the embedded chip.