Patent ID: 11971842
Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 25:
26. The communication system according to claim 25, wherein the first communication device includes
a first memory that stores the first serial signal group transmitted from the master in synchronization with a first clock and stores the second serial signal group transmitted from the slave in synchronization with the first clock,
a first packet encoder that converts the first serial signal group stored in the first memory into a first packet of the predetermined communication protocol,
a first packet decoder that converts a second packet of the predetermined communication protocol received from the second communication device into the second serial signal group, and
the first communication circuitry that transmits the first packet at timing defined in the predetermined communication protocol and receives the second packet at timing defined in the predetermined communication protocol, and, the second communication device includes
a second packet decoder that converts the received first packet into the first serial signal group,
a clock generator that generates a second clock on a basis of the clock frequency information included in in the packet transmitted from the first communication device to the second communication device,
a second memory that stores the first serial signal group in synchronization with the second clock and stores the second serial signal group transmitted from the slave in synchronization with the second clock,
a packet encoder that converts the second serial signal group stored in the second memory into the second packet, and
a second communication circuitry that transmits the second packet at timing defined in the predetermined communication protocol and receives the first packet at timing defined in the predetermined communication protocol.