Patent ID: 11950413
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. A method of forming an integrated circuit (IC) comprising:
providing a semiconductor substrate comprising a first region and a second region;
forming a gate oxide layer in the first region;
forming a polysilicon layer over the first region and the second region, whereby the polysilicon layer forms over the gate oxide layer;
forming a protective layer over the polysilicon layer;
masking the first region;
with the protective layer masked in the first region, selectively removing the protective layer and the polysilicon layer from the second region;
forming a high-κ dielectric layer over the first region and the second region, wherein the protective layer separates the high-κ dielectric layer from the polysilicon layer in the first region;
forming a dummy electrode layer over the high-κ dielectric layer;
patterning the dummy electrode layer and the high-κ dielectric layer to form dummy gates having dummy electrodes in the second region while removing the dummy electrode layer and the high-κ dielectric layer from the first region;
after forming the dummy gates, patterning the protective layer and the polysilicon layer to define polysilicon gates having polysilicon electrodes in the first region;
forming spacers adjacent the dummy gates;
filling an area adjacent the spacers;
planarizing the first and second regions, wherein planarizing exposes the dummy electrodes and the polysilicon electrodes;
removing the dummy electrodes to form voided areas;
depositing metal over the first and second regions, whereby the metal fills the voided areas to form metal electrodes; and
planarizing the first and second regions to remove excess metal.