Patent ID: 11887926
Assignee: KIOXIA CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A semiconductor storage device comprising:
a semiconductor substrate; and
a memory cell array on the semiconductor substrate, the memory cell array being spaced from a surface of the semiconductor substrate in a first direction, the memory cell array including first and second memory hole regions arranged along a second direction parallel to the surface of the semiconductor substrate and a penetrating contact region between the first and second memory hole regions, wherein
the memory cell array comprises:
a first stack including a plurality of first conductive layers and a plurality of first insulating layers alternately stacked in the first direction in the first and second memory hole regions;
a first semiconductor pillar extending through the first stack in the first direction in the first memory hole region;
a second semiconductor pillar extending through the first stack in the first direction in the second memory hole region;
a second stack including a plurality of second insulating layers and a plurality of third insulating layers alternately stacked in the first direction in the penetrating contact region;
a first contact extending through the second stack in the first direction in the penetrating contact region, a lower end of the first contact being closer to the semiconductor substrate than is a lower end of the first stack, and an upper end of the first contact being farther from the semiconductor substrate than is an upper end of the first stack;
a first stopper insulating layer extending in the first and second directions in the penetrating contact region and adjacent to a first side surface of the second stack facing a third direction parallel to the surface of the semiconductor substrate; and
a second stopper insulating layer extending in the first and third directions in the penetrating contact region and adjacent to a second side surface of the second stack facing the second direction, a first distance from a bottom end of the first stopper insulating layer to the semiconductor substrate being different from a second distance from a bottom end of the second stopper insulating layer to the semiconductor substrate,
wherein a width of the first stopper insulating layer in the third direction at a layer level in the first direction that is aligned with one of the second insulating layers is different from a width of the second stopper insulating layer in the second direction at the layer level in the first direction.