Patent ID: 11930640
Assignee: SK HYNIX INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. A semiconductor device comprising:
a substrate having a cell area, an extension area, and a via area;
a transistor and a logic interconnection disposed over the substrate;
a common source region disposed over the transistor and the logic interconnection in the cell area and the extension area;
a support pattern and a lower via plug disposed on a lower insulating layer in the via area;
a word line stack disposed on the common source region in the cell area and the extension area;
a plurality of vertical channel pillars vertically penetrating the word line stack to be commonly connected to the common source region in the cell area;
word line contact plugs electrically connected to the word lines of the word line stack in the extension area, respectively;
a dielectric layer stack disposed on the support pattern, the lower via plug and the lower insulating layer in the via area;
an upper via plug vertically penetrating the dielectric layer stack to be vertically aligned with the lower via plug,
wherein a side surface of the support pattern and a side surface of the lower via plug are in contact with each other,
wherein the support pattern is a conductor; and
wherein the semiconductor device further comprises:
a plurality of support patterns arranged to be spaced apart from each other in a horizontal direction by a portion of the lower insulating layer,
a plurality of lower via plugs, each of the plurality of lower via plugs in directly contact with each of the plurality of support patterns, respectively; and
wherein the support pattern has a pair of segments shaped to contact at least two side surfaces of the lower via plug having a plurality of side surfaces.