Patent ID: 11894853
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 17:
18. The semiconductor memory of claim 17, wherein the first controllable storage circuit comprises:
a first frequency division sub-circuit, a first end of the first frequency division sub-circuit being connected with the second end of the phase calibration circuit, wherein the first frequency division sub-circuit is configured to generate the first storage control signal according to the period of the second signal; and
a first storage sub-circuit, a first end of the first storage sub-circuit being connected with the third end of the second logical circuit, a second end of the first storage sub-circuit being connected with a second end of the first frequency division sub-circuit, a third end of the first storage sub-circuit being connected with the first end of the second detection circuit, wherein the first storage sub-circuit is configured to receive the first storage control signal, and perform at least one of storage or release of the first phase difference pulse signal according to the first storage control signal.