Patent ID: 11935950
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A semiconductor device comprising:
a first buried layer over a substrate;
a second buried layer over the first buried layer;
a first well over the first buried layer and the second buried layer;
a first high voltage well, a second high voltage well, and a third high voltage well extending through the first well, wherein the second high voltage well is between the first high voltage well and the third high voltage well;
a first drain/source region in the first high voltage well;
a first gate electrode over the first well;
a second drain/source region in the second high voltage well;
a third drain/source region in the third high voltage well; and
a second gate electrode formed over the first well.