Patent ID: 11875847
Assignee: STMICROELECTRONICS (ROUSSET) SAS
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. The sense circuit of claim 8,
wherein the input transistor comprises a first p-channel transistor having its source coupled to a second supply voltage, and having its drain coupled to its gate and having the current based upon the input voltage sunk therefrom;
wherein the first output transistor comprises a second p-channel transistor having its source coupled to the second supply voltage, its gate coupled to the gate of the first p-channel transistor, and a drain;
wherein the first diode-coupled transistor comprises a first n-channel transistor having its drain coupled to the drain of the second p-channel transistor, its source coupled to the full read voltage, and its gate coupled to its drain and at which the regulated voltage is produced;
wherein the second output transistor comprises a third p-channel transistor having its source coupled to the second supply voltage, its gate coupled to the gate of the first p-channel transistor, and a drain; and
wherein the second diode-coupled transistor comprises a second n-channel transistor having its drain coupled to the drain of the third p-channel transistor, its source coupled to the fractional read voltage, and its gate coupled to its drain and at which the regulated fractional voltage is produced.