Patent ID: 11929335
Assignee: WINBOND ELECTRONICS CORP.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor structure for wafer level bonding, comprising:
an interconnecting layer comprising a plurality of interconnecting structures disposed on a substrate,
an etching stop layer on the interconnecting layer and directly contacting top surfaces of the interconnecting structures;
a bonding dielectric layer disposed on a the etching stop layer; and
a bonding pad disposed in the bonding dielectric layer and through the etching stop layer to directly contact one of the interconnecting structures, wherein the bonding pad comprises:
a top surface exposed from the bonding dielectric layer;
a bottom surface opposite to the top surface; and
a sidewall between the top surface and the bottom surface, wherein a bottom angle between the sidewall and the bottom surface of the bonding pad is smaller than 90 degrees.