Patent ID: 11862280
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 12:
13. The apparatus of claim 12, wherein each transistor of the first plurality of transistors and the second plurality of transistors further comprises:
the ohmic material at a respective third layer for the transistor, the respective third layer for the first plurality of transistors being a third layer of the first memory array and the respective third layer for the second plurality of transistors being a third layer of the second memory array, wherein the semiconductor material extends into the respective second layer for the transistor, and wherein the ohmic material at the respective third layer for the transistor is in contact with the semiconductor material at the respective second layer for the transistor and is in contact with a conductive plug that extends through the respective first layer for the transistor, the respective second layer for the transistor, and the respective third layer for the transistor.