Patent ID: 11868263
Assignee: VENTANA MICRO SYSTEMS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A method, comprising:
in a microprocessor comprising:
a store queue;
a virtually-indexed first-level data cache that has an allocation policy that permits multiple synonyms to be co-resident in the first-level data cache; and
a physically-indexed physically-tagged second-level set-associative cache, wherein each entry in the second-level cache is uniquely identified by a set index and a way number; and

during execution of a store instruction that specifies store data and a store virtual address:
receiving a store physical address proxy (PAP) for a store physical memory line address from an entry of the first-level data cache hit upon by the store virtual address, wherein the store physical memory line address is a translation of the store virtual address, wherein the store PAP comprises the set index and the way number of an entry of the second-level cache that holds a copy of a line of memory specified by the store physical memory line address; and
writing the store PAP to an entry of the store queue allocated to the store instruction; and

during commit of the store instruction:
reading the store PAP from the store queue;
looking up the store PAP in the first-level data cache to detect synonyms each of which holds a copy of the line of memory specified by the store physical memory line address for which the store PAP is a proxy;
writing the store data to one or more of the detected synonyms; and
evicting the detected synonyms to which the store data is not written.