Patent ID: 11868807
Assignee: IMAGINATION TECHNOLOGIES LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. The apparatus according to claim 7, further comprising:
one or more de-activated scheduled tasks counters; and
hardware logic arranged to check if an ALU pipeline targeted by a decoded instruction from a scheduled task in an active state is full by checking if an ALU pipeline targeted by a decoded instruction from a scheduled task in an active state is full by checking a value of both an ALU work fullness counter and a de-activated scheduled tasks counter associated with the targeted ALU pipeline; and
hardware logic arranged in response to determining that the targeted ALU pipeline is full, to update the de-activated scheduled tasks counter associated with the targeted ALU pipeline; and after triggering the scheduler to re-activate an oldest scheduled task waiting for the ALU pipeline by removing the oldest scheduled task from the waiting state, to update the de-activated scheduled tasks counter associated with the ALU pipeline.