Patent ID: 11894072
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 1:
2. The memory apparatus as set forth in claim 1, wherein the plurality of the plurality of word lines and a plurality of dielectric layers extend horizontally and overlay one another in an alternating fashion in a stack, the strings extend vertically through the stack, the memory cells are connected in series between a drain-side select gate transistor on a drain-side of each of the strings and connected to one of a plurality of bit lines and a source-side select gate transistor on a source-side of each of the strings and connected to a source line, the plurality of neighboring ones of the plurality of word lines are arranged in a plurality of neighboring pairs of the plurality of word lines, each successive one of the plurality of neighboring pairs of the plurality of word lines is progressively arranged more remotely from the selected one of the plurality of word lines and previous ones of the plurality of neighboring pairs, one of the plurality of word lines of each of the plurality of neighboring pairs is disposed on a drain-side of at least one of the selected one of the plurality of word lines and another of the plurality of word lines of each of the plurality of neighboring pairs is disposed on a source-side of at least one of the selected one of the plurality of word lines.