Patent ID: 11956134
Assignee: UFI SPACE CO., LTD.
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 3:
4. A multi-link receiver, comprising:
a receiving circuit, receiving a j-th data section belonging to an i-th data frame;
a processing circuit, coupled to the receiving circuit, and being configured to:
determine a reference delay range of the j-th data section of the i-th data frame according to a preset delay time and a receiving time point of the j-th data section of the i-th data frame, wherein the i-th data frame comprises an N number of data sections, where 1≤j≤N, i is an index value, and N is a positive integer larger than 1;
in response to determining that the j-th data section of the i-th data frame is first received among the N number of data sections of the i-th data frame, take the reference delay range of the j-th data section of the i-th data frame as a designated delay range corresponding to the i-th data frame; and
in response to determining that receiving time points of the data sections of the i-th data frame are each within the designated delay range corresponding to the i-th data frame, restore the i-th data frame based on the N number of data sections of the i-th data frame;
wherein the receiving circuit receives an n-th data section belonging to an m-th data frame, wherein the m-th data frame comprises an N number of data sections, where 1≤n≤N, m is an index value, and m is greater than i; and
in response to determining that a receiving time point of the n-th data section of the m-th data frame is within the designated delay range corresponding to the i-th data frame, the processing circuit ignores the N number of data sections of the i-th data frame.