Patent ID: 11961160
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. The bounding box generation circuit of claim 13, comprising:
a first calculating element comprising:
at least one first comparing element configured to compare at least two x-coordinates of a plurality of x-coordinates and to output a first comparing value; and
at least one first multiplexing element configured to take as inputs the first comparing value and the plurality of x-coordinates, and to output a maximum and a minimum of the plurality of x-coordinates; and

a second calculating element comprising:
at least one first comparing element configured to compare at least two y-coordinates of a plurality of y-coordinates and to output a second comparing value; and
at least one first multiplexing element configured to take as inputs the second comparing value and the plurality of y-coordinates, and to output a maximum and a minimum of the plurality of y-coordinates, and

wherein the maximum and minimum x- and y-coordinates define opposite corners of at least one bounding box for the primitive.