Patent ID: 11915759
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A memory system comprising:
a semiconductor memory including:
a first block including a plurality of first memory cells;
a second block including a plurality of second memory cells;
a plurality of first word lines coupled to the first memory cells;
a plurality of second word lines coupled to the second memory cells; and
a driver circuit capable of applying voltages to the first word lines via a first row decoder and applying voltages to the second word lines via a second row decoder; and

a controller configured to control the semiconductor memory, wherein
in response to a data read command for data stored in the first block or the second block, the data read command being issued by the controller to the semiconductor memory, a first voltage is applied to a selected word line, and a second voltage larger than the first voltage is applied to unselected word lines, and
in response to a first command, the first command being issued by the controller to the semiconductor memory, the driver circuit is configured to apply a third voltage smaller than the first voltage to the plurality of first word lines via the first row decoder and to apply the third voltage to the plurality of second word lines via the second row decoder.