Patent ID: 11860734
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 19:
20. A semiconductor memory device comprising:
a memory cell array;
an on-die error correction code (ECC) engine, based on an ECC, configured to, in a write operation:
perform an ECC encoding operation on main data received from an external memory controller to generate first parity data;
selectively replace a portion of the first parity data with a poison flag received from the external memory controller to generate second parity data, based on a poison mode signal, wherein the poison mode signal designates a normal mode or a poison mode;
output the second parity data and the poison flag;
provide the main data to a normal cell region in a target page of the memory cell array; and
provide the first parity data to a parity cell region in the target page in the normal mode or provide the poison flag and the second parity data to the parity cell region in the poison mode;

a control logic circuit configured to control the on-die ECC engine and to generate the poison mode signal based on a command and an address from the external memory controller, and
wherein, in a read operation, the on-die ECC engine, in response to the poison mode signal designating the poison mode, is configured to:
receive the main data read from the normal cell region in the target page;
receive the poison flag and the second parity data read from the parity cell region in the target page; and
perform an ECC decoding operation on the main data and the poison flag based on the second parity data using the ECC to correct an error bit in the main data and the poison flag,

wherein, in a read operation, the on-die ECC engine, in response to the poison mode signal designating the normal mode, is configured to:
receive the main data read from the normal cell region in the target page;
receive the first parity data read from the parity cell region in the target page; and
perform an ECC decoding operation on the main data based on the first parity data using the ECC to correct one error bit in the main data and detect two error bits in the main data,

wherein the main data comprises a plurality of data bits divided into a plurality of sub data units,
wherein the ECC is represented by a parity check matrix that comprises a plurality of column vectors and a plurality of parity vectors which are divided into a plurality of code groups corresponding to the sub data units and the first parity data, and
wherein the control logic circuit is configured to:
perform don't care process on a row associated with a first parity bit of the first parity data among a plurality of rows of the parity check matrix; and
change a first parity vector associated with the first parity bit among the plurality of parity vectors such that elements of the first parity vector are not overlapped with elements of each of the plurality of column vectors and elements of second parity vectors among the plurality of parity vectors except the first parity vector to generate a modified parity check matrix.