Patent ID: 11961585
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G  H

Claim 17:
18. A system, comprising:
one or more processors;
a memory controller operably coupled to the one or more processors; and
one or more memory devices operably coupled to the memory controller, each memory device of the one or more memory devices comprising:
a bonding pad region including two or more bonding pads for operably coupling to external signals and two or more CA input signals;
a memory cell region for storing information in a number of memory cells; and
a centralized command and address (CA) interface region including two or more CA input circuits operably coupled to two or more CA input signals;
wherein at least two of the two or more CA input circuits are configured in CA pairs and each CA pair comprises:
a first CA input circuit and a second CA input circuit positioned adjacent the first CA input circuit in a mirror relationship;
wherein the first CA input circuit includes a first swap circuit configured to:
select, for a first operation;a first CA output for a first internal CA signal;
select for a second, different operation, the first CA output for a second internal CA signal, and

wherein the second CA input circuit includes a second swap circuit adjacent the first swap circuit and configured to:
select, for the first operation, second CA output for the second internal CA signal; and
select for the second, different operation, the second CA output for the first internal CA signal.