Patent ID: 11963355
Assignee: SK HYNIX INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of manufacturing a semiconductor memory device, the method comprising:
forming a memory cell array on a first substrate, wherein the memory cell array includes:
a gate stack structure with interlayer insulating layers and conductive patterns, which are alternately stacked in a vertical direction,
a plurality of channel structures penetrating the gate stack structure, the plurality of channel structures each with an end portion extending into the first substrate, and
a memory layer extending from between the plurality of channel structures and the gate stack structure to between the end portion of each of the plurality of channel structures and the first substrate;

removing the first substrate to expose the memory layer;
forming a first source layer on the top of the entire structure including the memory layer;
performing an etching process to expose and level the memory layer, the channel structure, and the first source layer to be at the same height; and
forming a second source layer on the memory layer, the channel structure, and the first source layer.