Patent ID: 11899049
Assignee: REALTEK SEMICONDUCTOR CORPORATION
Field: Measurement (Instruments)
Classification: CPC G  H | IPC G  H

Claim 9:
10. The comparison circuit operation method of claim 7, wherein the time accumulating circuit comprises a delay circuit and a triggering circuit, and the triggering circuit comprises a plurality of triggering D flip-flops coupled in series each comprising an input terminal, an output terminal and a clock input terminal configured to receive the stage indication signal, the comparison circuit operation method further comprising:
transmitting the enabling signal by a plurality of delay units coupled in series comprised by the delay circuit;
receiving the enabling signal directly by the input terminal of a first one of the triggering D flip-flops and receiving the enabling signal that the one of the delay units transmit by each of the other triggering D flip-flops electrically coupled to one of the delay units; and
outputting a signal at the input terminal to the output terminal of each of the triggering D flip-flops when the stage indication signal is at the comparison stage finished state;
wherein the comparison time is determined by a number of the triggering D flip-flops that output the enabling signal at the enabling state, and the number is related to a total delay time length of the delay units transmitting the enabling signal at the enabling state.