Patent ID: 11908507
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 19:
20. The memory system according to claim 19, wherein the row address comprises a first row address to a fourth row address, and
wherein the row decoder includes:
a selector configured to select the row address in response to the active command and select the refresh address in response to the refresh command or the hammer refresh command, to generate the first row address to the fourth row address;
a block selection signal generator configured to decode the first row address to generate a plurality of block selection signals for selecting the plurality of memory cell array blocks;
a plurality of first decoders configured to decode the first row address in response to at least one among the plurality of block selection signals to generate a plurality of main word line selection signals for selecting the plurality of main word lines; and
a plurality of second decoders configured to decode the second row address in response to at least one among the plurality of block selection signals to generate a plurality of selection signals for selecting the plurality of selection signal lines,
wherein each of the plurality of conjunction blocks comprises:
a plurality of selection signal drivers configured to drive the plurality of selection signals in response to the random pick signal and the fourth row address to generate a plurality of sub word line selection signals,
wherein each of the even sub word line driver blocks comprises:
a plurality of even sub word line drivers configured to select even-numbered sub word lines among the plurality of sub word lines of each of the sub memory cell array blocks arranged in both sides in response to each of the plurality of main word line selection signals and even-numbered sub word line selection signals among the plurality of sub word line selection signals, and
wherein each of the odd sub word line driver blocks comprises:
a plurality of odd sub word line driver configured to select odd-numbered sub word lines among the plurality of sub word lines of each of the sub memory cell array blocks arranged in both sides in response to each of the plurality of main word line selection signals and odd-numbered sub word line selection signals among the plurality of sub word line selection signals, and
wherein the fourth row address is the page selection signal.