Patent ID: 11907570
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. A system comprising:
a plurality of memory components; and
a processing device, operatively coupled with the plurality of memory components, to:
receive, from a host system at a memory sub-system, a read command to read data from a first block of a first memory die of the memory sub-system;
perform a test read operation on the first block prior to performing a read operation on the first block;
perform the read operation to read the data from the first block;
detect, at the memory sub-system and based at least in part on performing the read operation, that a bit error rate degradation for the first block of the first memory die satisfies a first degradation threshold specific to the first memory die and different from a second degradation threshold specific to a second memory die of the memory sub-system, the first degradation threshold associated with data recovery for the first memory die, wherein the first degradation threshold is set according to a number of read operations that triggers a data recovery procedure for the first block; and
write the data from the first block of the first memory die to a second block of the first memory die based at least in part on detecting that the bit error rate degradation satisfies the first degradation threshold or on an unsuccessful test read operation.