Patent ID: 11963364
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor device comprising:
a first stacked structure including a plurality of first insulating patterns and a plurality of first semiconductor patterns alternately stacked on a substrate, the first stacked structure extending in a first direction, each of a first semiconductor pattern of the plurality of first semiconductor patterns including a first impurity region, a first channel region, and second impurity region arranged in a sequential order along the first direction, the first direction being parallel to an upper surface of the substrate;
a first conductive pattern on a first side surface of the first stacked structure, the first conductive pattern extending in a second direction, the second direction crossing the upper surface of the substrate;
a first ferroelectric layer between the first stacked structure and the first conductive pattern, the first ferroelectric layer extending in the second direction;
a first wiring structure including a plurality of second insulating patterns and a plurality of first wiring patterns alternately stacked on the substrate, the first wiring structure extending in a third direction parallel to the upper surface of the substrate and crossing the first direction, each of the plurality of first wiring patterns is connected to the first impurity region of each of the plurality of first semiconductor patterns; and
a second wiring structure including a plurality of third insulating patterns and a plurality of second wiring patterns alternately stacked on the substrate, the second wiring structure extending in the third direction, each of the plurality of second wiring patterns is connected to the second impurity region of each of the plurality of first semiconductor patterns.