Patent ID: 11937437
Assignee: KIOXIA CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor memory comprising:
a first semiconductor layer provided above a substrate in a first direction perpendicular to the substrate, and extending in a second direction parallel to the substrate, the first semiconductor layer having one end and other end in the second direction, the one end being a source, the other end being a drain;
a second semiconductor layer provided above the first semiconductor layer in the first direction and extending in the second direction;
a third semiconductor layer arranged at the first semiconductor layer in a third direction crossing the first and second directions, and extending in the second direction;
a first gate electrode provided on first side surfaces of the first semiconductor layer and the second semiconductor layer, and extending in the first direction;
a second gate electrode provided on second side surfaces of the first semiconductor layer and the second semiconductor layer, separated from the first gate electrode in the third direction, and extending in the first direction;
a third gate electrode provided on the first side surfaces of the first semiconductor layer and the second semiconductor layer, and extending in the first direction, the third gate electrode arranged at the first gate electrode in the second direction;
a first memory cell provided at an intersection between the first gate electrode and the first semiconductor layer; and
a second memory cell provided at an intersection between the second gate electrode and the first semiconductor layer,
wherein the first gate electrode is electrically connected to the second gate electrode.