Patent ID: 11894482
Assignee: DUAL HELIOS SEMICONDUCTOR EQUIPMENT COMPANY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A system for processing a wafer, the system comprising:
a frame comprising a frame opening; and
a membrane configured to couple to the frame and to cover at least a part of the frame opening, the membrane comprising a membrane opening, wherein the membrane opening has a membrane opening area that is equal to or less than a frame opening area of the frame opening;
wherein the membrane is configured for coupling with the wafer, wherein when the wafer is coupled with the membrane, the wafer covers the membrane opening, and wherein the membrane is configured to maintain the wafer at a certain position with respect to the frame;
wherein the membrane opening area is less than a total area of the wafer; and
wherein the frame comprises a plasma resistant coating.