Patent ID: 11950405
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A semiconductor device comprising:
a substrate;
a first insulating layer on the substrate;
a first horizontal gate pattern on the first insulating layer;
a first semiconductor pattern on the first horizontal gate pattern, the first semiconductor pattern including a first end, a second end opposite the first end, and a first channel region between the first end and the second end;
a second horizontal gate pattern on the first semiconductor pattern;
a second insulating layer on the second horizontal gate pattern;
a third horizontal gate pattern on the second insulating layer;
a second semiconductor pattern on the third horizontal gate pattern, the second semiconductor pattern including a third end, a fourth end opposite the third end, and a second channel region between the third end and the fourth end;
a fourth horizontal gate pattern on the second semiconductor pattern;
a third insulating layer on the fourth horizontal gate pattern;
a vertical gate pattern passing through the first semiconductor pattern and the second semiconductor pattern;
a first bit line between the first insulating layer and the second insulating layer and connected to the first end of the first semiconductor pattern;
a second bit line between the second insulating layer and the third insulating layer and connected to the third end of the second semiconductor pattern;
a first capacitor lower electrode between the first insulating layer and the second insulating layer and connected to the second end of the first semiconductor pattern; and
a second capacitor lower electrode between the second insulating layer and the third insulating layer and connected to the fourth end of the second semiconductor pattern,
wherein the vertical gate pattern contacts the first to fourth horizontal gate patterns.