Patent ID: 11960811
Assignee: SYNOPSYS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A method comprising:
accessing a first circuit netlist that is related to a reference circuit netlist, wherein the reference circuit netlist is a pre-layout circuit netlist and the first circuit netlist is a post-layout circuit netlist;
accessing the pre-layout circuit netlist and partitioning the pre-layout circuit netlist into pre-layout sub-circuits;
accessing the post-layout circuit netlist and partitioning the post-layout circuit netlist into post-layout sub-circuits that correspond to the pre-layout sub-circuits;
applying first circuit simulations to the pre-layout sub-circuits, the first circuit simulations producing driving information for some of the pre-layout subcircuits; and
applying, by a processing device, second circuit simulations to the post-layout sub-circuits, wherein the driving information produced by the first circuit simulations of the pre-layout sub-circuits provide stimulus for inputs to the second circuit simulations of the post-layout sub-circuits.