Patent ID: 11888887
Assignee: nan
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A system comprising:
one or more processors; and
a memory storing instructions which, when executed by the one or more processors, causes performance of:
receiving first vulnerability data for a plurality of entities identifying first asset vulnerabilities and timing data corresponding to the first vulnerability data, the timing data indicating an amount of time between identification of an asset vulnerability and a result of the asset vulnerability, wherein the first asset vulnerabilities represent resolved asset vulnerabilities;
identifying a strict subset of the first vulnerability data that belongs to a particular category of a first plurality of categories;
receiving second vulnerability data for a particular entity identifying second asset vulnerabilities;
identifying a strict subset of the second vulnerability data that belongs to the particular category; and
based, at least in part, on the strict subset of the first vulnerability data, computing a time to remediate the second asset vulnerabilities in the strict subset of the second vulnerability data.