Patent ID: 11899574
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 3:
4. The memory system of claim 1, wherein the operations further comprise:
receiving a read request;
identifying whether a logical block address (LBA) of the read request matches an LBA of a record in the second cache;
responsive to identifying that the LBA of the read request does not match the LBA of the record in the second cache, identifying whether the LBA of the read request matches an LBA of a record in the first cache;
responsive to identifying that the LBA of the read request does not match the LBA of the record in the first cache, loading a record of the LBA from a logical-to-physical table stored in a NAND storage array into the first cache; and
reading a value stored in a physical address referenced by the mapping between physical and logical addresses corresponding to the write request.