Patent ID: 11950422
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An assembly, comprising:
a vertical stack of alternating insulative levels and wordline levels, the wordline levels comprising conductive regions having a concave vertical face and the insulative levels having substantially planar vertical faces;
charge-storage regions adjacent the conductive regions and having upper surfaces and lower surfaces, each of the upper and lower surfaces contacting an insulative material of the insulative levels, each of the charge-storage regions having a first concave face and an opposing second concave face;
charge-blocking regions between the charge-storage regions and the conductive regions, each of the charge-blocking regions having a third vertical face and an opposing fourth vertical face; the charge-blocking regions comprising silicon dioxide extending vertically along silicon oxynitride; the silicon dioxide being between the silicon oxynitride and the charge-storage regions, each of the first, second, third and fourth vertical faces being concave;
a first tunneling material entirely within the wordline levels and having concave opposing inner and outer faces; and
a second tunneling material extending along the first tunneling material and along and in direct physical contact with the substantially planar vertical faces of the insulative levels.