Patent ID: 11935935
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A method of forming a transistor, comprising:
forming a gate electrode in an insulating layer over a substrate;
forming a gate dielectric over the gate electrode, wherein the gate dielectric comprises a center gate dielectric portion having a first thickness and contacting a top surface of the gate electrode, and a pair of peripheral gate dielectric portions having a second thickness that is greater than the first thickness and contacting a top surface of the insulating layer;
forming an active layer comprising a compound semiconductor material over the gate dielectric; and
forming a source electrode and a drain electrode on peripheral portions of the active layer, wherein the source electrode and the drain electrode are laterally spaced from each other by the gate electrode.