Patent ID: 11888964
Assignee: BEIJING TENAFE ELECTRONIC TECHNOLOGY CO., LTD.
Field: Control (Instruments)
Classification: CPC H  G | IPC H

Claim 0:
1. A system, comprising:
a memory; and
a processor coupled to the memory, wherein:
there is a plurality of data processing units where each of the plurality of data processing units independently performs an end-to-end encryption operation associated with Advanced Encryption Standard (AES) on a data block;
the processor selects a selected key length, from a plurality of supported key lengths associated with the AES;
the processor selects a number of data processing units to have in the plurality of data processing units based at least in part on a desired processing throughput rate and power consumption, wherein the number of data processing units and the selected key length produce a total processing throughput rate, collectively for the plurality of data processing units, that is a multiple of one or more of the following: 1/10, 1/12 or 1/14 of a maximum throughput rate; and
the processor selects a target data processing unit, from the plurality of data processing units, to:
receive a target data block that is to be encrypted, including by:
sequentially communicating with the plurality of data processing units in a round-robin order to obtain an idle state information until an idle data processing unit in the plurality of data processing units is encountered; and
selecting the idle data processing unit to be the target data processing unit; and

generate a ciphertext data block corresponding to the target data block, including by performing the end-to-end encryption operation associated with AES, including all SubByte transformations, all ShiftRow transformations, all MixColumn transformations, and all AddRoundKey transformations on the target data block.