Patent ID: 11881869
Assignee: SK HYNIX INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for improving a performance of an iterative decoder in a non-volatile memory, comprising:
receiving a noisy codeword that is based on a transmitted codeword generated from a low-density parity-check (LDPC) code;
partitioning a maximum number of iterations of the iterative decoder into a plurality of stages, each stage comprising a first number of iterations;
initializing a set of log likelihood ratios (LLRs) with symmetric LLRs;
for each stage of the plurality of stages:
performing, for each iteration of the first number of iterations and based on the set of LLRs, a message passing algorithm between a plurality of variable nodes and a plurality of check nodes that represent a parity matrix of the LDPC code,
determining, at a last iteration of the first number of iterations for the stage, a hard decision corresponding to a candidate version of the transmitted codeword,
determining, based on the hard decision, a set of asymmetric LLRs, and
assigning the set of asymmetric LLRs to the set of LLRs; and

determining the candidate version of the transmitted codeword using the set of LLRs.