Patent ID: 11909388
Assignee: SHENZHEN PANGO MICROSYSTEMS CO., LTD
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A terminal resistance circuit, adapted for a high-speed differential input/output (I/O) pair of a chip; wherein the high-speed differential I/O pair comprises a first interface and a second interface, and the terminal resistance circuit comprises:
two resistance circuits, wherein an end of the two resistance circuits connected in series is electrically connected to the first interface, another end of the two resistance circuits connected in series is electrically connected to the second interface, a conductor wire connected between the two resistance circuits has a target node thereon, and the two resistance circuits are symmetrically arranged with respect to the target node; and
a control circuit, electrically connected to the two resistance circuits individually and configured to control the two resistance circuits each to be in a turn-off state during powering-on of the chip.