Patent ID: 11925013
Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A memory device using a pillar-shaped semiconductor element, comprising:
a first semiconductor pillar, a second semiconductor pillar, a third semiconductor pillar, and a fourth semiconductor pillar, the first semiconductor pillar and the second semiconductor pillar standing on a substrate in a vertical direction, having respective center points on a first line in plan view, and being adjacent to each other, the third semiconductor pillar and the fourth semiconductor pillar standing on the substrate in the vertical direction, having respective center points on a second line parallel to the first line in plan view, and being adjacent to each other;
a first impurity region connected to bottom portions of the first to fourth semiconductor pillars;
first gate insulating layers located above the first impurity region in the vertical direction and each surrounding a lower portion of a corresponding one of the first to fourth semiconductor pillars;
first gate conductor layers and second gate conductor layers surrounding the respective first gate insulating layers, the first gate conductor layers being continuous around the first semiconductor pillar and the second semiconductor pillar, the second gate conductor layers being continuous around the third semiconductor pillar and the fourth semiconductor pillar;
second gate insulating layers located above the respective first gate insulating layers and each surrounding a side surface of a corresponding one of the first to fourth semiconductor pillars;
third gate conductor layers and fourth gate conductor layers surrounding the respective second gate insulating layers, each having an upper surface located below top portions of the first to fourth semiconductor pillars in the vertical direction, and each being apart from the first gate conductor layers and the second gate conductor layers in the vertical direction, the third gate conductor layers being continuous around the first semiconductor pillar and the second semiconductor pillar, the fourth gate conductor layers being continuous around the third semiconductor pillar and the fourth semiconductor pillar;
second impurity regions at the respective top portions of the first to fourth semiconductor pillars;
a first wiring conductor layer connected to the second impurity regions at the respective top portions of the first semiconductor pillar and the third semiconductor pillar; and
a second wiring conductor layer connected to the second impurity regions at the respective top portions of the second semiconductor pillar and the fourth semiconductor pillar, wherein
the first gate conductor layer of the first semiconductor pillar and the first gate conductor layer of the second semiconductor pillar are in contact with each other, and the first gate conductor layer of the third semiconductor pillar and the first gate conductor layer of the fourth semiconductor pillar are in contact with each other,
in plan view, a first length between two opposing intersections among intersections between the first line and two outer periphery edges of the first gate insulating layers surrounding the first semiconductor pillar and the second semiconductor pillar is smaller than twice a second length that is a thickness of a portion of each of the first gate conductor layers that is not in contact with the other first gate conductor layers, and
voltages to be applied to the first gate conductor layers, the second gate conductor layers, the third gate conductor layers, the fourth gate conductor layers, the first impurity region, and the second impurity region regions are controlled to perform a data write operation, a data erase operation, and a data read operation.