Patent ID: 11908505
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 4:
5. The data processing device of claim 4, further comprising:
a plurality of wordlines (“WLs”), each connected to the gates of the FeFETs in a respective row of the memory devices;
a plurality of ML-enable lines, each connected to the gates of the ML switching transistors in a respective row of the memory devices;
a plurality of pairs of first and second bitlines (“BLs”), wherein the first BL in each pair is connected to the drains of the FeFETs in the first data storage units in a respective column of the memory cells, and the second BL in each pair is connected to the drains of the FeFETs in the second data storage units in a respective column of the memory cells;
a plurality of pairs of selectlines (“SLs”), wherein the first SL in each pair is connected to the sources of the FeFETs in the first data storage units in a respective column of the memory cells, and the second SL in each pair is connected to the sources of the FeFETs in the second data storage units in a respective column of the memory cells; and
a plurality of pairs of first and second inputlines (“INs”), wherein the first IN in each pair is connected to the gates of the input switching transistors in the first data storage units in a respective column of the memory cells, and the second IN in each pair is connected to the gates of the input switching transistors in the second data storage units in a respective column of the memory cells.