Patent ID: 11925022
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 11:
12. A method of forming a semiconductor device, the method comprising:
forming an opening extending through a tiered material structure comprising an insulative material interleaved with an other material;
forming a charge-blocking material in the opening along a sidewall of the tiered material structure;
forming a charge storage material in the opening along a sidewall of the charge-blocking material;
forming a tunneling structure, comprising:
forming a high-κ material in the opening along a sidewall of the charge storage material;
oxidizing only a portion of the high-κ material to convert the portion of the high-κ material into an oxide material, to form a first portion of the tunneling structure comprising the high-κ material, and to form a second portion of the tunneling structure consisting essentially of oxide material comprising the oxide material formed from the portion of the high-κ material, the second portion of the tunneling structure being substantially free of the high-κ material and being above the first portion of the tunneling structure, an entirety of the high-κ material of the first portion being elevationally below the second portion of the tunneling structure; and

forming a channel structure, comprising:
forming a channel material in the opening along a sidewall of the tunneling structure, the channel structure comprising a first channel portion along a sidewall of the first portion of the tunneling structure and comprising a second channel portion along a sidewall of the second portion of the tunneling structure,
the channel material of the first channel portion differing in at least one of thickness, horizontal outer dimension, and composition from the channel material of the second channel portion.