Patent ID: 11948890
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A device comprising:
an integrated circuit die comprising a conductive pillar;
a through via adjacent the integrated circuit die;
a molding compound encapsulating the integrated circuit die and the through via; and
a redistribution structure comprising:
a first conductive via extending through a first dielectric layer, the first conductive via electrically connected to the integrated circuit die through the conductive pillar, wherein a topmost surface of the first conductive via extends above a topmost surface of the first dielectric layer, the conductive pillar having a top surface that is coplanar with a top surface of the through via and a top surface of the molding compound, the first dielectric layer being over the integrated circuit die, the through via, and the molding compound; and
a first conductive line over the first dielectric layer and the first conductive via, the first conductive via extending into the first conductive line, wherein the first conductive line comprises:
a seed layer extending along the topmost surface of the first dielectric layer, sides of the first conductive via, and the topmost surface of the first conductive via; and
a conductive material disposed on the seed layer.