Patent ID: 11968822
Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A memory device using a semiconductor element, comprising:
a first semiconductor pillar standing on a substrate in a vertical direction to the substrate, the first semiconductor pillar including, from bottom to top, a first impurity layer, a first semiconductor layer, and a second impurity layer;
a second semiconductor pillar on top of the first semiconductor pillar in such a manner as to be connected to the first semiconductor pillar in the vertical direction, the second semiconductor pillar including, from bottom to top, the second impurity layer, a second semiconductor layer, and a third impurity layer, the second impurity layer being shared with the first semiconductor pillar;
a first gate insulating layer surrounding a lower portion of the first semiconductor pillar;
a first gate conductor layer surrounding the first gate insulating layer;
a second gate insulating layer surrounding an upper portion of the first semiconductor pillar;
a second gate conductor layer surrounding the second gate insulating layer;
a third gate insulating layer surrounding a lower portion of the second semiconductor pillar;
a third gate conductor layer surrounding the third gate insulating layer;
a fourth gate insulating layer surrounding an upper portion of the second semiconductor pillar; and
a fourth gate conductor layer surrounding the fourth gate insulating layer, wherein
the memory device is configured to perform:
a data write operation for controlling voltages to be applied to the first gate conductor layer, the second gate conductor layer, the third gate conductor layer, the fourth gate conductor layer, the first impurity layer, the second impurity layer, and the third impurity layer to form, in both or one of the first semiconductor layer and the second semiconductor layer, a hole group or an electron group serving as majority carriers of both or one of the first semiconductor layer and the second semiconductor layer, the hole group or the electron group being formed by an impact ionization phenomenon or a gate induced drain leakage current, and to hold the formed hole group or electron group in both or one of the first semiconductor layer and the second semiconductor layer; and
a data erase operation for controlling the voltages to be applied to the first gate conductor layer, the second gate conductor layer, the third gate conductor layer, the fourth gate conductor layer, the first impurity layer, the second impurity layer, and the third impurity layer to discharge the hole group or the electron group serving as majority carriers from within both or one of the first semiconductor layer and the second semiconductor layer.