Patent ID: 11881246
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An electronic device comprising:
a target address generation circuit configured to generate a counting signal by counting the number of times each logic level combination of an address is input by performing an internal read operation and an internal write operation during an active operation, configured to store the counting signal as the storage counting signal when the counting signal is counted more than a storage counting signal that is stored therein, and configured to store the address, corresponding to the counting signal, as a target address;
a refresh control circuit configured to control a smart refresh operation on the target address, and
wherein the target address generation circuit is configured to initialize row hammering cells that store the counting signal that is counted to be the same as the storage counting signal after the smart refresh operation is performed.