Patent ID: 11894052
Assignee: STMICROELECTRONICS S.R.L.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 22:
23. An in-memory computation circuit, comprising:
a memory array including a plurality of memory cells arranged in a matrix with plural rows and plural columns, the memory cells storing computational weights for an in-memory compute operation, each row including a word line connected to the memory cells of the row, and each column including a bit line connected to the memory cells of the column;
a biasing circuit for each bit line, each biasing circuit connected between the bit line and a column output and configured to apply a fixed reference voltage level to said bit line;
wherein an analog signal at the column output is dependent on the coefficient data and computational weight; and
a column combining circuit configured to combine and integrate the analog signals generated at the column outputs of the biasing circuits.