Patent ID: 11921636
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A device comprising:
a processor that includes a template register configured to store a stream definition template that specifies a respective count for each loop of a set of nested loops;
a cache memory;
a circuit coupled to the processor and the cache memory and configured to:
receive a stream open instruction;
receive a format value that specifies whether a portion of the template register is associated with the respective count for a first loop of the set of nested loops or the respective count for a second loop of the set of nested loops;
based on the stream open instruction and the format value:
generate a set of addresses based on the set of nested loops according to the stream definition template; and
using the set of addresses, retrieving the set of data from the cache memory;

receive a stream read instruction; and
based on the stream read instruction, provide a portion of the set of data to the processor.