Patent ID: 11942364
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A method of forming a contact via, comprising:
forming an etch stop layer (ESL) over a lower conductive structure;
forming a first interconnect dielectric layer over the ESL;
forming a second interconnect dielectric layer over the first interconnect dielectric layer;
forming a first masking structure comprising a first opening over the second interconnect dielectric layer;
performing a first removal process to remove portions of the first and second interconnect dielectric layers arranged below the first opening to form a first trench structure;
performing a second removal process to remove additional portions of the first and second interconnect dielectric layers according to remaining portions of the first masking structure to form a second trench structure and to extend the first trench structure, wherein a bottom surface of the first trench structure is defined by an upper surface of the ESL;
depositing a protective layer selectively on the first and second interconnect dielectric layers, wherein the upper surface of the ESL still defines the bottom surface of the first trench structure;
performing a third removal process to remove additional portions of the ESL that are uncovered by the first interconnect dielectric layer or the protective layer to expose the lower conductive structure; and
forming a conductive material within the first and second trench structures to form an interconnect via and an interconnect wire arranged over and coupled to the lower conductive structure.