Patent ID: 11923043
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: nan (nan)
Classification: CPC nan | IPC G  H

Claim 0:
1. A memory, comprising:
a clock generation circuit, configured to generate a first oscillation signal and a second oscillation signal, wherein the first oscillation signal and the second oscillation signal have a same frequency but opposite phases, and a duty cycle of the first oscillation signal and a duty cycle of the second oscillation signal are both within a first preset range; and
a differential input circuit, configured to receive a first external signal and a second external signal, and generate a first internal signal and a second internal signal; wherein the differential input circuit is further configured to receive the first oscillation signal and a second oscillation signal;
wherein the clock generation circuit is further configured to monitor at least one of a duty cycle of the first internal signal or a duty cycle of the second internal signal, and enable the at least one of the duty cycle of the first internal signal or the duty cycle of the second internal signal to be within a second preset range;
wherein the clock generation circuit comprises:
an oscillation circuit, configured to generate the first oscillation signal and the second oscillation signal;
a comparison circuit, configured to receive the first oscillation signal and the second oscillation signal, and compare the at least one of the duty cycle of the first oscillation signal or the duty cycle of the second oscillation signal; and
a logical unit, connected with the comparison circuit and the oscillation circuit, the logical unit being configured to control the oscillation circuit according to an output result of the comparison circuit, so that the duty cycle of the first oscillation signal and the duty cycle of the second oscillation signal are within the first preset range;
wherein the comparison circuit is further connected with an output terminal of the differential input circuit, and the comparison circuit is configured to receive the first internal signal and the second internal signal, and compare the at least one of the duty cycle of the first internal signal or the duty cycle of the second internal signal; and
wherein the logical unit is further connected with the differential input circuit, and configured to control the differential input circuit according to the output result of the comparison circuit, so that the at least one of the duty cycle of the first internal signal or the duty cycle of the second internal signal is within the second preset range.