Patent ID: 11954364
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 6:
7. A method of controlling a memory system including a plurality of memory chips operable in parallel, each memory chip of the plurality of memory chips including a plurality of first storage areas, the method comprising:
generating a plurality of first groups, each first group of the plurality of first groups including first storage areas selected from different memory chips among the plurality of memory chips;
generating a plurality of second groups, each second group of the plurality of the second group being constituted by a minimum number of first storage areas composed by excluding one or more first storage areas from each first group of the plurality of first groups, the minimum number of first storage areas being capable of storing at least a first amount of data received from the host;
executing writing of the data to all the minimum number of first storage areas constituting one second group;
setting, to be unusable, one or more first storage areas included in a first second group of the plurality of second groups; and,
based on a second amount becoming smaller than the first amount due to the setting of the one or more first storage areas to be unusable, adding at least one of second storage areas to the first second group, the second storage areas each being the first storage area excluded from any first group of the plurality of first groups, the second amount indicating a storage capacity of the first second group capable of storing data received from the host.