Patent ID: 11929407
Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of fabricating a high electron mobility transistor, comprising:
providing a substrate having a group III-V channel layer, a group III-V barrier layer, a group III-V gate layer, and a gate etch stop layer disposed thereon;
forming a passivation layer covering the group III-V barrier layer and the gate etch stop layer;
forming a gate contact hole and at least one source/drain contact hole in the passivation layer, wherein the gate contact hole exposes the gate etch stop layer, and the at least one source/drain contact hole exposes the group III-V channel layer; and
forming a conductive layer conformally disposed on a top surface of the passivation layer and in the gate contact hole and the at least one source/drain contact hole.