Patent ID: 11950402
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 8:
9. A method comprising:
forming levels of materials;
forming a first dielectric material over the levels of materials;
forming first trenches in at least the dielectric material, each of the first trenches including a length in a first direction;
forming a semiconductor material in the first trenches;
forming a second dielectric material over the semiconductor material;
forming charge storage material over the second dielectric material, such in each of the trenches the charge storage material includes a first portion and a second portion opposite and separated from the first portion in each of the first trenches;
forming a third dielectric material on respective side walls the first and second portions of the charge storage material;
forming a conductive material between the first and second portions of the charge storage material, such that the conductive material is separated from the first and second portions of the charge storage material by the third dielectric material;
removing a portion of the conductive material, the third dielectric material, and the charge storage material from the first trenches;
forming an additional material in the first trenches and over remaining portions of the charge storage material; and
forming second trenches extending in a second direction across materials in the first trenches to form memory cells, such that a remaining part of the first and second portions of the charge storage material formed in each of the first trenches forms respective charge storage structures of the memory cells.