Patent ID: 11894382
Assignee: STMICROELECTRONICS FRANCE
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 2:
3. The integrated circuit according to claim 2, comprising at least two standard filling cells adjacent to the first standard cell, respectively disposed between the first standard cell and the two second standard cells, respectively butted to the first standard cell and to the two second standard cells, each of the at least two standard filling cells including a filling region having a first part containing silicon and germanium in contact with the active area at least one of the at least two PMOS transistors of the first standard cell and a second part containing silicon in contact with the active area of at least one of the at least two PMOS transistors of the second corresponding standard cell, and two first polysilicon lines located above a border between the filling cell and the first standard cell or the second standard cell respectively, and configured to be biased at a supply voltage, the filling regions forming the semiconductor connection region.