Patent ID: 11902785
Assignee: INTEL CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An apparatus comprising:
at least one memory;
instructions;
programmable circuitry to be programmed by the instructions to:
cause a first transmission of a first challenge packet at a first frequency, the first challenge packet to instruct a first electronic system to transmit a first challenge response at a second frequency, the first frequency and the second frequency based on a first frequency band hopping pattern;
cause a second transmission of a second challenge packet at a third frequency, the second challenge packet to instruct a second electronic system to transmit a second challenge response at a fourth frequency, the third frequency and the fourth frequency based on a second frequency band hopping pattern;
increment a counter corresponding to the first electronic system if no first challenge response is received from the first electronic system; and
after a determination that the counter satisfies a threshold, cause a third transmission of a data packet to a third electronic system to cause the third electronic system to ignore at least one future message from the first electronic system.