Patent ID: 11876064
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. The manufacturing method according to claim 11, further comprising, before forming the metal barrier layer:
forming a first mask layer on a side of the semiconductor substrate wherein the first solder layer is formed;
applying a photolithography process to pattern the first mask layer to expose a part of the first solder layer;
etching the first solder layer with a chemical acid etching process to expose the bump;
removing the first mask layer;
forming a second mask layer; and
applying a photolithography process to pattern the second mask layer to expose the first solder layer and a part of the bump, and disposing the metal barrier layer on the first solder layer, the bump, and the second mask layer, wherein the metal barrier layer covers a portion of the first solder layer.