Patent ID: 11901033
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. An operating method of a memory device including first page buffers connected to a first bit line group, second page buffers connected to a second bit line group, third page buffers connected to a third bit line group, and fourth page buffers connected to a fourth bit line group, the operating method comprising:
receiving an address for memory access from a memory controller;
determining whether a column address in the address is a defect address;
when the column address is not the defect address, accessing first normal memory cells corresponding to the column address, the first normal memory cells connected to the first bit line group or the second bit line group;
when the column address is the defect address, accessing first redundant memory cells corresponding to a repair address, the first redundant memory cells connected to the third bit line group or the fourth bit line group; and
outputting as a decoder output signal, first data received from the first page buffers through a first wired OR line, second data received from the second page buffers through a second wired OR line, third data received from the third page buffers through a third wired OR line, and fourth data received from the fourth page buffers through a fourth wired OR line, the outputting according to column repair information,
wherein the first and second page buffers are connected to normal memory cells and collinear in a first direction,
the third and fourth page buffers are connected to redundant memory cells and collinear in the first direction,
a first width of a region including the first bit line group is the same as a width of a first gate in a first transistor of a second direction, the first transistor included in each of the first page buffers,
a second width of a second region including the second bit line group is the same as a width of a second gate of a second transistor in the second direction, the second transistor included in each of the second page buffers, and
the first transistor in the first page buffers and the second transistor included in the second page buffers are collinear in the first direction.