Patent ID: 11935894
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. An integrated circuit device, comprising:
a cell, the cell comprising:
a device layer having devices spaced in accordance with a device pitch;
a first interconnection layer disposed above the device layer and coupled to the device layer; and
a second interconnection layer disposed above the first interconnection layer and coupled to the first interconnection layer,
wherein the second interconnection layer has connection lines spaced in accordance with a connection line pitch, and
wherein a ratio of the connection line pitch to device pitch is less than 1,
wherein the cell conforms with the equation M0_Enc≤(Max_M0_Length−Max_M1_Pitch_Length−VIA0_Width)/2, where:
Max_M0_Length represents a maximum possible length of a line in the first interconnection layer in the cell;
Max_M1_Pitch_Length represents a maximum possible pitch between two lines in the second interconnection layer in the cell;
VIA0_Width represents a width of a via that connects a line in the first interconnection layer with a line in the second interconnection layer; and
M0_Enc represents a distance from an outermost edge of the line in the first interconnection layer to an edge of a nearest possible via connecting the line in the first interconnection layer to the line in the second interconnection layer.