Patent ID: 11929115
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A memory device, comprising:
memory cells, each comprising:
a static random access memory (SRAM) cell, configured to store complementary data at first and second storage nodes; and
a non-volatile memory cell, configured to replicate and retain the complementary data stored in the SRAM cell, and comprising a first ferroelectric tunneling junction (FTJ) and a second FTJ, wherein the first and second FTJs respectively have a first terminal connected to a first bit line, a second terminal of the first FTJ is selectively connected to the first storage node of the SRAM cell and selectively connected to a second bit line, and a second terminal of the second FTJ is selectively connected to the second storage node of the SRAM cell and selectively connected to the second bit line.