Patent ID: 11948874
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. An integrated circuit (IC), comprising:
a device layer comprising a plurality of transistors comprising one or more semiconductor materials; and
a plurality of interconnect levels over the device layer, wherein the interconnect levels further comprise:
a first interconnect level comprising:
a first metallization line co-planar with an adjacent second metallization line;
a third metallization line out of a plane of the first and second metallization lines, the third metallization line having a centerline coincident with a centerline of a space between the first and second metallization lines; and

a second interconnect level above or below the first interconnect level, the second interconnect level comprising one or more metallization lines interconnected to one or more of the first, second, or third metallization lines by via metallization.