Patent ID: 11870399
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. The receiver of claim 9, wherein the control circuit includes:
first and second inverters connected in series to receive the internal signal;
an exclusive OR gate that receives the internal signal and an output of the first and second inverters connected in series;
a multiplexer that has a first input connected to a power supply voltage line and a second input connected to a ground voltage line, outputs a power supply voltage level of the first input in response to a first logic level of the selection signal, and outputs a ground voltage level of the second input in response to a second logic level of the selection signal;
a flip-flop having a data input connected to an output line of the multiplexer and a clock input connected to an internal signal line; and
a NOR gate that receives an output of the exclusive OR gate and an output of the flip-flop and outputs the control signal.