Patent ID: 11937432
Assignee: KIOXIA CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor device comprising:
a semiconductor substrate having a main surface;
a first insulating layer disposed in a groove extending in a direction perpendicular to the main surface of the semiconductor substrate;
a plurality of transistor pairs that are formed on the first insulating layer, arranged in a first direction along the main surface of the semiconductor substrate, and arranged in a second direction intersecting the first direction, wherein
each of the plurality of transistor pairs has (i) a first semiconductor layer formed on the first insulating layer and including a first region, a second region, a third region, a fourth region, and a fifth region sequentially arranged in the first direction, (ii) second insulating layers respectively disposed on the second region and the fourth region of the first semiconductor layer, and (iii) first conductive layers respectively disposed on the second insulating layers,
a first contact is connected to the first region,
a second contact is connected to the third region,
a third contact is connected to the first conductive layer on the second region,
a fifth contact is connected to the fifth region of the first semiconductor layer,
a sixth contact is connected to the first conductive layer on the fourth region, and
portions corresponding to the first region to the third region are configured to provide a first transistor, and portions corresponding to the third region to the fifth region are configured to provide a second transistor; and
a memory cell array including a plurality of memory blocks electrically connected to the first transistor and the second transistor, wherein
the plurality of transistor pairs includes a first transistor pair, a second transistor pair adjacent to the first transistor pair in the first direction, a third transistor pair adjacent to the first transistor pair in the second direction, and a fourth transistor pair adjacent to the second transistor pair in the second direction and adjacent to the third transistor pair in the first direction, and
the first transistor of the first transistor pair arranged on a side of the second transistor pair, the second transistor of the second transistor pair arranged on a side of the first transistor pair, the first transistor of the third transistor pair arranged on a side of the fourth transistor pair, and the second transistor of the fourth transistor pair arranged on a side of the third transistor pair are electrically connected to the same memory block of the memory cell array.