Patent ID: 11947810
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. The memory system of claim 13,
wherein the memory controller comprises a second CRC engine and a central processing unit (CPU) configured to control operation of the memory controller,
wherein the second CRC engine, during a write operation on the semiconductor memory device, is configured to generate the system parity data based on the main data and is configured to transmit the main data and the system parity data to the semiconductor memory device,
wherein the first CRC engine comprises a CRC generator and a CRC checker, and
wherein, during the write operation based on a write command from the memory controller, the CRC generator is configured to generate a first reference system parity data based on the main data, and the CRC checker is configured to transmit, to the memory controller, the first error flag having a first logic level indicating that the first type of error occurs based on comparing the system parity data with the first reference system parity data.