Patent ID: 11961572
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. The controller as set forth in claim 8, wherein the plurality of word lines and a plurality of dielectric layers extend horizontally and overlay one another in an alternating fashion in a stack, the strings extend vertically through the stack, the memory cells connected in series between at least one drain-side select gate transistor on a drain-side of each of the strings and connected to one of a plurality of bit lines and at least one source-side select gate transistor on a source-side of each of the strings and connected to a source line, the at least one edge word line being disposed vertically above the plurality of other data word lines and immediately adjacent the at least one drain-side select gate transistor, the threshold voltage possible for each of the memory cells spans a threshold window, each of the memory cells is configured to store a plurality of bits, the plurality of data states includes the erased state at a first end of the threshold window and a plurality of programmed data states each corresponding to the threshold voltage being higher than the threshold voltage associated with the erased state, the plurality of programmed data states including a highest data state at a second end of the threshold window opposite the first end and associated with the threshold voltage being higher than the threshold voltage associated with the erased state and at least one other of the plurality of programmed data states.