Patent ID: 11967357
Assignee: NATIONAL TSING HUA UNIVERSITY
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A memory unit with time domain edge delay accumulation for computing-in-memory applications, which is controlled by a first word line and a second word line, the memory unit with time domain edge delay accumulation for computing-in-memory applications comprising:
at least one memory cell storing a weight, wherein the at least one memory cell is controlled by the first word line and comprises a local bit line transmitting the weight;
at least one edge-delay cell multiplexor connected to the at least one memory cell and controlled by the second word line; and
at least one edge-delay cell connected to the at least one edge-delay cell multiplexor and comprising:
a weight reader configured to receive the weight and a multi-bit analog input voltage and generate a multi-bit voltage according to the weight and the multi-bit analog input voltage; and
a driver connected to the weight reader and configured to receive an edge-input signal, wherein the driver is configured to generate an edge-output signal having a delay time according to the edge-input signal and the multi-bit voltage;

wherein the delay time of the edge-output signal is positively correlated with the multi-bit analog input voltage multiplied by the weight.