Patent ID: 11923408
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A semiconductor structure, comprising:
one or more channel layers;
a gate structure engaging the one or more channel layers;
a first source/drain feature connected to a first side of the one or more channel layers and adjacent to the gate structure;
a second source/drain feature connected to a second side of the one or more channel layers and adjacent to the gate structure;
a first dielectric cap disposed over the first source/drain feature;
a contact plug disposed over and electrically connected to the second source/drain feature;
two gate spacers;
two contact etch stop layers, wherein each of the two contact etch stop layers is laterally between the first dielectric cap and each of the two gate spacers;
a first interconnect structure over the first dielectric cap and the contact plug, wherein the first interconnect structure is electrically connected to the contact plug and is isolated from the first source/drain feature by the first dielectric cap;
a first via disposed under and electrically connected to the first source/drain feature; and
a second interconnect structure disposed under and electrically connected to the first via.