Patent ID: 11882701
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor device comprising:
a substrate having a cell region and a connection region adjacent to the cell region;
a plurality of extension lines in the connection region and sequentially stacked on the substrate;
a plurality of gate electrodes in the cell region and sequentially stacked on the substrate;
a plurality of insulating layers between the plurality of extension lines and between the plurality of gate electrodes; and
a channel structure in a channel hole passing through the plurality of gate electrodes and the plurality of insulating layers, the channel hole including a lower channel hole and an upper channel hole communicatively connected to the lower channel hole underneath,
wherein each of the plurality of gate electrodes is connected to a corresponding one of the plurality of extension lines,
first distances between pairs of two neighboring ones of the plurality of extension lines are substantially equal to each other, and
the plurality of insulating layers include a first insulating layer between the plurality of gate electrodes adjacent to a boundary between the lower channel hole and the upper channel hole in the cell region, the first insulating layer having a thickness greater than each of the first distance, and wherein
the plurality of extension lines comprise a dummy extension line adjacent to the boundary,
the plurality of insulating layers comprise a dummy insulating layer under the dummy extension line, and
a top surface of the dummy extension line is substantially coplanar with the boundary.