Patent ID: 11916020
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 12:
13. A method of fabricating a microelectronic assembly, the method comprising:
providing a plurality of first dies coupled to a package substrate with first interconnects; and
providing a plurality of second dies coupled to one or more of the first dies with second interconnects, wherein individual ones of the second dies are also coupled to the package substrate with third interconnects;
wherein a communication network is at least partially included in the first dies and at least partially included in the second dies; and
wherein routing circuitry is included in a routing die, the routing die is at least one of the first dies or at least one of the second dies, the routing circuitry is coupled to the communication network, and the routing circuitry comprising logic to select at least one of the first dies or the second dies to route data from the routing die via one or more communication pathways of the communication network without routing the data through the package substrate.