Patent ID: 11955960
Assignee: CHIP-GAN POWER SEMICONDUCTOR CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. A depletion mode GaN product, comprising:
one or more depletion mode GaN transistors formed on a depletion mode GaN wafer; and
one or more control circuits formed on a silicon wafer;
wherein the control circuits and the depletion mode GaN transistors are paired one-to-one with each other;
wherein each control circuit detects leakage current of a paired depletion mode GaN transistor and then adjusts gate voltage of the paired depletion mode GaN transistor accordingly;
wherein each control circuit comprises a current detecting module configured to detect the leakage current of a paired depletion mode GaN transistor and a gate voltage adjusting module configured to adjust the gate voltage of the paired depletion mode GaN transistor according to the detected leakage current;
wherein the gate voltage adjusting module comprises both a voltage source configured to provide a fixed voltage to the gate of the paired depletion mode GaN transistor and a negative voltage converter configured to provide a negative voltage according to the detected current to the gate of the paired depletion mode GaN transistor, wherein the gate voltage of the paired depletion mode GaN transistor is modified by the combination of the fixed voltage of the negative voltage.