Patent ID: 11962509
Assignee: DELL PRODUCTS L.P.
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. An information handling system, comprising:
a transmitter; and
a receiver coupled to the transmitter by a high-speed data communication interface having a number (N) of lanes;
wherein the transmitter includes a clock circuit for clocking the high-speed data communication interface, the clock circuit including:
a triangle wave generator that provides a number (P) of phase outputs, wherein P is greater than or equal to N;
a number (N) of clock generators, wherein each clock generator receives an associated one of the phase outputs and generates a clock signal having a frequency based upon the phase output; and
a number (N) of lane first-in/first-out buffers (FIFOs), wherein each receives data and an associated one of the clock signals, and provides the data at a clock frequency associated with the associated clock signal; and

wherein the receiver asynchronously decodes the data from the high-speed data communication interface; and
wherein N is equal to eight (8), and the order provides a 0th clock signal to the FIFO associated with a 1st lane, a 1st clock signal to the FIFO associated with a 5th lane, a 2nd clock signal to the FIFO associated with a 0th lane, a 3rd clock signal to the FIFO associated with a 4th lane, a 4th clock signal to the FIFO associated with a 6th lane, a 5th clock signal to the FIFO associated with a 2nd lane, a 6th clock signal to the FIFO associated with a 7th lane, and a 7th clock signal to the FIFO associated with a 3rd lane.