Patent ID: 11967391
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. A test system, comprising:
a storage device including a plurality of flash translation layer (FTL) cores, each FTL core associated with multiple memory blocks; and
a test device configured to generate test preconditions for the plurality of FTL cores and provide the test preconditions to the plurality of FTL cores, the test preconditions including differing conditions, wherein each of the plurality of FTL cores performs one or more test operations based on a corresponding test precondition of the test preconditions, wherein:
each of the test preconditions indicates a state of the multiple memory blocks, and
the test preconditions include an erase counter value and a read counter value for each of the multiple memory blocks.