Patent ID: 11935882
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 14:
15. A memory device, comprising:
a first plurality of bit cells continuously arranged in a column direction; and
a second plurality of bit cells continuously arranged in the column direction and aligned to the first plurality of bit cells in the column direction, wherein:
the first plurality of bit cells and the second plurality of bit cells are spaced apart from each other by an abutting dummy cell which includes one or more dummy gate electrode layers and one or more dummy contacts,
the dummy gate electrode layers and dummy contacts have lengths extending along a row direction,
the dummy gate electrode layers are spaced apart from each other and arranged along a plurality of dummy gate electrode lines extending along the row direction,
the dummy contacts are arranged along a plurality of dummy contact lines extending along the row direction,
at least one of the dummy contacts extends, in the row direction, continuously across the dummy cell,
the dummy gate electrode lines and dummy contact lines are alternately arranged along the column direction perpendicular to the row direction, and
the abutting dummy cell has a width along the column direction equal to or less than six times a pitch of the dummy gate electrode layers along the column direction.