Patent ID: 11870461
Assignee: MICRON TECHNOLOGY, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A method comprising:
receiving a plurality of codewords of an error correcting code for a memory sub-system;
dividing each of the plurality of codewords of the error correcting code into a plurality of segments, wherein the plurality of segments are distributed across a plurality of dies of the memory sub-system;
calculating an exclusive-OR (XOR) value based on a combination of the plurality of codewords;
applying respective shifts to the plurality of segments of each of the plurality of codewords to arrange the plurality of segments into a first layout spread across the plurality of dies in the memory sub-system, wherein a number of codewords in the plurality of codewords is equal to a number of dies in the plurality of dies, and wherein a codeword segment along a column or row of the first layout is unique; and
forming an error correcting (EC) layout across the plurality of dies, wherein the first layout constitutes at least a portion of the EC layout, wherein the EC layout stores the plurality of segments of the plurality of codewords and the calculated XOR value.