Patent ID: 11879939
Assignee: NXP B.V.
Field: Measurement (Instruments)
Classification: CPC G  H | IPC G  H

Claim 16:
17. The IC of claim 16, wherein the clocking system further comprises:
an on-chip clock controller (OCC) configured to generate a third clock enable signal based on the first clock signal, wherein during the capture phase, the third clock enable signal facilitates the generation of the second clock signal comprising the first clock pulse and the second clock pulse;
a second logic circuit that is coupled to the pipeline circuit and the OCC, and configured to generate a fourth clock enable signal based on the first clock enable signal, the third clock enable signal, and a scan enable signal, wherein the fourth clock enable signal is asserted based on at least one of a group consisting of (i) an assertion of the scan enable signal and (ii) the assertion of the first clock enable signal and an assertion of the third clock enable signal, and wherein the fourth clock enable signal is de-asserted based on a de-assertion of the scan enable signal and at least one of a group consisting of (i) the de-assertion of the first clock enable signal and (ii) a de-assertion of the third clock enable signal; and
a sixth clock gate that is coupled to the second logic circuit, and configured to generate the second clock signal based on the first clock signal and the fourth clock enable signal, wherein the second clock signal is de-asserted based on the de-assertion of the fourth clock enable signal, and the second clock signal is same as the first clock signal based on the assertion of the fourth clock enable signal.