Patent ID: 11908692
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. A method, comprising:
performing a first exposure process using a first mask to transfer a first alignment pattern and a first layout pattern onto a photoresist layer;
performing a first development process to form a first alignment opening and a first wiring opening in the photoresist layer;
performing a second exposure process using a second mask to transfer a second alignment pattern and a second layout pattern onto the photoresist layer, wherein the second layout pattern transferred onto the photoresist layer is substantially aligned with and overlaps an overlay region of the first wiring opening, and the second alignment pattern of the second mask is substantially aligned with the first alignment opening formed in the photoresist layer when performing the second exposure process;
performing a second development process to form a second alignment opening and a second wiring opening in the photoresist layer, wherein the first wiring opening and the second wiring opening are communicated at the overlay region;
forming alignment marks in the first alignment opening and the second alignment opening; and
forming a conductive wiring in the first wiring opening and the second wiring opening.