Patent ID: 11940927
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. A method comprising:
receiving, by a processor core of a processor, a read or write memory operation comprising a virtual memory address, wherein the virtual memory address comprises a plurality of memory tag bits;
accessing, by a memory management unit (MMU) of the processor, a page table entry based on the virtual memory address, wherein the page table entry comprises a plurality of page tag bits;
determining, by the MMU, whether to abort the read or write memory operation based on a comparison between the plurality of page tag bits to the plurality of memory tag bits;
selecting, by the MMU, one or more of the plurality of memory tag bits based on the plurality of page tag bits;
determining whether memory tag bits of the plurality of memory tag bits other than the selected one or more memory tag bits are correct values; and
sending, by the MMU the read or write memory operation to a memory connected to the processor with the one or more selected bits of the plurality of memory tag bits.