Patent ID: 11860227
Assignee: SYNOPSYS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. A system for delay estimation, the system comprising:
a memory; and
a processor, operatively coupled with the memory, to:
receive a plurality of logic blocks of a DUT;
identify a combinatorial path based on the DUT, the combinatorial path connecting one or more logic blocks of the plurality of logic blocks;
generate a feature vector including values of one or more orthogonal features representing characteristics of the combinatorial path;
apply a pre-trained machine learning delay model to the feature vector to determine a wire delay of the combinatorial path, the pre-trained machine learning delay model trained using (1) values of one or more orthogonal features representing the characteristics of a plurality of combinatorial paths, and (2) measured wire delay of the plurality of combinatorial paths;
generate a timing graph based on a delay of the combinatorial path; and
provide the timing graph to a compiler to perform placement and routing of the DUT.