Patent ID: 11862595
Assignee: SJ SEMICONDUCTOR(JIANGYIN) CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. The packaging method for the fan-out wafer-level packaging structure as in claim 1, wherein a method for forming vias in the first redistribution sublayer comprises:
dividing the dielectric layer on the semiconductor chips into a plurality of to-be-etched dielectric layer units; and
etching the plurality of to-be-etched dielectric layer units one by one in a predetermined order by photolithography to form vias in each of the plurality of to-be-etched dielectric layer units;
wherein the pads of each of the semiconductor chip are exposed from bottoms of the vias; and where a number of the plurality of to-be-etched dielectric layer units is equal to or larger than 2.