Patent ID: 11887840
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A method for manufacturing a semiconductor device, the method comprising:
providing a substrate;
forming a conductive layer on the substrate;
forming an insulating layer on the conductive layer;
forming a photoresist layer on the insulating layer;
exposing the photoresist layer to light using a mask including a pattern group and developing the exposed photoresist layer to form a photoresist hole pattern;
etching the insulating layer using the photoresist hole pattern as an etching mask to form a via hole defined in the insulating layer, the via hole exposing at least a portion of the conductive layer; and
forming a redistribution conductive layer that includes a first pad area disposed in the via hole and a line area that at least partially extends along a sidewall of the via hole,
wherein the pattern group includes:
a main pattern having a same planar shape as a planar shape of the via hole; and
a plurality of parasitic patterns arranged sequentially and outwardly to surround the main pattern, wherein each of the plurality of parasitic patterns has a closed ring shape in a plan view.