Patent ID: 11869563
Assignee: GLOBALFOUNDRIES DRESDEN MODULE ONE LIMITED LIABILITY COMPANY & KG
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. The memory structure of claim 3, further comprising an additional voltage driver configured to receive the data verification signal and to apply an additional specific voltage to the source-line depending upon the data verification signal,
wherein the voltage driver is configured to output an initial programming assist voltage to the bit-line during an initial programming process following an initial verification process when the data verification signal has the second value and to output decremental programming assist voltages to the bit-line during repeat programming processes following subsequent verification process when the data verification signal has the second value, and
wherein the additional voltage driver is configured to output an additional initial programming assist voltage to the source-line during the initial programming process following the initial verification process when the data verification signal has the second value and to output additional decremental programming assist voltages to the source-line during the repeat programming processes following subsequent verification process when the data verification signal has the second value.