Patent ID: 11894074
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. The device of claim 1, further comprising:
a plurality of bit lines coupled to the memory cell transistors, respectively;
a first sense circuit coupled to a first bit line included among the bit lines, the first sense circuit including a first sense node, and the first sense circuit configured to determine a threshold voltage of a first memory cell transistor coupled to the first bit line, based on a voltage of the first sense node; and
a second sense circuit coupled to a second bit line included among the bit lines, the second sense circuit including a second sense node, the second sense circuit configured to determine a threshold voltage of a second memory cell transistor coupled to the second bit line, based on a voltage of the second sense node,
wherein
in the write operation, where the controller is configured to write the first data and the second data to the first memory cell transistor and the second memory cell transistor, respectively, a discharge time of the first sense node used for determining whether a threshold voltage of the first memory cell transistor exceeds the verify high voltage of the first data and a discharge time of the second node used for determining whether not a threshold voltage of the second memory cell transistor exceeds the verify low voltage of the second data are different from each other.