Patent ID: 11861337
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. A compiler system for compiling neural network code to a plurality of executable instructions or other executable code for execution by a computational acceleration system having a first memory circuit and one or more acceleration circuits having a maps data buffer and a kernel data buffer, each acceleration circuit of the one or more acceleration circuits comprising a plurality of multiply and accumulate (“MAC”) circuits, the compiler system comprising:
a second memory circuit configured to store the neural network code; and
one or more processors coupled to the second memory circuit, the one or more processors configured to: generate a list of neural network layer model objects from the neural network code; fuse available functions and layers in the list of neural network layer model objects; select a cooperative mode, an independent mode, or a combined cooperative and independent mode for code execution by the one or more acceleration circuits; determine first memory circuit usage when kernel data is maintained in the kernel data buffer for a predetermined number of computations with reordering of maps data movement and computations to utilize the selected kernel data which is currently loaded in the kernel data buffer; determine first memory circuit usage when maps data is maintained in the maps data buffer for the predetermined number of computations with reordering of kernel data movement and computations to utilize the selected maps data which is currently loaded in the maps data buffer; determine first memory circuit usage when maps data movement is reordered, kernel data movement is reordered, and computations are reordered to utilize one or more rows of the selected maps data or kernel data which is currently loaded respectively in the maps data buffer or in the kernel data buffer; reorder at least one computation to utilize one or more rows of selected maps data or kernel data which is currently loaded respectively in the maps data buffer or in the kernel data buffer; select a data movement mode and an ordering of computations which minimizes usage of the first memory circuit; generate an ordered sequence of load objects, compute objects, and store objects; order the sequence of load objects, compute objects, and store objects to reduce any computational latency and to provide data pre-fetching; and convert the ordered sequence of load objects, compute objects, and store objects into the plurality of executable instructions or other executable code.