Patent ID: 11862633
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 14:
15. An integrated chip, comprising:
a first channel structure extending between a first source/drain region and a second source/drain region;
a first gate electrode layer wrapping around the first channel structure in a first closed loop;
a second channel structure extending between a third source/drain region and a fourth source/drain region;
a second gate electrode layer wrapping around the second channel structure in a second closed loop, wherein the second gate electrode layer continuously extends from around the second channel structure to cover the first gate electrode layer;
a third channel structure extending between a fifth source/drain region and a sixth source/drain region; and
a third gate electrode layer wrapping around the third channel structure in a third closed loop, wherein the third gate electrode layer continuously extends from around the third channel structure to cover the second gate electrode layer.