Patent ID: 11907044
Assignee: INFINEON TECHNOLOGIES AG
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. A method for operating a memory device comprising a plurality of memory cells and a plurality of evaluation elements, wherein each evaluation element of the plurality of evaluation elements is connectable with a memory cell of the memory device and is configured to evaluate a physical parameter, of the memory cell, comprising at least one of a voltage at the memory cell, a potential at the memory cell, a current through the memory cell or an electrical resistance of the memory cell, the method comprising:
connecting the plurality of memory cells to a first assignment of evaluation elements in a first state;
connecting the plurality of memory cells to a second assignment of the evaluation elements in a second state, wherein, in the second state, at least one memory cell of the plurality of memory cells is connected to a different evaluation element to which the at least one memory cell is not connected in the first state; and
reading error information, indicating that a reading operation using a pair of a memory cell of the plurality of memory cells and an evaluation element in the first state, in which the at least one memory cell is not connected to the different evaluation element, is error-prone, from a memory to obtain, using the evaluation elements connected to the plurality of memory cells in accordance with the second assignment, an evaluation result of the plurality of memory cells based on a reading operation performed using the second state, in which the at least one memory cell is connected to the different evaluation element, based on the error information.