Patent ID: 11868654
Assignee: RENESAS ELECTRONICS CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 4:
5. A semiconductor device comprising:
a nonvolatile memory cell including a plurality of first memory cells and a plurality of second memory cells;
a first bit latch; and
a second bit latch, wherein
in a first writing operation, first writing data are stored in the first bit latch, and writing to the plurality of first memory cells is executed on a basis of the first writing data stored in the first bit latch,
during the first writing operation, in response to the first writing operation being interrupted on a basis of a suspension command, a second writing operation is executed,
in the second writing operation, second writing data are stored in the second bit latch, and writing to the plurality of second memory cells is executed on a basis of the second writing data, wherein the second writing data are stored in the second bit latch in response to receiving a second writing operation command while the first writing operation is interrupted, and
after the second writing operation is ended, the interrupted first writing operation is restarted on a basis of a resume command and latched data of the first bit latch.