Patent ID: 11928443
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An integrated circuit comprising:
a memory block;
a first processing circuit operating a first transpose engine that writes elements in a first column or row of a matrix to a first region of storage in the memory block; and
a second processing circuit operating a second transpose engine that writes elements in a second column or row of the matrix to a second region of storage in the memory block, wherein the first and the second transpose engines write the first and the second columns or rows of the matrix to the first and the second regions of storage in parallel, and
wherein the first and the second transpose engines transpose the matrix to generate a transposed matrix by reading first and second columns or rows of the transposed matrix from third and fourth regions of storage, respectively, in the memory block in parallel.