Patent ID: 11935602
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G  H

Claim 10:
11. The memory device of claim 7, wherein the controller is further configured to cause the memory device to:
in response to the third sum being greater than the first current demand budget or the fourth sum being greater than the second current demand budget:
generate a fifth sum of the respective expected peak current magnitudes of each register of the plurality of registers other than the respective register of the memory device, and an expected peak current magnitude for the next phase of the access operation in a third operating mode;
generate a sixth sum of the respective expected peak current magnitudes of each register of the particular subset of registers other than the respective register of the memory device, and an expected peak current magnitude for the next phase of the access operation in the third operating mode;
compare the fifth sum to the first current demand budget for the plurality of the memory devices;
compare the sixth sum to the second current demand budget for the particular subset of the memory devices; and
in response to the fifth sum being less than or equal to the first current demand budget and the sixth sum being less than or equal to the second current demand budget, initiate the next phase of the access operation in the third operating mode.