Patent ID: 11876013
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A semiconductor device comprising:
an isolation feature disposed over a semiconductor substrate;
a first dielectric layer disposed over the isolation feature;
a first gate and a second gate disposed in the first dielectric layer, wherein the first gate and the second gate are disposed over the isolation feature;
a second dielectric layer disposed over the first dielectric layer, the first gate, and the second gate, wherein the second dielectric layer is between the first gate and the second gate along a first direction and the second dielectric layer extends through the first gate and the second gate to the isolation feature;
a third dielectric layer and a fourth dielectric layer, wherein the second dielectric layer is between the third dielectric layer and the fourth dielectric layer along a second direction that is different than the first direction; and
a fifth dielectric layer and a sixth dielectric layer, wherein the first dielectric layer is between the fifth dielectric layer and the third dielectric layer and the first dielectric layer is between the sixth dielectric layer and the fourth dielectric layer.