Patent ID: 11935614
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. A memory system, comprising:
row logic circuitry;
a bank of a memory array, the bank coupled with the row logic circuitry;
a first set of power supply nodes configured to have a first voltage differential;
a second set of power supply nodes configured to have a second voltage differential and coupled with the row logic circuitry, wherein the second voltage differential is smaller than the first voltage differential; and
processing circuitry coupled with the row logic circuitry and the bank, wherein the processing circuitry is configured to:
activate, in response to receiving an activate command, the row logic circuitry and the bank, wherein activating the row logic circuitry is based at least in part on coupling one or more of the first set of power supply nodes with one or more of the second set of power supply nodes; and
perform, after activating the bank and the row logic circuitry, an access operation on the bank.