Patent ID: 11921577
Assignee: LAPIS SEMICONDUCTOR CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A semiconductor memory element, comprising:
a memory part storing data;
an input/output circuit through the data is read from or written to the memory part;
an error detection and correction part coupled to the input/output circuit and detecting an error in the data stored in the memory part and correcting the error if possible;
a first terminal that is a pad of the semiconductor memory element, coupled to the error detection and correction part and through which the data is written to or read from the memory part;
an uncorrectable error detection part coupled to the error detection and correction part and issuing an uncorrectable error signal when an uncorrectable error occurs in the error detection and correction part; and
a second terminal coupled to the uncorrectable error detection part and transmitting the uncorrectable error signal to an MCU (micro central unit) or a higher-level control part when an uncorrectable error is detected, so that the uncorrectable error is determined at a same time as an occurrence of an abnormality in the semiconductor memory element,
wherein the second terminal is different from the first terminal and is a non-specified pad of the semiconductor memory element.