Patent ID: 11914490
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. A system comprising:
one or more memory devices having multiple blocks of memory cells; and
a memory controller including processing circuitry including one or more processors, the memory controller configured to perform operations to:
track multiple metrics associated with memory operations on a block of the multiple blocks, each metric of the multiple metrics being a measurable event of a specified memory operation;
generate a Z-score for each of the multiple metrics;
compare the Z-scores of the multiple metrics to Z-score thresholds for the multiple metrics, providing multiple comparisons; and
control retirement of the block of memory based on at least one of the multiple comparisons and a comparison of a parameter to a parameter threshold, the parameter associated with the metric of the at least one of the multiple comparisons.