Patent ID: 11948829
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A circuit device, comprising:
a substrate that includes a first well region having a first dopant type and a second well region having a second dopant type different from the first dopant type, wherein the second well interfaces with the first well region at an interface;
a first fin, a second fin, and a third fin extending from the substrate, the first fin and the third fin being over the first well region and the second fin being over the second well region, wherein the third fin is disposed between the first fin and the second fin; and
an integral isolation feature comprising an upper portion over the substrate and extending from a bottom portion of the first fin to a bottom portion of the second fin and a lower portion extending into both the first well region and the second well region in the substrate, wherein the lower portion of the integral isolation feature spans directly over the interface, and
wherein, in a cross-sectional view cut through the first fin, the isolation feature, and the second fin, a shape of the integral isolation feature is asymmetrical, and
wherein, in a top view, the third fin is in direct contact with the integral isolation feature.