Patent ID: 11917806
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of manufacturing a semiconductor structure, comprising:
providing a substrate;
forming multiple active pillars on the substrate, wherein the multiple active pillars are arranged in an array, and an outer surface layer of each of the active pillars has a concave-convex surface;
forming a gate oxide layer on the substrate, wherein the gate oxide layer covers a top surface of the substrate and sidewalls and a top surface of each of the active pillars, and a filling region is formed between two adjacent active pillars in the same row;
sequentially forming a word line and a first dielectric layer in the filling region;
removing a part of the first dielectric layer and a part of the gate oxide layer, to expose the top surface of each of the active pillars;
forming a contact layer on the top surface of each of the active pillars; and
forming a capacitor structure on the contact layer.