Patent ID: 11961917
Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. A semiconductor device comprising:
a first transistor; and
a second transistor over the first transistor,
wherein a channel of the first transistor comprises silicon,
wherein a first semiconductor layer in which a channel of the second transistor is formed comprises indium, gallium, and zinc,
wherein part of a bottom surface of a first conductive layer functioning as one of a source and a drain of the second transistor is positioned below the first semiconductor layer,
wherein part of a bottom surface of a second conductive layer functioning as the other of the source and the drain of the second transistor is positioned below the first semiconductor layer,
wherein the first conductive layer and the second conductive layer are in contact with a top surface of the first semiconductor layer,
wherein a first insulating layer is provided over the first semiconductor layer,
wherein a third conductive layer functioning as a gate of the second transistor is provided over the first insulating layer,
wherein a second insulating layer is provided over the third conductive layer,
wherein a third insulating layer is provided over the second insulating layer, the first conductive layer and the second conductive layer,
wherein a fourth conductive layer functioning as a gate of the first transistor is provided over the channel of the first transistor,
wherein a fourth insulating layer, a fifth insulating layer, and a sixth insulating layer are provided over the channel of the first transistor,
wherein the second conductive layer is electrically connected to the channel of the first transistor via a first opening in the fourth insulating layer, a second opening in the fifth insulating layer, and a third opening in the sixth insulating layer,
wherein a bottom surface of the third conductive layer is provided below the top surface of the first semiconductor layer,
wherein the first semiconductor layer is in contact with a top surface of the sixth insulating layer,
wherein the sixth insulating layer overlaps with the fourth conductive layer, and
wherein the first conductive layer is not in contact with a bottom surface of the first semiconductor layer.