Patent ID: 11967286
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 1:
2. The display substrate according to claim 1, further comprising an output reset circuit,
wherein the output reset circuit is configured to reset the output terminal under control of the level of the first node;
the output reset circuit comprises a first capacitor and an output reset transistor;
a first electrode of the first capacitor is connected to and integrally formed with the first portion of the first connection wire, and an orthographic projection of the first electrode of the first capacitor on the base substrate is on an imaginary line, in the first direction, of the orthographic projection of the active layer of the first control transistor on the base substrate; and
an orthographic projection of an active layer of the output reset transistor on the base substrate is on a side of an orthographic projection of the first capacitor on the base substrate close to the display region.