Patent ID: 11968039
Assignee: HUAWEI TECHNOLOGIES CO., LTD.
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A processor for executing Forward Error Correction (FEC) coding, the processor being configured to:
acquire a stream of real data symbols from a communication medium,
the stream of real data symbols being arranged in a real matrix such that a given real data symbol is associated with a respective real row position and a respective real column position in the real matrix;

generate virtual data symbols being arranged in a virtual matrix such that a given virtual data symbol is associated with a respective virtual row position and a respective virtual column position in the virtual matrix,
the generating including applying an interleaver map onto the real matrix such that (i) at most c number of virtual data symbols in a given virtual row of the virtual matrix are copies of (ii) real data symbols associated with a same real row of the real matrix, c being a positive integer higher than 1; and

decode codewords formed by the virtual matrix and the real matrix, a given codeword represented by a given row of virtual data symbols in the virtual matrix and a corresponding row of real data symbols in the real matrix.