Patent ID: 11923362
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 18:
19. An integrated circuit device comprising:
a fin-type active area extending on a substrate in a first horizontal direction;
a source/drain region disposed on the fin-type active area;
a nanosheet stack structure disposed on the fin-type active area, the nanosheet stack structure comprising a first nanosheet and a second nanosheet, wherein the first nanosheet is closer to the fin-type active area than the second nanosheet;
a gate line covering the nanosheet stack structure on the fin-type active area, and extending in a second horizontal direction intersecting the first horizontal direction;
a gate dielectric layer disposed between the nanosheet stack structure and the gate line; and
a bottom insulation structure interposed between the fin-type active area and the first nanosheet, and integrally connected to the gate dielectric layer,
wherein a first level of a lower surface of the source/drain region being higher than a second level of an upper surface of the fin-type active area, and
wherein no portion of the gate line is disposed between the fin-type active area and the first nanosheet.