Patent ID: 11868619
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 15:
16. A method of operating a memory system, comprising:
configuring a memory component in a first array refresh mode;
while the memory component is in the first array refresh mode, transmitting, to the memory component, a first refresh command;
based at least in part on the memory component being in the first array refresh mode, waiting a first minimum time interval before allowing a first memory access command to be transmitted to the memory component;
configuring the memory component in a second array refresh mode;
while the memory component is in the second array refresh mode, transmitting, to the memory component, a second refresh command; and,
based at least in part on the memory component being in the second array refresh mode, waiting a second minimum time interval before allowing a second memory access command to be transmitted to the memory component, the first minimum time interval and the second minimum time interval being unequal.