Patent ID: 11893078
Assignee: CEREMORPHIC, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A process for forming dot products of a 1×m A matrix with an m×m B matrix, the process operative on an m column and m row array of processing elements (PE), the A matrix having ‘a’ elements and the B matrix having ‘b’ elements, each ‘a’ element and each ‘b’ element comprising a sign bit and n value bits, each processing element comprising a sign voltage source and a plurality n of multipliers, each multiplier operative on a unique value bit an of a value of the A matrix and a value bit of the B matrix, the process comprising:
charging a multiplier capacitor in each multiplier to a sign voltage provided by the sign voltage source during a first clock phase PH1 if a corresponding bit an is 1;
sharing capacitor charge across all multiplier capacitors during a second clock phase PH2;
clearing a charge from the multiplier capacitor if a value bit bn of the B matrix is 0 during a third clock phase PH3;
connecting all processing element multiplier capacitors of each column together and converting the charge of each column to a digital output value during a fourth clock phase PH4.