Patent ID: 11962309
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G  Y | IPC H

Claim 9:
10. The phase adjusting circuit of claim 9, wherein the adjustment circuit further comprises a third adjustment circuit and a fourth adjustment circuit; wherein,
the third adjustment circuit is configured to receive the preset fixed value and a third original clock signal, and perform transmission of the third original clock signal based on the preset fixed value to obtain a third clock signal; wherein a phase difference between the third original clock signal and the first original clock signal is 180 degrees; and
the fourth adjustment circuit is configured to receive the count value and a fourth original clock signal, and perform transmission of the fourth original clock signal based on the count value to obtain a fourth clock signal; wherein a phase difference between the fourth original clock signal and the second original clock signal is 180 degrees;
wherein, in a case that the count value is greater than the preset fixed value, a rising edge of the fourth clock signal moves in the first direction relative to a rising edge of the third clock signal; or in a case that the count value is less than the preset fixed value, a rising edge of the fourth clock signal moves in the second direction relative to a rising edge of the third clock signal.