Patent ID: 11942148
Assignee: THE REGENTS OF THE UNIVERSITY OF MICHIGAN
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 18:
19. A computing system, comprising:
an array of memory cells arranged in columns and rows, such that memory cells in each row of the array is interconnected by a respective drive line and each column of the array is interconnected by a respective bit line;
each memory cell in a given group of memory cells is configured to receive an input signal indicative of a multiplier and operates to output a product of the multiplier and the value of the bit stored in the given memory cell onto the corresponding bit line of a given memory cell, where the value of the multiplier is encoded in the input signal; and
a plurality of drive circuits interfaced with the array of memory cells, each drive circuit is electrically connected to respective drive line in the array of memory cells;
a global level shifter circuit shared by the plurality of drive circuits;
each drive circuit includes
a digital-to-analog converter operating at a low voltage level and configured to perform a read operation of memory cells connected to the respective drive line;
a writing subcircuit is configured to receive and operates to deliver a write signal to the respective drive line during a write operation and is disabled during the read operation, where voltage of the write signal is higher than the low voltage level; and
a write enabled switch is interposed between the digital-to-analog converter and the writing subcircuit and operates to electrically isolate the digital-to-analog converter from the writing subcircuit during the write operation and is turned on during the read operation.