Patent ID: 11973041
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 40:
41. A multi-die electronic package, comprising:
a first die in a first mold layer, the first die comprising interconnections;
a first plurality of vias in the first mold layer, the first plurality of vias laterally adjacent to a first side of the first die, each of the first plurality of vias extending from a first surface of the first mold layer to a second surface of the first mold layer;
a second plurality of vias in the first mold layer, the second plurality of vias laterally adjacent to a second side of the first die, each of the second plurality of vias extending from the first surface of the first mold layer to the second surface of the first mold layer;
a second die electrically coupled to the first die, and the second die electrically coupled to the first plurality of vias;
a third die electrically coupled to the first die, the third die electrically coupled to the second die by the interconnections of the first die, wherein the first mold layer is not vertically between the first die and the second die, and the first mold layer is not vertically between the first die and the third die;
a second mold layer between and in contact with the second die and the third die, the second mold layer having a surface co-planar with a surface of the second die, the second mold layer between the second die and the first die, the second mold layer between the third die and the first die, and the second mold layer in contact with the interconnections of the first die; and
a fourth die between the second die and the third die, the fourth die coupled to the first die.