Patent ID: 11973082
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 4:
5. The integrated circuit device of claim 1, further comprising:
a third region comprising the SOI substrate layer;
a plurality of third fin-type active areas defined by a third plurality of trenches in the third region, the third fin-type active areas protruding from the main surface of the SOI substrate layer and extending in the first horizontal direction;
nanosheet stacked structures above the plurality of third fin-type active areas, each comprising a plurality of nanosheets; and
a plurality of third source/drain regions between adjacent nanosheet stacked structures above the plurality of third fin-type active areas, the third source/drain regions extending into the SOI substrate layer to contact the insulating substrate layer, the plurality of third source/drain regions comprising lower surfaces thereof at a third vertical level above the main surface of the SOI substrate layer and the main surface of the semiconductor substrate layer that is different from the first vertical level.