Patent ID: 11894056
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 18:
19. A method, comprising:
fabricating a memory die, comprising:
creating a three dimensional non-volatile memory structure that includes word lines connected to non-volatile memory cells, the non-volatile memory cells are arranged in blocks,
adding one or more bottom metal layers positioned below the three dimensional non-volatile memory structure and connected to the word lines, and
adding a first interface connected to the one or more bottom metal layers;

fabricating a control die, comprising:
adding a second interface in electrical communication with the first interface,
adding one or more control metal layers below the second interface, and
adding a plurality of electrical circuits to a substrate below the one or more control metal layers including adding word line switch transistors arranged in groups of four word line switch transistors such that each group of four word line switch transistors is positioned in a line under three blocks of non-volatile memory cells and has a length that is equal to the width of the three blocks of non-volatile memory cells, the word line switch transistors are connected to the second interface via the one or more control metal layers;

bonding the control die to the memory die; and
communicating electrical signals from the word line switch transistors to the word lines via the one or more control metal layers, the second interface, the first interface and the one or more bottom metal layers.