Patent ID: 11917052
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Digital communication (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 9:
10. The hash algorithm method according to claim 9, wherein
the second hash circuit unit comprises a third exclusive OR circuit, a second summation circuit, a second right shift circuit, a second left shift circuit, a fourth exclusive OR circuit, and a fifth exclusive OR circuit, wherein the third exclusive OR circuit is electrically coupled to the first right shift circuit and the first exclusive OR circuit respectively, the second summation circuit is electrically coupled to the second exclusive OR circuit and the first left shift circuit respectively, the second right shift circuit is electrically coupled to the second summation circuit, the second left shift circuit is electrically coupled to the first summation circuit, the fourth exclusive OR circuit is electrically coupled to the third exclusive OR circuit and the second left shift circuit respectively, and the fifth exclusive OR circuit is electrically coupled to the fourth exclusive OR circuit and the second right shift circuit respectively; and
the hash algorithm method also comprises:
using the third exclusive OR circuit to perform an exclusive OR operation on the first intermediate sequence and the second intermediate sequence, so as to form a first temporary sequence;
using the second summation circuit to perform a summation operation on the third intermediate sequence and the fourth intermediate sequence, so as to form a second temporary sequence;
using the second right shift circuit to shift the second temporary sequence to the right by a first predetermined number of bits, so as to form a third temporary sequence;
using the second left shift circuit to shift the fifth intermediate sequence to the left by a second predetermined number of bits, so as to form a fourth temporary sequence;
using the fourth exclusive OR circuit to perform an exclusive OR operation on the first temporary sequence and the fourth temporary sequence, so as to form a fifth temporary sequence; and
using the fifth exclusive OR circuit to perform an exclusive OR operation on the third temporary sequence and the fifth temporary sequence, so as to form the target data.