Patent ID: 11874788
Assignee: CADENCE DESIGN SYSTEMS, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A transmitter circuit comprising:
a most significant bit (“MSB”) main driver;
a most significant bit boost driver operatively connected to the MSB main driver;
a least significant bit (“LSB”) main driver; and
a least significant bit boost driver operatively connected to the LSB main driver, wherein the MSB main driver and the LSB main driver are configured to receive two parallel non-return-to-zero (“NRZ”) data inputs, wherein the MSB boost driver applies a boost based upon, at least in part, a pulse amplitude modulation 4-level (“PAM 4”) transition level and wherein a magnitude of the boost differs between each of the 4 PAM4 transition levels.