Patent ID: 11962338
Assignee: QORVO US, INC.
Field: Telecommunications (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A transceiver circuit comprising:
a memory circuit; and
a calibration circuit coupled to a power amplifier circuit and configured to:
determine and store a plurality of gain offset entries in a gain offset lookup table (LUT) in the memory circuit to correlate a plurality of calibrated frequencies comprising a center frequency and multiple non-center frequencies within a modulation bandwidth of the power amplifier circuit with a plurality of gain offsets, respectively, wherein each of the plurality of gain offsets is determined relative to a reference frequency within the modulation bandwidth; and
determine and store a plurality of delay offset entries in a delay offset LUT in the memory circuit to correlate the plurality of calibrated frequencies with a plurality of delay factors, respectively.