Patent ID: 11899586
Assignee: SYNOPSYS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A method, comprising:
receiving a memory address at an m-way set-associative cache, wherein the memory address is partitioned into a tag, an index, and an offset, wherein the m-way set-associative cache stores a set of cache entries, and wherein the m-way set-associative cache includes a first structure to store a first subset of tag bits corresponding to the set of cache entries and a second structure to store a second subset of tag bits corresponding to the set of cache entries;
using the index to select m entries in the first structure;
matching a first portion of tag bits of the memory address with the m entries in the first structure; and
in response to the first portion of tag bits of the memory address matching n entries in the first structure, where n is less than m, matching a second portion of tag bits of the memory address with n entries in the second structure corresponding to the n entries in the first structure; and
wherein the matching the first portion of tag bits of the memory address with the m entries in the first structure and the matching the second portion of tag bits of the memory address with n entries in the second structure is performed in a single clock cycle.