Patent ID: 11936917
Assignee: BYTEDANCE INC.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. An apparatus for processing video data comprising a processor and a non-transitory memory with instructions thereon, wherein the instructions upon execution by the processor, cause the processor to:
perform a conversion between a video and a bitstream of the video according to a rule,
wherein the rule specifies that a sub-bitstream extraction process is implemented to generate a sub-bitstream for decoding,
wherein the sub-bitstream extraction process is configured to extract, from the bitstream, the sub-bitstream with a target highest temporal identifier,
wherein the rule specifies that, during the sub-bitstream extraction process, upon removing a video coding layer (VCL) network abstraction layer (NAL) unit, filler data units and filler supplemental enhancement information (SEI) messages in SEI NAL units that are associated with the VCL NAL unit are also removed, and
wherein the bitstream conforms to a format rule that specifies that a SEI NAL unit that comprises a SEI message with a filler payload does not include SEI messages with a payload different from the filler payload.