Patent ID: 11868650
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. The method of claim 16, wherein:
the first memory chip is configured to store a first data set corresponding to a first set of addresses, the first memory chip including a first CS pad and a first set of address pads;
the memory device further comprises a third memory chip configured to store a second data set corresponding to a second set of addresses, the third memory chip including a second CS pad and a second set of address pads, wherein
the second CS pad is directly connected to the first CS pad, and
the third memory chip is configured to emphasize the first type of performance measure over the second memory chip;

the shared interface connects the first set of address pads and the second set of address pads in parallel;
generating a CS signal includes selecting both the first memory chip and the third memory chip through the directly connected first and second CS pads; and
further comprising:
generating a memory address for selecting either the first memory chip or the third memory chip when the CS signal selects both the first memory chip and the third memory chip.