Patent ID: 11923289
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A method of forming a memory array, the method comprising:
providing a substrate having a first array region and a second array region adjacent the first array region;
forming a vertical stack of plates over the substrate, the vertical stack of plates comprising first material plates comprising a first material alternating with second material plates comprising a second material, the vertical stack of plates comprising:
a lowest first material plate over the substrate, the lowest first material plate extending across the first array region and extending across a first distance of the second array region;
an intermediate first material plate over the lowest first material plate, the intermediate first material plate extending across the first array region and extending across a second distance of the second array region, the second distance being less than the first distance; and
an upper first material plate over the intermediate first material plate, the upper first material plate extending across the first array region and extending across a third distance of the second array region, the third distance being less than the second distance;

forming a plurality of openings in the first array region and in the second array region, the openings extending through the vertical stack of plates into the substrate;
depositing a semiconductive material within the openings to form vertically extending structures;
forming trenches through the vertical stack of plates, the trenches extending across the first array region and the second array region and transforming the vertical stack of plates into horizontally extending lines, each of the horizontally extending lines comprising the first material alternating with the second material, and comprising multiple of the vertically extending structures;
after forming the trenches, removing at least a portion of the first material;
replacing the portion of the first material with conductive line structures, the conductive line structures contacting the vertically extending structures in the first array region and in the second array region, the vertically extending structures within the first array region being operative structures and the vertically extending structures in the second array region being inoperative structures; and
forming conductive contacts in the second array region, each of the conductive contacts being in direct contact with one of the conductive line structure.