Patent ID: 11860685
Assignee: ADVANCED MICRO DEVICES, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 11:
12. The method as recited in claim 11, further comprising:
receiving, by a first pass gate circuit of the multiplexer circuit, an inverted version of the second output clock signal as a first data input signal;
conveying, in the given clock cycle by the first pass gate circuit of the multiplexer circuit, a non-inverted version of the second output clock signal as the second intermediate clock signal, responsive to the reset signal being negated;
receiving, by a second pass gate circuit of the multiplexer circuit, the first intermediate clock signal as a second data input signal; and
conveying, in the given clock cycle by the second pass gate circuit of the multiplexer circuit, an inverted version of the first intermediate clock signal as the second intermediate clock signal, responsive to the reset signal being asserted.