Patent ID: 11862269
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 0:
1. A testing method for a packaged chip, comprising:
acquiring a target chip;
in a post-burn-in test process, testing a first data retention time of each memory unit on the target chip;
comparing the first data retention time of each memory unit with a preset reference time;
determining that the target chip is a qualified chip if the first data retention time of each memory unit is not less than the preset reference time;
determining that a memory unit is an abnormal memory unit if the first data retention time of the memory unit is less than the preset reference time;
repairing the abnormal memory unit;
testing a third data retention time of the abnormal memory unit; and
determining that the target chip is a failed chip if the third data retention time is less than the preset reference time; wherein
the determining that a memory unit is an abnormal memory unit if the first data retention time of the memory unit is less than the preset reference time comprises:
determining that the target chip is a failed chip if the first data retention time of the memory unit is less than a preset repair time,
wherein the preset repair time is less than the preset reference time.