Patent ID: 11935962
Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A transistor comprising:
a silicon oxide layer;
a silicon nitride layer;
an oxide semiconductor layer over the silicon oxide layer and the silicon nitride layer, the oxide semiconductor layer comprising a channel formation region and a second region which is not the channel formation region; and
a gate electrode over the channel formation region of the oxide semiconductor layer with a gate insulating layer therebetween,
wherein the oxide semiconductor layer comprises indium, gallium and zinc,
wherein the silicon oxide layer comprises a region which contacts the channel formation region of the oxide semiconductor layer,
wherein the silicon nitride layer comprises a region which contacts the second region of the oxide semiconductor layer, and
wherein an upper portion of the second region of the oxide semiconductor layer has a lower resistance than the channel formation region of the oxide semiconductor layer.