Patent ID: 11887687
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 18:
19. An apparatus, comprising:
a memory array;
a register coupled with the memory array, wherein the register is associated with one or more parameters for operation of the memory array;
a data bus coupled with the memory array and the register; and
a controller coupled with the memory array and the register, wherein the controller is operable to cause the apparatus to:
receive, during a first set of clock cycles, a first command for reading first data of the memory array;
receive a second command for reading second data of the register during a second set of clock cycles; and
output the first data from the memory array and the second data from the register via the data bus coupled with the memory array and the register based at least in part on receiving the first command and the second command, wherein the first data is output from the memory array during a third set of clock cycles and the second data is output from the register during a fourth set of clock cycles, and wherein a last clock cycle of the third set of clock cycles and a first clock cycle of the fourth set of clock cycles are consecutive clock cycles, and, wherein a first latency between receiving the first command and outputting the first data is the same as a second latency between receiving the second command and outputting the second data.