Patent ID: 11971780
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 2:
3. The data error correction circuit of claim 2, wherein the first latch unit is connected to a first control unit, the second latch unit is connected to a second control unit, the first control unit is configured to control the first latch unit to start latching at a time point n+mt, n is a relative delay time, a starting point of the relative delay time is a time at which the first data is transmitted to the decoding circuit, m is a natural number, t is a transmission interval of the first data, and n is greater than 0 and less than t; and the second control unit is configured to control the second latch unit to start latching between n+mt and n+(m+1)t.