Patent ID: 11937515
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 8:
9. A method, comprising:
receiving a workpiece that includes:
a first dielectric layer,
a plurality of magneto-resistive random-access memory (MRAM) cells disposed in the first dielectric layer, wherein top electrodes of the plurality of MRAM cells are exposed on a top surface of the first dielectric layer, and
a plurality of conductive features extending through the first dielectric layer such that top surfaces of the plurality of conductive features are exposed on the top surface of the first dielectric layer;

depositing a first etch stop layer (ESL) over the first dielectric layer, the MRAM cells, and the plurality of conductive features;
depositing a second ESL on the first ESL;
patterning the first ESL and the second ESL to form a common electrode opening; and
depositing a common electrode in the common electrode opening such that the common electrode is in electrical communication with the top electrodes.