Patent ID: 11929716
Assignee: ANHUI UNIVERSITY
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 13:
14. A method for controlling a Sense Amplifier (SA), the SA comprising an amplifier circuit, an offset voltage storage circuit and a load compensation circuit, wherein the amplifier circuit comprises: a first P-channel Metal Oxide Semiconductor (PMOS) transistor; a second PMOS transistor, a source of the second PMOS transistor being connected to a source of the first PMOS transistor; a first N-channel Metal Oxide Semiconductor (NMOS) transistor, a drain of the first NMOS transistor being connected to a drain of the first PMOS transistor and a first end of the offset voltage storage circuit, and a gate of the first NMOS transistor being connected to a gate of the first PMOS transistor; and a second NMOS transistor, a drain of the second NMOS transistor being connected to a drain of the second PMOS transistor, a source of the second NMOS transistor being connected to a source of the first NMOS transistor, and a gate of the second NMOS transistor being connected to a second end of the offset voltage storage circuit,
the method for controlling the SA comprising:
configuring, in an offset elimination stage of the SA, the first PMOS transistor and the second PMOS transistor as a current mirror, and configuring each of the first NMOS transistor and the second NMOS transistor as a diode connection mode, to control an offset voltage of the amplifier circuit to be stored in the offset voltage storage circuit; and
compensating, in an amplification stage of the SA, a difference between loads of the amplifier circuit through the load compensation circuit.