Patent ID: 11967366
Assignee: NUMEM INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A memory, comprising:
an array comprising rows and columns of memory cells, the rows comprising a first pair of rows of memory cells, the first pair comprising a first row of memory cells and a second row of memory cells;
a plurality of logic gates embedded in the first pair of rows of memory cells, each comprising a first input coupled to a respective memory cell in the first row, a second input coupled to a respective memory cell in the second row, and an output, wherein respective logic gates of the plurality of logic gates are embedded in the first pair of rows between successive memory cells along the first and second rows; and
a plurality of sense lines in the array, wherein the output of each logic gate of the plurality of logic gates is coupled to a sense line of the plurality of sense lines.