Patent ID: 11862639
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 0:
1. A semiconductor device, comprising:
a first semiconductor layer including a first region and a second region;
a plurality of first channel layers spaced apart from each other in a vertical direction on the first semiconductor layer in the first region;
a first gate electrode surrounding the plurality of first channel layers;
a plurality of second channel layers spaced apart from one another in the vertical direction on the first semiconductor layer in the second region; and
a second gate electrode surrounding the plurality of second channel layers,
wherein each of the plurality of first channel layers has a first crystallographic orientation, and each of the plurality of second channel layers has a second crystallographic orientation different from the first crystallographic orientation,
wherein the plurality of first channel layers include a first lowermost channel layer closest to the first semiconductor layer among the plurality of first channel layers,
wherein the plurality of second channel layers include a second lowermost channel layer closest to the first semiconductor layer among the plurality of second channel layers, and
wherein a level of a lower surface of the first lowermost channel layer is different from a level of a lower surface of the second lowermost channel layer.