Patent ID: 11942171
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A method comprising:
decoding, at a row decoder of a memory, a prime row address to provide a prime section signal, wherein the prime row address corresponds to a respective prime memory cell row of a first row section of the plurality of row sections of a memory array mat;
in response to a determination that the prime row address matches a defective prime row address, providing a redundant section signal corresponding to a respective redundant memory cell row of a second row section of the plurality of row sections of the memory array mat;
in response to the prime section signal, initiating, via a first section control circuit of a global decoder, a first threshold voltage compensation operation on first sensing circuitry coupled to the first row section; and
in response to the redundant section signal indicating a defective prime row, initiating, via a second section control circuit of the global decoder, a second threshold voltage compensation operation on second sensing circuitry coupled to the second row section concurrent with the first threshold voltage compensation operation.