Patent ID: 11961891
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method, comprising:
forming a gate dielectric layer;
depositing a first work function metal layer over the gate dielectric layer;
depositing a fill-metal layer over the first work function metal layer, wherein the fill-metal layer defines a concave recess;
depositing a second work function metal layer in the concave recess;
etching the first work function metal layer, the fill-metal layer, and the second work function metal layer in a manner such that a plurality of segments of the fill-metal layer protrude above the first work function metal layer and the second work function metal layer after the etching;
after the etching, forming a dielectric material over the first work function metal layer, the fill-metal layer, and the second work function metal layer;
etching an opening through the dielectric material, wherein the opening exposes upper surfaces and side surfaces of a plurality of segments of the fill-metal layer; and
filling the opening with a conductive gate contact, wherein the plurality of segments of the fill-metal layer protrudes vertically into the conductive gate contact.