Patent ID: 11968825
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 3:
4. A three-dimensional memory device, comprising:
an alternating stack of insulating layers and word-line-level electrically conductive layers located over a substrate;
a vertical layer stack located over the alternating stack, the vertical layer stack comprising an insulating cap layer, drain select electrodes, and a drain-select-level insulating layer, wherein the drain select electrodes are laterally spaced apart from each other by drain-select-level isolation structures; and
memory stack structures comprising a respective vertical semiconductor channel and a respective memory film vertically extending through the alternating stack, wherein each of the vertical semiconductor channels comprises a word-line-level semiconductor channel portion extending through the alternating stack, a connection channel portion contacting a top end of the word-line-level semiconductor channel, and a drain-select-level semiconductor channel portion vertically extending through the vertical layer stack,
wherein the insulating cap layer contacts an annular top surface of each of the connection channel portions.