Patent ID: 11923325
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 19:
20. A wafer comprising:
a memory structure including a plurality of first conductor layers stacked in a first direction above a substrate, a first semiconductor layer extending in the first direction in the plurality of first conductor layers, and a first charge storage layer provided between the plurality of first conductor layers and the first semiconductor layer;
a second conductor layer provided above the memory structure;
a third conductor layer provided above the second conductor layer;
a fourth conductor layer electrically coupling the second conductor layer and the third conductor layer; and
an insulator layer provided between the second conductor layer and the third conductor layer and including polyimide, wherein
in plan view,
the fourth conductor layer crosses a dicing line, and
the second conductor layer and the third conductor layer sandwich the dicing line.