Patent ID: 11955991
Assignee: nan
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. An apparatus comprising:
a first error correcting code (ECC) circuit coupled to a memory array and configured to:
receive first data and second data;
correct an error in the first data if detected to provide corrected first data, and if an error is not detected, provide the first data as the corrected first data; and
merge the corrected first data with the second data to provide merged data;

a second ECC circuit coupled to the memory array and configured to:
receive the first data and the second data;

merge the first data and the second data to provide initial merge data while the first ECC circuit is merging the corrected first, data with the second data; and
generate second parity data from the initial merge data; and

a write circuit coupled to the first and second ECC circuits and configured to output the merged data and the second parity data to the memory array.