Patent ID: 11900885
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 4:
5. The display panel according to claim 3, futher comprising:
the active layer, the gate insulating layer, the gate conductive layer, the interlayer dielectric layer and the source-drain conductive layer that are disposed on the substrate in sequence;
wherein the active layer includes the first electrodes, the channel portions and the second electrodes of the switching transistor, the driving transistor and the sensing transistor; the gate conductive layer includes the control electrodes of the switching transistor, the driving transistor and the sensing transistor; the source-drain conductive layer includes the first connection patterns and the second connection patterns;
the interlayer dielectric layer and the gate insulating layer are together provided with the second via holes each penetrating through both of the interlayer dielectric layer and the gate insulating layer, and the interlayer dielectric layer is provided with the third via holes therein; the first connection pattern in the first connection patterns is electrically connected to the second electrode of the switching transistor through the second via hole in the second via holes, and is electrically connected to the control electrode of the driving transistor through the third via hole in the third via holes;
the interlayer dielectric layer is further provided with the fourth via holes therein, and the second connection pattern in the second connection patterns is electrically connected to the second electrode of the driving transistor through the fourth via hole in the fourth via holes; and
in the same sub-pixel region, in the second direction, the filter portion and the first via hole have the control electrode, the channel portion and the first electrode of the driving transistor and the auxiliary supply voltage line therebetween; and
the display panel further comprising:
a first electrode layer and a buffer layer that are disposed on the substrate in sequence,
wherein the first electrode layer and the buffer layer are located on a side of the active layer proximate to the substrate; the first electrode layer includes the second electrode plate of the storage capacitor, and the active layer further includes the first electrode plate of the storage capacitor;
the interlayer diecltric layer is further provided with fifth via holes therein, the first connection pattern is further electrically connected to the first electrode plate of the storage capacitor through a fifth via hole in the fifth via holes; the interlayer dielectric layer and the buffer layer are together provided with sixth via holes each penetrating through both of the interlayer dielectric layer and the buffer layer, and the second connection pattern is further electrically connected to the second electrode plate of the storage capacitor through a sixth via hole in the sixth via holes; and
the fith via hole and the sixth via hole are both located on a side of the storage capacitor proximate to the third gap region.