Patent ID: 11960989
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory system comprising:
a memory device including multiple pages coupled to select word lines in a memory region; and
a controller, coupled to the memory device, suitable for:
performing multiple read operations on a select type of page for each word line using multiple read threshold sets;
obtaining fail bit count (FBC) information associated with the multiple read operations, the FBC information including multiple FBC values corresponding to the multiple read threshold sets;
selecting a lowest FBC value among the multiple FBC values;
determining, using a neural network, a read threshold set corresponding to the lowest FBC value as an optimal read threshold set for each word line, wherein the neural network utilizes suboptimal FBC information in addition to the optimal read threshold set to predict the optimal read threshold set; and
when optimal read threshold sets for the select word lines are different each other, predicting, using the neural network, a best read threshold set using the optimal read threshold sets.