Patent ID: 11960344
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. A memory control component comprising:
first and second signaling contacts to be coupled respectively to counterpart signaling contacts of a memory IC; and
control circuitry to:
transmit a write data signal to the memory IC via the first signaling contact while the memory control component is operating in an active mode, the write data signal conveying a plurality of data values to be stored within a memory core of the memory IC; and
while the memory control component is operating in a calibration mode:
transmit, via the first signaling contact, a timing calibration signal to be sampled by the memory IC; and
receive, via the second signaling contact, a plurality of digital samples of the timing calibration signal generated by the memory IC.