Patent ID: 11869949
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor device, comprising:
an insulating dielectric layer disposed on a semiconductor substrate;
a source terminal and a drain terminal, disposed in the insulating dielectric layer over the semiconductor substrate and spaced apart from each other;
a gate structure, disposed in the insulating dielectric layer over the semiconductor substrate and extending from the source terminal to the drain terminal; and
a channel region, located in the insulating dielectric layer over the semiconductor substrate and extending between the source and drain terminals, wherein the channel region is sandwiched between the gate structure and the source and drain terminals and sandwiched between the gate structure and the insulating dielectric layer, and sidewalls of the gate structure are covered by the channel region.