Patent ID: 11901897
Assignee: FUJIFILM BUSINESS INNOVATION CORP.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G  Y | IPC G  H

Claim 0:
1. An information processing apparatus comprising:
a processor connected to a programmable logic circuit, the processor being configured to
allow a first circuit reconfigured in a first region of the programmable logic circuit to execute a process,
in parallel with the process of the first circuit, allow a second circuit to be reconfigured in a second region different from the first region, and
adjust at least one of a clock frequency used in the process of the first circuit and a clock frequency used in reconfiguration of the second circuit so that a time point at which the process of the first circuit is completed and a time point at which the reconfiguration of the second circuit is completed will become closer to each other.