Patent ID: 11916026
Assignee: QUALCOMM INCORPORATED
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 17:
18. A clamp comprising:
first and second transistors coupled in series between a power bus and a ground;
a resistive voltage divider configured to bias a gate of the first transistor and a gate of the second transistor based on a supply voltage on the power bus;
a capacitive voltage divider configured to turn on the first and second transistors in response to a voltage transient on the power bus exceeding a trigger threshold voltage;
a third transistor coupled between the gate of the first transistor and the resistive voltage divider; and
a bias circuit,
wherein the clamp is coupled between the power bus and the ground, in parallel with a circuit that is supplied with power by the power bus, and
wherein the bias circuit is configured to turn on the third transistor when the circuit that is supplied with power by the power bus is active and turn off the third transistor when the circuit that is supplied with power by the power bus is in a sleep mode.