Patent ID: 11899049
Assignee: REALTEK SEMICONDUCTOR CORPORATION
Field: Measurement (Instruments)
Classification: CPC G  H | IPC G  H

Claim 3:
4. The comparison circuit of claim 1, wherein the time accumulating circuit comprises:
a delay circuit comprising a plurality of delay units coupled in series configured to transmit the enabling signal; and
a triggering circuit comprising a plurality of triggering D flip-flops coupled in series each comprising:
an input terminal, wherein the input terminal of a first one of the triggering D flip-flops is configured to receive the enabling signal directly and each of the other triggering D flip-flops is electrically coupled to one of the delay units to receive the enabling signal that the one of the delay units transmit;
an output terminal; and
a clock input terminal configured to receive the stage indication signal;

wherein the output terminal of each of the triggering D flip-flops outputs a signal at the input terminal when the stage indication signal is at the comparison stage finished state, in which the comparison time is determined by a number of the triggering D flip-flops that output the enabling signal at the enabling state, and the number is related to a total delay time length of the delay units transmitting the enabling signal at the enabling state.