Patent ID: 11887690
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. The apparatus of claim 1, further comprising:
a third digit line associated with the first level of the memory die, the third digit line coupled with a third set of memory cells of the memory die;
a fourth digit line associated with the second level of the memory die, the fourth digit line coupled with a fourth set of memory cells of the memory die;
a fifth transistor associated with the first level of the memory die and operable to couple the third digit line with a third conductor that is coupled with the sense amplifier;
a sixth transistor associated with the second level of the memory die and operable to couple the fourth digit line with the second conductor;
a seventh transistor associated with the first level of the memory die and operable to couple the second conductor with a second voltage source; and
an eighth transistor associated with the second level of the memory die and having a channel portion coupled between the third conductor and a fourth conductor.