Patent ID: 11907560
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. An apparatus, comprising:
one or more processors;
one or more memories coupled with the one or more processors; and
instructions stored in the one or more memories and executable, individually or collectively, by the one or more processors to cause the apparatus to:
receive, from a memory device, a plurality of bursts over a plurality of channels, the plurality of bursts comprising a first portion of a code word and a second portion of the code word, the first portion of the code word comprising a cyclic redundancy check (CRC) field comprising a plurality of bits across at least one channel of the plurality of channels; and
identify at least one error bit in the second portion of the code word based at least in part on the CRC field, wherein the CRC field comprises a spare bit, and wherein the at least one error bit indicates bit failure.