Patent ID: 11973019
Assignee: QUALCOMM INCORPORATED
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. A method of fabricating an integrated circuit (IC) die, the method comprising:
forming circuits in a semiconductor layer on a substrate;
forming at least one metal layer on the semiconductor layer, the at least one metal layer comprising horizontal metal traces interconnecting the circuits;
forming an inter-layer medium (ILM) on the at least one metal layer;
forming a plurality of interconnects extending through the ILM and coupled to the at least one metal layer; and
forming a deep trench capacitor (DTC) in the ILM, comprising:
forming a first terminal coupled to a first vertical interconnect among the plurality of interconnects; and
forming a second terminal coupled to a second vertical interconnect among the plurality of interconnects.