Patent ID: 11966600
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. A memory system, comprising:
one or more memory devices comprising memory cells that are each configured to store multiple bits; and
one or more controllers coupled with the one or more memory devices and configured to cause the memory system to:
receive an access command indicating a first set of bits to store in the one or more memory devices using one or more memory cells;
determine, based at least in part on receiving the access command, whether to operate in a first mode of operation associated with a reliability above a first threshold or a second mode of operation associated with a storage capacity above a second threshold;
generate a second set of bits based at least in part on determining to operate in the first mode of operation; and
store the first set of bits and the second set of bits within the one or more memory cells.