Patent ID: 11871553
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 0:
1. A semiconductor device, comprising:
a substrate including a logic cell region and a connection region;
a dummy transistor on the connection region;
an intermediate connection layer on the dummy transistor, the intermediate connection layer including a connection pattern electrically connected to the dummy transistor;
a first metal layer on the intermediate connection layer;
an etch stop layer between the intermediate connection layer and the first metal layer, the etch stop layer covering a top surface of the connection pattern; and
a penetration contact extended from the first metal layer toward a bottom surface of the substrate penetrating the connection region,
wherein an upper portion of the penetration contact protrudes above the etch stop layer,
the first metal layer including a first interconnection line, a second interconnection line, and a via below the second interconnection line,
the via penetrates the etch stop layer and connects the second interconnection line to the connection pattern, and
a top surface of the penetration contact is in direct contact with a bottom surface of the first interconnection line.