Patent ID: 11908692
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method, comprising:
performing a first exposure process using a first mask to transfer a first layout pattern of the first mask onto a photoresist layer;
performing a first development process to form a first wiring opening with the first layout pattern in the photoresist layer;
after performing the first development process, performing a second exposure process using a second mask to transfer a second layout pattern of the second mask onto the photoresist layer, wherein the second layout pattern transferred onto the photoresist layer is substantially aligned with and overlaps an overlay region of the first wiring opening;
performing a second development process to form a second wiring opening with the second layout pattern in the photoresist layer, wherein the first wiring opening and the second wiring opening are communicated at the overlay region; and
after performing the second development process, forming a conductive wiring in the first wiring opening and the second wiring opening.