Patent ID: 11862702
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 0:
1. An integrated circuit structure, comprising:
an insulator fin directly on an insulator layer of an insulator substrate, the insulator fin having a bottommost surface;
a vertical arrangement of horizontal semiconductor nanowires over the insulator fin;
a gate stack surrounding a channel region of the vertical arrangement of horizontal semiconductor nanowires, and the gate stack overlying the insulator fin; and
a pair of epitaxial source or drain structures at first and second ends of the vertical arrangement of horizontal semiconductor nanowires, each of the pair of epitaxial source or drain structures having a bottommost surface at a different level than the bottommost surface of the insulator fin, and each of the pair of epitaxial source or drain structures in contact with a corresponding sidewall of the insulator fin, wherein each of the pair of epitaxial source or drain structures does not vertically overlap with the insulator fin.