Patent ID: 11960744
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A device, comprising:
a memory controller that when in operation:
initiates an access of a first portion of a memory partition at a predetermined first time;
initiates an access of a register at a predetermined second time during a latency period associated with access of the first portion of the memory partition, wherein the latency period comprises a time period in which to access the first portion of the memory partition, wherein the second predetermined time is selected to allow for completion of the access of first register during the latency period; and
initiates an access of a second portion of the memory partition at a predetermined third time occurring during the access of the first portion of the memory partition or subsequent to completion of the access of the first portion of the memory partition or initiates a access of a second memory partition at the predetermined third time.