Patent ID: 11888030
Assignee: IDEAL POWER INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 5:
6. A switch assembly comprising:
an upper terminal, a lower terminal, and an upper-control input;
a transistor defining an upper-control lead, an upper-main lead, a lower-control lead, and a lower-main lead;
an upper-main FET defining a first lead coupled to the upper terminal, a second lead coupled to the upper-main lead, and a gate;
a lower-main FET defining a first lead coupled to the lower-main lead, a second lead coupled to the lower terminal, and a gate;
a controller coupled to the upper-control input, the gate of the upper-main FET, and the gate of the lower-main FET, and for a first applied voltage across the upper terminal and the lower terminal, the controller configured to:
assert the gate of the upper-main FET to make the upper-main FET conductive, arrange the transistor for conduction, and assert the gate of the lower-main FET to make the lower-main FET conductive such that a first load current flows from the upper terminal to the lower terminal;
sense de-assertion of the upper-control input; and responsive to de-assertion of the upper-control input
de-assert the gate of the lower-main FET to interrupt the first load current and commutate a first shutoff current through the lower-control lead to the lower terminal; and
arrange the transistor to block current flow from the upper terminal to the lower terminal.