Patent ID: 11950423
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 0:
1. A semiconductor device comprising:
a cell area comprising a cell substrate, a memory cell array, and a first bonding metal pad on the memory cell array, the memory cell array comprising a plurality of word lines stacked in a vertical direction on the cell substrate and a plurality of bit lines on the plurality of word lines; and
a peripheral circuit area having the cell area stacked thereon in the vertical direction, the peripheral circuit area comprising a peripheral circuit substrate, a plurality of circuits on the peripheral circuit substrate, and a second bonding metal pad bonded to the first bonding metal pad,
wherein the plurality of circuits comprise:
a plurality of planar channel transistors respectively configured to form a channel along a top surface of the peripheral circuit substrate; and
at least one recess channel transistor configured to form a channel along a surface of a recess trench in the peripheral circuit substrate,
wherein the at least one recess channel transistor comprises first and second recess channel transistors,
the first recess channel transistor comprises a first gate electrode or a first source/drain region extending to a first depth in the vertical direction relative to the top surface of the peripheral circuit substrate, and
the second recess channel transistor comprises a second gate electrode or a second source/drain region extending to a second depth greater than the first depth in the vertical direction relative to the top surface of the peripheral circuit substrate.