Patent ID: 11942528
Assignee: nan
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. A semiconductor device comprising:
a substrate;
a first fin, a second fin and a third fin on the substrate;
a first epitaxial source/drain on the first fin;
a second epitaxial source/drain on the second fin;
a third epitaxial source/drain on the third fin; and
a contact in contact with the first, second and third epitaxial source/drains,
wherein the first, second and third epitaxial source/drains are merged into a merged epitaxial source/drain,
wherein an upper surface of the merged epitaxial source/drain includes a first recess and a second recess,
wherein a depth of the first recess is different from a depth of the second recess.