Patent ID: 11961555
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. The resistive memory device of claim 2,
wherein a second edge bit line included in the second bit line group is adjacent to the first bit line group and is connected to a fourth global bit line through a second edge transistor; and
the resistive memory device further comprises a third bit line group including a plurality of bit lines and differing from the second bit line group, the third bit line group being adjacent to the second bit line group,
wherein a third edge bit line included in the third bit line group is adjacent to the second bit line group,
the third edge bit line is connected to the fourth global bit line through a third edge transistor, and
the third edge bit line is connected to the second global bit line through a third boundary transistor.