Patent ID: 11960408
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. The semiconductor memory device of claim 1, wherein:
the first to third upper latch blocks are electrically connected to the first upper sub-selection block,
the fourth to sixth upper latch blocks are electrically connected to the second upper sub-selection block,
the seventh to ninth upper latch blocks are electrically connected to the third upper sub-selection block,
the tenth to twelfth upper latch blocks are electrically connected to the fourth upper sub-selection block,
the first to third lower latch blocks are electrically connected to the first lower sub-selection block,
the fourth to sixth lower latch blocks are electrically connected to the second lower sub-selection block,
the seventh to ninth lower latch blocks are electrically connected to the third lower sub-selection block, and
the tenth to twelfth lower latch blocks are electrically connected to the fourth lower sub-selection block.