Patent ID: 11961550
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device comprising:
a memory cell array comprising a plurality of memory cells connected to a plurality of wordlines and a plurality of bitlines;
a target row refresh logic circuit configured to:
select a target row address from among a plurality of target row addresses as a refresh row address based on victim point values, and
perform a refresh operation on first memory cells of the plurality of memory cells connected to a wordline of the plurality of wordlines indicated by the refresh row address;

a victim point table configured to store the victim point values for the target row addresses; and
a victim point accumulator configured to:
receive a first row address from an external device, and
accumulate a first victim point value for at least one target row address corresponding to the first row address during a unit time period.