Patent ID: 11923298
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A method of fabricating a semiconductor device, the method comprising:
patterning a substrate to form an active pattern;
forming a gate electrode that crosses the active pattern;
forming a pair of source/drain patterns in an upper portion of the active pattern, the pair of source/drain patterns being formed at opposite sides, respectively, of the gate electrode;
forming a gate capping pattern on the gate electrode;
forming a first interlayer insulating layer on the pair of source/drain patterns;
forming first and second active contacts that penetrate the first interlayer insulating layer and connect to the pair of source/drain patterns, respectively;
forming an insulating structure that covers a top surface of the second active contact; and
forming an interconnection line on the first active contact, the gate capping pattern, and the insulating structure,
wherein the forming of the insulating structure includes:
sequentially forming first, second, and third insulating layers;
forming a photoresist pattern on the third insulating layer to define a node close region; and
etching the first, second, and third insulating layers using the photoresist pattern as an etch mask.