Patent ID: 11967388
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. A method for operating non-volatile storage, the method comprising:
erasing a block of NAND memory cells;
applying stress to the block of memory cells including performing the following for a plurality of successively programmed word lines in the block:
i) applying a program voltage to a presently selected word line in the block;
ii) applying a nominal boosting voltage to a group of unselected word lines in the block; and
iii) applying a stress voltage to an unselected word line adjacent to the selected word line for which memory cells have already been programmed, wherein the stress voltage has a lower magnitude than the nominal boosting voltage;

determining whether the block of memory cells passes a test criterion after applying the stress voltage; and
marking the block of memory cells as a grown bad block (GBB) in response to the block of memory cells failing the test criterion.