Patent ID: 11908850
Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 9:
10. A display device comprising:
a substrate;
an insulating layer;
a plurality of light-emitting diodes over the substrate, the plurality of light-emitting diodes arranged in a matrix;
a plurality of transistors each electrically connected to at least one of the plurality of light-emitting diodes; and
a plurality of conductive pastes between the plurality of light-emitting diodes and the plurality of transistors,
wherein one of the plurality of transistors is electrically connected to the one of the plurality of light-emitting diodes via one of the plurality of conductive pastes,
wherein the plurality of light-emitting diodes is closer to the substrate than the plurality of transistors is,
wherein each of the plurality of light-emitting diodes is a micro light-emitting diode,
wherein an area of a light-emitting region of each of the plurality of light-emitting diodes is less than or equal to 10000 μm2,
wherein the plurality of light-emitting diodes is configured to emit light toward the substrate,
wherein each of the plurality of transistors comprises a metal oxide layer, a gate insulating layer, a gate electrode, a first conductive layer, and a second conductive layer,
wherein the metal oxide layer comprises a first region, a second region, and a third region comprising a channel formation region between the first region and the second region,
wherein the first conductive layer overlaps with the first region and the second conductive layer overlaps with the second region,
wherein the first conductive layer and the second conductive layer are apart from each other over the metal oxide layer,
wherein the insulating layer is over the first conductive layer and the second conductive layer,
wherein the insulating layer comprises an opening overlapping with the third region,
wherein the gate insulating layer and the gate electrode are inside the opening, and
wherein the gate electrode faces the insulating layer with the gate insulating layer therebetween and faces the third region with the gate insulating layer therebetween.