Patent ID: 11888496
Assignee: KIOXIA CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 16:
17. A semiconductor integrated circuit comprising:
an A/D converter configured to convert an analog signal into a digital signal based on a clock signal;
a first equalizer circuit configured to receive a signal based on the digital signal and output a first signal;
a second equalizer circuit configured to receive a signal based on the digital signal and output a second signal;
a first data comparator circuit configured to determine data based on the first signal and output the determined data as first data;
a control circuit configured to adjust a phase of the clock signal based on the first signal and the first data by executing an adjusting operation, and input the adjusted clock signal to the A/D converter; and
a second data comparator circuit configured to determine data based on the second signal and output the determined data to an outside, wherein
in the adjusting operation, the control circuit is configured to perform adjustment to make a gain of the first signal decrease.