Patent ID: 11947840
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 28:
29. An apparatus comprising:
a memory device including a first die, a second die, and a third die, the first die coupled to the second die, the second die coupled to the third die;
an interconnect coupled to the memory device; and
a host device, the host device including a memory controller coupled to the interconnect, the memory controller configured to:
transmit a first command to the first die of the memory device using the interconnect,

the first die of the memory device configured to:
receive the first command from the memory controller using the interconnect, the first command directing the memory device to enter a self-refresh mode;
perform at least one first refresh operation responsive to receipt of the first command; and
transmit a second command to the second die of the memory device responsive to receipt of the first command, the second command relating to at least one second refresh operation;

the second die of the memory device configured to:
receive the second command from the first die of the memory device;
perform the at least one second refresh operation so as to at least partially overlap the at least one first refresh operation responsive to receipt of the second command; and
transmit a third command to the third die of the memory device responsive to receipt of the second command, the third command relating to at least one third refresh operation; and

the third die of the memory device configured to:
receive the third command from the second die of the memory device; and
perform the at least one third refresh operation so as to at least partially overlap the at least one second refresh operation responsive to receipt of the third command.