Patent ID: 11899959
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. A memory device comprising:
a plurality of memory banks, each of the plurality of memory banks comprising a plurality of memory cells;
a control circuit configured to control an operation of the memory device, wherein the control circuit comprises a mode register that provides operational options of the memory device, and a test mode register that provides test mode options comprising a parallel bit test (PBT) test mode and a double data rate (DDR) test mode; and
a memory built-in self-test (MBIST) circuit configured to test the plurality of memory banks in the DDR test mode or the PBT test mode,
wherein the MBIST circuit is further configured to perform a repair operation for replacing a defective cell detected in the PBT test or the DDR test with a redundancy cell, and perform a re-test on only a portion of the plurality of memory cells including the defective cell to verify the repair operation.