Patent ID: 11862238
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. The apparatus of claim 7, wherein the memory cell block is a first memory cell block, and the apparatus further comprises:
a first portion of a second memory cell block, the first portion of the second memory cell block including first additional memory cell string;
a second portion of the second memory cell block located over the first portion of the second memory cell block, the second portion of the second memory cell block including second additional memory cell strings;
first additional select transistors, each of the first additional select transistors located between a respective data line of the first data lines and a respective memory cell string of the first additional memory cell strings;
second additional select transistors, each of the second additional transistors located between a respective data line of the second data lines and a respective memory cell string of the second additional memory cell strings; and
additional select lines, each of the additional select lines coupled to a respective select transistor of the first additional select transistors and a respective select transistor of the second additional select transistors.