Patent ID: 11886725
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. The computer-implemented method according to claim 7, wherein the memory blocks corresponding to a split node do not include a pointer to any of the child nodes of the split node,
wherein, in executing the nodes, the attributes of the nodes are accessed from the memory according to an implicit ordering of the memory blocks in the memory buffer, and
wherein the implicit ordering of the memory blocks results in accessing attributes of child nodes of a split node in accordance with the following rules:
an offset of a first child block corresponding to the first child node of each the split node is equal to an offset of the split block corresponding to the split node plus S bytes; and
an offset of a second child block corresponding to the second child node of the split node is equal to the offset of the split block corresponding to the split node plus 2(R−1)×(S+L) bytes, where R denotes a number of tree levels in the decision tree under a tree level that includes any of the split nodes.