Patent ID: 11948972
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 15:
16. A structure, comprising:
a first nanostructure and a second nanostructure disposed on a substrate;
a source/drain (S/D) region disposed on the substrate and adjacent to the first and second nanostructures;
a spacer structure interposed between the S/D region and the first nanostructure;
a gate structure, comprising:
a dielectric layer disposed on and in contact with a top surface of the second nanostructure, wherein sidewalls of the dielectric layer are aligned with sidewalls of the second nanostructure, and wherein the dielectric layer comprises a silicon oxide with a first thickness; and
a high-k dielectric layer with a second thickness disposed on the dielectric layer, and wherein a ratio of the first thickness to the second thickness is between about 1.1 and about 3.5; and

gate spacers disposed on and in contact with a top surface of the dielectric layer.