Patent ID: 11862236
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 7:
8. The method of claim 1 further comprising:
receiving a second command/address value that specifies a memory write access;
if the configuration value specifies the first operating mode:
receiving first write data via the fixed-width data interface over Q successive data reception intervals; and
decoding a third column address constituted by N bits of the second command/address value to enable storage of the first write data within a second one of the 2N independently accessible regions of the page buffer; and

if the configuration value specifies the second operating mode:
receiving second write data via the fixed-width data interface over R successive data reception intervals; and
decoding a fourth column address constituted by M bits of the second command/address value to enable storage of the second write data within a second one of the 2M independently accessible regions of the page buffer.