Patent ID: 11934527
Assignee: GENERAL ELECTRIC COMPANY
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. The device of claim 13, further comprising machine-readable instructions that, when executed, cause the one or more processors to perform at least the following:
execute the first set of machine-readable instructions within a predetermined period of time;
load a second set of machine-readable instructions and second configuration information associated with the second set of machine-readable instructions onto the non-transitory computer-readable medium in response to the predetermined period of time elapsing, wherein the second set of machine-readable instructions and the second configuration information are associated with one or more non-priority partitions;
authenticate the second set of machine-readable instructions; and
execute the second set of machine-readable instructions in response to authentication of the second set of machine-readable instructions.