Patent ID: 11930715
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 14:
15. A method comprising:
forming a metal layer on a bottom electrode;
forming a first antireflective coating layer on the metal layer;
forming a patterned first resist layer on the first antireflective coating layer;
patterning the first antireflective coating layer and the metal layer by using the patterned
trimming the patterned metal layer to form a metal via;
forming a first dielectric layer around the metal via;
forming a pinned layer on the metal via;
forming a tunnel barrier layer on the pinned layer;
forming a top electrode on the tunnel barrier layer;
patterning the tunnel barrier layer, the pinned layer and the first dielectric layer while using the top electrode as mask, wherein patterning of the tunnel barrier layer, the pinned layer and the first dielectric layer forms metal re-deposition material on the patterned first dielectric layer; and
forming a second dielectric layer directly on the metal re-deposition material.