Patent ID: 11923034
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 18:
19. An integrated circuit comprising:
a first layer disposed on a first side of a substrate; and
a second layer disposed on a second side of the substrate, the second side being opposite to the first side;
wherein the second layer includes a set of metal rails; and
wherein the first layer includes:
a first region configured to form a memory array including memory cells;
a plurality of second regions configured to form a set of interface circuits operatively coupled to the memory array, the plurality of second regions arranged next to the first region along a first lateral direction; and
a plurality of third regions configured to form a set of header circuits to receive power from the set of metal rails in the second layer and to provide the power to the set of interface circuits;

wherein each of the plurality of third regions is arranged next to a corresponding one of the plurality of second regions along a second lateral direction perpendicular to the first lateral direction;
wherein a first side of each of the second regions extending along the first lateral direction is longer than a second side of each of the second regions extending along the second lateral direction.