Patent ID: 11923430
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A device structure, comprising:
a substrate; and
a first transistor disposed over a first region of the substrate, the first transistor comprising:
a first fin;
a first gate structure comprising:
an interfacial layer over a channel region of the first fin,
a first high-k dielectric layer disposed on the interfacial layer,
a second high-k dielectric layer disposed on the first high-k dielectric layer, and
a capping layer disposed on the second high-k dielectric layer,

wherein the first high-k dielectric layer and the second high-k dielectric layer comprise hafnium oxide,
wherein the second high-k dielectric layer is doped with lanthanum and the first high-k dielectric layer is substantially undoped.