Patent ID: 11967357
Assignee: NATIONAL TSING HUA UNIVERSITY
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 8:
9. The memory unit with time domain edge delay accumulation for computing-in-memory applications of claim 8, wherein,
the at least one first-column memory cell further comprises a first-column local bit line bar, wherein the first-column local bit line bar is connected to the at least one edge-delay cell multiplexor and transmits a first inverted weight opposite to the first weight to the at least one edge-delay cell multiplexor;
the at least one second-column memory cell further comprises a second-column local bit line bar, wherein the second-column local bit line bar is connected to the at least one edge-delay cell multiplexor and transmits a second inverted weight opposite to the second weight to the at least one edge-delay cell multiplexor.