Patent ID: 11923035
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. A pseudo dual port memory device comprising:
a memory cell;
a pair of bit lines connected to the memory cell;
a column multiplexer connected to the bit lines and configured to receive a write multiplexer control signal and a read multiplexer control signal;
a bit line precharge circuit configured to precharge the bit lines during a first time interval in response to the write multiplexer control signal and the read multiplexer control signal;
a sense amp configured to perform a read operation during a second time interval that is subsequent to the first time interval; and
a write driver configured to perform a write operation during a third time interval that is subsequent to the second time interval,
wherein the column multiplexer is configured to connect the bit lines to the write driver in response to the write multiplexer control signal and connect the bit lines to the sense amp in response to the read multiplexer control signal, and
wherein the bit line precharge circuit is configured to not perform a precharge operation on the bit lines during a fourth time interval between the second time interval and the third time interval.