Patent ID: 11972144
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. An apparatus, comprising:
a plurality of memory dice;
a data bus coupled with each of the plurality of memory dice; and
a controller coupled with each of the plurality of via the data bus, the controller configured to:
transmit a first command associated with a first operation to a first memory die of the plurality of memory dice, wherein the first command comprises an assignment of the first operation to a queue slot of a status bank, wherein the first memory die comprises a plurality of queue slots of each of a plurality of status banks, wherein each queue slot of the plurality of queue slots of each of the plurality of status banks is associated with a respective channel of the data bus;
transmit a second command to the first memory die based at least in part on transmitting the first command, wherein the second command requests a status associated with the status bank; and
receive, via a first channel of the data bus determined based at least in part on the assigned queue slot of the status bank, the status of the first operation based at least in part on transmitting the second command to the first memory die.