Patent ID: 11882688
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A semiconductor memory device comprising:
a substrate comprising a cell region, wherein the cell region comprises a first region and a second region along a boundary of the first region;
a plurality of support patterns on the first region of the cell region and spaced apart from each other;
a dummy support pattern extending along the second region of the cell region, wherein the first region of the cell region is free of the dummy support pattern;
a plurality of lower electrodes on the first region of the cell region, wherein respective subsets of the lower electrodes are connected by each of the support patterns; and
a plurality of dummy lower electrodes on the second region of the cell region of the substrate and connected by the dummy support pattern,
wherein the support patterns are arranged in a honey-comb structure, and
wherein the respective subsets of the lower electrodes consist of six edge lower electrodes arranged along a periphery of each of the support patterns at respective vertices of a hexagonal shape and free of electrodes between the respective vertices, and one center lower electrode that is centrally positioned within the periphery, wherein respective distances between the center lower electrode and each of the edge lower electrodes are the same.