Patent ID: 11869607
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A system comprising:
a memory die comprising:
a set of physical memory locations storing pre-loaded data; and
an aging bin comprising one or more physical memory locations of the memory die that are different from the set of physical memory locations, and the aging bin storing a program-erase count describing a number of times data has been written to or erased from the set of physical memory locations; and
a processing device operatively coupled to the memory die, the processing device configured to perform operations comprising:
determining a charge loss value of the aging bin based on a difference between a current charge distribution of the aging bin and a reference charge distribution, the reference charge distribution being measured prior to the memory die being solder mounted to a printed circuit board;
determining a voltage level threshold for reading data from the set of physical memory locations, the voltage level threshold being determined based on the charge loss value; and
reading a portion of preloaded data from the set of physical memory locations based on the voltage level threshold.