Patent ID: 11881242
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A memory device including a plurality of memory cells, each memory cell comprising:
a multi-gate ferroelectric gate Field Effect Transistor (FeFET) comprising:
a substrate defining first and second source/drain regions having a first doping type, and a channel region having a second doping type opposite the first doping type situated between the first and second source/drain regions;
a first source/drain terminal electrically connected to the first source/drain region;
a second source/drain terminal electrically connected to the second source/drain region;
a gate electrode arranged over the channel region;
a back end of the line (BEOL) ferroelectric gate structure over the gate electrode including:
a plurality of ferroelectric layers including a first ferroelectric layer and a second ferroelectric layer arranged in a stacked configuration;
a first conductive gate layer abutting a first side of the first ferroelectric layer, the first side of the first ferroelectric layer having a first surface area;
a buffer layer between a second side of the first conductive gate layer and a first side of the second ferroelectric layer, the first side of the second ferroelectric layer having a second surface area that is different from the first surface area;
a second conductive gate layer arranged on the second side of the second ferroelectric layer; and
a non-ferroelectric gate oxide positioned between the gate electrode and the substrate.