Patent ID: 11943939
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. An integrated circuit (IC) device, comprising:
a substrate;
a circuit region over the substrate, the circuit region corresponding to an intellectual property (IP) block, the circuit region comprising:
a boundary, and
a plurality of input/output (IO) patterns inside the boundary;

a first via over and electrically coupled to a first IO pattern among the plurality of IO patterns of the circuit region;
a first metal layer over the first via, the first metal layer comprising an access pattern which extends from outside the boundary of the circuit region to inside the boundary to overlap and electrically contact the first via, wherein the access pattern and the first IO pattern form an acute angle therebetween;
a second metal layer over the substrate, the second metal layer comprising a further pattern outside the boundary of the circuit region;
a second via over and electrically coupled to the further pattern; and
a third metal layer over the second via, the third metal layer comprising:
the plurality of IO patterns parallel to each other, and
an extension pattern which is contiguous to a second IO pattern among the plurality of IO patterns, and extends from inside the boundary of the circuit region to outside the boundary where the extension pattern overlaps and is electrically coupled to the second via,

wherein
the extension pattern extends transversely to and overlaps the further pattern in the second metal layer, and
the access pattern and the further pattern form an acute angle therebetween.