Patent ID: 11879170
Assignee: MASSACHUSETTS INSTITUTE OF TECHNOLOGY
Field: Semiconductors (Electrical engineering)
Classification: CPC C  H  G | IPC C  G  H

Claim 10:
11. A method for fabricating a device, the method comprising:
providing a substrate having a stressed layer disposed on a first surface of the substrate;
etching a first set of patterns into the stressed layer, the first set of patterns having a predetermined geometry, size, and arrangement selected to control an equibiaxial stress field of the stressed layer, wherein the equibiaxial stress field varies in magnitude over the first surface of the substrate; and
etching a second set of patterns into the first set of patterns and the substrate, the second set of patterns comprising a plurality of substantially parallel lines arranged to control at least a uniaxial stress field of the stressed layer, wherein the uniaxial stress field varies in magnitude over the first surface of the substrate.