Patent ID: 11972264
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. An apparatus comprising:
processing circuitry to perform processing operations in response to micro-operations;
front end circuitry to supply the micro-operations to be processed by the processing circuitry; and
prediction circuitry to generate a prediction of a number of loop iterations for which one or more micro-operations per loop iteration are to be supplied by the front end circuitry, where an actual number of the loop iterations to be processed by the processing circuitry is resolvable by the processing circuitry based on at least one operand corresponding to a first loop iteration to be processed by the processing circuitry; in which:
the front end circuitry is configured to vary, based on a level of confidence in the prediction of the number of the loop iterations, a supply rate with which the one or more micro-operations for at least a subset of the loop iterations are supplied to the processing circuitry;
in which for a prediction where the level of confidence meets a supply rate reduction criterion, the front end circuitry is configured to:
supply the one or more micro-operations for an initial subset of the loop iterations at a first supply rate; and
supply the one or more micro-operations for a further subset of the loop iterations at a second supply rate lower than the first supply rate; in which:

the one or more micro-operations comprise one or more predicated micro-operations for which, if at least one unnecessary iteration of the one or more micro-operations is processed by the processing circuitry following an over-prediction of the number of the loop iterations, processing of the at least one unnecessary iteration is predicated to suppress any architectural effect of the unnecessary iteration of the one or more micro-operations;
the initial subset of the loop iterations comprises the number of the loop iterations predicted by the prediction circuitry; and
the further subset of the loop iterations comprises at least one further loop iteration supplied to the processing circuitry at the second supply rate despite being predicted not to be required for processing by the processing circuitry.