Patent ID: 11868692
Assignee: IMAGINATION TECHNOLOGIES LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A system to verify an integrated circuit hardware design for an n-way set associative cache, the n-way set associative cache configured to store a subset of data stored in a main memory, the system comprising:
one or more processors; and
memory comprising computer executable instructions that when executed by the one or more processors cause the one or more processors to implement:
an address generator configured to:
receive an address request;
in response to receiving the address request, select an address from a list of cache set addresses, the list of cache set addresses comprising one or more addresses of the main memory corresponding to each of one or more target sets; and
provide the selected address to a driver to apply stimulus to an instantiation of the integrated circuit hardware design for the n-way set associative cache based on the received address.