Patent ID: 11934481
Assignee: HUAWEI TECHNOLOGIES CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A matrix multiplier, comprising:
an operation circuit, wherein the operation circuit comprises operation units of X rows and Y columns; and
a controller connected to the operation circuit, wherein the controller is configured to perform the following actions:
dividing a first matrix into blocks in a unit of a sub-block whose size is X*L; and
dividing a second matrix into blocks in a unit of a sub-block whose size is L*Y; wherein
the controller is further configured to perform the following action:
inputting sub-blocks of the first matrix and sub-blocks of the second matrix into the operation units of X rows and Y columns, so as to perform matrix multiplication operation between sub-blocks of the first matrix and sub-blocks of the second matrix and wherein:
when M % X≠0, values on a row (M+1) to a row (S*X−M) of the first matrix, are assigned 0; and when K % Y≠0, values on a column (K+1) to a column (R*Y−K) of the first matrix, are assigned 0; or
when K % Y≠0, values on a column (K+1) to a column (R*Y−K) of the first matrix are assigned 0; and when N % X≠0, values on a row (N+1) to a row (T*X −N) of the first matrix are assigned 0.