Patent ID: 11935955
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. A device comprising:
a fin extending from a substrate;
a gate stack over and along sidewalls of the fin;
a gate spacer along a sidewall of the gate stack; and
a source/drain region in the fin and adjacent the gate spacer, the source/drain region comprising:
a first epitaxial layer on the fin, the first epitaxial layer comprising a first silicon-containing semiconductor material and a first n-type dopant;
a second epitaxial layer on the first epitaxial layer, the second epitaxial layer comprising a second silicon-containing semiconductor material and a second n-type dopant, the first silicon-containing semiconductor material being different than the second silicon-containing material, the first epitaxial layer separating the second epitaxial layer from the fin; and
a third epitaxial layer on the second epitaxial layer, the third epitaxial layer comprising a third silicon-containing semiconductor material.