Patent ID: 11973144
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A method of manufacturing a semiconductor device, the method comprising:
forming an epitaxial growth enhancement layer on a semiconductor substrate;
forming a hard mask pattern on the epitaxial growth enhancement layer;
forming a fin structure by patterning the epitaxial growth enhancement layer and a part of the semiconductor substrate by using the hard mask as an etching mask;
forming an isolation insulating layer over a substrate so that an upper portion of the fin structure protrudes from the isolation insulating layer;
forming a sacrificial gate structure over a channel region of the fin structure;
forming a source/drain space by recessing a source/drain region of the fin structure such that the epitaxial growth enhancement layer of the fin structure is exposed in the source/drain space; and
forming a source/drain epitaxial layer in the source/drain recess,
wherein the epitaxial growth enhancement layer is made of oxide of one of SiGe or SiP,
the fin structure includes two epitaxial growth enhancement layers separated by one body layer, and
the source/drain region of the fin structure is recessed such that one of the two epitaxial growth enhancement layers located above the upper surface of the isolation insulating layer is exposed in the source/drain space, and another of the two epitaxial growth enhancement layers located below the upper surface of the isolation insulating layer is not exposed.