Patent ID: 11960408
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A semiconductor memory device comprising:
a unit page buffer block including first to fourth page buffer pairs arranged in a column direction,
wherein each of the first to fourth page buffer pairs includes:
a common column decoder block; and
an upper page buffer stage and a lower page buffer stage electrically and commonly connected to the common column decoder block,
wherein each the upper page buffer stage includes:
an upper selection block;
an upper latch block; and
an upper cache block,
wherein each the lower page buffer stage includes:
a lower selection block;
a lower latch block; and
a lower cache block,
wherein each the upper selection block includes first to fourth sub-selection blocks arranged in a row direction,
wherein each the upper latch block includes first to twelfth upper sub-latch blocks arranged in the row direction,
wherein each the upper cache block includes first to twelfth upper sub-cache blocks arranged in the row direction,
wherein each the lower selection block includes first to fourth sub-section blocks arranged in the row direction,
wherein each the lower latch block includes first to twelfth lower sub-latch blocks arranged in the row direction,
wherein each the lower cache block includes first to twelfth lower sub-cache blocks arranged in the row direction, and
wherein each the common column decoder block includes first to third sub-common column decoder blocks arranged in the row direction.