Patent ID: 11928015
Assignee: NATIONAL TECHNOLOGY & ENGINEERING SOLUTIONS OF SANDIA, LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. A system comprising: a MIL-STD-1553/MIL-STD-1760 communications bus; a terminal that comprises one of a bus controller or a remote terminal, the terminal configured for operation according to at least one of a MIL-STD-1553 communications protocol or a MIL-STD-1760 communications protocol; and a fault insertion device (FID) communicatively coupled between the communications bus and the terminal such that the FID receives transmits and receives messages to and from each of the terminal and the communications bus, the FID comprising a field-programmable gate array (FPGA) that is configured to perform the following acts: responsive to receiving, at the FID, a first signal that indicates a first bit, the first signal received from one of the communications bus or the terminal, determining whether the first bit matches a rule; responsive to determining that the first bit fails to match the rule, causing the FID to transmit a second signal to another of the communications bus or the terminal, the second signal indicative of the first bit; and responsive to determining that the first bit matches the rule, performing an action specified by the rule.