Patent ID: 11862264
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 18:
19. A method of operating a memory circuit, the method comprising:
storing a first value in a first memory cell;
turning on a select transistor in response to a select signal, the select transistor being coupled between the first memory cell and a first node;
applying a first voltage to a first word line of the first memory cell thereby causing a first cell current to flow through the first memory cell to at least the first node;
comparing, by a comparator, a second voltage of the first node with a reference voltage thereby generating a first output signal;
enabling a detection circuit in response to the first output signal; and
disrupting a first current path between the select transistor and at least the first node or a second node in response to the enabling of the detection circuit, wherein disrupting the first current path between the select transistor and at least the first node or the second node comprises:
triggering a first flip-flop in response to a transition of the first output signal from a first level to a second level, thereby causing the first flip-flop to generate a second output signal.