Patent ID: 11925032
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A method of forming a memory device comprising:
forming a continuous first bottom electrode material layer in a memory array region of the memory device;
forming a continuous second bottom electrode material layer on the continuous first bottom electrode material layer;
forming memory cell portions comprising memory elements and top electrodes on the continuous second bottom electrode material layer;
depositing a continuous dielectric sidewall spacer material layer on the memory cell portions and the continuous second bottom electrode material layer;
forming dielectric sidewall spacers on sidewalls of the memory eells cell portions and in contact with an upper surface of the continuous second bottom electrode material layer by selectively removing the continuous dielectric sidewall spacer material layer, wherein the forming of the dielectric sidewall spacers exposes a top surface of a portion of the continuous second bottom electrode material layer;
forming an etch stop dielectric layer on the top electrodes the dielectric sidewall spacers and the continuous second bottom electrode material layer;
forming a patterned mask layer over the etch stop dielectric layer;
and
forming bottom electrodes by etching the etch stop dielectric layer, the continuous second bottom electrode material layer and the continuous first bottom electrode material layer through the patterned mask layer, wherein the bottom electrodes comprise a flat-top portion that extends horizontally beyond an outer periphery of the dielectric sidewall spacers.