Patent ID: 11921578
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 6:
7. A semiconductor device comprising:
an error correction circuit configured to detect an error included in first and second internal data, to generate a failure detection signal during a read operation, and to correct the error included in the first and second internal data during a refresh operation;
a refresh control circuit configured to store an address signal for activating a word line in which the first and second internal data including an error are stored as first and second failure address signals, to output the first and second failure address signals during the refresh operation, and to control a read modify write operation during the refresh operation; and
a core circuit configured to output the first and second internal data stored in the core circuit through the word line activated by the first and second failure address signals during the read modify write operation, and then, store the error-corrected first and second internal data.