Patent ID: 11908685
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A method, comprising:
forming a fin protruding from a semiconductor substrate;
forming a dummy gate over the fin;
forming a spacer layer over the dummy gate;
etching the spacer layer to form a gate spacer along a sidewall of the dummy gate;
forming source/drain (S/D) features in the fin and adjacent to the gate spacer;
after forming the S/D features, treating the gate spacer, including:
implanting Si atoms in an upper portion of the gate spacer using a first dosage source, thereby increasing an amount of Si in the upper portion of the spacer layer with respect to a lower portion; and
implanting C atoms in the Si-implanted upper portion using a second dosage source different from the first dosing source, thereby increasing an amount of C in the Si-implanted upper portion with respect to the lower portion;

forming an interlayer dielectric (ILD) layer over the treated gate spacer;
replacing the dummy gate with a high-k metal gate (HKMG) in the ILD layer; and
forming a dielectric layer in a portion of the ILD layer over the S/D features.