Patent ID: 11917067
Assignee: INTEL CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 19:
20. A hardware processor comprising:
a decoder of a core to decode a single instruction into a decoded single instruction, the single instruction comprising an input operand of a handle including a ciphertext of original data, an authentication tag, and additional authentication data that indicates the handle is usable for decryption but not usable for encryption and indicates the handle is limited for use within a process whose process identification matches corresponding bits in the handle; and
an execution unit of the core to execute the decoded single instruction to:
perform a first check of the authentication tag against the ciphertext and the additional authentication data for any modification to the ciphertext or the additional authentication data,
perform a second check of a current request of the core against one or more restrictions specified by the additional authentication data of the handle,
decrypt the ciphertext to generate the original data only when the first check indicates no modification to the ciphertext or the additional authentication data, and the second check indicates the one or more restrictions are not violated,
perform an operation on the original data to generate result data, and
provide the result data as a resultant of the single instruction.