Patent ID: 11923010
Assignee: INTEL NDTM US LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus, comprising:
a flash memory chip comprising i), ii), iii) and iv) below:
i) a chip interface to receive commands;
ii) a first array of stacked storage cells;
iii) a temperature sensing device; and,
iv) a controller coupled to the chip interface, the first array of stacked storage cells and the temperature sensing device, wherein the controller is to modulate a program step size voltage applied to the first array of stacked storage cells based on a temperature of the flash memory chip as measured by the temperature sensing device, wherein the controller is to decrease the program step size voltage as the temperature of the flash memory chip moves away from a midpoint temperature of a rated temperature range of the flash memory chip and toward a maximum temperature of the rated temperature range of the flash memory chip and is to decrease the program step size voltage as the temperature of the flash memory chip moves away from the midpoint temperature of the rated temperature range of the flash memory chip and toward a minimum temperature of the rated temperature range of the flash memory chip, such that, a different program step size voltage exists for each different temperature within the rated temperature range of the flash memory chip from the midpoint temperature of the rated temperature range of the flash memory chip to the minimum temperature of the rated temperature range of the flash memory chip.