Patent ID: 11907157
Assignee: CORNAMI, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G  H

Claim 31:
32. A reconfigurable processor circuit comprising:
a first interconnection network;
a second interconnection network;
a processor coupled to the first interconnection network; and
a plurality of computational cores arranged in an array, the plurality of computational cores coupled to the first interconnection network and to the second interconnection network, the second interconnection network configured to couple adjacent computational cores of the plurality of computational cores, each computational core comprising:
a memory circuit;
a zeros compression circuit comprising:
a zeros counter configured to count one or more sequential data packets having a zero data payload to generate a zeros count; and
a first data packet generator configured, when a next data packet has a nonzero data payload, to encode the zeros count as a suffix in the next data packet;

a zeros decompression circuit configured to receive the next data packet from the first or second interconnection networks, the zeros decompression circuit comprising:
a suffix counter configured to determine the zeros count from the suffix of the next data packet; and
a second data packet generator configured to generate the one or more data packets having a zero data payload, corresponding to the zeros count, before providing the next data packet having the nonzero data payload;

and
a reconfigurable arithmetic circuit comprising:
at least one input reordering queue configured to store a plurality of inputs, the at least one input reordering queue further comprising input reordering logic circuitry configured to reorder a sequence of the plurality of inputs of the reconfigurable arithmetic circuit and an adjacent reconfigurable arithmetic circuit of an adjacent computational core of the plurality of computational cores;
a configurable multiplier having a plurality of operating modes, the configurable multiplier coupled to the at least one input reordering queue, the plurality of operating modes comprising a fixed point operating mode and a floating point operating mode, wherein the configurable multiplier has a native operating mode of a 27×27 unsigned multiplier further configurable to process signed inputs, and wherein the configurable multiplier is further configurable to become four 8×8 multipliers, two 16×16 single-instruction multiple-data (SIMD) multipliers, one 32×32 multiplier and one 54×54 multiplier;
a shifter and combiner network coupled to the configurable multiplier, the shifter and combiner network comprising:
a shifter circuit; and
a plurality of series-coupled adder circuits coupled to the shifter circuit;

an accumulator circuit coupled to the shifter and combiner network;
at least one control logic circuit coupled to the multiplier shifter and combiner network and to the accumulator circuit; and
at least one output reorder queue coupled to receive and reorder a plurality of outputs from the reconfigurable arithmetic circuit and the adjacent reconfigurable arithmetic circuit of the adjacent computational core of the plurality of computational cores.