Patent ID: 11948644
Assignee: LODESTAR LICENSING GROUP LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. A memory, comprising:
an array of memory cells comprising a plurality of memory cells, wherein each memory cell of the plurality of memory cells is selected for programming to a respective data state of a plurality of data states for a programming operation; and
control logic;
wherein the control logic is configured to cause the memory to:
store data corresponding to the respective data states for a first subset of memory cells of the plurality of memory cells in a first subset of latches of a plurality of latches and store level zero inhibit data in a second subset of latches of the plurality of latches;
in response to the stored data corresponding to the respective data states for the first subset of memory cells, program the first subset of memory cells from a lowest data state of the plurality of data states to their respective data states using a first set of program pulses having programming voltages within a first range of programming voltages;
store data corresponding to the respective data states for a second subset of memory cells of the plurality of memory cells in the second subset of latches and store level zero inhibit data in the first subset of latches; and
in response to the stored data corresponding to the respective data states for the second subset of memory cells, program the second subset of memory cells from the lowest data state of the plurality of data states to their respective data states using a second set of program pulses having programming voltages within a second range of programming voltages;
wherein the first range of programming voltages overlaps the second range of programming voltages;
wherein the first subset of memory cells contains each memory cell of the plurality of memory cells having its respective data state for the programming operation lower than or equal to a highest data state of the plurality of data states and higher than or equal to a first particular data state of the plurality of data states different than the highest data state; and
wherein the second subset of memory cells contains each memory cell of the plurality of memory cells having its respective data state for the programming operation higher than a lowest data state of the plurality of data states and lower than or equal to a second particular data state of the plurality of data states lower than the first particular data state.