Patent ID: 11903189
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 9:
10. A three-dimensional memory, comprising:
a memory cell array comprising a plurality of levels stacked in a first direction, wherein a plurality of memory cells are formed in a plurality of lines in each of the levels, wherein each of the memory cells comprises a transistor, and the transistor comprises:
a first isolation region and a second isolation region formed in a lower layer of the level, wherein the first isolation region is separated from the second isolation region by a first memory film in the lower layer;
a drain region and a source region formed in a middle layer of the level, wherein the drain region is separated from the source region by a second memory film in the middle layer, and a channel between the drain region and source region is wrapped by the second memory film;
a first electrode and a second electrode formed in a higher layer of the level, wherein the first electrode is separated from the second electrode by a third memory film in the higher layer; and
a gate electrode formed between the source region and drain region, wherein the first, second, and third memory films are wrapped by the gate electrode,
wherein the channels and the gate electrodes of the transistors in the memory cells of two adjacent lines in the same level are staggered.