Patent ID: 11881246
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 3:
4. The electronic device according to claim 1, wherein the target address generation circuit comprises:
an input circuit configured to generate a transfer read counting signal based on a read counting signal that is received from the memory region when an internal read signal is input;
an adder configured to generate the counting signal by up-counting the transfer read counting signal;
an output circuit configured to, when an internal write signal is input, generate a write counting signal based on the counting signal and configured to output the write counting signal to the memory region;
a compare circuit configured to generate a flag signal by comparing the counting signal and the storage counting signal, store the counting signal again as the storage counting signal when the flag signal is generated, and initialize the storage counting signal when a reset signal is input; and
a smart refresh control circuit configured to store the address when the flag signal is input, output the stored address as the target address when a smart refresh signal is input, and generate the reset signal by delaying the smart refresh signal.