Patent ID: 11907712
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A hardware processor core comprising:
a first decode cluster comprising a plurality of decoder circuits;
a second decode cluster comprising a plurality of decoder circuits;
a branch predictor to identify a first block of instructions and a second block of instructions younger in program order than the first block of instructions, cause the first block of instructions to be sent to the first decode cluster for decoding, and cause the second block of instructions to be sent to the second decode cluster for decoding;
a microcode sequencer comprising a memory that stores a plurality of micro-operations; and
an arbitration circuit to arbitrate access by the first decode cluster and the second decode cluster to a shared read port of the memory, wherein the arbitration circuit is to allow the second decode cluster decoding the second block of instructions access to the shared read port of the memory instead of the first decode cluster decoding the first block of instructions when an instruction of the second block of instructions has a number of corresponding micro-operations in the microcode sequencer below an arbitration threshold.