Patent ID: 11960990
Assignee: NANOSEMI, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 20:
21. A design structure encoded on a non-transitory machine-readable medium, said design structure comprising elements that, when executed by a processor in a computer-aided design system, generate a machine-executable representation of an artificial neural network computing circuitry comprising:
a receiving circuit to receiving input values at input nodes of an input layer of the neural network comprising a plurality of nodes, at least some of the plurality of nodes further arranged in at least one hidden layer and an output layer;
a computing circuit to compute for a first receiving node, from the plurality of nodes, a first resultant value according to functions realized by respective links coupling the first receiving node to respective source nodes including a first source node and a second source node, wherein computing the first resultant value for the receiving node comprises evaluating, by at least one link of the respective links coupling the first receiving node to the respective source nodes, a piecewise linear function implemented on the at least one link and applied to a first source node from the respective source nodes, including a first piecewise linear function implemented on the link coupling the first source node to the first receiving node and a second piecewise linear function implemented on the link coupling the second source node to the first receiving node;
an aggregation circuit to aggregate at the first receiving node values provided by the respective links coupling the first receiving node to the respective source nodes to produce a non-linear output based, in part, on the evaluated piecewise linear function applied to the first source node by the piecewise linear function implemented by the at least one link; and
computing circuit to compute for a second receiving node, from the plurality of nodes, a second resultant value according to functions realized by respective links coupling the second receiving node to respective source nodes including the first source node and the second source node, wherein computing the second resultant value for the second receiving node comprises evaluating, by at least one link of the respective links coupling the second receiving node to the respective source nodes, a piecewise linear function implemented on the at least one link and applied to a first source node from the respective source nodes, including a third piecewise linear function implemented on the link coupling the first source node to the second receiving node and a fourth piecewise linear function implemented on the link coupling the first source node to the second receiving node, wherein the first, second, third, and forth piecewise linear functions are distinct functions;
wherein computing the first resultant value for the first receiving node comprises evaluating by multiple links of the respective links coupling the first receiving node to the respective source nodes, piecewise linear functions implemented on the multiple links; and
wherein the computing circuitry comprises computing circuitry for concurrent evaluation of the distinct piecewise linear functions for the separate links.