Patent ID: 11860670
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. A method at a processor, the method comprising:
performing a first access of reference information based on a physical address of a memory access request, wherein multiple route tables provide entries corresponding to different respective memory access resources, wherein the multiple route tables comprise:
a first route table which is to correspond to a first table identifier; and
a second route table which is to correspond to a second table identifier;, wherein the reference information represents a list of items which each correspond to a different respective range of addresses, wherein the items each comprise an identifier of a respective one of the multiple route tables, and an identifier of a respective index offset, wherein the items comprise:
a first item comprising the first table identifier and an identifier of a first index offset; and
a second item comprising the second table identifier and an identifier of a second index offset;, based on the first access:
determining a first index which is based on both the physical address and the identifier of the first index offset;
determining, based on the first table identifier, that the first route table comprises memory access information corresponding to a first memory access resource which is a target of the memory access request; and
with the first index, performing a second access of the first route table to identify the memory access information; and
based on the second access, signaling that the memory access request is to be directed to the first memory access resource.