Patent ID: 11886835
Assignee: CEREMORPHIC, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 11:
12. A multi-stage multiplier operative to multiply an n bit A value with an n bit B value, the multi-stage multiplier comprising:
an input splitter separating the A value and B value into a plurality of pairs of sub-values;
each pair of sub-values applied to a respective sub-multipliers operative to form a digital product value;
at least one sub-multiplier comprising:
an analog charge bus;
at least one unit element coupled to the analog charge bus, the at least one unit element comprising a plurality of AND-groups equal in number to a number of bits of a sub-value, each AND-group comprising a plurality of AND gates equal in number to the number of bits of a sub-value, the plurality of AND gates in each AND-group receiving each of the A sub-value bits and a unique one of the B sub-value bits, each AND gate coupled to an analog charge bus according to a binary order;
the analog charge bus coupled to a binary weighted charge summing unit comprising binary weighted capacitors, each binary weighted capacitor having one terminal connected to a unique one of the analog charge bus lines and the other terminal commonly connected to the input of an analog to digital converter (ADC), the ADC generating a digital product value;

each digital product value of each respective sub-multiplier applied to a shifter and shifted according to a sub-value of the A value and B value;
the outputs of the shifters summed to form a product.