Patent ID: 11922018
Assignee: HITACHI, LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 7:
8. The storage system according to claim 6, wherein
in the network learning, the processor divides the feature value map into a plurality of partial feature value maps in a channel direction and, for each of the plurality of partial feature value maps, performs learning for setting the partial feature value map to zero at a predetermined probability and minimizing the error,
in the write processing, the processor divides a feature value map of an input dataset based on the write target multidimensional dataset into a plurality of feature value maps in the channel direction and writes a plurality of encoded datasets respectively corresponding to the plurality of partial feature value maps respectively in a plurality of storage apparatuses, and
in read processing, when there is a storage apparatus having a failure among the plurality of storage apparatuses, the processor reads one or more encoded datasets respectively from one or more storage apparatuses other than the storage apparatus and returns a dataset based on a dataset obtained by subjecting each of the read one or more encoded datasets to decoding processing.