Patent ID: 11916550
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. The integrated circuit of claim 11, wherein each multiplexing latch circuit of the plurality of multiplexing latch circuits further comprises:
a first tri-state inverter comprising:
an input terminal coupled to a data line of the first data line set;
a low enable terminal configured to receive the first latching clock signal; and
a high enable terminal coupled to an output terminal of the first inverter; and

a second tri-state inverter comprising:
an input terminal coupled to a data line of the second data line set;
a low enable terminal configured to receive the second latching clock signal; and
a high enable terminal coupled to an output terminal of the second inverter.