Patent ID: 11916114
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 13:
14. A method comprising:
depositing a first p-type work function metal over a gate dielectric, the first p-type work function metal is disposed around a first nanostructure and a second nanostructure, the first nanostructure and the second nanostructure being vertically stacked;
performing a fluorine treatment on the first p-type work function metal, wherein the fluorine treatment comprises flowing a fluorine-containing precursor on exposed surfaces of the first p-type work function metal without flowing a precursor that triggers a reduction-oxidation reaction with the fluorine-containing precursor; and
after performing the fluorine treatment, depositing a second p-type work function metal over the first p-type work function metal.