Patent ID: 11915743
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 14:
15. A latch circuit, comprising:
a first memory cell comprising:
a word line;
fist and second bit lines;
first and second inverters, the first inverter having an input terminal and an output terminal, the second inverter having an input terminal and an output terminal;
a first cross-coupling line extending directly between the output terminal of the first inverter and the input terminal of the second inverter;
a second cross-coupling line extending directly between the output terminal of the second inverter and the input terminal of the first inverter; and
first and second pass gate transistors, the first pass gate transistor coupled between the output terminal of the second inverter and the first bit line, the second pass gate transistor coupled between the output terminal of the first inverter and the second bit line, the first and second pass gate transistors each having a gate terminal coupled to the word line;
wherein the first cross-coupling line and the second-cross coupling line are cut;
wherein a first coupling line directly couples the input of the first inverter to the first bit line;
wherein a second coupling line directly couples the input of the second inverter to the second bit line, and
wherein the word line is coupled to a clock input terminal to receive a clock signal.