Patent ID: 11876037
Assignee: HOSIN GLOBAL ELECTRONICS CO., LTD
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. The chip stacking and packaging structure according to claim 1, wherein third bonding pads are arranged on the first surface of the substrate;
wherein the heat dissipation module comprises second conductive columns and a second groove; an opening of the second groove is on the first surface of the heat dissipation module; an area of a cross section of the second groove is greater than an area of a cross section of the first groove; and at least a portion of the second groove is arranged outside an orthographic projection of the first groove; each of the second conductive columns passes through the cooling liquid cavity from a bottom wall of the second groove and is connected to the second surface of the heat dissipation module; the second conductive columns are spaced apart from the first groove; a bottom end of each of the second conductive columns is electrically connected with a corresponding third bonding pad of the third bonding pads arranged on the substrate;
wherein the chip stacking and packaging structure further comprises a temperature sensing chip; the third welding pins are arranged on a surface of the temperature sensing chip; the temperature sensing chip is embedded in the second groove and is electrically connected to a top end of each of the second conductive columns through a corresponding third welding pins of the third welding pins.