Patent ID: 11901821
Assignee: M3 TECHNOLOGY INC.
Field: Electrical machinery, apparatus, energy (Electrical engineering)
Classification: CPC H  Y | IPC H

Claim 5:
6. The apparatus of claim 1, wherein the control logic block comprises:
a first latch circuit having a clock input configured to receive the set signal, and a data input and a Q-bar output connected together;
a first AND gate having a first input configured to receive the set signal, and a second input connected to a Q output of the first latch circuit;
a second AND gate having a first input connected to the Q-bar output of the first latch circuit, and a second input configured to receive the set signal;
a first delay block having an input configured to receive a gate drive signal of the high-side switch of the second phase;
a second delay block having an input configured to receive a gate drive signal of the high-side switch of the first phase;
a third AND gate having a first input connected to an output of the first delay block, and a second input configured to receive the set signal;
a fourth AND gate having a first input configured to receive the set signal, and a second input connected to an output of the second delay block;
a first OR gate having a first input connected to an output of the first AND gate, and a second input connected to an output of the third AND gate;
a second OR gate having a first input connected to an output of the fourth AND gate, and a second input connected to an output of the second AND gate;
a second latch circuit having a set input connected to an output of the first OR gate, a reset input configured to receive the first reset signal, a Q output configured to generate a gate drive signal for the high-side switch of the first phase, and a Q-bar output configured to generate a gate drive signal for a low-side switch of the first phase; and
a third latch circuit having a set input connected to an output of the second OR gate, a reset input configured to receive the second reset signal, a Q output configured to generate a gate drive signal for the high-side switch of the second phase, and a Q-bar output configured to generate a gate drive signal for a low-side switch of the second phase.