Patent ID: 11862271
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. A method, comprising:
selecting a column in an array of bitcells for error correction;
writing a first array of data bits to the column and then reading a second array of data bits from the column;
performing a first column error check on the column by comparing the first array of data bits to the second array of data bits and increasing a column error count based on identifying errors between the first array of data bits and the second array of data bits;
writing a third array of data bits to the column and then reading a fourth array of data bits from the column; and
performing a second column error check on the column that is different than the first column error check on the column by comparing the third array of data bits to the fourth array of data bits and increasing the column error count based on identifying errors between the third array of data bits and the fourth array of data bits,
wherein the third array of data bits is a complement or an inverse of the first array of data bits.