Patent ID: 11972070
Assignee: APPLE INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. The device of claim 1, wherein:
the plurality of chiplets further includes a third chiplet and a fourth chiplet, the second chiplet between the first chiplet and the third chiplet and the third chiplet between the second chiplet and the fourth chiplet;
the second chiplet includes a second buffer circuit;
the third chiplet includes a third buffer circuit;
the second routing trace further configured to route the first digital signal between the second pin of the first chiplet and a first pin of the third chiplet coupled to a first terminal of the third buffer circuit;
the plurality of routing traces further includes a third routing trace, a fourth routing trace and a fifth routing trace;
the third routing trace configured to route the first digital signal between a second pin of the third chiplet coupled to a second terminal of the third buffer circuit and a first pin of the fourth chiplet;
the fourth routing trace configured to route a second digital signal between the controller and a second pin of the second chiplet coupled to a first terminal of the second buffer circuit;
the fifth routing trace configured to route the second digital signal between a third pin of the second chiplet coupled to a second terminal of the second buffer circuit and a third pin of the third chiplet; and
the fifth routing trace further configured to route the second digital signal between the third pin of the second chiplet coupled to the second terminal of the second buffer circuit and a second pin of the fourth chiplet.