Patent ID: 11882776
Assignee: TOKYO ELECTRON LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 11:
12. A method of forming a resistive random access memory (RERAM), comprising:
forming a first electrode layer;
forming a memory cell dielectric layer;
forming a second electrode layer, wherein the memory cell dielectric layer is arranged between the first electrode layer and the second electrode layer;
etching the first electrode layer, the memory cell dielectric layer and the second electrode layer to form one or more Metal-Insulator-Metal (MIM) stacks for one or more RERAM cells, wherein said etching is performed within at least one plasma etch chamber;
depositing an encapsulation layer onto the one or more MIM stacks and surrounding surfaces, wherein said depositing is performed within the at least one plasma etch chamber; and
removing the encapsulation layer from a top surface of the one or more MIM stacks and the surrounding surfaces, wherein said removing is performed within the at least one plasma etch chamber.