Patent ID: 11940492
Assignee: STMICROELECTRONICS S.R.L.
Field: Measurement (Instruments)
Classification: CPC G | IPC G

Claim 8:
9. A circuit comprising:
a set of test stimulus generators configured to produce test stimulus signals for at least one circuit under test, wherein a first test stimulus generator of the set of test stimulus generators comprises a first linear-feedback shift register as the test stimulus register in the first test stimulus generator and wherein a second test stimulus generator of the set of test stimulus generators comprises a second linear-feedback shift register as the test stimulus register in the first test stimulus generator, the first linear-feedback shift register being a 32-bit linear-feedback shift register and the second linear-feedback shift register being a 16-bit linear-feedback shift register;
a set of controllers coupled to the set of test stimulus generators and configured to control loading of test stimulus information in the set of test stimulus generators; and
a test programming interface coupled to the set of controllers and configured to load test programming information in the set of controllers, the set of test stimulus generators being configurable at runtime by the set of controllers via software using the test programming interface;
a set of input signature registers, configured to store therein signature reference signals indicative of signature reference values received from the test programming interface; and
signature control circuitry comprising a set of signature control modules coupled to respective ones of the set of input signature registers, the signature control circuitry being separate from the set of controllers, wherein the signature control circuitry further comprises compressor circuitry configured to receive plural sets of test outcome signals from the at least one circuit under test in response to the test stimulus signals being applied thereto, the compressor circuitry comprising:
two gated via AND gates under control of respective enabling signals produced by one or more funnel configuration registers; and
an XOR gate coupled to respective outputs of the two gated via AND gates.