Patent ID: 11961917
Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 3:
4. A semiconductor device comprising:
a first transistor; and
a second transistor over the first transistor,
wherein a channel of the first transistor comprises silicon,
wherein a first semiconductor layer of the second transistor in which a channel is formed comprises an oxide semiconductor,
wherein part of a bottom surface of a first conductive layer functioning as one of a source and a drain of the second transistor is positioned below the first semiconductor layer,
wherein part of a bottom surface of a second conductive layer functioning as the other of the source and the drain of the second transistor is positioned below the first semiconductor layer,
wherein the first conductive layer and the second conductive layer are in contact with a top surface of the first semiconductor layer,
wherein a first insulating layer is provided over the first semiconductor layer,
wherein a third conductive layer functioning as a gate of the second transistor is provided over the first insulating layer,
wherein a second insulating layer is provided over the third conductive layer,
wherein a third insulating layer is provided over the second insulating layer, the first conductive layer and the second conductive layer,
wherein a fourth conductive layer is provided over and in contact with the third insulating layer,
wherein a fifth conductive layer functioning as a gate of the first transistor is provided over the channel of the first transistor with a fourth insulating layer provided therebetween,
wherein the first transistor is electrically connected to the second transistor,
wherein a fifth insulating layer is provided over and overlapping with the fifth conductive layer,
wherein the first semiconductor layer is in contact with a top surface of the fifth insulating layer, and
wherein the first conductive layer is not in contact with a bottom surface of the first semiconductor layer.