Patent ID: 11878388
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC B  H | IPC B  H

Claim 0:
1. A method of manufacturing a semiconductor package, comprising:
placing a die on a carrier;
forming a material layer over the die; and
polishing the material layer using a polishing pad, so as to reduce a height of the material layer, wherein the polishing pad comprises a plurality of grooves having a first width and a plurality of openings having a second width greater than the first width, and the plurality of openings are distributed asymmetrically with respect to a center point of the polishing pad,
wherein the grooves are intersecting X-Y patterns of continuous grooves, and some of the openings intersect at least three of the continuous grooves, and
wherein the openings penetrate through the polishing pad, while the grooves do not penetrate through the polishing pad.