Patent ID: 11966741
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. An apparatus, comprising:
a processor core configured to execute a plurality of instructions;
data path control circuitry configured to control an amount of data transferred in one or more data packets over an interconnection network; and
a core control circuit coupled to the processor core, the core control circuit comprising:
a thread control memory comprising a thread identifier pool register configured to store a plurality of thread identifiers, a program count register configured to store a received program count, and a general-purpose register configured to store at least one received argument;
an execution queue coupled to the thread control memory, the execution queue configured to store one or more thread identifiers, of the plurality of thread identifiers; and
a control logic and thread selection circuit coupled to the execution queue, the control logic and thread selection circuit configured, in response to a work descriptor data packet having the received program count and the at least one received argument, to assign a thread identifier of the plurality of thread identifiers to a corresponding execution thread of a plurality of execution threads, to place the thread identifier in the execution queue, and to periodically select the thread identifier of the one or more thread identifiers in the execution queue for execution, by the processor core, of an instruction of the corresponding execution thread, of the plurality of instructions.