Patent ID: 11935593
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus, comprising:
a control circuit configured to connect to memory cells connected in series in NAND strings, each NAND string including a plurality of data memory cells coupled to a plurality of data word lines in series with a plurality of dummy memory cells connected to a plurality of dummy word lines, the control circuit configured to:
apply a first dummy word line voltage to one or more dummy word lines of the plurality of dummy word lines in a verify step of a program operation to program data memory cells, apply the first dummy word line voltage to the one or more dummy word lines in a first read operation that is directed to a first data word line and apply a second dummy word line voltage to the one or more dummy word lines in a second read operation that is directed to a second data word line.