Patent ID: 11868813
Assignee: HT RESEARCH INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 43:
44. The computer system of claim 37, wherein the fifth fail-over pylon comprises:
a fifth top control fail-over block coupled to the fifth top control block through the fifth workgroup fail-over link;
a fifth mid-memory fail-over block coupled to the fifth mid-memory block through the fifth workgroup fail-over link; and
a fifth base fail-over block coupled to the fifth base attribute block through the fifth workgroup fail-over link,
wherein the fifth base fail-over block comprises:
a plurality of fourth fail-over pylons, wherein the plurality of the fourth fail-over pylons are coupled to the plurality of the fourth execution pylons through the fifth workgroup fail-over link; and
a third plurality of third fail-over pylons, wherein the third plurality of the third fail-over pylons are coupled to the third plurality of the third execution pylons through the fifth workgroup fail-over link,

wherein the fifth top control fail-over block comprises a fourth plurality of the third fail-over pylons, wherein the fourth plurality of the third fail-over pylons are coupled to the fourth plurality of the third execution pylons through the fifth workgroup fail-over link,
wherein each of the third fail-over pylons comprises:
a third top control fail-over block coupled to the third top control block through the fifth workgroup fail-over link;
a third mid-memory fail-over block coupled to the third mid-memory block through the fifth workgroup fail-over link; and
a third base fail-over block coupled to the third base attribute block through the fifth workgroup fail-over link,

wherein each of the fourth fail-over pylons comprises:
a fourth top control fail-over block coupled to the fourth top control block through the fifth workgroup fail-over link;
a fourth mid-memory fail-over block coupled to the fourth mid-memory block through the fifth workgroup fail-over link; and
a fourth base fail-over block coupled to the fourth base attribute block through the fifth workgroup fail-over link,
wherein the fourth top control fail-over block comprises a first plurality of the third fail-over pylons, wherein the first plurality of the third fail-over pylons are coupled to the first plurality of the third execution pylons through the fifth workgroup fail-over link,
wherein the fourth base fail-over block comprises a second plurality of the third fail-over pylons, wherein the second plurality of the third fail-over pylons are coupled to the second plurality of the third execution pylons through the fifth workgroup fail-over link.