Patent ID: 11936296
Assignee: B.G. NEGEV TECHNOLOGIES AND APPLICATIONS LTD., AT BEN-GURION UNIVERSITY
Field: Electrical machinery, apparatus, energy (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A method for voltage regulation in mixed-signal hybrid Average Current-Mode (ACM) controller architecture, comprising:
a. during steady-state operation of said ACM controller, simultaneously measuring an output voltage and average per-phase inductor current, once for each active phase during a switching cycle and in synchronization with an interleaved operation of a multiphase Digital Pulse Width Modulator (DPWM) that controls per-phase currents and output voltage supplied to the load;
b. using the output voltage measurement for generating a voltage error (ve[n]);
c. using a voltage compensator for calculating a current reference signal;
d. generating, by using calculated current reference signal and the inductor current measurement, a current error signal (ie[n]) which is used by a per-phase current compensator to generate a specific phase duty-cycle command (d[n]);
e. receiving said duty-cycle command d[n] by a multiphase DPWM and generating steady-state gating signals;
f. if a transient event occurs during steady-state operation, sensing a transient start time and a transient direction (loading or unloading) by a transient detection sensor;
g. upon detecting a transient event, using a Phase Count Optimizer (PCO) for activating all available phases and allowing a Transient Suppression Unit (TSU) to take control over the transient gating signals and to begin counting (T0);
h. according to the transient direction, said TSU turns on all the phases, using low-side transistors for unloading transients, and high-side transistors for loading transients;
i. continuing step g. above until an output voltage extremum is measured by an extremum detection sensor, while said TSU stops the T0 counter and if no output voltage extremum is detected, resuming the steady-state operation;
j. generating the remaining gating signals timings by said TSU, based on the counter value of T0 and an average duty-cycle value (D), where the correction signals of a hand-off procedure are calculated based on To and fed back to a steady-state controller;
k. completing a gating sequence by said TSU according to the values generated in step i. above; and
l. upon completing a full TSU gating sequence, transferring the control over the gating signals back to said ACM controller, while resuming phase synchronization by said DPWM and steady-state operation according to step a. above.