Patent ID: 11921660
Assignee: HUAWEI TECHNOLOGIES CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 6:
7. The equalization time configuration method of claim 1, further comprising:
when both the first working PHY type and the second working PHY type are SR:
reading a third equalization time of the slave chip in the third phase;
writing the third equalization time into the master chip to set the third equalization time as the first equalization time;
reading a fourth equalization time of the master chip in the fourth phase; and
writing the fourth equalization time into the slave chip to set the fourth equalization time as the second equalization time; and

configuring both the first equalization time and the second equalization time as a default value when both the first working PHY type and the second working PHY type are the LR.