Patent ID: 11914940
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. A system for manufacturing a semiconductor device comprising:
a layout style determination tool configured to detect whether a plurality of active cells have a distributed layout style;
a layout versus schematic (LVS) tool configured to compare a schematic design of the semiconductor device to a layout design of the semiconductor device; and
a dummy insertion tool configured to revise the layout design of the semiconductor device based on the layout design and the schematic design by revising an area of at least one dummy cell when the layout design includes the at least one dummy cell, or inserting the at least one dummy cell between the plurality of active cells and an outside edge of the semiconductor device when the layout design does not include the at least one dummy cell; and
a resistance-capacitance extraction tool configured to perform a resistance-capacitance extraction based on the layout design of the semiconductor device.