Patent ID: 11923861
Assignee: QUALCOMM INCORPORATED
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. The apparatus of claim 1, wherein the each of the set of N cascaded inverter comprises a p-channel metal oxide semiconductor field effect transistor (PMOS FET) coupled in series with an n-channel metal oxide semiconductor field effect transistor (NMOS FET) between the at least one second upper voltage rail and the at least one second lower voltage rail, wherein each ith PMOS FET includes a gate coupled to an output of the (i+2)mod Nth inverter of the set of N cascaded inverters for i=0 to N−1, and wherein each ith NMOS FET includes a gate coupled to an output of the (i−1)mod Nth inverter of the set of N cascaded inverters for i=0 to N−1.