Patent ID: 11862238
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. An apparatus comprising:
a first portion of a memory cell block located in a first deck, the first portion of the memory cell block including first memory cell strings;
a second portion of the memory cell block located in a second deck and located over the first portion of memory cell block, the second portion of the memory cell block including second memory cell strings;
first data lines located between the first and second portions of the memory cell block;
first select transistors located in the first deck, each of the first select transistors located between a respective data line of the first data lines and a respective memory cell string of the first memory cell strings;
second data lines located over the second portion of the memory cell block;
second select transistors located in the second deck, each of the second select transistors located between a respective data line of the second data lines and a respective memory cell string of the second memory cell strings;
select lines, each of the select lines coupled to a respective select transistor of the first select transistors and a respective select transistor of the second select transistors, such that the select lines includes a select line coupled to a transistor of the first select transistors in the first deck and coupled to a transistor of the second select transistors in the second deck;
first access lines coupled to the first memory cell strings; and
second access lines coupled to the second memory cell strings, the second access lines separated from the first access lines.