Patent ID: 11922993
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 13:
14. A device comprising:
an array of memory cells comprising a first word line coupled to at least a subset of the array of memory cells;
a page buffer comprising a plurality of latches to cache data read out of the array; and
control logic coupled to the first word line and the page buffer, the control logic to, in response to receiving a first read command from a processing device, perform operations comprising:
causing a voltage applied to the first word line to move to a target value;
causing the page buffer to sense first data from a first bit line coupled to a first page of the subset of the array;
receiving, from the processing device, a first cache release command associated with at least a first latch of the plurality of latches; and
causing, in response to the first cache release command and during a recovery period of the first word line, the first data to be stored in the first latch.