Patent ID: 11869869
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. A package comprising:
a first die comprising:
a first semiconductor substrate;
a first integrated circuit at a surface of the first semiconductor substrate; and
a first dielectric layer over the first integrated circuit, wherein the first dielectric layer comprises a first dielectric material; and

a second die bonding to the first die, wherein the second die comprises:
a second semiconductor substrate;
a second integrated circuit at a surface of the second semiconductor substrate; and
a second dielectric layer underlying the second integrated circuit, wherein the first dielectric layer is physically bonded to the second dielectric layer, and wherein the second dielectric layer comprises a second dielectric material different from the first dielectric material, wherein the first dielectric layer and the second dielectric layer form an interface layer, and the interface layer has a thickness smaller than about 80 Å.