Patent ID: 11923238
Assignee: QORVO US, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method comprising:
providing a precursor wafer comprising a plurality of device regions, a plurality of individual interfacial layers, and a silicon handle substrate wherein:
each of the plurality of device regions includes a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, wherein the FEOL portion comprises isolation sections and an active layer, which is surrounded by the isolation sections and does not extend vertically beyond the isolation sections;
each of the plurality of individual interfacial layers is over one active layer of a corresponding device region, wherein each of the plurality of individual interfacial layers is formed of silicon germanium (SiGe); and;
the silicon handle substrate is over each of the plurality of individual interfacial layers;

forming a barrier layer covering an entire bottom surface of the precursor wafer, such that the barrier layer covers a bottom surface of the BEOL portion of each of the plurality of device regions;
forming a first bonding layer underneath the barrier layer;
providing a support carrier with a second bonding layer over the support carrier;
attaching the precursor wafer to the support carrier by bonding the first bonding layer directly to the second bonding layer, wherein the first bonding layer and the second bonding layer merge to form a bonding structure, which is separated from the plurality of device regions by the barrier layer;
removing the silicon handle substrate from the precursor wafer to provide an etched wafer after attaching the precursor wafer to the support carrier; and
applying a first mold compound to the etched wafer to provide a mold device wafer, wherein the first mold compound is applied at least over the active layer of each of the plurality of device regions from where the silicon handle substrate is removed.