Patent ID: 11887955
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor die comprising:
dielectric material layers embedding metal interconnect structures;
a connection pad-and-via structure located on a first side of the dielectric material layers, wherein the connection pad-and-via structure comprises a connection via portion that vertically extending through a pad-level dielectric material layer and contacting one of the metal interconnect structures and a pad portion contacting a horizontal surface of the pad-level dielectric material layer;
a bump-level dielectric material layer overlying the connection pad-and-via structure; and
a bump structure located on the bump-level dielectric material layer and comprising a bump via portion extending through the bump-level dielectric material layer and contacting the pad portion, wherein an entirety of a bottom surface of the bump via portion is located within an area of a horizontal top surface of the pad portion of the connection pad-and-via structure, wherein a lateral distance between opposing segments of an outer sidewall of the connection via portion is greater than twice a thickness of the pad portion of the connection pad-and-via structure.