Patent ID: 11948646
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A semiconductor memory comprising:
a plurality of memory cell transistors, a threshold voltage of each of the memory cell transistors being changeable to store multi-bit data;
a word line which is electrically connected to gates of the memory cell transistors;
a plurality of bit lines which are electrically connected to first ends of the memory cell transistors, respectively;
a source line which is electrically connected to second ends of the memory cell transistors;
a plurality of sense amplifier units which are electrically connected to the bit lines, respectively, each of the sense amplifier units including a sense amplifier and a plurality of latches, the latches including a first latch; and
a controller,
wherein the sense amplifier in each of the sense amplifier units includes:
a first transistor having a first end electrically connected to a corresponding one of the bit lines,
a second transistor having a first end electrically connected to a second end of the first transistor and a second end electrically connected to a first node,
a third transistor having a first end electrically connected to the first node,
a fourth transistor having a gate electrically connected to the first latch, a first end electrically connected to a second end of the third transistor, and a second end electrically connected to a first power supply node,
a fifth transistor having a first end electrically connected to the first node, and a second end electrically connected to a second node,
a sixth transistor having a first end electrically connected to the second node, and
a seventh transistor having a gate electrically connected to one of the latches, a first end electrically connected to a second end of the sixth transistor, and a second end electrically connected to a second power supply node.