Patent ID: 11887951
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. A three-dimensional semiconductor memory device, comprising:
a first substrate including a cell array region and a cell array contact region;
a peripheral circuit structure including peripheral transistors, peripheral circuit interconnection lines, and first bonding pads,
the peripheral transistors being on the first substrate,
the peripheral circuit interconnection lines being on the peripheral transistors, and
the first bonding pads being connected to the peripheral transistors through the peripheral circuit interconnection lines; and

a cell array structure including second bonding pads, connection circuit interconnection lines, bit lines, a stack on the bit lines, first vertical channel structures, second vertical channel structures, third vertical channel structures, and a second substrate,
the connection circuit interconnection lines being on the second bonding pads, the bit lines being connected to the second bonding pads through the connection circuit interconnection lines, the first vertical channel structures to the third vertical channel structures penetrating the stack, and
the second substrate being connected to the first vertical channel structures to the third vertical channel structures,
the second bonding pads being integrally bonded to the first bonding pads of the peripheral circuit structure,

the stack being located between the peripheral circuit structure and the second substrate,
the stack including interlayer dielectric layers and gate electrodes, which are alternately and repeatedly stacked and extend in a direction parallel to a top surface of the first substrate,
the first vertical channel structures to the third vertical channel structures being in vertical channel holes penetrating the stack,

each of the first vertical channel structures, the second vertical channel structures, and the third vertical channel structures including a data storage pattern and a vertical semiconductor pattern enclosed by the data storage pattern,
the data storage pattern conformally covering an inner side surface of each of the vertical channel holes,
the data storage pattern including a blocking insulating layer, a charge storing layer, and a tunneling insulating layer, which are sequentially stacked,
the first vertical channel structures and the second vertical channel structures being on the cell array region,
the third vertical channel structures being on the cell array contact region, and
the second substrate including a first portion, a second portion, and a third portion,
the first portion being in contact with the first vertical channel structures and doped to have a first conductivity type,
the second portion being in contact with the second vertical channel structures and doped to have a second conductivity type different from the first conductivity type, and
the third portion being in contact with the third vertical channel structures and doped to have the second conductivity type.