Patent ID: 11863190
Assignee: nan
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. The compound sequential circuit of claim 1, wherein each flip-flop of the plurality of flip-flops further comprises:
a first buffer electrically coupled to the first shared clock node;
a first sequence detector comprising the first buffer and electrically couples to the first output of the latch, the second output of the latch, an input signal, and an inverted input signal, wherein the first sequence detector configured to activate a first transistor and a second transistor in response to:
(1) the input signal is the opposite logic polarity compared to the first output of the latch when a main clock signal is at a first level,
(2) the first transistor and the second transistor are deactivated when the main clock signal is at a second level;
wherein activating the first transistor and the second transistor when the main clock signal is at the first level activates the latch to capture a data bit from the input signal and to generate an output signal based on a level of the captured data bit when the main clock signal transitions from the first level to the second level.