Patent ID: 11900108
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. An apparatus comprising:
a register to store a carry flag, an overflow flag, a sign flag, a zero flag, an auxiliary carry flag, a parity flag;
a decoder operative to decode a rotate right instruction, the rotate right instruction to indicate a 64-bit source operand, to indicate a 64-bit general-purpose register, and having an immediate to indicate a rotate amount; and
execution circuitry coupled with the decoder, the execution circuitry operative to perform operations corresponding to the rotate right instruction, including to:
generate a result, the result to include the 64-bit source operand rotated by the rotate amount indicated by the immediate;
store the result in the 64-bit general-purpose register; and
complete execution of the rotate right instruction without causing the carry flag to be read, without causing the carry flag to be written, without causing the overflow flag to be read, without causing the overflow flag to be written, without causing the sign flag to be read, without causing the sign flag to be written, without causing the zero flag to be read, without causing the zero flag to be written, without causing the auxiliary carry flag to be read, without causing the auxiliary carry flag to be written, without causing the parity flag to be read, and without causing the parity flag to be written.