Patent ID: 11967357
Assignee: NATIONAL TSING HUA UNIVERSITY
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 16:
17. A computing method of a memory unit with time domain edge delay accumulation for computing-in-memory applications, which is controlled by a first word line and a second word line, the computing method comprising:
performing a voltage level applying step, wherein the voltage level applying step comprises applying a plurality of voltage levels to the first word line and the second word line of the memory unit, respectively; and
performing a computing step, wherein the computing step comprises configuring at least one edge-delay cell of the memory unit to compute a multi-bit analog input voltage, an edge-input signal and a weight to generate an edge-output signal having a delay time;
wherein the memory unit comprises:
at least one memory cell storing the weight, wherein the at least one memory cell is controlled by the first word line and comprises a local bit line transmitting the weight;
at least one edge-delay cell multiplexor connected to the at least one memory cell and controlled by the second word line; and
the at least one edge-delay cell connected to the at least one edge-delay cell multiplexor and comprising:
a weight reader configured to receive the weight and the multi-bit analog input voltage and generate a multi-bit voltage according to the weight and the multi-bit analog input voltage; and
a driver connected to the weight reader and configured to receive the edge-input signal, wherein the driver is configured to generate the edge-output signal having the delay time according to the edge-input signal and the multi-bit voltage;

wherein the delay time of the edge-output signal is positively correlated with the multi-bit analog input voltage multiplied by the weight.