Patent ID: 11894047
Assignee: ANHUI UNIVERSITY
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 1:
2. The sense amplifier according to claim 1, wherein the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor at a first node, and the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor at a second node; the sense amplifier further comprises:
a first switch, a first terminal of the first switch being connected to the first node, and a second terminal of the first switch being connected to the gate of the first NMOS transistor;
a second switch, a first terminal of the second switch being connected to the second node, and a second terminal of the second switch being connected to the gate of the second NMOS transistor; and
a third switch, a first terminal of the third switch being connected to the gate of the first PMOS transistor, and a second terminal of the third switch being connected to a gate of the second PMOS transistor;
wherein, in the offset cancellation stage of the sense amplifier, the first switch, the second switch and the third switch are all in a closed state.