Patent ID: 11935604
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device comprising:
a memory array having strings of cells, a first string of the strings having a first selector device, the first selector device coupled to a first select line and coupled to a data line to the memory array; and
one or more drivers to generate a selector signal simultaneously both to the first selector device and to a dummy memory cell of the first string directly adjacent to the first selector device with data memory cells of the first string maintained unselected, in response to a determination of completion of a selected erase operation to at least one data memory cell of the first string, the selected erase operation including an erase verify procedure, the completion completing erasure of the at least one data memory cell of the first string.