Patent ID: 11961908
Assignee: SK HYNIX INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A vertical transistor comprising:
a lower contact on a substrate;
a channel layer including a lower channel layer, an intermediate channel layer, and an upper channel layer sequentially formed on the lower contact, the channel layer including a metal component and an oxygen component; and
an upper contact on the upper channel layer, wherein
the channel layer has a gradual doping profile in which a doping concentration of the metal component is lowest in the intermediate channel layer and, in the upper channel layer, gradually increases towards the upper contact,
wherein the doping concentration of each metal component doped in the lower channel layer and the intermediate channel layer is maintained uniformly,
wherein the channel layer has an abrupt doping profile in which the doping concentration of the metal component sharply increases at a boundary between the intermediate channel layer and the lower channel layer, and
wherein the lower channel layer is a single layer, and the doping concentration of metal component doped in the lower channel layer is maintained constant throughout the lower channel layer.