Patent ID: 11955332
Assignee: APPLIED MATERIALS, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A processing system, comprising:
a first processing chamber;
a second processing chamber;
a third processing chamber;
a fourth processing chamber;
a fifth processing chamber; and
a system controller configured to cause the processing system to:
pre-clean a surface of a substrate in the first processing chamber;
deposit a high-κ gate dielectric layer on the substrate in the second processing chamber;
performing a thermal anneal process in the third processing chamber, to thermally oxidize the substrate;
subsequent to the thermal anneal process, performing a plasma nitridation process in the fourth processing chamber, to insert nitrogen atoms in the deposited high-κ gate dielectric layer, thermal anneal process comprising annealing the high-K gate dielectric layer in an oxygen (O2), nitrous oxide (N2O), and H2 ambient at a temperature of between 400° C. and 900° C.; and
subsequent to the plasma nitridation process, performing a post-nitridation anneal process in the fifth processing chamber, to passivate chemical bonds in the plasma nitridated high-κ gate dielectric layer, the post-nitridation anneal process comprising spike annealing the plasma nitridated high-κ gate dielectric layer in a nitrogen (N2) and argon (Ar) ambient at a temperature of between 700° C. and 850° C.