Patent ID: 11880689
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. A non-transitory computer-readable storage medium storing a computer program, wherein the computer program, upon execution by a processor, is configured to cause the processor to:
in response to a completion of hardware power on, control a platform controller hub (PCH) to read BIOS (Basic Input Output System) codes from a BIOS flash memory via a first interface and running the BIOS codes;
detect whether bits of a register of the PCH have been set;
in response to the bits of the register of the PCH being set, control the PCH to send power-down completion information to a BMC (Baseboard Management Controller) via a second interface; and
in response to the BMC receiving the power-down completion information, record the power-down completion information in a BMC flash memory, and perform the hardware power on again until a test is completed.