Patent ID: 11881858
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 12:
13. A method for calibrating a clock duty cycle, comprising:
generating, by an oscillation circuit, a first oscillation signal and a second oscillation signal, wherein a frequency of the first oscillation signal is same as a frequency of the second oscillation signal, and a phase of the first oscillation signal is opposite to a phase of the second oscillation signal, and the first oscillation signal having an initial duty cycle;
receiving, by a comparison unit, the first oscillation signal and the second oscillation signal, and comparing a duty cycle of the first oscillation signal or a duty cycle of the second oscillation signal; and
controlling, by a logical unit, the oscillation circuit according to an output result of the comparison unit, so that the duty cycle of the first oscillation signal generated by the oscillation circuit changes from the initial duty cycle to a preset duty cycle;
wherein receiving, by the comparison unit, the first oscillation signal and the second oscillation signal comprises:
receiving, by a first input end of an integral unit of the comparison unit, the first oscillation signal when a turnover identification signal is at a low level, and receiving, by the first input end of the integral unit of the comparison unit, the second oscillation signal when the turnover identification signal is at a high level; and
receiving, by a second input end of the integral unit of the comparison unit, the second oscillation signal when the turnover identification signal is at the low level, and receiving, by the second input end of the integral unit of the comparison unit, the first oscillation signal when the turnover identification signal is at the high level.