Patent ID: 11943925
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 8:
9. A semiconductor memory device comprising:
a plurality of semiconductor patterns stacked in a first direction perpendicular to a top surface of a substrate, wherein each of the plurality of semiconductor patterns includes a source region having a first conductivity type, a drain region having a second conductivity type different from the first conductivity type, and a channel region between the source region and the drain region;
a pair of first and second word lines surrounding a channel region of each of the plurality of semiconductor patterns and extending lengthwise in the first direction;
a plurality of charge storage patterns, each surrounding a channel region of a corresponding semiconductor pattern of the plurality of semiconductor patterns, and being disposed between the corresponding semiconductor pattern and each of the pair of the first and second word lines;
a plurality of first conductive lines stacked in the first direction, each being connected to a drain region of a corresponding one of the plurality of semiconductor patterns; and
a second conductive line extending lengthwise in the first direction and connected in common to a plurality of source regions of the plurality of semiconductor patterns,
wherein the pair of first and second word lines are disposed between the source region and the drain region of each of the plurality of semiconductor patterns.