Patent ID: 11877434
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of forming an apparatus comprising a memory cell array comprising microelectronic devices, the method comprising:
forming at least one isolation trench in a silicon structure, the silicon structure comprising at least one dopant adjacent an upper surface of the silicon structure;
at least partially filling the at least one isolation trench with insulative material;
forming at least one opening within the insulative material in the at least one isolation trench;
forming conductive material within the at least one opening to form at least one lower elongate conductive structure within the at least one isolation trench;
exposing the silicon structure and the insulative material to an etching chemistry at a first bias voltage of greater than about 500 V, comprising vertically etching regions of the silicon structure adjacent the at least one isolation trench and vertically etching the insulative material within the at least one isolation trench to form at least one initial trench above the insulative material and between sidewalls of initial features formed in the silicon structure;
exposing at least the sidewalls of the initial features above the insulative material to the etching chemistry at a second bias voltage of less than about 100 V to remove material from the sidewalls to expand the at least one initial trench and form at least one broader trench above the insulative material and between features formed from the initial features without substantially reducing a height of the initial features; and
forming elongate conductive structures in the at least one broader trench and above the features,, whereby at least one of the microelectronic devices formed by the method comprises: whereby the features comprising silicon of the silicon structure, each feature of at least one pair of the features comprising:
a lower portion with a tapering sidewall adjacent the at least one broader trench at least partially filled with the insulative material; and
a fin portion above the lower portion, the fin portion comprising a sidewall defining a different slope above the insulative material than a slope of the tapering sidewall of the lower portion of the feature;
the elongate conductive structures above the features, the elongate conductive structures comprising portions laterally adjacent the fin portion of the each feature of the at least one pair of the features, the elongate conductive structures being arranged parallel to one another and parallel to a first horizontal axis;
doped features comprising the silicon in other regions not vertically etched during the exposure to the etching chemistry at the first bias voltage, the doped features comprising the at least one dopant, the doped features spacing the elongate conductive structures from one another along a second horizontal axis perpendicular to the first horizontal axis; and
within the at least one isolation trench, the at least one lower elongate conductive structure extending substantially perpendicular to the elongate conductive structures;
wherein:
the conductive material of the at least one lower elongate conductive structure comprises one or more of titanium (Ti), tungsten (W), ruthenium (Ru), cobalt (Co), an alloy of any of the foregoing, or one or more compounds or combinations of any of the foregoing,
the insulative material is interposed between the at least one lower elongate conductive structure and the lower portion of the feature, and
the doped features extend to a higher elevation than the fin portions of the features.