Patent ID: 11881254
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 14:
15. The enable control circuit according to claim 14, wherein the counting circuit comprises six second flip-flops, and the six second flip-flops are connected in sequence, wherein
a first output terminal of an ith second flip-flop of the six second flip-flops is configured to output an ith counting signal, wherein i is an integer greater than 0 and less than or equal to 6; and
the selection circuit is configured to: receive the first config signal, a fifth counting signal, and a sixth counting signal, and perform selection on the fifth counting signal and the sixth counting signal according to the first config signal to generate the target achievement signal, wherein two input terminals of the selection circuit are respectively connected to a first output terminal of a fifth second flip-flop of the six second flip-flops and a first output terminal of a sixth second flip-flop of the six second flip-flops.