Patent ID: 11862584
Assignee: NXP USA, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A semiconductor package device comprising:
a bottom carrier device comprising a first high-k glass substrate layer surrounding a first patterned ceramic layer in which a first waveguide region is located, a semiconductor die attached to a top surface of the first high-k glass substrate layer over a die region, and a first array of conductors formed on a top surface of the first patterned ceramic layer to define a waveguide ring positioned to substantially surround the first waveguide region and a separate excitation element positioned to extend from the die region to a first interior side of the first waveguide region to be substantially surrounded by the waveguide ring;
a top carrier device comprising a second high-k glass substrate layer surrounding a second patterned ceramic layer in which a second waveguide region is located and surrounded by a waveguide interface perimeter of one or more conductors that are positioned for alignment with the waveguide ring; and
an adhesive or bonding layer attaching the bottom carrier device to the top carrier device with the first waveguide region formed in the first patterned ceramic layer of the bottom carrier device aligned with the second waveguide region formed in the second patterned ceramic layer of the top carrier device.