Patent ID: 11899532
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. An apparatus, comprising:
one or more controllers configured to couple with a memory system, wherein the one or more controllers is configured to cause the apparatus to:
set a first timeout duration for a boot sequence of a host system;
set a second timeout duration for the boot sequence of the host system based at least in part on an increase in an operating age of a memory device above an age threshold, an increase in an average error rate of the memory device above an error threshold, an increase in a temperature of the memory device above a temperature threshold, modifying a power setting for the memory device, or any combination thereof;
transmit, to the memory device, an indication of the first timeout duration for the boot sequence; and
initialize the boot sequence to access a set of memory cells of the memory device that store information for the boot sequence based at least in part on the first timeout duration.