Patent ID: 11936893
Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
Field: Audio-visual technology (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A decoder comprising:
memory; and
circuitry coupled to the memory and configured to:
decode a bitstream obtained by dividing a slice into one or more data access regions in a variable-length decoding process; and
decode one or more offsets from a slice header, based on a flag written into a sequence header and a total number of the one or more data access regions, the one or more offsets each specifying a head position of a corresponding one of the one or more data access regions in the bitstream, wherein

when the flag indicates that the one or more offsets are to be decoded and the total number is at least two, the one or more offsets are decoded, and
the flag switches between decoding and not decoding the one or more offsets regardless of whether the total number is at least two.