Patent ID: 11948871
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. An integrated circuit (IC) comprising:
a silicon wafer having first and second surfaces, the second surface opposite the first surface;
a first conductive line having first and second surfaces, wherein the second surface is opposite the first surface, and the first surface of the first conductive line is coupled to the first surface of the silicon wafer;
a second conductive line having first and second surfaces, wherein the second surface is opposite the first surface, and the first surface of the second conductive line is coupled to the first surface of the silicon wafer;
a first insulation block having first and second portions, wherein the first portion has a first surface coupled to the first surface of the silicon wafer, and the second portion has a first surface coupled to the second surface of the first conductive line;
a second insulation block laterally spaced from the first insulation block and having third, fourth and fifth portions, wherein the third portion has a first surface coupled to the second surface of the first conductive line, the fourth portion has a first surface coupled to the first surface of the silicon wafer and other surfaces coupled to the first and second conductive lines, and the fifth portion has a first surface coupled to the second surface of the second conductive line;
a third insulation block laterally spaced from the second insulation block and having sixth and seventh portions, wherein the sixth portion has a first surface coupled to the second surface of the second conductive line, and the seventh portion has a first surface coupled to the first surface of the silicon wafer;
a first conductive pillar on the second surface of the first conductive line, and coupled to the second portion and to the third portion, wherein the first conductive pillar extends beyond the first and second insulation blocks;
a second conductive pillar on the second surface of the second conductive line, and coupled to the fifth portion and to the sixth portion, wherein, and the second conductive pillar extends beyond the second and third insulation blocks;
a capacitor having first and second capacitor terminals, wherein the first capacitor terminal is coupled to the second surface of the silicon wafer; and
a lead frame having first and second lead frame terminals, wherein the first and second respective lead frame terminals are connected to the first and second conductive pillars, respectively, using a conductive adhesive.