Patent ID: 11957068
Assignee: MICRON TECHNOLOGY, INC.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 14:
15. An apparatus, comprising:
a memory array comprising:
a first plurality of memory cells comprising first electrodes, second electrodes, and self-selecting storage elements having bulk regions and sidewall regions that separate respective bulk regions and respective second electrodes; and
a second plurality of memory cells comprising first electrodes, second electrodes, and second self-selecting storage elements having bulk regions that extend from the first electrodes of the second plurality of memory cells to the second electrodes of the second plurality of memory cells through sidewall regions of the second self-selecting storage elements, at least a portion of the sidewall regions of the second self-selecting storage elements extending between the bulk regions of the second self-selecting storage elements and the second electrodes of the second plurality of memory cells.