Patent ID: 11894043
Assignee: INTEGRATED SILICON SOLUTION INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. The power management circuit in the low-power double data rate memory of claim 8, wherein,
the first power network circuit comprises:
a plurality of first horizontal power lines arranged parallel to each other and extending in a first direction; and
a plurality of first vertical power lines arranged parallel to each other and extending in a second direction, wherein each of the first vertical power lines is connected to each of the first horizontal power lines, and the second direction is perpendicular to the first direction;

the second power network circuit comprises:
a plurality of second horizontal power lines arranged parallel to each other and extending in the first direction; and
a plurality of second vertical power lines arranged parallel to each other and extending in the second direction, wherein each of the second vertical power lines is connected to each of the second horizontal power lines; and

the second connecting point is separated from the first connecting point by the distance along one of the first direction and the second direction.