Patent ID: 11942154
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 15:
16. The nonvolatile memory device of claim 1, wherein the second semiconductor layer further comprises:
a voltage generator configured to generate a high voltage, word-line voltages, a turn-on voltage, and a turn-off voltage based on control signals;
a page buffer circuit coupled to the memory cell array through the plurality of bit-lines, the page buffer circuit configured to latch sensed data in a sensing operation; and
a control circuit configured to control the first address decoder, the second address decoder, the voltage generator, and the page buffer circuit based on a command and an address,
wherein the control circuit is configured to control the first address decoder, the second address decoder and the voltage generator to:
apply the high voltage to each gate of the plurality of first pass transistors and the plurality of second pass transistors,
apply the word-line voltages, the turn-on voltage, and the turn-off voltage to the plurality of first pass transistors, and
apply the turn-on voltage and the turn-off voltage to the plurality of second pass transistors.