Patent ID: 11967547
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A semiconductor structure, comprising:
a first substrate including a first surface and a second surface opposite to the first surface;
a first die disposed over the second surface of the first substrate;
a second die disposed over the second surface of the first substrate and adjacent to the first die;
a plurality of first conductive bumps disposed between the first substrate and the first die and between the first substrate and the second die;
a second substrate disposed below the first surface of the first substrate;
a plurality of second conductive bumps disposed between the first substrate and the second substrate;
a multi-tiered solder-resist structure disposed on the second substrate and arranged between the plurality of second conductive bumps, the multi-tiered solder-resist structure having different widths at different heights over the second substrate and contacting sidewalls of the plurality of second conductive bumps to separate the plurality of second conductive bumps from one another;
a first underfill material disposed over the first substrate and surrounding the plurality of first conductive bumps; and
a second underfill material disposed over the second substrate and surrounding the plurality of second conductive bumps.