Patent ID: 11965919
Assignee: ZHEJIANG UNIVERSITY
Field: Measurement (Instruments)
Classification: CPC G  H | IPC G

Claim 3:
4. A phase frequency detector-based high-precision feedback frequency measurement method, comprising the following steps:
(1) roughly measuring a measured signal fx by an equal-precision frequency measurement method in the FPGA (3);
(2) determining a reference clock Fclk of the DDS (4) and phase accumulator bit number N according to a result fc roughly measured in step (1), obtaining a control word M of the DDS (4) through the following formula, directly synthesizing a reference signal fx′ according to a frequency control word M by the DDS (4), and outputting a rough measurement completion signal flag=1;

M=(2N×fc)/Fclk 

(3) connecting the measured signal fx and the signal fx′ directly synthesized by the DDS (4) obtained in step (2) to the phase frequency detector (5) for performing phase frequency detection;
(4) connecting an output end of the phase frequency detector (5) in step (3) to the charge pump (6), then converting a frequency and phase difference between two signals into a voltage value after passing through the low-pass filter circuit (7) and the A/D converter (8), and then transmitting the voltage value to the FPGA (3);
(5) calculating a frequency difference between the two signals obtained in step (4) according to a relationship between the frequency f and the phase p in the following formula, performing negative feedback adjustment on the control word M of the DDS (4) according to the frequency difference, performing a precise measurement process to output a precisely measured frequency value, and setting the rough measurement completion signal as zero flag=0;

p=∫fdt 

wherein the negative feedback adjustment is that: after the FPGA (3) receives the frequency difference Δf between the measured signal fx and the fx′ directly synthesized by the DDS (4) converted and processed by the phase frequency detector (5), the charge pump (6), the low-pass filter circuit (7), and the A/D converter (8), converting the frequency difference Δf into a variable quantity ΔM of the control word of the DDS (4) to adjust the fx′, and continuing to compare the frequency difference between the fx′ and the measured signal fx by using the phase frequency detector (5) until reaching a stable state, that is, fx′=fx, and outputting the measurement result at this moment by the FPGA (3).