Patent ID: 11877432
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of preparing a capacitor structure, comprising:
providing a substrate, the substrate comprising a conductive contact region and an insulating region which are spaced apart;
forming a stacked layer on the substrate, the stacked layer comprising a plurality of units which are superposed and a main dielectric layer located between adjacent two units of the plurality of units, and each of the plurality of units comprising a conductive layer, the main dielectric layer, and a sacrificial layer;
forming a plurality of first via holes penetrating through the stacked layer, the plurality of first via holes corresponding to the conductive contact region and exposing a part of an upper surface of the conductive contact region;
removing a part of the sacrificial layer of a sidewall of the plurality of first via holes to form a first groove in a corresponding region of the sacrificial layer of the sidewall of the plurality of first via holes;
forming a first supplementary dielectric layer in the first groove;
filling the plurality of first via holes with a conductive material to form a conductive pillar, the conductive pillar being connected with the conductive layer, and the conductive pillar being connected with the conductive contact region;
forming a plurality of second via holes penetrating through the stacked layer at a preset radius with the conductive pillar as an axis, the plurality of second via hole surrounding the conductive pillar circumferentially, the plurality of second via holes corresponding to the insulating region and exposing a part of an upper surface of the insulating region, and the conductive pillar and the conductive layer connected with the conductive pillar together forming a columnar bottom electrode with a first gear;
removing a part of the conductive layer of a sidewall of the plurality of second via holes to form a second groove in a corresponding region of the conductive layer of the sidewall of the plurality of second via holes;
forming a second supplementary dielectric layer in the second groove, the main dielectric layer, the first supplementary dielectric layer, and the second supplementary dielectric layer covering the columnar bottom electrode;
removing all the sacrificial layer of the sidewall of the plurality of second via holes; and
filling the plurality of second via holes with the conductive material to form an annular top electrode with a second gear.