Patent ID: 11869843
Assignee: KEPLER COMPUTING INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 8:
9. The method of claim 1, wherein the via electrode is a first via electrode, the memory device is a first memory device, wherein etching the material layer stack further comprises forming a second memory device on a first plane behind the first memory device on a second plane, wherein the contact electrode is a first contact electrode and wherein the hanging trench is a first hanging trench, wherein the second process further comprises:
forming a second hanging trench above the second memory device;
forming the mask in the second hanging trench, the mask providing a third opening that exposes a portion of the second dielectric;
etching the second dielectric through the third opening to form a third via opening, the third via opening exposing the second memory device;
depositing the second conductive hydrogen barrier layer on the second memory device in the third via opening and in the second hanging trench; and
planarizing to form a second via electrode in the third via opening, and form a second contact electrode in the second hanging trench on the second via electrode.