Patent ID: 11948798
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for manufacturing an integrated circuit, the method comprising:
forming a first layer;
forming a first patterned mask, the first patterned mask having a first line pattern and a second line pattern;
forming a second patterned mask over an upper surface of the first patterned mask, the second patterned mask having an opening, the opening exposing a region between the first line pattern and the second line pattern of the first patterned mask;
depositing a first gap-filling material along sidewalls of the opening;
depositing a second gap-filling material over the first gap-filling material within the opening, the second gap-filling material being different from the first gap-filling material;
removing the second patterned mask; and
patterning the first layer using the second gap-filling material as a mask.