Patent ID: 11929425
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 7:
8. A semiconductor device comprising:
a substrate;
a plurality of nano structures over the substrate;
a gate structure over the plurality of nano structures, the gate structure comprising a gate dielectric and a gate electrode, the gate structure being interposed between adjacent ones of the plurality of nano structures;
an outer spacer laterally adjacent the gate structure;
inner spacers adjacent the gate structure, each of the inner spacers being interposed between adjacent ones of the plurality of nano structures, the inner spacers extending below the outer spacers, wherein an upper inner spacer of the inner spacers extends along a vertical sidewall of the outer spacer; and
a first source/drain region and a second source/drain region on opposing ends of the plurality of nano structures.