Patent ID: 11950428
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. The memory device of claim 10, in a cross-section of the memory device along the first direction,
wherein the first insulating layers comprised in each of the plurality of first stacking structures each comprises a first side, and the first gate layers comprised in each of the plurality of first stacking structures each comprises a second side, wherein the first sidewalls are aligned to each other, the second sidewalls are aligned to each other, and the first sidewalls are offset from the second sidewalls,
wherein the second insulating layers comprised in each of the plurality of second stacking structures each comprises a third side, and the second gate layers comprised in each of the plurality of second stacking structures each comprises a fourth side, wherein the third sidewalls are aligned to each other, the fourth sidewalls are aligned to each other, and the third sidewalls are offset from the fourth sidewalls.