Patent ID: 11877439
Assignee: INVENTION AND COLLABORATION LABORATORY PTE. LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. An IC system, comprising:
a package;
a plurality of base memory chips enclosed in the package, each base memory chip comprising a memory region and a bridge area, the memory region of each base memory chip comprising a plurality of memory cells and each memory cell comprising a first transistor, and the bridge area of each base memory chip comprising a plurality of memory input/output (I/O) pads and a plurality of third transistors; and
a logic chip physically separated from the plurality of base memory chip and enclosed in the package, the logic chip comprising a logic bridge area and a plurality of second transistors, the logic bridge area comprising a plurality of logic I/O pads;
wherein the plurality of base memory chips and the logic chip are configured above a substrate, each base memory chip is horizontally spaced apart from the logic chip, and the plurality of memory I/O pads of each base memory chip are electrically coupled to the plurality of logic I/O pads;
wherein a voltage level of a signal to or from the third transistor is the same or substantially the same as a voltage level of a signal to or from the second transistor.