Patent ID: 11948888
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor device, comprising:
a plurality of gate structures on a semiconductor substrate,
a plurality of source/drain impurity layers in the semiconductor substrate on opposite sides of each gate structure of the plurality of gate structures;
a plurality of metal contact patterns connected to the plurality of gate structures and the plurality of source/drain impurity layers;
an etch stop layer covering top surfaces of the plurality of metal contact patterns and top surfaces of the plurality of gate structures;
an interlayer dielectric layer on the etch stop layer; and
a contact plug penetrating the interlayer dielectric layer and the etch stop layer and connected to one metal contact pattern of the plurality of metal contact patterns,
wherein:
the etch stop layer includes a sequentially stacked first insulation layer, second insulation layer, and third insulation layer,
the first insulation layer, second insulation layer, and third insulation layer include different insulating materials from each other,
the first insulation layer directly contacts top surfaces of the plurality of metal contact patterns and top surfaces of the plurality of gate structures,
a thickness of the third insulation layer is greater than a thickness of the second insulation layer and a thickness of the first insulation layer,
the semiconductor substrate includes a first region and a second region,
the third insulation layer includes a first portion on the first region and a second portion on the second region,
the first portion has a first thickness and the second portion has a second thickness greater than the first thickness, and
the first thickness is greater than a thickness of the second insulation layer.