Patent ID: 11892948
Assignee: EDGEQ, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 12:
13. A non-transitory computer-readable medium or media comprising one or more sequences of instructions which, when executed by at least one processor, causes steps for data packet processing comprising:
learning, at a fast path enabler, architecture information about a system-on-a-chip (SoC), the SoC comprises multiple clusters with each cluster comprising multiple cores;
communicating, from a packet dispatcher thread, to the fast path enabler resource allocation information of the SoC regarding a packet processing agent to be involved in data packet sharing; and
based on the learned architecture information and the resource allocation information for the packet processing agent, pre-fetching, by the fast path enabler, one or more packets from a memory into a common cache, identified among multiple common caches in the SoC based on the learned architecture information and the resource allocation information, in a preparation for running the packet processing agent.