Patent ID: 11861177
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus, comprising:
a memory device; and
a controller coupled with the memory device and configured to cause the apparatus to:
receive, from a host device, a command indicating a target level of reliability associated with a set of data stored in the memory device, wherein the command indicates a request to perform one or more error management operations for the set of data based at least in part on the target level of reliability;
determine, based at least in part on the command, the target level of reliability from a plurality of target levels of reliability corresponding to a plurality of respective one or more error management operations comprising the one or more error management operations, wherein the target level of reliability corresponds to the one or more error management operations of the plurality of respective one or more error management operations;
perform the one or more error management operations for the set of data based at least in part on the target level of reliability; and
transmit, to the host device in response to the command, an indication of a level of reliability associated with the set of data based at least in part on performing the one or more error management operations.