Patent ID: 11914417
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory, comprising:
a control chip; and
a plurality of storage chips, wherein the plurality of storage chips are electrically connected with the control chip via a common communication channel, the plurality of storage chips are configured to perform information interaction with the control chip by adopting different clock edges of a first clock signal, the first clock signal has a first clock cycle, the different clock edges comprise at least one of two consecutive rising edges or two consecutive falling edges, the plurality of storage chips are further configured to receive a second clock signal and distinguish the different clock edges based on the second clock signal, and a second clock cycle of the second clock signal is greater than the first clock cycle,
wherein the different clock edges comprise a first rising edge, a first falling edge, a second rising edge and a second falling edge that are consecutive; and the plurality of storage chips comprise a first storage chip set and a second storage chip set;
wherein the first storage chip set comprises a first storage chip and a second storage chip, the first storage chip performs information interaction with the control chip at the first rising edge, and the second storage chip performs information interaction with the control chip at the first falling edge; and the second storage chip set comprises a third storage chip and a fourth storage chip, the third storage chip performs information interaction with the control chip at the second rising edge, and the fourth storage chip performs information interaction with the control chip at the second falling edge.