Patent ID: 11961552
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. A memory device comprising:
a first wafer including a logic structure and a cell structure disposed under the logic structure,
a cell region disposed in the cell structure, and including a plurality of memory blocks, which are coupled to a plurality of bit lines that extend in a first direction and that are arranged in a second direction;
a pass transistor circuit, disposed in the logic structure, that is configured to transfer an operating voltage to the plurality of memory blocks in response to a block selection signal; and
a block switch circuit included in a second wafer, which overlaps with the first wafer in a vertical direction, that is configured to provide the block selection signal to the pass transistor circuit,
wherein each memory block is divided into a plurality of sub-blocks each including a plurality of partial pages that are disposed in a plurality of rows arranged in the first direction.