Patent ID: 11966335
Assignee: GOOGLE LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A system comprising:
a host device and an accelerator communicatively coupled over a hardware interconnect supporting memory-coherent data transmission between the host device and the accelerator, the host device comprising a host cache and the accelerator comprising an accelerator cache;
wherein the host device is configured to:
read or write data to one or more data buffers to a first memory device shared between the host device and the accelerator,
write control information to a second computing device, the control information comprising one or more flags indicating the status of one or more data buffers in the first memory device,

wherein the accelerator is configured to:
non-coherently read or write data from or to the one or more data buffers of the first memory device based on the control information, and after non-coherently reading or writing the data, coherently write updated control information to the second memory device, wherein coherently writing the updated control information causes the control information in the host cache to be updated,

wherein the accelerator is further configured to receive, at an enqueue register, one or more command descriptors, each command descriptor specifying a respective data descriptor in the accelerator cache, and
wherein to non-coherently read or write data from or to the one or more data buffers, the accelerator is configured to read addresses from the one or more command descriptors corresponding to the one or more data descriptors.