Patent ID: 11935924
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A semiconductor device, comprising:
a substrate including a first region and a second region;
a device isolation layer that defines a first active area on the first region and a second active area on the second region;
a pair of first source/drain patterns and a pair of second source/drain patterns on the first active area and the second active area, respectively, the first source/drain patterns being spaced apart in a first direction;
a first channel pattern and a second channel pattern, the first channel pattern being between members of the pair of first source/drain patterns, the second channel pattern being between members of the pair of second source/drain patterns, and each of the first and second channel patterns including first, second, and third semiconductor patterns that are sequentially stacked on the substrate;
first, second, and third support patterns on the first active area, the first support pattern between the substrate and the first semiconductor pattern, the second support pattern between the first semiconductor pattern and the second semiconductor pattern, and the third support pattern between the second semiconductor pattern and the third semiconductor pattern;
a first gate electrode and a second gate electrode on the first channel pattern and the second channel pattern, respectively;
a first gate dielectric layer and a second gate dielectric layer, the first gate dielectric layer between the first channel pattern and the first gate electrode, and the second gate dielectric layer between the second channel pattern and the second gate electrode;
a pair of gate spacers on opposite sides of each of the first and second gate electrodes;
a gate capping pattern on a top surface of each of the first and second gate electrodes;
a plurality of active contacts electrically connected to the first and second source/drain patterns;
a plurality of gate contacts electrically connected to the first and second gate electrodes;
a first metal layer on the active contacts and the gate contacts, the first metal layer including a plurality of first lines electrically connected to the active contacts and the gate contacts; and
a second metal layer on the first metal layer,
wherein a length of the first channel pattern is greater than a length of the second channel pattern,
at least one selected from the first, second, and third support patterns has a crooked sidewall, and
wherein the first gate electrode includes a first sgment and a second segment that are between the two vetically adjacent first semiconductor patterns, and the first support pattern is between the first segment and the second segment in the first direction.