Patent ID: 11908514
Assignee: STMICROELECTRONICS S.R.L.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A non-volatile memory device, comprising:
a memory array including a plurality of memory portions, each memory portion comprising a respective plurality of memory cells arranged in rows and columns, wherein the memory portions are arranged in groups, each group of memory portions comprising a plurality of respective memory portions arranged in a row and a plurality of respective wordlines that extend through the respective memory portions, and wherein the memory cells of the memory portions of the group are coupled to the respective wordlines; and
a row decoder comprising a pre-decoding stage configured to execute a selection, in which it selects a wordline that extends through a group of memory portions and deselects other wordlines that extend through the group of memory portions, and a subsequent deselection, in which it deselects all the wordlines that extend through the group of memory portions, the row decoder further comprising, for each group of memory portions:
a shared pull-up stage configured to decouple from or couple to a node at a first reference potential each wordline that extends through the group of memory portions, when the wordline is respectively selected or deselected, to impose on each wordline, when deselected, a deselection voltage,
a plurality of pull-down stages distributed along the group of memory portions, each pull-down stage being configured to locally couple each wordline that extends through the group of memory portions, when selected, to a node at a second reference potential, to impose locally a selection voltage on the wordline, wherein each pull-down stage is further configured to locally decouple from the node at the second reference potential each wordline that extends through the group of memory portions, when deselected, and
a number of local pull-up stages distributed along the group of memory portions, each local pull-up stage comprising, for each wordline that extends through the group of memory portions, a corresponding local pull-up transistor of an NMOS type, wherein the local pull-up transistors of each local pull-up is being configured to:
locally decouple the corresponding wordline from the node at the first reference potential when one of the wordlines that extend through the group of memory portions is selected; and
locally couple the corresponding wordline to the node at the first reference potential when all the wordlines that extend through the group of memory portions are deselected to restore locally the deselection voltage on the wordline previously selected.