Patent ID: 11955462
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A device, comprising:
a redistribution layer having a first side opposite a second side, the redistribution layer having a lateral width;
a first die on the first side of the redistribution layer, the first die having an uppermost surface, a bottommost surface, a first side surface and a second side surface between the uppermost surface and the bottommost surface, the second side surface opposite the first side surface;
a molding on the first side of the redistribution layer, the molding laterally adjacent to and in contact with the first side surface and the second side surface of the first die, the molding having an uppermost surface co-planar with the uppermost surface of the first die, and the molding having a lateral width the same as the lateral width of the redistribution layer;
a first through mold via in the molding and laterally spaced apart from the first side surface of the first die;
a second through mold via in the molding and laterally spaced apart from the second side surface of the first die;
a dielectric layer over the molding and the first die, the dielectric layer having a lateral width the same as the lateral width of the molding, and the dielectric layer having an uppermost surface;
a second die in the dielectric layer, the second die directly electrically connected to the first through mold via and to the second through mold via, the second die having an uppermost surface co-planar with the uppermost surface of the dielectric layer; and
a plurality of solder balls on the second side of the redistribution layer.