Patent ID: 11935749
Assignee: NANYA TECHNOLOGY CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A method of manufacturing a semiconductor structure, comprising:
forming a first oxide layer over a substrate, wherein the first oxide layer includes an opening exposing the substrate;
forming a nitride layer in the opening, wherein the nitride layer lines sidewalls of the first oxide layer and a portion of a top surface of the substrate in the opening;
forming a second oxide layer in the opening, wherein the second oxide layer is separated from the substrate and the first oxide layer by the nitride layer, and top surfaces of the first oxide layer, the second oxide layer and the nitride layer are coplanar;
removing a portion of the nitride layer lining the sidewalls of the first oxide layer, thereby forming a rounded top surface of the second oxide layer and a rounded top surface of the first oxide layer;
forming a third oxide layer over the first oxide layer and the second oxide layer without filling a gap between the first oxide layer and the second oxide layer; and
performing an etching until an exposure of the gap, thereby forming a planar top surface of the first oxide layer and a planar top surface of the second oxide layer.