Patent ID: 11908702
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A method, comprising:
forming first and second fin structures on a substrate;
forming first and second gate openings on the first and second fin structures, respectively;
forming a first dielectric layer with first and second layer portions formed within the first and second gate openings, respectively;
selectively doping the first layer portion with first dopants, wherein the first dopants have an electronegativity value greater than an electronegativity value of a metal or a semiconductor of the first dielectric layer;
selectively doping the second layer portion with second dopants different from the first dopants, wherein the second dopants have an electronegativity value less than an electronegativity value of the metal or the semiconductor of the first dielectric layer;
forming a second dielectric layer with first and second layer portions on the first and second layer portions of the first dielectric layer; and
forming first and second gate metal fill layers over the first and second layer portions of the second dielectric layer, respectively.