Patent ID: 11893393
Assignee: TESLA, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A microprocessor system, comprising:
a computational array that includes a plurality of computation units, wherein each of the plurality of computation units operates on a corresponding value addressed from memory, and wherein the computational array is configured to perform a convolution operation associated with weight data and input data; and
a hardware arbiter configured to manage memory requests, wherein the hardware arbiter is configured to queue a first portion of the memory requests in a first queue corresponding to weight data and a second portion of the memory requests in a second queue corresponding to input data, wherein the hardware arbiter is configured to prioritize a first individual memory request from one of the first queue and second queue over a second individual memory request from the other of the first queue and second queue, and wherein the second individual memory request was received earlier than the first individual memory request,
wherein the hardware arbiter is in communication with a control queue configured to queue operations, and wherein the hardware arbiter is configured to trigger a particular operation of one or more computation units in the plurality of computation units on a subset of the corresponding values based on the hardware arbiter granting memory access for the subset of the corresponding values.