Patent ID: 11923020
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device comprising:
a plurality of memory cell transistors configured to store a plurality of bit data, respectively;
a first word line connected to a plurality of first memory cell transistors among the plurality of memory cell transistors;
a controller configured to perform a loop process including repetition of a program loop, the program loop including a program operation and a first verification operation; and
a storage circuit configured to store status information,
wherein the controller is configured to:
perform the loop process, and then perform a second verification operation, and
store first status data relating to a result of the loop process and store second status data relating to a result of the second verification operation in the storage circuit, in a write operation using the plurality of first memory cell transistors as targets.