Patent ID: 11908533
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. The memory device of claim 7, wherein, during the first time interval, the first block selecting circuit is configured to float the first driving line from the first word line, and the driving line driver is configured to float the first driving line from a second voltage,
wherein, during the second time interval, the first block selecting circuit is configured to electrically connect the first driving line to the first word line, and the driving line driver is configured to precharge the first driving line with the second voltage, and
wherein, during the third time interval, the first block selecting circuit is configured to electrically connect the first driving line to the first word line, and the driving line driver is configured to float the first driving line from the second voltage.