Patent ID: 11894425
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A method of forming a semiconductor arrangement, comprising:
forming a gate dielectric layer over a semiconductor layer;
forming a gate electrode layer over the gate dielectric layer;
forming a first gate mask over the gate electrode layer;
etching the gate electrode layer using the first gate mask as an etch template to form a first gate electrode;
implanting a first dopant into the semiconductor layer using the first gate mask and the first gate electrode as an implantation template to form a first doped region in the semiconductor layer;
forming a first sidewall spacer adjacent the first gate electrode after implanting the first dopant; and
implanting a second dopant using the first sidewall spacer and the first gate electrode as an implantation template to form a second doped region in the semiconductor layer, wherein:
the first doped region extends to a first depth below a top surface of the semiconductor layer,
the second doped region extends to a second depth below the top surface of the semiconductor layer, and
the second depth is less than the first depth.