Patent ID: 11886727
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 3:
4. The memory system according to claim 1, wherein
the controller is configured to:
construct, when a difference between the number of defective blocks included in a die or plane having a smallest number of defective blocks among the plurality of dies or the plurality of planes and the number of defective blocks included in a die or plane having a largest number of defective blocks among the plurality of dies or the plurality of planes is equal to or less than one, the plurality of block groups using the first type block group; and
construct, when a difference between the number of the defective blocks included in the die or plane having the smallest number of defective blocks and the number of the defective blocks included in the die or plane having the largest number of defective blocks is equal to or more than two, the plurality of block groups using the first type block group and the second type group.