Patent ID: 11907005
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G  H

Claim 18:
19. A clock management circuit comprising:
a synchronization circuit configured to generate a clock gating signal that is activated to control a clock gating period when a frequency of at least one of a plurality of core clock signals provided to a plurality of processor cores of a multi-core system is changed;
a plurality of clock switching circuits configured to a plurality of switching clock signals by selecting one of a first clock signal having a first frequency and a second clock signal having a second frequency different from the first frequency;
a plurality of core clock gating circuits configured to generate the plurality of core clock signals respectively corresponding to the plurality of switching clock signals by deactivating the plurality of switching clock signals in the clock gating period based on the clock gating signal; and
an interface clock gating circuit configured to generate an interface clock signal provided to a function block of the multi-core system by deactivating the second clock signal in the clock gating period based on the clock gating signal.