Patent ID: 11909401
Assignee: UNIVERSITY OF WASHINGTON
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A self-clocked dynamic comparator, comprising:
a latch configured to receive an input voltage (VIN), a reference voltage (VREF) and a clocking (CLKsf) signal, and configured to output a first rail-to-rail output (OUT+) signal and a second rail-to-rail output (OUT−) signal;
a pre-amplifier (PRE-AMP) configured to output an enable (TRI) signal based on a comparison between the VIN and an adjusted VREF; and
a logic gate configured to receive the TRI signal and one of the OUT+ signal and OUT− signal, and configured to output the CLKsf signal,
wherein cycles of the CLKsf signal control operation of the comparator and a power dissipation of the comparator.