Patent ID: 11862724
Assignee: APOGEE SEMICONDUCTOR, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 4:
5. A method of fabricating a radiation-hardened NMOS device, comprising the steps of:
providing a silicon substrate having a surface that is lightly doped p-type;
forming a field oxide in the surface of the substrate, patterned to define an active region having a boundary within which the field oxide is absent and along which the field oxide has an edge, the active region having a total length between two ends in a length direction, and a total width between a first boundary side and a second boundary side in a width direction orthogonal to the length direction;
growing a gate oxide in the active region;
depositing a polysilicon gate layer;
patterning and etching the polysilicon gate layer to form at least one gate having two sidewalls and a gate length between the two sidewalls in the length direction, the at least one gate crossing the total width of the active region and crossing each of the first boundary side and the second boundary side of the active region, a parasitic edge channel formed along the field oxide edge where each gate crosses over each of the first boundary side and the second boundary side, each parasitic edge channel having an edge channel length;
patterning and doping a partially pulled-back n-type source/drain diffusion region using a pattern that excludes N+ doping from a gap region, wherein a segment of a border of the diffusion region having two segment ends on opposite sides of the gate, the segment crossing the gate proximate a parasitic edge channel, has a length between the two segment ends at least as long as the edge channel length and shorter than the total length of the active region, and wherein at least one of the two segment ends is separated by at least a predetermined nonzero distance from the nearest end of the active region, the segment of the border displaced from the field oxide edge toward the center of the active region along the width direction by a gap width g, and wherein the gap region is bounded by the at least one gate, the active region boundary, and the border of the n-type diffusion region;
forming an n-type lightly-doped drain structure along at least one sidewall of the gate using a pattern that excludes n-type doping from the gap region; and
completing fabrication of the radiation-hardened NMOS device.