Patent ID: 11869811
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor device comprising:
a device isolation layer provided on a substrate, the device isolation layer defining a first sub-active pattern and a second sub-active pattern, the first and second sub-active patterns extending in a first direction and spaced apart from each other in the first direction;
a first gate electrode and a second gate electrode crossing the first sub-active pattern and the second sub-active pattern, respectively; and
an isolation structure provided on the device isolation layer between the first and second sub-active patterns,
wherein the device isolation layer includes a diffusion break region disposed between the first and second sub-active patterns,
wherein the isolation structure covers a top surface of the diffusion break region,
wherein the isolation structure comprises:
an isolation pattern extending in a second direction crossing the first direction; and
isolation spacers provided on both sidewalls of the isolation pattern, respectively,
wherein the gate electrodes and the isolation pattern are formed of different materials from each other, and
wherein the isolation pattern has a first width that is the maximum width in the first direction, the diffusion break region has a second width that is the maximum width in the first direction, and the second width is greater than the first width.