Patent ID: 11899975
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. An apparatus, comprising:
a non-volatile memory;
a volatile memory configured to operate as a cache for the non-volatile memory; and
an interface controller coupled with the non-volatile memory and the volatile memory, the interface controller configured to cause the apparatus to:
receive a first command from a host device;
communicate the first command to a machine learning engine and to circuitry configured to store and manage commands for the non-volatile memory and the volatile memory, wherein the machine learning engine is configured to:
determine a page open operation or a page close operation based at least in part on the first command and information determined by the machine learning engine during a training mode; and
communicate a second command generated by the machine learning engine to the circuitry, wherein the second command based at least in part on the information determined by the machine learning engine during the training mode, and wherein the second command is associated with the page open operation or the page close operation.