Patent ID: 11908543
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 15:
16. A semiconductor apparatus comprising:
a memory cell array configured to store normal data;
a control circuit configured to generate control signals including multi-phase clock signals in response to an external clock signal and configured to output internally stored state information in response to a state information read command;
an input/output pad unit; and
a transmission circuit configured to:
generate output signals by detecting levels of each of the normal data, which are input through a plurality of differential input terminals, according to each of a rising edge and a falling edge of control clock signals and to output the output signals to an external device through the input/output pad unit during a normal read operation, and
generate the output signals by detecting a level of state information, which is input through the plurality of differential input terminals, in response to the control clock signals and to output the output signals to an external device through the input/output pad unit during a state information read operation,
wherein the control clock signals transits repeatedly during the normal read operation, and the control clock signals are fixed to a first logic level during the state information read operation.