Patent ID: 11907680
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 23:
24. The MAC operator of claim 23, wherein the output circuit includes:
a first buffer that receives the exponent upper data of the MAC data and outputs the exponent upper data of the MAC data in response to the MAC read signal of a first logic level;
a second buffer that receives the mantissa data of the MAC data and outputs the mantissa data of the MAC data in response to the MAC read signal of the first logic level;
a second normalizer that performs second normalization processing on the mantissa data of the MAC data to generate and output sign data, exponent lower data, and mantissa data of a standard format of the MAC data; and
a bit joining circuit that joins the exponent upper of the MAC data from the first buffer, the sign data of the MAC data from the second normalizer, and the mantissa data of the standard format to output the joined data as the MAC result data.