Patent ID: 11899589
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. A system comprising:
a host;
a host memory coupled to the host;
a device coupled to the host using_an interconnect; and
a device memory coupled to the device;
wherein the host is configured to maintain coherency between the host memory and the device memory; and
wherein the device is configured to select a coherency bias for a page of the device memory based on an access pattern of the page of the device memory:,
wherein the system further comprises bias management logic configured to:
monitor a first access, by a first apparatus, of a page of the device memory;
monitor a second access, by a second apparatus, of the page of the device memory;
modify, based on the first access and the second access, an indication;
determine, based on the indication, an access pattern of the page of the device memory; and
select, based on the access pattern, a coherency bias for the page of the device memory.