Patent ID: 11916567
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A sample-and-hold circuit, comprising:
a first resistor having a first terminal and a second terminal wherein the second terminal is coupled to a first current source;
a second resistor having a first terminal and a second terminal wherein the second terminal is coupled to a second current source;
a first transistor having a control terminal, a first current terminal and a second current terminal, wherein the first current terminal is coupled to the second terminal of the first resistor;
a second transistor having a control terminal, a first current terminal and a second current terminal, wherein the first current terminal is coupled to the second current terminal of the first transistor and the second terminal of the second transistor is coupled to the second terminal of the second resistor;
a third resistor having a first terminal and a second terminal wherein the second terminal is coupled to a third current source;
a fourth resistor having a first terminal and a second terminal wherein the second terminal is coupled to a fourth current source;
a third transistor having a control terminal, a first current terminal and a second current terminal, wherein the first current terminal is coupled to the second terminal of the third resistor;
a fourth transistor having a control terminal, a first current terminal and a second current terminal, wherein the first current terminal is coupled to the second current terminal of the third transistor and the second terminal of the second transistor is coupled to the second terminal of the fourth resistor;
a first capacitor having a first terminal and a second terminal wherein the first terminal is coupled to the second current terminal of the first transistor and the second terminal is coupled to ground; and
a second capacitor having a first terminal and a second terminal wherein the first terminal is coupled to the second current terminal of the third transistor and the second terminal is coupled to ground;
wherein the control terminals of the first and third transistors are coupled together, the control terminals of the second and fourth transistors are coupled together, and the control terminals are controlled by the complementary signals.