Patent ID: 11961579
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 14:
15. A computing system, comprising:
a memory device including:
a complementary metal-Oxide-semiconductor (CMOS) wafer including sense amplifier circuitry and sub word driver circuitry; and
a memory cell wafer bonded to the CMOS wafer, the memory cell wafer including primary bit lines and secondary bit lines, each of the secondary bit lines extending in parallel proximate to a corresponding one of the primary bit lines, a cross intersection of a first primary bit line of the primary bit lines with a first secondary bit line of the secondary bit lines located proximate to a parity intersection of a second primary bit line of the primary bit lines with a second secondary bit line of the secondary bit lines, the first primary bit line adjacent to the second primary bit line.