Patent ID: 11934700
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. A storage device, comprising:
a memory including a plurality of data structures, wherein each of the data structures is associated with a different submission queue; and
one or more processors coupled to the memory, the one or more processors, individually or in combination, configured to:
receive a first command for a fused operation from one of the different submission queues, the first command indicating a first logical address range,
store the first command in one of the data structures,
receive a second command for the fused operation from the one of the different submission queues, the second command indicating a second logical address range,
determine whether the second command corresponds to the fused operation and whether the first logical address range is same as the second logical address range,
store the second command in the one of the data structures in response to determining that the second command corresponds to the fused operation and that the first logical address range is the same as the second logical address range, and
perform the fused operation in response to storing the second command.