Patent ID: 11922566
Assignee: IMAGINATION TECHNOLOGIES LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 4:
5. The coarse depth test hardware of claim 1, wherein the front depth test logic is further configured to:
maintain a record of each pixel sample in the tile for which a best depth value is available;
in response to determining that a primitive fragment has better depth than the primitives previously processed for the tile:
determine whether the record indicates that the best depth value is available for the pixel sample in the tile associated with that primitive fragment,
in response to determining that the record indicates that the best depth value is not available for the pixel sample in the tile associated with that primitive fragment, identify the primitive fragment as not requiring a full resolution depth test, and
update the record to indicate that the best depth value is available for the pixel sample in the tile associated with that primitive fragment; and

if a primitive fragment is not identified as not requiring a read of the depth buffer to perform full resolution depth testing, updating the record to indicate that the best depth value is available for each pixel sample of the tile.