Patent ID: 11894388
Assignee: HKC CORPORATION LIMITED
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A display panel, comprising:
an array substrate;
a contralateral substrate, arranged opposite to the array substrate; and
a liquid crystal layer, sandwiched between the array substrate and the contralateral substrate;
wherein the array substrate is fabricated by the following operations:
forming a gate metal layer and a gate insulating layer on a first surface of a glass substrate;
forming a semiconductor layer on a first surface of the gate insulating layer, and forming an etching stop layer at a position corresponding to a channel of a thin film transistor;
forming a metal layer on a first surface of the etching stop layer;
depositing a layer of photoresist on a first surface of the metal layer, the photoresist covering the metal layer and the position of the channel, and performing one mask manufacturing process on the photoresist to form a photoresist layer of a preset shape through exposure and development, the photoresist layer of the preset pattern covering a source and a drain of the thin film transistor and not covering the etching stop layer corresponding to the position of the channel;
etching the metal layer to obtain the source and the drain of the thin film transistor, wherein during the process of etching the metal layer thus forming the source and the drain of the thin film transistor, the semiconductor layer disposed under the metal layer is left intact without being etched, and the photoresist layer of the preset pattern is not peeled off after the metal layer has been etched to form the source and the drain;
post-baking the photoresist layer of the preset pattern remained on first surfaces of the source and the drain to melt, allowing a portion of the photoresist layer of the preset pattern to flow to the position of the channel and again cover up the etching stop layer at the position of the channel, and allowing a remaining portion of the photoresist layer of the preset pattern to remain on the first surfaces of the source and the drain, leaving the source, the drain and the etching stop layer all covered up by the photoresist;
etching the semiconductor layer to form a preset pattern;
peeling off the photoresist layer on the first surfaces of the source, the drain, and on a first surface of the etching stop layer at the position of the channel; and
forming a passivation layer and an ITO layer on the first surfaces of the source, the drain, and the position of the channel;
wherein a width of the etching stop layer is greater than a width of the channel between the source and the drain;
wherein portions of the source and the drain adjacent to the channel are formed on the first surface of the etching stop layer;
wherein the gate metal layer has a greater width than that of the semiconductor layer, and wherein both ends of the gate metal layer along the width thereof extend beyond the respective two ends of the semiconductor layer along the width;
wherein the source is entirely disposed on an upper surface of the semiconductor layer other than the portion that is adjacent to the etching stop layer and that is disposed on the first surface of the etching stop layer; wherein the source is entirely disposed on the upper surface of the semiconductor layer other than the portion that is adjacent to the etching stop layer and that is disposed on the first surface of the etching layer.