Patent ID: 11941250
Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. The apparatus of claim 1, wherein:
the processor subsystem comprises a level one (L1) cache, a level two (L2) cache, a first miss status handling register (MSHR) queue associated with the L1 cache and a second miss status handling register (MSHR) queue associated with the L2 cache; and
the instructions, when executed by the hardware processor, further cause the hardware processor to:
associate the metric with one of the first MSHR queue or the second MSHR queue;
use the metric as an indication of an occupancy of the associated one of the first MSHR queue or the second MSHR queue;
compare the occupancy to a capacity of the associated one of the first MSHR or the second MSHR; and
select the optimization responsive to a result of the comparison.