Patent ID: 11923037
Assignee: CANON KABUSHIKI KAISHA
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. The memory control circuit according to claim 5, wherein
the management unit further manages, for each of the plurality of banks, a page miss time until a read or write command issuance to a bank is enabled in an event of occurrence of a page miss in the bank, based on the shortest issuance interval, and
the determination unit
prioritizes read when only read access requests are held in the holding unit,
prioritizes write when only write access requests are held in the holding unit,
does not change the prioritized access type when both read and write access requests are held in the holding unit and there is no bank in which a page miss has occurred, and
when both read and write access requests are held in the holding unit and there is a bank in which a page miss has occurred, does not change the prioritized access type in case where time required for performing all the access requests that are of the same type as the access in which a page is already open, among the access requests held in the holding unit, is equal to or longer than the page miss time, and changes the prioritized access type in case where the time is shorter than the page miss time.