Patent ID: 11929112
Assignee: ANHUI UNIVERSITY
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. The sense amplifier of claim 1, wherein the amplification circuit comprises:
a first positive channel Metal Oxide Semiconductor (PMOS) transistor, a drain of the first PMOS transistor being connected to a first node;
a first negative channel Metal Oxide Semiconductor (NMOS) transistor, a drain of the first NMOS transistor being connected to the first node, and a gate of the first NMOS transistor being connected to a gate of the first PMOS transistor;
a second PMOS transistor, a drain of the second PMOS transistor being connected to a second node;
a second NMOS transistor, a drain of the second NMOS transistor being connected to the second node, and a gate of the second NMOS transistor being connected to a gate of the second PMOS transistor;
a third PMOS transistor, a drain of the third PMOS transistor being connected to a source of the first PMOS transistor and a source of the second PMOS transistor, a gate of the third PMOS transistor being configured to receive a second control signal, and a source of the third PMOS transistor being configured to receive a supply voltage; and
a third NMOS transistor, a drain of the third NMOS transistor being connected to a source of the first NMOS transistor and a source of the second NMOS transistor, a gate of the third NMOS transistor being configured to receive a first control signal, and a source of the third NMOS transistor being grounded;
wherein the gate of the first PMOS transistor is connected to the second node, and the gate of the second PMOS transistor is connected to the first node.