Patent ID: 11943925
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 16:
17. The semiconductor memory device of claim 15,
wherein each of the plurality of first charge storage patterns comprises:
a first charge trap layer between a corresponding first semiconductor pattern of the plurality of first semiconductor patterns and each of the pair of the first and second word lines;
a first blocking insulating layer between the first charge trap layer and each of the pair of the first and second word lines; and
a first tunnel insulating layer between the first charge trap layer and the corresponding first semiconductor pattern,
wherein each of the plurality of second charge storage patterns comprises:
a second charge trap layer between a corresponding second semiconductor pattern of the plurality of second semiconductor patterns and each of the pair of the third and fourth word lines;
a second blocking insulating layer between the second charge trap layer and each of the pair of the third and fourth word lines; and
a second tunnel insulating layer between the second charge trap layer and the corresponding second semiconductor pattern.