Patent ID: 11966310
Assignee: MELLANOX TECHNOLOGIES, LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. An electronic circuit, comprising:
one or more functional hardware circuits;
one or more processing circuits, to handle events occurring in the one or more functional hardware circuits;
a cause-tree circuit, to deliver the events from the one or more functional hardware circuits to the one or more processor cores for handling, the cause tree circuit comprising (i) storage elements to collect the events from the one or more functional hardware circuits, and (ii) coalescing circuits to coalesce the collected events;
a memory buffer coupled to the root node of the cause-tree circuit, the memory buffer to buffer a plurality of the coalesced events, so as to trigger the processing circuits to handle the buffered events; and
a buffer analysis circuit, to analyze a performance of the cause-tree circuit based on the events buffered in the memory buffer.