Patent ID: 11868327
Assignee: JIHENG ZHANG
Field: Digital communication (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 8:
9. An apparatus for adding blocks of a blockchain based on a structured directed acyclic graph (DAG) according to the method of claim 4, the apparatus comprising:
a memory and a processor, wherein the memory stores machine-executable instructions and the processor reads and executes the machine-executable instructions;
a receiving unit, stored in the memory and executed by the processor, configured to perform the receiving the new block information;
a first determining unit, stored in the memory and executed by the processor, configured to perform the determining whether the new block information satisfies a set of conditions;
an adding unit, stored in the memory and executed by the processor, configured to perform the adding the new block information;
a removing unit, stored in the memory and executed by the processor, configured to perform the removing the first transaction information from the local transaction pool;
a second determining unit, stored in the memory and executed by the processor, configured to perform the determining whether the block pointed by the new block is in the local database;
a requesting unit, stored in the memory and executed by the processor, configured to perform the requesting the block from the node device;
a third determining unit, stored in the memory and executed by the processor, configured to perform the determining whether the new block is the milestone block; and
an updating unit, stored in the memory and executed by the processor, configured to perform the updating the local distributed ledger.