Patent ID: 11888751
Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A computer system, comprising:
a processor;
an egress logic block to allocate, from the computer system, flow control credits for a first virtual channel to an upstream node in the distributed computing environment;
an ingress logic block to:
receive, via a message path comprising the upstream node, a message on the first virtual channel based on the allocated flow control credits; and
store the message in a queue associated with an input port at which the message has been received;

a remapping logic block to:
determine whether the message is a candidate for changing the first virtual channel to a different channel at the node based on a mapping rule associated with the input port;
in response to the message being a candidate, select a second virtual channel for the message based on the mapping rule and the first virtual channel;
associate the message with the second virtual channel in the queue; and
determine that the first virtual channel is an ingress virtual channel for the message based on metadata stored in the queue in association with the message; and

wherein the egress logic block is further to send the message from the queue on the second virtual channel based on flow control credits for the second virtual channel.