Patent ID: 11961556
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 7:
8. An apparatus, comprising:
a first access line for an array of memory cells, the first access line coupled with a first socket of a first row of sockets, wherein the first row of sockets is non-orthogonal to the first access line;
a second access line for the array of memory cells, the second access line coupled with a second socket of a second row of sockets, wherein the second row of sockets is parallel to the first row and non-orthogonal to the second access line; and
a controller coupled with the array of memory cells, wherein the controller is configured to cause the apparatus to:
receive an access command for a memory cell of the array of memory cells, the memory cell coupled with the first access line and the second access line;
route, based at least in part on the access command, a current through the memory cell, the first access line, the first socket coupled with the first access line, the second access line, and the second socket coupled with the second access line; and
read or write the memory cell based at least in part on the current.