Patent ID: 11955562
Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A transistor device comprising:
a first insulator;
a first oxide over the first insulator;
a second oxide over the first oxide;
a third oxide and a fourth oxide over the second oxide;
a first conductor over the third oxide;
a second conductor over the fourth oxide;
a fifth oxide over the second oxide;
a second insulator over the fifth oxide;
a third conductor over the second insulator;
a third insulator over the first conductor and the second conductor; and
a fourth insulator over the third insulator,
wherein the fifth oxide is in contact with a top surface of the second oxide, a first side surface of the first conductor, a first side surface of the second conductor, a first side surface of the third oxide, a first side surface of the fourth oxide, and a side surface of the third insulator,
wherein the fifth oxide is in contact with an inner surface of an opening provided in the fourth insulator,
wherein the third conductor is provided to fill the opening,
wherein the second oxide comprises In, an element M and Zn, where the element M is Al, Ga, Y, or Sn,
wherein the first oxide comprise at least one of constituent elements included in the second oxide,
wherein the third oxide and the fourth oxide each comprise the element M, and
wherein the third oxide and the fourth oxide each comprise a region having a concentration of the element M higher than a concentration of the element M in the second oxide, and
wherein a shift voltage change amount ΔVsh of the transistor is less than or equal to 100 mV after 550 hours of the +GBT stress test,
wherein a gate voltage of the +GBT stress test is set to 3.63V and a temperature of the +GBT stress test is set to 150° C.