Patent ID: 11943924
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 17:
18. A method of forming a memory device, the method comprising:
forming a layered structure above a source region; and
forming multiple strings of a vertical arrangement of multiple charge trap structures in the layered structure, the forming of each string including:
forming a vertical opening in the layered structure with the vertical opening bounded by a sidewall;
forming, on and contacting the sidewall, material for dielectric barriers for a vertical arrangement of multiple charge trap structures, the material for dielectric barriers structured as a nanolaminate of multiple regions of different material compositions, with the material for dielectric barriers continuously extending vertically between and as a part of the charge trap structures in the formed string with each charge trap structure having a charge trap region separated from a portion of the material for dielectric barriers by a dielectric blocking region;
forming gates of the multiple charge trap structures; and
forming dielectric isolation structures with gates for adjacent charge trap structures on opposite sides of the dielectric isolation structures, with the dielectric isolation structures having a void with the material for dielectric barriers as a first portion of a boundary of the void and having a sealing dielectric, opposite the material for dielectric barriers, as a second portion of the boundary of the void.