Patent ID: 11888586
Assignee: nan
Field: Telecommunications (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A low-latency network device for treating serial data received at a receiving data rate, the device comprising:
an oscillator generating a device-wide clock;
a receiving physical medium attachment (PMA) having an internal data width, the PMA being configured to:
receive the serial data,
deserialize the serial data based on the device-wide clock and internal data width, whereby the received serial data is oversampled, the oversampling of the received serial data being asynchronous relative to a timing of the received serial data, and
output a parallelized sample stream;

a symbol timing synchronization module configured to:
receive the parallelized sample stream; and
detect, from the parallelized sample stream, synchronized bit values corresponding to bit values of the received serial data; and

a physical convergence sublayer (PCS) configured to:
receive the synchronized bit values; and
delineate packets from the synchronized bit values, to provide packet-delineated parallelized data,

the receiving PMA, the symbol timing synchronization module and the PCS being all driven by the device-wide clock.