Patent ID: 11875858
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device comprising:
a memory array comprising memory cells; and
control logic operatively coupled to the memory array, the control logic to perform memory erase operations comprising:
performing a true erase sub-operation by causing multiple pulse steps to be applied sequentially to a group of memory cells of the memory array, wherein each sequential pulse step of the multiple pulse steps occurs during a pulse-step period and at a higher voltage compared to an immediately-preceding pulse-step;
in response to detecting an erase suspend command during a pulse step, suspending the true erase sub-operation at a start of a subsequent pulse-step period after the pulse step; and
resuming the true erase sub-operation at an end of the subsequent pulse-step period.