Patent ID: 11894367
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 5:
6. A method, comprising:
forming first semiconductor nanosheets of a first gate all around transistor of an integrated circuit;
forming second semiconductor nanosheets of a second gate all around transistor of the integrated circuit;
depositing an interfacial dielectric layer on the first and second semiconductor nanosheets;
depositing a dipole-inducing layer on the interfacial dielectric layer on the first and second semiconductor nanosheets;
covering the dipole-inducing layer on the first semiconductor nanosheets with a mask layer; and
exposing the second semiconductor nanosheets by removing the dipole-inducing layer and the interfacial dielectric layer from the second semiconductor nanosheets while the dipole-inducing layer on the first semiconductor nanosheets is covered by the mask layer.