Patent ID: 11973079
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 12:
13. The method according to claim 11, further comprising:
forming an isolation structure over the semiconductor substrate and laterally between the first fin structure and the second fin structure;
forming a dummy gate structure over the first fin structure, the second fin structure, and the stack of semiconductor layers;
forming a pair of first source/drain regions directly over the first fin structure and on opposite sides of the dummy gate structure;
forming a pair of second source/drain regions directly over the second fin structure and on opposite sides of the dummy gate structure;
removing the dummy gate structure;
forming a first plurality of nanostructures directly over the first fin structure by selectively removing the plurality of first semiconductor layers; and
forming a gate dielectric layer and a gate electrode over the first and second fin structures and around the first plurality of nanostructures.