Patent ID: 11929428
Assignee: WOLFSPEED, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 32:
33. A method of making a device comprising:
providing a substrate;
providing a group III-Nitride barrier layer;
electrically coupling a source to the group III-Nitride barrier layer;
arranging a gate on the group III-Nitride barrier layer;
electrically coupling a drain to the group III-Nitride barrier layer;
configuring a recovery enhancement circuit to provide a bias voltage and/or a dynamic electrical pulse in order to reduce an impact of an overload received by the gate; and
providing a p-region being arranged at or below the group III-Nitride barrier layer,
wherein at least a portion of the p-region is arranged vertically below at least one of the following: the source, the gate, an area between the gate and the drain.