Patent ID: 11895224
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Digital communication (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 14:
15. An electronic device, comprising:
one or more processors configured to:
encrypt a first plaintext to a first ciphertext, which is expressed by a first polynomial including a first message and a second polynomial including a first encrypt key;
encrypt a second plaintext to a second ciphertext, which is expressed by a third polynomial including a second message and a fourth polynomial including a second encrypt key;
control respective generations, in parallel, of plural multiplication results based on multiplexed of coefficients of the first polynomial, the second polynomial, the third polynomial, and the fourth polynomial; and
generate a lattice-based text result for a polynomial multiplication of the first ciphertext and the second ciphertext based on the generated plural multiplication results, including a first multiplication result generated based on a first portion of the multiplexed coefficients, a second multiplication result generated based on a second portion of the multiplexed coefficients, and selectively a summation result generated based on some of the generated plural multiplication results.