Patent ID: 11948224
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 10:
11. A method comprising:
performing, operations including, via a multiply-accumulate circuit, multiply-accumulate operations, on matrix data in a first layer of a neural network implementation to produce a result matrix comprising a plurality of matrix data elements at a first precision, the multiply-accumulate operations including a matrix multiplication operation with values smaller than 32 bits and an accumulate operation having a 32-bit input, the multiply-accumulate circuit included within at least one multiprocessor of a plurality of multiprocessors, each multiprocessor of the plurality of multiprocessors having a single instruction, multiple thread (SIMT) architecture, the plurality of multiprocessors included within a parallel processor coupled to a memory stack via one or more memory interfaces;
dynamically evaluating metrics associated with the matrix data elements via precision tracking logic of the at least one multiprocessor;
indicating, via the precision tracking logic and based on the metrics, that an optimization is to be performed for representing data at a second layer of the neural network implementation, wherein the optimization includes applying a numerical transform operation on the data to enable representation of the data at the second layer at a second precision; and
dynamically performing the numerical transform operation on the matrix data elements based on the indication, the numerical transform operation performed via a numerical transform unit of the at least one multiprocessor to produce transformed matrix data elements at the second precision, wherein the second precision is lower than the first precision.