Patent ID: 11916565
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 17:
18. The analog-to-digital converter of claim 17, wherein a voltage level of the first input voltage is greater than a voltage level of the second input voltage,
a voltage level of the first comparison voltage is greater than a voltage level of the second comparison voltage,
a voltage level of the first offset voltage is greater than a voltage level of the second offset voltage, and
the offset calibration logic is further configured to:
increase the first offset voltage and reduce the second offset voltage based on the first logic level of the corresponding reference signal being greater than the second logic level of the comparison result signal, and
reduce the first offset voltage and increase the second offset voltage based on the first logic level of the corresponding reference signal being less than the second logic level of the comparison result signal.