Patent ID: 11871565
Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A method for manufacturing a semiconductor device, comprising:
filling a sacrificial layer in a first via of a first stack including alternating first insulating layers and first gate layers, the first stack being over a substrate of the semiconductor device, an initial top CD (CDinit) being larger than an initial bottom CD (CD1init) of the first via;
forming a second via of a second stack including alternating second insulating layers and second gate layers, the second stack being along a vertical direction over the first stack;
forming a third via of a third stack including alternating third insulating layers and third gate layers, the third stack being along the vertical direction over the second stack, wherein the second insulating layers etch at a faster rate than the third insulating layers and the second gate layers etch at a faster rate than the third gate layers;
removing portions of the second stack and the third stack to form a combined via including the second via and the third via, the combined via being above the first via wherein an initial bottom CD (CD3init) of the combined via is less than CD2init and an initial discontinuity is between CD2init and CD3init;
etching an additional portion of the second stack to enlarge the second via and to reduce the initial discontinuity to a final discontinuity between a final bottom CD of the combined via and a final top CD of the first via wherein the second insulating layers etch at a faster rate than the third insulating layers and the second gate layers etch at a faster rate than the third gate layers; and
removing the sacrificial layer from the first via.