Patent ID: 11862280
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 19:
20. The apparatus of claim 17, wherein the first memory array is at a first deck included in a plurality of decks of the apparatus and the second memory array is at a second deck included in the plurality of decks of the apparatus, the apparatus further comprising:
first decoder circuitry included in the first deck and configured to activate a first transistor of the plurality of transistors based at least in part on selecting a gate electrode for the first transistor from a corresponding first plurality of gate electrodes included in the first deck; and
second decoder circuitry included in the second deck and configured to activate a second transistor of a second plurality of transistors based at least in part on selecting a gate electrode for the second transistor from a corresponding second plurality of gate electrodes included in the second deck, the second plurality of transistors configured to select electrodes from the second plurality of electrodes.