Patent ID: 11935607
Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. The integrated circuit die of claim 12,
wherein the first transistor comprises a first PMOS transistor having a source coupled to a supply voltage, a drain at which the gate voltage is produced, and a gate coupled to receive the output voltage of the comparator of the voltage regulator; and wherein the second transistor comprises a second PMOS transistor having a source coupled to a supply voltage, a drain at which the copy voltage is produced, and a gate coupled to receive the output voltage of the comparator of the voltage regulator; and
wherein the comparator of the voltage regulator includes a non-inverting terminal coupled to receive a reference voltage, an inverting terminal coupled to receive the feedback voltage, and an output at which the output voltage is generated; and wherein the voltage regulator further comprises a resistance coupled between the drain of the first PMOS transistor and the inverting terminal of the comparator of the voltage regulator.