Patent ID: 11887666
Assignee: ZENO SEMICONDUCTOR, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 7:
8. An integrated circuit comprising:
an array of semiconductor memory cells, the array comprising:
a plurality of said semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes:
a first bipolar device having a first floating base region, a first collector, and a first emitter, and
a second bipolar device having a second floating base region, a second collector, and a second emitter;
wherein said first floating base region is common to said second floating base region;
wherein said first collector is common to said second collector;
wherein application of back-bias to said first and second collectors results in at least two stable floating base region charge levels, and
wherein said first and second collectors are commonly connected to at least two of said memory cells;

a region extending from and electrically connected to said first and second collectors, wherein said region has a conductivity type selected from a p-type conductivity type and an n-type conductivity type that is the same as a conductivity type of said first and second collectors;

a control circuit configured to apply said back-bias to said first and second collectors; and
a second control circuit configured to access a selected memory cell selected from said semiconductor memory cells and perform a read or write operation on said selected memory cell.