Patent ID: 11916558
Assignee: QUALCOMM INCORPORATED
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 18:
19. The system of claim 17, further comprising:
a third clock path;
a sixth multiplexer having a first input, a second input, and an output, wherein the first input of the sixth multiplexer is coupled to the third clock source, the second input of the sixth multiplexer is coupled to the fourth clock source;
a seventh multiplexer having a first input, a second input, and an output, wherein the first input of the seventh multiplexer is coupled to the first clock path, the third clock path is coupled between the output of the sixth multiplexer and the second input of the seventh multiplexer, and the output of the seventh multiplexer is coupled to the input of the first delay control circuit; and
an eighth multiplexer having a first input, a second input, and an output, wherein the first input of the seventh multiplexer is coupled to the second clock path, the third clock path is coupled between the output of the sixth multiplexer and the second input of the eighth multiplexer, and the output of the eighth multiplexer is coupled to the input of the second delay control circuit.