Patent ID: 11901436
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 11:
12. A method comprising:
forming first and second fins over a substrate, the first and second fins each comprising alternately stacking first semiconductor layers and second semiconductor layers;
forming first and second dummy gate structures across the first and second fins;
forming first gate spacers on either side of the first dummy gate structure and second gate spacers on either side of the second dummy gate structure;
removing the first and second dummy gate structures to form a first gate trench between the first gate spacers and a second gate trench between the second gate spacers;
selectively etching the first semiconductor layers in the first and second gate trenches;
depositing a first gate dielectric layer in the first and second gate trenches and a second gate dielectric layer over the first gate dielectric layer;
forming a hard mask layer over the second gate dielectric layer by using one or more atomic layer deposition (ALD) cycles each comprising sequentially performing a first pulse step, a first purge step for a first purge time, a second pulse step, and a second purge step for a second purge time, wherein the first purge time is longer than the second purge time;
patterning the hard mask layer to expose a portion of the second gate dielectric layer; and
etching the exposed portion of the second gate dielectric layer.