Patent ID: 11916159
Assignee: SOLAERO TECHNOLOGIES CORP
Field: Semiconductors (Electrical engineering)
Classification: CPC H  C  Y | IPC H

Claim 16:
17. A method as defined in claim 1, further comprising an intermediate graded layer disposed between one of the first solar subcell and the second solar subcell and the adjacent solar subcell disposed directly below the one solar subcell, wherein the intermediate layer is compositionally graded to lattice match the one of the first solar subcell and the second solar subcell on one side and the adjacent solar subcell on the other side and is composed of any of the As, P, N, Sb based III-V compound semiconductors subject to the constraints of having the in-plane lattice parameter greater than or equal to that of the one solar subcell and less than or equal to that of the adjacent solar subcell, and having a band gap greater than that of the one of the first solar subcell and the second solar subcell.