Patent ID: 11928072
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 15:
16. A memory system comprising:
a board;
a connector portion that is provided on the board and configured to support Dual Port including a first port and a second port both conforming to a PCIe standard, the first port including a first number of lanes with a first order, the second port including a second number of lanes with a second order;
a semiconductor memory chip that is mounted on the board; and
a controller mounted on a surface of the board and configured to control an operation of the semiconductor memory chip,
wherein the controller comprises:
a physical layer interface circuit configured to support the Dual Port, the first number of lanes and the second number of lanes being connected to the physical layer interface circuit via traces arranged in an order in which at least a part of the first order and at least a part of the second order are changed based on Lane Reversal conforming to the PCIe standard;
first and second PCIe media access control (MAC) layer circuits that are provided for the first port and the second port, respectively, and connect to the physical layer interface circuit based on the Lane Reversal;
a signal processing circuit comprising: a first terminal and a second terminal, the first terminal being configured to receive a part of Sideband signals of the first port to be transmitted via first auxiliary signal lines that are different from first signal lines for the first number of lanes, and the second terminal being configured to receive a part of the Sideband signals of the second port to be transmitted via second auxiliary signal lines that are different from second signal lines for the second number of lanes; and
a switching circuit configured to:
switch between a first trace and a second trace for the first and second terminals of the signal processing circuit based on the Lane Reversal, the first trace configured for the part of the signals of the first auxiliary signal lines, the second trace configured for the part of the signals of the second auxiliary signal lines, and
switch, based on the Lane Reversal, between a trace for another part of the signals of the first auxiliary signal lines and a trace for another part of the signals of the second auxiliary signal lines between the physical layer interface circuit and the first and second PCIe MAC layer circuits.