Patent ID: 11942178
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A circuit comprising:
a ground node;
first and second data lines;
a first device series coupled between the first and second data lines, wherein the first device series comprises a first n-type metal-oxide-semiconductor (NMOS) capacitor coupled between first and second switching devices;
a second device series coupled between the first and second data lines, wherein the second device series comprises a second NMOS capacitor coupled between third and fourth switching devices;
a sense amplifier comprising a first input terminal coupled to a first terminal of the first NMOS capacitor and a second input terminal coupled to a first terminal of the second NMOS capacitor;
a first NMOS transistor coupled between a second terminal of the first NMOS capacitor and the ground node; and
a second NMOS transistor coupled between a second terminal of the second NMOS capacitor and the ground node,
wherein the circuit is configured to
in a first part of a read operation, close each of the first through fourth switching devices and open each of the first and second NMOS transistors, and
in a second part of the read operation, open each of the first through fourth switching devices and close each of the first and second NMOS transistors.