Patent ID: 11967549
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A method of manufacturing a semiconductor package, the method comprising:
forming a planar conductive pattern on a first carrier;
forming a redistribution structure on the first carrier, wherein the redistribution structure includes a plurality of insulation layers, and a plurality of redistribution layers between the plurality of insulation layers, each of the plurality of redistribution layers having a connection via connected to an adjacent one of planar conductive pattern and the plurality of redistribution layers;
forming a plurality of bonding pads on the redistribution structure, each of the plurality of bonding pads having a bonding via connected to an uppermost redistribution layer among the plurality of redistribution layers
disposing at least one semiconductor chip to electrically connect the plurality of bonding pads;
forming a molding portion encapsulating the at least one semiconductor chip;
grinding the molding portion to expose the upper surface of the at least one semiconductor chip;
attaching a second carrier to the upper surface of the at least one semiconductor;
removing the first carrier from a surface of the redistribution structure, in which the planar conductive pattern is disposed;
forming a base insulation layer on the surface of the redistribution structure to cover the planar conductive pattern; and
forming an underbump metallurgy (UBM) pad on the base insulation layer, the UBM pad having a UBM via connected to the planar conductive pattern.