Patent ID: 11950423
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 18:
19. An electronic system comprising:
a main substrate;
a semiconductor device on the main substrate; and
a controller on the main substrate and electrically connected to the semiconductor device,
wherein the semiconductor device comprises:
a cell area comprising a memory cell array; and
a peripheral circuit area having the cell area stacked thereon in a vertical direction, the peripheral circuit area comprising a peripheral circuit substrate and a plurality of circuits on the peripheral circuit substrate and electrically connected to the memory cell array,
wherein the plurality of circuits comprise:
a plurality of planar channel transistors respectively configured to form a channel along a top surface of the peripheral circuit substrate; and
at least one recess channel transistor configured to form a channel along a surface of a recess trench in the peripheral circuit substrate,
wherein the at least one recess channel transistor comprises:
a first recess channel transistor comprising a first gate electrode and a first source/drain region including a first impurity region and a second impurity region, the first impurity region having a first dopant concentration, and the second impurity region having a second dopant concentration greater than the first dopant concentration; and
a second recess channel transistor comprising a second gate electrode and a second source/drain region including a third impurity region and a fourth impurity region, the third impurity region having a third dopant concentration, and the fourth impurity region having a fourth dopant concentration greater than the third dopant concentration,
wherein, in the vertical direction relative to the top surface of the peripheral circuit substrate, a depth of the second gate electrode or the third impurity region of the second recess channel transistor is greater than a depth of the first gate electrode or the first impurity region of the first recess channel transistor.