Patent ID: 11876702
Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Field: Digital communication (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A network interface controller (NIC), comprising:
a host interface to receive a memory access request from a host device;
a cache for storing resolved memory address translations; and
an address translation unit (ATU) to:
determine an operating mode for the ATU, wherein the operating mode is one of:
a regular mode that causes the ATU to perform the memory address translation of the memory address; and
a bypass mode that causes the ATU to defer to the host device for the memory address translation of the memory address;

determine whether a memory address indicated in the memory access request is available in the cache; and
in response to the memory address not being available in the cache, perform an operation on the memory address based on the operating mode of the ATU,
wherein in response to the ATU being in the regular mode, the ATU is to:
generate an address translation request for the memory address translation of the memory address; and
send the address translation request to an address translation service via the host interface.