Patent ID: 11950518
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A memory device comprising:
a bottom electrode;
a top electrode disposed over the bottom electrode; and
a phase-change layer disposed between the top electrode and bottom electrode, the phase change layer comprising:
an upper sublayer comprising a chalcogenide germanium (Ge)-antimony (Sb)-tellurium (Te) (GST) material that comprises at least 30 at % Ge;
a lower sublayer comprising a GST material; and
a middle sublayer disposed between the upper sublayer and the lower sublayer and comprising a GST material,
wherein the lower sublayer directly contacts the bottom electrode, a Ge content of the lower sublayer is from about 10 at % to about 30 at % greater than a Ge content of the upper sublayer, and a Ge content of the middle sublayer is greater than the Ge content of the upper sublayer and is less than the Ge content of the lower sublayer.