Patent ID: 11917184
Assignee: BYTEDANCE INC.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. An apparatus for processing video data comprising a processor and a non-transitory memory with instructions thereon, wherein the instructions upon execution by the processor, cause the processor to:
perform a conversion between a video comprising one or more subpictures and a bitstream of the video according to a format rule,
wherein the format rule specifies that a first syntax element in a scalable nesting supplemental enhancement information message in the bitstream is set to a particular value in response to the scalable nesting supplemental enhancement information message including one or more subpicture level information supplemental enhancement information messages,
wherein the particular value of the first syntax element indicates that one or more scalable-nested supplemental enhancement information messages in the scalable nesting supplemental enhancement information message apply to a specific output video layer set, and
wherein a payload type of 203 for a supplemental enhancement information message indicates that the supplemental enhancement information message is the subpicture level information supplemental enhancement information message.