Patent ID: 11886713
Assignee: NEC CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. A memory control device comprising:
at least one memory configured to store instructions; and
at least one processor configured to execute instructions to:
store additional data in an additional data area of memory-stored data of a memory including compressed data, the additional data including an error correcting code of the compressed data and compression information representing a degree of compression of the compressed data; and
when reading out the memory-stored data from the memory, perform a readout process a number of times based on the degree of compression represented by the compression information in the additional data area, wherein
the number of times that the readout process is performed is determined when reading out the memory-stored data from the memory on a basis of a data capacity before compression, a read capacity of one readout process, and the degree of compression represented by the compression information in the additional data area.