Patent ID: 11916114
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 0:
1. A device comprising:
a first nanostructure;
a second nanostructure over the first nanostructure;
a first high-k gate dielectric around the first nanostructure;
a second high-k gate dielectric around the second nanostructure, wherein the first high-k gate dielectric and the second high-k gate dielectric each comprise fluorine; and
a gate electrode over the first and second high-k gate dielectrics, wherein the gate electrode comprises:
a first work function metal;
a second work function metal over the first work function metal; and
a first metal residue at an interface between the first work function metal and the second work function metal; and

a first source/drain region and a second source/drain region on opposing sides of the gate electrode, wherein a first insulation structure is between and separates the gate electrode from the first source/drain region, and wherein a second insulation structure is between and separates the gate electrode from the second source/drain region.