Patent ID: 11935957
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for semiconductor processing, the method comprising:
etching trenches in a substrate to define a first fin and a second fin;
recessing the second fin;
forming a first isolation region adjacent the first fin, wherein the first fin extends above the first isolation region by a first distance;
forming a second isolation region adjacent the second fin, wherein the second fin extends above the second isolation region by a second distance, wherein the first distance is greater than the second distance; and
forming a first gate structure over the first fin and a second gate structure over the second fin, wherein a third distance from an upper surface of the first fin to an upper surface of the first gate structure is less than a fourth distance from an upper surface of the second fin to an upper surface of the second gate structure.