Patent ID: 11929761
Assignee: SEAGATE TECHNOLOGY LLC
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 18:
19. The memory device of claim 16 storing instructions that, when executed, cause the processor to perform the method further comprising:
generating a plurality of check-to-variable (c2v) message vectors at the check node processor based on the plurality of check node vectors, the plurality of c2v message vectors including estimates for the selected set of bits;
providing the plurality of c2v message vectors from the check node processor to the variable node processor in parallel;
receiving input data related to a selected set of bits of the codeword at the variable node processor, the input data indicating a confidence of the selected set of bits as initially read;
generating the plurality of v2c message vectors at the variable node processor based on the input data and the plurality of c2v message vectors; and
the input data, the plurality of v2c message vectors, and the plurality of c2v message vectors include bit value estimates in the form of log likelihood ratio (LLR) values.