Patent ID: 11862245
Assignee: ZENO SEMICONDUCTOR, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 5:
6. A semiconductor memory device comprising a plurality of memory strings to form a grid of semiconductor memory cells, each said memory string comprises a plurality of memory cells connected in series, wherein each said memory cell comprises:
a floating body region configured to be charged to a level of charge indicative of a state of said memory cell to store data as volatile memory indicative of said state of said memory cell;
a first region in electrical contact with said floating body region;
a second region in electrical contact with said floating body region and spaced apart from said first region;
a floating gate or trapping layer positioned between said first and second regions and configured to receive transfer of said data stored as volatile memory and store said data as nonvolatile memory indicative of said state of the memory cell; and
a control gate positioned above said floating gate or trapping layer,
wherein said level of charge indicative of said state of said memory cell stored in said floating body region determines a current flowing through said semiconductor memory cell, and
wherein said transfer of data to said floating gate or trapping layer occurs to one or more of said memory cells.