Patent ID: 11949019
Assignee: ZINITE CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A vertical thin film transistor comprising:
a substantially planar substrate;
an insulating layer formed on the substrate;
a source formed on the insulating layer;
a source-channel interfacial member formed on the source;
a second insulating layer formed on the source-channel interfacial member and forming a vertical well having an inner surface extending upward from the source-channel interfacial member;
an n-type semiconductor material formed on inner surface of the well and the source-channel interfacial member, wherein the source-channel interfacial member electrically connects the source to the n-type semiconductor material;
a gate dielectric layer formed over the n-type semiconductor material;
a gate formed over the dielectric layer; and
a drain formed on the second insulating layer in electrical contact with the n-type semiconductor material wherein, when the transistor is in an on state current can flow from the source to the drain through the source-channel interfacial member and through a channel formed in the n-type semiconductor material.