Patent ID: 11901455
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method comprising:
forming a gate stack over a semiconductor fin;
forming an epitaxial source/drain region in the semiconductor fin adjacent the gate stack;
depositing a first dielectric layer over the gate stack and over the epitaxial source/drain region;
forming an opening in the first dielectric layer to expose the epitaxial source/drain region;
depositing a sacrificial material within the opening;
depositing a conductive material over the sacrificial material within the opening;
removing the sacrificial material to form a recess; and
implanting the first dielectric layer with a dopant, wherein after implanting the first dielectric layer the recess is covered by the first dielectric layer.