Patent ID: 11948617
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. The memory device of claim 7, further comprising:
one or more controllers operable to cause the memory device to:
write a first plurality of memory values to a row of memory cells;
enable a row of magnetic storage components corresponding to the row of memory cells, concurrent with writing the first plurality of memory values to the row of memory cells, wherein the row of magnetic storage components is operable to be programmed to states corresponding to the first plurality of memory values based at least in part on the row of magnetic storage components being enabled while the first plurality of memory values are written to the row of memory cells; and
read, concurrently with enabling the row of magnetic storage components, memory values from a second row of magnetic storage components previously written to a corresponding second row of memory cells.