Patent ID: 11948942
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. An integrated circuit device, comprising:
a fin-type active area along a first horizontal direction on a substrate, the fin-type active area including a fin top and a recess, and a level of a lowermost surface of the recess being less than a level of the fin top in a vertical direction;
a nanosheet stack including a plurality of nanosheets on the fin top, the plurality of nanosheets being spaced apart from the fin top and having different vertical distances from the fin top; and
a source/drain area on the recess and facing the plurality of nanosheets in the first horizontal direction, the source/drain area including an outer blocking layer, an inner blocking layer, and a main body layer that are sequentially stacked on the nanosheet stack and on the recess,
wherein each of the outer blocking layer and the main body layer includes a Si1-xGex layer, where x≠0, and the inner blocking layer includes a Si layer, and
wherein a first level of a lowermost surface of the outer blocking layer is lower than the level of the fin top in the vertical direction.