Patent ID: 11955932
Assignee: PSEMI CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for biasing the final stages of a cascode amplifier, including:
(a) providing a cascode amplifier having at least two serially connected field effect transistor (FET) stages, each FET stage having a gate, a drain, and a source, the bottom FET stage having an input configured to be coupled to an RF input signal to be amplified, and the top FET stage of the cascode amplifier having an output for providing an amplified RF input signal;
(b) providing a cascode reference circuit having at least two serially connected FET stages, each FET having a gate, a drain, and a source, the gates of the bottom two FET stages of the cascode reference circuit being coupled to the corresponding gates of the bottom two FET stages of the cascode amplifier, for biasing the cascode amplifier to output a final current approximately equal to a multiple of a mirror current in the cascode reference circuit; and
(c) providing an op-amp having a first and a second input and an output, the first input being coupled between a voltage source through a first resistor and a reference current source, the second input being coupled between the voltage source through a second resistor and the drain of the top FET stage of the cascode reference circuit, the output being coupled to the respective gates of the bottom FET stages of the cascode reference circuit and the cascode amplifier, wherein the op-amp is responsive to differences between its first and second inputs and outputs an adjustment gate bias voltage applied to the respective gates of the bottom FET stage of the cascode amplifier and of the cascode reference circuit that forces the mirror current in the cascode reference circuit to be approximately equal to a selected current value.