Patent ID: 11917806
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. The method of manufacturing a semiconductor structure according to claim 6, wherein the step of removing the etching sacrificial layer exposed in each of the third grooves to form the second groove comprises:
removing the etching sacrificial layer exposed in each of the third grooves by a predetermined thickness to form a recess, wherein the recess is a semioval-shaped groove;
forming a barrier layer in the recess;
removing the barrier layer at a bottom of the recess, such that a retained barrier layer forms a first opening, wherein a bottom surface of the first opening exposes the etching sacrificial layer;
removing the etching sacrificial layer exposed in the first opening by a predetermined thickness, to form a second opening, wherein a top surface of the etching sacrificial layer in the second opening is higher than the top surface of the substrate; and
repeatedly removing the etching sacrificial layer in the second opening by a predetermined thickness until the top surface of the bit line is exposed, such that a retained etching sacrificial layer forms a concave-convex inner wall on an inner wall of the second groove.