Patent ID: 11967634
Assignee: MIRISE TECHNOLOGIES CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor device comprising:
a semiconductor element includes:
a semiconductor layer having a first conductivity type or a second conductivity type;
a first-conductivity-type layer disposed above the semiconductor layer, and having the first conductivity type with an impurity concentration lower than an impurity concentration of the semiconductor layer;
a saturation current suppression layer disposed above the first-conductivity-type layer, and including
a first deep layer whose lengthwise direction is defined as a first direction, the first deep layer having the second conductivity type and having a plurality of sections aligned in a stripe pattern, and
a JFET portion whose a lengthwise direction is identical to the first direction, the JFET portion having the first conductivity type, the JFET portion having a plurality of sections aligned in a stripe pattern and disposed in alternate arrangement with the plurality of sections of the first deep layer;
a current dispersion layer having the first conductivity type disposed above the saturation current suppression layer;
a base region having the second conductivity type and disposed above the current dispersion layer;
a source region disposed above the base region, and having the first conductivity type with an impurity concentration higher than the impurity concentration of the first-conductivity-type layer;
a contact region disposed at a position different from the source region above the base region, and having the second conductivity type with an impurity concentration higher than an impurity concentration of the base region;
a plurality of trench gate structures aligned in a stripe pattern, each of which has a lengthwise direction defined as a second direction intersecting the first direction, each of which includes
a gate trench penetrating the source region and the base region,
a gate insulation film covering an inner wall surface of the gate trench, and
a gate electrode disposed above the gate insulation film;
an interlayer insulation film covering the gate electrode, and including a contact hole for exposing the contact region and the source region;
a source electrode electrically connected to the source region through the contact hole;
a drain electrode disposed at a rear side of the semiconductor layer; and
a second deep layer disposed among the plurality of trench gate structures and connected to the first deep layer, the second deep layer having a lengthwise direction identical to the second direction, the second deep layer having a width larger than or equal to a spacing between adjacent two of the trench gate structures and disposed at an entire region between the adjacent two of the trench gate structures along a widthwise direction of each of the trench gate structures.