Patent ID: 11881273
Assignee: SOCIONEXT INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 0:
1. A semiconductor storage device provided with a read only memory (ROM) cell, comprising:
a word line extending in a first direction;
first and second bit lines extending in a second direction perpendicular to the first direction; and
a ground power supply line extending in the second direction,, wherein
the ROM cell includes
a first transistor that is a three-dimensional transistor provided between the first bit line and the ground power supply line,
a second transistor that is a three-dimensional transistor provided between the second bit line and the ground power supply line, formed above the first transistor, channel portions of the first and second transistors overlapping each other as viewed in plan,
a first local interconnect that is connected to a source of the first transistor and extends from the first transistor toward a first-oriented direction in the first direction,
a second local interconnect that is connected to a source of the second transistor and extends from the second transistor toward a direction opposite to the first-oriented direction in the first direction,
a third local interconnect that is connected to a drain of the first transistor and extends from the first transistor toward a second-oriented direction in the first direction, and
a fourth local interconnect that is connected to a drain of the second transistor and extends from the second transistor toward a direction opposite to the second-oriented direction in the first direction,

gates of the first and second transistors are connected to the word line, and
first data is stored in the ROM cell depending on the presence or absence of connection between the first local interconnect and the ground power supply line or the presence or absence of connection between the third local interconnect and the first bit line, and second data is stored in the ROM cell depending on the presence or absence of connection between the second local interconnect and the ground power supply line or the presence or absence of connection between the fourth local interconnect and the second bit line.