Patent ID: 11881451
Assignee: NANYA TECHNOLOGY CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A method for preparing a semiconductor device, comprising:
forming a device substrate over a carrier substrate; and
forming an interconnect part over the device substrate, wherein the step of forming the interconnect part comprises:
forming a lower redistribution layer electrically connected to the backside contact;
forming an interconnect structure over and electrically connected to the lower redistribution layer; and
forming an upper redistribution layer over and electrically connected to the interconnect structure;
forming a second source/drain structure over the carrier substrate;
forming a frontside contact over and electrically connected to the second source/drain structure; and
forming a redistribution structure over and electrically connected to the frontside contact;
wherein the step of forming the interconnect structure of the interconnect part comprises:
forming an energy removable layer over the lower redistribution layer;
etching the energy removable layer to form a first opening and a second opening exposing the lower redistribution layer;

forming a first passivation liner and a second passivation liner on sidewalls of the first opening and sidewalls of the second opening, respectively; and
forming a first interconnect conductor in the first opening and surrounded by the first passivation liner and a second interconnect conductor in the second opening and surrounded by the second passivation liner.