Patent ID: 11930629
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 15:
16. A semiconductor memory device, comprising:
a plurality of memory cells on a substrate, each of the memory cells including a plurality of memory transistors; and
a first line layer, a second line layer, and a third line layer sequentially stacked on the memory cells,
wherein the first line layer includes a bit line, a power line, and a first lower landing pad,
wherein the second line layer includes a ground line having an opening, an upper landing pad in the opening, and vias provided below the ground line and the upper landing pad, the ground line including a pair of first segments and a pair of second segments that define the opening, each of the first segments extending in a first direction and having a first width in a second direction intersecting the first direction, each of the second segments extending in the second direction and having a second width in the first direction, the first width being different from the second width,
wherein the opening surrounds the upper landing pad when viewed in a plan view,
wherein the third line layer includes a word line,
wherein the word line is electrically connected through the upper landing pad and the first lower landing pad to a terminal of a first memory transistor of the memory transistors,
wherein the power line included in the first line layer is under a corresponding one of the first segments of the ground line included in the second line layer, and the power line vertically overlaps the corresponding one of the first segments, and
wherein the vias below the ground line are connected only to the second segments and not to the first segments.