Patent ID: 11942138
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 3:
4. The memory system of claim 1,
wherein the memory controller is further suitable for setting a plurality of reference counting values based on the row-hammer data,
wherein the memory controller includes a plurality of latch circuits respectively corresponding to the plurality of reference counting values,
wherein the memory controller is further suitable for comparing the plurality of reference counting values with the plurality of counting values,
wherein the memory controller calculates the plurality of adjacent addresses using a corresponding sampling address when a result of the comparing of the plurality of reference counting values with the plurality of counting values matches,
wherein the memory controller is further suitable for storing the plurality of adjacent addresses into the plurality of latch circuits, and
wherein the memory controller provides the stored adjacent addresses as the first row-hammer address according to the first target refresh command.