Patent ID: 11935951
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 3:
4. The device of claim 1, further comprising:
a second gate stack disposed over a second fin structure;
a third source/drain feature disposed on the second fin structure, wherein the second source/drain feature is formed of a third semiconductor material that includes the second-type dopant;
a second passivation material layer disposed within the second fin structure and interfacing with a third side and a fourth side of the third source/drain feature, the third side of the third source/drain feature being opposite the fourth side of the third source/drain feature, the second passivation material layer formed of the second semiconductor material that includes the second-type dopant, wherein the second semiconductor material that includes the second-type dopant interfaces with the third semiconductor material that includes the second-type dopant of the third source/drain feature.