Patent ID: 11881442
Assignee: SHANGHAI INTEGRATED CIRCUIT MANUVACTURING INNOVATION CENTER CO., LTD
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 4:
5. A method for fabricating an SOI active interposer for three-dimensional packaging, comprising:
providing an SOI substrate including a silicon substrate, a silicon dioxide and a top silicon;
producing a CMOS inverter on the surface of the SOI substrate, the CMOS inverter including a PMOS transistor and an NMOS transistor;
forming a first insulating medium to cover the PMOS transistor and the NMOS transistor;
performing photolithography and etching on an area between the PMOS transistor and the NMOS transistor until a part of the silicon substrate is etched away;
forming a second insulating medium on the resulting structure;
removing the first insulating medium and the second insulating medium on the sources, drains and gates of the PMOS transistor and the NMOS transistor by photolithography and etching to form source, drain and gate via holes;
forming a copper diffusion barrier layer, a seed layer and copper, and removing the copper, the seed layer and the copper diffusion barrier layer above the second insulating medium by a chemical mechanical polishing process;
forming a top adhesion layer/seed layer laminated film and micro bumps; and
thinning the silicon substrate on the back of the SOI substrate by a combined process of mechanical grinding and chemical mechanical polishing, so that the bottom of the copper is exposed to form a bottom adhesion layer/seed layer laminated film and a C4 bump;
wherein the second insulating medium is disposed on the first insulating medium and in direct contact with the first insulating medium, and the side wall of the SOI via hole is continuously covered by the second insulating medium.