Patent ID: 11860748
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. A memory test system, comprising a central processing unit and a graphics processing unit, wherein:
the central processing unit is configured to run a test program to access a memory to-be-tested based on an accessible capacity of an allocated central processing unit; when the central processing unit runs the test program, the central processing unit controls the graphics processing unit to access the memory to-be-tested based on an accessible capacity of an allocated graphics processing unit, the central processing unit and the graphics processing unit serially access the memory to-be-tested simultaneously through a bus of memory to-be-tested; and the bus of memory to-be-tested is an advanced extensible interface bus comprising a predetermined transmission path; and
the graphics processing unit is configured to access the memory to-be-tested based on the accessible capacity of the allocated graphics processing unit; wherein
obtaining the accessible capacity of the allocated central processing unit comprises obtaining an accessible capacity, based on a capacity of the memory to-be-tested, of the memory to-be-tested and that is accessible by the central processing unit, and obtaining an address of the accessible capacity of the memory to-be-tested and accessible by the central processing unit; and
obtaining the accessible capacity of the allocated graphics processing unit comprises obtaining an accessible capacity, based on the capacity of the memory to-be-tested, of the memory to-be-tested and that is accessible by the graphics processing unit, and obtaining an address of the accessible capacity of the memory to-be-tested and accessible by the graphics processing unit.