Patent ID: 11881441
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor package comprising:
a substrate having an upper surface, a transversely opposed second surface, and a substrate footprint area and a contact pad array disposed on the second surface of the substrate;
wherein the contact pad array includes a plurality of contact pads arranged in a first pattern; and
wherein the first pattern includes a plurality of peripheral electrical contact pads and a plurality of mechanical contact pads;
a first die stack having a first die stack footprint area, the first die stack comprising a first die vertically over a second die, the first die having a footprint smaller than and entirely within a footprint of the second die, and the first die stack footprint area less than the substrate footprint area; and
a spacer die disposed between the upper surface of the substrate and first die stack the spacer die having a footprint area that is greater than the first die stack footprint area and the same or smaller than the substrate footprint area;
wherein the first die stack physically couples to the upper surface of the spacer die in a location such that the first die stack footprint area partially overlaps a portion of the plurality of peripheral electrical contact pads from a plan view perspective, wherein the plurality of mechanical contact pads is outside of the first die stack footprint area; and
wherein the spacer die footprint area completely overlaps the portion of the plurality of peripheral electrical contact pads at least partially overlapped by the first die stack footprint from the plan view perspective, wherein the spacer die footprint area overlaps the plurality of mechanical contact pads, and wherein there are no contact pads on the second surface of the substrate outside of the spacer die footprint area.