Patent ID: 11954360
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory controller comprising:
one or more substrates; and
logic coupled to the one or more substrates, wherein the logic is at least partly implemented in one or more of configurable or fixed-functionality hardware, and the logic coupled to the one or more substrates is to:
program a plurality of seed values into a plurality of linear feedback shift registers (LFSRs), wherein the plurality of LFSRs correspond to a data word and at least two of the plurality of seed values differ from one another, and wherein each of the plurality of seed values differ from one another and are automatically selected to each differ from one another based on one or more of an expected traffic pattern on a link coupled to the plurality of LFSRs or a deskew constraint associated with the link; and
train the link coupled to the plurality of LFSRs.