Patent ID: 11962309
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G  Y | IPC H

Claim 6:
7. The phase adjusting circuit of claim 6, wherein the duty cycle sub-circuit comprises a first switch transistor, a second switch transistor, a third switch transistor, a fourth switch transistor, a first current source, a second current source, a third current source, a fourth current source, a first capacitor, a second capacitor, and an operational amplifier; wherein,
a control terminal of the first switch transistor and a control terminal of the second switch transistor form a connection point configured to receive the first detection signal; a first terminal of the first switch transistor is connected to an output terminal of the first current source, an input terminal of the first current source is connected to a power supply signal, a second terminal of the second switch transistor is connected to an input terminal of the second current source, and an output terminal of the second current source is connected to a ground signal; and a second terminal of the first switch transistor and a first terminal of the second switch transistor are both connected to a first terminal of the first capacitor, and a second terminal of the first capacitor is connected to the ground signal;
a control terminal of the third switch transistor and a control terminal of the fourth switch transistor form a connection point configured to receive the second detection signal; a first terminal of the third switch transistor is connected to an output terminal of the third current source, an input terminal of the third current source is connected to the power supply signal, a second terminal of the fourth switch transistor is connected to an input terminal of the fourth current source, and an output terminal of the fourth current source is connected to the ground signal; and a second terminal of the third switch transistor and a first terminal of the fourth switch transistor are both connected to a first terminal of the second capacitor, and a second terminal of the second capacitor is connected to the ground signal; and
the first terminal of the first capacitor is further connected to an inverting input terminal of the operational amplifier, the first terminal of the second capacitor is further connected to a non-inverting input terminal of the operational amplifier, and an output terminal of the operational amplifier is configured to output the comparison result signal.