Patent ID: 11907139
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. A system comprising:
a central processing unit (CPU);
at least one dual in-line memory module (DIMM) comprising a first rank of one or more memory devices and a second rank of one or more memory devices;
a data buffer integrated circuit (IC);
a first data path coupled between the CPU and the data buffer IC;
a second data path coupled between the data buffer IC and a first data buffer device within the at least one DIMM, wherein the first data buffer device is coupled to the first rank of the one or more memory devices via the second data path; and
a third data path coupled between the data buffer IC and a second data buffer device within the at least one DIMM, wherein the second data buffer device is coupled to the second rank of the one or more memory devices via the third data path.