Patent ID: 11935610
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. A method, comprising:
providing an array of memory cells including data memory cells actively used for storing data and backup memory cells;
storing an error table that tracks errors of the data memory cells;
in response to determining from the error table that a failure count of a first data memory cell is higher than a threshold failure count, replacing the first data memory cell with a backup memory cell and designate the backup memory cell as an activated data memory cell to be used for actively storing data, wherein the first data memory cell is designated as a deactivated data memory cell; and
responsive to a second failure count for a second data memory cell exceeding the failure count of the first data memory cell, designating the deactivated data memory cell as a restored data memory cell.