Patent ID: 11949595
Assignee: INTEL CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A system comprising:
a semiconductor substrate comprising:
a first set of processing element nodes arranged in at least two columns and at least two rows, the first set of processing element nodes defining a first hierarchy of processing element nodes, the first set of processing element nodes comprising:
a source node,
a source look-up table (LUT),
a first router, the first router to comprise a first forwarder node, and
a first reflection LUT;

a second set of processing element nodes arranged in at least two columns and at least two rows, the second set of processing element nodes defining a second hierarchy of processing element nodes, the second set of processing element nodes comprising:
a second router, the second router to comprise a second forwarder node, and
a second reflection LUT; and

a third set of processing element nodes arranged in at least two columns and at least two rows, the third set of processing element nodes defining a third hierarchy of processing element nodes, the third set of processing element nodes comprising:
a third forwarder node, and
a target node;

wherein the first reflection LUT is to comprise an address of the second forwarder node in the second hierarchy, the first forwarder node to identify a cardinal direction for the second forwarder node from the first reflection LUT and to forward a message to the second forwarder node;
wherein the second reflection LUT is to comprise an address of the third forwarder node in the third hierarchy, the second forwarder node to identify a cardinal direction for the third forwarder node from the second reflection LUT and to forward a message to the third forwarder node; and
wherein the third forwarder node is to forward a packet to the target node.