Patent ID: 11955980
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A method for reducing a coarse lock time of a Phase Locked Loop (PLL), the method comprising:
controlling, by the PLL, a voltage transient in an Automatic Bank Calibration (ABC) current Digital to Analog Converter (DAC) of the PLL using a plurality of switchable voltage clamps, wherein the ABC current DAC comprises a plurality of Metal Oxide Silicon Field Effect Transistors (MOSFETs);
dividing, by the PLL, a loop filter capacitor of the PLL into two segments to reduce a Low Pass Filter (LPF) settling time; and
reducing, by the PLL, the coarse lock time of the PLL using the controlled voltage transients and the divided loop filter capacitor,
wherein dividing, by the PLL, the loop filter capacitor of the PLL into two segments to reduce the LPF settling time includes
dividing, by the PLL, the loop filter capacitor of the PLL into two segments, wherein a first segment is pre-charged to a supply voltage through a pull-up switch and a second segment is pre-charged to a ground voltage through a pull-down switch when the PLL is turned off;
determining, by the PLL, whether the PLL is turn on; and
performing, by the PLL, one of:
shorting the first segment and the second segment to reduce the LPF settling time in response to determining that the PLL is turn on, wherein the pull-up switch and the pull-down switch are turned off, or
separating the first segment and the second segment to reduce the LPF settling time in response to determining that the PLL is turned off.