Patent ID: 11908812
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 0:
1. A device comprising:
a substrate comprising a first substrate contact, a second substrate contact, and a third substrate contact;
a first memory die coupled to the substrate, the first memory die comprising:
a first power supply contact pad electrically coupled to the first substrate contact and a first power supply circuit on the first memory die;
a first electrostatic discharge (ESD) power clamp contact pad electrically coupled to the first substrate contact and a first ESD power clamp circuit on the first memory die; and
a first data bus contact electrically coupled to the second substrate contact and a first data bus on the first memory die;

a second memory die comprising:
a second power supply contact pad electrically coupled to the first substrate contact and a second power supply circuit on the second memory die;
a second ESD power clamp contact pad electrically coupled to a second ESD power clamp circuit on the second memory die, wherein the second ESD power clamp contact pad is electrically disconnected from the first substrate contact and the second substrate contact; and
a second data bus contact electrically coupled to the second substrate contact and a second data bus on the second memory die; and

a third memory die comprising a third data bus contact electrically coupled to the third substrate contact and a third data bus on the third memory die.