Patent ID: 11886706
Assignee: STMICROELECTRONICS (GRAND OUEST) SAS
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. The device according to claim 9, wherein the compressed application comprises a plurality of sections stored at consecutive memory addresses of the first location, and wherein the processing circuitry, in operation, decompresses the compressed application by:
decompressing a first section located at least partially at an address next to the location of the another compressed application;
storing the decompressed first section at least partially into the second location storing the another compressed application;
decompressing a second section of the compressed application located at least partially at an address next to the first compressed section of the compressed application; and
storing the decompressed second section of the compressed application into at least one address next to the decompressed first section.