Patent ID: 11900498
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A processor comprising:
an input circuit to receive a set of N input values to be sorted into a sorted order, the set of N input values are obtained with in a graphics pipeline stage;
comparison circuitry to compare each input value with all other input values in parallel to generate at least N*(N−1)/2 comparison result values;
matrix generation circuitry and/or logic to generate a result matrix having a row associated with each input value, a plurality of bits in each row comprising comparison result values indicating results of comparisons with other input values, wherein a first region of the result matrix is to store a first set of bits comprising the N*(N−1)/2 comparison result values and a second region of the result matrix, opposite the first region, is to store a second set of bits comprising an inverse of the N*(N−1)/2 comparison result values;
a parallel adder circuit to perform parallel additions of the bits in each row to generate N unique result values; and
sorting circuitry to index into the N unique result values to return the sorted order to the graphics pipeline stage.