Patent ID: 11935756
Assignee: nan
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method used during fabrication of a semiconductor device, comprising:
providing a layer to be etched;
forming a sacrificial patterning layer over the layer to be etched, wherein the sacrificial patterning layer comprises a plurality of segmented portions having at least first and second cross sectional sidewalls;
forming a plurality of sacrificial first spacers, with one spacer formed on each sidewall of each segmented portion of the sacrificial patterning layer;
removing the sacrificial patterning layer;
forming a conformal second spacer layer over the plurality of sacrificial first spacers;
removing a portion of the conformal second spacer layer to form a plurality of second spacers on the sacrificial first spacers, wherein the second spacers have different elevational thicknesses;
subsequent to forming the second spacers, removing the sacrificial first spacers; and
etching the layer to be etched using the second spacers as a pattern.