Patent ID: 11864394
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G  H

Claim 9:
10. A semiconductor device comprising:
a first memory deck comprising a plurality of first memory cells respectively coupled between first row lines and column lines crossing the first row lines, each of the plurality of first memory cells including a first variable resistance layer; and
a second memory deck comprising a plurality of second memory cells respectively coupled between the column lines and second row lines crossing the column lines, each of the plurality of second memory cells including a second variable resistance layer,
wherein a first read pulse of a first polarity is applied during a read operation of each of the plurality of first memory cells, and a second read pulse of a second polarity different from the first polarity is applied during a read operation of each of the plurality of second memory cells, and
wherein a first program pulse of the first polarity is applied during a set operation of each of the plurality of first memory cells, a second program pulse of the second polarity different from the first polarity is applied during a reset operation of each of the plurality of first memory cells, the second program pulse of the second polarity is applied during a set operation of each of the plurality of second memory cells, and the first program pulse of the first polarity is applied during a reset operation of each of the plurality of second memory cells.