Patent ID: 11935958
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 9:
10. A semiconductor device structure, comprising:
a first stacked nanostructure and a second stacked nanostructure formed over a substrate;
a first gate structure formed over the first stacked nanostructure, wherein the first gate structure comprises a first portion of a gate dielectric layer and a first portion of a filling layer;
a second gate structure formed over the second stacked nanostructure, wherein the second gate structure comprises a second portion of the gate dielectric layer and a second portion of the filling layer; and
a first isolation layer between the first gate structure and the second gate structure, wherein the first isolation layer has an extending portion which is formed in a recess between the gate dielectric layer and the filling layer.