Patent ID: 11875268
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A device, comprising:
a processor; and
a memory,
the processor and the memory being configured as a neural network comprising:
at least one first layer comprising an input and an output, the first layer configured to receive an input feature map at the input and output an output feature map at the output, the neural network further comprising at least one interim feature map between the input and the output of the first layer, the interim feature map having been quantized by a unitary quantizing operation or a supervised iterative quantization operation to reduce a number of bits of at least one value of the interim feature map from a first predetermined number of bits to a second predetermined number of bits that is less than the first predetermined number of bits without changing a dimension of the interim feature map.