Patent ID: 11948018
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A data processing system comprising:
a processor having one or more processing cores, one or more memory controllers, one or more general purpose engines on an On-Chip Controller that is not part of the one or more processing cores, and one or more links for communicatively coupling the one or more processing cores, the one or more memory controllers, and the On-Chip-Controller having the one or more general processing engines, the processor further comprising one or more performance monitoring units having one or more counters, each counter having an associated configuration register; and
main memory communicatively coupled to the processor via a memory bus,
wherein the system is configured to:
monitor, by at least one of the general processing engines on the On-Chip-Controller a first event by one of the one or more counters on the processor;
determine whether a change in the monitoring of the first event to the second different event has been requested;
copy, in response to a request to change the monitoring of the first event to the second different event, op-codes from main memory into microcode executable by the at least one of the general processing engines on the On-Chip-Controller;
execute the op-codes from memory by the at least one of the general processing engines to change the first event monitored by the one of the one or more counters on the processor to the second different event; and
monitor, by the at least one of the general processing engines on the On-Chip-Controller, the second different event by the same one of the one or more counters on the processor that monitored the first event.