Patent ID: 11935618
Assignee: QUICKLOGIC CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 10:
11. An integrated circuit (IC) comprising a programmable logic device (PLD), wherein the PLD comprises a configuration memory latch, the configuration memory latch comprising:
a first pMOS transistor, wherein a first pMOS source of the first pMOS transistor is coupled to a supply voltage and the first pMOS transistor drain is coupled to a first node;
a first pull-down network comprising a first nMOS transistor in series with a second nMOS transistor, wherein the first nMOS transistor source is coupled to ground (GND) and the second nMOS transistor drain is coupled to the first node;
a second pull down network in parallel with the first pull-down network, wherein the second pull-down network comprises a third nMOS transistor in series with a fourth nMOS transistor, wherein the third nMOS transistor source is coupled to ground and the fourth nMOS transistor drain is coupled to the first node;
a first pull up network, wherein the first pull up network comprises a second pMOS transistor, a third pMOS transistor, and a fourth pMOS transistor, wherein: the second pMOS transistor drain is coupled to the first node, the third pMOS transistor drain and the fourth pMOS transistor drain are both coupled to the second pMOS transistor source, and the third pMOS transistor source and the fourth pMOS transistor source are both coupled to the supply voltage;
an input reset line coupled to the first pMOS transistor gate and to the first nMOS transistor gate, wherein the reset line is active low;
a first inverter, wherein the input of the first inverter is coupled to the first node, and the output of the first inverter is coupled to the second pMOS transistor gate and to the second nMOS transistor gate;
a bit line (BL) signal to input a first data to be written into the configuration memory latch during write operations, wherein the BL is coupled to the third pMOS transistor gate and to the third nMOS transistor gate;
an input Word Line Write (WLW) signal, which, when asserted, enables data to be written to the configuration memory latch, wherein the WLW signal is coupled to the fourth pMOS transistor gate and to the fourth nMOS transistor gate; and
a second inverter, wherein the input of the second inverter is coupled to the first node, and the output of the second inverter drives an output line of the configuration memory latch.