Patent ID: 11909407
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. The system as claimed in claim 6, wherein the failure scenario comprises one of:
a) a first ratio of a first frequency of an input clock to the IQ divider and a second frequency of the reference clock being a first integer;
b) a second ratio of the first frequency of the input clock and the second frequency of the reference clock is a first non-integer number, wherein a first fractional portion of the second ratio being less than a latch-up window threshold, wherein the latch-up window threshold is determined as tlatchup/N, and wherein N is a number of reference cycles allowed to pass before activating the delay control element; or
c) a third ratio of the first frequency of the input clock and the second frequency of the reference clock being a second non-integer number, wherein a second fractional portion of the third ratio is greater than the latch-up window threshold.