Patent ID: 11908865
Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor structure, comprising:
a substrate, wherein the substrate comprises a first region, a second region, and an isolation region disposed between the first region and the second region;
a first fin disposed over the first region, a second fin disposed over the second region, and a third fin disposed over the isolation region;
a high-K dielectric layer disposed on top and sidewall surfaces of the first fin, the second fin, and the third fin; and
a gate structure on the high-K dielectric layer and across the first fin, the second fin, and the third fin, wherein:
the gate structure comprises a first work function layer disposed over the first region and a first portion of the isolation region, and a second work function layer disposed over the second region and a second portion of the isolation region, and
an interface where the first work function layer is in direct contact with the second work function layer is located over a top surface of the high-K dielectric layer on the top surface of the third fin.