Patent ID: 11934307
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus to receive requests from a plurality of processing units, where multiple of the plurality of processing units have associated cache storage, the apparatus comprising:
a snoop unit to implement a cache coherency protocol when a request received by the apparatus identifies a cacheable address within memory;
the snoop unit having snoop filter storage comprising a plurality of snoop filter tables organised in a hierarchical arrangement, wherein the plurality of snoop filter tables comprise a primary snoop filter table at a highest level in the hierarchy, and each snoop filter table at a level in the hierarchy other than the highest level forms a backup snoop filter table for an adjacent snoop filter table at a higher level in the hierarchy;
wherein:
each snoop filter table is arranged as a multi-way set associative storage structure to provide a plurality of entries, and each backup snoop filter table has a different number of sets than are provided in the adjacent snoop filter table at the higher level in the hierarchy;
each entry in the snoop filter tables is used to store, for an associated address, coherence data used to determine which cache storages provided within the multiple processing units need to be subjected to a snoop operation in response to a request specifying that associated address; and
the snoop unit further comprises snoop control circuitry to control allocation of coherence data into entries of the snoop filter tables, wherein the snoop control circuitry is arranged, when new coherence data is to be allocated into the snoop filter storage, to apply an allocation policy to determine into which of the plurality of snoop filter tables the new coherence data is allocated.