Patent ID: 11886331
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. A system, comprising:
a memory sub-system comprising a memory device that includes a plurality of access rows; and
a processing device coupled to the memory device, wherein the processing device is configured to:
determine a quantity of addressable partitions in a first address row of the memory device;
write first data to the first set of contiguous partitions in the first access row of the particular memory device;
write a portion of second data to a second set of contiguous partitions in the first access row of the memory device, wherein:
a quantity of bits associated with the portion of the second data is based on the determined quantity of addressable partitions in the first address row, and
a null partition is provided between the first set of contiguous partitions and the second set of contiguous partitions; and

write a second portion of the second data to a first set of contiguous partitions in a second access row of the memory device.