Patent ID: 11876521
Assignee: CADENCE DESIGN SYSTEMS, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for updating a delay line code, comprising:
receiving a strobe input at a coarse delay line;
receiving a coarse delay cell code at the coarse delay line;
generating a first clock signal based upon a first chain of interleaved logic gates included within the coarse delay line;
generating a second clock signal based upon a second chain of interleaved logic gates included within the coarse delay line;
receiving the first clock signal, the second clock signal, and a fine delay cell code at a fine delay cell; and
generating a strobe delayed output based upon, at least in part, the first clock signal, and the second clock signal, and the fine delay code, wherein the strobe delayed output depends on only one of the first clock signal and the second clock signal when switching a coarse delay code.