Patent ID: 11901010
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A method comprising:
initiating a program operation on a memory array, the program operation comprising a seeding phase;
causing a seeding voltage to be applied to a string of memory cells in a data block of the memory array during the seeding phase of the program operation;
causing a first positive voltage to be applied to a first plurality of word lines of the data block during the seeding phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in the string of memory cells, the first plurality of word lines comprising a selected word line associated with the program operation, at least one word line adjacent to the selected word line on a drain-side of the selected word line, and at least one word line adjacent to the selected word line on a source-side of the selected word line; and
causing a second positive voltage to be applied to one or more second word lines coupled to one or more second memory cells on a source-side of the first plurality of memory cells in the string of memory cells during the seeding phase, wherein the second positive voltage is less than the first positive voltage.