Patent ID: 11916011
Assignee: MACRONIX INTERNATIONAL CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 8:
9. The vertical memory structure of claim 1, including a plurality of series of alternating conductive pillars and insulating pillars disposed through stack, the conductive pillars in the plurality of series being arranged in an array, the plurality of series including the series, wherein the plurality of series in the array are arranged in a plurality of distinct subarrays of the array, each distinct subarray including at least one series in the plurality of series, and further including:
a plurality of conductive strips separated by gaps disposed in a pillar select layer over the stack, including for each distinct subarray of the array, a corresponding conductive strip of the plurality of conductive strips, and including for each distinct subarray of the array a plurality of vertical channel structures through the corresponding conductive strip contacting respective conductive pillars in the distinct subarrays;
a plurality of alternating dummy conductive pillars and dummy insulating pillars disposed through the stack, arranged in lines aligned with the gaps separating the conductive strips in the plurality of conductive strips; and
a plurality of bit line conductors disposed over the pillar select layer over the stack, each bit line conductor having contacts to one vertical channel transistor in a plurality of vertical channel transistors in each of the distinct subarrays.