Patent ID: 11961552
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A memory device comprising:
a first wafer including a logic structure disposed on one surface of the first wafer and a cell structure disposed on the other surface of the first wafer, wherein the cell structure includes a cell region and the logic structure includes a pass transistor circuit,
a second wafer including a page buffer circuit, a peripheral circuit and a block switch circuit, and
a plurality of bit lines extending in a first direction and arranged in a second direction,
wherein the cell region includes a plurality of memory blocks that are coupled to the plurality of bit lines,
wherein each memory block is divided into a plurality of sub-blocks each including a plurality of partial pages that are disposed in a plurality of rows arranged in the first direction.