Patent ID: 11915651
Assignee: LG DISPLAY CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A circuit comprising:
a substrate;
a buffer layer overlying the substrate;
a light emitting device overlying the substrate and the buffer layer;
a driving voltage node;
a driving element having a first terminal, a second terminal, and a first gate terminal, the first terminal coupled to the driving voltage node, the second terminal coupled to the light emitting device;
a reference voltage node configured to provide a reference voltage via a reference line;
a data voltage node configured to provide a data voltage via a data line different from the reference line;
a second switch element having a fourth terminal, a fifth terminal, and a second gate terminal, the fourth terminal coupled to the first gate terminal of the driving element, the fifth terminal configured to receive a voltage corresponding to either the reference voltage from the reference voltage node or the data voltage from the data voltage node;
a third switch element coupled between the first terminal of the driving element and the driving voltage node, the third switch element having a third gate terminal;
a common gate line supplied with an emission control signal and coupled to the second gate terminal of the second switch element and the third gate terminal of the third switch element;
an initialization voltage node;
a fourth switch element coupled between the second terminal of the driving element and the initialization voltage node, the fourth switch element being turned on during an initialization time and a sampling time in one horizontal period, wherein the initialization time includes a first period and a second period;
a fifth switch element coupled between the reference voltage node and the fifth terminal, the fifth switch element being turned on to supply the reference voltage to the second switch element during the initialization time and the sampling time;
a first switch element, wherein the fifth terminal is coupled to the data voltage node through the first switch element different from the fifth switch element;
a first capacitor having a first plate coupled to the first gate terminal and a second plate coupled to the first terminal of the driving element,
wherein, during the first period of the initialization time, the third switch element is turned on in response to the emission control signal of a first voltage level to supply a driving voltage to the driving element,
wherein, during the second period of the initialization time and the sampling time, the second switch element is turned on in response to the emission control signal of a second voltage level to supply the reference voltage receiving through the fifth switch element to the driving element,
wherein the initialization time, the sampling time, the data writing time, and an emission time are contiguous and in the sequence of the initialization time, the sampling time, the data writing time, and then the emission time,
wherein the first switch element and the second switch element include a thin film transistor formed as an NMOS of a bottom gate structure,
wherein at least one of the driving element, the third switch element, the fourth switch element, and the fifth switch element include a polycrystalline silicon thin film transistor formed as a PMOS of a top gate structure, that includes:
a polycrystalline silicon overlying the buffer layer;
a first gate insulating layer overlying the polycrystalline silicon; and
a first gate overlying the first gate insulating layer;
wherein the second switch element formed as the NMOS of a bottom gate structure includes:
a second gate formed on the first gate insulating layer and constituting the second gate terminal;
a second gate insulating layer formed on the first gate insulating layer and overlying the first and second gates;
at least one interlayer dielectric layer formed on the second gate insulating layer;
a semiconductor pattern formed on the at least one interlayer dielectric layer; and
first and second electrodes formed on the semiconductor pattern and directly contacting a source region and a drain region of the second semiconductor pattern, the first and second electrodes each constituting the fourth terminal and the fifth terminal; and
wherein the second gate of the second switch element overlaps the first and second electrodes.