Patent ID: 11916044
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. The method of manufacturing a semiconductor structure according to claim 13, wherein the forming conductive through vias in at least two layers of dies, wherein each of the conductive through vias penetrates the at least two layers of dies comprises:
forming through vias on back surfaces of the dies, wherein each of the through vias penetrates the dies;
forming an insulating layer on an inner wall surface of each of the through vias;
forming a barrier layer on a surface of the insulating layer;
forming a seed layer on a surface of the barrier layer; and
forming a conductive layer on a surface of the seed layer, wherein the conductive layer and the seed layer form a conductive structure, and the conductive structure fills the through via;
wherein the conductive structure is electrically connected to an interconnecting structure in the interlayer dielectric layer.