Patent ID: 11966608
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. A memory system comprising a memory device, wherein the memory device comprises:
a memory cell array comprising a plurality of blocks;
a control logic circuit configured to control operations of writing and reading data to and from the memory cell array; and
an interface circuit configured to transmit and receive various signals to and from a memory controller,
wherein the interface circuit is configured to output to the memory controller deterioration information comprising information regarding one or more word lines at specific locations included in a deterioration region of the plurality of blocks,
a plurality of pieces of user data and parity data corresponding to the plurality of pieces of user data are stored in the memory device and constitute a redundant array of inexpensive disks (RAID), and
the control logic circuit is configured to copy the plurality of pieces of user data to a normal region of the plurality of blocks, and copy the parity data to the deterioration region of the plurality of blocks based on the various signals from the memory controller.