Patent ID: 11907157
Assignee: CORNAMI, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G  H

Claim 0:
1. A reconfigurable processor circuit comprising:
a first interconnection network;
a second interconnection network;
a processor coupled to the first interconnection network; and
a plurality of computational cores arranged in an array, the plurality of computational cores coupled to the first interconnection network and to the second interconnection network, the second interconnection network coupling adjacent computational cores of the plurality of computational cores, each computational core comprising:
a memory circuit;
a reconfigurable arithmetic circuit comprising:
at least one input reordering queue;
a configurable multiplier coupled to the at least one input reordering queue;
a configurable shifter and combiner network coupled to configurable multiplier; and
an accumulator circuit coupled to the configurable shifter and combiner network;

and
a zeros compression circuit comprising:
a zeros counter configured to count one or more sequential data packets having a zero data payload to generate a zeros count; and
a first data packet generator configured, when a next data packet has a nonzero data payload, to encode the zeros count as a suffix in the next data packet.