Patent ID: 11894267
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. A method for fabricating an integrated circuit device, comprising:
forming a first conductive via and a second conductive via in a first interlayer dielectric layer, wherein the first conductive via is laterally aligned with the second conductive via;
forming a memory structure over and in direct contact with a top surface of the first conductive via, wherein the memory structure comprises at least a metal oxide layer over the first conductive via and a top electrode over and in contact with the metal oxide layer; and
forming a first conductive line over and in direct contact with a top surface of the second conductive via, wherein the first conductive line is laterally aligned with the memory structure and has a top surface higher than a top surface of the memory structure, a bottom surface in direct contact with the top surface of the second conductive via, and a substantially straight sidewall extending from the top surface of the first conductive line to the bottom surface of the first conductive line;
forming a third conductive via over and in direct contact with the top surface of the first conductive line, wherein the first conductive line extends beyond an entire width of the third conductive via; and
forming a conductive feature over and in contact with the top electrode of the memory structure, wherein the conductive feature comprises a second conductive line, and the top surface of the first conductive line is substantially level with a top surface of the second conductive line.