Patent ID: 11901011
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A semiconductor storage device comprising:
a substrate having a surface extending in a first direction and a second direction crossing the first direction,
first to fourth memory pillars each extending in a third direction crossing the first direction and the second direction;
a first word line provided in a first layer, extending in the first direction and facing one sides of the first to fourth memory pillars in the second direction;
a second word line provided in the first layer, extending in the first direction and facing the other sides of the first to fourth memory pillars in the second direction;
a third word line provided in a second layer above the first layer in the third direction, extending in the first direction and facing the one sides of the first to fourth memory pillars in the second direction;
a fourth word line provided in the second layer, extending in the first direction and facing the other sides of the first to fourth memory pillars in the second direction;
a first select gate provided in a third layer above the second layer in the third direction, extending in the first direction and facing the other sides of the first and fourth memory pillars in the second direction;
a second select gate provided in the third layer in the third direction, extending in the first direction and facing the one sides of the first and second memory pillars in the second direction;
a third select gate provided in the third layer in the third direction, extending in the first direction and facing the other sides of the second and third memory pillars in the second direction;
a fourth select gate provided in the third layer in the third direction, extending in the first direction and facing the one sides of the third and fourth memory pillars in the second direction;
a control circuit,
wherein
memory cells are formed at intersections of the first to fourth word lines and the first to fourth memory pillars, respectively,
the control circuit is configured to:
perform a first write operation to the memory cells formed at the intersections of the first word line and the first and fourth memory pillars;
after the first write operation, perform a second write operation to the memory cells formed at the intersections of the first word line and the second and third memory pillars;
after the second write operation, perform a third write operation to the memory cells formed at the intersections of the second word line and the first and second memory pillars;
after the third write operation, perform a fourth write operation to the memory cells formed at the intersections of the second word line and the third and fourth memory pillars.