Patent ID: 11894100
Assignee: MACRONIX INTERNATIONAL CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 20:
21. The controlling method according to claim 18, wherein each of the at least one data buffer at least includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor and a second NMOS transistor, and the first PMOS transistor, the second PMOS transistor, the first NMOS transistor and the second NMOS transistor are connected in series;
wherein when the controlling signal is at the predetermined level and the inputting data is a first value, the first PMOS transistor and the second PMOS transistor are turned on, so that the outputting signal is raised to a first level;
wherein when the controlling signal is at the predetermined level and the inputting data is a second value, the first NMOS transistor and the second NMOS transistor are turned on, so that the outputting signal is fallen to a second level;
wherein when the first PMOS transistor and the second PMOS transistor work slower than the first NMOS transistor and the second NMOS transistor, the de-skew buffer is configured to pull the outputting signal and the complementary outputting signal high, so that forming the outputting signal is accelerated and forming the complementary outputting signal is slowed down; and
wherein when the first PMOS transistor and the second PMOS transistor work faster than the first NMOS transistor and the second NMOS transistor, the de-skew buffer is configured to pull the outputting signal and the complementary outputting signal down, so that forming the outputting signal is slowed down and forming the complementary outputting signal is accelerated.