Patent ID: 11917809
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 9:
10. The apparatus of claim 9, wherein:
each first memory cell of the set of first memory cells comprises a respective fifth transistor that is operable to couple a storage element of the first memory cell with a first access line of the plurality of first access lines, each respective fifth transistor associated with a respective fifth channel portion comprising one or more fifth semiconductor portions of the first level;
each second memory cell of the set of second memory cells comprises a respective sixth transistor that is operable to couple a storage element of the second memory cell with a second access line of the plurality of second access lines, each respective sixth transistor associated with a respective sixth channel portion comprising one or more sixth semiconductor portions of the first level;
each third memory cell of the set of third memory cells comprises a respective seventh transistor that is operable to couple a storage element of the third memory cell with a third access line of the plurality of third access lines, each respective seventh transistor associated with a respective seventh channel portion comprising one or more seventh semiconductor portions of the second level; and
each fourth memory cell of the set of fourth memory cells comprises a respective eighth transistor that is operable to couple a storage element of the fourth memory cell with a fourth access line of the plurality of fourth access lines, each respective eighth transistor associated with a respective eighth channel portion comprising one or more eighth semiconductor portions of the second level.