Patent ID: 11956156
Assignee: INTEL CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A system, comprising:
a host processor, having a plurality of cores;
host memory, coupled to the host processor;
software, loaded into the host memory, including at least one instance of an operating system and a first application having instructions to be executed on a first core of the plurality of cores, wherein execution of the software allocates an offline packet buffer in the host memory;
a Network Interface Controller (NIC), coupled to the host processor, including,
at least one network port, including a first port; and
embedded logic configured to,
while at least one of the host processor and the first core is in a sleep state,
receive network traffic comprising a one or more packets from a remote server at the first port;
determine if the network traffic is associated with the predetermined traffic class; and
when the network traffic is associated with the predetermined traffic class, write packet data extracted from the network traffic to the offline packet buffer.