Patent ID: 11893388
Assignee: FLEX LOGIX TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. A processing system comprising:
a plurality of processing components, each processing component disposed on a different die, wherein each processing component is configurable to process image data of a plurality of image frames, wherein each image frame includes a plurality of stages, wherein each processing component of the integrated circuit includes:
a plurality of multiplier-accumulator execution pipelines, wherein each multiplier-accumulator execution pipeline includes a plurality of multiplier-accumulator circuits configured to, in operation, perform multiply and accumulate operations using image data and filter weights; wherein:
a first processing component of the plurality of processing components is configured to process all of the data associated with a first plurality of stages of each image frame via a first plurality of multiplier-accumulator execution pipelines of the first processing component, wherein:
the first plurality of multiplier-accumulator execution pipelines is configurable to: (i) input data corresponding to a first plurality of stages of a first image frame, (ii) perform a first plurality of multiply and accumulate operations using data corresponding to a first plurality of stages of the first image frame and a first set of filter weights, and (iii) output processed data of a final stage of the first plurality of stage of the first image frame; and

a second processing component of the plurality of processing components is configured to process all of the data associated with a second plurality of stages of each image frame via the first plurality of multiplier-accumulator execution pipelines of the second processing component, wherein:
the first plurality of multiplier-accumulator execution pipelines is configurable to: (i) input (a) the processed data of the final stage of the first plurality of stages of the first image frame and (b) data corresponding to a second plurality of stages of the first image frame, (ii) perform a first plurality of multiply and accumulate operations using (a) the processed data of the final stage of the first plurality of stage of the first image frame, (b) the data corresponding to the second plurality of stage of the first image frame, and (c) a second set of filter weights, and
each stage of the first plurality of stages is different from each stage of the second plurality of stages, and

wherein the first and second processing components are electrically connected via a bus.