Patent ID: 11948975
Assignee: WINBOND ELECTRONICS CORP.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for fabricating semiconductor device, comprising:
forming a gate structure on a substrate;
forming a spacer around the gate structure;
forming a contact etch stop layer (CESL) directly contacting the spacer;
forming a buffer layer adjacent to the gate structure, wherein the buffer layer comprises a crescent moon shape and the buffer layer comprises an inner curve, an outer curve, and a planar surface connecting the inner curve and an outer curve along a top surface of the substrate, wherein the planar surface directly contacts the outer curve on an outer sidewall of the spacer;
forming an epitaxial layer on the buffer layer; and
forming a cap layer directly contacting a top surface of the epitaxial layer and between and directly contacting the CESL and the buffer layer, wherein the cap layer and the spacer are made of different materials.