Patent ID: 11886346
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A method comprising:
receiving, at a memory device and from a requestor, a plurality of cache read commands requesting first data from a memory array of the memory device and spread across a plurality of memory planes of the memory array;
receiving, at the memory device and from the requestor, a cache read context switch command and a snap read command requesting second data from a single plane of the plurality of memory planes of the memory array, wherein the cache read context switch command and the snap read command are stored in a command queue associated with the requestor with an indication of a higher priority than the plurality of cache read commands;
responsive to receiving the cache read context switch command, suspending processing of the plurality of cache read commands; and
processing the snap read command to read the second data from the single plane of the plurality of memory planes of the memory array and return the second data to the requestor.