Patent ID: 11972819
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. A method, comprising:
applying doses of programming to a selected word line of a plurality of word lines connected to multiple NAND strings, a first subset of the NAND strings are selected for programming, a second subset of the NAND strings are not selected for programming, the NAND strings form a block having three sub-blocks, each NAND string includes memory cells in each of the three sub-blocks, the selected word line is connected to multiple memory cells of the NAND strings in a same sub-block;
inhibiting the second subset of NAND strings from programming by boosting channels of the second subset of NAND strings from a positive pre-charge voltage to a boosted voltage; and
performing program-verify between one pair of successive doses of programming, comprising:
applying verify signals to the word lines to determine whether at least a subset of the memory cells connected to the selected word line have reached their programming target, and
lowering voltages applied to the word lines from the verify signals to one or more reduced voltages at a conclusion of program-verify between one pair of successive doses of programming such that channel potential of the second subset of NAND strings is at the positive pre-charge voltage at a conclusion of the lowering voltages by successively lowering voltages applied to groups of one or more word lines on one side of the selected word line at the conclusion of the program-verify.