Patent ID: 11860786
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. The system of claim 1, wherein the logic circuit is configured to:
select the first cache for a memory access request from the processor, when the configurable data bit is in the first state and a connection to an execution-type signal line receives an indication of a first type of the non-speculative execution of instructions;
select the second cache for a memory access request from the processor, when the configurable data bit is in the first state and the connection to the execution-type signal line receives an indication of a second type of the speculative execution of instructions;
select the second cache for a memory access request from the processor, when the configurable data bit is in the second state and the connection to the execution-type signal line receives an indication of the first type; and
select the first cache for a memory access request from the processor, when the configurable data bit is in the second state and the connection to the execution-type signal line receives an indication of the second type.