Patent ID: 11879939
Assignee: NXP B.V.
Field: Measurement (Instruments)
Classification: CPC G  H | IPC G  H

Claim 5:
6. The IC of claim 3, wherein the testing system further comprises:
a second flip-flop configured to generate a second division enable signal based on the first division enable signal and a fifth clock signal, wherein the fifth clock signal is same as the second clock signal during the capture phase; and
a second inverter that is coupled to the second flip-flop, and configured to generate the first division enable signal as an inverted version of the second division enable signal, wherein based on the activation of the capture phase, the second division enable signal is asserted and the first division enable signal is de-asserted, wherein during the capture phase, (i) the second division enable signal is de-asserted and the first division enable signal is asserted based on the assertion of the first clock pulse, and (ii) the second division enable signal is asserted and the first division enable signal is de-asserted based on the assertion of the second clock pulse, and wherein the first clock pulse and the second clock pulse are sequential.