Patent ID: 11928497
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. The computer-implemented method of claim 1, comprising:
determining modified volatile memory address locations in the volatile transaction cache that have been written to during the transaction,
identifying first data at the modified volatile memory address locations in the volatile transaction cache, and
identifying second data at corresponding persistent memory address locations in the persistent memory,, wherein:
the first data within the modified volatile memory address locations is copied to corresponding persistent memory address locations in the persistent memory, utilizing a determined correlation,
pools of storage within the volatile transaction cache and the persistent memory are segmented into predetermined memory regions of a predetermined size,
updates to the parity node and data transfers to the persistent memory in the first node are performed in a kernel space, and
the persistent memory contains a completed transaction ID and a current transaction ID, wherein:
in response to an initiation of a copying of transaction results from the volatile transaction cache to the persistent memory, the current transaction ID is incremented at the persistent memory,
as each row within the persistent memory is updated from the volatile transaction cache, its associated row transaction ID is updated with the current transaction ID, and
in response to an updating of all rows associated with the transaction at the persistent memory, the completed transaction ID is updated with the current transaction ID.