Patent ID: 11862234
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. The memory system of claim 1, wherein the first data line driver circuit comprises:
a first reference voltage generator configured to generate a first reference voltage based on the first code;
a first DFE generator configured to generate a first DFE positive voltage and a first DFE negative voltage based on the second code; and
a first sampler configured to determine the bit values of the first input data received through the first data line based on the first reference voltage, the first DFE positive voltage, and the first DFE negative voltage,
the second data line driver circuit comprises:
a second reference voltage generator configured to generate a second reference voltage based on the third code;
a second DFE generator configured to generate a second DFE positive voltage and a second DFE negative voltage based on the fourth code; and
a second sampler configured to determine the bit values of the second input data received through the second data line based on the second reference voltage, the second DFE positive voltage, and the second DFE negative voltage.