Patent ID: 11910620
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 8:
9. A method for fabricating a semiconductor structure, comprising:
forming a metal line;
forming a magnetic tunneling junction (MTJ) layer over the metal line, wherein the MTJ layer comprises a first material;
forming a top electrode over the MTJ layer;
forming a first dielectric layer, comprising a first portion over at least a portion of a sidewall of the top electrode and a second portion above at least a portion of the MTJ layer;
partially removing the MTJ layer to form an MTJ after forming the first dielectric layer, thereby generating residue over an outer sidewall of the first dielectric layer, wherein the residue comprises the first material, and at least a portion of a remaining portion of the MTJ layer is in direct contact with the MTJ; and
forming a second dielectric layer over the first dielectric layer to encapsulate the residue.