Patent ID: 11880595
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus, comprising:
a memory array; and
a controller coupled with the memory array and configured to cause the apparatus to:
receive, from a host system, a set of commands to write data to the memory array;
analyze a set of parameters associated with the set of commands based at least in part on receiving the set of commands;
determine whether to write the data of the set of commands to the memory array using a first mode or to write the data to the memory array using a second mode based at least in part on analyzing the set of parameters;
write the data to the memory array using the first mode based at least in part on the determining;
receive a second set of commands to write second data to the memory array;
determine whether a machine learning algorithm for determining whether to use the first mode or the second mode is tuned; and
tune the machine learning algorithm using the second set of commands, writing the second data to the memory array using the first mode or the second mode, or both based at least in part on determining whether the machine learning algorithm is tuned.