Patent ID: 11892504
Assignee: CADENCE DESIGN SYSTEMS, INC.
Field: Measurement (Instruments)
Classification: CPC G | IPC G

Claim 8:
9. A system for debugging a design under test (DUT) for metastability issues using formal verification, the system comprising:
one or more processor having instructions stored thereon that, when executed by the one or more processors, causes the one or more processors to:
determine that a functionality of the DUT failed an assertion;
inject a metastability effect to a plurality of clock domain crossing (CDC) pairs that are in a cone of influence (COI) of the assertion;
generate a plurality of first waveforms for the plurality of CDC pairs;
apply a constraint including a condition to the plurality of first waveforms; and
generate one or more second waveforms for a first subset of the plurality of CDC pairs, wherein the first subset of the CDC pairs satisfied the condition.