Patent ID: 11960922
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. A system comprising:
a processor comprising:
a first core having a first execution circuit to execute instructions, a first cache memory coupled to the first execution circuit, and a first table storage element to store a first plurality of entries each to store object metadata of an object used in a code sequence, the object metadata including a user space address of the object, wherein in response to a map add instruction of an instruction set architecture, the first table storage element is to store a user space address of a first object and a version number of the first object in a first entry of the first table storage element;
a second core having a second execution circuit to execute instructions, a second cache memory coupled to the second execution circuit, and a second table storage element to store a second plurality of entries each to store object metadata of an object used in another code sequence; and
a coherency circuit coupled to the first core and the second core, wherein in response to eviction of the first entry from the first table storage element, the coherency circuit is to send an invalidation message to the second table storage element to cause the second table storage element to update a status of an entry associated with the first object in the second table storage element to a fail state; and

a system memory coupled to the processor.