Patent ID: 11909566
Assignee: SOOCHOW UNIVERSITY
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 1:
2. The method for designing a complex-valued channel equalizer according to claim 1, wherein in the digital communication system, a complex-valued digital sequence of the nonlinear channel is denoted by s(n), a channel order is h, a channel mapping is f(⋅), a noiseless channel output is ŷ(n), an additive noise is v(n), an actual channel output y(n) is a superposition result of the noiseless channel output and the additive noise and is taken as the input data of the equalizer, an equalizer order is m, and a decision delay of the equalizer is assumed to be τ; a state ns of the channel is a data set generated by a limited character set transmitted through the channel, and a size of the data set is determined by the equalizer order and the channel order; a modulation order of a transmitted signal is M; and thus a transmission function of the channel is described by, H
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and a quantity of the state ns of the channel is determined by
ns Mh m,
in this case, an input sequence s(n)=[s(n), . . . , s(n−m 1−h)]T has ns states, after transmission through a noiseless channel, a desired channel output ŷ(n) also has ns states;
the equalizer is used to reconstruct a sequence transmitted by a transmit end according to an observed channel output vector y(n)=[y(n), y(n−1), . . . , y(n−m+1)]T with additive noise, herein y(n)=[y(n), y(n−1), . . . , y(n−m+1)]T is a distortion signal with m delays, and m is the equalizer order.