Patent ID: 11877505
Assignee: QORVO US, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A method comprising:
providing a semiconductor die on a package substrate, the semiconductor die comprising an active area and one or more metallization layers on the active area, wherein at least one wire bond is electrically connected between the semiconductor die and the package substrate; and
depositing at least one fluorinated polymer layer on the semiconductor die and on surfaces of the package substrate that are adjacent the semiconductor die by a vapor deposition process, wherein the at least one fluorinated polymer layer is arranged to conformally coat the at least one wire bond;
wherein an additional layer is arranged between the at least one fluorinated polymer layer and the one or more metallization layers, the additional layer comprising at least one of a planarization layer and a diecoat film; and
wherein the at least one wire bond is arranged to pass through an opening in the additional layer to electrically connect with the semiconductor die, and a portion of the at least one fluorinated polymer layer is arranged within the opening.