Patent ID: 11862596
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. A semiconductor package, comprising:
a redistribution substrate; and
a chip pad on the redistribution substrate, the chip pad electrically connects to the redistribution substrate;
wherein the redistribution substrate includes:
a first dielectric layer;
a second dielectric layer in contact with the first dielectric layer;
a third dielectric layer in contact with the second dielectric layer;
a first redistribution pattern in the first dielectric layer and the second dielectric layer;
a second redistribution pattern in the second dielectric layer and the third dielectric layer; and
a first insulative pattern formed in a first recess region of the first redistribution pattern,
wherein the first redistribution pattern is interposed between and electrically connects the chip pad and the second redistribution pattern,
wherein each of the first to second redistribution pattern includes:
a wire part on one surface of a corresponding one of the first to second dielectric layers, the wire part extending parallel to the one surface of the corresponding one of the first to second dielectric layers; and
a via part that extends from the wire part and penetrates the corresponding one of the first to second dielectric layers,
the first via part, the second via part and the first insulative pattern are vertically aligned.