Patent ID: 11949595
Assignee: INTEL CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. The apparatus of claim 1, further comprising a semiconductor substrate, the semiconductor substrate comprising the first set of processing element nodes and the second set of processing element nodes,
wherein the second set of processing element nodes comprises a second reflection LUT,
wherein the semiconductor substrate further comprises a third set of processing element nodes, the third set of processing element nodes defining a third hierarchy of processing element nodes, the third set of processing element nodes comprising:
a third forwarder node, and
a second target node;

wherein the first forwarder node to identify a cardinal direction for the second forwarder node from the first reflection LUT and to forward a message to the second forwarder node;
wherein the second reflection LUT is to comprise an address of the third forwarder node in the third hierarchy, the second forwarder node to identify a cardinal direction for the third forwarder node from the second reflection LUT and to forward a message to the third forwarder node; and
wherein the third forwarder node is to forward the packet to the second target node.