Patent ID: 11916146
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method comprising:
forming a dummy gate stack over a semiconductor region;
forming gate spacers, wherein the gate spacers are on opposite sides of the dummy gate stack;
replacing the dummy gate stack with a replacement gate stack, wherein the replacement gate stack comprises:
a gate dielectric;
a work-function layer over the gate dielectric; and
a high-resistance conductive layer over the work-function layer;

etching back the replacement gate stack and the gate spacers, wherein the etching back the replacement gate stack and the gate spacers comprises:
performing a first etch-back process to etch both of the gate spacers and the replacement gate stack; and
performing a second etch-back process to etch the work-function layer and the high-resistance conductive layer; and

depositing a metal layer on the work-function layer and the high-resistance conductive layer, wherein the metal layer has a lower resistivity than the high-resistance conductive layer.