Patent ID: 11942945
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 7:
8. A method of forming a semiconductor device, comprising:
forming active regions including doping areas of a substrate;
forming source/drain (S/D) regions including doping first areas of the active regions, the S/D regions representing first transistor-components, wherein second areas of the active regions which are between corresponding S/D regions are channel regions representing second transistor-components;
forming gate lines over corresponding ones of the channel regions, the gate lines representing third transistor-components; and
forming metal-to-S/D (MD) contact structures over corresponding ones of the S/D regions, the MD contact structures representing fourth transistor-components; and
the forming the active regions, the forming the S/D regions, the forming the MD contact structures and the forming the gate lines resulting in:
a first set of the first to fourth transistor-components connected as corresponding transistors that define a first time delay circuit having a first input configured to receive a first clock signal and having a first output configured to generate a second clock signal from the first clock signal;
a second set of the first to fourth transistor-components connected as corresponding transistors that define a second time delay circuit having a second input configured to receive the second clock signal and having a second output configured to generate a third clock signal from the second clock signal;
a third set of the first to fourth transistor-components connected as corresponding transistors that define a master-slave flip-flop that includes:
a gated input circuit,
a master latch,
a slave latch, and
a transmission gate coupled between the master latch and the slave latch, wherein the master latch is coupled between the gated input circuit and the transmission gate and configured to receive the first clock signal and the second clock signal to control a transmission state of the transmission gate, and the gated input circuit is configured to have an input transmission state controlled by the third clock signal at the second output of the second time delay circuit.