Patent ID: 11948918
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A method comprising:
forming a redistribution structure over a semiconductor structure, wherein the semiconductor structure comprises a first connector, wherein forming the redistribution structure comprises:
forming a first insulating layer directly on the semiconductor structure;
forming a first metallization pattern, the first metallization pattern comprising a base via and a first redistribution line, the base via extending through the first insulating layer over the first connector of the semiconductor structure; and
forming stacked vias over the first insulating layer, the stacked vias being electrically coupled to the base via, wherein a first via of the stacked vias physically contacts the first redistribution line, wherein the stacked vias are completely non-overlapping the base via, the stacked vias overlapping each other; and

forming a second connector over the redistribution structure, wherein the stacked vias electrically couple the first connector to the second connector, wherein the stacked vias are completely non-overlapping the first connector in a cross-sectional view, wherein the second connector is completely non-overlapping the stacked vias in the cross-sectional view.