Patent ID: 11937421
Assignee: SK HYNIX INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A semiconductor memory device comprising:
a gate stack including a plurality of conductive patterns stacked apart from each other, the plurality of conductive patterns includes at least one gate pattern which is formed at the part of the gate stack and at least one drain select pattern formed over the gate pattern;
a plurality of channel structures formed in the gate stack; and
a plurality of contact plugs arranged on the gate stack and overlapped with the plurality of channel structures, respectively,
wherein at least one of the channel structures comprises:
a first channel pillar formed in a part of the gate stack, the first channel pillar including a first channel layer with a cylindrical shape and a second channel layer formed to cover an upper surface of the first channel layer;
a memory layer configured to surround a bottom surface and a side surface of the first channel layer pillar, and upper surface of the memory layer higher than upper surfaces of the first and second channel layer;
a second channel pillar formed in the gate stack to connect an upper surface of the first channel pillar to the contact plug; and
a gate insulation layer configured to surround a side surface of the second channel pillar,
wherein a junction region is formed in an upper portion of the second channel pillar and an upper surface and an upper sidewall of the junction region are inserted into the contact plug.