Patent ID: 11942372
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A method for manufacturing an integrated chip, comprising:
forming a transistor structure over a substrate, wherein the transistor structure comprises a pair of source/drain regions and a gate electrode between the source/drain regions;
forming a first dielectric layer over the pair of source/drain regions and around the gate electrode;
forming a gate capping layer over the gate electrode;
performing a selective etch and deposition process to form a dielectric protection layer on the gate capping layer while forming openings within the first dielectric layer over the pair of source/drain regions, wherein the selective etch and deposition process reduces a thickness of the gate capping layer;
forming a plurality of source/drain contacts within the openings; and
forming a plurality of conductive contacts over the gate electrode and the plurality of source/drain contacts.