Patent ID: 11923410
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 22:
23. An integrated circuit comprising:
a nanowire comprising a semiconductor material, the nanowire having a bottommost surface;
a gate structure in contact with and wrapped around the nanowire the gate structure defining a channel region in the nanowire;
a source region in contact with the nanowire;
a drain region in contact with the nanowire such that the channel region of the nanowire is between the source region and the drain region;
a first isolation region under an entirety of the source region and having a top surface in contact with a portion of a bottom surface of the source region laterally adjacent to the channel region, the first isolation region having an uppermost surface above the bottommost surface of the nanowire; and
a second isolation region under an entirety of the drain region and having a top surface in contact with a portion of a bottom surface of the drain region laterally adjacent to the channel region, the second isolation region having an uppermost surface above the bottommost surface of the nanowire, wherein the semiconductor material is a first semiconductor material, the integrated circuit further comprising a fin stub of a second semiconductor material, the fin stub having a top surface spaced from the nanowire and laterally opposed sidewalls extending down from the top surface of the fin stub, wherein a first one of the laterally opposed sidewalls of the fin stub contacts the first isolation region and a second one of the laterally opposed sidewalls of the fin stub contacts the second isolation region.