Patent ID: 11894103
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 7:
8. The apparatus of claim 1, further comprising:
a third word line tile comprising a third plurality of word line plates stacked in the vertical direction, the third plurality of word line plates comprising a third word line plate that includes a plurality of word lines in the first plane, each word line of the plurality of word lines coupled with one or more respective memory cells of a plurality of memory cells;
a dielectric material positioned between the plurality of first word lines and the plurality of word lines, wherein a first portion of the dielectric material extends in a first direction within the first plane, and wherein a second portion of the dielectric material extends in a second direction within the first plane; and
a third set of electrodes coupled with a third word line decoder and each coupled with a respective word line plate of the third plurality of word line plates, the third word line decoder operable to activate one of the third plurality of word line plates based at least in part on applying a third voltage to a respective electrode of the third set of electrodes.