Patent ID: 11942155
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H  B | IPC G  H

Claim 0:
1. A memory device, comprising:
a memory cell that randomly presents either a first logic state or a second logic state, the memory cell comprising:
a plurality of first nanostructures extending along a first lateral direction;
a plurality of second nanostructures extending along the first lateral direction;
a dielectric fin structure disposed between the plurality of first nanostructures and the plurality of second nanostructures, wherein a first sidewall of each of the plurality of first nanostructures facing toward or away from a second lateral direction and a second sidewall of each of the plurality of second nanostructures facing toward or away from the second lateral direction are in contact with the dielectric fin structure, the second lateral direction being perpendicular to the first lateral direction;
a first gate structure wrapping around each of the plurality of first nanostructures except for the first sidewall; and
a second gate structure wrapping around each of the plurality of second nanostructures except for the second sidewall.