Patent ID: 11899613
Assignee: KEPLER COMPUTING INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G  Y | IPC G

Claim 12:
13. A method of processing an instruction for a distributed logic having an accelerator core and a processor core that are tightly coupled in a multi-dimensional packaging configuration, the method comprising:
fetching the instruction;
determining whether a type of the instruction is for the processor core or for the accelerator core, wherein the processor core is part of a compute die while the accelerator core is part of an accelerator die, wherein the processor core is coupled to a first memory, wherein the accelerator core is coupled to a second memory, wherein the processor core and/or the accelerator core includes ferroelectric logic;
assembling the instruction in a command packet that includes data address associated with the second memory; and
sending the command packet to the accelerator core via an interconnect.