Patent ID: 11888025
Assignee: WINBOND ELECTRONICS CORP.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 0:
1. A method of forming a silicon on insulator (SOI) device, comprising:
providing a wafer comprising a bottom silicon substrate, a buried oxide layer and a top silicon layer stacked from bottom to top;
removing the bottom silicon substrate to expose the buried oxide layer;
providing a high resistivity substrate;
depositing a trap-rich layer on the high resistivity substrate, comprising:
depositing a germanium layer on the high resistivity substrate; and
annealing the germanium layer to form the trap-rich layer having germanium nano-dots;

depositing an oxide layer on the trap-rich layer, wherein a thickness of the oxide layer is thinner than that of the buried oxide layer; and
bonding the oxide layer with the buried oxide layer, wherein the germanium nano-dots have dangling bonds capable of trapping negative carriers to wipe out induced positive charges at an interface of the buried oxide layer and the oxide layer.