Patent ID: 11971831
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 18:
19. A method of transferring data from a source domain to a sink domain across a clock boundary using first-in, first-out (FIFO) buffer circuitry, the method comprising:
storing the data to be transferred across the clock domain boundary using one or more data storage elements;
maintaining a source state vector indicative of a state of the FIFO buffer circuitry in the source domain and a sink state vector indicative of a state of the FIFO buffer circuitry in the sink domain;
stabilising, using synchronisation circuitry in each of the source domain and the sink domain, a signal indicative of a received state vector received from the other of the source domain and the sink domain;
storing, using the synchronisation circuitry, the received state vector, wherein for at least one of the source domain and the sink domain, the respective synchronisation circuitry is clock-gated by an enable signal; and
for at least one of the source domain and the sink domain:
advancing, in response to a change in the state of the FIFO buffer circuitry in the respective domain, the respective state vector by controlling the enable signal to enable output of one or more elements of the received state vector.