Patent ID: 11871572
Assignee: nan
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A method of forming an integrated structure, comprising:
forming a vertical stack of alternating first and second levels; the first levels comprising first material and the second levels comprising second material;
forming an opening to extend through the stack, the opening having a peripheral sidewall;
forming charge-blocking material adjacent the peripheral sidewall;
forming charge-storage material adjacent the charge-blocking material;
forming gate-dielectric material adjacent the charge-storage material;
forming channel material adjacent the gate-dielectric material;
removing the second material to leave first voids;
forming conductive material within the first voids;
forming high-k dielectric material within the first voids to line the first voids;
removing portions of the high-k dielectric material above and below the conductive material;
removing the first material to leave second voids;
forming strips within the second voids to narrow a vertical thickness of the second voids; and
extending the second voids through the charge-storage material to divide the charge-storage material into vertically-spaced segments.