Patent ID: 11915992
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 5:
6. A method for forming a package structure, comprising:
forming a semiconductor die over a first side of an interconnect structure, wherein the semiconductor die has a first height;
forming a first stacked die package structure over the first side of the interconnect structure, wherein the first stacked die package structure has a second height, and the second height is greater than the first height;
forming an underfill layer below the first stacked die package structure, wherein the underfill layer covers sidewalls of the semiconductor die;
forming a package layer between the semiconductor die and the first stacked die package structure, wherein the package layer is in contact with the sidewalls of the semiconductor die; and
forming a lid structure over the semiconductor die and the first stacked die package structure, wherein the lid comprises a main portion and a protruding portion extending from the main portion, and the protruding portion is directly over the semiconductor die.