Patent ID: 11961812
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor package comprising:
a lower redistribution layer including an insulating pattern having an opening and a via in the opening;
a first semiconductor chip on the lower redistribution layer, the first semiconductor chip including a chip pad on a lower surface of the first semiconductor chip, a passivation layer, and a pad bump, the pad bump extending through the passivation layer and being connected to the chip pad; and
a first encapsulant on the lower redistribution layer and the first semiconductor chip,
wherein the opening of the insulating pattern defines a lower surface and an outer side surface of the pad bump, and
wherein the via includes a central protrusion in physical contact with the lower surface of the pad bump; a first portion in physical contact with a lower surface of the passivation layer and the outer side surface of the pad bump; and a second portion spaced apart from the passivation layer.