Patent ID: 11955085
Assignee: LG DISPLAY CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A gate driver comprising a plurality of signal transmission units cascade-connected via a carry line of an nth signal transmission unit to which a carry signal from other signal transmission units is applied,
wherein n is a positive integer and the nth signal transmission unit includes:
a first circuit unit configured to receive the carry signal from the other signal transmission units to charge a first control node;
a second circuit unit including an inverter circuit configured to discharge a second control node according to a voltage of the first control node; and
a third circuit unit configured to output a gate signal based on a first high potential voltage and a first low potential voltage based on potentials of the first control node and the second control node,

wherein the inverter circuit includes:
a first transistor connected between a second high potential voltage line and a first node;
a second transistor having a gate connected to the first node and turned on according to a voltage of the first node to charge the second control node to a second high potential voltage applied to the second high potential voltage line;
a third transistor having a gate connected to the first control node, a first electrode connected to the first node, and a second electrode directly connected to the second control node; and
a fourth transistor having a gate connected to the first control node, a first electrode directly connected to the second control node, and a second electrode connected to a second low potential voltage line,

the third transistor and the fourth transistor are turned on according to the voltage of the first control node to discharge the second control node to a second low potential voltage applied to the second low potential voltage line, and
the third transistor and the fourth transistor are connected in series between the first node and the second low potential voltage line.