Patent ID: 11894045
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. A system, comprising:
a memory device comprising compute components configured to perform bit vector operations; and
a host, comprising:
a sequencer that comprises a very large instruction word (VLIW) type controller configured to operate on compute commands associated with the bit vector operations and to:
provide instructions for the bit vector operations to be performed by a compute component of the memory device;
provide information to indicate a length of bit vectors and a source row address for retrieval of the bit vectors; and
provide different information to indicate a length of data values and a destination row address for transfer of the data values after performance of the bit vector operations;

control logic configured to issue the compute commands to the sequencer in response to a signal from a processing resource of the host; and
timing circuitry selectably coupled to the memory device, the timing circuitry configured to control timing, associated with the bit vector operations, of performance of a compute operation using the compute components.