Patent ID: 11879919
Assignee: CYPRESS SEMICONDUCTOR CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 7:
8. A device, comprising:
a balance current generating circuit configured to generate a balance current;
a sequencer circuit configured to receive a clock signal and generate switch control signals in synchronism with the clock signal;
a switching circuit comprising a plurality of switches, the switching circuit configured to, in response to the switch controls signals,
periodically couple an energizing voltage to a first input/output (I/O),
periodically enable an inductance current path between a second I/O and a modulator node, and
periodically couple the balance current to the modulator node; and

an analog-to-digital converter (ADC) circuit configured to convert a modulator voltage at the modulator node into a digital value; wherein
the sequencer circuit, switching circuit and ADC circuit are formed with a same integrated circuit substrate.