Patent ID: 11869616
Assignee: CYPRESS SEMICONDUCTOR CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 11:
12. A memory device, comprising:
one or more memory banks; and
a built-in self-test (BIST) unit configured to:
perform a memory test on the one or more memory banks of the memory device using a first algorithm;
generate miscompare results responsive to performing the memory test on the one or more memory banks of the memory device;
determine failure diagnostic information based on the miscompare results;
generate an error packet comprising the failure diagnostic information and the miscompare results;
determine that the first algorithm was used to perform the memory test associated with the error packet;
tag the error packet with an identifier to the first algorithm to generate a tagged error packet; and
place the tagged error packet in a queue of a plurality of error packets to generate a queued error packet.