Patent ID: 11895836
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 4:
5. The IC according to claim 2, wherein the memory device comprises:
first and second individual source/drain regions in the semiconductor substrate;
a common source/drain region in the semiconductor substrate, laterally spaced between the first and second individual source/drain regions, wherein the common source/drain region is separated from the first individual source/drain region by a first channel region, and wherein the common source/drain region is separated from the second individual source/drain region by a second channel region;
an erase gate electrode over the common source/drain region;
first and second floating gate electrodes respectively over the first and second channel regions;
first and second control gate electrodes respectively overlying the first and second floating gate electrodes; and
the first select gate electrode and a second select gate electrode respectively on the first and second channel regions, and laterally spaced from the common source/drain region respectively by the first and second floating gate electrodes.