Patent ID: 11917038
Assignee: INTEL CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. An apparatus comprising:
at least one memory;
instructions in the apparatus; and
processor circuitry to execute the instructions to:
determine a compression policy of a destination node, the compression policy corresponding to whether the destination node supports a compression of an input packet;
identify two or more different compression functions to apply to the input packet based on a comparison of a first payload type of the input packet to known payload types associated with compression functions, the comparison to determine which known payload types are similar to the first payload type;
select a first compression function of the two or more compression functions to compress the input packet based on the compression policy and a first amount of reduction of the input packet, the first amount of reduction by the first compression function being greater than a second amount of reduction of the input packet compressed utilizing a second compression function; and
modify a protocol identifier of the input packet to inform the destination node of the first compression function utilized to compress the input packet.