Patent ID: 11954340
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A nonvolatile memory device comprising:
a plurality of nonvolatile memories connected with a plurality of data lines,
wherein a first nonvolatile memory of the plurality of nonvolatile memories includes:
a first plurality of input/output pads connected with the plurality of data lines;
a first enable input pad;
a first enable output pad; and
a first chip address initialization circuit,

wherein a second nonvolatile memory of the plurality of nonvolatile memories includes:
a second plurality of input/output pads connected with the plurality of data lines;
a second enable input pad;
a second enable output pad; and
a second chip address initialization circuit,

wherein each of the first and second chip address initialization circuits is configured to:
receive a current chip address through the plurality of input/output pads;
generate a next chip address by using the current chip address;
output a next enable signal through the corresponding enable output pad of the first and second enable output pads; and
output the next chip address through the plurality of input/output pads, and

wherein the first enable output pad and the second enable input pad are connected,
wherein the next enable signal is center-aligned with a window of the next chip address.