Patent ID: 11894278
Assignee: nan
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for producing a wafer map, the method comprising:
step (a) of producing a circular layer corresponding to the horizontal and vertical dimensions in the same plane of an actual semiconductor wafer;
step (b) of producing an edge region on a circumference portion of the circular layer;
step (c) of producing one central chip with reference to the size of one of a plurality of chips on the central point of the circular layer;
step (d) of repeatedly producing chips having the same size as the central chip sequentially from the central chip to the edge region using the size of chips and gap between the chips;
step (e) of producing, when one of the chips is produced in the edge region, a chip layer including all of the chips on the circular layer; and
step (f) of producing a dynamic wafer map by producing respective layers for a plurality of components included in one of the chips to produce GIS-based spatial wafer map, wherein the plurality of components includes a plurality of banks included in one of the chips, a mat that divides one of the banks into a multiple part, and a plurality of cells included in one of the mats, and wherein the step (f) comprises:
step (f1) of producing a bank list based on the number of banks in the column and row directions included in the chips;
step (f2) of producing a bank layer based on the size of banks and a gap between banks;
step (f3) of producing a mat list according to a bank type designated for each bank; and
step (f4) of producing a mat layer based on the size of mats and the gap between mats;

wherein, GIS is defined as Geographic Information System.