Patent ID: 11909565
Assignee: CADENCE DESIGN SYSTEMS, INC.
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. An integrated circuit, comprising:
a receiver circuit having a slicer and decision feedback equalization (DFE) circuitry, the DFE circuitry having a DFE coefficient, the slicer having a reference voltage; and
control circuitry configured to calibrate the DFE coefficient by:
measuring, at a first sample timing and by varying the DFE coefficient, a first eye height while receiving a first data pattern;
measuring, at the first sample timing by varying the DFE coefficient, a second eye height while receiving a second data pattern; and
based on the first eye height and the second eye height, adjusting the DFE coefficient to a first setting.