Patent ID: 11887888
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Semiconductors (Electrical engineering)
Classification: CPC H  C | IPC H

Claim 9:
10. A method of forming an integrated circuit, comprising:
forming a plurality of metal layers over a metal seed layer located on surfaces of an opening in a dielectric layer located over a semiconductor substrate, the forming of each metal layer including:
electroplating a current metal layer on a previous metal layer without annealing the previous metal layer;
rinsing the current metal layer with water after the electroplating; and
drying the current metal layer after the rinsing;

annealing the plurality of metal layers only after electroplating a last one of the plurality of metal layers, the annealing forming a final metal layer; and
forming metal lines from the final metal layer, the metal lines electrically connecting electronic components formed in or over the semiconductor substrate.