Patent ID: 11861369
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A processing-in-memory (PIM) device comprising:
a first memory bank configured to output data that corresponds to a plurality of elements of a first matrix based on a first bank access control signal and a bank column address signal;
a second memory bank configured to output data that corresponds to a plurality of elements of a second matrix based on a second bank access control signal and the bank column address signal;
a third memory bank configured to store arithmetic data based on a delayed bank access control signal and a delayed column address signal;
a column control circuit configured to generate the first bank access control signal, the second bank access control signal, and an arithmetic operation signal based on a calculation signal, which is generated by decoding an external command signal received from an external device, and configured to generate the bank column address signal based on a column address signal, which is generated based on an input address signal received from the external device; and
a multiplication-accumulative addition (MAC) operator configured to generate the arithmetic data by performing a calculation on data that is output from the first and second memory banks, provide the arithmetic data to the third memory bank, and generate the delayed bank access control signal and the delayed column address signal based on the first bank access control signal, the second bank access control signal, the arithmetic operation signal, and the bank column address signal.