Patent ID: 11928588
Assignee: UIF (UNIVERSITY INDUSTRY FOUNDATION), YONSEI UNIVERSITY
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. The multi-bit cell array according to claim 6, wherein the final summation unit includes:
a first final summation line which receives the first group sum value output from the at least one multi-bit unit to calculate a first final sum value; and
a second final summation line which receives the second group sum value output from the at least one multi-bit unit to calculate a second final sum value,
the final summation unit adjusts the first group sum value and the second group sum value at a specific ratio according to a switching operation of a first final switch connected between at least one multi-bit unit and the first final summation line and a second final switch connected between at least one multi-bit unit and the second final summation line, and sums the first final sum value and the second final sum value by a switching operation of a third final switch connected between the first final summation line and the second final summation line to output the final output value.