Patent ID: 11868244
Assignee: QUALCOMM INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. A compressed memory system of a processor-based system, comprising:
a memory partitioning circuit configured to partition a memory region into a plurality of data regions, each data region associated with a respective priority level;
a cache line selection circuit configured to select (i) a first cache line from a first data region of the plurality of data regions and (ii) a second cache line from a second data region of the plurality of data regions, wherein the first data region has a higher priority level than the second data region;
a compression circuit configured to compress (i) the first cache line to obtain a first compressed cache line and (ii) the second cache line to obtain a second compressed cache line; and
a cache line packing circuit configured to:
in accordance with a determination that the first cache line is compressible:
write (i) the first compressed cache line to a first predetermined portion of a candidate compressed cache line, and (ii) either the second cache line or a second portion of the second compressed cache line to a second predetermined portion of the candidate compressed cache line, wherein the first predetermined portion is larger than the second predetermined portion; and

in accordance with a determination that (i) the first cache line is not compressible, (ii) the second cache line is not compressible, or (iii) the second compressed cache line does not fit within the second predetermined portion of the candidate compressed cache line;
set an overflow pointer in the candidate compressed cache line, wherein the overflow pointer points to one of a plurality of overflow blocks depending on compressibility of the second cache line or a size of the second compressed cache line, and wherein each overflow block of the plurality of overflow blocks is of a different size.