Patent ID: 11930696
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. A method comprising:
forming a plurality of carbon nanotubes substantially parallel to and spaced apart from each other, wherein the plurality of carbon nanotubes are substantially aligned to a same plane that is over and in physical contact with a top surface of a dielectric layer;
etching the dielectric layer to remove a portion of the dielectric layer directly underlying and overlapped by the plurality of carbon nanotubes;
forming a gate stack comprising:
a gate dielectric comprising a first portion directly over the plurality of carbon nanotubes, and a second portion directly under the plurality of carbon nanotubes; and
a gate electrode comprising a third portion over the first portion of the gate dielectric, and a fourth portion under the second portion of the gate dielectric;

forming a gate spacer, wherein sidewalls of the gate stack and the gate spacer are in contact with each other, wherein the first portion of the gate dielectric and the third portion of the gate electrode extend higher than a bottom surface of the gate spacer, and the second portion of the gate dielectric and the fourth portion of the gate electrode extend lower than the bottom surface of the gate spacer;
forming a contact etch stop layer extending on a sidewall of the gate spacer, wherein the contact etch stop layer is further over and contacting the carbon nanotubes; and
forming an inter-layer dielectric over the contact etch stop layer.