Patent ID: 11870592
Assignee: QUALCOMM INCORPORATED
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An apparatus comprising:
a memory;
a transceiver; and
at least one processor coupled to the memory and the transceiver, wherein the apparatus is configured to:
communicate, with a second wireless communication device, a downlink control information (DCI) message that schedules a first communication signal and includes a second grant for transmitting a first feedback associated with the first communication signal;
communicate, with the second wireless communication device, a first grant for transmitting the first feedback associated with the first communication signal, the second grant being communicated before the first grant for transmitting the first feedback, wherein the first grant comprises a physical uplink control channel (PUCCH) trigger and the first grant does not schedule a physical downlink shared channel (PDSCH) communication; and
communicate, with the second wireless communication device, the first feedback based on the first grant.