Patent ID: 11874773
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus comprising:
a processor core to access a memory and a cache that stores cache lines; and
a prefetch circuit to prefetch a cache line into the cache from the memory, wherein the prefetch circuit is to:
track page and cache line accesses to the cache for a single access signature,
generate a spatial bit pattern, for the cache line accesses for each page of a plurality of pages, that is shifted to a first cache line access for each page,
generate a single spatial bit pattern for the single access signature for each of the spatial bit patterns that have a same spatial bit pattern to form a plurality of single spatial bit patterns,
perform a logical OR operation on the plurality of single spatial bit patterns to create a first modulated bit pattern for the single access signature,
perform a logical AND operation on the plurality of single spatial bit patterns to create a second modulated bit pattern for the single access signature,
receive a prefetch request for the single access signature, and
perform a prefetch operation for the prefetch request using the first modulated bit pattern when a threshold is not exceeded and the second modulated bit pattern when the threshold is exceeded.