Patent ID: 11923405
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A semiconductor device, comprising:
a substrate;
a first insulating layer disposed on the substrate;
first, second, and third conductive features disposed in the first insulating layer;
a capacitor structure disposed on the first insulating layer and comprising a first electrode, a first dielectric layer, a second electrode, a second dielectric layer, and a third electrode sequentially stacked;
a first via connected to the first electrode, the third electrode, and the third conductive feature;
a second via connected to the second electrode and the second conductive feature;
a third via connected to the first conductive feature; and
a second insulating layer disposed over the capacitor structure, wherein each of the first, second, and third vias penetrates the second insulating layer, wherein the second via has a first sidewall in physical contact with the second insulating layer and a second sidewall under the first sidewall and in physical contact with the second electrode, and wherein a slope of the first sidewall is larger than a slope of the second sidewall with respect to a top surface of the substrate.