Patent ID: 11955480
Assignee: STMICROELECTRONICS (TOURS) SAS
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of manufacturing an integrated circuit, comprising:
performing a local etching of a portion of a substrate to define in the substrate a first region having a first thickness and a second region having a second thickness smaller than the first thickness;
forming a three-dimensional capacitor inside and on top of the first region;
forming on the second region first and second connection terminals respectively connected to first and second electrodes of the three-dimensional capacitor; and
forming third and fourth connection terminals respectively arranged opposite the first and second connection terminals, on a side of the substrate opposite to the first and second connection terminals;
forming a first conductive via crossing the substrate and connecting the third connection terminal to the first connection terminal; and
forming a second conductive via crossing the substrate and connecting the fourth connection terminal to the second connection terminal.