Patent ID: 11923446
Assignee: GLOBALFOUNDRIES U.S. INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A semiconductor device comprising:
a buffer layer on a substrate;
an active region above the substrate, the active region comprising a channel layer disposed on the buffer layer, and a barrier layer disposed on the channel layer;
source and drain electrodes in contact with the channel layer;
a gate on the barrier layer, the gate is laterally between the source and drain electrodes, the gate has an upper surface;
a polysilicon layer above the barrier layer, the polysilicon layer has a lower surface, wherein the polysilicon layer comprises heavily doped regions and lightly doped regions, and wherein the polysilicon layer is positioned laterally adjacent to the gate and the lower surface of the polysilicon layer is at a lower elevation than the upper surface of the gate;
a silicide layer on each of the heavily doped regions; and
an isolation layer above the substrate, the isolation layer being adjacent to the channel layer, wherein the polysilicon layer is positioned above the isolation layer.