Patent ID: 11870449
Assignee: INTEL CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 12:
13. A non-transitory computer-readable storage medium with an executable computer program stored thereon, the program instructing a processor to:
generate, by a phase-locked loop (PLL), an output clock signal based on a reference clock signal;
generate a control signal to cause the PLL to adjust a frequency signal of the PLL to provide an adjusted frequency signal based on a digital signal of the PLL, the digital signal being generated based on the adjusted frequency signal;
sample the digital signal of the PLL;
determine a distribution of the sampled digital signal of the PLL per each respectively received digital-to-time converter (DTC) code from among generated DTC codes; and
generate a correction signal based on the distribution,
wherein the frequency signal is adjusted using a correction circuit that comprises;
a code ramp configured to generate the DTC codes; and
a statistics processor configured to generate the correction signal,

wherein the correction circuit generates the control signal based upon the correction signal and a generated DTC code from among the generated DTC codes.