Patent ID: 11863183
Assignee: KEPLER COMPUTING INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 16:
17. An apparatus comprising:
a 5-input majority gate with an integrated AND function, wherein the 5-input majority gate includes a non-linear polar material, wherein the 5-input majority gate comprises a first set of capacitors of different sizes, and wherein one input of the 5-input majority gate is coupled to a bias;
an inversion circuitry coupled to an output of the 5-input majority gate; and
a 7-input majority gate with an integrated AND function, wherein the 7-input majority gate having the non-linear polar material, wherein the 7-input majority gate comprises a second set of capacitors of different sizes, wherein an output of the inversion circuitry is coupled to two inputs of the 7-input majority gate, wherein one input of the 7-input majority gate is coupled to the bias, and wherein the 5-input majority gate includes:
a first input coupled to a first capacitor of a first size;
a second input coupled to a second capacitor of the first size;
a third input coupled to a third capacitor of a second size;
a fourth input coupled to a fourth capacitor of the second size; and
a fifth input coupled to a fifth capacitor of the first size, wherein the first capacitor, the second capacitor, the third capacitor, the fourth capacitor, and the fifth capacitor are part of the first set of capacitors.