Patent ID: 11917828
Assignee: MACRONIX INTERNATIONAL CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A semiconductor device comprising:
a three-dimensional (3D) array of memory cells; and
a plurality of common source lines (CSLs) configured to separate the 3D array of memory cells into a plurality of portions, each portion of the plurality of portions being between two adjacent CSLs and comprising:
a plurality of conductive layers separated from each other by insulating layers; and
a plurality of vertical channels being arranged orthogonally through the plurality of conductive layers and the insulating layers, each of the plurality of vertical channels comprising a string of memory cells,
wherein a top part of each portion of one or more portions of the plurality of portions comprises one or more string select line (SSL) cuts configured to separate the portion into multiple independent units, and
wherein each SSL cut of the one or more SSL cuts comprises an insulating material and configured to separate two adjacent units of the portion, and wherein a top part of at least one vertical channel of the plurality of vertical channels is covered by a corresponding SSL cut of the one or more SSL cuts and filled with the insulating material of the corresponding SSL cut.