Patent ID: 11900114
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 24:
25. A non-transitory machine readable medium that stores code that when executed by a machine causes the machine to perform a method comprising:
translating a single instruction into one or more instructions of a different instruction set architecture, the single instruction having fields to specify an opcode and locations of a first source matrix, a second source matrix, and a destination matrix, the opcode indicating that execution circuitry is to cause a matrix operations accelerator to detect close to but non zero values of corresponding elements of the first source matrix and the second source matrix that would generate inconsequential results when operated on, skip operations that would generate inconsequential results based on the detected close to but non zero values of the corresponding elements by disabling a corresponding circuit of the matrix operations accelerator, operate on other elements of the first source matrix with a corresponding other element of the second source matrix by a corresponding circuit of the matrix operations accelerator to generate a resultant, and store the resultant in a corresponding element in the destination matrix;
decoding the one or more instructions of the different instruction set architecture into decoded one or more instructions with a decoder of a hardware processor; and
executing the decoded one or more instructions with an execution circuit of the hardware processor.