Patent ID: 11915772
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. A memory in a data storage device, the memory comprising:
a plurality of memory cells;
means for receiving, from a controller of the data storage device, a first command specifying an initial voltage level and a digital-to-analog converter (DAC) shift;
means for receiving, from the controller of the data storage device, a second command a plurality of times; and
means for each time in response to receiving the second command:
(a) reading data from a plurality of memory cells in the memory using a read voltage level;
(b) sending the data read from the plurality of memory cells to the controller; and
(c) incrementing the read voltage threshold by a multiple of the DAC shift;
wherein:
a first time the memory receives the second command, the plurality of memory cells are read using the initial read voltage threshold;
each subsequent time the memory receives the second command, the plurality of memory cells are read using the initial read voltage threshold incremented by a different multiple of the DAC shift; and
the memory incrementing the read voltage threshold in response to receiving the second commands avoids a latency that would be incurred by the controller specifying an incremented read voltage threshold.