Patent ID: 11972503
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A graphics processor that is operable to execute a graphics processing pipeline that comprises plural processing stages including an early culling tester followed a renderer; the graphics processor comprising:
plural culling test data buffers including at least a first culling test data buffer and a second culling test data buffer, wherein each of the plural culling test data buffers is operable to store a respective set of data values for use by the early culling tester; and
a processing circuit configured to maintain information that indicates which, if any, of the plural culling test data buffers are expected to be accessed by a processing stage of the graphics processing pipeline after the early culling tester, wherein:
the information indicates whether or not a processing stage of the graphics processing pipeline after the early culling tester is expected to access the first culling test data buffer; and
the information separately indicates whether or not a processing stage of the graphics processing pipeline after the early culling tester is expected to access the second culling test data buffer;

wherein the graphics processor is configured to control the early culling tester using information maintained by the processing circuit.