Patent ID: 11900175
Assignee: SHANGHAI BIREN TECHNOLOGY CO., LTD
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A computing equipment, comprising a first computing core, a first memory, and the computing device comprises:
a scratchpad memory, coupled to the first memory;
a second computing core, configured for acceleration in a specific field, and coupled to the scratchpad memory;
a first hardware queue, configured to receive a load request from the first computing core, and coupled to the first computing core and the first memory, wherein the load request instructs to load data from the first memory to the scratchpad memory;
a second hardware queue, configured to receive an execution request from the first computing core, and coupled to the first computing core and the scratchpad memory, wherein the execution request instructs to extract data from the scratchpad memory to the second computing core for execution; and
a synchronization unit, coupled to the first hardware queue and the second hardware queue, wherein the synchronization unit is configured to use a synchronization channel, synchronization channel configuration information in the load request in the first hardware queue, and synchronization channel configuration information in the execution request in the second hardware queue to make triggering of the load request and the execution request to cooperate with each other,
wherein the first computing core is configured for general graphics processing, the computing device is coupled to the first computing core and the first memory, and the first computing core is configured to add a load request to a first hardware queue in the computing device and add an execution request to a second hardware queue in the computing device.