Patent ID: 11862064
Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. The array substrate of claim 10, wherein:
the driving signal lines includes first clock signal lines, an initialization signal line, a first level signal line, a second clock signal line and a second level signal line;
the GOA circuit includes four thin film transistors and a capacitor, and the four thin film transistors are sequentially arranged in the horizontal direction;
a layout model of the first thin film transistor is that a gate of the first thin film transistor serves as the input terminal and is connected to one of the first clock signal lines, a first electrode of the first thin film transistor serves as the input terminal and is connected to the initialization signal line, and a second electrode of the first thin film transistor serves as the intermediate node and is connected to a first GOA internal wire;
a layout model of the second thin film transistor is that a gate of the second thin film transistor serves as the input terminal and is connected to the first level signal line, a first electrode of the second thin film transistor serves as the intermediate node and is connected to the first GOA internal wire, and a second electrode of the second thin film transistor serves as the intermediate node and is connected to a second GOA internal wire;
a layout model of the third thin film transistor is that a gate of the third thin film transistor serves as the intermediate node and is connected to the second GOA internal wire, a first electrode of the third thin film transistor serves as the input terminal and is connected to the second clock signal line, and a second electrode of the third thin film transistor serves as the output terminal and is connected to a scan line corresponding to a row where the GOA circuit is located;
a layout model of the fourth thin film transistor is that a gate of the fourth thin film transistor serves as the input terminal and is connected to another of the first clock signal lines, a first electrode of the fourth thin film transistor serves as the input terminal and is connected to the second level signal line, and a second electrode of the fourth thin film transistor serves as the output terminal and is connected to the scan line corresponding to the row where the GOA circuit is located; and
a first plate of the capacitor is connected to the second GOA internal wire, and a second plate of the capacitor is connected to the scan line corresponding to the row where the GOA circuit is located.