Patent ID: 11921668
Assignee: BEIJING TSINGMICRO INTELLIGENT TECHNOLOGY CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A processor array, comprising:
a plurality of processing elements arranged in a two-dimensional array, wherein the two-dimensional array comprises a first edge row and a second edge row parallel to the first edge row, and a first edge column and a second edge column parallel to the first edge column;
wherein a first end of the first edge row and a first end of the first edge column have a first shared processing element, and a second end of the first edge row and a first end of the second edge column have a second shared processing element; and
wherein a first end of the second edge row and a second end of the first edge column have a third shared processing element, and a second end of the second edge row and a second end of the second edge column have a fourth shared processing element;
wherein the processor array further comprises:
a plurality of first load units correspondingly arranged and connected to processing elements of the first edge row, respectively, and the plurality of the first load units are respectively connected directly to the processing elements of the first edge column;
a plurality of second load units correspondingly arranged and connected to processing elements of the first edge column, respectively;
a plurality of first store units correspondingly arranged and connected to processing elements of the second edge column, respectively; and
a plurality of second store units correspondingly arranged and connected to processing elements of the second edge row, respectively.