Patent ID: 11899067
Assignee: SHANGHAI JIAO TONG UNIVERSITY
Field: Electrical machinery, apparatus, energy (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 5:
6. A testing method suitable for SMs in a cascaded converter under a nearest level control (NLC) modulation, wherein the testing method is based on the testing circuit for the plurality of SMs in the cascaded converter according to claim 1 or a testing system by using a current control method, wherein the testing system comprises
the current generator, the testing module group, a cascaded converter system parameter model, a current controller, and a voltage controller; wherein
the current generator is used to provide a testing current, with a specific waveform, to the testing module group;
the testing module group comprises a plurality of testing arms, each of the plurality of testing arms comprises a plurality of tested SMs connected in series, and the plurality of testing arms are in a reverse series connection structure, in which DC voltage components in capacitor voltages of the plurality of tested SMs of the plurality of testing arms are equal in magnitude but opposite in direction, or
the testing module group comprises one or more tested units, and the each testing unit comprises the two tested SMs in reverse series, and the one or more tested units are in series relationship;
when the testing module group receives the testing current regulated by the current generator, the testing module group outputs voltage signals of the two tested SMs;
the cascaded converter system parameter model is used to output a reference current signal and a reference voltage signal, corresponding to system parameters and operating conditions of an actual cascaded converter, to the current controller and voltage controller;
the current controller is used to control the testing current generated by the current generator and the current controller is used to generate control signals required by the current generator; and
the voltage controller is used to control a capacitor voltage of the one or more tested SMs in the testing module group, and to generate switching signals of the one or more tested SMs in the testing module group,
wherein
the current control method is used to suppress an interference of a pulse voltage of a tested SM caused by a nearest level control (NLC) modulation on a current output waveform; wherein by compensating a feedforward voltage in a current controller, the interference of the pulse voltage of the tested SM caused by the NLC modulation is eliminated; wherein: the feedforward voltage used for compensation is generated by any of the following methods:
a first method: calculating a difference between an inserted number of tested SMs in an inverting mode and the tested SMs in a rectifying mode, and generating the feedforward voltage in combination with a capacitor voltage of a single SM;
a second method: sampling a terminal pulse voltage signal of the tested SM through a voltage sampler; performing a low-pass filtering on the terminal pulse voltage signal to remove a sampling error caused by a switching dead zone; using a filtered voltage signal as the feedforward voltage;

the feedforward voltage changing synchronously with the pulse voltage at a terminal of the tested SM is compensated to an output of a PIR regulator in the current controller to eliminate the interference caused by the pulse voltage at the terminal of the tested SM and remove a current distortion caused by the interference of the pulse voltage.