Patent ID: 11950408
Assignee: NANYA TECHNOLOGY CORPORATION
Field: nan (nan)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor structure, comprising:
a plurality of transistors disposed in a substrate, wherein each of the plurality of transistors comprises a gate structure and source/drain regions disposed at opposite sides of the gate structure;
an interlayer dielectric layer disposed above the substrate;
a plurality of contact plugs disposed in the interlayer dielectric layer, wherein the plurality of contact plugs are electrically connected to the source/drain regions of the plurality of transistors, respectively; and
a patterned conductive layer disposed on the interlayer dielectric layer and electrically connected to the plurality of transistors through the plurality of contact plugs, wherein the patterned conductive layer comprises a ring structure above a first contact plug of the plurality of contact plugs, and the ring structure is aligned with a first source/drain region of the source/drain regions of one of the plurality of transistors below the first contact plug.