Patent ID: 11868263
Assignee: VENTANA MICRO SYSTEMS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 20:
21. A microprocessor, comprising:
a virtually-indexed first-level data cache that has an allocation policy that permits multiple synonyms to be co-resident in the first-level data cache;
a store unit configured to:
execute a store instruction that specifies store data and a store virtual address; and
during commit of the store instruction:
detect synonyms each of which holds a copy of a line of memory;
write the store data to one or more of the detected synonyms; and
evict the detected synonyms to which the store data is not written;

a store queue; and
a physically-indexed physically-tagged second-level set-associative cache, wherein each entry in the second-level cache is uniquely identified by a set index and a way number;
wherein the line of memory is specified by a store physical memory line address, wherein the store physical memory line address is a translation of the store virtual address; and
wherein the store unit is configured to:
during execution of the store instruction:
write a store physical address proxy (PAP) for the store physical memory line address to an entry of the store queue allocated to the store instruction, wherein the store PAP comprises the set index and the way number of an entry of the second-level cache that holds a copy of a line of memory specified by the store physical memory line address; and

during commit of the store instruction:
read the store PAP from the store queue; and
lookup the store PAP in the first-level data cache to detect the synonyms.