Patent ID: 11871345
Assignee: ITRON, INC.
Field: Digital communication (Electrical engineering)
Classification: CPC H  Y | IPC H

Claim 13:
14. A mains-powered device comprising:
one or more processors; and
memory communicatively coupled to the one or more processors, the memory storing thereon processor-executable instruction that, when executed by the one or more processors, perform operations comprising:
transmitting, according to a schedule, a broadcast transmission to a plurality of devices at a first event start-time offset from among a plurality of event start-time offsets indicated by the schedule;
transmitting, according to the schedule, a first unicast transmission to a device of the plurality of devices at a second time indicated by a second event start-time offset from among the plurality of event start-time offsets indicated by the schedule;
transmitting a plurality of unicast transmissions to the plurality of devices, wherein the transmitting is performed according to the schedule, and wherein a distribution of numbers of devices associated with event start-time offsets dedicated to unicast transmissions is substantially uniform;
receiving a request from a device to join a network of the plurality of devices; and
assigning the device requesting to join the network to an event start-time offset such that a number of devices assigned to each event start-time offset is substantially uniform.