Patent ID: 11899971
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A memory device, comprising:
a command receiving unit, configured to receive a read command or a write command;
a memory cell, configured to correspond to address information pointed to by the read command or write command;
a spare memory cell;
a preset memory space, provided with a plurality of memory bits configured for storing address information corresponding to a memory cell with data error, each of the plurality of memory bits being associated with one spare memory cell; and
an execution unit, configured to perform a read operation or a write operation on the memory cell or the spare memory cell;
a comparison unit, wherein the comparison unit is connected to the command receiving unit and the preset memory space, and the comparison unit is configured to compare the address information pointed to by the read command or write command with the address information stored in the preset memory space;
wherein the execution unit is further connected to the comparison unit, and the execution unit is configured to:
perform a read operation or a write operation on the memory cell corresponding to the address information pointed to by the read command or write command according to a result outputted by the comparison unit;
stop performing the read operation or the write operation on the memory cell corresponding to the address information pointed to by the read command or write command; and
perform the read operation or the write operation on the spare memory cell corresponding to a first memory bit where the address information is stored in the preset memory space.