Patent ID: 11961916
Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC H

Claim 8:
9. A memory device comprising:
a plurality of first wirings extending in a first direction;
a plurality of oxide layers; and
a first memory element group; a second memory element group; and a first region,
wherein the plurality of first wirings comprise a region overlapping with the first memory element group, a region overlapping with the second memory element group, and a region overlapping with the first region,
wherein one of the plurality of oxide layers comprises a region extending along a side surface of one of the first wirings,
wherein the first memory element group and the second memory element group comprise a plurality of memory elements,
wherein each of the plurality of memory elements comprises a first transistor and a capacitor,
wherein in each of the plurality of memory elements, a gate of the first transistor is electrically connected to one of the plurality of first wirings, and a semiconductor layer of the first transistor comprises a region in contact with one of the plurality of oxide layers,
wherein the first region comprises a plurality of second transistors,
wherein in each of the plurality of second transistors, a gate electrode is electrically connected to one of the plurality of first wirings, and one or both of a source electrode and a drain electrode are electrically connected to a fourth wiring, and
wherein a function of supplying a high power supply potential to the fourth wiring is provided.