Patent ID: 11956974
Assignee: WINBOND ELECTRONICS CORP.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC H

Claim 9:
10. A memory, comprising:
a plurality of data storage cells, arranged in an array, wherein a plurality of gates of the plurality of data storage cells respectively constitute a plurality of gate electrode lines; and
a plurality of conductive lines, wherein each of the plurality of conductive lines is coupled to two of the plurality of gate electrode lines, and each of the plurality of conductive lines at least partially overlaps the two gate electrode lines of the plurality of gate electrode lines,
wherein the plurality of conductive lines comprise a plurality of first conductive lines and a plurality of second conductive lines, the plurality of first conductive lines are perpendicular to the plurality of second conductive lines, one of the plurality of first conductive lines overlapping one of the plurality of second conductive lines are staggered and non-aligned with another of the plurality of first conductive lines overlapping another of the plurality of second conductive lines.