Patent ID: 11973044
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. A method, comprising:
fabricating a memory die, comprising:
creating a first plane with a first staircase at an edge of the first plane,
creating a second plane with a second staircase at an edge of the second plane, the edge of the first plane is positioned adjacent to the edge of the second plane with a gap between the edge of the first plane and the edge of the second plane such that the first staircase is adjacent the second staircase with the gap being between the first staircase and the second staircase,
adding a first top metal layer positioned above the first plane and the second plane,
adding a first bottom metal layer positioned below the first plane and the second plane,
adding a first metal interlayer segment positioned in the gap, and connecting the first top metal layer to the first bottom metal layer via the first metal interlayer segment, and
adding a first interface connected to the bottom metal layer;

fabricating a control die, comprising:
adding a second interface in electrical communication with the first interface,
adding a second top metal layer below the second interface,
adding a second middle metal layer below the second top metal layer,
adding a second bottom metal layer below the second middle metal layer, and
adding a plurality of electrical circuits to a substrate below the second bottom metal layer; and

bonding the control die to the memory die to form a first electrical pathway from the first top metal layer through the first metal interlayer segment to the first bottom layer, to the second top metal layer via the first interface and the second interface, to the second middle metal layer, along the second middle metal layer to one or more of the electrical circuits on the control die via the second bottom layer.