Patent ID: 11948225
Assignee: TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An image processing apparatus for connecting to an imaging unit including a plurality of cameras, the image processing apparatus comprising:
a FIFO memory;
a plurality of line buffers configured to store data inputted from the plurality of cameras each having the different number of pixels in one line;
an image processing circuit that performs predetermined image processing on the data stored in the plurality of line buffers;
a controller that detects whether or not overwriting of the data in at least one of the plurality of line buffers occurs before the predetermined image processing is finished, and outputs an output control signal according to a result of the detection; and
a control circuit that performs control, according to the output control signal, such that output of the data to the plurality of line buffers is stopped and the data stopped from being outputted is stored in the FIFO memory,
wherein the image processing apparatus has an operating frequency that is twice or more than a rate of input pixels from the imaging unit.