Patent ID: 11893928
Assignee: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 12:
13. The array substrate according to claim 12, further comprising:
a third conductive layer located on a side of the second conductive layer away from the substrate, wherein the third conductive layer comprises the data signal line, the reset voltage source signal line, a second voltage source signal line as the first voltage source, a third voltage source signal line as the first voltage source, a first connecting portion, a second connecting portion, a third connecting portion, a fourth connecting portion, a fifth connecting portion, and a sixth connecting portion,
wherein one end of the first connecting portion is coupled to the first electrode of the compensation transistor in the sub-pixel in the (2n−1)-th column, and the other end is coupled to the second electrode of the driving transistor in the sub-pixel in the (2n−1)-th column,
wherein one end of the second connecting portion is coupled to the first electrode of the driving reset transistor in the sub-pixel in the (2n−1)-th column, and the other end is coupled to the gate of the driving transistor in the sub-pixel in the (2n−1)-th column,
wherein one end of the third connecting portion is coupled to the second electrode of the data writing transistor in the sub-pixel in the (2n−1)-th column, and the other end is coupled to the first electrode of the driving transistor in the sub-pixel in the (2n−1)-th column,
wherein the fourth connecting portion is coupled to the second electrode of the second light-emitting control transistor in the sub-pixel in the (2n−1)-th column,
wherein one end of the fifth connecting portion is coupled to the first electrode of the driving reset transistor in the sub-pixel in the 2n-th column, and the other end is coupled to the gate of the driving transistor in the sub-pixel in the 2n-th column,
wherein one end of the sixth connecting portion is coupled to the second electrode of the second light-emitting control transistor in the sub-pixel in the 2n-th column, and the other end is coupled to the first electrode of the light-emitting reset transistor in the sub-pixel in the 2n-th column,
wherein the data signal line is coupled to the first electrode of the data writing transistor in the sub-pixel in the (2n−1)-th column and the first electrode of the data writing transistor in the sub-pixel in the 2n-th column,
wherein the second voltage source signal line extends in the column direction and is located in the sub-pixel in the (2n−1)-th column, and is coupled to the second electrode of the capacitor and the first electrode of the first light-emitting control transistor in the sub-pixel in the (2n−1)-th column, and
wherein the third voltage source signal line extends in the column direction and is located in the sub-pixel in the 2n-th column, and is coupled to the second electrode of the capacitor and the first electrode of the first light-emitting control transistor in the sub-pixel in the 2n-th column.