Patent ID: 11916110
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 0:
1. A method for forming a semiconductor device structure, comprising:
forming a fin structure having a stack of semiconductor layers comprising first semiconductor layers and second semiconductor layers alternatingly arranged;
forming a sacrificial gate structure over a portion of the fin structure;
removing the first and second semiconductor layers in a source/drain region of the fin structure that is not covered by the sacrificial gate structure;
forming an epitaxial source/drain feature in the source/drain region;
removing portions of the sacrificial gate structure to expose the first and second semiconductor layers;
removing portions of the second semiconductor layers so that at least one second semiconductor layer has a width less than a width of each of the first semiconductor layers;
after removing portions of the second semiconductor layers, forming a conformal gate dielectric layer on exposed first and second semiconductor layers in the same process, wherein at least a portion of the conformal gate dielectric layer is disposed between adjacent first semiconductor layers; and
forming a gate electrode layer on the conformal gate dielectric layer.