Patent ID: 11934305
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory system connectable to a host, the memory system comprising:
a non-volatile first memory configured to store data received from the host;
a second memory configured to store management information associating a logical address used by the host and a location where the data is stored in the first memory for each first data unit; and
a memory controller that includes a first circuit, a second circuit, a plurality of third circuits, a fourth circuit, a fifth circuit, and a sixth circuit, wherein
the memory controller is configured to receive from the host a read request designating a continuous logical address range of a size of a plurality of the first data units,
the first circuit is configured to issue, in response to reception of the read request, a plurality of first sub-commands for requesting to read data of all the first data units included in the logical address range in order of logical addresses, each of the plurality of first sub-commands requesting to read data of one first data unit,
the second circuit is configured to respectively add first serial numbers corresponding to the order of issuance to the plurality of first sub-commands, and distribute to the plurality of third circuits the plurality of first sub-commands to which the first serial numbers are respectively added,
each of the plurality of third circuits is configured to specify a storage location of data in the first data unit related to a first sub-command distributed to itself among the plurality of first sub-commands by referring to the management information, and add location information indicating the specified storage location to the first sub-command,
the fourth circuit is configured to acquire from the plurality of third circuits the plurality of first sub-commands to which the location information is added,
the fifth circuit is configured to reorder the plurality of first sub-commands acquired by the fourth circuit in order based on the first serial numbers, and
the sixth circuit is configured to execute a read operation on the first memory based on the plurality of reordered first sub-commands.