Patent ID: 11955980
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 4:
5. The PLL of claim 1, wherein the PLL is configured to reduce the LPF settling time by:
dividing the loop filter capacitor of the PLL into two segments, wherein a first segment is pre-charged to a supply voltage through a pull-up switch and a second segment is pre-charged to a ground voltage through a pull-down switch in response to the PLL being turned off;
determining whether the PLL is turn on; and
performing one of,
shorting the first segment and the second segment to reduce the LPF settling time in response to determining that the PLL is turn on, wherein the pull-up switch and the pull-down switch are turned off, or
separating the first segment and the second segment to reduce the LPF settling time in response to determining that the PLL is turned off.