Patent ID: 11886740
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 24:
25. An apparatus, comprising:
a hypervisor coupled to one or more virtual machines associated with a host system and coupled to a memory system; and
an Input/Output (I/O) scheduler associated with the hypervisor and configured to cause the apparatus to:
receive, by the host system and from the one or more virtual machines, a plurality of commands to access the memory system common to the one or more virtual machines;
store, in a command queue of the host system associated with the memory system, the plurality of commands and a set of parameters associated with each command of the plurality of commands according to a first order;
arrange, by the host system, the plurality of commands within the command queue from the first order to a second order that is based at least in part on one or more identified patterns of accessing sequential addresses in the plurality of commands; and
transmit the plurality of commands to the memory system based at least in part on the second order.