Patent ID: 11868258
Assignee: APPLE INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A system comprising:
a plurality of coherent agent circuits, wherein a given agent circuit of the plurality of coherent agent circuits comprises one or more caches to cache memory data; and
a directory configured to track at least: (i) which of the plurality of coherent agent circuits is caching copies of a plurality of cache blocks in a memory in the system, and (ii) states of the cached copies in the plurality of coherent agent circuits;
a coherency controller circuit coupled to the directory, wherein based on a first request for a first cache block by a first agent circuit of the plurality of coherent agent circuits, the coherency controller circuit is configured to:
read an entry corresponding to the first cache block from the directory, and
issue a message to a second agent circuit of the plurality of coherent agent circuits that has a cached copy of the first cache block according to the entry, wherein the message requests a state change in the state of the cached copy in the second agent circuit, and
include an identifier of a first state of the first cache block in the second agent circuit in the message; and

wherein, based on the message, the second agent circuit is configured to:
compare the first state to a second state of the first cache block in the second agent circuit, and
delay processing of the state change based on the first state not matching the second state until the second state is changed to the first state.