Patent ID: 11907151
Assignee: DRUT TECHNOLOGIES INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. A computing system comprising:
a first fabric interface device coupled to receive first multi-lane serial peripheral component interconnect express (PCIe) data from first functional elements of a first computing asset through a first multi-lane PCIe bus, wherein the first fabric interface device is configured to transparently extend the first multi-lane PCIe bus by converting the first multi-lane PCIe data into a retimed parallel version of the first PCIe multi-lane data to be sent on a first bidirectional data communication path, wherein the first multi-lane PCIe bus has a first number of lanes and the first bidirectional data communication path has a second number of lanes; wherein the first number does not equal the second number;
wherein the first fabric interface device is configured to transparently extend the first multi-lane PCIe bus between the first computing asset and two other computing assets of a first at least three computing assets via a plurality of bidirectional data communications paths and the data path transport by converting the first multi-lane PCIe data into the retimed parallel version of the first PCIe multi-lane data to be sent on the first bidirectional data communication path through the data path transport and to the two other computing assets;
wherein each of the first at least three computing assets is located in a different computing device from each other of the first at least three computing assets, wherein each functional element performs a function of a central processing unit (CPU), and wherein each functional element includes one of a processor chip, a chip set, a PCIe root controller, or a memory.