Patent ID: 11967612
Assignee: NANYA TECHNOLOGY CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of manufacturing a semiconductor structure, comprising:
providing a first semiconductor wafer, wherein the first semiconductor wafer comprises a first dielectric layer and at least one first top metallization structure embedded in the first dielectric layer, and a top surface of the first dielectric layer is higher than a top surface of the first top metallization structure by a first distance;
providing a second semiconductor wafer, wherein the second semiconductor wafer comprises a second dielectric layer and at least one second top metallization structure embedded in the second dielectric layer, and a top surface of the second top metallization structure is higher than a top surface of the second dielectric layer by a second distance, wherein providing the second semiconductor wafer comprises:
forming an etch stop layer vertically on the second dielectric layer, wherein a thickness of the etch stop layer is substantially equal to the second distance; and

hybrid-bonding the first semiconductor wafer and the second semiconductor wafer.