Patent ID: 11966749
Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. A booting method for a processor, applicable to a processor having at least two sockets and a memory, wherein one of the at least two sockets comprises a first die and a second die, the other one of the at least two sockets comprises a third die and a fourth die, the memory is electrically connected to the second die and the fourth die, the second die is electrically connected to the first die through a first communication bus, and the fourth die is electrically connected to the third die through a second communication bus; the booting method comprising:
receiving a boot-enable signal and an internal boot-enable signal, so that the first die executes a boot procedure;
outputting a first boot-completion signal after completing the boot procedure of the first die;
receiving the boot-enable signal and the boot-completion signal from the first die, so that the second die executes the boot procedure;
outputting a second boot-completion signal after completing the boot procedure of the second die;
receiving the second boot-completion signal from the second die and the internal boot-enable signal, so that the third die executes the boot procedure;
outputting a third boot-completion signal after completing the boot procedure of the third die;
receiving the second boot-completion signal from the second die and the third boot-completion signal from the third die, so that the fourth die executes the boot procedure; and
accessing the memory through the first communication bus and the second die via the first die when the first die executes the boot procedure.