Patent ID: 11934654
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A method of operation in a memory device, the method comprising:
storing data in an array of storage cells organized into multiple banks;
configuring the memory device to generate hidden refresh commands on-die during a hidden refresh mode of operation;
receiving commands from a host memory controller to start a memory access operation with at least one selected bank from the multiple banks, the memory access operation occurring during a memory access interval;
performing a hidden refresh operation to at least one idle bank of the multiple banks during a designated hidden refresh interval that at least partially overlaps the memory access interval; and
generating a corrective action control signal indicating a request for the host memory controller due to a failed operation caused by a collision between a memory request command to a given bank of the multiple banks and a hidden refresh operation to the given bank.