Patent ID: 11901338
Assignee: XILINX, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC G  H

Claim 4:
5. The integrated circuit device of claim 1, further comprising:
a third wafer having a plurality of IC dies formed thereon separated by scribe lanes, the third wafer having a first front side bond pad disposed on an active side and coupled with a first backside bond pad disposed on a back side of the second wafer, a second front side bond pad disposed on the active side and coupled to a second back side bond pad disposed on the back side of the second wafer, a third front side bond pad disposed on the active side and coupled to a third back side bond pad disposed on the back side of the second wafer, the third wafer coupled to the second wafer by the second hybrid bond interface layer, and the first wafer having a third front side bond pad disposed on the active side of the first water.