Patent ID: 11862217
Assignee: TOHOKU UNIVERSITY
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 14:
15. The device according to the claim 1, wherein the FPAG-ACC comprises: a plurality of tiles; and a plurality of power gate switches, each power gate being provided for each tile, wherein each tile comprises: a configuration logic block; a connecting block to interface the configuration logic block to some routing tracks; and a switch block for signal routing, wherein the configuration logic block has a Look up table circuit with a nonvolatile storage area comprising MTJ elements, a flip-flop circuit with a nonvolatile storage area comprising MTJ elements and a multiplexer circuit, wherein the switch block and the connecting block are both configured to include a routing switch, the routing switch including a nonvolatile storage area to store configuration data, and a state of each flip-flop.