Patent ID: 11869567
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. A memory, comprising a refresh control circuit that comprises:
a random output sub-circuit, configured to:
sequentially receive a plurality of single-row addresses, wherein the plurality of single-row addresses comprise n single-row addresses and m single-row addresses in L single-row addresses, a single enabling duration of word lines pointed to by the n single-row addresses is greater than a preset duration, the m single-row addresses rank top m in occurrence frequency, the L single-row addresses are corresponding to word lines turned on between adjacent refresh commands, n is a natural number, and m is a positive integer; and
receive a first random number, the first random number being a positive integer less than or equal to n+m, and after receiving the first random number, output an i-th received single-row address, wherein i is equal to the first random number;

a row hammer address generation sub-circuit, connected to an output end of the random output sub-circuit, and configured to output a row hammer address corresponding to the received single-row address; and
a signal selector, configured to receive a general refresh address and the row hammer address, and output address information, wherein the address information is the row hammer address or the address information is the row hammer address and the general refresh address, and the address information acts as a refresh object corresponding to the refresh command.