Patent ID: 11971992
Assignee: LATTICE SEMICONDUCTOR CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 11:
12. The secure PLD failure characterization system of claim 11, further comprising:
the secure PLD, wherein the secure PLD comprises a plurality of programmable logic blocks (PLBs) arranged in the PLD fabric of the secure PLD, a configuration engine configured to program the PLD fabric according to a configuration image stored in a non-volatile memory (NVM) of the secure PLD and/or coupled through the configuration input/output (I/O) to the configuration engine, and a security engine configured to provide a plurality of security functions for the PLD fabric and/or the configuration engine, wherein the secure PLD is configured to perform a secure PLD-implemented method comprising:
receiving the FC command from the external system coupled to the secure PLD through the configuration I/O;
authenticating the received FC command using one or more security functions of the security engine of the secure PLD, wherein the authenticating comprises using an application public key stored in the NVM to verify that the FC command is signed using an application private key associated with a secure PLD customer for the secure PLD; and
executing the FC command, wherein the executing the FC command comprises erasing and/or nullifying at least a portion of the NVM of the secure PLD; and
performing a debug process corresponding to the debug configuration provided by the external system, wherein the performing the debug process comprises generating a debug digest comprising debug information identifying and/or characterizing failures in the operation of any one or combination of elements of the secure PLD.