Patent ID: 11862245
Assignee: ZENO SEMICONDUCTOR, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 11:
12. A semiconductor memory device comprising a plurality of memory strings to form a grid of semiconductor memory cells, each said memory string comprises a plurality of memory cells connected in series, wherein each said memory cell comprises:
a floating body region; and
a floating gate or trapping layer positioned above and insulated from said floating body region;
wherein said floating body region is configured to be charged to a level indicative of a state of said memory cell based on a charge stored in said floating gate or trapping layer, upon restoration of power to said semiconductor memory device, and
wherein transfer of data from said floating gate or trapping layer to said floating body region upon said restoration of power occurs to one or more of said memory cells.