Patent ID: 11901441
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A method, comprising:
forming a trench over a channel region of a semiconductor layer, the trench having an upper portion over a lower portion;
forming a work function layer in the trench;
forming a capping layer over the work function layer;
forming a first glue layer over the capping layer, the first glue layer having a first portion formed in the upper portion of the trench and a second portion completely filling the lower portion of the trench;
forming a second glue layer over the first portion of the first glue layer; and
performing an etching process to remove the second glue layer and the first portion of the first glue layer, thereby exposing the capping layer and the second portion of the first glue layer.