Patent ID: 11864393
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 6:
7. The memory device of claim 1, wherein
the at least one bit line comprises first and second bit lines,
the at least one word line comprises first and second word lines,
the at least one memory cell comprises first and second memory cells,
the memory device further comprises a common source line electrically coupled to the second source/drains of the first transistors of the first and second memory cells, and
the plurality of select bit lines comprises:
a plurality of first select bit lines each electrically coupled to a gate of a corresponding second transistor among the plurality of second transistors in the first memory cell; and
a plurality of second select bit lines each electrically coupled to a gate of a corresponding second transistor among the plurality of second transistors in the second memory cell.