Patent ID: 11876096
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 17:
18. The method of claim 17, further comprising:
forming a patterned photoresist layer over the gate strip, the dielectric gate spacer, and the plurality of semiconductor active regions, wherein the patterned photoresist layer comprises a row of openings arranged along the second horizontal direction and located within the areas of the shallow trench isolation structure; and
transferring a pattern of the row of openings in the patterned photoresist layer through the gate strip and into unmasked portions of the dielectric gate spacer by performing an anisotropic etch process, wherein the anisotropic etch process removes unmasked portions of the gate electrode strip and remaining portions of the gate electrode strip comprise the plurality of gate electrodes.