Patent ID: 11961554
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 16:
17. A method comprising, comprising:
providing a first circuit block connected between a first virtual VSS terminal and a first power rail to operate in a first power domain;
providing a second circuit block connected between the first virtual VSS terminal and a second power rail to operate in a second power domain, wherein the second power rail is different from the first power rail, and wherein the second power domain is different from the first power domain;
placing the first and second circuit blocks in a predetermined power mode by controlling a connection between the first virtual VSS terminal and a ground terminal in response to a first footer control signal;
providing a third circuit block connected between a second virtual VSS terminal and a third power rail to operate in a third power domain; and
placing the third circuit block in the predetermined power mode by controlling a connection between the second virtual VSS terminal and the ground terminal in response to a second footer control signal;
wherein the first footer control signal is driven by the first power domain, and wherein the second footer control signal is driven by the second power domain.