Patent ID: 11963354
Assignee: SANDISK TECHNOLOGIES, INC.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 11:
12. The three-dimensional memory device of claim 11, wherein the perforated wall structure comprises multiple columns of pillar portions that are arranged along the second horizontal direction and laterally spaced apart along the first horizontal direction at each level of the insulating layers, wherein the multiple rows of pillar structures and the multiple columns of pillar structures define an M×N array of insulator portions that are portions of a respective insulating layer within each level of the insulating layers, wherein M and N are positive integers and has a sum that is at least 3, and an M×P array of dielectric material plates located at a level of one of the electrically conductive layers within an area of the perforated wall structure, wherein P is a positive integer not greater than N.