Patent ID: 11922292
Assignee: GOOGLE LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A circuit configured to implement a neural network comprising a plurality of neural network layers, the circuit comprising:
a first memory configured to provide data for performing computations to generate an output for a layer of the neural network;
a first processor core comprising:
a first vector memory located within the first processor core and configured to store first vector values derived from the data provided by the first memory, and
a first vector register located within the first processor core and configured to at least load data from or store data to the first vector memory;

a second processor core comprising:
a second vector memory located within the second processor core and configured to store second vector values derived from the data provided by the first memory, and
a second vector register located within the second processor core and configured to at least load data from or store data to the second vector memory; and

a shared memory disposed intermediate the first memory and at least one of the first processor core or the second processor core, wherein the shared memory and the first memory are communicatively coupled by direct memory access (DMA), wherein the shared memory comprises:
a first direct memory access (DMA) data path configured to route data communications between the shared memory and the first vector memory included in the first processor core, a second direct memory access (DMA) data path configured to route data communications between the shared memory and the second vector memory included in the second processor core;
a first load-store data path configured to route data communications between the shared memory and the first vector register included in the first processor core, and a second load-store data path configured to route data communications between the shared memory and the second vector register included in the second processor core;
a software-controlled staging resource that is formed from a subset of memory resources of the shared memory, wherein the software-controlled staging resource is used to manage a flow of data values from the first memory to the first vector register of the first processor core or the second vector register of the second processor core,
wherein the software-controlled staging resource is a first-in-first-out (FIFO) memory structure along a load section of the first load-store data path or the second load-store data path; and
the FIFO memory structure is configured to temporarily store a vector of values received from other memory locations of the shared memory for a threshold number of processor cycles and to subsequently route the vector of values from the FIFO memory structure to the first vector register of the first processor core or the second vector register of the second processor core; and

a matrix computation unit, within the first processor core or the second processor core, configured to perform a subset of the computations to generate accumulated values that are used to generate the output of the layer of the neural network, wherein the software-controlled staging resource is used to manage the flow of the data values corresponding to vector arrays between the first memory and the matrix computation unit, wherein the vector arrays are derived from the data values provided by the first memory.