Patent ID: 11894083
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. The electronic device of claim 16, wherein the signal reconstruction circuit comprises a first NAND gate, a second NAND gate and a first NOT gate, and wherein
input ends of the first NAND gate are respectively connected with the input signal and an output signal of the second NAND gate;
input ends of the second NAND gate are respectively connected with a system reset signal, the delayed signal and an output signal of the first NAND gate; and
an input end of the first NOT gate is connected with an output end of the first NAND gate, and an output end of the first NOT gate is configured to output the repaired signal that has a width satisfying the preset width.