Patent ID: 11894277
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 0:
1. A method comprising:
etching an opening in a gate stack, the opening exposing sidewalls of gate spacers, and the gate spacers being disposed on first sidewalls of the gate stack;
performing a treatment process in the opening, wherein the treatment process defines:
a first passivation region extending from the sidewalls of the gate spacers into the gate spacers; and
a second passivation region extending from second sidewalls of the gate stack into the gate stack;

extending the opening through the gate stack using an etch process, the etching process removes the first passivation region within the gate spacers; and
after extending the opening through the gate stack, filling the opening with a dielectric material.