Patent ID: 11961466
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G  H

Claim 13:
14. A method for driving the shift register unit according to claim 1, the driving method comprises:
in a first reset phase, the signal input terminal writing a high level input signal; under the control of the input control terminal, the input circuit controlling to connect the signal input terminal and the first node; under the control of the first node and the second level signal input terminal, the inverter circuit controlling to connect the second node and the second level signal input terminal; under the control of the second node, the output pull-down circuit controlling to disconnect the signal output terminal and the second level signal input terminal; under the control of the first level signal input terminal, the coupling circuit controlling to connect the first node and the second terminal of the first capacitor circuit; under the control of the second terminal of the first capacitor circuit, the output circuit controlling to connect the first level signal input terminal and the signal output terminal;
in an initial phase, the signal input terminal writing a low level input signal; under the control of the input control terminal, the input circuit controlling to disconnect the signal input terminal and the first node; under the control of the first node and the second level signal input terminal, the inverter circuit controlling to connect the second node and the second level signal input terminal; under the control of the second node, the output pull-down circuit controlling to disconnect the signal output terminal and the second level signal input terminal; under the control of the first level signal input terminal, the coupling circuit controlling to connect the first node and the second terminal of the first capacitor circuit; under the control of the second terminal of the first capacitor circuit, the output circuit controlling to connect the first level signal input terminal and the signal output terminal;
in a first sub-phase of an output phase, the signal input terminal continuing to write the low level input signal; under the control of the input control terminal, the input circuit controlling to connect the signal input terminal and the first node; under the control of the first level signal input terminal, the input control terminal and the first node, the inverter circuit controlling to connect the first level signal input terminal and the second node; under the control of the second node, the output pull-down circuit controlling to connect the signal output terminal and the second level signal input terminal;
in a second sub-phase of the output phase, the signal input terminal writing a high level input signal; under the control of the input control terminal, the input circuit controlling to disconnect the signal input terminal and the first node, under the action of the first capacitor circuit, the potential of the first node continuing to be maintained at a potential in the first sub-phase; under the control of the first level signal input terminal, the input control terminal and the first node, the inverter circuit continuing to control to connect the first level signal input terminal and the second node; under the control of the second node, the output pull-down circuit controlling to connect the signal output terminal and the second level signal input terminal; and
in a second reset phase and a maintenance phase, the signal input terminal continuing to write a high level input signal; under the control of the input control terminal, the input circuit controlling to connect the signal input terminal and the first node; under the control of the first node and the second level signal input terminal, the inverter circuit controlling to connect the second node and the second level signal input terminal, under the control of the second node, the output pull-down circuit controlling to disconnect the signal output terminal and the second level signal input terminal; under the control of the first level signal input terminal, the coupling circuit controlling to connect the first node and the second terminal of the first capacitor circuit; under the control of the second terminal of the first capacitor circuit, the output circuit controlling to connect the first level signal input terminal and the signal output terminal.