Patent ID: 11864382
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A three-dimensional semiconductor memory device, comprising:
a substrate including a cell array region and a connection region;
an electrode structure including a plurality of electrodes vertically stacked on the substrate;
a plurality of first vertical channels that penetrate the electrode structure on the cell array region;
a plurality of second vertical channels that penetrate the electrode structure on the connection region;
a dummy insulating pattern provided in the connection region of the substrate,
wherein each of the first vertical channels and the second vertical channels includes a lower channel pattern connected to the substrate and an upper channel pattern connected to the lower channel pattern,
wherein a lowermost electrode of the plurality of electrodes surrounds the lower channel patterns of the first vertical channels and the upper channel patterns of the second vertical channels,
wherein top-most surfaces of the lower channel patterns of the second vertical channels are positioned at a lower level than a top surface of the substrate,
wherein the dummy insulating pattern is spaced apart from the plurality of first vertical channels, and
wherein the dummy insulating pattern contacts sidewalls of the lower channel patterns of the second vertical channels.