Patent ID: 11871572
Assignee: nan
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 20:
21. A method of forming an integrated structure, comprising:
forming a vertical stack of alternating first and second levels; the first levels comprising first material and the second levels comprising second material;
forming an opening to extend through the stack, the opening having a peripheral sidewall;
recessing the first levels relative to the second levels to form cavities along the first levels, and to form a first undulating sidewall surface of the opening;
forming a layer of silicon along the first undulating sidewall surface;
partially oxidizing the layer of silicon to form an oxide laterally outward of remaining silicon, the remaining silicon being within the cavities;
forming charge-blocking material adjacent the peripheral sidewall;
forming charge-storage material adjacent the charge-blocking material;
forming gate-dielectric material adjacent the charge-storage material;
forming channel material adjacent the gate-dielectric material;
removing the second material to leave first voids;
forming conductive levels within the first voids;
removing the first material to leave second voids; and
extending the second voids through the charge-storage material to divide the charge-storage material into vertically-spaced segments.