Patent ID: 11908508
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. A memory system, comprising:
a memory controller; and
a dynamic random access memory (DRAM) device operably connected to the memory controller, wherein the DRAM device includes a memory array including a first memory region and a second memory region,
wherein:
the memory controller and/or the DRAM device are configured to write first data to the memory array in accordance with a programming sequence by writing first data to memory cells of the first memory region before memory cells of the second memory region,
the programming sequence is defined prior to the memory controller and/or the DRAM device writing the first data to the memory cells of the first memory region,
the programming sequence defines an order of memory locations in the DRAM device to which the memory controller and/or the DRAM device sequentially writes the first data, the first memory region appearing before the second memory region in the order of the memory locations; and
the memory controller and/or the DRAM device are configured to update the programming sequence after writing the first data, such that the memory controller and/or the DRAM device are configured to write second data to memory cells of the second memory region before writing the second data to memory cells of the first memory region.