Patent ID: 11934666
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. A memory device, comprising:
a memory array including a plurality of memory cells arranged in memory pages; and
a controller coupled to the memory array, the controller configured to:
determine a target profile including edge targets and middle targets, wherein each of the targets represent a target distribution of program-verify voltages corresponding to a logic value for the memory cells,
determine a feedback measure based on reading the memory cells, wherein the feedback measure represents a separation between adjacent distributions of program-verify voltages,
wherein the controller is further configured to determine the feedback measure based on error counts associated with a set of read-level voltages,
wherein the feedback measure is calculated based on a difference in a first error count and a second error count corresponding to different read-level voltages, and

dynamically adjust the target profile based on adjusting one or more of the middle targets according to the feedback measure.