Patent ID: 11955987
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 5:
6. An electronic device for decoding a low-density parity-check (LDPC) code, the electronic device comprising:
a processor; and
a memory,
wherein the processor is configured to:
receive a signal, a codeword and information about an LPDC code used for encoding the codeword,
configure a neural network self-correction condition for adjusting a neural network node deletion and dropout rate,
perform iterative decoding on the received signal and the codeword based on the information about the LPDC code used for encoding the codeword, wherein the iterative decoding uses decoding factors and a neural network self-correction technique,
determine whether the iterative decoding of the received signal and the codeword succeeds or fails,
store, in the memory, the received signal and the codeword which are successfully decoded, based on a result of the determination, and
update the decoding factors, based on the stored received signal and the codeword,

wherein, to update the decoding factors, the processor is further configured to:
read the received signal and the codeword,
erase at least one node of the neural network through hysteresis-based neural network self-correction,
learn a normalization factor, an offset factor, a channel normalization factor, and a channel offset factor of a corresponding iteration from a structure of the neural network having the read received signal as an input, and
generate learning data for the neural network for optimizing a factor of a next iteration using the learned factors.