Patent ID: 11953794
Assignee: ADVANCED SILICON DISPLAY OPTOELECTRONICS CORPORATION LTD.
Field: Optics (Instruments)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A preparation method of a liquid crystal on silicon (LCoS) panel, comprising:
step A, providing a wafer substrate, wherein the wafer substrate comprises a silicon substrate and a plurality of die areas defined by a plurality of intersecting dividing lines, the silicon substrate comprises a first surface and a second surface opposite to the first surface, each of the plurality of die areas comprises an active circuit on the first surface, and the active circuit comprises a pixel circuit area and a peripheral circuit area;
step B, forming a seal on a side of the first surface in each of the plurality of die areas of the wafer substrate, wherein the seal at least surrounds the pixel circuit area of the active circuit, and defines a liquid crystal space of each of the plurality of die areas where the seal is located; providing a transparent substrate comprising a transparent conductive layer, and coupling a surface of the transparent substrate with the transparent conductive layer and the wafer substrate by the seal;
step C, thinning the silicon substrate to a first thickness ranging from 220 μm to 500 μm; manufacturing a plurality of vias extending through the first surface and the second surface in each of the plurality of die areas of the wafer substrate; and manufacturing a plurality of conductive interfaces on the second surface, wherein each of the plurality of conductive interfaces is arranged to correspond to one of the plurality of vias, and is electrically connected to the active circuit of one of the plurality of die areas where the conductive interface is located by a corresponding one of the plurality of vias; and
step D, cutting the wafer substrate along the plurality of dividing lines, and correspondingly cutting the transparent substrate to obtain a plurality of LCoS panels;
wherein in the step C, projections of the plurality of vias manufactured on the wafer substrate surround but do not intercept with the pixel circuit area in each of the plurality of die areas.