Patent ID: 11862602
Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A method of forming a microelectronic assembly, comprising:
forming local adjacent connections on a surface of a semiconductor wafer, the surface extending in first and second horizontal orthogonal directions, the local adjacent connections electrically connecting a grid of sixteen network nodes to one another, the local adjacent connections each extending in only one of the first and second horizontal orthogonal directions;
forming local oblique connections on a surface of an interconnection structure comprising a low-loss dielectric material, the surface extending in third and fourth horizontal oblique directions that are each oriented at an oblique angle relative to the first and second directions, the local oblique connections each extending in only one of the third and fourth horizontal oblique directions;
directly hybrid bonding, using a non-adhesive technique, a first surface of the semiconductor wafer to a first surface of the interconnection structure, such that the first surface of the semiconductor wafer is in surface-to-surface contact with the first surface of the interconnection structure, and such that each of the network nodes is electrically connected with at least one of the other network nodes through at least one of the local adjacent connections and at least one of the local oblique connections; and
interconnecting, through a combination of the semiconductor wafer and the interconnection structure, a plurality of processor cores, wherein the plurality of processor cores, the semiconductor wafer, and the interconnection structure are together configured to function as a hierarchical mesh network,
wherein, the hierarchical mesh network is configured such that a maximum of two hops is needed for an electrical signal to travel from any one of the network nodes, through the interconnection structure, to any other one of the network nodes, and
wherein the maximum of two hops is a maximum of two direct electrical signal connections extending between the any one of the network nodes to the any other one of the network nodes.