Patent ID: 11871419
Assignee: INTEL CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An apparatus comprising:
memory to store downlink control information (DCI); and
processor circuitry, coupled with the memory, to:
retrieve the DCI from the memory, wherein the DCI is to schedule a plurality of shared channels with different transport blocks (TB s) in different slots, wherein a plurality of fields within the DCI are common among the plurality of shared channels, wherein a carrier indicator and a bandwidth part (BWP) indicator indicated in the DCI are common for the plurality of shared channels, wherein the common carrier indicator is to indicate that a same component carrier (CC) is to be used for the plurality of shared channels, and wherein the common BWP indicator is to indicate that a same BWP is to be used for the plurality of shared channels; and
encode a physical downlink control channel (PDCCH) message that includes the DCI for transmission to a user equipment (UE).