Patent ID: 11886292
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 17:
18. The memory system of claim 17, wherein each of the decoding sub-circuits comprises:
a decoder, configured to receive the X first operation codes and output N first decoded signals, each of the N first decoded signals corresponding to a respective one bit of the N data;
a first AND gate circuit, configured to receive at least two selected operation codes and perform a logical AND operation, the at least two selected operation codes being the second operation codes obtained by performing the fourth encoding operation on a subset of the Y second check codes corresponding to the respective byte;
an NOR gate circuit, configured to receive at least two unselected operation codes and perform a logical NOR operation, the at least two unselected operation codes being the second operation codes other than the selected operation codes corresponding to the respective byte; and
N second AND gate circuits, each having an input terminal connected to an output terminal of the first AND gate circuit, an output terminal of the NOR gate circuit and one of the first decoded signals, wherein a position of erroneous data is acquired based on outputs of the N second AND gate circuits.