Patent ID: 11860685
Assignee: ADVANCED MICRO DEVICES, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 7:
8. A method comprising:
receiving, by a first clock divider circuit, a first input clock signal;
generating, by the first clock divider circuit, a first output clock signal based on the first input clock signal;
receiving, by a second clock divider circuit, a second input clock signal, wherein the first input clock signal and the second input clock signal have an initial phase difference between them;
receiving, by the second clock divider circuit, a first intermediate clock signal based on the first output clock signal;
receiving, by the second clock divider circuit, a reset signal that is asserted asynchronously, in a given clock cycle of the second input clock signal, with respect to the second input clock signal; and
in response to the reset signal being asserted, generating, in the given clock cycle by the second clock divider circuit, a second output clock signal such that the first output clock signal and the second output clock signal have the initial phase difference between them.