Patent ID: 11923297
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A semiconductor structure, comprising:
a gate structure;
a plurality of first metal lines formed in a first dielectric layer below the gate structure, wherein the plurality of first metal lines is at a back side of a standard cell;
at least one first via formed in a second dielectric layer that is between the gate structure and the first dielectric layer, wherein each of the at least one first via is electrically connected to the gate structure and a corresponding one of the plurality of first metal lines;
a plurality of second metal lines formed in a third dielectric layer over the gate structure, wherein the plurality of second metal lines is at a front side of the standard cell, wherein:
the standard cell is a device with a plurality of input/output (I/O) pins,
at least one first pin of the plurality of I/O pins is routed from the back side of the standard cell, wherein the at least one first pin toggles between a power supply voltage level and a ground voltage level when the device is powered on, and
at least one second pin of the plurality of I/O pins is routed from the front side of the standard cell, wherein the at least one second pin toggles between the power supply voltage level and the ground voltage level when the device is powered on; and

at least one second via formed in a fourth dielectric layer that is between the gate structure and the third dielectric layer, wherein each of the at least one second via is electrically connected to the gate structure and a corresponding one of the plurality of second metal lines.