Patent ID: 11968839
Assignee: SANDISK TECHNOLOGIES, INC.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 0:
1. A memory device, comprising:
an alternating stack of insulating layers and electrically conductive layers comprising gate electrodes and located over a substrate;
a vertical semiconductor channel vertically extending through the alternating stack; and
a stack located between the vertical semiconductor channel and the electrically conductive layers, the stack including, from one side to another, a first ferroelectric material layer comprising a first ferroelectric material, a second ferroelectric material layer comprising a second ferroelectric material, and a gate dielectric layer,
wherein the vertical semiconductor channel is in direct contact with the gate dielectric layer, the first ferroelectric material layer, and the second ferroelectric material layer; and
wherein the second ferroelectric material extends vertically from a bottommost one of the insulating layers to a topmost one of the insulating layers, and exhibits spontaneous electrical polarization in an absence of an external electric field at each level of the insulating layers.