Patent ID: 11968817
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A method, comprising:
forming a first gate structure, a second gate structure, a source/drain, and dielectric materials disposed over the source/drain and between the first gate structure and the second gate structure;
etching an opening in the dielectric materials until the source/drain is exposed, wherein the opening partially extends into the source/drain, and wherein the opening is etched to have an asymmetrical profile in a cross-sectional view, such that a portion of the first gate structure is exposed by the opening, but no portion of the second gate structure is exposed by the opening; and
forming a source/drain contact in the opening, wherein a first segment of the source/drain contact is formed to be in direct contact with the source/drain, and wherein a second segment of the source/drain contact is formed to be in direct contact with the portion of the first gate structure.