Patent ID: 11923038
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. A method comprising:
receiving at an address decoder, address signals;
providing with the address decoder, decoded addresses;
receiving at a command decoder, internal command signals;
providing with the command decoder, internal control signals for performing memory operations;
receiving at a command/address input circuit, a plurality of multilevel command and address signals; and
providing with the command/address input circuit, output signals to the address decoder and the command decoder, wherein the multilevel command and address signals represent a command structure including a command operand to identify a memory command and further including memory address information to identify a memory location to which the memory command is directed,
wherein the command operand is represented by a first portion of the plurality of multilevel command and address signals and each of the multilevel command and address signals of the first portion represent a non-binary value, and wherein the address information is represented by a second portion of the plurality of multilevel command and address signals and the multilevel command and address signals of the second portion represent bits of memory address information.