Patent ID: 11955377
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 15:
16. A method of fabricating an interconnect structure for an integrated circuit, the method comprising:
forming a first layer of the interconnect structure above a substrate, the first layer comprising a first grating of alternating metal lines and dielectric lines in a first direction, wherein the dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines; and
forming a second layer of the interconnect structure above the first layer of the interconnect structure, the second layer comprising a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction, wherein the dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines of the second grating, wherein the dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating; and
forming a region of dielectric material between the metal lines of the first grating and the metal lines of the second grating, and in a same plane as upper portions of the dielectric lines of the first grating and lower portions of the dielectric lines of the second grating, the region of dielectric material comprising a cross-linked photolyzable material on a distinct underlying hardmask portion, wherein the distinct underlying hardmask portion includes a porous dielectric material comprising pores filled with a metal-containing material.