Patent ID: 11973024
Assignee: KIOXIA CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor memory device comprising:
a substrate including a first area, a second area, and a plurality of block areas, the first area and the second area being arranged in a first direction, each of the block areas being provided to extend in the first direction, and the block areas being arranged in a second direction intersecting the first direction;
a plurality of conductive layers divided for each of the block areas, the conductive layers being arranged in a third direction intersecting the first and second directions and provided to be separated from one another, the conductive layers including a plurality of terraced portions, and the terraced portions being provided not to overlap an upper conductive layer for each area in which the second area and any one of the block areas overlap;
a plurality of pillars provided for each of the block areas, each of the pillars being provided to penetrate the conductive layers, and a portion at which one of the pillars and one of the conductive layers intersect each other functioning as a memory cell; and
a plurality of contacts respectively provided on the terraced portions for each of the block areas, wherein
the first area contains at least one of the pillars,
the second area includes a first sub area and a second sub area arranged in the first direction,
the first sub area includes a first stepped structure, the first stepped structure including a structure in which a plurality of first terraced portions included in the terraced portions ascend or descend along the first direction and in a direction toward the first area,
the second sub area includes a second stepped structure and a first pattern, the second stepped structure including a structure in which a plurality of second terraced portions included in the terraced portions ascend or descend along the first direction and in a direction away from the first area, and the first pattern being continuous with any one of the conductive layers, and
the first pattern is arranged between the first stepped structure and the second stepped structure, at least one contact of the contacts being arranged between the first pattern and a terraced portion of a conductive layer physically continuous with the first pattern.