Patent ID: 11943757
Assignee: PANASONIC HOLDINGS CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An integrated circuit for controlling operation of a device, the integrated circuit comprising,
circuitry, which, in operation:
controls reception of assignment information indicating resource blocks, each of which being formed of consecutive subcarriers in a frequency domain, allocated to the device according to one of a plurality of resource allocations including:
a resource allocation allocating Distributed Virtual Resource Blocks (DVRBs), where a pair of DVRBs assigned with a single resource block number are mapped to Physical Resource Blocks (PRBs) with a variable gap in the frequency domain, the variable gap is an integer multiple of a Resource Block Group (RBG) size defined as a number of one or more consecutive resource blocks forming one RBG in a given system bandwidth; and
a resource allocation allocating one or more RBGs; and

decodes data based on the assignment information.