Patent ID: 11894039
Assignee: NIF/T, LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 14:
15. A dynamic random-access memory (DRAM) device, comprising:
a gate having a conductive gate electrode positioned over a gate dielectric;
a first portion of an epitaxial drain and a first portion of an epitaxial source on a surface of a substrate, the first portion of the epitaxial drain and the first portion of the epitaxial source formed over and in contact with respective source and drain regions of the surface of the substrate, the epitaxial drain and epitaxial source being isolated from the conductive gate electrode by a first dielectric, the epitaxial drain and epitaxial source forming respective junctions at their interfaces with the respective drain and source regions of the surface of the substrate; and
a second portion of the epitaxial source over the first portion of the epitaxial source and a second portion of the epitaxial drain over the first portion of the epitaxial drain, the respective second portions of the epitaxial source and the epitaxial drain being isolated from the conductive gate electrode by a second dielectric;
the epitaxial source, the epitaxial drain and the gate together forming a pass transistor enabled to connect the epitaxial source to the epitaxial drain when a voltage value in excess of a threshold value is applied to the conductive gate electrode;
the source region having one or more charge storage capacitors, each charge storage capacitor having one of its terminals connected to the epitaxial source to store charge responsive to data being stored, the charge storage capacitor having first and second conductive electrodes separated by a capacitor dielectric, the first conductive electrode having its terminal coupled to the epitaxial source, the second conductive electrode being isolated from the epitaxial source and the first conductive electrode by the capacitor dielectric, and the second conductive electrode being connected to a ground terminal or a fixed voltage terminal;
wherein
a channel of the pass transistor forms a path connecting the first terminal of the charge storage capacitor to a bit line connected to the epitaxial drain when a gate voltage in excess of a threshold voltage is applied to the conductive gate electrode to turn on the pass transistor; and
the channel of the pass transistor is turned off, when the gate voltage is removed from the conductive gate electrode to isolate the terminal of the first conductive electrode of the charge storage capacitor from the bit line.