Patent ID: 11968821
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. A method of forming an array of two transistor-one capacitor memory cells, comprising:
forming columns of digit lines;
forming rows of elevationally-extending first and second field effect transistors individually having an elevationally inner of their source/drain regions electrically coupled to individual of the digit lines, the first and second transistors comprising access lines above the digit lines, individual of the first and second transistors comprising a gate comprising part of individual of the access lines;
forming a plurality of capacitor openings that individually extend to an elevationally outer source/drain region of the individual first transistors;
forming a capacitor pillar in individual of the capacitor openings; the capacitor pillar comprising a conductive first capacitor node electrically coupled to individual of the elevationally outer source/drain regions of the individual first transistors, a conductive second capacitor node, and a capacitor insulator between the first and second capacitor nodes;
recessing a material in which the capacitor openings were formed to result in projecting portions of the capacitor pillars;
forming a ring of masking material circumferentially about the projecting portions of individual of the capacitor pillars, the rings forming individual mask openings between diagonally-adjacent of the capacitor openings;
using the rings and capacitor pillars as a mask while etching the material through the mask openings, the etching vertically extending the mask openings into the material to form via openings within the material that extend to individual of elevationally outer source/drain regions of the individual second transistors;
removing the projecting portions of the capacitor pillars and the rings from being above the material in which the capacitor openings were formed; and
forming conductive material in the individual via openings electrically coupled to the individual elevationally outer source/drain region of the individual second transistors and electrically coupled to one of four immediately-surrounding of the capacitor pillars.