Patent ID: 11940914
Assignee: QUALCOMM INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 20:
21. A non-transitory computer-readable medium comprising computer-executable instructions that, when executed by one or more processors of an apparatus, cause the apparatus to perform a partial cache collapse procedure, comprising:
counting a number of cache lines that satisfy an eviction criteria based on a deterministic cache eviction policy in each cache way of a group of cache ways;
selecting at least one cache way from the group for collapse, based on its corresponding number of cache lines that satisfy the eviction criteria, wherein selecting the at least one cache way comprises one or more of:
selecting, for collapse, one cache way having a highest number of cache lines that satisfy the eviction criteria, or
selecting multiple cache ways having highest numbers of cache lines that satisfy the eviction criteria; and

performing the partial cache collapse procedure based on the at least one cache way selected from the group for collapse.