Patent ID: 11930634
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A method of forming a microelectronic device, comprising:
forming a first semiconductor wafer comprising memory cells within array regions, digit lines coupled to the memory cells and terminating within digit line exit regions neighboring the array regions, and word lines coupled to the memory cells and terminating within word line exit regions neighboring the array regions;
forming a second semiconductor wafer comprising control logic devices;
attaching the second semiconductor wafer to the first semiconductor wafer through oxide-oxide bonding such that some of the control logic devices are positioned within the array regions;
forming digit line contact structures within the digit line exit regions after attaching the second semiconductor wafer to the first semiconductor wafer, the digit line contact structures coupled to the digit lines and some of the control logic devices; and
forming word line contact structures within the word line exit regions after attaching the second semiconductor wafer to the first semiconductor wafer, the word line contact structures coupled to the word lines and some other of the control logic devices.