Patent ID: 11862706
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A memory device, comprising:
a first read pull-down transistor, a first pull-down transistor, a first pull-up transistor, a first pass-gate transistor, and a first read pass-gate transistor sharing a first metal gate electrode; and
a second read pass-gate transistor, a second pass-gate transistor, a second pull-up transistor, a second pull-down transistor, and a second read pull-down transistor sharing a second metal gate electrode,
wherein the first pass-gate transistor and the second pass-gate transistor comprise a first gate dielectric layer, the first pull-down transistor and the second pull-down transistor comprise a second gate dielectric layer, the first read pass-gate transistor and the second read pass-gate transistor comprise a third gate dielectric layer, and the first read pull-down transistor and the second read pull-down transistor comprise a fourth gate dielectric layer,
wherein the first gate dielectric layer, the second gate dielectric layer, the third gate dielectric layer comprise hafnium oxide,
wherein the first gate dielectric layer, the second gate dielectric layer, the third gate dielectric layer further comprises lanthanum,
wherein the fourth gate dielectric layer is substantially free of lanthanum.