Patent ID: 11942459
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. The semiconductor device package of claim 10 further comprising:
a third substrate having a top planar surface and an electrical circuit, the top planar surface being oriented generally parallel to the top planar surface of the first substrate;
a second plurality of semiconductor dies stacked one on top of the other and positioned above the third substrate;
a second plurality of bond wires electrically connected one to another and electrically coupling the second plurality of semiconductor dies to one another and to the electrical circuit on the third substrate, the second plurality of bond wires including a first bond wire having a first portion connected to a first semiconductor die of the second plurality of semiconductor dies, a second portion connected to the electrical circuit of the third substrate, and an intermediate portion between the first portion and second portion;
a second molding compound encapsulating the second plurality of semiconductor dies, the first portion of the first bond wire, and second portion of the first bond wire, wherein the second molding compound has top and side planar surfaces, the side planar surface being substantially perpendicular to the top planar surface;
a third redistribution layer coupled to the side planar surface of the second molding compound; and
a second solder ball electrically connected to the third redistribution layer,
wherein the intermediate portion of the first bond wire is exposed along the side planar surface of the second molding compound and is electrically connected to the third redistribution layer, and
wherein the second solder ball is electrically connected to a fourth redistribution layer electrically connected to the top planar surface of the second substrate.