Patent ID: 11880585
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. The semiconductor memory according to claim 1, further comprising:
a plurality of bit line pairs, each of the plurality of bit line pairs comprising a first bit line and a second bit line, the first bit line and the second bit line being configured to transmit opposite signals, and the plurality of storage units positioned in the same column being connected to the same one of the plurality of bit line pairs;
a plurality of local data line pairs, each of the plurality of local data line pairs comprising a first local data line and a second local data line, and the first local data line and the second local data line being configured to transmit opposite signals; and
a plurality of sense amplifiers, each of the plurality of sense amplifiers being respectively connected to one of the plurality of bit line pairs and one of the plurality of local data line pairs;
wherein two storage units positioned in the adjacent columns are respectively connected to different local data line pairs among the plurality of local data line pairs via a corresponding one of the plurality of bit line pairs and a corresponding one of the plurality of sense amplifiers.