Patent ID: 11875061
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A system comprising:
a memory device comprising:
a single-level cell (SLC) cache;
a first multiple level cell (XLC) storage comprising a first XLC block, wherein data is indirectly written to the first XLC storage via the SLC cache in a first XLC write mode;
a second XLC storage comprising a second XLC block, wherein data is directly written to the second XLC storage in a second XLC write mode; and
a processing device, operatively coupled with the SLC cache, the first XLC storage and the second XLC storage, to perform operations comprising:
receiving data from a host system;
initiating a write operation to write the data to the first XLC storage and the second XLC storage; and
causing a first portion of the data to be written to a first number of pages of the first XLC block in the first XLC write mode and a second portion of the data to be written to a second number of pages of the second XLC block in the second XLC write mode using page level interleave, wherein the first number of pages and the second number of pages are defined by an interleave mix comprising an interleave ratio A:B between the first XLC write mode and the second XLC write mode.