Patent ID: 11908855
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC B  H

Claim 18:
19. A semiconductor device, comprising:
a circuit area; and
an external dummy area adjacent to the circuit area,
wherein the circuit area includes circuit active regions, circuit gate lines overlapping the circuit active regions in a vertical direction, and circuit source/drain regions,
wherein the external dummy area includes an external dummy active region, and external dummy gate lines overlapping the external dummy active region in the vertical direction, the external dummy gate lines isolated from direct contact with the circuit gate lines, wherein the external dummy active region has
a linear shape extending in a first horizontal direction, or
a shape including active portions isolated from direct contact with each other and extending sequentially in the first horizontal direction,

wherein the circuit active regions include
a first plurality of circuit active regions extending sequentially in the first horizontal direction, and
a second plurality of circuit active regions extending sequentially in a second horizontal direction perpendicular to the first horizontal direction,

wherein each circuit active region of the circuit active regions includes a circuit active pattern and a circuit channel region on the circuit active pattern and adjacent to the circuit source/drain regions,
wherein the external dummy active region includes a dummy active pattern and a dummy channel region on the dummy active pattern,
wherein at least one circuit gate line of the circuit gate lines covers an upper surface and a side surface of the circuit channel region, and
wherein at least one external dummy gate line of the external dummy gate lines covers an upper surface and a side surface of the dummy channel region.