Patent ID: 11887655
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 2:
3. The sense amplifier of claim 2, wherein the control circuit comprises:
a first switch, a first terminal of the first switch being connected to a gate of the first PMOS transistor, and a second terminal of the first switch being connected to a gate of the second PMOS transistor;
a second switch, a first terminal of the second switch being connected to the gate of the second PMOS transistor, and a second terminal of the second switch being connected to the first node;
a third switch, a first terminal of the third switch being connected to the second node, and a second terminal of the third switch being connected to the gate of the first PMOS transistor;
a fourth switch, a first terminal of the fourth switch being connected to the first node, and a second terminal of the fourth switch being connected to the first bit line; and
a fifth switch, a first terminal of the fifth switch being connected to the second bit line, and a second terminal of the fifth switch being connected to the second node;
wherein in the case of reading the data in the memory cell on the first bit line, at the offset compensation stage of the sense amplifier, the first switch, the second switch, the fourth switch and the fifth switch are turned on, and the third switch is turned off;
in the case of reading the data in the memory cell on the second bit line, at the offset compensation stage of the sense amplifier, the first switch, the third switch, the fourth switch and the fifth switch are turned on, and the second switch is turned off.