Patent ID: 11861234
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A method comprising:
receiving, by a processing device, data to write to a memory sub-system, wherein the memory sub-system comprises a single-level cell (SLC) cache and a multiple level cell (XLC) storage, wherein the SLC cache comprises a static SLC cache having a fixed size and dynamic SLC cache, wherein the dynamic SLC cache has a default maximum size corresponding to a first mode of operation and an enhanced maximum size greater than the default maximum size corresponding to a second mode of operation;
determining, by the processing device, whether to initiate a write operation in the first mode;
in response to determining to initiate the write operation in the first mode, initiating, by the processing device, the write operation in the first mode to write a first portion of the data to the SLC cache;
determining, by the processing device, whether a logical saturation of the first portion of the data written to the SLC cache satisfies a first threshold condition based on the default maximum size; and
in response to determining that the logical saturation of the first portion of the data satisfies the first threshold condition, continuing, by the processing device, the write operation in the second mode to write a second portion of the data to the SLC cache.