Patent ID: 11922108
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A method of forming a memory cell array, the method comprising:
generating, by a processor, a layout design of the memory cell array, wherein the generating of the layout design comprises:
generating a first set of memory cell layout patterns corresponding to fabricating a first set of memory cells arranged in a first column of memory cells, each layout pattern of the first set of memory cell layout patterns being separated from an adjacent layout pattern of the first set of memory cell layout patterns in a first direction;
generating a second set of memory cell layout patterns corresponding to fabricating a second set of memory cells arranged in a second column of memory cells, the second set of memory cell layout patterns being separated from the first set of memory cell layout patterns in a second direction different from the first direction, each layout pattern of the second set of memory cell layout patterns being separated from an adjacent layout pattern of the second set of memory cell layout patterns in the first direction;
generating a first set of conductive feature layout patterns extending in the first direction, a layout pattern of the first set of conductive feature layout patterns being positioned between the first set of memory cell layout patterns and the second set of memory cell layout patterns, the first set of conductive feature layout patterns corresponding to fabricating a source line extending in the first direction and being coupled to the first set of memory cells and the second set of memory cells;
generating a second set of conductive feature layout patterns extending in the first direction, the second set of conductive feature layout patterns being located on a first layout level, and the second set of conductive feature layout patterns corresponding to fabricating a first portion of a first bit line coupled to the first set of memory cells;
generating a third set of conductive feature layout patterns extending in the first direction, the third set of conductive feature layout patterns being located on a second layout level different from the first layout level, and the third set of conductive feature layout patterns corresponding to fabricating a second portion of the first bit line, the first portion of the first bit line and the second portion of the first bit line overlap a source of a transistor of a memory cell of the first set of memory cells; and
generating a first set of via layout patterns, the first set of via layout patterns being located between the second layout level and the first layout level, and the first set of via layout patterns corresponding to fabricating vias coupled between the first portion of the first bit line and the second portion of the first bit line, a pair of vias of the first set of vias being located above where the first portion of the first bit line overlaps each memory cell of the first column of memory cells; and

manufacturing the memory cell array based on the layout design.