Patent ID: 11881477
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 7:
8. A computer-aided design process for forming an integrated chip, the process comprising:
generating an integrated circuit layout file comprising an oxide definition mask, wherein the oxide definition mask defines active device areas including a first active device area and a second active device area;
defining a shallow trench isolation structure, wherein the shallow trench isolation structure spans a distance between the first active device area and the second active device area and surrounds the first active device area and the second active device area so as to establish boundaries of the first active device area and the second active device area;
adding a first array of linear features to the integrated circuit layout file, wherein the first array of linear features extends over the first active device area;
adding a third array of linear features to the integrated circuit layout file, wherein the third array of linear features extends over the second active device area and is on grid with the first array of linear features;
inserting dummy fill into the integrated circuit layout file, wherein the dummy fill is directly over the shallow trench isolation structure and extends between the first active device area and the second active device area;
wherein the dummy fill is outside the active device areas;
the dummy fill comprises a second array of linear features, wherein the second array of linear features is on gird with the first array of linear features and the third array of linear features, whereby the first array of linear features, the second array of linear features, and the third array of linear features all have a pitch which is the same and fall on a grid having the pitch;
the integrated circuit layout file specifies a first mask for patterning the shallow trench isolation structure; and
the integrated circuit layout file specifies a second mask for simultaneously patterning the first array of linear features, the second array of linear features, and the third array of linear features.