Patent ID: 11956127
Assignee: ARTERIS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 12:
13. A computing system comprising a processor and computer-readable memory encoded with instructions that, when executed, cause a topology modification tool to:
receive an initial Network-on-Chip (NoC) topology that satisfies and is based on initial requirements, wherein the initial NoC topology includes elements and connections;
receive an update to the initial requirements, wherein the update results in updated requirements;
make incremental modifications to a portion of the initial NoC topology that is impacted by the updated requirements in order to satisfy the updated requirements and generate an incremental updated NoC topology, each incremental modification is in response to the update and changes existing components in the initial NoC topology, wherein the incremental modifications result in the initial NoC topology being outdated including at least one of an unnecessary element and an unnecessary connection;
remove at least one of the unnecessary element and the unnecessary connection;
generate an updated NoC topology that combines the initial NoC topology with the incremental updated NoC topology that satisfies the update; and
generate a computer readable format of the updated NoC topology thereby minimizing delays and costs resulting from topology modifications,
wherein minimizing changes includes preserving names of the existing components, which are part of the initial NoC topology, in the updated NoC topology.