Patent ID: 11966752
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. A memory system, comprising:
one or more devices; and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
store, in a linked mapping, a sequence of logical addresses of the memory system that are accessed as part of a first boot-up procedure;
increment, in the linked mapping and as part of the first boot-up procedure, a first counter associated with a first logical address of the sequence of logical addresses and a second counter associated with a second logical address of the sequence of logical addresses;
transfer, as part of a second boot-up procedure occurring after the first boot-up procedure, first information stored at the first logical address and second information stored at the second logical address from a non-volatile memory device to a volatile memory device based at least in part on the linked mapping;
receive a command to access the first logical address as part of the second boot-up procedure;
increment the first counter in the linked mapping based at least in part on receiving the command to access the first logical address; and
store a second sequence of logical addresses in a second linked mapping, based at least in part on a size of information associated with the first boot-up procedure and the second boot-up procedure.