Patent ID: 11934763
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. A method, comprising:
selecting a first wire in an array of wires wherein the first wire has a first width and is adjoined by a first open track;
adjusting a width of the first wire to a second width in a direction toward the first open track according to a resistance/capacitance (RC) table for a semiconductor device design;
calculating a switching speed of a first circuit element electrically connected to the first wire;
determining whether the switching speed of the first circuit element exceeds a performance specification; and
reducing the second width of the first wire, wherein the first wire, subsequent to reducing the second width, has a third width less than the second width, and a second switching speed, in response to determining the switching speed of the first circuit element exceeds the performance specification.