Patent ID: 11935932
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. A device comprising:
a gate electrode;
a source/drain region adjacent the gate electrode;
a first inter-layer dielectric over the source/drain region;
a second inter-layer dielectric over the first inter-layer dielectric;
a source/drain contact extending through the first inter-layer dielectric and the second inter-layer dielectric, the source/drain contact connected to the source/drain region;
a contact spacer surrounding the source/drain contact, the second inter-layer dielectric contacting a sidewall of the contact spacer; and
a void disposed between the sidewall of the contact spacer and the first inter-layer dielectric, a bottom surface of the second inter-layer dielectric exposed to the void.