Patent ID: 11923317
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 13:
14. A semiconductor device, comprising:
a substrate that comprises a plurality of chip regions and a scribe line between the plurality of chip regions;
a plurality of key patterns on the scribe line; and
a test element group (TEG) on the scribe line,
wherein the test element group comprises a plurality of pads that are spaced apart from each other in a first direction parallel to a top surface of the substrate,
wherein the plurality of key patterns are between the substrate and the plurality of pads,
wherein each of the plurality of key patterns vertically overlaps in a second direction with a corresponding one of the plurality of pads, the second direction being perpendicular to the top surface of the substrate, and
wherein the plurality of key patterns are at different levels in the second direction from the top surface of the substrate.