Patent ID: 11973016
Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 5:
6. A semiconductor device, comprising:
a semiconductor die comprising a vertical transistor device having a source electrode, a drain electrode and a gate electrode, the semiconductor die having a first surface and a second surface opposing the first surface;
a first metallization structure on the first surface and comprising at least one source pad coupled to the source electrode, at least one drain pad coupled to the drain electrode, and at least one gate pad coupled to the gate electrode;
a second metallization structure on the second surface and comprising a conductive layer and an electrically insulating inorganic layer and forming an outermost surface of the semiconductor device,
wherein the outermost surface of the second metallization structure is electrically insulated from the semiconductor die by the electrically insulating inorganic layer,
wherein the semiconductor die comprises a doped drain region forming the drain electrode and the second surface of the semiconductor die,
wherein the conductive layer of the second metallization structure comprises a metallic layer arranged directly on the second surface of the semiconductor die,
wherein the electrically insulating inorganic layer is arranged directly on the metallic layer.