Patent ID: 11900115
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A processor comprising:
a plurality of cores, each core of the plurality of cores comprising decode circuitry to decode instructions and execution circuitry to execute the instructions and process data;
a plurality of programmable interrupt controllers, each programmable interrupt controller associated with one or more cores of plurality of cores and to manage interrupt information for processing interrupts, including non-markable interrupts (NMIs), at least one of the programmable interrupt controllers comprising:
local interrupt processing circuitry including a plurality of registers to store entries of a local vector table (LVT), each entry of the LVT comprising a first plurality of fields to store information associated with a corresponding interrupt, the first plurality of fields including a first delivery mode field and a first vector field, wherein responsive to an NMI from a local NMI source, the first delivery mode field in a corresponding entry to store an indication of an NMI delivery mode, and the first vector field in the corresponding entry to store an indication of the local NMI source; and
inter-processor interrupt (IPI) processing circuitry comprising an interrupt command register (ICR) to store a second plurality of fields associated with an IPI, the second plurality of fields including a second delivery mode field and a second vector field, wherein based on an inter-processor NMI, the second delivery mode field in the ICR to store an indication of an NMI delivery mode and the second vector field to store an indication of a source of the inter-processor NMI.