Patent ID: 11880760
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. A processor, comprising: a first tile, a second tile, a memory, and a bus, the bus being connected to: the memory, the first tile, and the second tile, the first tile comprising: a first weight register, a second weight register, an activations cache, a shuffler, an activations buffer, and a plurality of multipliers, the plurality of multipliers comprising: a first multiplier, a second multiplier, a plurality of bit shifters, for shifting products involving at least one most significant nibble to be offset from products involving two least significant nibbles, and a plurality of accumulators, for accumulating outputs of the plurality of bit shifters, the multipliers of the plurality of multipliers being arranged in a plurality of columns and a group of lanes, the group of lanes including an adder tree for summing outputs of the multipliers, the activations buffer being configured to include: a first queue connected to the first multiplier, and a second queue connected to the second multiplier, the first queue comprising a first register and a second register, the first register of the first queue being an output register for the first queue, the second queue comprising a first register and a second register, the first register of the second queue being an output register for the second queue, the activations cache including a plurality of independent lanes, each of the independent lanes being randomly accessible, the first tile being configured: to receive a tensor of activations representing an image comprising a plurality of pixels each having a plurality of color components, the tensor comprising a plurality of two-dimensional arrays, each representing one color component of the image; and to perform a convolution of a kernel with one of the two-dimensional arrays.