Patent ID: 11862292
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A controller having programmed instructions that when executed cause the controller to:
determine whether to block updating a first register for a first clock cycle according to a second register and a third register, wherein the second register indicates a first entry storing an address of a memory bank, on which a write process is predicted to be completed next among a plurality of memory banks, wherein the third register indicates a second entry to be updated;
select, for the first clock cycle, the second entry, in response to determining that updating the first register for the first clock cycle is unblocked; and
update, for the first clock cycle, the second entry according to an input address of a target memory bank of the plurality of memory banks to store input data through the write process.