Patent ID: 11971821
Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A computing system with write-back and invalidation in a hierarchical cache structure based on one single designated key identification code, comprising:
a first core provided by a first processor that is fabricated on a first die, including
a decoder, a memory ordering buffer, and a first in-core cache module; and

a first last-level cache, fabricated in the first processor;
wherein:
in response to a first instruction of an instruction set architecture that is provided for write-back and invalidation in a hierarchical cache structure based on one single designated key identification code, the decoder outputs at least one microinstruction;
based on the at least one microinstruction, a write-back and invalidation request is provided to the first in-core cache module through the memory ordering buffer, and then passed to the first last-level cache by the first in-core cache module; and
in response to the write-back and invalidation request, the first last-level cache searches itself to determine which cache lines within the first last-level cache match the designated key identification code, wherein: if a matched cache line has been modified and does not exist in any upper-level cache, the first last-level cache writes back the matched cache line to a system memory; and, whether modified or not, all matched cache lines within the first last-level cache are invalidated.