Patent ID: 11967980
Assignee: INTEL CORPORATION
Field: Telecommunications (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 10:
11. A wireless device, comprising:
a plurality of transceiver chains;
processing circuitry; and
a memory configured to store executable instructions that, when executed by the processing circuitry, causes each transceiver chain from the plurality of transceiver chains to:
generate, from an input signal having an input signal frequency that is a fraction of an output signal frequency, a set of phase-shifted input signals at the input signal frequency,
output a subset of phase-shifted signals from among the set of phase-shifted input signals, and
combine and frequency multiply, via an injection locked clock multiplier (ILCM), the subset of phase-shifted signals to generate a set of LO signals at the output signal frequency,

wherein the subset of the phase-shifted signals have an equally-spaced phase-shift with respect to another that is a fraction of a full clock cycle, the fraction of the full clock cycle being equal to the fraction of the output signal frequency.