Patent ID: 11892909
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A system comprising:
a set of memory devices; and
a processing device, operatively coupled with the set of memory devices, to perform operations comprising:
detecting a failure of at least one memory device of the set, wherein the failure affects stored data;
notifying a host system of a change in a capacity of the set of memory devices;
receiving from the host system an indication to continue at a reduced capacity;
updating the set of memory devices to change the capacity to the reduced capacity, wherein the updating comprises reducing a quantity of bits stored per memory cell of one or more memory devices of the set of memory devices;
sending an indication to the host system that the set of memory devices comprise data in excess of the reduced capacity;
receiving, from the host system, a storage location for storing the data in excess of the reduced capacity;
storing the data in excess of the reduced capacity at the storage location; and
recovering, by the processing device, the stored data using recovery data in the set of memory devices.