Patent ID: 11861785
Assignee: QUALCOMM INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. An apparatus for ray tracing, comprising:
a memory; and
one or more processors coupled to the memory, the one or more processors configured to:
obtain an acceleration data structure, the acceleration data structure including one or more primitives of a scene object;
determine one or more child nodes of a root node of the acceleration data structure;
determine a Surface Area Heuristic (SAH) for each child node of the one or more child nodes;
determine a computational budget that corresponds to a maximum number of nodes for a graph cut;
determine the graph cut based on the determined SAH for each child node and the computational budget;
apply the graph cut to the acceleration data structure;
determine a set of nodes of the acceleration data structure based on the graph cut, wherein the set of nodes is located adjacent to the graph cut; and
generate a world-space bounding box for the scene object, wherein the world-space bounding box is generated for the set of nodes determined based on the graph cut.