Patent ID: 11886626
Assignee: UTIMACO, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 15:
16. An apparatus comprising:
a first substrate comprising one or more first traces configured to detect penetration of the first substrate;
a second substrate comprising one or more second traces configured to detect penetration of the second substrate;
one or more protected devices coupled to at least one of the first substrate or the second substrate, the one or more protected devices being disposed between the first substrate and the second substrate;
a plurality of gaskets coupled between the first substrate and the second substrate, the plurality of gaskets forming a first perimeter around the one or more protected devices, wherein each of the plurality of gaskets is electrically connected to each of the first substrate and the second substrate and is configured to detect an interruption of at least one of the electrical connection to the first substrate or the electrical connection to second substrate;
a plurality of second devices coupled to at least one of the first substrate or the second substrate, the plurality of second devices forming a second perimeter around the one or more protected devices, wherein the plurality of second devices inhibit penetration laterally between the first substrate and the second substrate, wherein the plurality of second devices form a first row of devices and a second row of devices, wherein the devices of the second row are staggered with respect to the devices of the first row; and
an electrical connector held in compression between the first substrate and the second substrate, wherein the electrical connector circumscribes the one or more protected devices.