Patent ID: 11875994
Assignee: NANYA TECHNOLOGY CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for preparing a semiconductor device structure, comprising:
forming a target layer over a semiconductor substrate at a position that a bottom surface of the target layer is overlapped on a top surface of the semiconductor substrate;
forming a plurality of first energy-sensitive patterns over the target layer;
forming a lining layer conformally covering the first energy-sensitive patterns, wherein a first opening is formed over the lining layer and between the first energy-sensitive patterns;
filling the first opening with a second energy-sensitive pattern; and
performing an etching process to form a plurality of second openings and a third opening in the target layer, wherein the third opening is between the second openings, wherein each of the second openings has a bottom wall defining a depth thereabove and positioning above the bottom surface of the target layer, wherein the third opening has a bottom wall defining a depth thereabove and positioning above the bottom surface of the target layer, wherein the bottom wall of each of the second openings is positioned below the bottom wall of the third opening, such that the depth of each of the second openings is larger than the depth of the third opening.