Patent ID: 11960722
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. A memory device comprising:
an array of memory cells comprising a plurality of blocks of memory cells; and
a controller configured to access the plurality of blocks of memory cells,
wherein the controller is further configured to:
program a first number of bits to each memory cell of a first block of memory cells of the plurality of blocks of memory cells;
program a second number of bits to each memory cell of a second block of memory cells of the plurality of blocks of memory cells, the second number of bits being greater than or equal to the first number of bits;
following a period after programming each memory cell of the second block of memory cells, merge at least a subset of the first number of bits stored in each memory cell of the first block of memory cells to the second number of bits stored in a corresponding memory cell of the second block of memory cells without erasing the second block of memory cells such that the second number of bits plus at least the subset of the first number of bits are stored in each memory cell of the second block of memory cells; and
prior to merging at least the subset of the first number of bits stored in each memory cell of the first block of memory cells to the second number of bits stored in the corresponding memory cell of the second block of memory cells, perform a touch up programming operation on one or more memory cells of the second block of memory cells to increase a threshold voltage of each of the one or more memory cells towards a respective desired threshold voltage of each of the one or more memory cells, and

an error correction code (ECC) engine configured to monitor the second block of memory cells and instruct the controller to perform the touch up programming operation on the one or more memory cells of the second block of memory cells in response to the second block of memory cells comprising a raw bit error rate greater than or equal to a threshold raw bit error rate.