Patent ID: 11868775
Assignee: IMAGINATION TECHNOLOGIES LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 15:
16. A device comprising:
a processor; and
a memory arranged to store device-executable instructions configured when executed by the processor to cause the processor, in response to receiving mapping data for an instruction set and instruction data describing instructions in an instruction set in canonical form, to:
parse the mapping data and instruction data using a grammar library;
generate both encoding software and a hardware description of a decoder based on the parsed mapping data and instruction data; and
output the encoding software and the hardware description of a decoder;
wherein the encoding software maps different instructions in the instruction set to different numbers of instruction words by, for each instruction of a plurality of instructions in the instruction set:
re-ordering and grouping bits in the instruction into a plurality of instruction words according to an encoding type to generate an ordered sequence of instruction words; and
comparing the instruction words in the ordered sequence to their corresponding predicted values and generating a compressed version of the instruction by omitting one or more of the instruction words in the ordered sequence based on the comparison.