Patent ID: 11942171
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. An apparatus comprising:
a memory cell array comprising a mat having a plurality of row sections, wherein each of the plurality of row sections includes respective prime memory cell rows and a respective redundant memory cell row; and
a global decoder comprising a plurality of control circuits each corresponding to a respective one of the plurality of row sections and each configured to receive a respective prime section signal and a respective redundant section signal from a row decoder, wherein, in response to the respective prime section signal, a first corresponding control circuit of the plurality of control circuits is configured to initiate a first threshold voltage compensation operation on first sensing circuitry coupled to a first respective one of the plurality of row sections, wherein, in response to the respective redundant section signal indicating a defective prime row, a second corresponding control circuit of the plurality of control circuits is configured to initiate a second threshold voltage compensation operation on second sensing circuitry coupled to a second respective one of the plurality of row sections concurrent with the first threshold voltage compensation operation.