Patent ID: 11962440
Assignee: QUALCOMM INCORPORATED
Field: Digital communication (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A comparator, comprising:
an input stage, comprising:
a first input circuit coupled to a first node and a second node, the first input circuit configured to receive an input of the comparator and a first compare voltage including a first offset-cancellation component;
a first switching transistor configured to enable the first input circuit if a previous bit value is one;
a second input circuit coupled to the first node and the second node, the second input circuit configured to receive the input of the comparator and a second compare voltage including a second offset-cancellation component, wherein the first offset-cancellation component and the second offset-cancellation component contribute to cancellation of an offset voltage of the comparator; and
a second switching transistor configured to enable the second input circuit if the previous bit value is zero;

a regeneration stage, comprising:
a first inverter;
a second inverter cross coupled with the first inverter;
a first drive transistor coupled to the first inverter, wherein a gate of the first drive transistor is coupled to the second node; and
a second drive transistor coupled to the second inverter, wherein a gate of the second drive transistor is coupled to the first node; and

an offset cancellation circuit, comprising:
a first offset transistor coupled to the second node, wherein a gate of the first offset transistor is configured to receive a first offset-cancellation voltage; and
a second offset transistor coupled to the first node, wherein a gate of the second offset transistor is configured to receive a second offset-cancellation voltage, and the offset cancellation circuit contributes to the cancellation of the offset voltage of the comparator.