Patent ID: 11901221
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for forming an integrated chip, the method comprising:
forming a pair of dielectric structures over a substrate and on opposite sides of a first metal line, the pair of dielectric structures comprising a first dielectric;
selectively forming a blocking layer directly over a top surface of the first metal line;
selectively forming a pair of protective etch-stop structures on top surfaces of the pair of dielectric structures, the pair of protective etch-stop structures comprising a second dielectric, different from the first dielectric;
removing the blocking layer from directly over the top surface of the first metal line;
depositing an interlayer dielectric (ILD) layer over the pair of protective etch-stop structures and over the first metal line;
etching the ILD layer to uncover the top surface of the first metal line, wherein the etching is selective to the ILD layer, and wherein the pair of protective etch-stop structures remain on the top surfaces of the pair of dielectric structures throughout the etching; and
forming a metal via directly over the first metal line, wherein the metal via is separated from a first dielectric structure of the pair of dielectric structures by a first protective etch-stop structure of the pair of protective etch-stop structures.