Patent ID: 11915057
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. An apparatus comprising:
a first, synchronous network;
a second, packet network;
a plurality of configurable circuits arranged in an array, each configurable circuit of the plurality of configurable circuits coupled to the synchronous network, each configurable circuit of the plurality of configurable circuits comprising:
a packet network output queue coupled to the second, packet network, the packet network output queue configured to generate a stop signal when a predetermined threshold has been reached in the packet network output queue;
a configurable computation circuit configurable to perform a plurality of computations;
a configuration memory coupled to the configurable computation circuit, the configuration memory comprising:
a first instruction memory configured to store a first plurality of configuration instructions to configure the configurable computation circuit; and
a second instruction memory configured to store a second plurality of configuration instructions or instruction indices for selection of a configuration instruction of the first plurality of configuration instructions from the first instruction memory, for selection of a network input from the synchronous network for receipt of the configuration instruction or a configuration instruction index from another configurable circuit of the plurality of configurable circuits of the array, and for selection of a next configuration instruction or instruction index for output to a next configurable circuit of the plurality of configurable circuits;

a flow control circuit coupled to the packet network output queue of each of the configurable circuits within a separate partition of configurable circuits of a plurality of partitions of configurable circuits, the flow control circuit configured to assert a stop signal to all configurable circuits within the separate partition of configurable circuits;
a partition enable circuit coupled to each flow control circuit of the plurality of separate partitions of configurable circuits; and
a dispatch interface circuit coupled to the partition enable circuit and further coupled to the plurality of configurable circuits through the second, packet network, the dispatch interface circuit configured to partition the plurality of configurable circuits into the plurality of separate partitions of configurable circuits; to select a plurality of thread identifiers for each partition of configurable circuits; to balance loads across the plurality of separate partitions of configurable circuits by starting threads for execution in the partition having the highest number of available thread identifiers; and to assert a partition enable signal to the partition enable circuit to merge the plurality of separate partitions of configurable circuits and assert the stop signal to all configurable circuits of the plurality of separate partitions of configurable circuits.