Patent ID: 11889696
Assignee: MICRON TECHNOLOGY, INC.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 15:
16. A method used in forming a memory array comprising strings of memory cells, comprising:
forming a conductor tier comprising conductor material on a substrate;
forming a lower portion of a stack that will comprise vertically-alternating first tiers and second tiers above the conductor tier, the stack comprising laterally-spaced memory-block regions, material of the first tiers being of different composition from material of the second tiers, a lowest of the first tiers comprising first sacrificial material;
forming horizontally-elongated troughs in the lowest portion that extend to the conductor tier;
laterally recessing the second-tier material of the second tier that is immediately-above the lowest first tier to form laterally-opposed recesses longitudinally-along individual of the troughs;
after the recessing, forming horizontally-elongated lines in the troughs that are individually between immediately-laterally-adjacent of the memory-block regions, the lines individually comprising laterally-opposing projections longitudinally-there-along that are in the laterally-opposed recesses, the lines comprising second sacrificial material;
forming the vertically-alternating first tiers and second tiers of an upper portion of the stack above the lower portion and the lines,
forming channel-material-string structures that extend through first tiers and the second tiers in the upper portion to the lowest first tier in the lower portion;
forming horizontally-elongated trenches into the stack that are individually between the immediately-laterally-adjacent memory-block regions and extend to the line there-between;
removing the second sacrificial material of the lines through the trenches; and
forming intervening material in the trenches and void-spaces left as a result of the removing of the second sacrificial material of the lines.