Patent ID: 11934310
Assignee: CENTAUR TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A method for handling zero valued data in a microprocessor comprising plural cores, each of the cores comprising a level 1 (L1) cache and a level 2 (L2) cache, the microprocessor further comprising a shared level 3 (L3) cache comprising plural L3 tag array entries, each of the plural L3 tag array entries comprising tag information, wherein a first portion of the plural L3 tag array entries is associated with data in the shared L3 cache and a second portion of the plural L3 tag array entries is decoupled from data in the shared L3 cache and available in the L2 cache of one of the plural cores, the method comprising:
receiving a load request at the shared L3 cache; and
returning a data value of zero without performing a data read based on a load request hit in the shared L3 cache.