Patent ID: 11876622
Assignee: INTEL CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A forward-error-correction (FEC) decoder that is suitable for use with hard-decision input at a receiver and for use with soft-decision input at the receiver, comprising:
Low-Density Parity Check (LDPC) decoder circuitry configured to obtain an input signal as Log-Likelihood-Ratio (LLR) values; and decode the input signal using LDPC iterative decoding that is based on an LDPC code; and
output circuitry configured to generate a binary output from the decoded input signal from the LDPC decoder circuitry,
wherein the LDPC decoder circuitry is configured to decode the input signal either:
a) using a single LDPC code that is suitable for use with soft-decision input and hard-decision input at the receiver, wherein the input signal is decoded using the same LDPC code with hard-decision input at the receiver and with soft-decision input at the receiver, and the single LDPC code uses a first set of puncturing bits and/or a first set of shortening bits for use with soft-decision input at the receiver and second set of puncturing bits and/or a second set of shortening bits for use with hard-decision input at the receiver, or
b) using one of two LDPC codes that are suitable for soft-decision input and hard-decision input, respectively, wherein one of the two LDPC codes is used for use with soft-decision input at the receiver and the other of the two LDPC codes is used for use with hard-decision input at the receiver.