Patent ID: 11899963
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. An apparatus, comprising:
a controller configured to couple with a memory system, wherein the controller is configured to cause the apparatus to:
transmit data for writing to a memory device of the memory system, the data associated with a plurality of planes of the memory device;
receive an indication that a first plane of the plurality of planes has a latency for writing a first subset of the data that is greater than a threshold latency; and
transmit an indication that the memory device is to delay writing a second subset of the data to the first plane until a remainder of the data is written to a remainder of the plurality of planes, wherein the remainder of the data excludes the first and second subsets of the data, and wherein the remainder of the plurality of planes excludes the first plane.