Patent ID: 11894267
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. The method of claim 1, wherein forming the first and second conductive features comprises:
etching openings in the first and second portions of the first interlayer dielectric layer, respectively;
filling the openings with a conductive material; and
performing a planarization process to remove the conductive material from a top surface of the first interlayer dielectric layer, such that a top surface of the first conductive feature is higher than a top surface of the first portion of the first interlayer dielectric layer, wherein forming the memory structure is performed such that the memory structure comprises a bottom electrode layer below the resistance switching element, and a bottommost portion of a bottom surface of the bottom electrode layer is lower than the top surface of the first conductive feature.