Patent ID: 11916062
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Electrical machinery, apparatus, energy (Electrical engineering)
Classification: CPC H | IPC H

Claim 22:
23. A microelectronic device, comprising:
a protected line;
a reference line separate from the protected line;
an active field effect transistor (FET) having a drain coupled to the protected line, a source coupled to the reference line, and a gate;
an electrostatic discharge (ESD) trigger circuit coupled to the gate of the active FET, wherein the ESD trigger circuit includes an ESD trigger high-pass filter coupled between the protected line and the reference line, the ESD trigger high-pass filter having a time constant of 5 nanoseconds to 20 nanoseconds, the ESD trigger high-pass filter having an ESD trigger output line coupled to the gate of the active FET;
a shunt transistor between the gate of the active FET and the reference line, the shunt transistor having a gate; and
a transient detection circuit having a high bandwidth detector, an ESD detector, and an output driver, wherein:
the high bandwidth detector includes a blocking capacitor coupled between the protected line and the output driver, wherein the blocking capacitor is configured to provide an ENABLE signal to the output driver when a first overvoltage transient occurs on the protected line, the first overvoltage transient being characteristic of an ESD event;
the ESD detector includes:
an input high-pass filter and a voltage discriminator, the input high-pass filter being coupled between the protected line and the reference line, the input high-pass filter having a time constant of 5 nanoseconds to 20 nanoseconds;

a voltage discriminator, including:
an upper input FET in series with a lower input FET, wherein a drain of the upper input FET is coupled to the blocking capacitor of the high bandwidth detector, a source of the lower input FET is coupled to the reference line, a source of the upper input FET is coupled to a drain of the lower input FET, and gates of the upper input FET and the lower input FET are coupled to an output line of the input high-pass filter;
a first output line coupled to the output driver and a second output line coupled to the output driver; and
an output FET having a source coupled to the source of the upper input FET and the drain of the lower input FET, a drain coupled to the output line of the voltage discriminator, and a gate coupled to the input high-pass filter; and

the output driver includes an output FET, a low-pass filter with an output node, the output FET having a drain coupled to the protected line, a source coupled to the low-pass filter, and a gate coupled to the protected line through the blocking capacitor, and to the second output line of the voltage discriminator, the low-pass filter being coupled between the source of the output FET and the reference line, the output node being coupled to a gate of an active FET shunt transistor of a gate control circuit and to the first output line of the voltage discriminator.