Patent ID: 11929321
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. The method as claimed in claim 9, further comprising:
forming a second gate electrode layer and a second source/drain contact over the substrate; and
forming a third metal via to connect the second gate electrode layer, and a fourth metal via to connect the second source/drain contact before forming the organic film, wherein the organic film exposes a top surface of the third metal via and a top surface of the fourth metal via; and
growing a third metal feature with a convex top surface from the exposed top surface of the third metal via and a fourth metal feature with a convex top surface from the exposed top surface of the fourth metal via by the deposition process using the metal inhibition layer,
wherein each of the first metal bump, the second metal bump, the third metal bump, and the fourth metal bump has a bottom area greater than a top area of each of the first metal via, the second metal via, the third metal via, and the fourth metal via.