Patent ID: 11861223
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A storage device, comprising:
a memory device including a plurality of planes; and
a memory controller configured to store, in a first read command queue, a first read command and a first physical address in response to a read request, the first read command instructing the memory device to perform a read operation including reading data stored in the memory device by using the first physical address mapped to a logical address,
wherein the memory controller is further configured to sequentially provide read commands and physical addresses, which are stored in the first read command queue, to the memory device according to a scheduled sequence, and wherein
each of the physical addresses includes a plane number, a block number, and a page number, and
when a page number of a second physical address scheduled in a first priority index number among index numbers of the first read command queue and a page number of the first physical address are equal, the memory controller is configured to schedule the first physical address in the first priority index number.