Patent ID: 11967395
Assignee: MEDIATEK INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 4:
5. The buffer as claimed in claim 3, further comprising:
a second signal input terminal; and
a second signal output terminal;
wherein the path circuit is further coupled between the second signal input terminal and the second signal output terminal and further comprises:
a third inductor coupled between the second signal input terminal and a fourth node;
a third switch coupled between the fourth node and a fifth node;
a fourth inductor coupled between the fifth node and the second signal output terminal;
a fourth switch coupled between the voltage source terminal and a sixth node; and
a second resistor coupled between the sixth node and the fifth node,
wherein the amplifier further has a second input terminal coupled to the fourth node and a second output terminal coupled to the second signal output terminal,
wherein in response to the buffer operating at the first mode, the third switch is turned on, and the fourth switch is turned off, and
wherein in response to the buffer operating at the second mode, the third switch is turned off, and the fourth switch is turned on.