Patent ID: 11960717
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 9:
10. A method, comprising:
receiving, at a power management integrated circuit (PMIC), a first signal from a memory device of a memory system via a first conductive path coupled with a first loopback pin of the memory device while one or more components of the PMIC is in a deactivated state, the first signal sent outside a testing phase of operation, wherein:
a transistor, which electrically separates the first loopback pin from the first conductive path, selectively couples the first loopback pin of the memory device with the PMIC based at least in part on receiving a second signal via a second loopback pin of the memory device coupled with a gate of the transistor, wherein the second signal is received outside a testing phase of operation and activates the transistor outside the testing phase of operation, and wherein:
the first loopback pin and the second loopback pin are each configured to communicate feedback data during the testing phase of operation; and

activating the one or more components of the PMIC based at least in part on receiving the first signal from the memory device via the first conductive path.