Patent ID: 11973061
Assignee: YIBU SEMICONDUCTOR CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A package, comprising:
a rewiring layer including a first side and a second side;
a plurality of bumps disposed on the first side of the rewiring layer;
a first chip stack disposed on the second side of the rewiring layer, the first chip stack including stacked first chips facing the rewiring layer;
a first chip connector stack and a second chip connector stack on the second side of the rewiring layer and flanking the first chip stack; and
a second chip placed over the first chip stack and assembled over the first chip connector stack and the second chip connector stack,
wherein at least the first chip stack is encapsulated in a molding compound; and
wherein the rewiring layer is formed on a bottom side of the first chip stack and on a bottom side of each of the first chip connector stack and the second chip connector stack; and
wherein chip connectors in each chip connector stack of the first and second chip connector stacks respectively correspond to first chips of the stacked first chips, each chip connector in the each chip connector stack has a top surface facing away from the rewiring layer, a bottom surface facing the rewiring layer, top connector contacts formed on the top surface, bottom connector contacts formed on the bottom surface, and through vias between the top surface and the bottom surface, each respective through via of the through vias extending through the each chip connector to couple a respective top connector contact to a respective bottom connector contact.