Patent ID: 11875748
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A gate driving circuit, comprising: a frequency doubling control circuit and an effective output circuit, the effective output circuit comprises a plurality of first shift registers cascaded, the first shift register at a first stage in the effective output circuit is provided with a first signal input terminal and a second signal input terminal, the first signal input terminal is coupled with an output control signal line, the second signal input terminal is coupled with the frequency doubling control circuit, each of other first shift registers except the first shift register at the first stage in the effective output circuit is provided with a first cascade signal input terminal, and the first cascade signal input terminal of each of the other first shift registers is coupled with a signal output terminal of the first shift register in a previous stage corresponding thereto;
the frequency doubling control circuit is coupled with the output control signal line and configured to provide, in response to a control of an output control signal provided by the output control signal line, a frequency doubling control signal to the second signal input terminal after a preset time period elapses from receiving of the output control signal; and
the first shift register at the first stage is configured to output a scanning signal in response to a control of the output control signal and to output a scanning signal in response to a control of the frequency doubling control signal,
wherein in the frequency doubling control circuit, the second shift register comprises: a signal writing circuit, a first control circuit, a second control circuit and a signal output circuit;
the signal writing circuit, the first control circuit, the second control circuit, and the signal output circuit are coupled to a first node, both the first control circuit and the second control circuit are coupled to a second node, and both the second control circuit and the signal output circuit are coupled to a third node;
the signal writing circuit is coupled with a corresponding signal input terminal and a first clock signal terminal and is configured to write, in response to a control of a first clock signal provided by the first clock signal terminal, a signal provided by the corresponding signal input terminal into the first node;
the first control circuit is coupled with a first power supply terminal and the first clock signal terminal, and is configured to write a first operating voltage provided by the first power supply terminal into the second node in response to the control of the first clock signal, and to write the first clock signal into the second node in response to a control of a voltage at the first node;
the second control circuit is coupled to a second power supply terminal and a second clock signal terminal, and is configured to write a second clock signal into the third node in response to a control of a voltage at the second node and the second clock signal provided by the second clock signal terminal, and to write a second operating voltage provided by the second power supply terminal into the third node in response to the control of the voltage at the first node;
the signal output circuit is coupled with the first power supply terminal and the second power supply terminal, and is configured to write the first operating voltage into the signal output terminal in response to the control of the voltage at the first node, and to write the second operating voltage into the signal output terminal in response to a control of a voltage at the third node, and
wherein in the effective output circuit, the first signal input terminal and the second signal input terminal of the first shift register at the first stage are different signal input terminals;
the first shift register at the first stage is provided with a second switch circuit and a third switch circuit;
the second switch circuit is located between the signal writing circuit and the first signal input terminal, is coupled with the second signal input terminal, and is configured to write, in response to a control of a signal provided by the second signal input terminal, a signal provided by the first signal input terminal into the signal writing circuit;
the third switch circuit is arranged between the signal writing circuit and the second signal input terminal, is coupled with the first signal input terminal, and is configured to write, in response to a control of the signal provided by the first signal input terminal, signal provided by the second signal input terminal into the signal writing circuit.