Patent ID: 11909421
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G  Y | IPC G  H

Claim 9:
10. The MAC operator of claim 7, wherein the second 4:1 demultiplexer is configured to:
generate an 11-bit mantissa obtained by adding an implicit bit to the 10-bit mantissa of the 16-bit input data input to the first input terminal,
generate an 11-bit mantissa obtained by adding an implicit bit and lower one ‘0’ bit to the 9-bit mantissa of the 16-bit input data input to the second input terminal,
generate an 11-bit mantissa obtained by adding an implicit bit and lower two ‘0’ bits to the 8-bit mantissa of the 16-bit input data input to the third input terminal; and
generate an 8-bit mantissa obtained by adding an implicit bit and lower three ‘0’ bits to the 7-bit mantissa of the 16-bit input data input to the third input terminal.