Patent ID: 11930631
Assignee: FUJIAN JINHUA INTEGRATED CIRCUIT CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. A semiconductor memory device comprising:
a substrate;
a plurality of bit lines, separately disposed on the substrate;
a plurality of plugs, disposed on the substrate, the plugs and the bit lines are alternately arranged with each other;
a spacer structure, disposed on the substrate between each of the bit lines and each of the plugs, wherein the spacer structure comprises a first air gap layer, a first spacer and a second air gap layer, and the first air gap layer, the first spacer and the second air gap layer are sequentially stacked between sidewalls of the bit lines and the plugs;
a plurality of storage node pads, disposed on the plugs and the bit lines, wherein the storage node pads respectively contact the plugs; and
a plurality of capacitors, disposed on the storage node pads to respectively in alignment with the storage node pads, each of the capacitors comprising a bottom electrode layer, a capacitor dielectric layer, and a top electrode layer stacked sequentially, wherein a bottommost surface of the capacitor dielectric layer is lower than a bottom surface of the storage node pads.