Patent ID: 11960408
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 2:
3. The semiconductor memory device of claim 2, wherein:
the first and second upper sub-cache blocks and the first and second lower sub-cache blocks are electrically connected to the upper sub-common column decoder block of the first sub-common column decoder block,
the third and fourth upper sub-cache blocks and the third and fourth lower sub-cache blocks are electrically connected to the lower sub-common column decoder block of the first sub-common column decoder block,
the fifth and sixth upper sub-cache blocks and the fifth and sixth lower sub-cache blocks are electrically connected to the upper sub-common column decoder block of the second sub-common column decoder block,
the seventh and eighth upper sub-cache blocks and the seventh and eighth sub-cache blocks are electrically connected to the lower sub-common column decoder block of the second sub-common column decoder block,
the ninth and tenth upper sub-cache blocks and the ninth and tenth lower sub-cache blocks are electrically connected to the upper sub-common column decoder block of the third sub-common column decoder block, and
the eleventh and twelfth upper sub-cache blocks and the eleventh and twelfth lower sub-cache blocks are electrically connected to the lower sub-common column decoder block of the third sub-common column decoder block.