Patent ID: 11923042
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 18:
19. An apparatus comprising:
a memory controller; and
a memory device connected to the memory controller by a bus, wherein the memory device receives a data clock from the memory controller via the bus and the memory controller receives a read clock from the memory device via the bus,
the data clock controls data write timing during a write operation executed by the memory device and the read clock controls read timing during a read operation executed by the memory device,
the memory device is configured to perform first duty cycle monitoring that monitors a duty cycle of the data clock and generates a first result, provide a timing-adjusted data clock in response to the first duty cycle monitoring, generate a read clock offset code in response to the first result, and correct a duty error of the read clock using the read clock offset code, and
the read clock offset code indicates a difference between a first propagation delay associated with a write data path used to communicate data from the memory controller to the memory device and a second propagation delay associated with a read data path used to communicate data from the memory device to the memory controller.