Patent ID: 11955159
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 12:
13. A memory system comprising:
a semiconductor memory device; and
a memory controller configured to control the semiconductor memory device,
wherein the semiconductor memory device includes:
a memory cell array including a plurality of memory cell rows, each including a plurality of memory cells;
a row hammer management circuit configured to:
count a number of times of access associated with each of the plurality of memory cell rows in response to an active command from the memory controller to store the counted values in each of the plurality of memory cell rows as count data;
determine a hammer address associated with least one of the plurality of memory cell rows, which is intensively accessed more than a predetermined reference number of times, based on the counted values; and
in response to a first command applied after the active command, perform an internal read-update-write operation to read the count data from a target memory cell row from among the plurality of memory cell rows, to update the read count data, and to write the updated count data in the target memory cell row; and
a refresh control circuit configured to receive the hammer address and to perform a hammer refresh operation on one or more victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address,
wherein the memory controller is configured to apply a second command to the semiconductor memory device before the first command is applied and after the active command is applied to the semiconductor memory device such that the row hammer management circuit is configured to perform the internal read-update-write operation in response to the first command,
wherein the first command is applied from the memory controller after a predetermined delay time from the second command, and
wherein the second command is applied associated with a memory operation on the target memory cell row.