Patent ID: 11876022
Assignee: TOKYO ELECTRON LIMITED
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A substrate treatment method, comprising:
generating, for each of layers constituting a stacked film on a substrate, a captured image of the substrate after a treatment regarding a relevant layer, wherein the captured image includes a table associating coordinates of a plurality of regions of the substrate with corresponding pixel values, each pixel value representing red, green, blue values of a corresponding region of the substrate; and
acquiring information indicating a dimension estimated based on the captured image for each of the layers constituting the stacked film on the substrate including an outermost layer of the stacked film on the substrate, wherein
the dimension of each of the layers constituting the stacked film on the substrate is estimated based on the captured image of the substrate generated for the relevant layer;
the information indicating the dimension includes information on an in-plane distribution of a pixel value in the captured image correlating with the dimension; and
the substrate treatment method further comprises:
acquiring correlation information indicating a correlation between the dimension and the pixel value;
determining whether the dimension expresses an abnormal value or not; and
when the dimension is determined to express the abnormal value, determining based on the information on the in-plane distribution of the pixel value correlating with the dimension and the correlation information, whether the abnormal value is caused by inaccuracy of the correlation information.