Patent ID: 11887957
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A method of manufacturing semiconductor device, the method comprising:
forming an under-bump pattern and a protective layer on a semiconductor substrate;
forming a first seed layer on the under-bump pattern and the protective layer;
forming a second seed layer on the first seed layer;
forming a resist pattern comprising a guide opening on the second seed layer, the guide opening exposing at least a portion of a top surface of the second seed layer which overlaps the under-bump pattern;
forming a first opening in the second seed layer by performing a first etching process in the guide opening of the resist pattern;
forming a second opening in the first seed layer by performing a second etching process in the first opening; and
forming a bump pattern on the under-bump pattern.