Patent ID: 11876651
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 15:
16. The driving adjustment circuit of claim 10, wherein the second NOT gate comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor;
a first end of the first transistor and a first end of the fifth transistor are connected to the first adjustment signal, a first end of the second transistor and a first end of the fourth transistor are connected to the first enable signal, and a first end of the third transistor and a first end of the sixth transistor are connected to the second enable signal;
a second end of the first transistor is connected to a first power supply signal, a second end of the second transistor is connected to a second power supply signal, and both a third end of the fifth transistor and a third end of the sixth transistor are connected to a ground signal;
a third end of the first transistor is connected to a third end of the second transistor, a second end of the third transistor, and a second end of the fourth transistor, and is used to output the second first adjustment signal; and
a third end of the third transistor is connected to a third end of the fourth transistor, a second end of the fifth transistor, and a second end of the sixth transistor, and is used to output the second second adjustment signal.