Patent ID: 11922055
Assignee: SEAGATE TECHNOLOGY LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A method comprising:
initiating communication between a controller and a ferroelectric stack register memory having a first arrangement of ferroelectric memory cells (FMEs) having a first construction arranged to provide a first number of cache lines adapted to respectively receive a corresponding first number of data entries from the processor and a second arrangement of FMEs having a different, second construction arranged to provide a second number of cache lines adapted to respectively receive a corresponding second number of data entries from the processor;
using the controller to store a first data set to the first number of cache lines of the first arrangement and a second data set to the second number of cache lines of the second arrangement; and
utilizing a pointer mechanism to provide pointers to point to each of the respective first and second numbers of cache lines based on a time sequence of operation of the controller.