Patent ID: 11908384
Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
Field: Electrical machinery, apparatus, energy (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A method for generating a PWM signal by a circuit comprising
a shift register comprising a plurality of clock-controlled register units each having an input and an output,
a write unit configured to set the outputs of the register units each to a designated logic value, and, a clock generator configured to output a clock signal, wherein the register units are connected in series, so that in each case a logic value at the output of one of the register units is present at the input of the respectively following register unit,, a) wherein the outputs of the register units are each set to a predetermined logical value by the write unit, and, b) the register units are operated together by the clock signal,
wherein the register units take over the respective logical value of the input at the output with each clock pulse,
wherein the clock signal is cyclic,
wherein during a cycle the duration of successive clocks increases,
wherein the shift register outputs the PWM signal at an output contact, the PWM signal being a chronological sequence of the logic values set in the register units, and the PWM signal assumes each of the logic values with the duration of one clock of the clock signal, and
wherein one or more of:
ascending ordinal numbers are assigned to the register units starting from the output contact,
the output of the register unit with the lowest ordinal number is coupled to the input of the register unit with the highest ordinal number, and
between two executions of the process step a) the process step b) is executed over a duration of several cycles; or
a holding unit is coupled between the output contact and the output of a first register unit of the plurality of register units,
in a first state, the holding unit sets the output contact to the logic value provided at the output of the first register unit,
in a second state, the holding unit sets the logical value of the output contact,
the holding unit is in the second state during step a), and
the holding unit is in the first state during step b).