Patent ID: 11860670
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A processor comprising:
multiple route tables to provide entries corresponding to different respective memory access resources, wherein the multiple route tables comprise:
a first route table which is to correspond to a first table identifier; and
a second route table which is to correspond to a second table identifier;

a repository to store reference information which represents a list of items corresponding to different respective ranges of addresses, wherein the items are each to comprise an identifier of a respective one of the multiple route tables, and an identifier of a respective index offset, wherein the items are to comprise:
a first item comprising the first table identifier and an identifier of a first index offset; and
a second item comprising the second table identifier and an identifier of a second index offset; and

first circuitry coupled to the multiple route tables and to the repository, the first circuitry to:
perform a first access of the first item based on a physical address of a memory access request, wherein the first item corresponds to a first address range which comprises the physical address;
based on the first access:
determine a first index which is based on both the physical address and the identifier of the first index offset;
determine, based on the first table identifier, that the first route table comprises memory access information corresponding to a first memory access resource which is a target of the memory access request; and
perform a second access of the first route table, with the first index, to identify the memory access information; and

generate a signal, based on the second access, to indicate that the memory access request is to be directed to the first memory access resource.