Patent ID: 11915743
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 8:
9. The method of claim 8, further comprising:
coupling a first data input transistor between the first bit line and the second voltage terminal;
coupling a first input terminal of a first NOR gate to the word line to receive the clock signal;
coupling a second input terminal of the first NOR gate to receive a data input signal;
coupling an output terminal of the first NOR gate to a gate of the first data input transistor;
coupling a second data input transistor between the second bit line and the second voltage terminal;
coupling a first input terminal of a second NOR gate to the word line to receive the clock signal;
coupling a second input terminal of the second NOR gate to receive a complement of the data input signal; and
coupling an output terminal of the second NOR gate to a gate of the second data input transistor.