Patent ID: 11923859
Assignee: INTEL CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 15:
16. A digital frequency synthesizer, comprising:
a reference signal generator configured to generate a reference clock signal;
a time-to-digital-converter (TDC), the TDC configured to receive an output signal and the reference clock signal, and generate a plurality of time-to-digital conversion phase samples based on the output signal and the reference clock signal;
a cycle counter (CC), the CC configured to receive the output signal and the reference clock signal, and generate a clock cycle count based on the output signal and the reference clock signal; and
a frequency estimator, the frequency estimator configured to:
generate a cycle count based frequency estimation of the output signal based on the reference clock signal and the clock cycle count;
generate a fractional frequency estimation of the output signal based on the reference clock signal and a plurality of time-to-digital conversion phase samples of the output signal; and
generate a frequency estimate of the output signal using the cycle count based frequency estimation within a range and a frequency error determined from the fractional frequency estimation, wherein the plurality of time-to-digital conversion phase samples and the cycle count based frequency estimation use a same number of reference clock cycles of the reference clock signal.