Patent ID: 11948798
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A method for manufacturing an integrated circuit, the method comprising:
forming a first layer over a substrate;
forming a first patterned layer over the first layer, the first patterned layer having a first pattern feature and a second pattern feature;
forming a photomask layer over the first patterned layer;
patterning the photomask layer to form a gap therethrough, wherein the gap extends between the first pattern feature and the second pattern feature;
forming a first material layer along sidewalls of the gap;
forming a second material layer over the first material layer, wherein a combined thickness of the first material layer and the second material layer in the gap is greater than a height of the first pattern feature and the second pattern feature;
removing the photomask layer; and
transferring a pattern formed by the second material layer to the first layer.