Patent ID: 11894247
Assignee: NANYA TECHNOLOGY CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 5:
6. A method of manufacturing a semiconductor device, comprising:
forming a dielectric layer on a substrate;
etching the dielectric layer to create a plurality of openings in the dielectric layer;
applying a sacrificial layer in at least one of the openings to cover at least a portion of the dielectric layer;
forming at least one first conductive feature in the openings where the sacrificial layer is disposed and a plurality of bases in the openings where the sacrificial layer is not disposed;
removing the sacrificial layer to form at least one air gap in the dielectric layer;
forming a plurality of protrusions on the bases;
depositing a diffusion barrier layer in the openings before the applying of the sacrificial layer in the openings; and
removing portions of the diffusion barrier layer not covered by the first conductive feature and the base after the formation of the protrusions.