Patent ID: 11881243
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G  H

Claim 0:
1. A semiconductor device comprising:
a memory cell array including a multiplicity of memory cells coupled between a plurality of word lines and one or more bit lines; and
an operation circuit configured to perform a multiplication and accumulation (MAC) operation with one or more first multi-bit data provided from the one or more bit lines and one or more second multi-bit data,
wherein a plurality of memory cells is coupled to each of the one or more bit lines, and the plurality of memory cells store a plurality of bits included in a corresponding one of the one or more first multi-bit data, and
wherein the memory cell array sequentially provides the plurality of bits included in the corresponding first multi-bit data to the operation circuit,
wherein the operation circuit includes:
one or more unit operation circuits respectively corresponding to the one or more bit lines; and
an accumulation capacitor,
wherein each of the one or more unit operation circuits includes a unit capacitor selectively coupled to the accumulation capacitor for charge distribution.