Patent ID: 11894068
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 3:
4. The non-volatile memory device of claim 1, the control circuit comprising:
a sense amplifier circuit including a sense node configured to connect to a first selected memory cell, wherein, to perform the first hard bit read operation and to perform the first soft bit read operation on the first selected memory cell, the control circuit configured to:
bias the first selected memory cell at a first voltage level;
pre-charge the sense node to a first level;
discharge the sense node pre-charged to the first level through the first selected memory cell biased at the first voltage level for a first sensing interval;
determine the first hard bit value for the first selected memory cell based on an amount that the sense node discharges during the first sensing interval;
subsequent to discharging the sense node for the first sensing interval, continue discharging the sense node pre-charged to the first level through the first selected memory cell biased at the first voltage level for a first additional sensing interval; and
determine the first soft bit value for the first selected memory cell based on an amount that the sense node discharges during the combined first sensing interval and first additional sensing interval.