Patent ID: 11955095
Assignee: LAPIS TECHNOLOGY CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. The output circuit according to claim 4,
wherein the first current source is connected between the back gate of the first PMOS transistor switch and a positive power supply voltage terminal that receives a positive power supply voltage,
wherein the first back gate control switch is connected between the back gate of the first PMOS transistor switch and a reference power supply voltage terminal that receives the reference power supply voltage, and
wherein
the first PMOS transistor is configured such that a drain is connected to one of the source and the drain of the first PMOS transistor switch, a gate is connected to the other of the source and the drain of the first PMOS transistor switch, and a source is connected to the back gate of the first PMOS transistor switch, and
the second PMOS transistor is configured such that a drain is connected to the other of the source and the drain of the first PMOS transistor switch, a gate is connected to the one of the source and the drain of the first PMOS transistor switch, and a source is connected to the back gate of the first PMOS transistor switch.