Patent ID: 11950517
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 3:
4. The device of claim 3, further comprising:
a substrate;
a first capping pattern;
barrier metal patterns;
a sidewall spacer; and
a second gapfill insulating pattern, wherein
the first conductive line is one of a plurality of first conductive lines on the substrate and extending in the first direction,
the first direction is parallel to a top surface of the substrate,
the second conductive line is one of a plurality of second conductive lines on the substrate and extending in the second direction,
the cell stack is one of a plurality of cell stacks on the substrate,
the plurality of cell stacks are at respective intersections of the plurality of first conductive lines and the plurality of second conductive lines, and
each of plurality of cell stacks includes a same structure as the cell stack such that each of the plurality of cell stacks includes the first electrode, the second electrode, and the third electrode sequentially stacked, a switching pattern between the first electrode and the second electrode, the variable resistance pattern between the second electrode and the third electrode, and the switching pattern having the maximum width at the level between the top surface of the switching pattern and the bottom surface of the switching pattern,
the variable resistance pattern has a minimum width at a level between a top surface of the variable resistance pattern and a bottom surface of the variable resistance pattern;
the gapfill insulating pattern is a first gapfill insulating pattern filling a region between the plurality of cell stacks such that an uppermost surface of the first gapfill insulating pattern is located between the top surface of the third electrode and the bottom surface of the third electrode,
the first capping pattern is between side surfaces of the plurality of cell stacks and the first gapfill insulating pattern,
the variable resistance pattern in each of the plurality of cell stacks provides a plurality of variable resistance patterns,
the sidewall spacer is between the plurality of variable resistance patterns of the plurality of cell stacks and the first capping pattern
the barrier metal patterns are between the plurality of second conductive lines and the plurality of cell stacks,
the barrier metal patterns extending in the second direction,
the second gapfill insulating pattern is on the first gapfill insulating pattern, and
the second gapfill insulating pattern covers side surfaces of the plurality of second conductive lines and side surfaces of the barrier metal patterns.