Patent ID: 11950399
Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor device, comprising:
a first semiconductor structure comprising a device layer, a first interconnect layer, and a first bonding layer, wherein the device layer comprises a processor and a logic circuit, and the first bonding layer comprises a plurality of first bonding contacts wherein the plurality of first bonding contacts are arranged in a first bonding contact pattern; and
a second semiconductor structure comprising a plurality of static random-access memory (SRAM) arrays, each SRAM array having a plurality of SRAM cells, each SRAM array disposed so as to be laterally spaced apart from other SRAM arrays of the plurality of SRAM arrays, a second interconnect layer, and a second bonding layer comprising a plurality of second bonding contacts wherein the plurality of second bonding contacts are arranged in a second bonding contact pattern;
wherein each SRAM array, of the plurality of SRAM arrays, is disposed relative to the second bonding contact pattern such that no second bonding contact is disposed in perpendicular alignment with any SRAM array of the plurality of SRAM arrays,
wherein the first semiconductor structure and the second semiconductor structure are bonded together in a face-to-face orientation such that the plurality of first bonding contacts arranged in the first bonding contact pattern, and the plurality of second bonding contacts arranged in the second bonding contact pattern are in physical contact with each other respectively.