Patent ID: 11900996
Assignee: GLOBALFOUNDRIES U.S. INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. The memory structure of claim 11,
wherein the voltage boost circuit is configured so that, when a first wordline voltage on the wordline switches to a positive supply voltage level and the mode select signal indicates the read mode, the first voltage boost line, the second voltage boost line, and the third voltage boost line are charged creating coupling capacitances between the first wordline and both the first voltage boost line and the second voltage boost line to increase the first wordline voltage on the first wordline above the positive supply voltage level and creating coupling capacitances between the cell supply line and both the second voltage boost line and the third voltage boost line to increase a cell supply voltage on the cell supply line above the positive supply voltage level, and
wherein the voltage boost circuit is configured so that, when the first wordline voltage on the wordline switches to the positive supply voltage level and the mode select signal indicates the write mode, the first voltage boost line is charged creating a coupling capacitance between the first wordline and the first voltage boost line to increase the first wordline voltage on the first wordline above the positive supply voltage level without increasing the cell supply voltage on the cell supply line.