Patent ID: 11941289
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. A memory system, comprising:
a memory device including a plurality of memory groups, each memory group including a plurality of non-volatile memory cells; and
a controller configured to:
transmit a command to the memory device so that the memory device performs a data input/output operation within at least one memory group among the plurality of memory groups,
receive a response which is subject to the command and output from the memory device, the response including a result of an operation that changes data of the at least one memory group performed corresponding to the command, and a status data output from the memory device in response to the operation that changes data of the at least one memory group, the status data including a current operation information, regarding the at least one memory group for which data was changed during the operation that changes data of the at least one memory group,
compare the status data with a physical to logical (P2L) map data item associated with the data input/output operation to perform a first determination regarding whether the data input/output operation has succeeded or failed,
perform, based on the response, a second determination regarding whether the data input/output operation has succeeded or failed,
determine whether the data input/output operation has succeeded or failed based on both the first determination and the second determination, and
update a logical to physical (L2P) map data item based on the P2L map data item according to the first determination and the second determination regarding whether the data input/output operation has succeeded or failed.