Patent ID: 11864422
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 5:
6. The method according to claim 1, wherein after the step of forming the second grid on the first grid insulating layer, the method further comprises:
forming a second grid insulating layer covering the second grid and the first grid insulating layer;
forming an inter-layer-medium layer on the second grid insulating layer;
forming a first via hole, a second via hole, a third via hole and a fourth via hole that penetrate the inter-layer-medium layer, the second grid insulating layer and the first grid insulating layer;
forming a first source, a first drain, a second source and a second drain on the inter-layer-medium layer, wherein the first source is connected to the first active layer by the first via hole, the first drain is connected to the first active layer by the second via hole, the second source is connected to the second active layer by the third via hole, and the second drain is connected to the second active layer by the fourth via hole;
forming a planarization layer covering the first source, the first drain, the second source, the second drain and the inter-layer-medium layer;
forming an anode layer on the planarization layer, wherein the anode layer is connected to the first drain by a fifth via hole penetrating the planarization layer; and
forming a pixel defining layer on the planarization layer, wherein the pixel defining layer partially covers the anode layer, and the pixel defining layer has a pixel opening exposing the anode layer.