Patent ID: 11889769
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. An integrated chip, comprising:
a magnetic tunnel junction arranged between a bottom electrode and a top electrode and surrounded by a dielectric structure disposed over a substrate, wherein the top electrode has a width that decreases as a height of the top electrode increases;
a bottom electrode via coupling the bottom electrode to a lower interconnect; and
an upper interconnect structure coupled to the top electrode, wherein the upper interconnect structure has a vertically extending surface that is disposed laterally between first and second outermost sidewalls of the upper interconnect structure and along a sidewall of the top electrode, wherein the vertically extending surface and the first outermost sidewall are connected to a bottom surface of the upper interconnect structure that is vertically below a top of the top electrode.