Patent ID: 11922030
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 11:
12. A memory device manufacturing method comprising:
preparing a wafer including a first nonvolatile memory die that includes a first temperature sensor, a second nonvolatile memory die that includes a second temperature sensor, and a third nonvolatile memory die that includes a third temperature sensor;
setting an ambient temperature around the wafer to a first set value higher than 30° C.;
after setting the ambient temperature to the first set value, measuring a first temperature, using the first temperature sensor;
determining a first correction value, using a measurement value of the first temperature sensor, the first correction value being used for temperature measurement by the first temperature sensor;
writing the first correction value to the first nonvolatile memory die;
after setting the ambient temperature to the first set value, measuring a second temperature, using the second temperature sensor;
determining a second correction value, using a measurement value of the second temperature sensor, the second correction value being used for temperature measurement by the second temperature sensor;
writing the second correction value to the second nonvolatile memory die;
after setting the ambient temperature to the first set value, measuring a third temperature, using the third temperature sensor;
determining a third correction value, using a measurement value of the third temperature sensor, the third correction value being used for temperature measurement by the third temperature sensor;
writing the third correction value to the third nonvolatile memory die;
setting the ambient temperature to a second set value higher than the first set value;
after setting the ambient temperature to the second set value, measuring a fourth temperature, using the first temperature sensor;
after setting the ambient temperature to the second set value, measuring a fifth temperature, using the second temperature sensor;
after setting the ambient temperature to the second set value, measuring a sixth temperature, using the third temperature sensor;
determining whether or not the fourth, fifth, and sixth temperatures are each within a threshold range;
cutting out the first, second, and third nonvolatile memory dies from the wafer;
when the fourth, fifth, and sixth temperatures are each within the threshold range, packaging the cut out first, second, and third nonvolatile memory dies as a memory device such that the first, second, and third nonvolatile memory dies are stacked, wherein a first surface, a second surface located opposite to the first surface, and a plurality of terminals exposed on the first surface are included in the memory device, the first nonvolatile memory die is stacked above the third nonvolatile memory die, the second nonvolatile memory die is stacked above the first nonvolatile memory die, and the third nonvolatile memory die is located closer to the first surface than the first and second nonvolatile memory dies; and
after the first, second, and third nonvolatile memory dies are packaged, deciding not to read a temperature measured by the third temperature sensor, or not to compare the temperature with a threshold temperature, by learning temperature tendencies of the first, second, and third nonvolatile memory dies, wherein
in the memory device, temperatures measured by the first and second temperature sensors are read from the first and second nonvolatile memory dies, and when at least one of the temperatures read from the first and second nonvolatile memory dies is equal to or higher than the threshold temperature, a frequency of issue of commands to the first, second, and third nonvolatile memory dies or a speed of access to the first, second, and third nonvolatile memory dies is reduced.