Patent ID: 11928018
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. The apparatus of claim 15, wherein:
to indicate that the first error management procedure and the second error management procedure identified the set of data as error-free, the first logic is configured to output a first voltage and the second logic, the third logic, and the fourth logic are configured to output a second voltage,
to indicate that the first error management procedure detected a first error in the set of data and the second error management procedure identified the set of data as error-free, the second logic is configured to output the first voltage and the first logic, the third logic, and the fourth logic are configured to output the second voltage,
to indicate that the first error management procedure identified the set of data as error-free and the second error management procedure detected a second error in the set of data, the third logic is configured to output the first voltage and the first logic, the second logic, and the fourth logic are configured to output the second voltage, or
to indicate that the first error management procedure and the second error management procedure detected errors in the set of data, the fourth logic is configured to output the first voltage and the first logic, the second logic, and the third logic are configured to output the second voltage,
wherein an output of the first logic corresponds to a first bit of the plurality of bits, an output of the second logic corresponds to a second bit of the plurality of bits, an output of the third logic corresponds to a third bit of the plurality of bits, and an output of the fourth logic corresponds to a fourth bit of the plurality of bits.