Patent ID: 11894420
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A memory, comprising:
a substrate, comprising an array area and a peripheral area encircling the array area; and
a plurality of discrete active areas arranged in staggered rows and located in the array area; and, wherein
a first-positioned discrete active area, in each row of a first plurality of adjacent rows, contacts the substrate of the peripheral area at a first side of the array area;
a first-positioned discrete active area, in each row of a second plurality of adjacent rows, contacts the substrate of the peripheral area at a second side of the array area that intersects the first side of the array area; and
the discrete active areas are separated from each other by a shallow trench isolation structure;
wherein a last-positioned discrete active area, in each row of the first plurality of adjacent rows, contacts the substrate of the peripheral area; and
a last-positioned discrete active area, in each row of the second plurality of adjacent rows, contacts the substrate of the peripheral area.