Patent ID: 11962509
Assignee: DELL PRODUCTS L.P.
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A clock circuit for clocking a high-speed data communication interface having a number (N) of lanes, the clock circuit comprising:
a triangle wave generator that provides a number (P) of phase outputs, wherein P is greater than or equal to N;
a number (N) of clock generators, wherein each clock generator receives an associated one of the phase outputs and generates a clock signal having a frequency based upon the phase output; and
a number (N) of lane first-in/first-out buffers (FIFOs), wherein each FIFO receives data and an associated one of the clock signals, and provides the data at a clock frequency associated with the associated clock signal;
wherein N is equal to four (4), and the order provides a 0th clock signal to the FIFO associated with a 2nd lane, a 1st clock signal to the FIFO associated with a 0th lane, a 3rd clock signal to the FIFO associated with a 3rd lane, and a 4th clock signal to the FIFO associated with a 2nd lane.