Patent ID: 11894362
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 2:
3. A method of forming an integrated circuit with an electrostatic discharge protection device, the method comprising:
providing a p-doped semiconductor substrate with a buried n-doped layer;
forming a plurality of n-wells in the p-doped semiconductor substrate above the buried n-doped layer, wherein:
the plurality of n-wells extend to a depth of the buried n-doped layer;
the plurality of n-wells comprise one or more first n-wells, one or more second n-wells, one or more third n-wells, and one or more fourth n-wells;
a plurality of p-wells are provided by portions of the p-doped semiconductor substrate between neighboring members of the plurality of n-wells;
the plurality of p-wells comprise one or more first p-wells and one or more second p-wells;
the first p-wells abut the first n-wells; and
the second p-wells abut the third n-wells and the fourth n-wells;

doping to provide deep p-wells that isolate the fourth n-wells from the buried n-doped layer;
implanting p-type dopants to provide first collector contact regions directly above the first n-wells, first emitter contact regions directly above the first p-wells, and second base contact regions directly above the second p-wells;
implanting n-type dopants to provide first base contact regions directly above the second n-wells, second collector contact regions directly above the third n-wells, and second emitter contact regions directly above the fourth n-wells; and
forming a metal interconnect comprising:
a first metal structure that couples an anode terminal to the first collector contact regions, the first base contact regions, and the second collector contact regions;
a second metal structure that couples a cathode terminal to the second emitter contact regions; and
a third metal structure that couples the first emitter contact regions to the second base contact regions.