Patent ID: 11935580
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. The device of claim 9, wherein:
the first precharge blocks are coupled to the first sense amplifiers in the first columns with the first bitlines, and the second precharge blocks are coupled to the second sense amplifiers in the second columns with the second bitlines,
the first delay block is coupled to the first precharge blocks in the first columns, and the first delay block delays precharging of the first bitlines to a supply voltage with the first precharge burst in the multi-burst precharge event; and
the second delay block is coupled to the second precharge blocks in the second columns, and the second delay block delays precharging of the second bitlines to the supply voltage with the second precharge burst in the multi-burst precharge event.