Patent ID: 11923308
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor device package, comprising:
a substrate including first routing;
an interconnect structure die on or at least partially in the substrate, the interconnect structure die including second routing;
a first die electrically connected to the first routing; and
a second die electrically connected to the first routing and electrically connected to the first die through the second routing,
wherein the interconnect structure die includes:
a region comprising a plurality of bumps, and
first, second, and third metal layers, wherein the first metal layer is closer to the first and second dies than the second and third metal layers, the second metal layer is between the first and third metal layers and includes a ground plane outside a footprint of the region and includes traces within the footprint of the region, the first metal layer includes a ground plane within the footprint of the region and signal traces outside the footprint of the region, the third metal layer includes a ground plane within the footprint of the region and includes traces outside the footprint of the region and the first metal layer includes two signal traces for an individual ground trace in the first metal layer.