Patent ID: 11887841
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor package comprising:
a first semiconductor chip;
a second semiconductor chip;
first main connection pad structures arranged at an interface between the first semiconductor chip and the second semiconductor chip and arranged to be apart from each other by a first main pitch in a first direction parallel to a top surface of the first semiconductor chip, wherein each of the first main connection pad structures comprises a first connection pad electrically connected to the first semiconductor chip, and a second connection pad electrically connected to the second semiconductor chip and contacting the first connection pad;
first dummy connection pad structures arranged at the interface between the first semiconductor chip and the second semiconductor chip, arranged to be apart from the first main connection pad structures, and arranged to be apart from each other by a first dummy pitch in the first direction, the first dummy pitch being greater than the first main pitch;
second dummy connection pad structures arranged at the interface between the first semiconductor chip and the second semiconductor chip and arranged to be apart from each other by a second dummy pitch in the first direction; and
third dummy connection pad structures arranged at the interface between the first semiconductor chip and the second semiconductor chip and arranged to be apart from each other by a third dummy pitch in the first direction,
wherein the second dummy pitch is greater than the first dummy pitch, and the third dummy pitch is greater than the second dummy pitch.