Patent ID: 11880706
Assignee: NANJING QINHENG MICROELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. An interrupt control method based on RISC-V, comprising an interrupt control, wherein the interrupt control comprises the following steps of:
(a1) defining an attribute of an interrupt service function which determines that the interrupt service function does not contain an instruction for protecting/recovering a value of a general-purpose register, receiving and responding to, by a processor, a first interrupt request, and stopping executing an original program stream;
(a2) saving a context by hardware, wherein the saving, by the hardware, the context comprises: storing, by an interrupt controller, a content in a Caller-save type general-purpose register into a hardware memory area; and program jumping, by the processor, to a first interrupt entry simultaneously when the hardware saves the context;
(a3) handling, by the processor, a first interrupt event; and
(a4) once the first interrupt event is completed, the processor immediately returning to an original program breakpoint through an interrupt return instruction, and continuously executing the original program stream; and meanwhile, restoring, by the hardware, the context, wherein the restoring, by the hardware, the context comprises: loading back, by theme interrupt controller, the content from the hardware memory area into the Caller-save type general-purpose register; wherein
the hardware memory area comprises a first-type memory area and a second-type memory area, the first-type memory area is used for storing a content of a control and status register set, and the second-type memory area is used for storing the content in the Caller-save type general-purpose register; the first-type memory area comprises at least a level 2 sub-memory area, the level 2 sub-memory area of the first-type memory area is used for storing the content of the control and status register set before an interrupt preemption, the second-type memory area comprises at least a level 1 sub-memory area and a level 2 sub-memory area, the level 1 sub-memory area of the second-type memory area is used for storing the content of the Caller-save type general-purpose register before entering a first interrupt, and the level 2 sub-memory area of the second-type memory area is used for storing the content in the Caller-save type general-purpose register before entering the interrupt preemption.