Patent ID: 11888490
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 15:
16. A delay estimation method, adapted for a delay estimation device comprising a pulse generator, a mode selecting circuit, a digitally controlled delay line (DCDL), a time-to-digital converter (TDC), and a control circuit, wherein the method comprises:
selectively outputting, by the mode selecting circuit, a reference clock signal or a first clock signal to the DCDL in response to a first mode selection signal;
receiving, by the pulse generator, the reference clock signal and outputting the first clock signal and a second clock signal in response to the reference clock signal;
receiving the first clock signal from the pulse generator and generating a plurality of first phase signals based on the first clock signal by the DCDL;
generating, by the TDC, a first timing code based on the first phase signal and a second clock signal; and
estimating, by the control circuit, a specific delay between the first clock signal and the second clock signal based on the first timing code.