Patent ID: 11935585
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus comprising:
a plurality of non-volatile memory cells arranged in a plane of a memory die, the plane comprising:
a first word line comprising a first word line portion coupled to a corresponding first group of the non-volatile memory cells;
a second word line comprising a second word line portion coupled to a corresponding second group of the non-volatile memory cells, the second word line different from the first word line; and

a control circuit configured to apply a first voltage to the first word line portion and apply a second voltage to the second word line portion to concurrently read the first group of the non-volatile memory cells and the second group of the non-volatile memory cells,
wherein the first group of the non-volatile memory cells and the second group of the non-volatile memory cells each store less than a page of data.