Patent ID: 11907572
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. A memory sub-system, comprising:
a memory device;
a processing device coupled to the memory device and configured to control cache memory for the memory device to store data prior to storing the data on the memory device;
an interface of the memory sub-system comprising error correction circuitry and a comparator, wherein the interface is coupled to the processing device and configured to:
receive a write command addressed to a first address and a first read command and a second read command addressed to a second address from a host;
receive data corresponding to the write command from the host;
store the write command, the first read command, and the second read command in a command buffer of the interface;
store the data in a write buffer of the interface;
determine, using the comparator of the interface, whether the write command was inserted into the command buffer prior to insertion of the first read command and the second read command into the command buffer by comparing a write identifier (ID) of the write command, a first read ID of the first read command, and a second read ID of the second read command, wherein the write ID, the first read ID, and the second read ID are assigned sequentially based on an order in which commands are received from the host;
responsive to determining that the first address matches the second address and that the write command was inserted into the command buffer prior to inserting the read command into the command buffer using the comparator of the interface while the write command, the first read command, and the second read command are stored in the command buffer and that the data is not corrupt:
drop the first read command, the second read command, and the second address from the command buffer by sending a signal from the comparator to the error correction circuitry to cause the error correction circuitry to mark the first read command and the second read command as being erroneous without regard to performing an error check on the read command and without regard to whether the read command passes an error check if performed, wherein a memory sub-system controller is configured to delete the first read command and the second read command responsive to the first read command and the second read command being marked by the error correction circuitry;
forward the data from the write buffer directly to a read buffer of the interface via lines that couple the write buffer to the read buffer; and
provide the data to the host from the read buffer; and

responsive to determining that the first address does not match the second address or that the data is corrupt while the write command, the first read command, and the second read command are stored in the command buffer, provide the first read command, the second read command, and the second address to the processing device for processing.