Patent ID: 11861180
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A memory system comprising:
a plurality of non-volatile memory chips; and
a controller configured to communicate with a host and control the plurality of non-volatile memory chips, wherein the controller is configured to:
write a data frame that includes write data and first parity for error detection and correction of the write data into first memory chips of the non-volatile memory chips in a distributed manner, the first memory chips including N (N is a natural number of two or more) memory chips;
write second parity used in restoring data stored in one of the N first memory chips, together with data read from the other N-1 of the N first memory chips, into a second memory chip of the non-volatile memory chips that is different from any of the first memory chips;
generate a first data frame from data read from the first N memory chips;
generate a second data frame through restoration of data stored in a first one of the first N memory chips with data read from N-1 of the first N memory chips other than the first one and the second parity read from the second non-volatile memory chip;
generate a third data frame through restoration of data stored in a second one of the first N memory chips with data read from N-1 of the first N memory chips other than the second one and the second parity read from the second non-volatile memory chip; and
perform at least a part of decoding of the second data frame using the first parity included therein, in parallel with decoding of the third data frame using the first parity included therein.