Patent ID: 11948929
Assignee: KIOXIA CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor device comprising:
a first chip including:
a first substrate; and
a logic circuit provided on the first substrate;

a second chip provided above the first chip, bonded to the first chip, and including:
a first bit line provided above the logic circuit and extending in a first direction parallel to a surface of the first substrate,
a second bit line arranged in a second direction of the first bit line and extending in the first direction, the second direction crossing the first direction and being parallel to the surface of the first substrate,
a plurality of electrode layers provided above the first bit line and the second bit line and stacked in a third direction;
a metal layer functioning as a source line and provided above an uppermost layer of the plurality of electrode layers;
a first semiconductor layer extending in the third direction in the plurality of electrode layers and having a first end and a second end, the first end being electrically connected to the first bit line;
a second semiconductor layer extending in the third direction in the plurality of electrode layers and having a third end and a fourth end, the third end being electrically connected to the second bit line;
a third semiconductor layer connecting the metal layer and the second end of the first semiconductor layer; and
a fourth semiconductor layer connecting the metal layer and the fourth end of the second semiconductor layer; and

a bonding metal provided on a bonding surface of the first chip and the second chip, the first semiconductor layer and the logic circuit being electrically connected via the bonding metal; wherein
the third semiconductor layer includes an impurity and has an impurity concentration higher than an impurity concentration of the first semiconductor layer, and
the fourth semiconductor layer includes an impurity and has an impurity concentration higher than an impurity concentration of the second semiconductor layer.