Patent ID: 11916128
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 19:
20. The method of claim 19,
wherein the depositing of the first gate electrode includes depositing a n-type work function layer in the nFET region, the n-type work function layer including at least one of titanium (Ti), aluminum (Al), tantalum carbide (TaC), tantalum carbide nitride (TaCN), tantalum silicon nitride (TaSiN), titanium silicon nitride (TiSiN), or combinations thereof,
wherein the depositing of the second gate electrode includes depositing a p-type work function layer in the pFET region, the p-type work function layer including at least one of titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), tungsten (W), platinum (Pt), or combinations thereof,
wherein the depositing of the first and second gate electrodes further includes depositing a metal fill layer over the n-type and p-type work function layers, the metal fill layer including at least one of aluminum (Al), tungsten (W), copper (Cu), cobalt (Co), or combinations thereof.