Patent ID: 11929132
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A testing method for a semiconductor chip, comprising:
acquiring a target chip;
obtaining an abnormal chip after a test of read and write functions is performed on a preset number of memory cells in an edge region of the target chip, wherein obtaining the abnormal chip comprises determining that the target chip is the abnormal chip based upon the target chip comprising memory cells with abnormal read and write functions;
recording location information of the memory cells with abnormal read and write functions; and
judging whether an abnormality of read and write functions of the abnormal chip is a block abnormality based on the location information, comprising:
when the memory cells with abnormal read and write functions are more than two consecutive full rows or more than two consecutive full columns in the edge region of the memory cells on the abnormal chip, determining that the abnormality of read and write functions of the abnormal chip are the block abnormality.