Patent ID: 11947823
Assignee: SAP SE
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A computing system comprising:
a memory comprising a memory slice of a logical architecture, wherein the memory slice stores a plurality of documents; and
a processor configured to:
generate a document vector for the memory slice in the memory Which comprises a plurality of document pointers that point to a plurality of self-contained locations of the plurality of documents within the memory slice, respectively,
backup a copy of the memory slice and a copy of the document vector in a backup storage device in response to a checkpoint operation, and
restore, to the memory, the backup copy of the memory slice and the backup copy of the document vector with copies of the plurality of document pointers that were included in the document vector prior to the checkpointing, in response to a reload operation.