Patent ID: 11934334
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. A system, comprising:
a peripheral component interface express (PCIe) master device;
a first chip including a first coherent interconnect (CHI), the first CHI including:
at least one request node coupled to the PCIe master device by a PCIe protocol, and
a plurality of chip-to-chip interconnect (CCI) ports; and

a second chip including a second CHI, the second CHI including:
at least one home node, and
a plurality of CCI ports, each CCI port coupled to a respective CCI port of the first CHI by a coherent protocol that is not the PCIe protocol of the CHI,

where the request node is configured to receive at least one PCIe transaction from the PCIe master device, distribute PCIe data traffic in accordance with PCIe ordering rules by selection of a CCI port of the first CHI based on a stream identifier of the PCIe transaction, and send the PCIe transaction to the selected CCI port using the PCIe protocol, and
where the selected CCI port is configured to receive the PCIe transaction, and send the PCIe transaction to a respective CCI port of the second CHI using the coherent protocol.