Patent ID: 11868870
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. The neuromorphic apparatus of claim 6, wherein the single neuron circuit is configured to obtain each bit value of the multi-bit neuromorphic operation result using the single adder to perform an addition operation using, as inputs, at least one of a pre-set initial value, a synaptic operation value output from the single synaptic circuit at a previous time period of the different time periods, a synaptic operation value output from the single synaptic circuit at a current time period of the different time periods, an addition value processed by the single adder at a previous time period of the different time periods, and a carry value determined by the single adder at a previous time period of the different time periods.