Patent ID: 11966450
Assignee: KABUSHIKI KAISHA TOSHIBA
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 21:
22. A computer program product comprising a non-transitory computer-readable medium including programmed instructions for solving a combinatorial optimization problem by an information processing device, wherein the information processing device comprises a computing circuit and an output circuit, and the computing circuit comprises a first memory, a second memory, and an updating circuit, and the updating circuit comprising a first adder, a second adder, a first constraint circuit, a second constraint circuit, and a determination circuit, the instructions causing the information processing device to execute a calculation method comprising:
storing a plurality of elements using the first memory and the second memory, wherein elements of the plurality of elements stored in the first memory are associated with a first variable and elements of the plurality of elements stored in the second memory are associated with a second variable;
updating, by the updating circuit coupled to the first memory and the second memory, for each of the plurality of elements associated with the first variable and the second variable, the first variable and the second variable for each of unit times from an initial time to an end time, sequentially for the unit times and alternately between the first variable and the second variable; and
outputting, by the output circuit coupled to the computing circuit, a solution to the combinatorial optimization problem that is calculated based on the elements associated with the first variable at the end time, wherein
the plurality of elements correspond to a plurality of discrete variables representing the combinatorial optimization problem,
the first variable and the second variable are represented by a real number,
in an updating process for each of the unit times by the computing circuit, the calculation method includes, for each of the plurality of elements:
outputting, by the first memory, the first variable to the first adder to update the first variable based on the second variable;
outputting, by the second memory, the second variable to the second adder to update the second variable based on the first variable;
when the first variable is smaller than a predetermined first value, applying, by the determination circuit, a first enable signal to the first constraint circuit, and changing, by the first constraint circuit, the first variable to a value equal to or greater than the predetermined first value and equal to or smaller than a predetermined threshold value in response to the first enable signal; and
when the first variable is greater than a predetermined second value, applying, by the determination circuit, a second enable signal to the first constraint circuit, and changing, by the first constraint circuit, the first variable to a value equal to or greater than the threshold value and equal to or smaller than the predetermined second value in response to the second enable signal,

the predetermined second value is greater than the predetermined first value, and
the threshold value is greater than the predetermined first value and smaller than the predetermined second value.