Patent ID: 11955082
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. The display substrate of claim 16, wherein
a control electrode of the eighth transistor and a control electrode of the ninth transistor are of an integrally formed structure,
the first scanning signal line and the light emitting signal line connected to the pixel circuit are respectively located on two sides of the first plate of the capacitor of the pixel circuit, and the integrally formed structure of the control electrode of the eighth transistor and the control electrode of the ninth transistor is located between the first plate of the capacitor and the light emitting signal line connected to the pixel circuit; and/or
the first control electrode of the first transistor and the first sub-reset signal line are of an integrally formed structure, and the first control electrode of the second transistor and the first sub-scanning signal line are of an integrally formed structure,
a first initial signal line, a first sub-reset signal line and a first sub-scanning signal line connected to the pixel circuit extend in a first direction and are located on the same side of the second plate of the capacitor of the pixel circuit, the first sub-reset signal line is located on a side of the first initial signal line close to the second plate of the capacitor of the pixel circuit, and the first sub-scanning signal line is located on a side of the first sub-reset signal line close to the second plate of the capacitor of the pixel circuit the control signal line is located on a side of the second plate of the capacitor of the pixel circuit away from the first sub-scanning signal line,
the orthographic projection of the first scanning signal line on the base substrate is located between the orthographic projection of the first sub-reset signal line on the base substrate and the orthographic projection of the first sub-scanning signal line on the base substrate,
the orthographic projection of the integrally formed structure of a control electrode of the eighth transistor and a control electrode of the ninth transistor on the base substrate is located between the orthographic projection of the second plate of the capacitor on the base substrate and the orthographic projection of the control signal line on the base substrate,
the orthographic projection of the control signal line on the base substrate is located between the orthographic projection of the light emitting signal line on the base substrate and the orthographic projection of the integrally formed structure of the control electrode of the eighth transistor and the control electrode of the ninth transistor on the base substrate,
the second plate of the capacitor of the pixel circuit is electrically connected with the second plate of the capacitor of the first adjacent pixel circuit; and/or
an active layer of the first transistor and an active layer of the second transistor are respectively located on two sides of the active connection part,
the orthographic projection of the active layer of the first transistor on the base substrate overlaps the orthographic projection of the first initial signal line on the base substrate,
the orthographic projection of the active layer of the second transistor on the base substrate overlaps the orthographic projection of the first sub-scanning signal line on the base substrate,
the orthographic projection of the active connection part on the base substrate at least overlaps a part of the orthographic projection of the first scanning signal line on the base substrate; and/or
a second control electrode of the first transistor and the second sub-reset signal line are of an integrally formed structure, and a second control electrode of the second transistor and the second sub-scanning signal line are of an integrally formed structure,
the second sub-scanning signal line is located between the second sub-reset signal line and the third reset signal line, and the third initial signal line is located on a side of the third reset signal line away from the second sub-reset signal line,
the orthographic projection of the second sub-reset signal line on the base substrate at least overlaps a part of the orthographic projection of the first sub-reset signal line on the base substrate and is located between the orthographic projection of the first initial signal line on the base substrate and the orthographic projection of the first scanning signal line on the base substrate,
the orthographic projection of the second sub-scanning signal line on the base substrate at least overlaps a part of the orthographic projection of the first sub-scanning signal line on the base substrate and is located between the orthographic projection of the first scanning signal line on the base substrate and the orthographic projection of the second plate of the capacitor on the base substrate,
the orthographic projection of the third reset signal line on the base substrate is located between the orthographic projection of the second plate of the capacitor on the base substrate and the orthographic projection of the integrally formed structure of the control electrode of the eighth transistor and the control electrode of the ninth transistor on the base substrate,
the orthographic projection of the third initial signal line on the base substrate is located on a side of the orthographic projection of the control signal line on the base substrate away from the orthographic projection of the second plate of the capacitor on the base substrate, and overlaps a part of the orthographic projections of the light emitting signal line and the control signal line on the base substrate; and/or
the sixth insulating layer is opened with a plurality of via patterns, the plurality of via patterns comprise: a first via to a seventh via opened on the second insulating layer to the sixth insulating layer, an eighth via and ninth via opened on the third to sixth insulating layers, a tenth via to a twelfth via opened on the fourth to sixth insulating layers, a thirteenth via to a fifteenth via opened on the fifth and sixth insulating layers, and a sixteenth via and a seventeenth via opened on the sixth insulating layer,
the third via exposes the active layer of the fifth transistor, the tenth via exposes the first initial signal line, and the eleventh via exposes the second plate of the capacitor; a virtual straight line extending in the second direction passes through the third via and the eleventh via,
the third via of the pixel circuit and the third via of the first adjacent pixel circuit are a same via,
the eleventh via of the pixel circuit and the eleventh via of the first adjacent pixel circuit are a same via,
the tenth via of the pixel circuit and the tenth via of the second adjacent pixel circuit are a same via; and/or
the first electrode of the fifth transistor of the pixel circuit and the first electrode of the fifth transistor of the first adjacent pixel circuit are a same electrode,
the orthographic projection of the second initial signal line on the base substrate overlaps a part of the orthographic projections of the first reset signal line and the first scanning signal line on the base substrate,
the orthographic projection of the integrally formed structure of the second electrode of the first transistor and the second electrode of the second transistor on the base substrate at least overlaps a part of the orthographic projections of the active connection part, the second scanning signal line and the second plate of the capacitor on the base substrate,
the orthographic projection of the first electrode of the fifth transistor on the base substrate overlaps the orthographic projections of the second plate of the capacitor, the third reset signal line, the control signal line, the light emitting signal line and the third initial signal line on the base substrate,
the orthographic projection of the first connection electrode on the base substrate at least overlaps a part of the orthographic projections of the third reset signal line and the control electrode of the eighth transistor on the base substrate,
the orthographic projection of the first electrode of the eighth transistor on the base substrate overlaps a part of the orthographic projections of the control signal line, the light emitting signal line and the third initial signal line on the base substrate,
the orthographic projection of the first electrode of the ninth transistor on the base substrate overlaps a part of the orthographic projection of the control signal line on the base substrate; and/or
the data signal line and the first power supply line connected to the pixel circuit are located on a same side of the second connection electrode,
the first power supply line comprises: a power supply body part and a power supply connection part connected with each other, wherein, the power supply connection part is located on a side of the power supply body part away from the data signal line,
the power supply connection part of the first power supply line connected to the pixel circuit is connected with the power supply connection part of the first power supply line connected to the second adjacent pixel circuit,
the orthographic projection of the power supply connection part on the base substrate overlaps a part of the orthographic projections of the active connection part, the second scanning signal line, the first scanning signal line and the second initial signal line on the base substrate.