Patent ID: 11901009
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 9:
10. The address decoding circuit of claim 9, wherein there are eight bank groups, and the group address input signals comprise a first group address input signal, a second group address input signal, and a third group address input signal;
a fifth NAND gate corresponding to a first bank group includes a first input end connected to an inverted signal of the first group address input signal, a second input end connected to an inverted signal of the second group address input signal, and a third input end connected to an inverted signal of the third group address input signal;
a fifth NAND gate corresponding to a second bank group includes a first input end connected to the first group address input signal, a second input end connected to the inverted signal of the second group address input signal, and a third input end connected to the inverted signal of the third group address input signal;
a fifth NAND gate corresponding to a third bank group includes a first input end connected to the inverted signal of the first group address input signal, a second input end connected to the second group address input signal, and a third input end connected to the inverted signal of the third group address input signal;
a fifth NAND gate corresponding to a fourth bank group includes a first input end connected to the first group address input signal, a second input end connected to the second group address input signal, and a third input end connected to the inverted signal of the third group address input signal;
a fifth NAND gate corresponding to a fifth bank group includes a first input end connected to the inverted signal of the first group address input signal, a second input end connected to the inverted signal of the second group address input signal, and a third input end connected to the third group address input signal;
a fifth NAND gate corresponding to a sixth bank group includes a first input end connected to the first group address input signal, a second input end connected to the inverted signal of the second group address input signal, and a third input end connected to the third group address input signal;
a fifth NAND gate corresponding to a seventh bank group includes a first input end connected to the inverted signal of the first group address input signal, a second input end connected to the second group address input signal, and a third input end connected to the third group address input signal; and
a fifth NAND gate corresponding to an eighth bank group includes a first input end connected to the first group address input signal, a second input end connected to the second group address input signal, and a third input end connected to the third group address input signal.