Patent ID: 11862286
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 3:
4. The data transmission circuit of claim 3, wherein the data conversion circuit comprises:
a first transmission circuit, electrically connected to the data bus and the global data line and electrically connected to an output terminal of the state recognition circuit through a first inverter circuit, and configured to transmit the first data to the global data line in response to the comparison result indicating that the number of different bits does not exceed the preset threshold; and
a second transmission circuit, electrically connected to the global data line and the output terminal of the state recognition circuit and electrically connected to the data bus through a second inverter circuit, and configured to invert the first data and transmit the inverted first data to the global data line in response to the comparison result indicating that the number of different bits exceeds the preset threshold.