Patent ID: 11954574
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: nan (nan)
Classification: CPC nan | IPC G

Claim 0:
1. A processor, comprising:
a first tile,
a second tile,
a memory, and
a bus,
the bus being connected to:
the memory,
the first tile, and
the second tile,

the first tile comprising:
a first weight register,
a second weight register,
an activations buffer,
a first multiplier, and
a second multiplier,

the activations buffer being configured to include:
a first queue connected to the first multiplier, and
a second queue connected to the second multiplier,

the first queue comprising a first register and a second register adjacent to the first register, the first register being an output register of the first queue,
the first tile being configured:
in a first state:
to multiply, in the first multiplier, a first weight by an activation from the output register of the first queue, and

in a second state:
to multiply, in the first multiplier, the first weight by an activation from the second register of the first queue,

wherein, in the first state, a first adder is configured to be connected to an output of the first multiplier, and
wherein, in the second state, a second adder is configured to be connected to the output of the first multiplier.