Patent ID: 11936791
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A method of verifying reliability of instructions for a device, the method performed by a computing system comprising a processor and a memory, the method comprising:
identifying a reliability requirement associated with instructions for a device;
receiving, from a user via a user device, an assertion in relation to the reliability requirement;
generating a cryptographic assertion tracer (CAT) based at least in part on the received assertion;
transmitting the CAT to the user device;
receiving, from the user device, identification of assertion-related instructions from a first copy of the instructions for the device, in association with the CAT;
generating a first code verification encrypted reproducible record (ERR) based at least in part on the CAT and the identified assertion-related instructions from the first copy of instructions for the device;
sending the first code verification ERR to a third party;
reporting that the reliability requirement is addressed;
receiving a second copy of the instructions for the device;
receiving a request from the third party to determine whether the reliability requirement is addressed in the second copy of the instructions for the device, the request including the first code verification ERR;
generating a second code verification ERR based at least in part on the CAT and the identified assertion-related instructions from the second copy of the instructions for the device;
comparing the first and second code verification ERRs, and
when the first and second code verification ERRs do not match, based on the comparison, reporting that the reliability requirement is not addressed.