Patent ID: 11880682
Assignee: AMAZON TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A method implemented by a systolic circuit, the method comprising:
receiving a first input represented in floating-point with a first bit-length;
reducing a quantity of trailing bits of the first input based on a difference between the first bit-length and a bit-length supported by a processing element of the systolic circuit for multiply-accumulate operations;
generating a first reduced input represented in floating-point with a second bit-length based on reducing the quantity of trailing bits of the first input, wherein the second bit-length is less than the first bit-length, wherein the second bit-length corresponds to the bit-length supported by the processing element; and
receiving the first reduced input and a second input for performing, by the processing element, multiply-accumulate operations.