Patent ID: 11953981
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A memory controller to control a memory module that includes a first dynamic random access memory (DRAM) device having a first plurality of memory cells and a second DRAM device having a second plurality of memory cells, the memory controller comprising:
a control interface to:
transmit, to the memory module, a memory access command that specifies an access to the first plurality of memory cells and the second plurality of memory cells;
transmit, to the memory module, a first register access command that specifies a first register access; and,
transmit, to the memory module, a second register access command that specifies a second register access;

a data interface to:
transmit, to the memory module, data to be stored in the first plurality of memory cells and the second plurality of memory cells in response to the memory access command;
transmit, to the memory module, a first indicator to enable the first DRAM device to store a first device identification value in response to the first register access command; and
transmit, to the memory module, a second indicator to enable the second DRAM device to store a second device identification value in response to the second register access command, the first device identification value and the second device identification value to be unequal.