Patent ID: 11907154
Assignee: QUALCOMM INCORPORATED
Field: Digital communication (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 18:
19. A data communication apparatus, comprising:
means for generating a base clock signal with a base frequency;
means for gating the base clock signal, including a clock gating circuit responsive to one or more control inputs, the means for gating the base clock signal being configured to output a gated base clock signal while the clock gating circuit is enabled;
means for counting positive and negative edges in the gated base clock signal, including a first counter clocked by the gated base clock signal;
means for disabling the clock gating circuit, including control logic coupled to a first control input of the clock gating circuit, the means for disabling the clock gating circuit being configured to disable the clock gating circuit when an output of the first counter corresponds to a maximum count value; and
means for synchronizing the means for counting positive and negative edges in the signal received from a one-wire bus, configured to:
ignore edges in the signal received from the one-wire bus while the output of the first counter represents a value that is less than the maximum count value; and
reset the first counter in response to an edge detected in the signal received from the one-wire bus.