Patent ID: 11947810
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. A semiconductor memory device comprising:
a memory cell array comprising a plurality of volatile memory cells coupled to respective ones of a plurality of word-lines and respective ones of a plurality of bit-lines; and
a cyclic redundancy check (CRC) engine, during a memory operation on the memory cell array, configured to perform operations comprising:
detecting an error in a main data and a system parity data received from a memory controller through a link, wherein the memory controller is external to the semiconductor memory device; and
generating an error flag indicating whether the error that was detected corresponds to either a first type of error associated with the link or a second type of error associated with the volatile memory cells based on the system parity data; and
an on-die error correction code (ECC) engine configured to perform an ECC encoding operation on the main data and the system parity data and configured to perform an ECC decoding operation on the main data and the system parity data,
wherein the CRC engine comprises a CRC generator and a CRC checker, and
wherein, during the memory operation based on a command from the memory controller, the CRC generator is configured to generate a first reference system parity data based on the main data provided from the memory controller, and
wherein the CRC checker is configured to determine a logic level of the error flag associated with one of the first type of error or the second type of error based on comparison of the system parity data and the first reference system parity data.