Patent ID: 11917805
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A semiconductor memory device comprising:
a first word line extending in a vertical direction over a substrate;
a second word line arranged over the substrate to be spaced apart from the first word line in a first horizontal direction, the second word line extending in the vertical direction;
a plurality of first semiconductor patterns arranged on a sidewall of the first word line to be spaced apart from each other in the vertical direction, the plurality of first semiconductor patterns constituting respective portions of a plurality of first cell transistors;
a plurality of second semiconductor patterns arranged on a sidewall of the second word line to be spaced apart from each other in the vertical direction, the plurality of second semiconductor patterns constituting respective portions of a plurality of second cell transistors;
a plurality of conductive filling layers respectively contacting the plurality of first semiconductor patterns;
a plurality of cell capacitors respectively disposed between the plurality of first semiconductor patterns and the plurality of second semiconductor patterns, each of the plurality of cell capacitors comprising a first electrode contacting a corresponding one of the plurality of conductive filling layers, a second electrode contacting a corresponding one of the plurality of second semiconductor patterns, and a capacitor dielectric film between the first electrode and the second electrode;
a plurality of first bit lines electrically connected to the plurality of first semiconductor patterns respectively, the plurality of first bit lines spaced apart from each other in the vertical direction, the plurality of first bit lines extending in a second horizontal direction that is perpendicular to the first horizontal direction; and
a plurality of second bit lines electrically connected to the plurality of second semiconductor patterns respectively, the plurality of second bit lines spaced apart from each other in the vertical direction, the plurality of second bit lines extending in the second horizontal direction.