Patent ID: 11860786
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A system, comprising:
a processor;
a memory system; and
a cache system coupled between the processor and the memory system, comprising:
a first cache;
a second cache;
a configurable data bit;
a logic circuit coupled to the processor to control the first cache and the second cache based on the configurable data bit;
wherein when the configurable data bit is in a first state, the logic circuit is configured to:
implement commands received for accessing the memory system via the first cache, in response to the processor performing a speculative execution of instructions; and
implement commands received for accessing the memory system via the second cache, in response to the processor performing a non-speculative execution of instructions; and

wherein when the configurable data bit is in a second state, the logic circuit is configured to:
implement commands received for accessing the memory system via the second cache, in response to the processor performing the speculative execution of instructions; and
implement commands received for accessing the memory system via the first cache, in response to the processor performing the non-speculative execution of instructions.