Patent ID: 11960811
Assignee: SYNOPSYS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A system comprising:
a database storing, in a shared format, both a pre-layout circuit netlist partitioned into pre-layout sub-circuits, and a post-layout circuit netlist partitioned into post-layout sub-circuits that correspond to the pre-layout sub-circuits;
a memory storing instructions and a processor, coupled with the memory and to execute the instructions, the instructions when executed cause the processor to:
access both the pre-layout sub-circuits and the corresponding post-layout sub-circuits from the shared database; and
apply first circuit simulations to the pre-layout sub-circuits, the first circuit simulations producing driving information for some of the pre-layout subcircuits; and
apply second circuit simulations to the post-layout sub-circuits, wherein the driving information produced by the first circuit simulations of the pre-layout sub-circuits provide stimulus for inputs to the second circuit simulations of the post-layout sub-circuits.