Patent ID: 11869766
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 10:
11. A method, comprising:
forming a bottom electrode layer over a substrate;
depositing a first seed layer over the bottom electrode layer, the first seed layer having an amorphous crystal phase;
performing a first treatment onto the first seed layer, wherein after the first treatment the first seed layer has an orthorhombic crystal phase;
depositing a layer stack over the first seed layer, the layer stack including a plurality of first dielectric layers and a plurality of second dielectric layers alternatingly arranged with the first dielectric layers;
forming a capping layer over the layer stack;
transforming the layer stack into a ferroelectric layer; and
performing a patterning operation on the bottom electrode layer, the first seed layer and the layer stack.