Patent ID: 11863187
Assignee: SYNOPSYS, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to:
generate an inverted signal of a data input signal using the inverter, wherein the inverted signal of the data input signal and the data input signal are available for input during a rising edge of a clock cycle of a clock signal;
apply the data input signal as an input to a first circuit path during the rising edge of the clock cycle to generate an output signal; and
apply the inverted signal to a second circuit path identical to the first circuit path during the rising edge of the clock cycle to generate an inverted output signal,
wherein the output signal and the inverted output signal are available concurrently, wherein the output signal and the inverted output signal are coupled by a cross-coupled circuit comprising a transistor gated by the clock signal.