Patent ID: 11916032
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 35:
36. An electronic system, comprising:
an input device;
an output device;
a processor device operably coupled to the input device and the output device; and
a memory device operably coupled to the processor device and comprising:
a first die comprising:
a multiplexer region within a base structure;
global digit lines vertically above the multiplexer region, the global digit lines horizontally extending in a first direction;
vertical stacks of memory cells vertically overlying the multiplexer region; and
a stack structure horizontally extending in a second direction and comprising a vertically alternating sequence of conductive structures and insulative structures intersecting the vertical stacks of memory cells;

a second die comprising a complementary metal-oxide-semiconductor (CMOS) region comprising a sense amplifier; and
conductive contact structures in electrical communication with the global digit lines, the sense amplifier vertically above the conductive contact structures.