Patent ID: 11955965
Assignee: INTEL CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A system comprising:
a transmission gate comprising:
an input;
an output;
a first n-MOS transistor and a second n-MOS transistor, wherein a first source/drain region of the first n-MOS transistor is connected to the input, a second source/drain region of the first n-MOS transistor is connected to a first source/drain region of the second n-MOS transistor, and a second source/drain region of the second n-MOS transistor is connected to the output;
a first p-MOS transistor and a second p-MOS transistor, wherein a first source/drain region of the first p-MOS transistor is connected to the input, a second source/drain region of the first p-MOS transistor is connected to a first source/drain region of the second p-MOS transistor, and a second source/drain region of the second p-MOS transistor is connected to the output;
a mid-point transistor, wherein a source/drain region of the mid-point transistor is connected to the second source/drain region of the first n-MOS transistor and to the first source/drain region of the second n-MOS transistor; and
control circuitry to:
apply a voltage to the input such that a voltage difference between the input and the output is greater than a breakdown voltage of transistors of the transmission gate; and
control voltages applied to gates of the first n-MOS transistor, second n-MOS transistor, first p-MOS transistor, second p-MOS transistor, and mid-point transistor such that voltages across terminals of the first n-MOS transistor, second n-MOS transistor, first p-MOS transistor, second p-MOS transistor, and mid-point transistor do not exceed a breakdown voltage of the corresponding transistor,

wherein, when the transmission gate is off, the control circuitry is to apply a gate voltage to the first n-MOS transistor and the first p-MOS transistor based on a voltage at the input and apply a gate voltage to the second n-MOS transistor and the second p-MOS transistor based on a voltage at the output.