Patent ID: 11929110
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 16:
17. The memory circuit of claim 16, wherein the first clock pre-decoder circuit comprises:
a first set of AND logic gates configured to generate a first set of signals in response to the first set of local address signals and an inverted first set of local address signals;
a second set of AND logic gates configured to generate a second set of signals in response to the first set of local address signals and the inverted first set of local address signals;
a third set of AND logic gates configured to generate a first set of bank select signals in response to the first set of local address signals and the inverted first set of local address signals;
a fourth set of AND logic gates coupled to the first set of AND logic gates and the third set of AND logic gates, and configured to generate the first set of clock signals in response to the first set of signals and the first set of bank select signals; and
a fifth set of AND logic gates coupled to the second set of AND logic gates and the third set of AND logic gates, and configured to generate the second set of clock signals in response to the second set of signals and the first set of bank select signals.