Patent ID: 11971992
Assignee: LATTICE SEMICONDUCTOR CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 12:
13. A method for failure characterization of a secure programmable logic device (PLD), the method comprising:
receiving a failure characterization (FC) command from a PLD fabric or an external system coupled to a secure PLD through a configuration I/O of the secure PLD;
executing the FC command, wherein the executing the FC command comprises erasing and/or nullifying at least a portion of the NVM of the secure PLD to remove customer data associated with the configuration image;
loading a debug configuration into the PLD fabric while the portion of the NVM remains erased and/or nullified; and
performing a debug process, wherein the performing the debug process comprises booting the debug configuration by the PLD fabric that is configured to identify and/or characterize failures in the operation of any one or combination of elements of the secure PLD.