Patent ID: 11972034
Assignee: AMAZON TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 4:
5. A method, comprising:
utilizing a plurality of security keys, comprising a first security key and a second security key, to perform respective memory accesses for respective ones of a plurality of security groups comprising a first security group and a second security group, the utilizing of the plurality of security keys comprising:
identifying a first set of candidate cache locations mapping to a memory address according to the first security key of the first security group, the memory address accessed by a first thread of execution of a processor as a member of the first security group and the first security key identified according to an identifier of the first security group, wherein the identifying comprises scrambling a portion of the memory address according to the selected first security key using a first scrambling function to generate a first index; and
identifying a second set of candidate cache locations mapping to another memory address according to the second security key of the second security group, the other memory address accessed by a second thread of execution of a processor as a member of the second security group and the second security key identified according to an identifier of the second security group, wherein the identifying comprises scrambling a portion of the other memory address according to the second security key using the first scrambling function to generate a second index, wherein the second security group differs from the first security group, wherein the second security key differs from the first security key, wherein the second thread of execution differs from the first thread of execution, and wherein the second set of candidate cache locations differs from the first set of candidate cache locations according to a difference between the second security key and the first security key.