Patent ID: 11901413
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC B  H

Claim 8:
9. An integrated chip, comprising:
a semiconductor-on-insulator (SOI) substrate comprising a first semiconductor layer, a second semiconductor layer, and an insulating layer disposed between the first and second semiconductor layers;
an N-type metal oxide semiconductor (NMOS) transistor disposed over the first semiconductor layer, wherein the NMOS transistor comprises a gate electrode, a gate dielectric layer disposed between the gate electrode and the first semiconductor layer, and a pair of source/drain structures disposed on opposing sides of the gate electrode, wherein the pair of source/drain structures comprise:
a first pair of epitaxial source/drain layers over the first semiconductor layer, wherein the first pair of source/drain epitaxial layers comprise a first N-type dopant; and
diffusion barrier layers disposed between the first semiconductor layer and the first pair of source/drain epitaxial layers, wherein the diffusion barrier layers comprise a barrier dopant that is different from the first N-type dopant, wherein the diffusion barrier layers extend continuously from a top surface of the first semiconductor layer to a top surface of the insulating layer.