Patent ID: 11955981
Assignee: MICRON TECHNOLOGY, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 10:
11. A memory device, comprising:
a clock input configured to receive a clock from a host device;
a command input configured to receive command and address bits from the host device;
a first die comprising a first plurality of memory cells and first local control circuitry, wherein the first local control circuitry is configured to:
receive the clock from the clock input;
receive the command and address bits from the command input;
transmit the command and address bits to a second die, wherein the first die and second die are arranged in a three-dimensional stack;
generate, in division circuitry of the first die, a divided clock from the clock in division circuitry;
generate, in the division circuitry, multiple clocks from the divided clock, wherein the multiple clocks have lower frequencies than the divided clock; and
transmit the multiple clocks to the second die;

a plurality of inter-die interconnects; and
the second die comprising:
a second plurality of memory cells; and
second local control circuitry, wherein the second local control circuitry comprises:
one or more receivers configured to receive the multiple clocks and the command and address bits from the first die via a first portion of the plurality of inter-die interconnects;
clock reconstruction circuitry configured to reconstruct, in the second die, the divided clock from the multiple clocks; and
a decoder configured to utilize the reconstructed divided clock to decode the command and address bits.