Patent ID: 11973050
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A method for forming an integrated chip, the method comprising:
depositing an upper dielectric structure over a conductive wire;
depositing a conductive masking layer over the upper dielectric structure;
depositing a dielectric masking layer on the conductive masking layer;
forming an opening in the dielectric masking layer, the conductive masking layer, and the upper dielectric structure;
forming a conductive layer lining the opening, wherein the conductive layer overlies the dielectric masking layer and is electrically coupled to the conductive wire, and wherein the conductive layer directly contacts inner sidewalls of the conductive masking layer and inner sidewalls of the dielectric masking layer; and
performing an etching process on the conductive masking layer, the dielectric masking layer, and the conductive layer to form an upper conductive structure over the conductive wire.