Patent ID: 11917818
Assignee: SK HYNIX INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 12:
13. The memory device according to claim 12,
wherein the memory cell array comprises a stack structure that is disposed on the source plate in the cell region and the slimming region, and vertical channels that pass through the stack structure in the cell region,
wherein the stack structure comprises:
a plurality of dielectric layers and a plurality of interlayer dielectric layers alternately stacked in a part of the slimming region; and
a plurality of electrode layers and the plurality of interlayer dielectric layers alternately stacked in the cell region and the other part of the slimming region,
wherein the vertical channels pass through the plurality of electrode layers and the plurality of interlayer dielectric layers stacked alternately in the cell region, and
wherein the electrode layers are coupled to the row control circuit through a plurality of vias that pass through the plurality of dielectric layers and the plurality of interlayer dielectric layers stacked alternately.