Patent ID: 11935898
Assignee: JAPAN DISPLAY INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 4:
5. A display device comprising:
a first gate electrode;
a first gate insulating layer on the first gate electrode;
a first oxide semiconductor layer on the first gate insulating layer;
source and drain electrodes connected to the first oxide semiconductor layer;
a second gate insulating layer on the first oxide semiconductor layer, the second gate insulating layer having a part of a third aperture;
a second oxide semiconductor layer on the second gate insulating layer;
a second gate electrode on the second oxide semiconductor layer, the second gate electrode being in contact with the second oxide semiconductor layer;
a first insulating layer on the second gate electrode, the first insulating layer having another part of the third aperture;
a third connecting electrode on the first insulating layer, the third connecting electrode being connected to one of the source and drain electrodes via the third aperture;
a second insulating layer on the third connecting electrode, the second insulating layer having a fourth aperture; and
a pixel electrode on the second insulating layer, the pixel electrode being connected to the third connecting electrode via the fourth aperture;
wherein
the first gate electrode and the one of the source and drain electrodes overlap each other in a planar view,
the one of the source and drain electrodes and the second gate electrode overlap each other in a planar view, and
the second gate electrode and the third connecting electrode overlap each other in a planar view.