Patent ID: 11908825
Assignee: SK HYNIX INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. A semiconductor package comprising a semiconductor die stack, the semiconductor die stack including:
a lower semiconductor die including first and second lower pads, and an upper semiconductor die including first and second upper pads stacked on the lower semiconductor die;
a first bent wire electrically connecting the first lower pad with the first upper pad in a first direction;
a second bent wire electrically connecting the second lower pad with the second upper pad in the first direction;
a first vertical wire disposed on any one of the first lower pad and the first upper pad; and
a second vertical wire disposed on any one of the second lower pad and the second upper pad,
wherein the first lower pad and the first upper pad are aligned in the first direction;
wherein the second lower pad and the second upper pad are aligned in the first direction;
wherein the first lower pad and the second lower pad are aligned in a second direction, the second direction being perpendicular to the first direction;
wherein the first upper pad and the second upper pad are aligned in the second direction; and
wherein the first vertical wire and the second vertical wire are arranged in a diagonal direction with respect to the first and second directions.