Patent ID: 11956376
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 12:
13. A memory device comprising:
a memory cell array including a plurality of memory cells at intersections between a plurality of word lines and a plurality of bit lines;
a first bit line sense amplifier connected to a first bit line among the plurality of bit lines, the first bit line sense amplifier configured to operate as a data sense amplifier including writing data to or reading data from the plurality of memory cells through the first bit line; and
second bit line sense amplifiers connected to second bit lines among the plurality of bit lines, the second bit line sense amplifiers configured to operate as physically unclonable function (PUF) bit line sense amplifiers including generating a PUF key as a random digital value, the random digital value being determined according to threshold voltage distributions of transistors included in the second bit line sense amplifiers, and the threshold voltage distributions being different from one another,
wherein the transistors included in the second bit line sense amplifier have a higher threshold voltage distribution than transistors included in the first bit line sense amplifier,
wherein the second bit line sense amplifiers are replaced with redundancy bit line sense amplifiers for data sense operation in a normal operation mode.