Patent ID: 11887554
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. The gate drive circuit according to claim 2, further comprising:
a second pull-down node, an energy storage sub-circuit, a second pull-down control sub-circuit, a third noise reduction sub-circuit, a second pull-down sub-circuit, a fourth noise reduction sub-circuit, and a sixth noise reduction sub-circuit;
the first noise reduction sub-circuit includes a first transistor, the input sub-circuit includes a second transistor, the first pull-down sub-circuit includes a third transistor, and the first pull-down control sub-circuit includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and a first control node;
the first output sub-circuit includes an eighth transistor, the energy storage sub-circuit includes a first capacitor, the second noise reduction sub-circuit includes a ninth transistor, and the reset sub-circuit includes a tenth transistor;
the second pull-down control sub-circuit includes an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor and a second control node, the third noise reduction sub-circuit includes a fifteenth transistor, the second pull-down sub-circuit includes a sixteenth transistor, and the fourth noise reduction sub-circuit includes a seventeenth transistor;
the second output sub-circuit includes an eighteenth transistor, the fifth noise reduction sub-circuit includes a nineteenth transistor, the sixth noise reduction sub-circuit includes a twentieth transistor, and the initialization sub-circuit includes a twenty-first transistor;
a control electrode of the first transistor is coupled to the first pull-down node, a first electrode of the first transistor is coupled to the first voltage signal terminal, and a second electrode of the first transistor is coupled to the pull-up node;
a control electrode of the second transistor is coupled to the signal input terminal, a first electrode of the second transistor is coupled to the signal input terminal, and a second electrode of the second transistor is coupled to the pull-up node;
a control electrode of the third transistor is coupled to the signal input terminal, a first electrode of the third transistor is coupled to the first voltage signal terminal, and a second electrode of the third transistor is coupled to the first pull-down node;
a control electrode of the fourth transistor is coupled to the second voltage signal terminal, a first electrode of the fourth transistor is coupled to the second voltage signal terminal, and a second electrode of the fourth transistor is coupled to the first control node;
a control electrode of the fifth transistor is coupled to the pull-up node, a first electrode of the fifth transistor is coupled to the first voltage signal terminal, and a second electrode of the fifth transistor is coupled to the first control node;
a control electrode of the sixth transistor is coupled to the first control node, a first electrode of the sixth transistor is coupled to the second voltage signal terminal, and a second electrode of the sixth transistor is coupled to the first pull-down node;
a control electrode of the seventh transistor is coupled to the pull-up node, a first electrode of the seventh transistor is coupled to the first voltage signal terminal, and a second electrode of the seventh transistor is coupled to the first pull-down node;
a control electrode of the eighth transistor is coupled to the pull-up node, a first electrode of the eighth transistor is coupled to the clock signal terminal, and a second electrode of the eighth transistor is coupled to the first signal output terminal;
a first terminal of the first capacitor is coupled to the pull-up node, and a second terminal of the first capacitor is coupled to the second electrode of the eighth transistor;
a control electrode of the ninth transistor is coupled to the first pull-down node, a first electrode of the ninth transistor is coupled to a third voltage signal terminal, and a second electrode of the ninth transistor is coupled to the first signal output terminal;
a control electrode of the tenth transistor is coupled to the reset signal terminal, a first electrode of the tenth transistor is coupled to the first voltage signal terminal, and a second electrode of the tenth transistor is coupled to the pull-up node;
a control electrode of the eleventh transistor is coupled to a fourth voltage signal terminal, a first electrode of the eleventh transistor is coupled to the fourth voltage signal terminal, and a second electrode of the eleventh transistor is coupled to the second control node;
a control electrode of the twelfth transistor is coupled to the pull-up node, a first electrode of the twelfth transistor is coupled to the first voltage signal terminal, and a second electrode of the twelfth transistor is coupled to the second control node;
a control electrode of the thirteenth transistor is coupled to the second control node, a first electrode of the thirteenth transistor is coupled to the fourth voltage signal terminal, and a second electrode of the thirteenth transistor is coupled to the second pull-down node;
a control electrode of the fourteenth transistor is coupled to the pull-up node, a first electrode of the fourteenth transistor is coupled to the first voltage signal terminal, and a second electrode of the fourteenth transistor is coupled to the second pull-down node;
a control electrode of the fifteenth transistor is coupled to the second pull-down node, a first electrode of the fifteenth transistor is coupled to the first voltage signal terminal, and a second electrode of the fifteenth transistor is coupled to the pull-up node;
a control electrode of the sixteenth transistor is coupled to the signal input terminal, a first electrode of the sixteenth transistor is coupled to the first voltage signal terminal, and a second electrode of the sixteenth transistor is coupled to the second pull-down node;
a control electrode of the seventeenth transistor is coupled to the second pull-down node, a first electrode of the seventeenth transistor is coupled to the third voltage signal terminal, and a second electrode of the seventeenth transistor is coupled to the first signal output terminal;
a control electrode of the eighteenth transistor is coupled to the pull-up node, a first electrode of the eighteenth transistor is coupled to the clock signal terminal, and a second electrode of the eighteenth transistor is coupled to the second signal output terminal;
a control electrode of the nineteenth transistor is coupled to the first pull-down node, a first electrode of the nineteenth transistor is coupled to the first voltage signal terminal, and a second electrode of the nineteenth transistor is coupled to the second signal output terminal;
a control electrode of the twentieth transistor is coupled to the second pull-down node, a first electrode of the twentieth transistor is coupled to the first voltage signal terminal, and a second electrode of the twentieth transistor is coupled to the second signal output terminal; and
a control electrode of the twenty-first transistor is coupled to an initialization signal terminal, a first electrode of the twenty-first transistor is coupled to the first voltage signal terminal, and a second electrode of the twenty-first transistor is coupled to the pull-up node.