Patent ID: 11967962
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 18:
19. An operating method of a frequency-locked loop (FLL) logic circuit, the operating method comprising:
receiving an external clock signal;
determining whether a glitch occurs in the external clock signal;
generating a reference frequency clock signal based on determining that the glitch does not occur in the external clock signal;
synchronizing a phase of the reference frequency clock signal with a phase of an oscillator clock signal;
performing clock counting;
determining whether an operating frequency of the oscillator clock signal is identical to a target frequency based on a result of the clock counting; and
adjusting a frequency selection value based on the result of the clock counting,
wherein the frequency selection value is used to calibrate the operating frequency of the oscillator clock signal.