Patent ID: 11929759
Assignee: AMS INTERNATIONAL AG
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 3:
4. The DAC according to claim 1, wherein each switching block further comprises
a first input for receiving the portion of the multi-bit word,
a second input for providing the weight factors,
a third input for providing a clock signal, the clock signal being provided for the weight accumulator to accumulate subsequent adjusted weight factors,
a detector configured to detect, if an integer represented by the portion of the multi-bit word is even or odd,
a divider configured to split the portion of the multi-bit word into two preliminary sub-portions, the preliminary sub-portions having a smaller absolute value than the portion of the multi-bit word,
a selector configured to select one of the preliminary sub-portions, the selection being based on the sign of the weight accumulator, and
an adder configured to add a remainder of the splitting conducted by the divider to the preliminary sub-portion selected by the selector,
a first output for forwarding the first sub-portion,
a second output for forwarding the second sub-portion.