Patent ID: 11948885
Assignee: APPLIED MATERIALS, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. An integrated tool for performing semiconductor processing, the integrated tool, comprising:
a set of process chambers of the integrated tool that are interconnected under vacuum and configured to form a dual metal interconnect structure, the dual metal interconnect structure including:
at least one 1X feature formed with a first barrier layer with a thickness of approximately 5 angstroms to approximately 12 angstroms and filled with a conductive material having low diffusivity, high electromigration resistance, low scattering, and low resistivity at critical dimensions (CD) of approximately 15 nm or less, where X is a minimum feature width; and
at least one 3X to 5X feature formed with the first barrier layer and partially filled with the conductive material used in forming the at least one 1X feature and filled with a copper-based material with low resistivity.