Patent ID: 11956953
Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 14:
15. A semiconductor device, comprising:
a first stacked layer;
an insulating layer disposed over the first stacked layer;
a second stacked layer disposed over the insulating layer;
a channel structure penetrating the second stacked layer, the insulating layer and the first stacked layer, wherein the channel structure comprises:
a first channel structure extending through the first stacked layer;
a second channel structure extending through the second stacked layer; and
a third channel structure disposed in the insulating layer and in contact with the first and second channel structures, wherein a diameter of the third channel structure is larger than a diameter of the first channel structure;

a first filling structure in contact with an inner surface of the first channel structure; and
a second filling structure in contact with the first filling structure and an inner surface of the second channel structure;
wherein a diameter of a portion of the channel structure located in the insulating layer is larger than a diameter of a portion of the channel structure located in the first stacked layer, wherein the first stacked layer comprises a conductive layer and a dielectric layer alternatingly stacked, and wherein the conductive layer comprises a metal material.