Patent ID: 11954490
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A non-transitory machine readable medium that stores code that when executed by a machine causes the machine to perform a method comprising:
storing, in each register of a plurality of registers, a plurality of matrix data elements; and
executing, by matrix processing circuitry, a matrix processing instruction to multiply a first source tile of a first matrix and a second source tile of a second matrix, the first source tile comprising rows and columns of a first subset of data elements of the first source matrix stored in a memory and the second source tile comprising rows and columns of a second subset of data elements of the second source matrix, the matrix processing circuitry comprising:
circuitry to transform the first source tile by merging adjacent pairs of rows of the first source tile to generate corresponding row-interleaved data element sequences, each row-interleaved data element sequence to be loaded in a corresponding register of the plurality of registers,
a set of multipliers to perform a parallel multiplication of each data element of the first subset of data elements stored in the corresponding registers of the plurality of registers with a corresponding data element of the second subset of data elements to generate a corresponding plurality of products, and
accumulator circuitry to add groups of the plurality of products to corresponding accumulated data elements of an accumulation matrix to generate corresponding result data elements of a result matrix.