Patent ID: 11923002
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus, comprising:
an array of memory cells;
an access component coupled with the array of memory cells and operable to:
apply a write voltage to a memory cell of the array in response to a write command for the memory cell, wherein the memory cell is operable to store a logic value based at least in part on a polarity of the write voltage; and
apply a read voltage to the memory cell in response to a read command for the memory cell; and
a sense component coupled with the array of memory cells and operable to;
identify a sensed logic value for the memory cell based at least in part on whether the read voltage exceeds a threshold voltage of the memory cell;
determine whether to invert the sensed logic value based at least in part on a polarity of the read voltage relative to a polarity of a default read voltage; and
generate an indication of the stored logic value based at least in part on determining whether to invert the sensed logic value.