Patent ID: 11967535
Assignee: KLA CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 16:
17. A method for measuring an overlay error, the method comprising:
depositing and patterning at least first and second thin-film layers on a semiconductor substrate to define a matrix of dies, which are separated by scribe lines and contain active areas circumscribed by the scribe lines;
forming a plurality of overlay targets in the first and second thin-film layers, each overlay target comprising respective first target features in the first thin-film layer and respective second target features in the second thin-film layer;
capturing first images of the plurality of overlay targets in a first angular orientation of the semiconductor substrate with respect to a normal to the semiconductor substrate;
processing the first images to find respective first displacements between the first and second target features;
capturing second images of the plurality of overlay targets in a second angular orientation of the semiconductor substrate that is rotated relative the first angular orientation with respect to the normal to the semiconductor substrate;
processing the second images to find respective second displacements between the first and second target features;
computing a model of overlay error between the first and second thin-film layers based on the first and second displacements; and
computing the overlay error at a given location on the semiconductor substrate using the model.