Patent ID: 11936390
Assignee: ZHEJIANG UNIVERSITY
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  Y | IPC H

Claim 2:
3. The low-power fractional-N phase-locked loop circuit according to claim 1, wherein when the phase detector is a variable slope sampling circuit, a timing logic of the phase detector is as follows:
when the rising edge of one of the feedback signal or the reference signal arrives, the charging signal controls the charging switch to be turned on, so that the variable current source charges the variable charging capacitor;
when the rising edge of the other feedback signal or reference signal arrives, the charging signal controls the charging switch to be turned off and stops the variable current source from charging the variable charging capacitor, while the sampling signal controls the holding switch to be turned on, and the holding capacitor samples and holds a voltage on the variable charging capacitor;
after the sampling and holding is completed, the sampling signal controls the holding switch to be turned off, a reset signal controls the reset switch to be turned on, and the variable charging capacitor is connected to the ground to reset the initial charging voltage to zero; the compensation signal of the digital logic processor is received to adjust a capacitance value of the variable charging capacitor or a current of the variable current source; the reset signal controls the reset switch to be turned off and waits for the charging switch to be turned on.