Patent ID: 11894853
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 1:
2. The differential signal skew calibration circuit of claim 1, wherein the first detection circuit comprises:
a first logical circuit, a first end of the first logical circuit being connected with a first end of the phase calibration circuit, a second end of the first logical circuit being connected with a second end of the phase calibration circuit, wherein the first logical circuit is configured to perform a first logical operation on a first signal and a second signal in the differential signals to generate a phase difference signal, wherein the first end of the phase calibration circuit and the second end of the phase calibration circuit form the output end of the phase calibration circuit;
a phase delay circuit, a first end of the phase delay circuit being connected with a third end of the first logical circuit, wherein the phase delay circuit is configured to perform phase delay processing on the phase difference signal to generate a phase delay signal;
a second logical circuit, a first end of the second logical circuit being connected with the first end of the phase calibration circuit, a second end of the second logical circuit being connected with a second end of the phase delay circuit, wherein the second logical circuit is configured to perform a second logical operation on the phase delay signal and the first signal to generate the first phase difference pulse signal; and
a third logical circuit, a first end of the third logical circuit being connected with the second end of the phase calibration circuit, a second end of the third logical circuit being connected with the second end of the phase delay circuit, wherein the third logical circuit is configured to perform a third logical operation on the phase delay signal and the second signal to generate the second phase difference pulse signal.