Patent ID: 11862594
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A package structure, comprising:
a semiconductor die having a front surface and a rear surface opposite to the front surface, the semiconductor die comprising a plurality of vias on the front surface and a protection layer laterally covering the plurality of vias and standing on the front surface;
an insulating encapsulation, laterally encapsulating the semiconductor die, wherein the plurality of vias are separated from the insulating encapsulation by the protection layer;
a first redistribution circuit structure, located on the front surface of the semiconductor die;
a solder resist layer, located over the rear surface of the semiconductor die, wherein the solder resist layer is photosensitive;
first conductive elements, disposed on an outermost surface of the solder resist layer and electrically coupled to the semiconductor die;
second conductive elements, disposed on and electrically coupled to the first redistribution circuit structure; and
at least one semiconductor device, disposed on and electrically couple to the first redistribution circuit structure, wherein the second conductive elements and the at least one semiconductor device are disposed on a side of the first redistribution circuit structure.