Patent ID: 11949623
Assignee: QUALCOMM INCORPORATED
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. An apparatus for wireless communication at a user equipment (UE), comprising:
memory; and
at least one processor coupled to the memory and configured to, based at least in part on information stored in the memory:
receive a physical sidelink control channel (PSCCH); and
perform an initial synchronization based on the PSCCH, wherein to perform the initial synchronization, the memory and the at least one processor are configured to:

obtain a timing synchronization based on a demodulation reference signal (DMRS) in the PSCCH, wherein the timing synchronization is with a symbol boundary and a subframe boundary based on a known PSCCH DMRS sequence and based on a set of frequency hypotheses.