Patent ID: 11955165
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 12:
13. A memory package comprising:
a first sub-package including:
a first memory component having redundant and interconnected first and second memory-component data interfaces with respective first and second memory-component data ports; and
a first memory-component substrate having a first signal trace extending through the first memory-component substrate, a second signal trace extending through the first memory-component substrate to the first memory-component data port of the first memory component, the second signal trace forming a first point-to-point connection to the first memory-component data port of the first memory component, and a third signal trace extending through the first memory-component substrate to the second memory-component data port of the first memory component; and

a second sub-package including:
a second memory component having redundant and interconnected third and fourth memory-component data interfaces with respective third and fourth memory-component data ports; and
a second memory-component substrate having a fourth signal trace extending between the first signal trace of the first memory-component substrate and the third memory-component data port of the second memory component, the first and fourth signal traces forming a second point-to-point connection to the first memory-component data port of the second memory component, and a fifth signal trace extending between the third signal trace of the first memory-component substrate and the fourth memory-component data port of the second memory component.