Patent ID: 11935584
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 18:
19. The memory device of claim 17, wherein:
the interconnection layer further comprises:
another drain interconnection, the other source interconnection positioned laterally between the drain interconnection and the other drain interconnection;
the first metal layer further comprises:
a drain element positioned above the source interconnection, the other source interconnection, the drain interconnection, and the other source interconnection, the drain element electrically coupled to the drain interconnection and the other drain interconnection through drain-interconnection inter-layer contacts; and
the driver further comprises a second metal layer above the first metal layer, the second metal layer comprising:
a first metal line electrically coupled to the source element through a source-element inter-layer contact, the first metal line configured to electrically couple the source element to a voltage line; and
a second metal line electrically coupled to the drain element through a drain-element inter-layer contact, the second metal line configured to electrically couple the drain element to a source of a sense-amplifier transistor.