Patent ID: 11875040
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. The semiconductor system of claim 12, wherein the bank control circuit comprises:
a comparison circuit configured to generate a comparison signal that is input when a row address among the selection addresses is identically input;
a command generation circuit configured to generate the command by delaying the request signal based on the flag signal, a command input signal, a command end signal, and the comparison signal;
a standby signal generation circuit configured to generate an enabled standby signal when the command input signal is repeatedly input when the comparison signal is enabled and configured to generate a disabled standby signal when the command end signal is input;
a command end signal generation circuit configured to generate the command end signal that is enabled when a pre-command is input and that is disabled when the command is output; and
an address generation circuit configured to generate the address based on the selection address.