Patent ID: 11868813
Assignee: HT RESEARCH INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 21:
22. The computer system of claim 21, wherein the third base fail-over block comprises:
a tie fail-over pylon coupled to the tie execution pylon through the third workgroup fail-over link;
a matrix fail-over pylon coupled to the matrix execution pylon through the third workgroup fail-over link; and
an array fail-over pylon coupled to the array execution pylon through the third workgroup fail-over link,
wherein the matrix fail-over pylon comprises:
a first top control fail-over block coupled to the first top control block through the third workgroup fail-over link;
a first mid-memory fail-over block coupled to the first mid-memory block through the third workgroup fail-over link; and
a first base fail-over block coupled to the first base attribute block through the third workgroup fail-over link,

wherein the tie fail-over pylon comprises:
a second top control fail-over block coupled to the second top control block through the third workgroup fail-over link;
a second mid-memory fail-over block coupled to the second mid-memory block through the third workgroup fail-over link; and
a second base fail-over block coupled to the second base attribute block through the third workgroup fail-over link.