Patent ID: 11900108
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A method comprising:
storing a plurality of flags in a register, the plurality of flags including a carry flag, a sign flag, a zero flag, and an overflow flag;
decoding instructions, including a single rotate right instruction, wherein some of the instructions indicate 64-bit general-purpose registers that store 64-bit operands in a 64-bit mode and store 32-bit operands in a 32-bit mode, wherein the 32-bit operands are stored in a lower 32-bits of the 64-bit general-purpose registers, and wherein the single rotate right instruction indicates a 64-bit operand size, a first 64-bit source operand, a second 64-bit source operand, and has a field specifying a first 64-bit general-purpose register; and
performing operations corresponding to the single rotate right instruction, including:
rotating the first 64-bit source operand right by an amount indicated by the second 64-bit source operand, wherein bits rotated out of a least significant bit of the first 64-bit source operand are rotated into a most significant bit of the first 64-bit source operand;
storing a result including the first 64-bit source operand rotated right by the amount into the first 64-bit general-purpose register; and
completing the execution of the decoded single rotate right instruction without reading the carry flag, without writing the carry flag, without reading the sign flag, without writing the sign flag, without reading the zero flag, without writing the zero flag, without reading the overflow flag, and without writing the overflow flag.