Patent ID: 11907141
Assignee: QUALCOMM INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A method implemented in a memory system, comprising:
receiving, at a memory controller, a first memory access command and a first address at which to implement the first memory access command in a logical rank;
generating, by the memory controller, a first signal configured to indicate to a first memory device of the logical rank to implement the first memory access command via a first partial channel;
sending, from the memory controller, the first signal to the first memory device;
generating, by the memory controller, a second signal configured to indicate to a second memory device of the logical rank that is different from the first memory device to implement the first memory access command via a second partial channel; and
sending, from the memory controller, the second signal to the second memory device; and
determining whether the first address at which to implement the first memory access command in the logical rank is at the logical rank,
wherein generating the first signal, sending the first signal, generating the second signal, and sending the second signal occur in response to determining that the first address at which to implement the first memory access command in the logical rank is at the logical rank.