Patent ID: 11888064
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method comprising:
depositing a contact etch stop layer (CESL) over a source/drain region;
depositing an inter-layer dielectric (ILD) layer over the CESL;
etching an opening in the ILD layer;
extending the opening through the CESL with a first etching process, the first etching process being anisotropic;
widening a lower portion of the opening by etching the CESL with a second etching process to form an undercut between the ILD layer and the source/drain region, the second etching process being isotropic;
forming a silicide in the opening and the undercut, the silicide contacting the source/drain region; and
forming a source/drain contact in the opening and the undercut, the source/drain contact contacting the silicide.