Patent ID: 11942380
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 6:
7. A method, comprising:
forming first and second dummy patterns over a test region of a substrate;
forming an interlayer dielectric (ILD) layer laterally surrounding the first and second dummy patterns;
removing the first and second dummy patterns to form first and second openings in the ILD layer;
forming a dielectric layer over the substrate, wherein the dielectric layer has a first portion in the first opening of the ILD layer and a second portion in the second opening of the ILD layer;
forming a cap layer in the first opening and over the first portion of the dielectric layer, while the cap layer is not formed in the second opening;
performing an annealing process to the dielectric layer; and
in-line testing properties of the first and second portions of the dielectric layer after performing the annealing process.