Patent ID: 11934654
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. An integrated circuit (IC) dynamic random access memory (DRAM) device, comprising:
mode register circuitry to store a refresh mode control value;
on-die refresh control circuitry selectively enabled based on the mode control value;
a first bank of storage cells responsive to a first memory access request from a host memory controller to perform a first memory access operation during a memory access interval;
a second bank of storage cells responsive to hidden refresh commands generated on-die by the refresh control circuitry to undergo a hidden refresh operation during a designated hidden refresh interval that at least partially overlaps the memory access interval; and
wherein the refresh control circuitry conditionally dispatches a corrective action control signal to the host memory controller indicating a retry request for the host memory controller due to a failed operation caused by a collision between a memory request command to a given bank of the multiple banks and a hidden refresh operation to the given bank.