Patent ID: 11863188
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 5:
6. The flip-flop circuit of claim 4, wherein the first slave latch circuit comprises:
a fourth P-type transistor having a gate terminal configured to receive the second control signal, a source terminal connected to a positive power node, and a drain terminal connected to a fourth node; and
a fourth N-type transistor having a gate terminal configured to receive the first control signal, a source terminal connected to a negative power node, and a drain terminal connected to a fifth node, and
the selection circuit is connected to the negative power node through the fifth node when the first control signal has the first logic level and is connected to the positive power node through the fifth node when the second control signal has the second logic level.