Patent ID: 11955180
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 0:
1. A memory, comprising:
an array of memory cells comprising a string of series-connected split-gate memory cells, wherein each split-gate memory cell of the string of series-connected split-gate memory cells comprises a first memory cell portion and a second memory cell portion on opposing sides of a semiconductor pillar; and
a controller for access of the array of memory cells, wherein the controller, during a read operation on a selected split-gate memory cell of the string of series-connected split-gate memory cells, is configured to cause the memory to:
selectively activate the first memory cell portion of the selected split-gate memory in response to a data state of the first memory cell portion of the selected split-gate memory cell and deactivate the second memory cell portion of the selected split-gate memory cell; and
while selectively activating the first memory cell portion of the selected split-gate memory cell and deactivating the second memory cell portion of the selected split-gate memory cell, activate the second memory cell portion of each remaining split-gate memory cell of the string of series-connected split-gate memory cells.