Patent ID: 11881771
Assignee: NXP USA, INC.
Field: Electrical machinery, apparatus, energy (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 3:
4. The controller of claim 1, wherein the controller circuit is configured to generate a fall deadtime setting signal as the delay control signal in response to the status signal, and wherein the low-side delay circuit comprises:
a low-side ON delay circuit configured to receive the fall deadtime setting signal from the controller circuit, and generate a low-side ON signal as a response;
a low-side buffer circuit configured to receive a PWM signal, and generate a low-side OFF signal in response to the PWM signal; and
a low-side trigger circuit connected to the low-side ON delay circuit and the low-side buffer circuit, and configured to generate the low-side control signal based on the low-side ON signal and the low-side OFF signal.