Patent ID: 11907831
Assignee: UNIVERSITY OF DAYTON
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. The analog neuromorphic circuit of claim 11, further comprising:
a plurality of first weights associated with a first combination of resistive memories is adjusted to generate a negative value for the first combination of resistive memories, wherein the first plurality of first weights is applied to each corresponding conductance of the first combination of resistive memories thereby triggering a change in the functionality of the analog neuromorphic circuit when the plurality of first weights associated with the first combination of resistive memories is adjusted to generate the negative value for the first combination of resistive memories; and
a plurality of second weights associated with a second combination of resistive memories is adjusted to generate a positive value applied to each corresponding conductance of the second combination of resistive memories thereby triggering a change in the functionality of the analog neuromorphic circuit when the plurality of second weights associated with the second combination of resistive memories is adjusted to generate the positive value for the second combination of resistive memories.