Patent ID: 11942148
Assignee: THE REGENTS OF THE UNIVERSITY OF MICHIGAN
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A computing system, comprising:
an array of memory cells arranged in columns and rows, such that memory cells in each row of the array is interconnected by a respective drive line and each column of the array is interconnected by a respective bit line;
each memory cell in a given group of memory cells is configured to receive an input signal indicative of a multiplier and operates to output a product of the multiplier and the value of the bit stored in the given memory cell onto the corresponding bit line of a given memory cell, where the value of the multiplier is encoded in the input signal;
a plurality of drive circuits interfaced with the array of memory cells, each drive circuit is electrically connected to respective drive line in the array of memory cells; and
a plurality of column circuits interfaced with the array of memory cells, each column circuit is electrically connected to at least one bit line and includes only one transimpedance amplifier.