Patent ID: 11967395
Assignee: MEDIATEK INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 2:
3. The buffer as claimed in claim 1, wherein the first circuit comprises:
a first inductor coupled between the first signal input terminal and a first node;
a first switch coupled between the first node and a second node;
a second inductor coupled between the second node and the first signal output terminal;
a second switch coupled between the voltage source terminal and a third node; and
a first resistor coupled between the third node and the second node;
wherein the amplifier has a first input terminal coupled to the first node and a first output terminal coupled to the first signal output terminal,
wherein in response to the buffer operating at the first mode, the first switch is turned on, the second switch is turned off, and the amplifier is disabled, and
wherein at the first mode, the first inductor, the first switch, and the second inductor are in the first signal transmission path.