Patent ID: 11908685
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A method, comprising:
forming a semiconductor structure including a dummy gate structure disposed over a semiconductor fin, the dummy gate structure extending lengthwise along a first direction;
depositing a spacer layer over the dummy gate structure;
recessing the spacer layer to form a gate spacer on a sidewall of the dummy gate structure, wherein the gate spacer includes an upper portion and a lower portion disposed below the upper portion;
forming source/drain (S/D) features in the semiconductor fin and adjacent to the gate spacer;
subsequently performing a silicon-based implantation to the upper portion of the gate spacer to form a silicon-treated upper portion;
performing a carbon-based implantation to the silicon-treated upper portion to form a carbon-treated upper portion, wherein the carbon-treated upper portion includes more carbon atoms than the lower portion;
depositing an interlayer dielectric (ILD) layer over the S/D features and on the gate spacer, wherein the ILD layer includes silicon oxide;
forming a high-k metal gate structure (HKMG) in place of the dummy gate structure; and
forming a dielectric layer in the ILD layer and over the S/D features,
wherein the performing of the silicon-based implantation and the performing of the carbon-based implantation each include implementing a dosage source tilted from a plane defined by the first direction and a second direction perpendicular to a top surface of the semiconductor fin.