Patent ID: 11934317
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. An apparatus comprising:
a first hierarchical memory level comprising a memory array;
a second hierarchical memory level comprising a cache, a pre-fetch buffer, or both; and
a memory controller configured to be communicatively coupled to a memory bus, wherein the memory controller is configured to:
receive a memory access request targeting a memory page of the memory array via the memory bus;
determine whether a data block of the memory page is stored in the second hierarchical memory level;
enable a cache bypassing associated with the second hierarchical memory level when the memory page is deactivated and a statistical likelihood that a subsequent memory access request will target the memory page is higher than a first threshold in response to determining that the data block of the memory page is not stored in the second hierarchical memory level;
instruct the memory array to output the data block of the memory page directly to a processor-side via the memory bus in response to determining that the cache bypassing is enabled; and
instruct the memory array to store the data block of the memory page in the second hierarchical memory level in response to determining that cache bypassing is disabled.