Patent ID: 11916565
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. An analog-to-digital converter comprising:
a signal generator configured to generate a sample signal and a flag signal based on an external clock signal;
a sample/hold circuit configured to sample a first input voltage and a second input voltage in response to the sample signal;
a digital-to-analog converter configured to output a first comparison voltage and a second comparison voltage based on the sampled first input voltage and the sampled second input voltage;
a first comparison circuit to an Nth comparison circuits configured to output, sequentially from an Nth bit to first bit of a digital signal, first to Nth comparison result signals indicating a result of comparison between the first comparison voltage and the second comparison voltage, and first to Nth comparison completion signals indicating that a comparison operation is completed, N being a natural number greater than or equal to 2;
a control logic configured to output, to the first to Nth comparison circuits, first to Nth reference signals, first to Nth enable signals, and first to Nth selection signals based on the first to Nth comparison result signals; and
a digital register configured to output the digital signal based on the first to Nth comparison result signals,
wherein each of the first to Nth comparison circuits, associated with a corresponding reference signal, comprises:
a comparator configured to receive the first comparison voltage and the second comparison voltage, a first offset voltage and a second offset voltage, compare the first comparison voltage and the second comparison voltage to each other in response to a first clock signal, and output a comparison result signal;
a data latch configured to latch the comparison result signal, and output a comparison completion signal in response to an enable signal;
an offset calibration logic configured to control the first offset voltage and the second offset voltage based on the corresponding reference signal and the comparison result signal in response to the flag signal;
a selector configured to output a second comparison completion signal selected according to a selection signal from among the first to Nth comparison completion signals;
an operation gate configured to perform an AND operation on the enable signal and the selected comparison completion signal and output an operation result signal; and
a clock generator configured to generate a second clock signal in response to the operation result signal and be reset in response to the comparison completion signal.