Patent ID: 11937419
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. The forming method of claim 11, wherein the substrate has a unit region, the conductive contact plugs which are arranged at intervals being formed on the unit region, and a width of the second conductive contact plug at an edge of the unit region being greater than a width of the first conductive contact plugs at a non-edge of the unit region, wherein forming the capacitor array and the supporting structure comprises:
sequentially forming a sacrificial layer and an insulating dielectric layer on the substrate, etching the sacrificial layer and the insulating dielectric layer in the unit region by taking the conductive contact plugs as an etching stop layer, forming a plurality of columnar void structures which are arranged at intervals in the unit region, and controlling an etching window, so that a cross-sectional spacing of the columnar void structures at a periphery of the unit region along a direction parallel to the substrate is greater than a cross-sectional spacing of the columnar void structures at a non-periphery of the unit region;
depositing a lower electrode material serving as the conductive materials, and forming a lower electrode layer on sidewalls of the columnar void structures;
depositing the dielectric material, the dielectric material filling up the columnar void structures at the periphery of the unit region to form the supporting structure, and the columnar void structures at the non-periphery of the unit region being not filled;
removing the sacrificial layer in the unit region, and retaining the insulating dielectric layer; and
sequentially forming a capacitor dielectric layer and an upper electrode layer on the lower electrode layer of the columnar void structures at the non-periphery of the unit region, to form the capacitor array.