Patent ID: 11915784
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 3:
4. The memory chip according to claim 1, wherein the data has a readout path, the readout path comprises a process from reading out the data from the memory cell to outputting the data through the data port, and the data transmitted on the readout path is defined as intermediate data; and the memory chip comprises:
a delay module, wherein the delay module is provided on the readout path, an input terminal receives the intermediate data, a control terminal receives the reference voltage, an output terminal outputs the intermediate data based on the reference voltage, and a length of the delay of the delay module from receiving the intermediate data to outputting the intermediate data corresponds to the value of the reference voltage; and
an adjustment module, wherein an output terminal of the adjustment module is connected to the control terminal of the delay module, an input terminal receives a preset reference voltage, a control terminal receives a control signal, and the output terminal outputs, based on the control signal and the preset reference voltage, the reference voltage with the adjustable value.