Patent ID: 11909567
Assignee: HITACHI, LTD.
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An equalizer comprising:
a core circuit configured to receive a signal transmitted via a communication medium; and
a source follower connected to a subsequent stage of the core circuit, wherein
the core circuit includes a differential pair including a first transistor and a second transistor,
a first terminal of the first transistor and a first terminal of the second transistor are connected to an input terminal,
a first resistor is connected to second terminals of the first and second transistors,
a zero point generation circuit is connected between the second terminal of the first transistor and the second terminal of the second transistor, and
a second resistor is connected to third terminals of the first and second transistors, and
the source follower includes a third transistor that connects a first terminal to the third terminal of the first transistor and a fourth transistor that connects a first terminal to the third terminal of the second transistor,
a variable bias current source is connected to second terminals of the third and fourth transistors, and
a load in which a capacitive element and a resistor element are connected in series via a switching element is connected to wiring that connects the second terminals of the third and fourth transistors to an output terminal.