Patent ID: 11861216
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. The apparatus of claim 1, wherein the buffer comprises a first buffer associated with single-level operations and a second buffer associated with multi-level operations, the data for the set of commands being written to the first buffer, wherein the controller is further configured to cause the apparatus to:
write, to the second buffer, second data for a second set of commands that is associated with a second barrier command and, to the first buffer, third data for a third set of commands that is associated with a third barrier command;
perform the flushing operation for the first buffer, wherein the portion of the data and a portion of the third data are written to the memory device based at least in part on performing the flushing operation; and
obtain an index of the third barrier command based at least in part on the third data being flushed from the first buffer at an end of the flushing operation.