Patent ID: 11888662
Assignee: QUALCOMM INCORPORATED
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. An apparatus for wireless communication, comprising:
a transceiver;
a memory configured to store instructions; and
one or more processors communicatively coupled with the transceiver and the memory, wherein the one or more processors are configured to:
receive a slot format indicator indicating a first slot format for communications of a first cyclic prefix (CP) type, wherein the first slot format indicates, for each of a first set of multiple symbols, a communication direction;
receive, in one or more of the first set of multiple symbols indicated in the first slot format as a downlink symbol, a first communication according to a first timeline, wherein the first timeline is associated with the first CP type;
receive, in a second set of one or more symbols determined, based on a second slot format for communications of a second CP type, as a downlink symbol, a second communication according to a second timeline that is associated with the second CP type, wherein the second slot format is based on the first slot format and indicates, for each of the second set of one or more symbols, a communication direction, and wherein the second CP type is associated with having a less number of symbols than the first CP type;
decode the first communication according to a first length of the first CP type; and
decode the second communication according to a second length of the second CP type.