Patent ID: 11942936
Assignee: SYNOPSYS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 8:
9. A method of designing an electronic structure, the method comprising:
connecting a first inductor in series with a first shunted Josephson junction at a first terminal end of the first inductor;
connecting a second terminal end of the first inductor to a feed point of a first cell comprising the first inductor, the first shunted Josephson junction, and a first resistor;
connecting a first end of the first resistor to ground and a second end of the first resistor to the first shunted Josephson junction at a terminal of the first shunted Josephson junction that is not connected to the first inductor; and
powering the first cell using an electrical current source, wherein the electrical current source is external to the first cell, and wherein the electrical current source is connected to the first shunted Josephson junction and the first resistor at a common point.