Patent ID: 11900953
Assignee: REALTEK SEMICONDUCTOR CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 5:
6. An audio processing device, comprising:
a data processor configured to generate a calculated value according to a plurality of first audio clock frequency information comprised in a plurality of audio input packets, wherein the calculated value is an arithmetic mean value, a weighted mean value, a geometric mean value, a moving average value, a median value, or a mode value, and the data processor comprises a packet receiver configured to obtain the first audio clock frequency information from the audio input packets, an accumulator configured to add up the first audio clock frequency information to generate a data sum value, a counter configured to calculate the amount of the first audio clock frequency information to generate a data number, and a divider configured to divide the data sum value by the data number to generate the calculated value, wherein when a variation range of the first audio clock frequency information does not exceed a tolerance value and the data number is greater than a predetermined number, the divider divides the data sum value by the data number to generate the calculated value;
a clock generator configured to calculate an audio sampling frequency by the calculated value, a second audio clock frequency information comprised in the plurality of audio input packets and a link symbol clock signal; and
a buffer memory configured to generate a plurality of audio output packets corresponding to the audio input packets according to the audio sampling frequency.