Patent ID: 11916096
Assignee: VUEREAL INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. An integrated system connecting electrodes to micro-devices comprising:
a substrate;
a micro-device array having a plurality of micro-devices transferred on top of the substrate;
a planarization layer surrounding the plurality of micro-devices, the planarization layer including individual openings on top of and for each micro-device;
a backplane including an integrated circuit layer and a patterned electrode system, wherein the patterned electrode system includes formed individual top electrodes disposed in the individual openings to directly connect each micro-device to the integrated circuit layer; and
a first reflective layer on one side of the planarization layer; and
a second patterned reflective layer, including reflective portions and transparent portions, on another side of the planarizing layer,
wherein the second patterned reflective layer has a gradient depending on a position, a number or a distribution of light sources.