Patent ID: 11880706
Assignee: NANJING QINHENG MICROELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 4:
5. The interrupt control method based on RISC-V according to claim 4, wherein the step (n2) is implemented by setting a hardware memory area enhanced control bit HS_ENHANCE to 1;
a programmable-fast interrupt control register is added, and the programmable fast-interrupt register comprises the hardware memory area enhanced control bit;
when HS_ENHANCE is 1, when the n+1th interrupt occurs, the program jumps and stores the content in the control and status register set before handling the n+l th interrupt event into the level n+1 sub-memory area of the first-type memory area without accessing the second-type memory area, and then the content in the Caller-save type general-purpose register before handling the n+1th interrupt event is protected by software; after the interrupt handling is finished, the software restores the content of the Caller-save type general-purpose register, returns to continuously process the n th interrupt event and simultaneously loads back the content from the level n+1 sub-memory area of the first-type memory area into the control and status register set; and
when HS_ENHANCE is 0, the interrupt is masked, and the n+1th interrupt does not occur.