Patent ID: 11947889
Assignee: SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. The chip according to claim 8, wherein:
the chip is used for implementing SHA-256 algorithm;
the rows of the first type of each operation stage include a first row, a second row, and a third row, wherein:
the first row includes a first set of register modules and a first set of logical operation modules, the first set of register modules of the first row including 4 32-bit cache register modules A, B, C and D arranged in the form of an array of 1 row and 4 columns,
the second row includes a first set of register modules and a first set of logical operation modules, the first set of register modules of the second row including 4 32-bit cache register modules E, F, G and H arranged in the form of an array of 1 row and 4 columns, and
the third row includes a first set of register modules, a first set of logical operation modules and a fifth set of register modules, the first set of register modules of the third row including 4 32-bit extension register modules R0, R1, R9, and R14 arranged in the form of an array of 1 row and 4 columns, the fifth set of register modules of the third row including 1 32-bit extension register module R15;
the plurality of rows of each operation stage further include a fourth row including a fourth set of modules, the fourth set of modules of the fourth row including 11 32-bit extension register modules R2, R3, R4, R5, R6, R7, R8, R10, R11, R12, R13 arranged in the form of an array of 1 row and 11 columns; and
each 32-bit cache register module is used to store one 32-bit intermediate value, and each 32-bit extension register module is used to store one 32-bit extension data.