Patent ID: 11953962
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 3:
4. A system comprising:
a processor comprising:
a plurality of cores, wherein each of the plurality of cores comprises a multi-threaded core to concurrently execute a plurality of threads; and
a control circuit to concurrently enable, based at least in part on selective multi-threaded configuration information, a first core of the plurality of cores to operate in a single-threaded mode and a second core of the plurality of cores to operate in a multi-threaded mode, wherein the processor is of a first stock keeping unit having N cores and M threads, M less than 2N and N greater than one, based at least in part on the selective multi-threaded configuration information; and

a non-volatile memory coupled to the processor to store a basic input/output system (BIOS), the BIOS including:
a first region to store the selective multi-threaded configuration information to identify a first subset of the plurality of cores to be enabled for the single-threaded mode and a second subset of the plurality of cores to be enabled for the multi-threaded mode; and
first code to cause the selective multi-threaded configuration information to be communicated to the processor.