Patent ID: 11915968
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for manufacturing a semiconductor structure, comprising:
providing a base, at least one shallow trench isolating structure being formed in the base and several active regions arranged at an interval being isolated by the at least one shallow trench isolating structure in the base;
forming a first trench in the base, a part of the several active regions being exposed in the first trench;
forming a first conducting structure in the first trench, the first trench being filled with the first conducting structure;
forming a first dielectric layer on the base, the first dielectric layer covering an upper surface of the base and an upper surface of the first conducting structure;
forming a second trench in the first dielectric layer, the first conducting structure being exposed in the second trench and a width of a top of the second trench being greater than a width of a top of the first trench; and
forming a second conducting structure in the second trench, wherein:
the second trench is an inverted trapezoidal trench,
each of the first conducting structure and the second conducting structure at least comprises a polysilicon structure, and
a mask layer used to form the first trench comprises a first spin-coated hard mask layer and a first silicon oxide layer stacked in sequence from a second dielectric layer of the base, the first dielectric layer comprises a second spin-coated hard mask layer and a second silicon oxide layer stacked in sequence from the second dielectric layer.