Patent ID: 11966741
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 17:
18. An apparatus, comprising:
a processor core configured to execute a plurality of instructions;
an interconnection network interface to receive a work descriptor data packet, the interconnection network interface configured to decode the received work descriptor data packet into an initial program count and a received argument for a corresponding execution thread;
data path control circuitry configured to control an amount of data transferred in one or more data packets over an interconnection network;
a thread control memory coupled to the interconnection network interface and comprising a thread identifier pool register configured to store a plurality of thread identifiers, a program count register configured to store the initial program count, a data cache configured to store cached data, and a general-purpose register configured to store the received argument and non-cached data;
an execution queue coupled to the thread control memory, the execution queue configured to store one or more thread identifiers, of the plurality of thread identifiers, having a valid status;
an instruction cache coupled to the processor core to receive the initial program count and provide to the processor core a corresponding single instruction for execution, of the plurality of instructions;
a control logic and thread selection circuit coupled to the execution queue, to the instruction cache, and to the thread control memory, the control logic and thread selection circuit configured, directly in response to the received work descriptor data packet, to assign a thread identifier, of the plurality of thread identifiers, to the corresponding execution thread and to place the thread identifier in the execution queue, the control logic and thread selection circuit further configured to select the thread identifier of the one or more thread identifiers in the execution queue for execution by the processor core of a single instruction, of the plurality of instructions, corresponding to the received program count using the received argument stored in the general-purpose register for the corresponding execution thread, and the control logic and thread selection circuit further configured to periodically select the thread identifier of the one or more thread identifiers in the execution queue for single instruction execution, by the processor core, of the corresponding execution thread while the thread identifier is in the execution queue.