Patent ID: 11928056
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 6:
7. A method of operating a memory controller including a memory buffer and a cache memory, the method comprising:
storing command data corresponding to a request received from a host in the memory buffer; and
caching the command data in the cache memory,
wherein the caching comprises dividing the command data and allocating divided command data to cache lines, based on reference addresses of the memory buffer and a flag, the flag being included in the command data and including a start address and an end address of a storage region in the memory buffer in which the command data is stored, and
wherein the allocating of the divided command data to the cache lines comprises:
obtaining, in response to the start address that is an address other than the reference addresses, first divided command data corresponding to a first interval between the start address and a first reference address, which is a next address of the start address, among the reference addresses, the first divided command data being a first part of the command data; and
obtaining second divided command data corresponding to a second interval between the first reference address and a second reference address, which is a next address of the first reference address, among the reference addresses, the second divided command data being a second part of the command data.