Patent ID: 11908705
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 19:
20. A method for aligning interconnects comprising:
trimming and forming a frame of strips of interconnects, wherein the frame of strips of interconnects comprises interdigitated pins, wherein the strip of interconnects of the first set of strips of interconnects have a first distance between an edge of a respective strip of interconnects of the first strip of interconnects and a pin nearest to the edge of the respective strip of interconnects of the first strip of interconnects, and the strips of interconnects of the second set of strips of interconnects have a second distance between an edge of a respective strip of interconnects of the second set of strips of interconnects and a pin nearest to the edge of the respective strip of interconnects of the second set of strips of interconnects, the first distance being different than the second distance, wherein the pins of the first set of strips of interconnects in the array of strips of interconnects are interleaved with the pins of the second set of strips of interconnects in the array of strips of interconnects;
removing siderails from the frame of strips of interconnects to provide an array of strips of interconnects;
aligning a first set of strips of interconnects in the array of strips of interconnects such that pins of the first set of strips of interconnects are aligned with pins of a second set of strips of interconnects in the array of strips of interconnects, wherein a strip of interconnects of the first set of strips of interconnects are adjacent to a strip of interconnects of the second set of strips of interconnects to provide an aligned array of strips of interconnects; and
singulating the aligned array of strips of interconnects to provide interconnects for dies of integrated circuit (IC) chips.