Patent ID: 11876072
Assignee: NANYA TECHNOLOGY CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for preparing a semiconductor device, comprising:
providing an integrated circuit die having a bond pad;
forming a first dielectric layer over the bond pad;
forming a second dielectric layer over the first dielectric layer;
etching the first dielectric layer and the second dielectric layer to form a first opening exposing a top surface area of the bond pad;
partially recessing the top surface area of the bond pad to form a concave depression;
bonding a wire bond to the concave depression;
forming a first photoresist layer over the second dielectric layer, wherein the first opening is formed by using the first photoresist layer as a mask; and
forming a second photoresist layer over the first photoresist layer before the concave depression is formed.