Patent ID: 11928411
Assignee: QUALCOMM INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A method, comprising:
receiving a plurality of test cases for an integrated circuit, each respective test case of the plurality of test cases identifying a set of operating conditions and fabrication properties for the integrated circuit;
generating an embedding data set from the plurality of test cases, wherein a respective embedding for a respective test case of the plurality of test cases comprises a mapping of the respective test case into a multidimensional space;
generating, based on a clustering model and the embedding data set, a plurality of test case clusters;
selecting a plurality of critical test cases for testing the integrated circuit based on the plurality of test case clusters; and
timing the integrated circuit based on the plurality of critical test cases;
wherein:
the set of operating conditions comprises at least an operating temperature, an operating voltage, and an operating performance regime, and
the set of fabrication properties comprise a specification of a transistor process variation, one or more front end of line (FEOL) fabrication parameters, and one or more back end of line (BEOL) fabrication variations.