Patent ID: 11948921
Assignee: nan
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A method of forming a stacked semiconductor die assembly, the method comprising:
forming an iRDL structure over active surfaces of each of a number of singulated semiconductor dice to reroute bond pads thereof to different locations, each of the number of singulated semiconductor dice comprising through silicon vias (TSVs) extending to terminal pads on back sides thereof;
after forming the iRDL structure, laminating a polymer film over the active surfaces of each of the number of semiconductor dice;
forming through polymer via holes to expose rerouted bond pads of each of the number of singulated semiconductor dice;
filling the through polymer via holes with conductive material;
singulating the semiconductor dice through the polymer film;
inverting one of the number of singulated semiconductor dice and stacking the one of the number of singulated semiconductor dice on a substrate with the polymer film of the one of the number of singulated semiconductor dice in contact with the substrate and the conductive material-filled through polymer via holes aligned with exposed terminal pads of the substrate;
inverting at least one other of the number of singulated semiconductor dice and stacking the at least one other of the number of singulated semiconductor dice on the inverted one of the number of singulated semiconductor dice with the polymer film of the at least one other of the number of singulated semiconductor dice in contact with the conductive material-filled through polymer via holes of the at least one other of the number of singulated semiconductor dice aligned with terminal pads of the inverted one of the number of singulated semiconductor dice; and
bonding the stacked singulated semiconductor dice and the substrate together by heating the polymer film.