Patent ID: 11917807
Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 5:
6. The memory device that uses a semiconductor element according to claim 1, wherein during the page write operation, a positive hole group generated by the impact ionization phenomenon is held in the channel semiconductor layer, and a voltage of the channel semiconductor layer is set to a first data retention voltage higher than a voltage/voltages of one or both of the first impurity layer and the second impurity layer; and
during the page erase operation, by controlling voltages applied to the first impurity layer, the second impurity layer, the first gate conductor layer, and the second gate conductor layer, the positive hole group is pulled out from one or both of the first impurity layer and the second impurity layer, and the voltage of the channel semiconductor layer is set to a second data retention voltage lower than the first data retention voltage.