Patent ID: 11934480
Assignee: MACRONIX INTERNATIONAL CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. A circuit, comprising:
a block of NAND strings, including B columns and S rows of NAND strings, and L levels of memory cells, wherein B, S and L are integers, the NAND strings including L memory cells in series in respective levels of the L levels;
B bit lines coupled to S NAND strings in respective columns in the B columns; S string select lines coupled to B NAND strings in respective rows in the S rows;
W word lines operatively coupled to (B*S) memory cells in respective levels in the L levels;
a block source line operatively coupled to the NAND strings in the block;
string select line drivers coupled to the S string select lines to supply string select voltages to connect NAND strings on multiple string select lines to corresponding bit line simultaneously;
word line drivers coupled to apply word line voltages to a word line or word lines in a selected level;
a plurality of bit line drivers coupled to bit lines in the B bit lines to apply at least two different input data signals to a plurality of the B bit lines; and
a current sensing circuit coupled to the block source line, the current sensing circuit comprising at least one current sense amplifier connected directly to the block source line, and producing an output derived from the current on the block source line.