Patent ID: 11881853
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 17:
18. A method for operating a true complement dynamic circuit comprising:
comparing binary data on dynamic first and second input signals to a third input signal and a fourth input signal, by:
operating at least a 1-bit compare circuit, wherein the dynamic first and second input signals being complementary signals during an evaluation phase,
receiving the third input signal from a true compare data line (CMP_T);
receiving the fourth input signal from a complement compare data line (CMP_C);
determining a logical behavior by the third and fourth input signals, the logical behavior representing:
an XOR gate in the case of a precharge to ‘1’ logic circuit; and
an XNOR gate in the case of a precharge to “0” logic circuit, respectively;

wherein:
the third and fourth input signals are complementary signals during the evaluation phase.