Patent ID: 11894410
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 5:
6. The IC of claim 1,
wherein the first interconnect structure comprises: a first lowermost metal layer spaced at a first distance from a first surface of the first substrate; and a first uppermost metal layer spaced at a second distance from the first surface of the first substrate, the second distance being less than the first distance;
wherein the second interconnect structure comprises: a second lowermost metal layer spaced at a third distance from a first surface of the second substrate; and a second uppermost metal layer spaced at a fourth distance from the first surface of the second substrate, the fourth distance being greater than the third distance, wherein the second uppermost metal layer is nearer to the first lowermost metal layer than to the first uppermost metal layer; and
wherein a bond pad opening extends through the first substrate, through the first interconnect structure, and past the second uppermost metal layer, and wherein the bond pad is in direct contact with the second lowermost metal layer.