Patent ID: 11874784
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 18:
19. The memory system of claim 18, wherein the first ODT strap value is based on a first distance from the first CA pin of the first memory device to an internal pin of the memory module, and the second ODT strap value is based on a second distance from the second CA pin of the second memory device to the internal pin of the memory module,
wherein the first memory device further comprises a first CA ODT circuit connected to the first CA pin and the first CA buffer, and configured to provide a first ODT resistance value to the first CA pin of the first memory device, and
wherein the second memory device further comprises a second CA ODT circuit connected to the second CA pin and the second CA buffer, and configured to provide a second ODT resistance value to the second CA pin of the second memory device, the second ODT resistance value being different from the first ODT resistance value applied to the first CA pin of the first memory device.