Patent ID: 11871686
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 0:
1. An integrated circuit (IC) comprising a memory cell, wherein the memory cell comprises:
a lower electrode;
a high k dielectric layer overlying the lower electrode, wherein the high k dielectric layer has a peripheral region with a first concentration of crystalline defects and further has a central region with a second concentration of crystalline defects less than the first concentration; and
an upper electrode overlying the high k dielectric layer;
wherein the lower electrode underlies the central region, but not the peripheral region, wherein the central and peripheral regions meet at a boundary at which the high k dielectric layer changes from the first concentration to the second concentration, and wherein the boundary is closer to a sidewall of the lower electrode than to a sidewall of the high k dielectric layer on a same side of the memory cell as the sidewall of the lower electrode.