Patent ID: 11862622
Assignee: WINBOND ELECTRONICS CORP.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC H

Claim 10:
11. The integrated circuit layout according to claim 1, further comprising:
a third standard cell, comprising:
two third vertical cell boundaries arranged in parallel in the first direction and extending along the second direction;
two third lateral cell boundaries arranged in parallel in the second direction and extending along the first direction;
a plurality of third active region patterns between the two third vertical cell boundaries and extending along the first direction and arranged in parallel along the second direction; and
a plurality of third gate lines arranged along the first direction on the plurality of third active region patterns, wherein the third standard cell is abutted to another side of the first standard cell by overlapping one of the two first vertical cell boundaries and one of the two third vertical cell boundaries, the third gate lines respectively comprise a third gate line width and are distanced from each other by the default gate line pitch, the first gate line width and the third gate line width are different, a third cell width between the two third vertical cell boundaries are integral multiples of the default gate line pitch.