Patent ID: 11907744
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A processor comprising:
a first configuration register to store quality of service (QoS) information for a process address space identifier (PASID) value associated with a first process; and
an execution circuit coupled to the first configuration register, wherein the execution circuit, in response to a first instruction, is to obtain command data from a first location identified in a source operand of the first instruction, insert the QoS information and the PASID value into the command data, and send a request comprising the command data to a device coupled to the processor, to enable the device to use the QoS information of a plurality of requests to manage sharing between a plurality of processes, wherein the QoS information comprises a class value and a priority value and the device comprises an input/output (I/O) device, the I/O device to store the request in a first queue associated with a first class based on the class value, and select, based on the priority value, the request from a plurality of requests in the first queue for delivery to a processing circuit of the device.