Patent ID: 11972127
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory system, comprising:
a memory device including a plurality of memory blocks, wherein each of the plurality of memory blocks include a plurality of pages; and
a memory controller in communication with the memory device and configured to:
determine a first super memory block among a plurality of super memory blocks, wherein each of the plurality of super memory blocks includes one or more of the plurality of memory blocks,
set a lock to prevent a background operation from being executed for the first super memory block, and
transmit data stored in the first super memory block to an external device,

wherein the background operation for the first super memory block is not executed until the lock is released, and
wherein the memory controller is configured to determine the first super memory block among the plurality of super memory blocks to satisfy predetermined conditions that include i) a ratio of pages in which valid data is stored is equal to or greater than a preset threshold ratio and ii) an erase count is equal to or less than a preset threshold count.