Patent ID: 11894462
Assignee: ADEIA SEMICONDUCTOR SOLUTIONS LLC
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. A method comprising:
providing a substrate having thereon a layer of epitaxial channel material;
patterning a hardmask above the layer of epitaxial channel material;
performing a first etch, using the hardmask as a mask, to form an upper portion of a first fin and an upper portion of a second fin, the first fin adjacent to the second fin, the first etch extending beyond a bottom surface of the layer of epitaxial channel material;
forming a liner over exposed surfaces of the upper portions of the first and second fins;
performing a second etch, using the liner as a mask, to form a lower portion of the first fin and a lower portion of the second fin;
subsequent to performing the second etch, filling gaps between the first fin and the second fin with a dielectric material;
recessing the dielectric material to a level below the upper surfaces of the first and second fins; and
removing the liner,
subsequent to removing the liner, forming a gate dielectric on exposed surfaces of the upper portions of the first and second fins, wherein the gate dielectric extends beyond the bottom surface of the layer of epitaxial channel material.