Patent ID: 11935793
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. A method comprising:
forming a gate stack at a top surface of a semiconductor substrate;
etching an opening adjacent to the gate stack;
forming a source/drain region in the opening, wherein the source/drain region comprises a first epitaxy region comprising first impurities;
implanting second impurities in the first epitaxy region;
implanting third impurities in the first epitaxy region, the second impurities having a lower formation enthalpy than the third impurities;
performing an annealing process after implanting the third impurities in the first epitaxy region, wherein after the annealing process, a first doped region and a second doped region are defined, the first doped region being doped with the second impurities, the second doped region doped with the third impurities, the first doped region surrounding sides of the second doped region such that the second impurities of the first doped region extend along sides of the third impurities of the second doped region and below the third impurities of the second doped region; and
forming a source/drain contact extending into the second doped region, wherein a concentration of the third impurities at the source/drain contact is at least 1023 cm−3.