Patent ID: 11900991
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 18:
19. An integrated circuit, comprising:
a first data line group, comprising a plurality of local data lines arranged in an array;
a second data line group, comprising a plurality of complementary local data lines arranged in a second array, wherein the plurality of complementary local data lines and the plurality of local data lines respectively transmit signals having opposite phases;
a plurality of read circuits, configured to read, in response to a read control signal, signals of the plurality of local data lines or the plurality of complementary local data lines during a read operation, wherein each of the plurality of read circuits is electrically connected to a local data line of the plurality of local data lines at a boundary of the first data line group or connected to a complementary local data line of the plurality of complementary local data lines at a boundary of the second data line group; and
a plurality of global data lines and a plurality of complementary global data lines, wherein the plurality of global data lines and the plurality of complementary global data lines transmit signals having opposite phases, and the plurality of read circuits are configured to transmit, in response to the read control signal, the signals of the plurality of local data lines or the plurality of complementary local data lines to the plurality of global data lines or the plurality of complementary global data lines during the read operation;
wherein each of the plurality of read circuits comprises a first N-channel metal oxide semiconductor (NMOS) transistor and a second NMOS transistor,
a source of the first NMOS transistor is grounded, a drain of the first NMOS transistor is electrically connected to a source of the second NMOS transistor, and a gate of the first NMOS transistor receives the read control signal; and
a gate of the second NMOS transistor is electrically connected to one of the plurality of local data lines or one of the plurality of complementary local data lines, and a drain of the second NMOS transistor is electrically connected to one of the plurality of complementary global data lines or one of the plurality of global data lines.