Patent ID: 11861230
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 17:
18. A memory system comprising:
a memory device; and
a controller coupled to the memory device and including a clock generator configured to generate at least one clock signal and at least one operation module configured to operate in response to the clock signal,
wherein the controller is configured to:
determine whether a change condition of a clock signal satisfies;
when it is determined that the change condition is satisfied, control the clock generator to provide a first clock signal with a first frequency to the operation module;
determine, as target performance, performance of the memory system when the first clock signal is provided to the operation module;
decrease the first frequency to determine a second frequency;
monitor, as actual performance, performance of the memory system when a second clock signal with the second frequency is provided to the operation module;
determine whether the actual performance is greater than or equal to the target performance;
when it is determined that the actual performance is less than the target performance, determine the second clock signal as an optimal clock signal; and
control the clock generator to provide the optimal clock signal to the operation module,
wherein an optimal clock frequency set corresponding to the optical clock signal is a clock frequency set such that power consumption of the controller and the memory device is minimized, among clock frequency sets so that the actual performance is maintained greater than or equal to the target performance.