Patent ID: 11886835
Assignee: CEREMORPHIC, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A multi-stage multiplier operative to multiply a digital A input and a digital B input, each A input and B input having n input bits, the multi-stage multiplier comprising:
an input splitter subdividing the n A input bits and B input bits into at least two groups of subdivided bits, each group of subdivided bits having fewer than n bits and coupled to a respective sub-product multiplier generating a digital sub-product value, each sub-product multiplier comprising:
a plurality of unit elements, each said unit element comprising a plurality of AND-groups, each plurality of AND-groups comprising AND gates, each AND gate having one input coupled to a unique one of the subdivided A bits of a respective group and the other AND gate inputs commonly coupled to one of the B bits of the respective group, the output of each AND gate of each AND-group coupled to a particular analog charge line through a charge transfer capacitor of value C, each analog charge line coupled to a first terminal of a respective summing capacitor having a value which as a capacitance value Cs2n where n is a bit weighted order of the respective analog charge line and Cs is a value smaller than C, each summing capacitor having a second terminal which is coupled together with other summing capacitor second terminals and also coupled to an input of an analog to digital converter (ADC) generating a digital value as the output of the sub-multiplier;

each sub-multiplier output coupled to a binary shifter according to an order of the bits of the sub-multiplier;
each binary shifter outputs summed together to form an output.