Patent ID: 11928412
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 5:
6. The design method of claim 5, wherein acquiring the parasitic resistance of the target preset capacitor unit based on the minimum distances and the characteristic quantities comprises:
acquiring the parasitic resistance of the target preset capacitor unit based on a following formula:

R=Rtcp*(L_nc*nc/2+b/2+f−d)/(L_nr*nr+a+c−e); and

defining the arrangement direction of the preset capacitor units as an X direction, a Y direction being perpendicular to the arrangement direction of the preset capacitor units;
wherein R is the parasitic resistance, and Rtcp is a resistivity of the equivalent conductive layer;
b is the first side minimum distance, and f is the second side minimum distance;
nc is a number of the unit capacitors in the X direction, L_nc is a line width of the unit capacitors in the X direction, and d is a spacing between the unit capacitors in the X direction;
nr is a number of the unit capacitors in the Y direction, L_nr is a line width of the unit capacitors in the Y direction, and e is a spacing between the unit capacitors in the Y direction; and
a and c are minimum spacings between the boundary of the target preset capacitor unit and a boundary of the capacitor array in the Y direction.