Patent ID: 11923293
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An integrated chip comprising:
a first interconnect dielectric layer arranged over a substrate;
an interconnect wire extending through the first interconnect dielectric layer;
a barrier structure arranged directly over the interconnect wire;
an etch stop layer arranged over the barrier structure and surrounding outer sidewalls of the barrier structure;
a second interconnect dielectric layer arranged over the etch stop layer; and
an interconnect via extending through the second interconnect dielectric layer, the etch stop layer, and the barrier structure to contact the interconnect wire;
wherein the interconnect via comprises a middle surface that is arranged between a topmost surface and a bottommost surface of the interconnect via, and wherein the middle surface of the interconnect via is arranged below a topmost surface of the barrier structure.