Patent ID: 11940836
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A system comprising:
a first semiconductor circuit that includes a first clock and a first division counter and is configured to execute operations at both a slow clock speed and a fast clock speed, wherein the fast clock speed is an even multiple of the slow clock speed;
a second semiconductor circuit that includes a second clock and a second division counter and is configured to execute operations at both the slow clock speed and the fast clock speed; and
an input/output (IO) at an interface between the first and second semiconductor circuit that is capable of operating at the slow clock speed but not the fast clock speed, wherein the first and second semiconductor circuit are configured to:
set the first and second clock a common clock source when the first and second semiconductor circuits are in the slow clock speed;
synchronize the first and second division counters at the slow clock speed; and
simultaneously switch to the fast clock speed.