Patent ID: 11869623
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. A method, comprising:
receiving a first input signal by a sense amplifier and generating, by a first inverter in response to the first input signal, a second input signal and generating, by a second inverter, a third input signal in response to a fourth input signal generated by a third inverter based on the first input signal;
in a transparent mode, generating, by the sense amplifier, a first output signal to have a first voltage in response to a voltage level of the second input signal changing from a second voltage to the first voltage at a first node and a second output signal associated with the third input signal at a second node, wherein the first output signal and the second output signal have different logic values;
in response to a first control signal to the sense amplifier, in a latch mode, latching, by the sense amplifier, a first data at the first node according to a voltage level of the first output signal changing from the first voltage to a third voltage different from the first and second voltages, and latching, by the sense amplifier, a second data at the second node according to the second output signal,
wherein the first control signal and the first input signal have a same voltage;
adjusting, by the sense amplifier, a voltage swing of one of the first output signal and the second output signal;
outputting, by the sense amplifier, the second output signal from the second node to a first latch circuit, wherein the first latch circuit comprises first to fourth transistors coupled in series between first and second voltage terminals, wherein gates of the first and fourth transistors are coupled to the second node to receive the second output signal, a gate of the second transistor is configured to receive a second control signal, and a gate of the third transistor is configured to receive a third control signal, wherein the first to third control signals are different from each other, and the first and third control signals having different logic values; and
outputting, by turning on at least two transistors of the first to fourth transistors, a third output signal.