Patent ID: 11901009
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 6:
7. The address decoding circuit of claim 6, wherein one bank group comprises four banks, and the block address input signals comprise a first block address input signal and a second block address input signal;
a fourth NAND gate corresponding to a first bank in the bank group includes a first input end connected to an inverted signal of the first block address input signal and a second input end connected to an inverted signal of the second block address input signal;
a fourth NAND gate corresponding to a second bank in the bank group includes a first input end connected to the first block address input signal and a second input end connected to the inverted signal of the second block address input signal;
a fourth NAND gate corresponding to a third bank in the bank group includes a first input end connected to the inverted signal of the first block address input signal and a second input end connected to the second block address input signal; and
a fourth NAND gate corresponding to a fourth bank in the bank group includes a first input end connected to the first block address input signal and a second input end connected to the second block address input signal.