Patent ID: 11923369
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 18:
19. An integrated circuit comprising:
a first power rail on a back-side of a substrate, extending in a first direction, and being configured to supply a first voltage;
a second power rail on the back-side of the substrate, extending in the first direction, and being separated from the first power rail in a second direction different from the first direction, the second power rail being configured to supply a second voltage different from the first voltage;
a first flip-flop coupled to at least the first power rail and the second power rail, and including a first region, the first region comprising:
a first inverter coupled to the first power rail and the second power rail; and
a first output pin coupled to the first inverter, and being located on a first metal layer;

a second flip-flop coupled to at least the first power rail and the second power rail, and including a second region, the second region abutting the first region at a first boundary and comprising:
a second inverter coupled to the first power rail and the second power rail; and
a second output pin coupled to the second inverter, and being located on the first metal layer; and

a first conductive structure on a second metal layer above the first metal layer, extending in the second direction, overlapping the first boundary, and electrically coupling the first output pin and the second output pin together, each of the first inverter and the second inverter being configured to output a clock signal on the first conductive structure;
wherein the first flip-flop and the second flip-flop are on a front-side of the substrate opposite from the back-side; and
wherein the first output pin and the second output pin are offset from the first boundary in the second direction.