Patent ID: 11960990
Assignee: NANOSEMI, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. A method for operating a computing apparatus implementing an artificial neural network comprising:
receiving input values at input nodes of an input layer of a neural network comprising a plurality of nodes, at least some of the plurality of nodes further arranged in at least one hidden layer and an output layer;
computing for a first receiving node, from the plurality of nodes, a resultant value according to functions realized by respective links coupling the first receiving node to respective source nodes including a first source node and a second source node, wherein computing the resultant value for the receiving node comprises evaluating, by at least one link of the respective links coupling the receiving node to the respective source nodes, a piecewise linear function implemented on the at least one link and applied to a first source node from the respective source nodes, including a first piecewise linear function implemented on the link coupling the first source node to the first receiving node and a second piecewise linear function implemented on the link coupling the second source node to the first receiving node;
aggregating at the first receiving node values provided by the respective links coupling the receiving node to the respective source nodes to provide a non-linear output resulting, in part, from the evaluated piecewise linear function applied to the first source node by the piecewise linear function implemented by the at least one link; and
computing for a second receiving node, from the plurality of nodes, a resultant value according to functions realized by respective links coupling the second receiving node to respective source nodes including the first source node and the second source node, wherein computing the resultant value for the receiving node comprises evaluating, by at least one link of the respective links coupling the receiving node to the respective source nodes, a piecewise linear function implemented on the at least one link and applied to a first source node from the respective source nodes, including a third piecewise linear function implemented on the link coupling the first source node to the second receiving node and a fourth piecewise linear function implemented on the link coupling the first source node to the second receiving node, wherein the first, second, third, and forth piecewise linear functions are distinct functions;
wherein computing the resultant value for the receiving node comprises evaluating by multiple links of the respective links coupling the receiving node to the respective source nodes, piecewise linear functions implemented on the multiple links; and
wherein the evaluating comprises concurrent computation using computing circuitry of the computing apparatus of multiple of the piecewise linear functions.