Patent ID: 11916432
Assignee: MEDIATEK INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G  H

Claim 3:
4. The chip with power-glitch detection as claimed in claim 1, wherein the latch comprises:
a first PMOS, having a source terminal coupled to the power terminal;
a first NMOS, having a drain terminal coupled to a drain terminal of the first PMOS as the positive output terminal of the latch, a gate terminal coupled to a gate terminal of the first PMOS, and a source terminal coupled to the ground terminal;
a second PMOS, having a source terminal coupled to the power terminal;
a second NMOS, having a drain terminal coupled to a drain terminal of the second PMOS as the negative output terminal of the latch, a gate terminal coupled to a gate terminal of the second PMOS, and a source terminal coupled to the ground terminal;
wherein:
the gate terminals of the first PMOS and the first NMOS are connected to the drain terminals of the second PMOS and the second NMOS; and
the gate terminals of the second PMOS and the second NMOS are connected to the drain terminals of the first PMOS and the first NMOS.