Patent ID: 11966632
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. An apparatus, comprising:
a controller configured to couple with a memory system, wherein the controller is configured to cause the apparatus to:
receive, at a host system, logical to physical mapping information associated with data stored at a memory system, the logical to physical mapping information comprising a plurality of entries that each include a respective first field indicating a logical address, a respective second field indicating a physical address, and a respective third field comprising a respective value that indicates a respective quantity of data that is sequential to data associated with a respective entry;
store the logical to physical mapping information at the host system;
determine, after storing the logical to physical mapping information at the host system, whether to read first data and second data from the memory system using one command or a plurality of commands based at least in part on a quantity of data that a value of a third field of an entry indicates is sequential to the first data and from the plurality of entries; and
transmit, to the memory system, a command indicating for the memory system to read the first data based at least in part on determining whether to read the first data and the second data from the memory system using one command or a plurality of commands, the command comprising at least the value of the third field of the entry.