Patent ID: 11924063
Assignee: PAYPAL, INC.
Field: Digital communication (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A system comprising:
a processor; and
a non-transitory memory having stored thereon instructions that are executable by the processor to cause the system to perform operations comprising:
receiving, from an application executing on a user device, a request for a time estimate associated with a task;
determining a plurality of potential steps associated with executing the task;
determining an estimated completion time for the task by:
predicting a time estimate for each step of the plurality of potential steps;
selecting, from the plurality of potential steps, a shortest combination of steps comprising two or more steps; and
aggregating the respective time estimates for each step of the shortest combination of steps;

sending, to the application executing on the user device, the estimated completion time for the shortest combination of steps and information associated with the shortest combination of steps to execute the task;
identifying a delay in the shortest combination of steps;
updating, based on the identified delay, the estimated completion time for the shortest combination of steps; and
sending, to the application executing on the user device, a notification of the identified delay and the updated estimated completion time.