Patent ID: 11875154
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. The method of claim 9, wherein the first field identifies a first vector of floating-point numbers, the second field identifies a second vector of floating-point numbers, and the execution circuit executes the decoded single instruction to:
cause a plurality of first comparisons of each exponent of the first vector of floating-point numbers to the about zero threshold,
cause a plurality of second comparisons of each exponent of the second vector of floating-point numbers to the about zero threshold,
provide as a resultant of the single instruction the value of zero for each of the plurality of first comparisons that indicates the exponent of a corresponding first floating-point number of the first vector of floating-point numbers does not exceed the about zero threshold,
provide as the resultant of the single instruction the value of zero for each of the plurality of second comparisons that indicates the exponent of a corresponding second floating-point number of the second vector of floating-point numbers does not exceed the about zero threshold, and
provide as the resultant of the single instruction a product of a multiplication of a first floating-point number of the first vector of floating-point numbers and a corresponding second floating-point number of the second vector of floating-point numbers when a first comparison indicates the exponent of the first floating-point number exceeds the about zero threshold and a corresponding second comparison indicates the exponent of the corresponding second floating-point number exceeds the about zero threshold.