Patent ID: 11955184
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. The apparatus of claim 1, wherein the one or more control circuits are configured to:
program the group of the memory cells to one bit per memory cell together without verifying, wherein the first set of the memory cells is programmed to a first natural threshold voltage distribution, wherein the second set of the memory cells is programmed to a second natural threshold voltage distribution that has a different threshold voltage range than the first natural threshold voltage distribution;
read the one bit per memory cell in the first set of the memory cells with the first set of read parameters; and
read the one bit per memory cell in the second set of the memory cells with a second set of read parameters, wherein the first set of read parameters are different from the second set of read parameters to compensate for different threshold voltage ranges in the first and the second natural threshold voltage distributions.