Patent ID: 11959965
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Measurement (Instruments)
Classification: CPC G | IPC G

Claim 5:
6. A test circuit for testing an integrated circuit core or an external circuit of the integrated circuit core, the test circuit comprising:
a clock gating circuit configured to:
receive a scan enable signal through a scan enable terminal, a clock signal through a clock signal terminal and a test signal, and
output a first output signal to control whether the clock signal is gated in response to a combination of the scan enable signal and the test signal;
a cell function input (CFI) terminal configured to receive a CFI signal;
a cell test input (CTI) terminal configured to receive a CTI signal; and
a scan flip-flop configured to:
receive the first output signal, the CFI signal, and the CTI signal, and
either hold or output data of captured one of the CFI signal input through the CFI terminal and the CTI signal input through the CTI terminal in response to the first output signal of the clock gating circuit.