Patent ID: 11915943
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor structure, comprising:
a conductive feature disposed over a semiconductor substrate;
a via disposed in a first interlayer dielectric (ILD) layer over the conductive feature;
a metal-containing etch-stop layer (ESL) disposed on the via, wherein the metal-containing ESL includes a first metal and is resistant to etching by a fluorine-containing etchant;
a conductive line disposed over the metal-containing ESL, wherein the conductive line includes a second metal different from the first metal and is etchable by the fluorine-containing etchant, and wherein the via is configured to interconnect the conductive line to the conductive feature; and
a second ILD layer disposed over the first ILD layer, wherein the second ILD layer extends to contact a sidewall of the metal-containing ESL.