Patent ID: 11961774
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor device, comprising:
a semiconductor substrate, comprising a plurality of chip regions and strip lines for separating the chip regions,
wherein test keys are formed in the strip lines, among which each of the test keys comprises:
a plurality of active regions, disposed in the semiconductor substrate, staggered and arranged in parallel, wherein an extending direction of the plurality of active regions has an included angle in the range of 60°-80° with a row direction; and
a plurality of connecting structures, disposed at ends of the plurality of active regions, the plurality of active regions aligned on a same column being sequentially connected end to end by the plurality of connecting structures, one of the plurality of active regions and corresponding connecting structures disposed at a head end and a tail end of the one of the plurality of active regions jointly constitute a “Z”-shaped test key in a column direction.