Patent ID: 11955199
Assignee: MACRONIX INTERNATIONAL CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. An operation method of memory device, comprising:
receiving a write request and a first data from a host controller;
transmitting a write command indicating a first parameter, wherein the first parameter represents the number of bits of binary data to be written into one memory unit, each memory unit is configured to store at most N bits of binary data, and N is an integer greater than 1;
in response to the write command, when the first parameter is K which is an positive integer smaller than N, configuring the first data as sub-data every K bit(s), generating a (N−K)-bit pseudo data corresponding to each of the sub-data, and storing the sub-data and the pseudo data into the at least one buffer; and

for each of the memory units to be programmed, programing the memory unit according to the K-bit sub-data to be written into the memory unit and the (N−K)-bit pseudo data corresponding to the sub-data to be written into the memory unit, to cause a threshold voltage of the memory unit to fall within one of 2K voltage ranges selected from 2N voltage ranges, wherein the 2N voltage ranges one-to-one corresponding to 2N data patterns formed by N bits of binary data.