Patent ID: 11967591
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A semiconductor package comprising:
a first package, the first package comprising:
a first die embedded in an encapsulant;
a first interconnect structure disposed over the first die;
a plurality of dielectric layers disposed below the first die;
a second interconnect structure disposed within the plurality of dielectric layers; and
a conductive feature disposed below the plurality of dielectric layers, wherein the conductive feature and a portion of the plurality of dielectric layers form a thermal dissipation window, the portion extending from a bottom surface of the first die through an entirety of the plurality of dielectric layers, the thermal dissipation window being electrically isolated from the second interconnect structure;

a second package, the second package comprising:
a third interconnect structure embedded in a substrate;
a molding compound along the substrate;
a second die embedded in the molding compound; and
a through via extending from a first surface of the substrate to a second surface of the molding compound, the first surface and the second surface facing away from one another; and

first conductive connectors and second conductive connectors attaching the first package to the second package, one of the second conductive connectors being electrically connected to the conductive feature, the second conductive connectors and the conductive feature being electrically isolated from the second package.