Patent ID: 11954329
Assignee: PHISON ELECTRONICS CORP.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. A memory control circuit unit, configured to control a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of dies, each of the plurality of dies comprises a plurality of planes, each of the plurality of planes comprises a plurality of physical erasing units, and a sum of a number of the plurality of planes comprised in the rewritable non-volatile memory module is a first number, wherein the memory control circuit unit comprises:
a host interface configured to be coupled to a host system;
a memory interface configured to be coupled to the rewritable non-volatile memory module; and
a memory management circuit coupled to the host interface and the memory interface,
wherein the memory management unit is configured to group the plurality of physical erasing units into a plurality of management units,
wherein each of the plurality of physical erasing units comprised in each of the plurality of management units respectively belongs to a plurality of different planes, and each of the plurality of management units has a second number of the plurality of physical erasing units,
wherein the second number is less than the first number.