Patent ID: 11940483
Assignee: TEKTRONIX, INC.
Field: Measurement (Instruments)
Classification: CPC G | IPC G  H

Claim 22:
23. A margin tester comprising:
a plurality of interfaces, wherein at least one interface of the plurality of interfaces is configured to connect to a removable test fixture that is connectable to a device under test (DUT);
one or more lanes connected to the at least one interface to couple the margin tester, via the test fixture, to the DUT; and
one or more controllers configured to:
establish a single-lane or multi-lane high speed input/output (I/O) link with the DUT through the one or more lanes and the test fixture, in which, for one or more lanes of the single-lane or multi-lane high speed I/O link, the one or more controllers implement physical and logical link layers that communicatively connect the margin tester with the DUT via the at least one interface and the test fixture; and
assess an electrical margin of the single-lane or multi-lane high speed I/O link in either or both transmit (Tx) and receive (Rx) directions.