Patent ID: 11951569
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC B  H | IPC B  H

Claim 13:
14. A method comprising:
aligning a wafer over a wafer chuck within a processing chamber, the wafer having thickness defined between an upper surface of the wafer and a lower surface of the wafer, the upper surface and the lower surface terminating at a circumferential edge that surrounds a central axis of the wafer;
rotating the wafer chuck and the wafer at a first rotational speed within the processing chamber;
while the wafer chuck and the wafer are rotating, using a blade to remove an annular portion of the upper surface of the wafer to thereby define an annular ledge that is recessed relative to the upper surface of the wafer along the circumferential edge of the wafer;
as the wafer chuck and the wafer are rotating and the blade is removing the annular portion of the upper surface of the wafer, measuring a lattice stress condition in an area of the wafer adjacent to the blade; and
reducing the first rotational speed of the wafer chuck and wafer to a second rotational speed when the lattice stress condition measured in the area of the of the wafer adjacent to the blade is greater than a predetermined stress threshold.