Patent ID: 11929121
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. An apparatus, comprising:
a memory array including a plurality of memory cells; and
circuitry coupled to the array of memory cells, wherein the circuitry is configured to:
select a pair of memory cells from the plurality of memory cells, wherein the pair of memory cells are located adjacent to one another along a same access line of the memory array; and
store one data value by programming a first memory cell of the pair of memory cells to a first data state, a second data state, or a third data state and by programming a second memory cell of the pair of memory cells to the first data state, the second data state, or the third data state, wherein:
the one data value corresponds to a combination of the first data state, the second data state, or the third data state to which the first memory cell of the pair of memory cells is programmed and the first data state, the second data state, or the third data state to which the second memory cell of the pair of memory cells is programmed; and
two combinations of the first data state, the second data state, or the third data state to which the first memory cell of the pair of memory cells is programmable and the first data state, the second data state, or the third data state to which the second memory cell of the pair of memory cells is programmable are ineligible to correspond to the one data value.