Patent ID: 11928329
Assignee: NXP B.V.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. The IC of claim 12, wherein a logic circuit of the second set of logic circuits comprises:
a second multiplexer that is coupled to the address decoder, and configured to receive a second write bit of the set of write bits, a second mask bit of the set of mask bits, and the third control bit, and select and output, based on the third control bit, one of a group consisting of the second write bit and the second mask bit as an intermediate bit; and
a third multiplexer that is coupled to the second multiplexer and a second storage element of the second half of the register, and configured to (i) receive the intermediate bit, a second register bit of the set of register bits that is stored in the second storage element, and a third select bit that is derived from the second mask bit, (ii) select and output, based on the third select bit, one of a group consisting of the second register bit and the intermediate bit as a second output bit, and (iii) write the second output bit to the second storage element, wherein when the second mask bit has the first logic state, the second write bit is written to the second storage element, and when the second mask bit has the second logic state, the second register bit is written to the second storage element.