Patent ID: 11907091
Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A computing device, comprising:
a plurality of processing units;
a plurality of (N-1)-level caches;
an N-level cache that is associated with two or more of the plurality of (N-1)-level caches, and that is configured as a backing store for the two or more (N-1)-level caches; and
control logic that includes computer-executable instructions to configure the computing device to record execution of an entity that executes parallel threads across two or more of the plurality of processing units, based on performing at least the following:
based at least on detecting an influx of memory data from a particular memory location in system memory to a particular cache location in the N-level cache that results from execution of a first thread of the entity by a first of the plurality of processing units, cause the influx of memory data to the particular cache location in the N-level cache to be logged into a replayable trace of the entity; and
based at least on having caused the influx of memory data to the particular cache location in the N-level cache to be logged into the replayable trace of the entity, subsequently cause one or more (N-1)-level cache coherence protocol (CCP) transitions between the two or more (N-1)-level caches to be logged into the replayable trace of the entity, the (N-1)-level CCP transitions resulting from the particular cache location being accessed by a second of the plurality of processing units based on execution of a second thread of the entity by the second of the plurality of processing units.