Patent ID: 11929412
Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 10:
11. A semiconductor device comprising:
a substrate;
a first insulating layer over the substrate;
a second insulating layer over the first insulating layer;
an oxide semiconductor layer over the second insulating layer;
a third insulating layer over the oxide semiconductor layer;
a first gate electrode over the third insulating layer;
a fourth insulating layer over the first gate electrode;
a first conductive layer functioning as one of a source and a drain of a transistor and being electrically connected to the oxide semiconductor layer; and
a second conductive layer functioning as the other of the source and the drain of the transistor and being electrically connected to the oxide semiconductor layer,
wherein, in a top view, the second insulating layer has an island shape,
wherein the fourth insulating layer is in contact with a top surface of the first insulating layer, a top surface and a side surface of the second insulating layer, and a top surface of the oxide semiconductor layer, and
wherein, in the top view, an end portion of the second insulating layer and an end portion of the one of the source and the drain of the transistor are substantially aligned with each other.