Patent ID: 11916146
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A method comprising:
forming a gate stack, wherein the gate stack is between a first portion and a second portion of a gate spacer, and wherein the gate stack comprises:
a gate dielectric;
a work-function layer over a portion of the gate dielectric; and
a metal-containing layer over the work-function layer;

recessing the gate spacer and the gate stack to form a recess, wherein the recess extends to a level lower than top ends of the gate spacer, and wherein first top surfaces of the work-function layer and the metal-containing layer are lower than a second top surface of the gate dielectric, wherein after the gate spacer is recessed, a first top surface of the gate spacer is lower than a third top surface of a contact etch stop layer, and wherein the contact etch stop layer contacts a sidewall of the gate spacer to form a vertical interface; and
forming a metal layer in the recess and over the work-function layer.