Patent ID: 11972810
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. The memory apparatus as set forth in claim 3, wherein the plurality of targeted word line biases include a plurality of verify voltages each associated with one of the plurality of data states for the selected ones of the plurality of word lines and a plurality of read pass voltages for the unselected ones of the plurality of word lines and the control means is further configured to:
select and apply one of the plurality of verify voltages to each one of the selected ones of the plurality of word lines based on which of the plurality of data states is associated with the memory cells connected to the one of the selected ones of the plurality of word lines and being verified during the verify phase of each of the plurality of program loops; and
select and apply one of the plurality of read pass voltages to the unselected ones of the plurality of word lines depending on a proximity of the unselected ones of the plurality of word lines to the one of the selected ones of the plurality of word lines in the at least one block and whether the unselected ones of the plurality of word lines are programmed.