Patent ID: 11881454
Assignee: ADEIA SEMICONDUCTOR INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A three-dimensional circuit, comprising:
a first integrated circuit (IC) die comprising a first set of interconnect layers;
a second IC die face-to-face mounted with and directly bonded with the first IC die and comprising a second set of interconnect layers,
wherein a first layer of the first set of interconnect layers has a majority of conductive line segments elongated in a first direction and a second layer of the second set of interconnect layers has a majority of conductive line segments elongated in a second direction orthogonal to the first direction, and
wherein a topmost interconnect layer of the first set of interconnect layers and a topmost interconnect layer of the second set of interconnect layers are directly hybrid bonded together, each of the topmost interconnect layers comprising conductive structures electrically connecting one or more of the conductive line segments of the first layer with one or more of the conductive line segments of the second layer.