Patent ID: 11900881
Assignee: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. The display substrate according to claim 1, wherein the scan driving circuit further includes a first voltage signal line, a second voltage signal line, a first clock signal line, and a second clock signal line; the at least one shift register unit also includes a signal output line, a first capacitor, an output capacitor, an output reset capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, an input transistor and a node control transistor; a first electrode plate of the output reset capacitor is coupled to a gate electrode of the second switch, and a second electrode plate of the output reset capacitor is coupled to the first voltage signal line;
the signal output line includes a first output line portion and at least one second output line portion;
a first electrode of the first switch is coupled to the second voltage signal line, and a first electrode of the second switch is coupled to the second electrode plate of the output reset capacitor; a second electrode of the first switch and a second electrode of the second switch are respectively coupled to the first output line portion;
a first electrode plate of the output capacitor is coupled to the gate electrode of the first switch, and a second electrode plate of the output capacitor is coupled to a gate electrode of the seventh transistor;
a gate electrode of the first transistor is coupled to a gate electrode of the third transistor, and the gate electrode of the first transistor is coupled to the first electrode of the first switch; a second electrode of the first transistor is coupled to a gate electrode of the first switch;
a gate electrode of the second transistor is coupled to a gate electrode of the input transistor, a first electrode of the second transistor is coupled to the first electrode of the first switch, and a second electrode of the second transistor is coupled to a gate electrode of the eighth transistor;
a first electrode of the third transistor is coupled to the gate electrode of the eighth transistor, and a second electrode of the third transistor is coupled to a gate electrode of the fourth transistor;
a first electrode of the fourth transistor is coupled to the first clock signal line, and a gate electrode of the fifth transistor is coupled to the first clock signal line;
the gate electrode of the fourth transistor is coupled to the first electrode plate of the first capacitor, and the second electrode plate of the first capacitor is coupled to the second electrode of the fourth transistor; the second electrode of the fourth transistor is multiplexed as a first electrode of the fifth transistor;
a second electrode of the fifth transistor is coupled to a second electrode of the sixth transistor;
a gate electrode of the sixth transistor is coupled to a gate electrode of the node control transistor, and a first electrode of the sixth transistor is coupled to a first electrode of the second switch;
a second electrode of the fifth transistor is coupled to a first electrode plate of the output reset capacitor, and a first electrode of the sixth transistor is connected to a second electrode plate of the output reset capacitor;
a gate electrode of the seventh transistor is coupled to the second electrode plate of the output capacitor, and a first electrode of the seventh transistor is multiplexed as a second electrode of the eighth transistor, a second electrode of the seventh transistor is coupled to the gate electrode of the node control transistor;
a gate electrode of the eighth transistor is coupled to the second electrode of the node control transistor, and a first electrode of the eighth transistor is coupled to the first voltage signal line;
a gate electrode of the input transistor is coupled to the second clock signal line, and a first electrode of the input transistor is coupled to the input end;
the gate electrode of the node control transistor is coupled to the first electrode of the first transistor, and the gate electrode of the node control transistor is also coupled to the second electrode of the input transistor;
the first electrode of the node control transistor is coupled to the gate electrode of the input transistor;
the second output line portion extends to the display area and is used to provide a light emitting control signal for a pixel circuit located in the display area;
wherein the input transistor, the node control transistor, the seventh transistor, the eighth transistor, the fourth transistor, and the fifth transistor and the output reset capacitor are arranged in sequence along the first direction;
the input transistor and the second transistor are arranged along the second direction;
the node control transistor, the output capacitor, and the first switch are arranged along the second direction;
the third transistor, the fourth transistor, the first capacitor, and the output reset capacitor are arranged in sequence along the first direction;
the first transistor, the sixth transistor, and the output reset capacitor are arranged in sequence along the first direction.