Patent ID: 11886290
Assignee: SONY INTERACTIVE ENTERTAINMENT LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An information processing apparatus comprising:
a memory; and
a memory controller writing data to the memory in response to a write for writing the data to the memory, wherein
the memory executes error correction processing for each data of a predetermined data length, and
the memory controller executes, in place of the memory, read modify write processing in a case where a data length of the data related to the write instruction is smaller than the predetermined data length, wherein:
the memory controller divides a sequence of read modify write processing into separate read processing, merge processing, and write processing, and causes consecutive execution of the read processing or write processing and another read processing or write processing,
the memory controller includes a memory queue, separate from the memory, as a temporary storage region usable for the read modify write processing, where the queue includes a plurality of entries each holding read data or write target data, and
information related to the read modify write processing to be executed is held in the queue to delay execution of the read processing and the write processing included in the read modify write processing, such that even after the read modify write processing ends, data in one or more of the entries of the queue holding the data corresponding to the ended processing is not discarded, and is used for data supply for a read request for a read from an address in the memory at which the data is stored or for integration of write data to be written to the address.