Patent ID: 11861208
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A non-transitory computer readable storage medium comprising instruction that, when executed by a processing device of a memory device, cause the processing device to perform operations comprising:
receiving a request to perform a read operation associated with at least one memory unit in a plurality of memory units of the memory device, the at least one memory unit comprising a first group of memory cells, each memory cell in the first group of memory cells supporting a specified number of charge levels such that each memory cell having a specified charge level represents a non-integer number of bits, the first group of memory cells represents a first sequence of bits based on a first sequence of charge levels stored by the first group of memory cells, and the first sequence of bits comprising an integer number of bits; and
performing the read operation on the at least one memory unit based on a mapping information, wherein the mapping information maps an individual sequence of charge levels, stored by an individual group of memory cells, to an individual sequence of bits that is below a specified Gray code penalty, wherein the mapping information comprises a mapping assignment matrix that satisfies a constraint of: {0, 1, 2, . . . , 2k−1}⊂unique(Σp2pMp), wherein Mp is a matrix having a size of L×L, wherein L is the specified number of charge levels, wherein k is a number of assignments, and wherein performing the read operation comprises:
reading the first sequence of charge levels from the first group of memory cells;
determining, based on the mapping assignment matrix, the first sequence of bits corresponding to the first sequence of charge levels; and
providing the first sequence of bits in response to the request.