Patent ID: 11948851
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. A semiconductor package comprising:
a wiring structure comprising an active region and a plurality of scribe lanes in continuity with side surfaces of the active region;
a semiconductor chip on the wiring structure;
a plurality of internal terminals between the wiring structure and the semiconductor chip;
a high thermal conductivity layer between the wiring structure and the semiconductor chip, the high thermal conductivity layer contacting the active region and the plurality of scribe lanes; and
an encapsulator on the wiring structure and the high thermal conductivity layer and contacting the semiconductor chip, the encapsulator including an upper surface at a different height compared to an upper surface of the semiconductor chip,
wherein the high thermal conductivity layer contacts a side surface of the semiconductor chip,
a maximum contact height between the high thermal conductivity layer and the semiconductor chip is a first length,
a height of the semiconductor chip is a second length,
the first length is greater than half of the second length, and
an upper surface of the encapsulator includes a flat portion substantially parallel to an upper surface of the wiring structure and an inclined portion between the flat portion and the semiconductor chip.