Patent ID: 11901280
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 2:
3. The semiconductor package of claim 1, further comprising:
a third layer of dielectric material on the second layer of dielectric material;
a fifth via above and electrically coupled to the third via and being in the third layer of dielectric material of the package substrate;
a sixth via above and electrically coupled to the fourth via and being in the third layer of dielectric material of the package substrate, the sixth via laterally spaced apart from the fifth via;
wherein the first line perpendicular to the first side of the package substrate intersects the ground solder ball pad, the first via, the third via, and the fifth via; and
wherein the second line perpendicular to the first side of the package substrate intersects the ground solder ball pad, the second via, the fourth via, and the sixth via.