Patent ID: 11935617
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. An apparatus, comprising:
an array of memory cells, the array comprising a set of word lines and a set of digit lines;
one or more sense amplifiers operable to couple with the set of digit lines;
a data line operable to couple with the one or more sense amplifiers;
circuitry operable to generate a current based at least in part on a mismatch between first data written to the one or more sense amplifiers from the data line and second data latched by the one or more sense amplifiers; and
a controller operable to cause the apparatus to:
latch the second data to the one or more sense amplifiers based at least in part on activating one or more word lines of the set of word lines;
deactivate the one or more word lines after latching the second data to the one or more sense amplifiers;
write the first data to the one or more sense amplifiers via the data line after deactivating the one or more word lines; and
output an indication of whether the first data matches the second data based at least in part on writing the first data to the one or more sense amplifiers.