Patent ID: 11960727
Assignee: MARVELL ASIA PTE LTD
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A system comprising:
a processor associated with a data-processing width; and
a processor accelerator configured to perform a large memory transaction (LMT) store of a data set to a coprocessor in response to an instruction from the processor targeting the coprocessor, the data set corresponding to the instruction, the LMT store including storing data from the data set, atomically, to the coprocessor based on a LMT line (LMTLINE), the LMTLINE wider than the data-processing width,
the processor accelerator further configured to send, to the processor, a response to the instruction, the response based on completion of the LMT store of the data set in its entirety.