Patent ID: 11968836
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A three-dimensional (3D) semiconductor memory device comprising:
a substrate including a cell array region and a connection region;
an electrode structure on the substrate, the electrode structure comprising gate electrodes stacked in a first direction vertical to a top surface of the substrate, the electrode structure extending from the cell array region onto the connection region in a second direction parallel to the top surface of the substrate, and the gate electrodes including electrode pad regions on the connection region;
a source structure between the substrate and the electrode structure, the source structure extending from the cell array region onto the connection region in the second direction;
a lower sacrificial pattern between a first portion of the source structure and the substrate and on the connection region;
a vertical semiconductor pattern penetrating the electrode structure and a second portion of the source structure on the cell array region; and
a dummy vertical semiconductor pattern penetrating one of the electrode pad regions on the connection region,
wherein the dummy vertical semiconductor pattern is wider, in the second direction, than the vertical semiconductor pattern.