Patent ID: 11869968
Assignee: ATOMERA INCORPORATED
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. A semiconductor device comprising:
a substrate;
spaced apart first and second doped regions in the substrate having a first conductivity type, the first doped region being larger than the second doped region to define an asymmetric channel therebetween;
a superlattice extending between the first and second doped regions to constrain dopant therein;
the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions;
a well implant constrained within the substrate by the superlattice adjacent the second doped region and having a second conductivity type different than the first conductivity type; and
a gate overlying the asymmetric channel so that the first doped region extends laterally beneath the gate beyond a center thereof.