Patent ID: 11880689
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A server power-down detection method, comprising following steps:
in response to a completion of hardware power on, controlling a platform controller hub (PCH) to read BIOS (Basic Input Output System) codes from a BIOS flash memory via a first interface and running the BIOS codes;
detecting whether bits of a register of the PCH have been set;
in response to the bits of the register of the PCH being set, controlling the PCH to send power-down completion information to a BMC (Baseboard Management Controller) via a second interface; and
in response to the BMC receiving the power-down completion information, recording the power-down completion information in a BMC flash memory, and performing the hardware power on again until a test is completed.