Patent ID: 11907720
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A data processing apparatus comprising:
a plurality of registers, each of the registers having data bits to store data, and metadata bits to store metadata, wherein each of the registers is adapted to operate in a metadata mode in which the metadata bits and the data bits are valid, and a data mode in which the data bits are valid and the metadata bits are invalid;
mode bit storage circuitry adapted to indicate whether each of the registers is in the data mode or the metadata mode; and,
execution circuitry, responsive to a memory operation that is a store operation on one or more given registers:
to determine from the mode bit storage circuitry whether a register in the one or more given registers is in the data mode or the metadata mode;
to store the data bits of the register and the metadata bits of the register to a data structure in memory when the register is in the metadata mode; and,
to store the data bits of the register without the metadata bits of the register to the data structure in the memory when the register is in the data mode.