Patent ID: 11972838
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 2:
3. A signal processing circuit, further comprising:
a first signal latch circuit that receives a command address signal and is driven by an even clock;
a second signal latch circuit that receives the command address signal and is driven by an odd clock; and
a decoder that is connected to the first signal latch circuit and the second signal latch circuit and outputs a control signal;
wherein a frequency of the even clock and a frequency of the odd clock are both equal to half a frequency of a reference clock, and a rising edge of the even clock and a rising edge of the odd clock are aligned with a rising edge of the reference clock;
the signal processing circuit further comprising:
a clock shaping circuit that receives the reference clock and outputs the even clock and the odd clock;
a first register group that receives the control signal and is driven by the even clock; and
a second register group that receives the control signal and is driven by the odd clock.