Patent ID: 11869579
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. The page buffer circuit of claim 19, wherein
each of the plurality of page buffers is configured to perform a second refresh operation process that, in the case where the inverted data in the storage node represent the first state, stores the data representing the second state in the storage node, and
to perform the second refresh process that stores the data representing the second state in the storage node,
the precharge circuit is configured to precharge the sensing node to the power supply voltage in response to the load signal,
the read transistor is configured to turn on in response to the read signal to provide the turned-on read transistor,
the storage transistor is configured to be turned on by the first voltage corresponding to the first state of the inverted data of the storage node to provide the turned-on storage transistor,
the turned-on read transistor and the turned-on storage transistor provide the ground voltage to the sensing node such that the data representing the second state are stored in the sensing node,
the write transistor is configured to turn on in response to the write signal to provide the turned-on write transistor and the turned-on write transistor connects the sensing node to the storage node such that the data representing the second state are stored in the storage node by the charge sharing between the storage node and the sensing node, and
wherein the bitline selection transistor includes a gate configured to receive a bitline selection signal, a first terminal connected to the corresponding bitline, and a second terminal connected to the sensing node.