Patent ID: 11956860
Assignee: FUJITSU LIMITED
Field: Digital communication (Electrical engineering)
Classification: CPC H  Y | IPC H

Claim 0:
1. A terminal comprising:
a memory; and
a processor coupled to the memory and configured to:
receive, from a first network device, an indication information relating to a predetermined position of a time window for a first synchronization signal (SS) block from a plurality of predetermined positions of the time window, the predetermined position being indicated by a period of a transmission of the first SS block and a time length from a starting position of the period,
receive the first SS block from the first network device or a second SS block from a second network device within the time window of the predetermined position in the period, wherein

the indication information relating to the predetermined position is included in measurement timing information that is transfer from the first network device to the second network device of a neighboring cell.