Patent ID: 11923453
Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 2:
3. The method for preparing the LDMOS device according to claim 2, wherein the forming the interlayer dielectric layer and etching the interlayer dielectric layer and the barrier layer to form the n levels of field plate holes further comprises:
etching the interlayer dielectric layer to form a source contact hole and a drain contact hole simultaneously, wherein an etching of the source contact hole stops at the source region, and an etching of the drain contact hole stops at the drain region; and
filling the source contact hole, the drain contact hole, and the n levels of field plate holes with metal, to form a source electrode, a drain electrode, and an n levels of hole field plates.