Patent ID: 11956966
Assignee: WINBOND ELECTRONICS CORP.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of forming a silicon-oxide-nitride-oxide-silicon (SONOS) memory cell, comprising:
sequentially depositing a first dielectric layer and a first electrode layer on a substrate;
patterning the first electrode layer and the first dielectric layer, to form a second dielectric layer and an electrode layer stacked from bottom to top;
removing two ends of the second dielectric layer, so that a dielectric layer being formed, wherein the electrode layer protrudes from the dielectric layer;
forming two charge trapping layers on sidewalls of the dielectric layer and the electrode layer, so that the charge trapping layers have L-shaped cross-sectional profiles; and
forming two selective gates at two opposite sides of the charge trapping layers, thereby constituting a two bit memory cell, wherein FN tunneling is induced while erasing, and wherein a top surface of the electrode layer is lower than a top surface of each selective gate, and wherein all of the selective gates does not disposed right above the electrode layer.