Patent ID: 11861049
Assignee: THE GEORGE WASHINGTON UNIVERSITY
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 14:
15. A system for defense against timing channel attacks, the system comprising:
a cache occupancy monitor configured to produce cache occupancy data tracking a number of cache blocks occupied by each of a plurality of application processes;
an occupancy pattern analyzer configured to analyze the cache occupancy data to identify a potential cache timing channel attack based on patterns of cache occupancy mirrored between application domains, wherein the potential cache timing channel attack is associated with a highest autocorrelation of the autocorrelations of cache occupancy of the pairs of application domains in respective time windows; and
a cache partition manager configured to partition cache access between a pair of application processes involved in the potential cache timing channel attack by assigning at least one of the pair of application processes to a separate cache partition, wherein each cache partition has a predefined cache ways accessible to a corresponding application process.