Patent ID: 11967357
Assignee: NATIONAL TSING HUA UNIVERSITY
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 19:
20. The computing method of claim 17, wherein a number of the at least one edge-delay cell multiplexor of the memory unit is plural, a number of the at least one edge-delay cell is plural, and the computing step further comprises:
configuring the edge-delay cell multiplexors to transmit a plurality of the weights to the edge-delay cells; and
configuring the edge-delay cells to receive a plurality of the multi-bit analog input voltages, a plurality of the edge-input signals and the weights, and then generate a plurality of the edge-output signals having a plurality of the delay times;
wherein the delay time of a last one of the edge-output signals is positively correlated with a sum of the multi-bit analog input voltages multiplied by the weights.