Patent ID: 11961586
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A memory system comprising:
a first semiconductor storage device;
a second semiconductor storage device; and
a controller configured to control data writing to and data reading from the first semiconductor storage device and second semiconductor storage device, wherein
the first semiconductor storage device includes
a first input circuit to which a signal from the controller is input,
a first timing information storage circuit configured to store first timing information related to a start timing of first correction processing that corrects a duty cycle of the signal in the first semiconductor storage device, and
a first control circuit configured to start the first correction processing in response to a command instructing execution of the first correction processing, the first correction processing being started at a first timing corresponding to the first timing information, and

the second semiconductor storage device includes
a second input circuit to which a signal from the controller is input,
a second timing information storage circuit configured to store second timing information related to a start timing of second correction processing that corrects a duty cycle of the signal in the second semiconductor storage device, and
a second control circuit configured to start the second correction processing in response to the command, the second correction processing being started at a second timing corresponding to the second timing information.