Patent ID: 11948848
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An electronic package, comprising:
a substrate, the substrate comprising a dielectric layer;
a conductive feature over the substrate, the conductive feature having a first width proximate to a top portion of the conductive feature, a second width proximate to a middle portion of the conductive feature, and a third width proximate to a bottom portion of the conductive feature, the bottom portion of the conductive feature directly on the dielectric layer of the substrate, wherein the second width is smaller than the first width, and the second width is smaller than the third width; and
a metallic mask over the conductive feature, wherein the metallic mask extends beyond a first edge of the conductive feature and a second edge of the conductive feature, and wherein the metallic mask has a lateral width greater than a maximum lateral width of the conductive feature.