Patent ID: 11934654
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An integrated circuit (IC) memory device comprising:
an array of storage cells configured into multiple banks;
interface circuitry to receive refresh commands from a host memory controller to refresh the multiple banks for a first refresh mode;
on-die refresh control circuitry to selectively generate local refresh commands to refresh the multiple banks in cooperation with the host memory controller during a designated hidden refresh interval in a second refresh mode;
mode register circuitry to store a value indicating whether the on-die refresh control circuitry is enabled for use during the second refresh mode; and
wherein the on-die refresh control circuitry is configured to generate a corrective action control signal in the second refresh mode to indicate a retry request for the host memory controller due to a failed operation caused by a collision between a memory request command to a given bank of the multiple banks and a hidden refresh operation to the given bank.