Patent ID: 11962679
Assignee: DUALITY TECHNOLOGIES, INC.
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. The system of claim 8, wherein one or more microprocessors are configured to: combine one or more of a plurality of partial encryption vectors b=Σjbj, wherein each partial encryption vector bj is generated at a jth one of the plurality of N parties and represents a partial encryption of 2irsj under the party's linear public key share pk; associated with the party's linear secret key share sj, generate a common encryption operator (a,b) that is based on the combined partial encryption vectors b and represents an encryption of 2irΣsj under the linear common public key pk associated with the linear common secret key Σsj, and combine one or more of a plurality of partial re-linearization operators (cj,dj) to generate a re-linearization key (c,d), wherein each of the plurality of partial re-linearization operators (cj,dj) is generated by each j of the plurality of N parties applying the linear secret key share sj to the common encryption operator (a,b), wherein each of the plurality of partial re-linearization operators (cj,dj) represents an encryption of 2irΣsj under the linear common public key pk associated with the linear common secret key Σsj; to generate the re-linearization key (c,d) represents encryptions of 2ir(Σsj)2 under the linear common public key pk associated with the linear common secret key Σsj.