Patent ID: 11869614
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A non-volatile memory (NVM) device, comprising:
a plurality of wordlines, each comprising a plurality of cells;
a hard decode configured to read each cell of the plurality of cells at a hard decode voltage;
a left read sense configured to read voltage values of each cell to the left of the hard decode voltage at a left read sense voltage;
a right read sense configured to read voltage values of each cell to the right of the hard decode voltage at a right read sense voltage;
a first adder for accumulating a plurality of voltage values of cells to the left of the hard decode voltage;
a second adder for accumulating a plurality of voltage values of cells to the right of the hard decode voltage;
a first combiner operating in additive mode to add the plurality of voltage values of cells to the left of the hard decode voltage and the plurality of voltage values of cells to the right of the hard decode voltage with an expectation constant to calculate a deviation output, wherein based on a value of the deviation output, an optimizing and tuning unit is configured to shift the left read sense voltage and the right read sense voltage as a pair; and
a second combiner operating in a subtractive mode to add the plurality of voltage values of cells to the left of the hard decode voltage and the plurality of voltage values of cells to the right of the hard decode voltage and subtract the expectation constant to calculate a dispersion output, wherein the expectation constant is an expected accumulation value of the plurality of voltage values of cells to the left of the hard decode voltage and the plurality of voltage values of cells to the right of the hard decode voltage.