Patent ID: 11903193
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. A method of forming a semiconductor device, the method comprising:
forming a first floating gate trench and a second floating gate trench in an upper portion of a substrate, wherein the first floating gate trench has a first depth and the second floating gate trench has a second depth that is different from the first depth;
forming a first tunnel dielectric layer on a bottom surface of the first floating gate trench and a second tunnel dielectric layer on a bottom surface of the second floating gate trench;
forming a first floating gate electrode in the first floating gate trench on the first tunnel dielectric layer and forming a second floating gate electrode in the second floating gate trench on the second tunnel dielectric layer;
forming a first control gate dielectric layer on the first floating gate electrode and forming a second control gate dielectric layer on the second floating gate electrode; and
forming a first control gate electrode on the first control gate dielectric layer and forming a second control gate electrode on the second control gate dielectric layer.