Patent ID: 11971826
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 15:
16. A non-volatile memory device, comprising:
an array of non-volatile memory comprising a plurality of planes;
an input-output interface configured to provide data to an external data bus;
a plurality of cache buffers each configured to data from a corresponding plane;
an internal data bus comprising a plurality of segments each configured to transfer data between a corresponding cache buffer and the corresponding cache buffer's corresponding plane;
one or more control circuits connected to the planes, input-output interface, cache buffers and internal data bus, the one or more control circuits comprising a plurality of compression circuits each configured to compress data from a corresponding one of the segments, the one or more control circuits configured, for each of the planes, to:
read and store in the corresponding cache buffer a page of hard bit data and corresponding soft bit data;
transfer the corresponding soft bit data over the corresponding segment from the corresponding cache buffer to the corresponding compression circuit;
compress the transferred soft bit data in the corresponding compression circuit;
transfer the compressed soft bit data over the corresponding segment from the corresponding compression circuit to the corresponding cache buffer; and
store the compressed soft bit data in the corresponding cache buffer,

where concurrently with one or both of transferring the soft bit data from the corresponding cache buffer to the corresponding compression circuit and transferring the compressed soft bit data over the corresponding segment from the corresponding compression circuit to the corresponding cache buffer for a first one of the planes, the one or more control circuits are configured to, for a second one of the planes, transfer data from the corresponding cache buffer over the corresponding segment.