Patent ID: 11916561
Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 10:
11. The clock generator of claim 10, wherein the 2-bit phase detector includes:
a first phase-detector configured to receive a replicated first first-level clock signal at an input of the first phase-detector, and a replicated first second-level clock signal at a clock input of the first phase-detector;
a second phase-detector configured to receive a replicated second first-level clock signal and the replicated first second-level clock signal at a clock input of the second phase-detector, wherein the second first-level clock signal is phase shifted from the first first-level clock signal by a time-margin;
wherein the first phase-detector is configured to produce a first phase-detector output indicative of a value of the first first-level clock signal; and
wherein the second phase-detector is configured to produce a second phase-detector output indicative of a value of the second first-level clock signal.