Patent ID: 11901034
Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device, comprising:
a plurality of memory planes;
a first pump set coupled with the plurality of memory planes, and configured to supply a first output voltage to a plurality of linear regulators during a steady phase;
a second pump set coupled with the plurality of memory planes, and configured to supply a second output voltage to the plurality of linear regulators during a ramping phase; and
a plurality of bidirectional switches each configured to alternatively connect a corresponding first linear regulator subset to the first pump set or the second pump set,
wherein the plurality of linear regulators includes:
a first linear regulator set configured to regulate the first output voltage or the second output voltage to generate a first voltage bias, and
a second linear regulator set configured to regulate the first output voltage or the second output voltage to generate a second voltage bias.