Patent ID: 11955421
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A method, comprising:
forming a plurality of transistors;
forming a first interlevel dielectric layer above the transistors and including a first region having a first dielectric constant a second region having a second dielectric constant greater than the first dielectric constant;
forming first metal signal lines in the first region of the first interlevel dielectric layer; and
forming a capacitor including a first electrode at least partially in the second region of the first interlevel dielectric layer and a second electrode at least partially in the second region of the first interlevel dielectric layer;
forming a second interlevel dielectric layer above the first interlevel dielectric layer and including a first region having the first dielectric constant and a second region having the second dielectric constant higher than the first dielectric constant; and
forming second metal lines in the first region of the second interlevel dielectric layer, wherein the first electrode is at least partially in the second region of the second interlevel dielectric layer, wherein the second electrode is at least partially in the second region of the second interlevel dielectric layer.