Patent ID: 11943921
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 18:
19. An integrated circuit (IC), comprising:
a substrate including a memory region;
a plurality of memory cell structures disposed on the memory region, wherein each of the memory cell structure of the plurality of memory cell structures comprises a pair of control gate electrodes respectively disposed over the substrate and a pair of select gate electrodes disposed on opposite sides of the pair of control gate electrodes;
source/drain regions on opposite sides of the pair of select gate electrodes within the memory region;
a contact etch stop layer (CESL) disposed along sidewalls of the plurality of memory cell structures and in direct contact with sidewalls of the pair of select gate electrodes and a select gate dielectric that separates the select gate electrodes from the substrate; and
a lower inter-layer dielectric layer disposed on the CESL, fill between and surrounding the plurality of memory cell structures.