Patent ID: 11895060
Assignee: QUALCOMM INCORPORATED
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An apparatus, comprising:
a processor; and
a memory coupled with the processor, wherein the memory comprises instructions executable by the processor to cause the apparatus to:
transmit, to a base station, a first indication of a switching latency for transitioning between a half-duplex mode that supports half-duplex communication and a full-duplex mode that supports full-duplex communication, wherein the first indication of the switching latency comprises a maximum latency associated with a plurality of pairs of beams, associated with the apparatus, that support full-duplex communication;
receive, from the base station in accordance with the first indication of the switching latency, a second indication that the apparatus is to transition to one of the half-duplex mode or the full-duplex mode; and
transition to the half-duplex mode or the full-duplex mode based at least in part on receiving the second indication.