Patent ID: 11876052
Assignee: SK HYNIX INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 4:
5. The semiconductor die bonding structure of claim 1, wherein the lower die further comprises:
a lower substrate;
a lower inter-layer dielectric layer over an active surface of the lower substrate; and
a lower wiring dielectric layer between the lower inter-layer dielectric layer and the lower top bonding dielectric layer,
wherein each of the lower connection structures further comprises:
a lower through-via structure vertically penetrating the lower substrate and the lower inter-layer dielectric layer;
a lower wiring via pad disposed over the lower inter-layer dielectric layer to contact an upper end of the lower through-via structure; and
a lower via, vertically penetrating the lower wiring dielectric layer to electrically connect the lower via pad to the lower top bonding pad structure of each of the lower connection structures.