Patent ID: 11908936
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. A semiconductor structure, comprising:
a gate electrode;
a semiconductor channel layer, wherein the semiconductor channel layer comprises:
a first alternating stack of first sublayers and second sublayers, the first sublayers having a different composition than the second sublayers,
a third sublayer over the first alternating stack of first and second sublayers, the third sublayer having a different composition than the first sublayers and the second sublayers, and
a second alternating stack of the first sublayers and the second sublayers over the third sublayer, wherein each of the first sublayers of the first alternating stack and the second alternating stack comprises a combination of a first metal oxide material, MOx, and a second metal oxide material, M′Ox, and each second sublayer of the first alternating stack and the second alternating stack comprises zinc oxide, and the third sublayer comprises a combination of a first metal oxide material, MOx, a second metal oxide material, M′ Ox, and zinc oxide, and wherein M is a first metal selected from a group consisting of indium (In) and tin (Sn) and combinations thereof, and M′ is a second metal selected from a group consisting of gallium (Ga), hafnium (Hf), zirconium (Zr), titanium (Ti), aluminum (Al), strontium (Sr), barium (Ba), scandium (Sc), magnesium (Mg), lanthanum (La), gadolinium (Gd), and combinations thereof;

a ferroelectric material layer located between the gate electrode and a surface of the semiconductor channel layer, wherein the ferroelectric material layer and the semiconductor channel layer have a same width dimension, and a width dimension of the gate electrode is less than the width dimensions of the ferroelectric material layer and the semiconductor channel layer; and
source and drain electrodes contacting the semiconductor channel layer.