Patent ID: 11908764
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor package comprising:
a circuit substrate having a first surface, a second surface opposite to the first surface and a cavity concave from the first surface, wherein the circuit substrate includes a dielectric material and a metal floor plate embedded in the dielectric material and located below the cavity, wherein the metal floor plate includes a plurality of metal plates, a location of the metal floor plate corresponds to a location of the cavity, both top and bottom surfaces of the metal floor plate are fully covered by the dielectric material, and the metal floor plate is electrically floating and isolated by the dielectric material;
a semiconductor die, disposed in the cavity and electrically connected with the circuit substrate; and
a filling material, disposed between the semiconductor die and the circuit substrate, wherein the filling material fills the cavity and encapsulates the semiconductor die to attach the semiconductor die and the circuit substrate.