Patent ID: 11914863
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A serial data buffer integrated circuit device comprising:
command scheduling logic to generate memory device commands for writing to and reading from a memory device based on command packets from a memory controller, the memory device commands including activate commands, read commands, and write commands scheduled to meet timing specifications of the memory device;
a unidirectional serial host side input port to receive the command packets and write data from the memory controller;
at least one unidirectional serial memory side output port to transmit the memory device commands and the write data to the memory device;
a unidirectional serial memory side input port to receive read data from the memory device in response to a read command; and
a unidirectional serial host side output port to transmit the read data to the memory controller.