Patent ID: 11861284
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. A method, comprising:
determining, by a processing device, a placement of components in an integrated circuit, wherein the components of the integrated circuit include all of Manhattan-routed conductors, diagonal-routed conductors, and at least one conductor that is neither Manhattan-routed nor diagonal-routed;
determining, by the processing device, a tree for each respective net in the integrated circuit based on the placement;
determining, by the processing device, a diagonal edge length for one or more diagonal edges in the trees;
determining the diagonal edge length for a respective diagonal edge is less than a threshold length and replacing the respective diagonal edge with a Manhattan edge;
determining, by the processing device, a number of conductor layers to be used for Manhattan routing of conductors, the determining comprising calculating a first ratio for Manhattan edges in the trees based on a total edge length of the Manhattan edges;
determining, by the processing device, a number of conductor layers to be used for diagonal routing of conductors, the determining comprising calculating a second ratio for diagonal edges in the trees based on a total edge length of the diagonal edges;
selecting, by the processing device, a conductor scheme for the integrated circuit based on the first and the second ratios, the conductor scheme; and
generating a layout of the integrated circuit.