Patent ID: 11908857
Assignee: GLOBALFOUNDRIES U.S. INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A structure comprising:
a first semiconductor fin including a top surface, a first cavity, a second cavity, and a third cavity laterally positioned between the first cavity and the second cavity;
a first gate structure and a second gate structure extending over the first semiconductor fin, the first gate structure adjacent to the second gate structure;
a first semiconductor layer including a first section in the first cavity and a second section in the second cavity, the first section of the first semiconductor layer laterally positioned between the third cavity and the first gate structure, and the second section of the first semiconductor layer laterally positioned between the third cavity and the second gate structure;
a shallow trench isolation region positioned in the first semiconductor fin adjacent to the second gate structure; and
a first isolation structure laterally positioned between the first section and the second section of the first semiconductor layer, the first isolation structure including a first dielectric layer and a first sidewall spacer, the first sidewall spacer having a first section and a second section, the first section and the second section of the first sidewall spacer positioned on the top surface of the first semiconductor fin, and the first dielectric layer including a first portion in the third cavity and a second portion between the first section and the second section of the first sidewall spacer,
wherein the first semiconductor fin includes a first portion laterally between the first cavity and the first portion of the first dielectric layer, the first semiconductor fin includes a second portion laterally between the second cavity and the second portion of the first dielectric layer, the second gate structure extends across a third portion of the first semiconductor fin, the third cavity extends to a depth relative to the top surface of the first semiconductor fin that is greater than the depth of the first cavity and the second cavity, and the second section of the first semiconductor layer, the second portion of the first semiconductor fin, and the third portion of the first semiconductor fin are positioned between the first isolation structure and the shallow trench isolation region.