Patent ID: 11966287
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. The memory device of claim 10, further comprising:
the partition coupled with the one or more processors and configured to store the error control information, wherein the one or more processors are further configured to cause the memory device to:
receive a command to write first data to the memory device;
determine whether to write the first data using the first error control mode or using the second error control mode;
write the first data and a third quantity of bits of the error control information to a first row of the plurality of rows based at least in part on receiving the command; and
write a fourth quantity of bits of the error control information to the partition storing the error control information based at least in part on determining to write the first data using the second error control mode, wherein determining to perform the scrub operation using the second error control mode is based at least in part on writing the fourth quantity of bits.