Patent ID: 11887887
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A method of fabricating an integrated circuit interconnect structure, the method
comprising:
preparing a first substrate, the preparing comprising:
forming a material layer stack comprising a first dielectric material layer and a second dielectric material layer on the first dielectric material layer, wherein the second
dielectric material layer comprises more nitrogen than the first dielectric material layer, and further comprises carbon;

forming a first opening in the material layer stack;
depositing a first conductive material in the first opening; and
forming a first interconnect feature by planarizing the first conductive material and an upper portion of the second dielectric material layer to form a first interconnect feature;

preparing a second substrate, the preparing comprising:
forming a second opening in a third dielectric material layer and an underlying fourth dielectric material layer, wherein the third dielectric material layer comprises more nitrogen than the fourth dielectric material layer, and further comprises carbon;
depositing a second conductive material in the second opening;
forming a second interconnect feature by planarizing the second conductive material and an upper portion of the third dielectric material layer;

reducing the carbon content of an uppermost portion of the second and fourth dielectric materials; and
bonding the first substrate with the second substrate by bringing into contact the first interconnect feature and the second interconnect feature.