Patent ID: 11934263
Assignee: AMPERE COMPUTING LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 3:
4. The memory control circuit of claim 3, wherein:
the first block comprises a first plurality of rows comprising:
a first number (N) of rows of bits of the first data portion;
a first row comprising the metadata bits; and
a first row comprising the parity bits; and

the second block comprises a second plurality of rows comprising:
a second N rows of bits of the second data portion;
a first row of ECC bits comprising the first ECC symbol; and
a second row of ECC bits comprising the second ECC symbol;

wherein:
the memory control circuit configured to demerge the merged second block based on the first block comprises the memory control circuit further configured to:
for each of the first N rows of bits of the first block, XOR the row of bits of the first block with a corresponding row of the second N rows of bits of the merged second block to generate a row of bits of the restored second block;
XOR the first row of ECC bits with the first row of the first block comprising the metadata bits to generate a row comprising a restored first ECC symbol; and
XOR the second row of ECC bits with the second row of the first block comprising the parity bits to generate a row comprising a restored second ECC symbol.