Patent ID: 11875043
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. A non-volatile memory device, comprising:
an array of non-volatile memory cells configured to store data in a multi-level cell format, comprising:
a plurality of word lines; and
a plurality of NAND strings each having a plurality of memory cells each with a control gate connected to a corresponding one of the word lines; and

one or more control circuits connected to the array and configured to write each of a plurality of non-volatile memory cells connected along a selected word line to a corresponding one of a plurality of target data states by performing a plurality of programming loops in each of which the one or more control circuits are configured to:
apply a programming pulse to the selected word line;
select one or more of a plurality of verify voltage levels;
based on a number of the one or more of the verify voltage levels selected, select a corresponding one of a plurality of delay times; and
subsequent to applying the programming pulse to the selected word line and selecting the corresponding one of the plurality of delay times, sequentially bias the selected word line to the selected one or more verify voltage levels after waiting the corresponding selected delay time.