Patent ID: 11941289
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 12:
13. A controller coupled via at least one data path to a memory device including a plurality of memory groups, each memory group including a plurality of non-volatile memory cells, wherein the controller comprises at least one processor and at least one memory including computer program code, wherein the at least one memory including the computer program code is configured, with the at least one processor, to cause the controller to:
transmit a command to the memory device for a data input/output operation;
perform the data input/output operation that changes data within at least one memory group in the memory device;
receive a response which is subject to the command and output from the memory device, the response including a result of the data input/output operation;
perform, based on the response, a second determination regarding whether the data input/output operation has succeeded or failed;
receive a status data, regarding the at least one memory group, output from the memory device in response to the data input/output operation, the status data including a current operation information, regarding the at least one memory group for which data was changed during the data input/output operation;
compare the status data with a physical to logical (P2L) map data item associated with the data input/output operation to perform a first determination regarding whether the data input/output operation has succeeded or failed;
determine whether the data input/output operation has succeeded or failed based on both the first determination and the second determination; and
update a logical to physical (L2P) map data item based on the P2L map data item according to the first determination and the second determination regarding whether the data input/output operation has succeeded or failed.