Patent ID: 11868804
Assignee: GROQ, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. A method, comprising:
receiving input instructions at an instruction buffer memory of an instruction dispatch circuit, the instruction dispatch circuit being configured to provide instructions to one or more computational arrays each comprising an array of computational elements arranged in a plurality of columns, each computational element adapted to perform a function on received data, and wherein the instruction buffer memory comprises a plurality of memory output locations connected to respective columns of the one or more computational arrays;
processing the input instructions received by the instruction buffer memory to generate a plurality of instructions for the one or more computational arrays; and
outputting each of the plurality of instructions to respective memory output locations of the plurality of memory output locations of the instruction memory buffer,
wherein computational elements of the one or more computational arrays execute instructions from the plurality of memory output locations on the received data, based upon a timing at which the instructions reach each computational element.