Patent ID: 11937301
Assignee: INTEL CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC H  Y | IPC H

Claim 17:
18. A wireless device comprising:
one or more processors coupled to an interface of a first wireless circuit operating in a first wireless communication network and to an interface of a second wireless circuit operating in a second wireless communication network, the one or more processors configured to:, perform a synchronization to allow the second wireless communication circuit of a wireless device to operatively coexist with the first wireless communication network scheduled in one or more wireless communication channels according to a time division multiplexing (TDM), wherein to perform the synchronization comprises the one or more processors to:, determine whether a network allocation vector (NAV) time for the one or more wireless communication channels is nonzero;
in response to the NAV time being nonzero grant, grant, to the second wireless communication network, use of the one or more wireless communication channels for use for a remainder of the NAV time;, in response to determining the NAV time being zero, perform a clear channel assessment (CCA) to determine whether the one or more wireless communication channels are busy; and, in response to determining the one or more wireless communication channels are busy by the performed CCA, grant, to the second communication network, use of the one or more channels wireless communication channels for a remainder of a back off (BO) time.