Patent ID: 11893241
Assignee: APPLE INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus, comprising:
a pipeline control circuit configured to initiate cache memory accesses for data;
a cache memory circuit having a data array arranged into a plurality of groups, wherein different ones of the plurality of groups have different minimum access latencies due to different distances from the pipeline control circuit; and
a plurality of latency control circuits configured to ensure a latency is bounded to a maximum value for a given access to the data array, wherein a given latency control circuit is associated with a corresponding group of the plurality of groups, and wherein a first latency control circuit is associated with a first of the plurality of groups and is configured to:
receive first data from first group;
receive second data from a second group that is more distant from the pipeline control circuit than the first group;
forward the second data rather than first data from the first group when both the first and second data are concurrently available; and
store the first data for forwarding at a later time.