Patent ID: 11962326
Assignee: ACCELERCOMM LIMITED
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An electronic device configured to perform a series of low density parity check, LDPC, decoding operations for a parity check matrix, PCM, derived from a basegraph selected from a set comprising at least one basegraph (200, 300) having a plurality of rows, the electronic device comprising:
a check node, CN, processor comprising two or more CN sub-processors, each CN sub-processor having one or more input-output (I-O) ports;
a controller, operably coupled to the CN processor and configured to activate a subset of the one or more I-O ports based on a current LDPC decoding sub-step of the LDPC decoding operations and the at least one basegraph;
two or more rotators, operably coupled to the controller that is configured to independently control an activation and a rotation of each rotator and configured to rotate an order of two or more soft bit values when activated in the LDPC decoding sub-step; and
an interconnection network, operably coupled to the controller and the CN processor and configured to support a connection of the one or more I-O ports to incomplete subsets of the two or more rotators;

wherein sub-steps in each LDPC decoding operation are grouped into a first set and a second set, and wherein:
in each sub-step, the controller is configured to activate a subset of the two or more rotators corresponding to a subset of the two or more columns that have a binary value of ‘1’ in the row(s) of the at least one basegraph; and activate connections within the interconnection network to connect the activated rotators to corresponding I-O ports of the CN sub-processors;

wherein the CN processor is configured to support at least two modes of operation:
a first mode of operation whereby each CN sub-processor is configured in a single LDPC decoding operation to perform LDPC decoding computations for two rows of the PCM that are derived from different orthogonal rows of the plurality of rows in the at least one basegraph;
a second mode of operation whereby two or more of the CN sub-processors are configured in a single LDPC decoding operation to co-operate to perform LDPC decoding computations for two rows of the PCM that are derived from a single row in the at least one basegraph.