Patent ID: 11917837
Assignee: WINBOND ELECTRONICS CORP.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 0:
1. A method of forming a semiconductor device, comprising:
forming a first conductive line over a substrate;
forming a memory structure over the first conductive line, and the memory structure is electrically connected to the first conductive line through a conductive via;
forming a sacrificial layer on the memory structure;
forming a spacer layer to cover a sidewall of the memory structure, and a sidewall and a top surface of the sacrificial layer;
forming a first dielectric layer to cover the spacer layer;
performing a planarization process to at least remove a portion of the first dielectric layer over a topmost surface of the spacer layer;
forming a second dielectric layer on the spacer layer and the first dielectric layer;
performing a patterning process to form an opening at least penetrating through the second dielectric layer, and the opening exposes a portion of the top surface of the sacrificial layer;
removing the sacrificial layer to form a recess; and
forming a second conductive line in the opening and the recess to be electrically coupled to the memory structure.