Patent ID: 11894064
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. An apparatus, comprising:
a block including a plurality of memory cells arranged in a plurality of data word lines, the plurality of data word lines being arranged in a plurality of sub-blocks which are not separated from one another by physical joints or by dummy word lines;
an erasing means for erasing the memory cells of a selected sub-block of the plurality of sub-blocks without erasing the memory cells of the unselected sub-blocks, the erasing means being further configured to:
read data of at least one edge word line of at least one unselected sub-block;
store the data in a temporary location external of the block;
erase the memory cells of the selected sub-block; and
re-program the data to the memory cells of the at least one edge word line.