Patent ID: 11913121
Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC C  H  Y | IPC C  H

Claim 0:
1. A method for fabricating a substrate having an electrical interconnection structure, the method comprising:
forming a passivation layer on a substrate body having a plurality of conductive pads and forming a plurality of first openings in the passivation layer for exposing at least a portion of each of the conductive pads;
forming a seed layer on the passivation layer and the conductive pads;
forming a first metal layer on a portion of the seed layer, wherein the portion of the seed layer is positioned between the first metal layer and the corresponding conductive pads and between the first metal layer and the passivation layer, wherein the first metal layer has an extending portion;
forming a second metal layer on the first metal layer, wherein the second metal layer is free from covering the extending portion of the first metal layer; and
removing the seed layer under the extending portion, and removing the extending portion of the first metal layer while removing the seed layer under the extending portion.