Patent ID: 11870399
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A receiver for receiving an input signal and outputting an internal signal that is a digital signal corresponding to bits of the input signal,
the receiver comprising:
a first amplifier circuit configured to amplify a voltage difference between a voltage level of the input signal and a level of a reference voltage to output a first output signal to a first node line and output a second output signal to a second node line;
a second amplifier circuit configured to amplify a voltage difference between the first output signal and the second output signal to output fifth and sixth output signals, the second amplifier circuit being connected to the first node line and the second node line;
a level conversion circuit configured to amplify a first swing width of the fifth and sixth output signals to a second swing width greater than the first swing width and generate the internal signal;
a first equalizer circuit configured to receive the input signal, amplify the voltage difference between the voltage level of the input signal and the level of the reference voltage to generate third and fourth output signals, generate an average voltage level of the third output signal through a first switching element in response to a control signal to output the average voltage level of the third output signal as a first feedback signal, generate an average voltage level of the fourth output signal through a second switching element in response to the control signal to output the average voltage level of the fourth output signal as a second feedback signal, and adjust the voltage difference between the first output signal and the second output signal based on a voltage difference between the first feedback signal and the second feedback signal; and
a control circuit configured to output the control signal of a pulse type whenever a logic level of the internal signal transitions, wherein the first and second switching elements are selectively turned on or off according to a logic pulse level of the control signal.