Patent ID: 11957065
Assignee: 1372934 B.C. LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. A method for fabricating a superconducting integrated circuit, the method comprising:
determining a target resolution of interlayer misalignment to be electrically detectable in the superconducting integrated circuit via a measurement of resistance of portions of the superconducting integrated circuit;
determining a set of dimensions for each of a number of verniers to be formed in the superconducting integrated circuit based at least in part on the determined target resolution of interlayer misalignment to be electrically detectable in the superconducting integrated circuit via a measurement of resistance of portions of the superconducting integrated circuit;
fabricating the superconducting integrated circuit; and
measuring a resistance of portions of the fabricated superconducting integrated circuit.