Patent ID: 11961877
Assignee: KEPLER COMPUTING INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 14:
15. A system comprising:
a processor;
a communication interface communicatively coupled to the processor; and
a memory coupled to the processor, wherein the memory comprises: bit-cells, wherein one of the bit-cells includes:
a first region comprising:
a first conductive interconnect within a first dielectric in a first level;
a second level above the first level, the second level comprising:
an electrode structure on the first conductive interconnect, the electrode structure comprising:
 a first conductive hydrogen barrier layer; and
 a first conductive fill material on the first conductive hydrogen barrier layer, wherein the electrode structure comprises a first lateral thickness;
an etch stop layer comprising an insulator, the etch stop layer laterally surrounding the electrode structure;
a second dielectric on the etch stop layer, the second dielectric comprising an amorphous, greater than 90% film density hydrogen barrier material;
a trench within the second dielectric, the trench on the electrode structure;
a memory device within the trench, the memory device comprising:
 a first electrode along a base and a sidewall of the trench, wherein the first electrode is in contact with the electrode structure;
 a dielectric layer comprising a ferroelectric material or a paraelectric material substantially conformal to the first electrode; and
 a second electrode in contact with the dielectric layer; and
a via electrode on the second electrode, the via electrode comprising:
 a second conductive hydrogen barrier layer comprising a lateral portion in contact with the second electrode and substantially vertical portions connected to the lateral portion; and
 a second conductive fill material adjacent to the second conductive hydrogen barrier layer; and

a second region adjacent to the first region, the second region comprising:
a second conductive interconnect within the first level; and
a third dielectric on the etch stop layer, the third dielectric directly adjacent to the second dielectric, wherein the third dielectric comprises a less than 90% film density material; and
a via structure on the second conductive interconnect, the via structure laterally in contact with the third dielectric.