Patent ID: 11928329
Assignee: NXP B.V.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. The IC of claim 10, wherein the logic circuit of the first set of logic circuits further comprises:
a first logic gate that is coupled to the address decoder, and configured to receive the second control bit and the first mask bit, and output a second select bit based on the second control bit and the first mask bit, wherein the second select bit has the first logic state when the first mask bit and the second control bit have the first logic state, and the second select bit has the second logic state when at least one of a group consisting of the first mask bit and the second control bit has the second logic state; and
a second logic gate that is coupled to the address decoder, the first logic gate, and the first multiplexer, and configured to (i) receive the first control bit and the second select bit, (ii) output the first select bit based on the first control bit and the second select bit, and (iii) provide the first select bit to the first multiplexer, wherein the first select bit has the second logic state when the first control bit and the second select bit have the second logic state, and the first select bit has the first logic state when at least one of a group consisting of the first control bit and the second select bit has the first logic state.