Patent ID: 11875183
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 11:
12. A method comprising:
determining, by a first processor, to access a computing resource, wherein:
the first processor is coupled to an interconnect by a first interface;
the first processor is further coupled to the interconnect by a broadside interface;
the broadside interface is coupled to a spinlock circuit;
the spinlock circuit is coupled to the interconnect by a third interface;
the computing resource is coupled to the interconnect by a second interface; and
the access of the computing resource by the first process uses the broadside interface and the second interface:

receiving, at the spinlock circuit, a first request from the first processor for use of the computing resource, through the broadside interface;
determining, by a second processor coupled to the interconnect by a fourth interface and further coupled to the interconnect by the broadside interface, to access the computing resource using the broadside interface;
receiving, at the spinlock circuit, a second request from the second processor for use of the computing resource, through the broadside interface;
determining, by the spinlock circuit, an availability of the computing resource based on a flag associated with the computing resource;
arbitrating, by the spinlock circuit, use of the computing resource between the first and second processors;
transmitting, using the spinlock circuit, the availability of the computing resource to each of the first and second processors through the broadside interface;
configuring, by a first task manager, a respective processor not assigned to the computing resource to trigger processing of a respective high priority task using the computing resource based on the spinlock circuit granting access to the computing resource in response to the flag being reset;
configuring, by the first task manager, the respective processor to process a respective low priority task until the processing of the respective high priority task is triggered;
preempting, by the first task manager, processing of the respective low priority task by the respective processor to process the respective high priority task in response to the processing of the respective high priority task being triggered; and
resetting, by the spinlock circuit, the flag upon completion of an event associated with the computing resource, wherein the broadside interface is separate from the first interface, the second interface, the third interface, and the fourth interface.