Patent ID: 11954360
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. A computing system comprising:
a memory controller including a plurality of linear feedback shift registers (LFSRs) corresponding to a data word;
a link coupled to the plurality of LFSRs;
a memory structure coupled to the memory controller, the memory structure including a set of instructions, which when executed by the memory controller, cause the memory controller to:
program a plurality of seed values into the plurality of LFSRs, wherein at least two of the plurality of seed values differ from one another, and wherein each of the plurality of seed values differ from one another and are automatically selected to each differ from one another based on one or more of an expected traffic pattern on a link coupled to the plurality of LFSRs or a deskew constraint associated with the link; and
train the link coupled to the plurality of LFSRs.