Patent ID: 11928768
Assignee: IMAGINATION TECHNOLOGIES LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 4:
5. The method according to claim 4, wherein tessellating the selected sub-patch until there is no further sub-division comprises:
analysing the selected sub-patch to determine whether to sub-divide the selected sub-patch;
in response to determining that the selected sub-patch is to be sub-divided, dividing the selected sub-patch into a left sub-patch and a right sub-patch;
selecting one of the left and right sub-patches formed by sub-division of the selected sub-patch based on one or more stored values;
first, tessellating the selected sub-patch until there is no further sub-division; and
then, tessellating the non-selected sub-patch until there is no further sub-division;, and wherein tessellating the non-selected sub-patch until there is no further sub-division comprises:
analysing the non-selected sub-patch to determine whether to sub-divide the non-selected sub-patch;
in response to determining that the non-selected sub-patch is to be sub-divided, dividing the non-selected sub-patch into a left sub-patch and a right sub-patch;
selecting one of the left and right sub-patches formed by sub-division of the non-selected sub-patch based on one or more stored values;
first, tessellating the selected sub-patch until there is no further sub-division; and
then, tessellating the non-selected sub-patch until there is no further sub-division.