Patent ID: 11955195
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H  B | IPC G

Claim 0:
1. A semiconductor memory device, comprising:
a substrate that comprises a memory cell region and a test region;
an active pattern on the memory cell region;
a source/drain pattern on the active pattern;
a dummy pattern on the test region;
a first gate electrode that extends in a first direction on the dummy pattern;
a first common contact in contact with the dummy pattern and the first gate electrode; and
a first wiring layer on the first common contact,
wherein the first wiring layer comprises a first test line electrically connected to the first common contact,
wherein the first common contact comprises:
a first contact pattern in contact with the dummy pattern; and
a first gate contact electrically connected to the first gate electrode,

wherein the first gate contact comprises:
a body part coupled to the first gate electrode; and
a protrusion part that extends from the body part and into the first contact pattern, and

wherein a lowermost level of a top surface of the active pattern is lower than a lowermost level of a top surface of the dummy pattern.