Patent ID: 11948917
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. A method, comprising:
disposing a first plurality of dies on a panel substrate, each of the first plurality of dies aligned with other dies of the first plurality of dies, and each of the plurality of first dies having a first sidewall laterally opposite a second sidewall, the substrate having a first outermost sidewall laterally opposite a second outermost sidewall;
encapsulating the first plurality of dies on the panel substrate in a first molding compound, the first molding compound in contact with the first sidewall and the second sidewall of each of the plurality of first dies, and the first molding compound having a first outermost sidewall and a second outermost sidewall, the second outermost sidewall laterally opposite the first outermost sidewall, and the first outermost sidewall of the first molding compound in vertical alignment with the first outermost sidewall of the substrate;
disposing a second plurality of dies on the first molding compound, each of the second plurality of dies aligned with other dies of the second plurality of dies, wherein a bottommost one of the second plurality of dies has a portion that extends laterally beyond the second outermost sidewall of the first molding compound, wherein the portion of the bottommost one of the second plurality of dies is electrically coupled to the panel substrate; and
encapsulating the second plurality of dies and the first molding compound in a second molding compound.