Patent ID: 11894262
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of fabricating an integrated circuit, the method comprising:
removing at least a portion of a substrate from a back side of an integrated circuit structure, the integrated circuit structure comprising a number of non-planar transistor devices on a front side of the integrated circuit structure, at least some of the transistor devices including a source region, a drain region, and a gate structure, the integrated circuit structure including a plurality of semiconducting fins extending from substrate, the fins being at least part of the transistor devices on the front side of the integrated circuit structure and including a first semiconductor fin and a second semiconductor fin, wherein the removing is carried out after formation of source and drain regions;
recessing, from the back side of the integrated circuit structure, isolation material between the first and second semiconductor fins to expose a sub-channel portion of the first semiconductor fin and a sub-channel portion the second semiconductor fin;
depositing a spacer material around the sub-channel portion of each of the first and second semiconductor fins; and
further recessing, from the back side integrated circuit structure, isolation material to form an air gap between the source region of the first semiconductor fin and the source region of the second semiconductor fin, and between the drain region of the first semiconductor fin and the drain region of the second semiconductor fin.