Patent ID: 11972111
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 1:
2. The memory device of claim 1, wherein the control logic is configured to perform the first even sensing, the second even sensing, the first odd sensing, and the second odd sensing such that
the first even sensing is performed on the even-numbered bit lines at a first time after a first bit line of the plurality of bit lines is completely precharged,
the second even sensing is performed on the even-numbered bit lines at a second time later than the first time,
the first odd sensing is performed on the odd-numbered bit lines at the second time after the first bit line is completely precharged, and
the second odd sensing is performed on the odd-numbered bit lines at a third time later than the second time.