Patent ID: 11880682
Assignee: AMAZON TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 4:
5. A systolic circuit comprising:
a group of processing elements arranged into a plurality of rows; and
a first convertor configured to:
receive a first input represented in floating-point with a first bit-length;
identify a quantity of trailing bits of the first input based on a difference between the first bit-length and a bit-length supported by the group of processing elements;
reduce the quantity of trailing bits of the first input; and
generate a first reduced input represented in floating-point with a second bit-length based on reducing the quantity of trailing bits of the first input, wherein the second bit-length is less than the first bit-length, wherein the second bit-length corresponds to a bit-length supported by the group of processing elements;

wherein an individual processing element in at least one row of the group of processing elements is configured to receive the first reduced input from the first convertor and to receive a second input for performing multiply-accumulate operations.