Patent ID: 11900146
Assignee: APPLE INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus comprising:
a plurality of agents;
a memory controller configured to receive real-time and non-real-time memory requests from ones of the plurality of agents, wherein the memory controller having a plurality of transaction tables that includes:
a real-time transaction table configured to store those memory requests, received from a subset of the plurality of agents, that are real-time memory requests;
a non-real-time transaction table configured to store those memory requests, received from the subset of the plurality of agents, that are non-real-time memory requests;
one or more additional transaction tables, wherein a given one of the one or more additional transaction tables is configured to store memory requests initiated by a corresponding processing circuit; and
wherein the memory controller further includes an arbitration circuit configured to select a memory request from among memory requests stored in the real-time and non-real-time transaction tables and further configured to enforce a quality of service policy for the real-time memory requests, wherein the arbitration circuit is configured to perform a credit-based arbitration, wherein the non-real-time transaction table and the additional transaction tables share a pool of credits, and wherein the real-time transaction table does not share credits with other ones of the plurality of transaction tables;
wherein the memory controller is configured to, in response to the arbitration circuit selecting a particular memory request, execute the particular memory request in a memory pipeline.