Patent ID: 11954045
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. A method comprising:
receiving a first request to perform a memory access operation for an address range in a memory allocation containing data or code, wherein the memory allocation is contained in one cacheline of memory;
identifying a first portion of the cacheline, wherein the first portion of the cacheline includes at least a first address of the address range and is identified based at least in part on a first data bounds value stored in a metadata region located within the cacheline;
identifying a second portion of the cacheline, wherein the second portion of the cacheline includes at least a second address of the address range and is identified based at least in part on a second data bounds value stored in the metadata region located within the cacheline;
generating a first integrity value based on at least the first portion of the cacheline and the second portion of the cacheline; and
allowing the memory access operation to continue based on the first integrity value corresponding to a second integrity value stored in the metadata region.