Patent ID: 11966628
Assignee: MACRONIX INTERNATIONAL CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 8:
9. An operating method of a memory device, wherein the memory device includes a memory array and a plurality of data latches, the memory array includes a plurality of memory units each having a first bit and a second bit, and the data latches include a first data latch, a second data latch and a common data latch, and the operating method comprising:
storing a plurality of vector data in the memory array, the vector data at least include an input feature vector and an output feature vector, and each vector data has an MSB vector and a LSB vector;
storing the MSB vector of each vector data in the first bit;
storing the LSB vector of each vector data in the second bit;
executing one time of bit-line-setup for a bit line corresponding to each vector data;
reading the MSB vector and the LSB vector of each vector data according to the bit line;
receiving the input feature vector from the memory device externally, by the common data latch;
transferring the input feature vector from the common data latch, and then temporarily storing the input feature vector to the first data latch;
executing a selective bit line read operation based on the input feature vector in the first data latch to read the MSB vector and the LSB vector of the input feature vector according to the corresponding bit line which have been performed with the bit-line-setup, by the memory device, so as to obtain the output feature vector; and
temporarily storing the output feature vector in the second data latch;
wherein the threshold voltage distribution of each memory unit is divided into N states, N is a positive integer and N is less than 2 to the power of 2, and the effective bit number stored by each memory unit is less than 2.