Patent ID: 11955995
Assignee: INTEL CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. An apparatus comprising:
a first lossless data compressor circuitry coupled to receive input data, the first lossless data compressor circuitry to apply a first lossless data compression approach to compress the input data to generate intermediate compressed data, wherein the first lossless data compression approach is a zero compress approach, wherein the first lossless data compressor circuitry to apply the first lossless data compression approach to the input data is to generate a bitmask and a concatenated sequence of non-zero-valued elements in the input data, the bitmask to indicate which elements of the input data are zero-valued elements and which are the non-zero-valued elements; and
a second lossless data compressor circuitry coupled with the first lossless data compressor circuitry to receive the intermediate compressed data, the second lossless data compressor circuitry to apply a second lossless data compression approach to compress at least some of the intermediate compressed data to generate compressed data, the second lossless data compression approach different than the first lossless data compression approach, wherein the second lossless data compressor circuitry is to apply the second lossless data compression approach to compress the concatenated sequence of the non-zero-valued elements but not the bitmask.