Patent ID: 11902414
Assignee: HUAWEI TECHNOLOGIES CO., LTD.
Field: Digital communication (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 3:
4. The method of claim 1, further comprising:
multiplying the polynomial matrix by a second Keyswitch matrix to generate a second intermediate polynomial matrix;
summing a last row of the second intermediate polynomial matrix to generate a second early-summation element and performing a modular reduction on the second early-summation element to generate a second early-summation vector;
summing remaining rows of the second intermediate polynomial matrix to generate a second summation vector; and
subtracting the second early-summation vector from the second summation vector to generate a second subtraction-result vector;
multiplying the second subtraction-result vector by an inverse moduli vector to generate a second result vector; and
outputting from the FPGA cluster the second result vector.