Patent ID: 11954340
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. An operation method of a memory controller which controls an external nonvolatile memory device including a plurality of nonvolatile memories connected with a plurality of data lines, the method comprising:
transmitting a chip address initialization command through the plurality of data lines to the external nonvolatile memory device in synchronization with a write enable signal;
transferring a first chip address through the plurality of data lines in synchronization with the write enable signal; and
initializing a chip address of a first memory of the plurality of nonvolatile memories based on the first chip address,
wherein a next chip address of each next memory of the plurality of nonvolatile memories is sequentially initialized based on an incremented chip address generated and transmitted from a previous memory of the plurality of nonvolatile memories when a transition of the next enable signal is center-aligned with a window of the next chip address, respectively.