Patent ID: 11948877
Assignee: QUALCOMM INCORPORATED
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. A package comprising:
a die;
a first substrate structure comprising:
at least one substrate dielectric layer; and
a plurality of substrate interconnects;

a first metallization structure at least partially coplanar with the first substrate structure on a horizontal plane,
wherein the first substrate structure is surrounded by the first metallization structure, and
wherein the first metallization structure comprises:
at least one first dielectric layer; and
a first plurality of interconnects;

a plurality of metal interconnects coupled to and touching the first plurality of interconnects of the first metallization structure;
a first mold, wherein the first metallization structure and the first substrate structure are at least partially separated by the first mold; and
a portion coupled to and touching the plurality of metal interconnects and the plurality of substrate interconnects, wherein the portion comprises:
at least one portion dielectric layer; and
a plurality of portion interconnects;

a second metallization structure, configured to be electrically coupled to the die, the first substrate structure, and the first metallization structure,
wherein the second metallization structure touches the first metallization structure and the first substrate structure,
wherein the second metallization structure comprises:
at least one second dielectric layer; and
a second plurality of second interconnects, and

wherein the die is configured to be (i) electrically coupled to the first metallization structure through the second metallization structure, and (ii) electrically coupled to the first substrate structure through the second metallization structure,
wherein the first metallization structure is configured to provide an electrical path for data signaling,
wherein the second metallization structure is configured to be coupled to a ground signal,
wherein the first substrate structure is configured to provide an electrical path for power,
wherein a first electrical path between the die and the portion includes (i) at least one interconnect from the second plurality of interconnects, (ii) at least one substrate interconnect from the plurality of substrate interconnects and (iii) at least one portion interconnect from the plurality of portion interconnects, and
wherein at least part of the first electrical path between the die and the portion extends through a first side of the first substrate structure and through a second side of the first substrate structure.