Patent ID: 11928027
Assignee: CADENCE DESIGN SYSTEMS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A method comprising:
receiving a plurality of fixed size error checking and correction data blocks and metadata at a DDR memory controller;
performing data to symbol mapping based upon, at least in part, the plurality of fixed size data blocks;
providing an output of the data to symbol mapping to a first RSECC encoder without metadata configured for full detection correction of single device error and to a second RSECC encoder with metadata configured for partial detection correction of single device error;
receiving data at a memory based upon, at least in part, an output from the first RSECC encoder and the second RSECC encoder;
receiving data from the memory at a first RSECC decoder without metadata configured for full detection correction of single device error and at a second RSECC decoder with metadata configured for partial detection correction;
re-mapping symbol data from the first RSECC decoder and the second RSECC decoder to actual data; and
generating a plurality of output data blocks and metadata.