Patent ID: 11903197
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 15:
16. A semiconductor device comprising:
gate electrodes spaced apart from each other on a substrate and stacked in a direction perpendicular to an upper surface of the substrate; and
channel structures that extend through the gate electrodes,
wherein ones of the channel structures comprise a channel insulating layer, a pad layer on the channel insulating layer, and a channel layer on a side surface of the channel insulating layer and on at least a portion of a side surface of the pad layer,
wherein the channel layer comprises a first channel region on the side surface of the channel insulating layer, and a second channel region on the first channel region,
wherein the second channel region is adjacent to a first erase gate electrode that is a farthest one of the gate electrodes from the substrate,
wherein the second channel region overlaps at least a portion of the side surface of the pad layer,
wherein the second channel region comprises a semiconductor material doped with a first conductivity type impurity, the first channel region comprises a semiconductor material having an impurity concentration lower than an impurity concentration in the second channel region, and the pad layer comprises a semiconductor material doped with a second conductivity type impurity that is different from the first conductivity type impurity, and
wherein the second channel region and the pad layer are configured to form a P-N junction therebetween.