Patent ID: 11901349
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A method for forming a semiconductor package, comprising:
providing a plurality of first integrated circuit dies each having a first circuit design, wherein each first integrated circuit die comprises a first device layer and a first interconnect structure;
providing a second integrated circuit die onto a wafer, wherein the second integrated circuit die has a second circuit design different than the first circuit design, and the second integrated circuit die comprises a second device layer and a second interconnect structure;
bonding the second integrated circuit die with the plurality of first integrated circuit dies so that a first side of the second interconnect structure is in contact with the second device layer and a second side is in direct contact with the first interconnect structure of the first integrated circuit die;
cutting the wafer into individual pieces each having at least one first integrated circuit die bonded to the second integrated circuit die; and
bonding a substrate to the second integrated circuit die such that the first integrated circuit die is surrounded by at least a portion of the substrate, wherein the substrate has an opening extending through the entire thickness of the substrate, wherein the opening is sized to allow the circumference of the first integrated circuit die in the opening.