Patent ID: 11862271
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A method, comprising:
selecting a row in an array of bitcells for error correction;
writing a first array of data bits to the row and then reading a second array of data bits from the row;
performing a first row error check on the row by comparing the first array of data bits to the second array of data bits and increasing a row error count based on identifying errors between the first array of data bits and the second array of data bits;
writing a third array of data bits to the row and then reading a fourth array of data bits from the row; and
performing a second row error check on the row that is different than the first row error check on the row by comparing the third array of data bits to the fourth array of data bits and increasing the row error count based on identifying errors between the third array of data bits and the fourth array of data bits,
wherein the third array of data bits is a complement or an inverse of the first array of data bits.