Patent ID: 11925033
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A method comprising:
forming a transistor on a first substrate, wherein the first substrate is a silicon-on-insulator (SOI) substrate comprising an active layer, a base layer, and an insulator layer between the active and base layers;
forming an interconnect structure overlying and electrically coupled to the transistor on a frontside of the transistor;
bonding the first substrate to a second substrate, such that the transistor and the interconnect structure are between the first and second substrates;
removing the first substrate from a backside of the transistor, which is opposite the frontside of the transistor, wherein the removing comprises:
a chemical mechanical polish (CMP) to partially remove the first substrate; and
performing an etch into a remainder of the first substrate after the CMP to remove the remainder of the first substrate; and

forming a memory cell overlying and electrically coupled to a source or drain of the transistor on the backside of the transistors;
wherein the CMP removes the base layer and the insulator layer and the etch removes the active layer.