Patent ID: 11948650
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. The testing circuit of claim 7, wherein the second sampling module further comprises a fourth inverter and a fifth inverter,
wherein an input terminal of the transmission gate is connected the to-be-tested pulse signal, an output terminal of the transmission gate is connected with a drive terminal of the second temporary storage unit, and the transmission gate is configured to transmit the to-be-tested pulse signal to the second temporary storage unit;
an input terminal of the second temporary storage unit is connected with an output terminal of the fourth inverter, and the second temporary storage unit is configured to, in response to the to-be-tested pulse signal, sample a signal output by the fourth inverter so as to generate a second temporary storage signal, an edge of the second temporary signal corresponding to a second edge of the to-be-tested pulse signal;
the fourth inverter is configured to invert the second temporary signal so as to generate a second feedback signal; and
an input terminal of the fifth inverter is connected with an output terminal of the fourth inverter, and the fifth inverter is configured to receive the second feedback signal, and generate the second sampled signal according to the second feedback signal.