Patent ID: 11942131
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. A processing apparatus comprising:
a bit-cell array comprising at least one bit-cell line including a plurality of bit-cells electrically connected to each other in series,
wherein each of the plurality of bit-cells comprises:
a first magnetic resistor comprising a pinned layer having a magnetization direction thereof pinned, a free layer comprising a magnetic domain-wall and a first region having an identical magnetization direction to the pinned layer and a second region having a different magnetization direction from the pinned layer, and a tunnel layer between the pinned layer and the free layer, wherein the first magnetic resistor is configured to store a first resistance value based on a movement of a location of the magnetic domain-wall;
a second magnetic resistor that is configured to store a second resistance value that is equal to or less than the first resistance value;
a first switching element configured to switch an electrical signal applied to the first magnetic resistor; and
a second switching element configured to switch an electrical signal applied to the second magnetic resistor,
wherein the bit-cell array comprises:
a fourth switching element electrically connected to the first magnetic resistor and the second magnetic resistor; and
a fifth switching element electrically connected to the first switching element and the second switching element, and electrically connected to a different data line from a data line to which the fourth switching element is electrically connected.