Patent ID: 11864373
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A semiconductor structure, comprising:
a substrate, the substrate comprising a core region, and a peripheral region located outside the core region and adjacent to the core region, and an active area being further arranged in the substrate;
a first barrier layer arranged on the substrate, covering at least the core region;
a dielectric layer arranged on the substrate and a part of the first barrier layer; and
a first conductive layer arranged on the dielectric layer, wherein an orthographic projection of the dielectric layer on the substrate partially overlaps an orthographic projection of the first barrier layer on the substrate to form an overlapped region, and a width of the overlapped region is in a range of 20 nm to 100 nm.