Patent ID: 11899615
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 16:
17. A processor comprising:
a plurality of dies including a first die and a plurality of other dies, each of the plurality of dies comprising a corresponding intra-die interconnect;
a plurality of secondary management controllers, each secondary management controller integral to a corresponding one of the plurality of other dies;
an inter-die interconnect coupled to the intra-die interconnects of the plurality of dies; and
a primary management controller integral to the first die to transmit one or more management requests to the plurality of secondary management controllers over the intra-die interconnects and the inter-die interconnect, the plurality of secondary management controllers to perform a modification to a clock of the corresponding one of the plurality of other dies based, at least in part, on the one or more management requests.