Patent ID: 11894459
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 5:
6. A method, comprising:
forming a channel region and a drift region;
depositing a gate dielectric layer on top surfaces of the channel region and the drift region;
forming a first gate structure on a top surface of the gate dielectric layer and over the channel and drift regions;
forming a second gate structure on the top surface of the gate dielectric layer and over the drift region;
etching the gate dielectric layer to form:
a continuous layer under the first and second gate structures,
a first sidewall of the gate dielectric layer aligned with an outer sidewall of the first gate structure, and
a second sidewall of the gate dielectric layer aligned with an outer sidewall of the second gate structure, wherein the outer sidewalls of the first and second gate structures face opposite to each other;
forming a first outer spacer on a first outer sidewall of the first gate structure and in physical contact with the top surface of the channel region;
forming a second outer spacer on a second outer sidewall of the second gate structure and in physical contact with the top surface of the drift region;
forming an inner spacer in contact with an inner sidewall of the first gate structure and an inner sidewall of the second gate structure;
removing the first gate structure to expose the top surface of the gate dielectric layer; and
forming a metal gate structure with a bottom surface directly on the top surface of the gate dielectric layer and with a sidewall in physical contact with the first outer spacer.