Patent ID: 11972136
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A method of operating a solid-state device, the solid-state device including a memory controller and a plurality of three-dimensional NAND flash memory chips each including a memory cell array including three-dimensional memory cells, the method comprising:
receiving temperature information including a plurality of entries through an NVMe protocol from a host, the plurality of entries including a first entry and a second entry, wherein the first entry includes a first temperature defined by the host and first temperature-dependent performance level information defined by the host and corresponding to the first temperature, and the second entry includes a second temperature defined by the host and second temperature-dependent performance level information defined by the host and corresponding to the second temperature, wherein the second temperature is greater than the first temperature;
detecting an internal temperature of the solid-state device;
performing a first throttling operation to cause the solid-state device to operate at a first performance level corresponding to the first temperature-dependent performance level information defined by the host when the detected internal temperature becomes greater than the first temperature and remains lower than the second temperature as the internal temperature increases; and
performing a second throttling operation to cause the solid-state device to operate at a second performance level corresponding to the second temperature-dependent performance level information defined by the host that is less than the first performance level when the detected internal temperature becomes greater than the second temperature as the internal temperature increases,
wherein the memory controller is further configured to automatically perform the first throttling operation and the second throttling operation based on the detected internal temperature and according to the temperature information received from the host without intervention from the host,
wherein the second performance level has a level that causes the internal temperature to be lowered below the second temperature included in the second entry, and
wherein the first and second performance levels are less than a normal performance level.