Patent ID: 11929663
Assignee: RENESAS ELECTRONICS AMERICA INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 18:
19. An apparatus comprising:
a first capacitor that is configured to alternately charge from a power source based at least in part on a first portion of a clock signal and to discharge to a bias voltage output of a power management integrated circuit based at least in part on a second portion of the clock signal;
a second capacitor that is configured to alternately charge from the power source based at least in part on the second portion of the clock signal and to discharge to the bias voltage output of the power management integrated circuit based at least in part on the second portion of the clock signal; and
a self-biased switch disposed between the output of the charge pump and the output of the voltage regulator, the self-biased switch being configured to switch between outputting the second output and having a high output impedance.