Patent ID: 11922058
Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. A method of operating a three-dimensional (3D) memory device comprising an array of 3D NAND memory cells and a device layer comprising a plurality of transistors, wherein:
an array of static random-access memory (SRAM) cells comprises a first portion of the plurality of transistors of the device layer, and a controller comprises a second portion of the plurality of transistors; and
the array of 3D NAND memory cells, the array of SRAM cells, and the controller are arranged on a same chip, the method comprising:
buffering, through the controller, data in the array of SRAM cells;
retrieving, through the controller, the data from the array of SRAM cells to the array of 3D NAND memory cells;
prior to transmitting the data to the array of 3D NAND memory cells, transmitting, through the controller, the data buffered in the array of SRAM cells to a page buffer; and
programming, through the controller, the data into the array of 3D NAND memory cells.