Patent ID: 11955972
Assignee: EPINOVATECH AB
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A field-programmable gate array, FPGA, device comprising:
a configurable logic block, CLB, comprising a logic inverter comprising a high-electron-mobility transistor, HEMT, wherein the HEMT comprises:
a Si substrate;
an AlyGay-1N layer structure, wherein 0<y≤1;
a GaN layer structure; and
a crystal transition layer structure arranged on the Si substrate, wherein the crystal transition layer comprises:
a plurality of vertical nanowire structures perpendicularly arranged on the Si substrate, and
an AlxGax-1N layer structure, wherein 0≤x<1, wherein the AlxGax-1N layer structure is arranged to vertically and laterally enclose the vertical nanowire structures.