Patent ID: 11876523
Assignee: XILINX, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 19:
20. A method of operating a DPLL, the method comprising:
delaying a reference clock using a DTC based on a received first digital code;
determining, using a TDC, a time difference between the delayed reference clock and a clock based on an output of a DCO;
normalizing the time difference to a resolution of the TDC to generate a phase difference output;
filtering the phase difference output using a DLF; and
correcting, by correction circuitry, quantization errors in the first digital code based on receiving a fractional portion of the first digital code, the correction circuitry including a multiplier configured to scale the fractional portion of the first digital code by a ratio of a resolution of the DTC.