Patent ID: 11953548
Assignee: UNIVERSITY OF FLORIDA RESEARCH FOUNDATION, INC.
Field: Measurement (Instruments)
Classification: CPC G | IPC G

Claim 0:
1. A computer-implemented method comprising:
receiving one or more key patterns for testing a design of a hardware intellectual property (IP), wherein (a) the design comprises one or more invisible scan chains and (b) each invisible scan chain comprises a plurality of flip-flops connected on-demand upon verification of the one or more key patterns;
determining a mode for the design based at least in part on the one or more key patterns and using a scan enable finite state machine (SEFSM);
responsive to determining a test mode for the design:
loading a set of scan input data into the one or more invisible scan chains of the design over a first configurable number of clock cycles;
causing the design to perform a normal operation for a second configurable number of clock cycles; and
obtaining a set of scan output data from the one or more invisible scan chains of the design over the first configurable number of clock cycles; and

performing one or more automated actions based at least in part on whether the set of scan output data is in accordance with an expected set of scan output data.