Patent ID: 11940926
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 18:
19. A method, comprising:
receiving, at a memory system, a command associated with data having a corresponding set of logical addresses;
determining whether a subset of logical addresses of the set of logical addresses is sequential;
generating a set of entries based at least in part on the determining, each entry of the set of entries indicating a mapping between a logical address of the set of logical addresses and a physical address of a set of physical addresses, the set of entries associated with a first level of a mapping information; and
storing a coalesced entry comprising the subset of logical addresses in a second level of the mapping information based at least in part on the generating, the entry indicating the mapping between the set of logical addresses and the set of physical addresses based at least in part on the subset of logical addresses being sequential.