Patent ID: 11929746
Assignee: MINIMA PROCESSOR OY
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G  Y | IPC H

Claim 7:
8. A method for temporarily storing a digital value obtained from an output of a preceding circuit element and for making such a temporarily stored digital value available for a subsequent circuit element at a controlled moment of time, the method comprising:
receiving said digital value for temporary storage, and
receiving a triggering signal, a triggering edge of which defines an allowable time limit before which a digital value must appear at a data input to become available for said subsequent circuit element,
using a sequence of first and second pulse-enabled subregister stages to temporarily store said digital value, and providing said triggering signal to said first pulse-enabled subregister stage delayed with respect to the triggering signal received by said second pulse-enabled subregister stage, the length of the delay being a fraction of a cycle of said triggering signal, wherein said sequence of first and second pulse-enabled subregister stages constitutes a dual edge triggered flip-flop,
outputting a timing event observation signal as an indicator of said digital value at said data input having changed within a time window that begins at said allowable time limit and is shorter than one cycle of said triggering signal, and
wherein said timing event observation logic comprises:
a TE data input coupled to said data input of the register circuit,
a TE clock input coupled to a clock input of the register circuit,
a TE delay element coupled to said TE clock input and configured to delay the triggering signal received at said TE clock input by the length of said delay,
an XOR gate coupled to said TE clock input and said TE delay element and configured to produce an active timing window indicator signal whenever the values received from said TE clock input and said TE delay element are unequal, and
a transition detector coupled to said TE data input and the output of said XOR gate and configured to produce said timing event observation signal in response to the value in said TE data input changing while said timing window indicator signal is active.