Patent ID: 11870431
Assignee: PSEMI CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of biasing a FET switch stack, including:
(a) providing a plurality of series-coupled FETs each including a gate and a body, the plurality of series-coupled FETs including one or more series-coupled positive-logic FETs requiring a relative negative VGS to effectively turn OFF but configured to not require a negative voltage source;
(b) coupling a gate bias resistor ladder to the plurality of series-coupled FETs, the gate bias resistor ladder including a plurality of resistors configured to be coupled to a gate bias voltage and coupled to the gate of at least one corresponding FET of the plurality of series-coupled FETs;
(c) coupling a body charge control resistor ladder to the plurality of series-coupled FETs, the body charge control resistor ladder including a plurality of resistors configured to be coupled to a body bias voltage and coupled to the body of at least one corresponding FET of the plurality of series-coupled FETs; and
(d) coupling a drain-source resistor ladder to the plurality of series-coupled FETs, the drain-source resistor ladder including a plurality of series-coupled resistors configured to be coupled to a drain-source bias voltage and coupled to the respective drains and sources of at least one corresponding adjacent FET of the plurality of series-coupled FETs;
wherein the resistors of the gate bias resistor ladder are series-coupled and the resistors of the body charge control resistor ladder are parallel-coupled.