Patent ID: 11868220
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus, comprising:
a first latch configured to store an address bit associated with an access line identified as defective;
a second latch configured to store at least one bit that indicates that the first latch is storing the address bit;
a first logic component coupled with the first latch and configured to perform a logic operation on a signal representing the address bit stored at the first latch;
a second logic component coupled with the second latch and configured to send, to the first logic component based at least in part on the at least one bit stored at the second latch, a second signal representing a second address bit associated with an access line selected for a memory access operation; and
a third logic component coupled with an output of the first logic component and coupled with an output of the second latch, and configured to receive the signal representing the address bit from the first logic component and the at least one bit from the second latch.