Patent ID: 11972832
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A command decoder circuit, comprising:
a first decoder unit, configured to generate a first command signal based on a dynamic clock signal generated by a clock gate;
a second decoder unit, configured to generate a second command signal based on the dynamic clock signal generated by the clock gate, the second command signal being triggered within a preset period after the first command signal; and
the clock gate, configured to generate the dynamic clock signal when a chip select signal of the first decoder unit indicates the first command signal is generated and before the second command signal is generated, and cut off the dynamic clock signal when the chip select signal indicates that the first command signal has not been generated, or after the second command signal is generated.