Patent ID: 11916561
Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 8:
9. The clock generator of claim 8, wherein the phase interpolator further comprises:
a first digital-to-analog converter configured to generate a first vector of a selected even-numbered first-level clock signal from the first multiplexer, weighted by a first weighting factor; and
a second digital-to-analog converter configured to generate a second vector of a selected odd-numbered first-level clock signal from the second multiplexer, weighted by a second weighting factor;
wherein the outputs of the first and second digital-to-analog converters are configured to be added, wherein the added first and second vectors form the interpolated clock signal, wherein the respective interpolated clock signal has a phase within the 1xT phase offset between the even-numbered and odd-numbered first-level clock signals.