Patent ID: 11887655
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 1:
2. The sense amplifier of claim 1, wherein the amplification circuit comprises:
a first P-channel Metal Oxide Semiconductor (PMOS) transistor;
a second PMOS transistor;
a first N-channel Metal Oxide Semiconductor (NMOS) transistor, a gate of the first NMOS transistor being connected to the first bit line, and a drain of the first NMOS transistor being connected to a drain of the first PMOS transistor through a first node; and
a second NMOS transistor, a gate of the second NMOS transistor being connected to the second bit line, and a drain of the second NMOS transistor being connected to a drain of the second PMOS transistor through a second node;
wherein in the case of reading the data in the memory cell on the first bit line, at the offset compensation stage of the sense amplifier, the second NMOS transistor is configured as the first diode structure, the first PMOS transistor and the second PMOS transistor are configured as the first current mirror structure, and the first PMOS transistor and the first NMOS transistor are configured as the first inverter with the input terminal and the output terminal connected to each other;
in the case of reading the data in the memory cell on the second bit line, at the offset compensation stage of the sense amplifier, the first NMOS transistor is configured as the second diode structure, the first PMOS transistor and the second PMOS transistor are configured as the second current mirror structure, and the second PMOS transistor and the second NMOS transistor are configured as the second inverter with the input terminal and the output terminal connected to each other.