Patent ID: 11955197
Assignee: ROBERT BOSCH GMBH
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device, comprising:
a cell field having a plurality of memory cells;
a number N of bit lines, which are each respectively connected to at least one of the memory cells of the cell field, N being a whole number greater than one and a bit line number in a range from 1 to N being assignable to each bit line according to a bit line sequence;
N sense amplifiers, a sense amplifier number in the range from 1 to N being assignable to each sense amplifier according to a sense amplifier sequence; and
a bit shift circuit, which has a number S of switch element rows, S being a whole number greater than one and a row number in a range from zero to S−1 being assignable to each switch element row according to a switch element row sequence;
wherein each switch element row has respectively at least one semiconductor switch element, each semiconductor switch element being connected to one of the bit lines and to one of the sense amplifiers, so that in a conductive state of the semiconductor switch element an electrically conductive connection exists between the bit line and the sense amplifier and in a non-conductive state of the semiconductor switch element the bit line is insulated from the sense amplifier;
wherein the semiconductor switch elements of each respective switch element row connects all bit lines whose bit line number is smaller than or equal to the number N minus the row number of the respective switch element row, to sense amplifiers, so that the respective sense amplifier number is equal to the respective bit line number plus the row number of the respective switch element row.