Patent ID: 11908802
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 4:
5. A system comprising:
a display subsystem;
a wireless communication interface; and a multi-chip package, the multi-chip package comprising:
one or more processor dies;
one or more memory dies; and
a substrate coupled with the processor and memory dies, wherein the substrate comprises: top surface contacts arranged as coupling sites for the processor and memory dies, wherein at least one coupling site contains at least a first contact pitch and a second contact pitch higher than the first contact pitch; bottom surface contacts at a third contact pitch, wherein the third contact pitch is lower than the first contact pitch; and

interconnects embedded within dielectric material, wherein the interconnects couple some of the top surface contacts with the bottom surface contacts and couple groupings of the top surface contacts having the second contact pitch along sides of a plurality of coupling sites with groupings of the top surface contacts along sides of adjacent coupling sites, wherein the interconnects further couple inner groupings of top surface contacts of adjacent coupling sites by extending deeper within the dielectric material.