Patent ID: 11907007
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. An integrated circuit (IC) device, comprising:
a substrate;
a circuit region over the substrate, the circuit region comprising:
at least one active region extending along a first axis, and
at least one gate region extending across the at least one active region and along a second axis transverse to the first axis; and

a clock distribution system over and electrically coupled to the circuit region, the clock distribution system configured to supply a clock signal to the circuit region, the clock distribution system comprising:
in a first metal layer over the circuit region,
a first metal pattern oblique to both the first axis and the second axis, and
a pair of first shielding metal patterns arranged along and on opposite sides of the first metal pattern,

in a second metal layer over the circuit region,
a second metal pattern transverse to the first metal pattern and oblique to both the first axis and the second axis, and
a pair of second shielding metal patterns arranged along and on opposite sides of the second metal pattern, and

in a third metal layer over the circuit region,
a third metal pattern extending along the first axis or the second axis, wherein the third metal pattern overlaps and is electrically coupled to the first metal pattern and the second metal pattern, and
a pair of third shielding metal patterns arranged along and on opposite sides of the third metal pattern,

wherein each of the first shielding metal patterns, the second shielding metal patterns, and the third shielding metal patterns is configured to receive a power supply voltage.