Patent ID: 11869625
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A data transmission circuit, comprising:
a serial-parallel conversion module configured to receive a plurality of pieces of external data in batches and output initial parallel data according to the external data, wherein a preset bit width of the initial parallel data is equal to a sum of bit widths of the plurality of pieces of external data;
a comparison module configured to receive global data on a global data line and the initial parallel data, and compare the initial parallel data with the global data to output a comparison result of whether a number of bits of the initial parallel data which are different from the global data exceeds a preset threshold, wherein the initial parallel data and the global data have identical preset bit widths;
a data conversion module electrically connected to the serial-parallel conversion module, the comparison module and a data bus, and configured to, responsive to that the comparison result indicates that the preset threshold is exceeded, invert the initial parallel data and transmit the inverted data to the data bus, and responsive to that the comparison result indicates that the preset threshold is not exceeded, transmit the initial parallel data to the data bus; and
a write circuit module configured to transmit data on the data bus to a global data bus;
wherein a length of a data transmission path between the serial-parallel conversion module and the data conversion module is less than a length of a data transmission path between the data conversion module and the write circuit module.