Patent ID: 11916003
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC B  H

Claim 18:
19. An electronic system, comprising:
a first substrate;
a second substrate attached to the first substrate by an array of first level of interconnects; and
a third substrate attached to the second substrate by an array of second level of interconnects, wherein at least one of the array of first level interconnects and the array of second level interconnects comprises:
first interconnects; and
second interconnects, wherein a number of first interconnects is greater than a number of second interconnects, wherein the first interconnects have a first volume and a first material composition, wherein the second interconnects have a second volume and a second material composition, wherein the first volume is different than the second volume and the first material composition is different than the second material composition, and wherein the second interconnects each comprise a core, and solder completely surrounding the core, the solder having a material composition different than the first material composition.