Patent ID: 11889706
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 18:
19. A display device comprising:
a substrate including a display region and a non-display region;
a plurality of pixels in the display region, the plurality of pixels each including at least one transistor, a storage capacitor connected to the at least one transistor, and a light emitting element connected to the at least one transistor;
a plurality of scan lines connected to each of the plurality of pixels, the plurality of scan lines extending in a first direction;
a data line connected to each of the plurality of pixels, the data line extending in a second direction crossing the first direction; and
a power line supplying a first power voltage to the light emitting element,
wherein the at least one transistor includes:
an active pattern provided on the substrate, source and drain electrodes each connected to the active pattern;
a gate electrode provided on the active pattern with a gate insulating layer interposed therebetween to overlap the active pattern;
an insulating interlayer covering the gate electrode and including:
a first insulating interlayer, a second insulating interlayer, and a third insulating interlayer, which are sequentially stacked; and
a protective layer provided on the third insulating interlayer, and

wherein at least one of the plurality of scan lines is disposed between the second insulating interlayer and the third insulating interlayer, and is connected to the gate electrode through a contact hole,
wherein the second insulating interlayer includes an inorganic insulating layer,
wherein the third insulating interlayer includes an organic insulating layer, the third insulating interlayer covering the plurality of scan lines and the power line, and
wherein the third insulating interlayer contacts at least one of the plurality of scan lines,
wherein the power line includes:
a first conductive pattern extending in the first direction, the first conductive pattern being provided on the first insulating layer;
a second conductive pattern extending in the first direction, the second conductive pattern being provided on the second insulating interlayer, the second conductive pattern being connected to the first conductive pattern; and
a third conductive pattern extending in the second direction, the third conductive pattern being provided on the third insulating interlayer, the third conductive pattern being connected to the second conductive pattern, and
wherein resistances of the second conductive pattern and the third conductive pattern are smaller than a resistance of the first conductive pattern.