Patent ID: 11923286
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A package substrate comprising:
an insulating layer comprising a first upper insulating layer having a mounting surface and a second upper insulating layer provided on the first upper insulating layer;
a wiring pattern extending in the insulating layer; and
a chip bonding pad provided on the mounting surface of the first upper insulating layer and connected to the wiring pattern, the chip bonding pad having a tapered shape in which a horizontal cross-sectional area of the chip bonding pad gradually decreases away from the mounting surface of the first upper insulating layer in a vertical direction,
wherein a portion of the chip bonding pad closest to the mounting surface of the first upper insulating layer has a horizontal length of about 20 μm to about 30 μm, and
wherein the second upper insulating layer comprises a hole in which the chip bonding pad is provided and through which the chip bonding pad and a portion of the mounting surface of the first upper insulating layer are exposed.