Patent ID: 11907154
Assignee: QUALCOMM INCORPORATED
Field: Digital communication (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 27:
28. A non-transitory processor-readable storage medium storing code thereon, the code when executed by a processor in a processing circuit causes the processing circuit to:
configure an oscillator to generate a base clock signal with a base frequency;
configure a clock gating circuit to output a gated base clock signal while the clock gating circuit is enabled, the clock gating circuit being responsive to one or more control inputs;
configure a first counter to provide a counter output that reflects a count of positive and negative edges in the gated base clock signal that clocks the first counter;
configure control logic to disable the clock gating circuit when the counter output corresponds to a maximum count value; and
configure an edge synchronization circuit to:
ignore edges in a signal received by the edge synchronization circuit from a one-wire bus while the counter output has a value that is less than the maximum count value; and
reset the first counter in response to an edge detected in the signal received from the one-wire bus.