Patent ID: 11899940
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. The apparatus according to claim 10,
wherein the pending load buffer circuitry is arranged to store for each of the load requests buffered in the pending load buffer circuitry a status indicator,
wherein the status indicator for load requests received from the address generation circuitry is initially set to indicate a valid state,
wherein in response to the address proximity condition being satisfied the status indicator corresponding to the set of one or more subsequent load requests is set to indicate an invalid state, and
the coalescing circuitry is responsive to an invalid load request in the pending load buffer circuitry to suppress forwarding of the invalid load request. wherein when the load request is forwarded the status indicator of the load request is set to indicate an in-flight state,
wherein in response to the decoalescing circuitry returning as the result of the load request the data item identified by the load request, the status indicator corresponding to the load request is set to the invalid state, and
wherein reinstating the load request in the pending load buffer comprises resetting the status indicator corresponding to the load request to the valid state.