Patent ID: 11947483
Assignee: XCONN TECHNOLOGIES HOLDINGS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A method, comprising:
receiving a transaction in a port of a plurality of ports of a switch, the switch also including a plurality of port logic modules and a core portion, the core portion including a switch fabric and a memory, the plurality of port logic modules being coupled with the plurality of ports, a port logic module of the plurality of port logic modules being coupled with the port, the core portion of the switch having a system clock domain, wherein each port control logic module includes routing logic, the controlling further including:
allowing, using the routing logic, a response transaction to bypass a request transaction; and
preventing, using the routing logic, the request transaction from bypassing the response transaction, wherein the routing logic including a router, a request bypass queue coupled to the router, and an arbitrator coupled with the router and the request bypass queue, the router configured to route the response transaction to an interface coupled with the port, to route the request transaction to the arbitrator if the interface can receive transactions, and to route the request transaction to the request bypass queue if the interface cannot receive the transactions, the arbitrator configured to forward an older request transaction from the router or the request bypass queue; and

controlling, using the port logic module, routing of the transaction through the core portion, the port logic module having core clock domain logic for a core clock domain specific to the port and different from the system clock domain.