Patent ID: 11928027
Assignee: CADENCE DESIGN SYSTEMS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. A system comprising:
a memory controller configured to receive one or more fixed size error checking and correction data blocks and metadata, the memory controller including a data to symbol mapping portion further configured to perform data to symbol mapping based upon, at least in part, the one or more fixed size data blocks, the data to symbol mapping portion further configured to provide an output of the data to symbol mapping to a first encoder without metadata configured for full detection correction of single device error and to a second encoder with metadata configured for partial detection correction of single device error;
a memory configured to receive data based upon, at least in part, an output from the first encoder and the second encoder;
a first decoder without metadata configured to receive data from the memory, wherein the first decoder without metadata is configured for full detection correction of single device error;
a second decoder with metadata configured to receive data from the memory, wherein the second decoder is configured for partial detection correction; and
a symbol re-mapping portion configured to re-map symbol data from the first decoder and the second decoder to actual data and to generate one or more output data blocks and metadata.