Patent ID: 11937426
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A method for forming a semiconductor structure, comprising:
depositing a multilayer film over a substrate and comprising a first dielectric layer, a sacrificial layer overlying the first dielectric layer, and a second dielectric layer overlying the sacrificial layer;
performing a first etch into the multilayer film to form a recess;
laterally recessing sidewalls of the sacrificial layer in the recess;
forming a data storage layer, a channel layer, a gate dielectric layer, and a gate electrode stacked in the recess, wherein the data storage layer is between the sacrificial layer and the gate electrode;
replacing the sacrificial layer with a third dielectric layer;
performing a second etch into the third dielectric layer to form a pair of openings exposing a common sidewall of the data storage layer; and
filling the pair of openings respectively with a source electrode and a drain electrode.