Patent ID: 11948872
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. A semiconductor package, comprising:
a redistribution substrate;
a semiconductor chip on a top surface of the redistribution substrate; and
a solder terminal on a bottom surface of the redistribution substrate,
wherein the redistribution substrate includes:
an under-bump pattern;
a dielectric layer on a sidewall of the under-bump pattern;
an under-bump seed pattern between the dielectric layer and the sidewall of the under-bump pattern; and
a redistribution pattern on a top surface of the under-bump pattern,

wherein the solder terminal is on a bottom surface of the under-bump pattern,
wherein the bottom surface of the under-bump pattern is at a level higher than a level of a bottom surface of the dielectric layer,
wherein a first angle between the bottom surface and the sidewall of the under-bump pattern is an obtuse angle, and
wherein the under-bump seed pattern does not extend onto any of a top surface of the dielectric layer and the bottom surface of the under-bump pattern.