Patent ID: 11907546
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G

Claim 14:
15. An apparatus, comprising:
a first memory device comprising a first plurality of memory cells;
a second memory device comprising a second plurality of memory cells; and
a controller coupled with the first memory device and the second memory device, the controller operable to cause the apparatus to:
receive, from a host device, command and address information associated with a set of data, the command and address information being received using a first channel and a buffer included in the first memory device, wherein the first channel is configured to support a first modulation scheme using a first Quantity of voltage levels;
determine that the set of data is stored in the first plurality of memory cells; and
transmit, to the first memory device and based at least in part on determining that the set of data is stored in the first plurality of memory cells, a command to cause the first memory device to transmit the set of data to the second memory device using a second channel, wherein the second channel is configured to support a second modulation scheme using a second Quantity of voltage levels that is different than the first quantity of voltage levels.