Patent ID: 11901362
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 17:
18. A method comprising:
forming a first set of nanostructures and a second set of nanostructures on a substrate, the first set of nanostructures comprising a first channel region and the second set of nanostructures comprising a second channel region;
forming a gate dielectric layer having a first portion and a second portion, the first portion deposited on the first channel region, the second portion deposited on the second channel region;
forming a n-type work function tuning layer on the first portion of the gate dielectric layer and the second portion of the gate dielectric layer, the n-type work function tuning layer wrapping around each of the first set of nanostructures;
forming a first barrier layer on the n-type work function tuning layer;
removing the first barrier layer and the n-type work function tuning layer from the second portion of the gate dielectric layer;
forming a p-type work function tuning layer on the first barrier layer on the first set of nanostructures and the second portion of the gate dielectric layer;
performing a treatment process on the p-type work function tuning layer to modify a work function of the p-type work function tuning layer; and
forming a fill layer on the p-type work function tuning layer.