Patent ID: 11955167
Assignee: NORTHWESTERN UNIVERSITY
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A three-transistors (3T) memory cell, comprising:
a read-access transistor M1 in electrical communication with a read bitline;
a switch transistor M2 in electrical communication with the read-access transistor M1;
a write-access transistor M3 in electrical communication with the read-access transistor M1 and a write bitline; and
a memory node MEM in electrical communication between the read-access transistor M1 and the write-access transistor M3, wherein the memory node MEM is configured to store a 4-bit weight WE,
wherein the 4-bit weight WE stored at the memory node MEM generates a read current IMEM proportional to a weight value that is configurable up to the 4-bit weight forming a dynamic-analog-random access memory (DARAM) with a configurable bit weight,
wherein the memory node MEM that stores the 4-bit weight comprises a three-dimensional (3D) interlayer/interdigit metal capacitor,
wherein the 3D interlayer/interdigit metal capacitor comprises a plurality of vertically stacked metal layers that form vertically and horizontally interleaving memory nodes MEM and ground nodes GND to enhance storage capacitance,
wherein the vertically interleaving memory nodes MEM and ground nodes GND form vertically stacked series capacitors, wherein each of the series capacitors in the vertical stack corresponds to a capacitance value with respect to a corresponding pair of MEM and GND nodes, and a horizontal interdigitated structure having formed on each metal layer each metal layer in the vertical stack corresponds to respective horizontal capacitors.