Patent ID: 11942371
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 13:
14. A method, comprising:
forming a gate structure between gate spacers and over a semiconductor substrate;
etching back the gate structure to fall below top ends of the gate spacers;
forming a gate dielectric cap over the etched back gate structure;
forming a source/drain contact in contact with a sidewall of the gate dielectric cap;
depositing an etch-resistant layer over the gate dielectric cap and the source/drain contact;
depositing in sequence an etch stop layer and an interlayer dielectric (ILD) layer over the etch-resistant layer;
performing a first etching process to form a via opening extending through the ILD layer;
after the first etching process is completed, performing a second etching process to extend the via opening down to the source/drain contact, wherein after the second etching process etches through the etch-resistant layer, a sidewall profile of the via opening becomes more vertical than before etching the etch-resistant layer; and
after performing the second etching process, forming a via structure in the via opening.