Patent ID: 11929113
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A memory precharge system, comprising:
a power supply voltage input terminal configured to receive a power supply voltage at a first voltage level;
a bit line precharge circuit having an output terminal configured to output a second voltage level lower than the first voltage level and precharge a memory bit line to the second voltage level,
wherein the second voltage level is determined by:
setting a precharge voltage at the first voltage level;
precharging the memory bit line to the first voltage level;
determining whether a data value of the memory cell has flipped from an initial value; and
if the data value of the memory cell has not flipped, then reducing the precharge voltage to the second voltage level lower than the first voltage level.