Patent ID: 11940494
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Measurement (Instruments)
Classification: CPC G | IPC G

Claim 0:
1. A system on chip, comprising:
a one-time programmable (OTP) memory configured to store secure data;
an OTP controller including at least one shadow register configured to read the secure data from the OTP memory and to store the secure data;
a power management unit configured to receive an operation mode signal from an external device and to output test mode information indicating whether an operation mode is a test mode according to the operation mode signal and a test valid signal corresponding to the secure data; and
a test circuit configured to receive the test mode information from the power management unit, to receive test data from the external device, and to output a scan mode signal and a test mode signal according to the test data and the test deactivation signal,
wherein the test deactivation signal corresponds to development state data indicating a chip development state in the secure data.