Patent ID: 11901235
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 12:
13. A method comprising:
forming multiple nanostructures over a substrate;
forming a dummy gate structure over the multiple nanostructures;
performing a first angled ion implantation to implant first dopants under the dummy gate structure into a first nanostructure of the multiple nanostructures;
etching the first nanostructure to remove a first portion of the first nanostructure exposed from the dummy gate structure, a second portion of the first nanostructure under the dummy gate structure remaining as a first doped channel region;
performing a second angled ion implantation to implant second dopants under the dummy gate structure into a second nanostructure;
etching the second nanostructure to remove a first portion of the second nanostructure exposed from the dummy gate structure and the first nanostructure, a second portion of the second nanostructure under the dummy gate structure remaining as a second doped channel region; and
forming a source region or a drain region contacting the first doped channel region and the second doped channel region.