Patent ID: 11961579
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. An apparatus, comprising:
a complementary metal-oxide-semiconductor (CMOS) wafer including:
CMOS wafer contact pads; and
sense amplifier circuitry electrically connected to some of the CMOS wafer contact pads; and

a memory cell wafer attached to the CMOS wafer, the memory cell wafer including:
memory cell wafer contact pads; and
bit lines electrically connected to some of the memory cell wafer contact pads, the bit lines including primary bit lines and secondary bit lines, each of the secondary bit lines extending in parallel proximate to a corresponding one of the primary bit lines, a cross intersection of a first primary bit line of the primary bit lines with a first secondary bit line of the secondary bit lines located proximate to a parity intersection of a second primary bit line of the primary bit lines with a second secondary bit line of the secondary bit lines, the first primary bit line adjacent to the second primary bit line.