Patent ID: 11881477
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A method of designing an integrated chip, the method comprising:
generating an integrated circuit layout file comprising an oxide definition mask, wherein the oxide definition mask specifies an isolation structure that surrounds and thereby defines each of a first active device area and a second active device area, wherein the isolation structure is specified to extend across a space between the first active device area and the second active device area;
adding specifications for linear features in an array to the integrated circuit layout file, wherein the first linear features in the array have a constant pitch and extend over the first active device area, the second active device area, and the space between the first active device area and the second active device area; and
operating a manufacturing process according to the integrated circuit layout file, wherein the manufacturing process includes:
providing a semiconductor substrate;
forming an isolation structure on the semiconductor substrate in a pattern determined by the integrated circuit layout file, whereby the isolation structure provides borders that define the first active device area and the second active device area on the semiconductor substrate; and
forming the linear features on the semiconductor substrate according to the specification in the integrated circuit layout file, whereby the linear features form an array having constant pitch and extending across the first active device area, the second active device area, and the space between the first active device area and the second active device area wherein the linear features become integrated into active devices in the first active device area and in the second active device area and provide dummy devices in the space between the first active device area and the second active device area.