Patent ID: 11950403
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor memory device, comprising:
an array of vertically stacked memory cells, having:
a vertical stack of horizontally oriented multi-directional conductive lines, each multi-directional conductive line comprising:
a first portion extending in a first horizontal direction;
a plurality of second portions, wherein each second portion of the plurality of second portions extends from the first portion in a second horizontal direction, and wherein each second portion of the plurality of second portions is wider than the first portion; and
a plurality of conductive line contacts that are formed between the second portions to allow for a direct contact with conductive layers of a staircase contact structure, wherein the conductive layers are in direct contact with conductive lines formed within the staircase contact structure.