Patent ID: 11907144
Assignee: AMAZON TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A system comprising:
system memory operable to:
store a set of data; and
generate a respective acknowledgement to indicate that a corresponding set of data has been stored in the system memory;
an integrated circuit device including:
an acceleration circuit;
an on-chip memory; and
a semaphore that is written to control operation of the acceleration circuit; and
a direct memory access (DMA) engine including:
a read descriptor queue operable to store read descriptors;
a write descriptor queue operable to store write descriptors; and
a controller operable to:
process the read descriptors to obtain the set of data from the on-chip memory for storage into the system memory;
insert a first semaphore update without a memory barrier in a processing flow of the DMA engine to indicate that the on-chip memory is free to store a new set of data before the set of data has been completely written into the system memory;
process the write descriptors to write the set of data into the system memory;
receive an acknowledgement from the system memory that the set of data has been stored in the system memory; and
perform a second semaphore update with a memory barrier to indicate that the set of data is available in the system memory in response to the acknowledgement.