Patent ID: 11968821
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method used in fabricating integrated circuitry, comprising:
forming a first row of pillar openings in a material and a second row of pillar openings in the material, the openings of the first row of pillar openings being horizontally aligned with the openings of the second row of pillar openings, the material having an upper surface at a first elevation;
forming pillars in the pillar openings, the pillars each having a projecting portion extending elevationally to a second elevation, the second elevation being greater than the first elevation;
forming a plurality of rings of masking material, each of the rings comprised by the plurality of rings encircling the projecting portion of one of the pillars, the masking material having mask openings present between diagonally-adjacent of the rings;
etching the material using the rings and pillars as a mask, the etching vertically extending the mask-openings into the material to form via openings within the material; and
forming conductive material in the via openings, the conductive material being directly electrically coupled to an operative circuit component formed in one of four of the pillar openings that immediately surround an individual of the via openings.