Patent ID: 11908783
Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor package, comprising:
a first power device having a first surface, a second surface opposite to the first surface, and a first terminal adjacent to the first surface of the first power device;
a second power device having a first surface, a second surface opposite to the first surface, and a second terminal adjacent to the first surface of the second power device;
a control device having a first surface, a second surface opposite to the first surface, and control device terminals adjacent to the first surface of the control device;
a first lower wiring adjacent to the second surface of the first power device;
a second lower wiring adjacent to the second surface of the second power device;
a third lower wiring adjacent to the second surface of the control device;
a first insulating layer covering the first power device, the second power device, the control device, the first lower wiring, the second lower wiring, and the third lower wiring, the first insulating layer comprising first openings extending from a first surface of the first insulating layer to the first terminal, the second terminal, and the control device terminals;
a first conductive layer over the first terminal and the second terminal but not over the control device terminals;
a second conductive layer over the first terminal, the second terminal, and the control device terminals, wherein:
the second conductive layer is within the first openings;
the second conductive layer is interposed between the first terminal and the first conductive layer and interposed between the second terminal and the first conductive layer; and
a first portion of the first conductive layer and a first portion of the second conductive layer are coupled to the first terminal and the second lower wiring through one of the first openings in the first insulating layer; and

a second insulating layer covering the first conductive layer and the second conductive layer.