Patent ID: 11862237
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 8:
9. The memory of claim 8, wherein the complementary bit-line write circuit comprises a third transistor and a fourth transistor;
wherein the third transistor is turned on in response to the low write control signal, and the fourth transistor is turned on in response to the high write control signal, and wherein a source of the third transistor is coupled to a power terminal, a drain of the third transistor is coupled to a drain of the fourth transistor, a source of the fourth transistor is grounded, and a gate of the third transistor is connected to a gate of the fourth transistor and is coupled to the second AND gate; or
wherein the third transistor and the fourth transistor are turned on in response to the low write control signal, and wherein the source of the third transistor is coupled to the complementary bit line, the drain of the third transistor is grounded, the source of the fourth transistor is coupled to the power terminal, the drain of the fourth transistor is coupled to the complementary bit line, and the gate of the third transistor is connected to the gate of the fourth transistor and is coupled to the second AND gate; or
wherein the third transistor and the fourth transistor are turned on in response to the high write control signal, and wherein the drain of the third transistor is coupled to the complementary bit line, the source of the third transistor is grounded, the drain of the fourth transistor is coupled to the power terminal, the source of the fourth transistor is coupled to the complementary bit line, and the gate of the third transistor is connected to the gate of the fourth transistor and is coupled to the second AND gate.