Patent ID: 11908749
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 18:
19. A method of forming a semiconductor structure, comprising:
forming a first dummy gate electrode and a second dummy gate electrode over a substrate;
forming first spacers on the first dummy gate electrode and second spacers on the second dummy gate electrode;
depositing an interlayer dielectric layer over the first and second dummy gate electrodes and the substrate;
etching the first and second dummy gate electrodes to form a first trench between the first spacers and a second trench between the second spacers;
depositing a layer stack in the first trench and the second trench;
depositing a work function layer over the layer stack;
etching at least a portion of the work function layer from the first trench while keeping the work function layer and the layer stack intact in the second trench; and
depositing a conductive layer to fill the first trench and the second trench.