Patent ID: 11967647
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 16:
17. A method for forming a semiconductor device, comprises:
forming a gate structure surrounding a nanostructure channel over a substrate;
forming source/drain structures adjacent to the nanostructure channel;
depositing a dielectric layer to cover the source/drain structures and the gate structure;
etching the dielectric layer to form source/drain contact openings, the source/drain contact openings exposing portions of the source/drain structures;
forming conductive plugs in the source/drain contact openings;
deposing a light blocking layer in direct contact with a top surface of the dielectric layer and top surfaces of the conductive plugs;
etching the light blocking layer to form openings exposing the conductive plugs but not the gate structure;
irradiating the conductive plugs and a remaining portion of the light blocking layer; and
removing the remaining portion of the light blocking layer from the top surface of the dielectric layer,
wherein etching the light blocking layer comprises:
forming a photoresist layer over the light blocking layer;
patterning the photoresist layer to form openings therein to expose portions of the light blocking layer overlying the conductive plugs; and
removing the exposed portions of the light blocking layer by an anisotropic etching process.