Patent ID: 11923207
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A method comprising:
encapsulating an integrated circuit die in a molding compound;
depositing a dielectric layer over the molding compound and the integrated circuit die;
exposing a top surface of the dielectric layer to a patterned energy source using an aligner, wherein exposing the top surface of the dielectric layer to the patterned energy source comprises bringing a photomask into alignment with the top surface of the dielectric layer such that the photomask completely covers the top surface of the dielectric layer;
developing the dielectric layer to form a plurality of openings exposing the integrated circuit die; and
forming a metallization pattern in the plurality of openings, wherein the metallization pattern is electrically connected to the integrated circuit die.