Patent ID: 11894037
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. An apparatus, comprising:
a control circuit configured to connect to an array comprising a plurality of bit lines and a plurality of word lines, the array formed according to a cross-point architecture in which each of a plurality of non-volatile memory cells is connected between a corresponding one of the bit lines and a corresponding one of the word lines, each memory cell comprising a programmable resistive element connected in series with a threshold switching selector configured to become conductive in response to application of a voltage level exceeding a corresponding threshold voltage, the control circuit is configured to:
access one or more selected memory cells of the array using a half-select biasing in which the control circuit is configured to concurrently apply an access voltage between a corresponding one or more selected bit lines and a corresponding one or more selected word lines, bias unselected bit lines of the array at a first unselected voltage, and bias unselected word lines at a second unselected voltage, the first unselected voltage and the second unselected voltage both intermediate to the access voltage and a low voltage level; and
prior to accessing the one or more selected memory cells, perform an initialization of the array in which the control circuit is configured to:
bias one or more memory cells of the array, including one or more of the selected memory cells, by applying an initialization voltage between the biased memory cells' corresponding one or more bit lines and corresponding one or more word lines;
while biasing the one or more memory cells of the array by applying the initialization voltage, bias bit lines other than the corresponding bit lines at a third unselected voltage; and
while biasing the one or more memory cells of the array by applying the initialization voltage, bias word lines other than the corresponding word lines at a fourth unselected voltage, the third unselected voltage and the fourth unselected voltage both intermediate to the initialization voltage and the low voltage level, where one or both of the third unselected voltage and the fourth unselected voltage are shifted relative to the first unselected voltage and to the second unselected voltage, respectively.