Patent ID: 11899828
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G  H

Claim 14:
15. The memory device of claim 13, wherein:
each column of the memory cell array includes a bit line and a bit bar line;
each bit line is electrically connected to a drain end of a first transistor, wherein
a source end of the first transistor is electrically connected to a system ground,
a gate end of the first transistor is controlled by a clear signal generated by the reset circuit based on the indication of the voltage tempering event, and
the clear signal triggers the first transistor to lock the bit line to its initial logical state; and

each bit bar line is electrically connected to a drain end of a second transistor, wherein
a source end of the second transistor is electrically connected to a logic high voltage,
a gate end of the second transistor is controlled by a clear bar signal that is a reverse of the clear signal, and
the clear bar signal triggers the second transistor to lock the bit bar line to its initial logical state.