Patent ID: 11954356
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus comprising:
one or more processor cores to access memory pages stored in a memory by issuing access requests to the memory; and
a cache to track recent accesses made by the one or more processor cores to the memory pages, wherein responsive to one or more criteria being met, the tracked recent accesses are to be subsequently stored into a page index bitmap to track accesses made by the one or more processor cores to the memory pages and to store the tracked accesses, the tracked accesses usable to identify infrequently-accessed memory pages, wherein the infrequently-accessed memory pages are to be removed from the memory and stored in a secondary storage;
wherein the memory comprises a plurality of memory modules, each of the plurality of memory modules storing a portion of the page index bitmap, and wherein the apparatus further comprises storage to store one or more interleave rules, the one or more interleave rules usable for determining which of the plurality of memory modules stores the portion of the page index bitmap that is to store the tracked recent accesses.