Patent ID: 11940855
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 9:
10. A system, comprising:
a power control unit of a processor;
a port to connect with a device external to the processor;
a peak power manager coupled to the power control unit;
a connection manager coupled to the peak power manager; and
a platform manager coupled to the connection manager and the port, wherein:
if within a fixed time interval, a sequence is completed in which the platform manager is to determine that the device is connected to the port and provide an attach notification to the device, and the peak power manager is to receive information from the connection manager regarding a maximum power budget required by the device and request that the power control unit set a peak power of the processor based on the maximum power budget required by the device, then:
the platform manager is to negotiate a power required by the device and inform the connection manager of an actual power required by the device; and
the peak power manager is to receive additional information from the connection manager of the actual power required by the device and request that the power control unit change the peak power of the processor based on the actual power required by the device; and

if the sequence is not completed within the fixed time interval, the platform manager is to assert a throttling signal to throttle power of the processor to a lowest power state before supplying a bus voltage to the port.