Patent ID: 11929122
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A memory system comprising:
a memory device configured to store data; and
a controller coupled to the memory device and configured to transmit an erase command regarding the data,
wherein the memory device comprises:
a cell string including plural non-volatile memory cells arranged in series between a bit line and a source line
plural first discharge transistors coupled in parallel to the source line for providing a first current path of discharging the charges;
at least one second discharge transistor coupled to the bit line for providing a second current path of discharging charges which are accumulated in a channel formed through the cell string; and
a control circuit configured to control the plural first discharge transistors and the at least one second discharge transistor for synchronizing discharge of the charges via the first and second current path, the bit line and the source line in response to the erase command.