Patent ID: 11894073
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 3:
4. The memory apparatus as set forth in claim 1, further including an error correction code engine configured to determine and correct errors in reading the memory cells and wherein the threshold voltage possible for each of the memory cells spans a threshold window, each of the memory cells is configured to store a plurality of bits, the plurality of data states includes an erased state at a first end of the threshold window and a plurality of programmed data states each corresponding to the threshold voltage being higher than the threshold voltage associated with the erased state, the plurality of programmed data states including a highest data state at a second end of the threshold window opposite the first end and associated with the threshold voltage being higher than the threshold voltage associated with the erased state and at least one other of the plurality of programmed data states and the control means is further configured to:
count an edge higher data state quantity of the memory cells associated with the at least one edge word line having the threshold voltage above a verify voltage corresponding to the highest data state;
determine whether the edge higher data state quantity is less than an edge highest data state threshold;
read data of the memory cells associated with the at least one edge word line and generate corrected data from the data using the error correction code engine in response to determining the edge higher data state quantity is less than the edge highest data state threshold; and
use the corrected data while reprogramming the memory cells associated with the at least one edge word line without erasing the memory cells associated with the at least one edge word line.