Patent ID: 11917832
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 17:
18. A method of forming a memory structure, comprising:
forming a bottom electrode layer;
forming a ferroelectric (FE) structure comprising:
depositing a dielectric layer on the bottom electrode layer;
depositing an FE layer on the dielectric layer; and
depositing an interface metal layer on the FE layer, wherein the interface metal layer is configured to induce a formation of an orthorhombic crystal phase in the FE layer;

depositing a top electrode layer on the interface metal layer;
forming a substrate; and
forming a transistor on the substrate, wherein forming the transistor on the substrate comprises:
forming a source region and a drain region in the substrate;
forming a channel region in the substrate between the source region and the drain region;
depositing a high-k dielectric layer on the channel region; and
depositing a gate electrode on the high-k dielectric layer, wherein the bottom electrode layer is electrically connected to the drain region.