Patent ID: 11972800
Assignee: EMEMORY TECHNOLOGY INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. The non-volatile memory cell array as claimed in claim 11, wherein the first gate structure comprises a first gate oxide layer and a first polysilicon gate layer, the second gate structure comprises a second gate oxide layer and a second polysilicon gate layer, and the third gate structure comprises a third gate oxide layer and a third polysilicon gate layer, wherein the first gate oxide layer and the second gate oxide layer are contacted with the N-well region, and the third gate oxide layer is contacted with the P-well region, wherein the first polysilicon gate layer covers the first gate oxide layer, the second polysilicon gate layer covers the second gate oxide layer, and the third polysilicon gate layer covers the third gate oxide layer, wherein the first polysilicon gate layer is connected with the first program word line, and the third polysilicon gate layer is connected with the first read word line.