Patent ID: 11863430
Assignee: AT&T INTELLECTUAL PROPERTY I, L.P.
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A device comprising:
a processing system including a processor; and
a memory that stores executable instructions that, when executed by the processing system, facilitate performance of operations, the operations comprising:
generating a set of Shared Risk Link Groups (SRLGs) associated with a set of link bundles, wherein the set of SRLGs comprises for each Shared Risk Link Group (SRLG) in the set of SRLGs an indication for each failed link bundle in a particular SRLG a respective bandwidth failure fraction, greater than 0 and less than or equal to 1, and wherein for at least one of the failed link bundles the failure is less than a complete failure;
generating a set of dominance relationships among the SRLGs in the set of SRLGs, wherein each dominance relationship comprises for two SRLGs an indication that one of the two SRLGs dominates another of the two SRLGs, and wherein the one of the two SRLGs dominating the another of the two SRLGs comprises: (a) the other of the two SRLGs having each associated failed link bundle also being failed by the one of the two SRLGs; and (b) each associated failed link bundle of the other of the SRLGs having a respective bandwidth failure fraction that is less than or equal to a respective bandwidth failure fraction of the corresponding failed link bundle of the one of the two SRLGs; and
generating, based at least in part upon the set of SRLGs and the set of dominance relationships, a packed set of SRLGs, wherein the packed set of SRLGs comprises a subset of the set of SRLGs.