Patent ID: 11888053
Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 2:
3. The method for manufacturing the field-effect transistor according to claim 1, wherein:
in the second step, forming the source electrode comprises forming a first source electrode and a second source electrode on the ohmic cap layer, and forming the drain electrode comprises forming a first drain electrode and a second drain electrode on the ohmic cap layer;
in the third step, the insulating layer is formed on the ohmic cap layer between the first source electrode and the first drain electrode and between the second source electrode and the second drain electrode;
in the fourth step, wherein forming the gate opening portion comprises forming a first gate opening portion and a second gate opening portion are formed in the insulating layer, the first gate opening portion being disposed between the first source electrode and the first drain electrode such that a distance of the first gate opening portion from the first drain electrode is greater than a distance of the first gate opening portion from the first source electrode, the second gate opening portion being disposed between the second source electrode and the second drain electrode such that a distance of the second gate opening portion from the second drain electrode is greater than a distance of the second gate opening portion from the second source electrode;
in the fifth step, forming the plurality of asymmetric recess-forming opening portions comprises forming a plurality of first asymmetric recess-forming opening portions between the first gate opening portion and the first drain electrode within the insulating layer, an opening size of the plurality of first asymmetric recess-forming opening portions in the gate length direction being greater than an opening size the plurality of first asymmetric recess-forming opening portions in the gate width direction, and forming the plurality of asymmetric recess-forming opening portions further comprises forming a plurality of second asymmetric recess-forming opening portions between the second gate opening portion and the second drain electrode within the insulating layer, an opening portion of the plurality of second asymmetric recess-forming opening portions in the gate length direction being greater than an opening size of the plurality of second asymmetric recess-forming opening portions in the gate width direction;
in the sixth step, the ohmic cap layer is etched using, as the mask, the insulating layer to define a first recess region of the recess region below the first gate opening portion and the plurality of first asymmetric recess-forming opening portions and to define a second recess region of the recess region below the second gate opening portion and the plurality of second asymmetric recess-forming opening portions;
in the seventh step, forming the gate electrode comprises forming a first gate electrode on the insulating layer and disposed in the first recess region and the first gate opening portion and forming a second gate electrode on the insulating layer and disposed in the second recess region and the second gate opening portion; and
in the fifth step, the opening size of the first asymmetric recess-forming opening portions in the gate length direction is made different from the opening size of the second asymmetric recess-forming opening portions in the gate length direction.