Patent ID: 11882701
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A semiconductor device comprising:
a substrate having a cell region and a connection region adjacent to the cell region;
a plurality of extension lines in the connection region, the plurality of extension lines sequentially stacked on the substrate;
a plurality of gate electrodes in the cell region, the plurality of gate electrodes sequentially stacked on the substrate, the plurality of gate electrodes connected to corresponding ones of the plurality of extension lines, respectively, to form a plurality of conductive layers;
a plurality of insulating layers alternately between the plurality of conductive layers, first distances between pairs of two neighboring ones of the plurality of extension lines are substantially equal to each other, and at least one of distances between pairs of two neighboring ones of the plurality of gate electrodes is greater than each of the first distances; and
a channel structure passing through the plurality of gate electrodes,
wherein a stack structure comprises the plurality of conductive layers and the plurality of insulating layers, and the stack structure includes a lower channel hole and an upper channel hole communicatively connected to the lower channel hole underneath,
the plurality of extension lines comprise a dummy extension line disposed between the plurality of extension lines,
the plurality of insulating layers comprise a dummy insulating layer on a bottom surface of the dummy extension line, and
a top surface of the dummy extension line is substantially coplanar with a top surface of the lower channel hole.