Patent ID: 11929132
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. A testing system for a semiconductor chip, the testing system being configured for testing a target chip and comprising:
a set unit configured to set a preset number of memory cells in an edge region of the target chip as cells to be tested;
a test unit connected to the set unit and configured to obtain test data after performing a test of read and write functions on the cells to be tested; and
a process unit connected to the test unit, the process unit being configured to obtain, based on the test data, an abnormal chip with abnormal read and write functions, and location information of memory cells with abnormal read and write functions on the abnormal chip, and the process unit being further configured to judge whether an abnormality of read and write functions of the abnormal chip is a block abnormality based on the location information;
wherein the process unit is further configured to determine that the target chip is the abnormal chip based upon the target chip comprising the memory cells with abnormal read and write functions; and
wherein the process unit is further configured to determine the abnormality of read and write functions of the abnormal chip to be the block abnormality when the memory cells with abnormal read and write functions are more than two consecutive full rows or more than two consecutive full columns in the edge region of the memory cells on the abnormal chip.