Patent ID: 11961789
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor package, comprising:
a chip comprising conductive posts exposed at an active surface of the chip;
a redistribution layer disposed on the active surface of the chip, comprising:
a first dielectric layer, including first openings exposing the conductive posts of the chip;
a topmost metallization layer, disposed over the first dielectric layer and electrically connected to the conductive posts, wherein the topmost metallization layer comprises first contact pads and routing traces connected to the first contact pads; and
a second dielectric layer, disposed on the topmost metallization layer and including second openings exposing the first contact pads; and

first under-ball metallurgies patterns disposed on the first contact pads, wherein the first under-ball metallurgy patterns extend on and contact sidewalls and top surfaces of the first contact pads.