Patent ID: 11907043
Assignee: APPLE INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A processor comprising:
a plurality of processing pipelines associated with different tasks, the plurality of processing pipelines including:
a first pipeline having a first memory circuit and a first logic circuit configured to process a physical downlink control channel;
a second pipeline having a second memory circuit and a second logic circuit configured to process a downlink data channel; and
a third pipeline having a third memory circuit and a third logic circuit configured to process one or more uplink data channels; and

a power management circuit configured to determine when to supply power to the first, second, and third memory circuits and the first, second, and third logic circuits, wherein the power management circuit is configured to:
periodically power up the first memory circuit and the first logic circuit to enable a listening operation to detect a data communication request;
power up the second and third memory circuits and the second and third logic circuits when data communication is requested; and
transition the second and third memory circuits and the second and third logic circuits to a lower power state in response to determining that data communication has ended.