Patent ID: 11917817
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 15:
16. An electronic system, comprising:
an input device;
an output device;
a processor device operably coupled to the input device and the output device; and
a memory device operably coupled to the processor device and comprising at least one microelectronic device structure comprising:
a stack structure comprising a vertically alternating sequence of conductive material and insulative material arranged in tiers, the stack structure comprising at least two blocks separated by at least one intervening dielectric structure, each of the at least two blocks comprising:
two elevated regions;
an uppermost stadium structure interposed between the two elevated regions in a first horizontal direction and comprising staircase structures opposing one another in the first horizontal direction, the staircase structures each having steps comprising horizontal ends of an upper group of the tiers of the stack structure;
two additional elevated regions neighboring opposing sides of the uppermost stadium structure in a second horizontal direction perpendicular to the first horizontal direction, upper boundaries of the two additional elevated regions substantially coplanar with upper boundaries of the two elevated regions; and

at least one dielectric slot structure within horizontal boundaries of the uppermost stadium structure in the first horizontal direction and horizontally overlapping the two additional elevated regions of each of the at least two blocks in the second horizontal direction,
the at least one dielectric slot structure only partially vertically extending through and segmenting both of the two additional elevated regions of each of the at least two blocks,
vertically lowermost boundaries of the at least one dielectric slot structure vertically overlying vertically lowermost boundaries of the uppermost stadium structure of each of the at least two blocks such that upper portions of the two additional elevated regions of each of the at least two blocks are respectively partitioned in the first horizontal direction while lower portions of the two additional elevated regions of each of the at least two blocks are respectively substantially continuous in first horizontal direction.