Patent ID: 11876535
Assignee: SILICON MOTION, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 3:
4. The memory controller as claimed in claim 2, wherein in the decoding phase, during each LDPC iterative operation:
the check-node circuit obtains a codeword difference from the variable-node circuit, and calculates the syndrome according to the codeword difference; and
the variable-node circuit performs the following steps:
determining a syndrome weight according to the syndrome from the check-node circuit;
obtaining a previous codeword generated by a previous LDPC decoding iterative operation, and obtaining a channel value that was previously read from a flash memory without accessing a channel-value memory;
determining a bit-flipping algorithm to flip one or more codeword bits in the previous codeword according to the syndrome weight to generate an updated codeword; and
subtracting the previous codeword from the updated codeword to generate the codeword difference.