Patent ID: 11917803
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 13:
14. A method, comprising:
forming on a substrate a stack comprising a plurality of semiconductor layers interleaved by a plurality of sacrificial layers;
forming a first fin element from the stack in a first area of the substrate and a second fin element from the stack in a second area of the substrate;
forming a first dummy gate stack over the first fin element and a second dummy gate stack over the second fin element;
depositing a gate spacer layer over the first dummy gate stack and the second dummy gate stack;
forming a first source/drain recess in the first area and a second source/drain recess in the second area;
depositing a masking layer over the second area while the first area remains exposed;
after the depositing of the masking layer, selectively and partially etching the plurality of sacrificial layers in the first area to form a plurality of inner spacer recesses;
forming a plurality of inner spacer features in the plurality of inner spacer recesses in the first area;
after the forming of the plurality of inner spacer features, removing the masking layer; and
forming a first source/drain feature in the first source/drain recess and a second source/drain feature in the second source/drain recess.