Patent ID: 11966334
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A hardware processor comprising:
an address generation unit to generate a linear address for a memory access request to a memory;
at least one control register comprising a masking bit; and
a memory management unit to mask out a proper subset of bits inside an address space of the linear address for the memory access request based on the masking bit to produce a resultant linear address, and output the resultant linear address,
wherein one of:
the masking bit comprises a supervisor mode masking bit, and the memory management unit is to mask out the proper subset of bits inside the address space of the linear address for the memory access request by an operating system kernel when the supervisor mode masking bit is set,
the masking bit comprises a user mode masking bit, and the memory management unit is to mask out the proper subset of bits inside the address space of the linear address for the memory access request by a user application when the user mode masking bit is set, or
the masking bit comprises the supervisor mode masking bit and the user mode masking bit, and the memory management unit is to not mask out the proper subset of bits inside the address space of the linear address for the memory access request by the operating system kernel to a user pointer when the supervisor mode masking bit is not set and the user mode masking bit is set.