Patent ID: 11929106
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. The memory device according to claim 7, further comprising:
a second memory cell including a second variable resistance element and a second switching element, wherein
the control circuit is further configured to:
execute third detection of applying the first voltage to a third interconnect coupled to the second memory cell, then turning the third interconnect into the floating state, and while the third interconnect is in the floating state, applying the second voltage to a fourth interconnect coupled to the second memory cell to decrease the voltage of the third interconnect, and detecting a third value obtained by decreasing the voltage of the third interconnect from the first voltage;
execute second write for storing the first data in the second memory cell;
execute, following the second write, fourth detection of applying the first voltage to the third interconnect, then turning the third interconnect into a floating state, and while the third interconnect is in the floating state, applying the second voltage to the fourth interconnect to decrease the voltage of the third interconnect, and detecting a fourth value obtained as a result of decrease in the voltage of the third interconnect from the first voltage; and
read third data related to the second memory cell based on the third value and the fourth value,
at least one of the third value and the fourth value is a value during the decrease in the voltage of the third interconnect,
first time from start of the decrease in the voltage of the first interconnect to detection of the first value in the first detection is substantially equal to second time from start of the decrease in the voltage of the first interconnect to detection of the second value in the second detection,
third time from start of the decrease in the voltage of the third interconnect to detection of the third value in the third detection is substantially equal to fourth time from start of the decrease in the voltage of the third interconnect to detection of the fourth value in the fourth detection,
the first memory cell is included in a first group,
when the second memory cell is included in the first group, the first time is substantially equal to the third time, and
when the second memory cell is included in a second group, the first time is different from the third time.