Patent ID: 11929321
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A method for forming a semiconductor device structure, comprising:
forming a first insulating layer over a substrate having a fin structure;
forming a first gate electrode layer in the first insulating layer and across the fin structure;
forming a first source/drain contact electrically connected to a first source/drain region in the fin structure;
forming a second insulating layer over the first insulating layer;
etching the second insulating layer to form a first via opening exposing the first gate electrode layer and a second via opening exposing the first source/drain contact;
forming a first metal via in the first via opening to connect the first gate electrode layer, and a second metal via in the second via opening to connect the first source/drain contact;
forming a third insulating layer over the second insulating layer;
etching the third insulating layer to form a first trench opening exposing the first metal via and a second trench opening exposing the second metal via; and
selectively growing a first metal hump from a top surface of the first metal via and a second metal hump from a top surface of the second metal via.