Patent ID: 11935922
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 8:
9. The semiconductor device of claim 6, further comprising a 1st metal pattern buried in the substrate, and 2nd, 3rd and 4th metal patterns formed above the 2nd transistor,
wherein the 1st metal pattern is connected to the 1st source/drain contact structure to provide one of a positive supply voltage and a negative supply voltage,
wherein the 2nd metal pattern is connected to the 2nd source/drain contact structure,
wherein the 3rd metal pattern is connected to the gate contact structure, and
wherein the 4th metal pattern is connected to the 3rd source/drain contact structure to provide the other of the positive supply voltage and the negative supply voltage.