Patent ID: 11862699
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for manufacturing a semiconductor structure, comprising:
providing a substrate, conductive contact regions being provided in the substrate, and the substrate exposing the conductive contact regions;
forming multiple discrete bit line structures on the substrate, wherein the bit line structures are configured to expose the conductive contact regions, and a top width is smaller than a bottom width of the bit line structures in a direction parallel to an orientation of the bit line structures; and
forming isolation walls including at least one isolation layer on sidewalls of the bit line structures, wherein capacitor contact holes are constituted by regions defined by the isolation walls between adjacent bit line structures, the isolation layer comprises a first isolation part close to the bit line structures and a second isolation part deviating from the bit line structures, wherein in a step of forming the isolation walls, doping doped ions into the second isolation part of the at least one isolation layer, such that a hardness of the second isolation part is greater than that of the first isolation part, or a dielectric constant of the second isolation part is smaller than that of the first isolation part;
wherein forming the isolation walls comprises:
forming a first isolation layer on the sidewalls of the bit line structures, the first isolation layer comprising a first isolation part of the first isolation layer close to the bit line structures and a second isolation part of the first isolation layer deviating from the bit line structures;
doping the second isolation part of the first isolation layer with first doped ions, such that the dielectric constant of the second isolation part of the first isolation layer is smaller than that of the first isolation part of the first isolation layer;
forming a second isolation layer on a side of the first isolation layer deviating from the second isolation part, the second isolation layer comprising a first isolation part of the second isolation layer close to the bit line structures and a second isolation part of the second isolation layer deviating from the bit line structures; and
doping the second isolation part of the second isolation layer with second doped ions, such that the hardness of the second isolation part of the second isolation layer is greater than that of the first isolation part of the second isolation layer.