Patent ID: 11943915
Assignee: SK HYNIX INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 1:
2. The three-dimensional memory device according to claim 1, further comprising:
a plurality of first dielectric patterns, which isolate the plurality of first vertical vias and the plurality of second vertical vias from the plurality of word lines of the lower stack, defined between outer walls of the plurality of first vertical vias and of the plurality of second vertical vias and the plurality of word lines of the lower stack; and
a plurality of second dielectric patterns, which isolate the plurality of third vertical vias and the plurality of fourth vertical vias from the plurality of word lines of the upper stack, defined between outer walls of the plurality of third vertical vias and of the plurality of fourth vertical vias and the plurality of word lines of the upper stack.