Patent ID: 11948989
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 9:
10. A method comprising:
forming a fin structure on a substrate, the fin structure including a first semiconductor layer, a second semiconductor disposed over the first semiconductor layer and a protective dielectric layer disposed over the second semiconductor layer;
removing a first portion of the second semiconductor layer such that a second portion of the second semiconductor layer remains disposed over the first semiconductor layer after the removing of the first portion of the second semiconductor layer;
forming a first spacer feature along a sidewall of the second portion of the second semiconductor layer;
removing the second portion of the second semiconductor layer to form an air gap between the protective dielectric layer and the first semiconductor layer;
forming a gate structure within the air gap, the gate structure including a first gate dielectric and a first gate electrode, the first gate dielectric interfacing with at least one of the protective dielectric layer and the first semiconductor layer; and
forming a second gate dielectric directly on the protective dielectric layer prior to the removing of the first portion of the second semiconductor layer.