Patent ID: 11973127
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A semiconductor structure, comprising:
a gate structure formed over a channel region of a substrate;
an Arsenic-doped region formed in the substrate adjacent to the channel region;
a source/drain structure formed over the Arsenic-doped region, wherein the source/drain structure further comprises:
a first region formed over the Arsenic-doped region;
a second region formed over the first region, wherein a concentration of phosphorus in the second region is different from a concentration of phosphorus in the first region; and
a third region formed over the second region, wherein the concentration of phosphorus in the second region is different from a concentration of phosphorus in the third region; and

a spacer formed on and in physical contact with a sidewall of the first region of the source/drain structure,
wherein a bottommost portion of the first region of the source/drain structure is in direct contact with the Arsenic-doped region.