Patent ID: 11972808
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 3:
4. The memory apparatus as set forth in claim 2, wherein the plurality of strings of rows of the plurality of memory holes comprise a plurality of blocks, the control means includes a read counter configured to count a block read quantity of a plurality of read operations of each of the plurality of blocks and a read timer configured to determine a read time of the plurality of read operations of each of the plurality of blocks, the control means is further configured to:
calculate a block read frequency equal to the block read quantity divided by the read time for each of the plurality of blocks;
identify one of the plurality of blocks is a susceptible block in response to determining the block read frequency is greater than a read frequency threshold; and
check the transistor threshold voltage of the drain-side select gate transistor of at least one of the plurality of strings including semi-circle rows of the one of the plurality of blocks identified as susceptible and insert at least one of the predetermined idle time in the one of the plurality of memory operations and the recovery pulse of a negative voltage to the drain-side select gate transistor of the plurality of memory holes of the at least one of the plurality of strings including semi-circle rows of the one of the plurality of blocks identified as susceptible.