Patent ID: 11894382
Assignee: STMICROELECTRONICS (CROLLES 2) SAS
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 3:
4. The integrated circuit according to claim 1, comprising at least two standard cells called filling cells framing the first standard cell, respectively disposed between the first standard cell and the two second standard cells, respectively butted to the first standard cell and to the two second standard cells, each filling cell including a filling region containing silicon and germanium, adjoined to the active area of at least one of the at least two PMOS transistors of the first standard cell and at least a first polysilicon line located above the filling region and configured to remain electrically floating, the filling regions being separated from the active area of at least one of the at least two PMOS transistors of each second standard cell by an insulating region.