Patent ID: 11908507
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 12:
13. The semiconductor memory device according to claim 12, wherein the memory cell array comprises:
a plurality of memory cell array blocks; and
a plurality of sense amplification blocks arranged between the plurality of memory cell array blocks,
wherein each of the plurality of memory cell array blocks comprises:
a plurality of sub memory cell array blocks;
a plurality of even sub word line driver blocks and odd sub word line driver blocks alternately arranged between the plurality of sub memory cell array blocks; and
a plurality of main word lines crossing the plurality of sub memory cell array blocks,
wherein each of the plurality of sense amplification blocks comprises:
a plurality of sub sense amplification blocks;
a plurality of conjunction blocks arranged between the plurality of sub sense amplification blocks; and
a plurality of selection signal lines arranged crossing the plurality of conjunction blocks,
wherein each of the plurality of sub memory cell array blocks comprises:
a plurality of sub word lines corresponding to each of the plurality of main word lines, and
wherein the sub memory cell array blocks in both sides of each of the plurality of even sub word line driver blocks among the plurality of sub memory cell array blocks are included in the even page memory cell array, and the sub memory cell array blocks arranged in both sides of each of a plurality of odd sub word line driver blocks among the plurality of sub memory cell array blocks are included in the odd page memory cell array.