Patent ID: 11972953
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor structure manufacturing method, comprising:
providing a substrate;
forming a first mask layer on the substrate, the first mask layer having a plurality of strip-shaped first patterns arranged in parallel and configured to form a plurality of strip-shaped continuous active areas arranged in parallel in the substrate;
forming a second mask layer on the first mask layer, the second mask layer having a plurality of strip-shaped second patterns arranged in parallel;
forming a third mask layer on the second mask layer, the third mask layer having a plurality of strip-shaped third patterns arranged in parallel and overlapping the second patterns, wherein the second patterns and the third patterns are configured to sever the first patterns at predetermined positions;
performing layer-by-layer etching, using the first mask layer, the second mask layer, and the third mask layer as masks, to transfer the first patterns, the second patterns, and the third patterns to the substrate to form an array of discrete active areas, wherein the substrate comprises an array area, and the first patterns, the second patterns, and the third patterns are all formed at least in the array area; and
forming a fourth mask layer on the third mask layer, the fourth mask layer having sixth patterns covering at least a portion of the second patterns and at least a portion of the third patterns at an edge portion of the array area, wherein the fourth mask layer is not extended to a portion of the array area other than the edge portion.