Patent ID: 11973032
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An integrated circuit structure, comprising:
a memory bit cell, comprising:
first, second, third and fourth three-dimensional semiconductor bodies parallel along a first direction;
first and second gate lines over the first, second, third and fourth three-dimensional semiconductor bodies, the first and second gate lines each surrounding one or more of the first, second, third and fourth three-dimensional semiconductor bodies, and the first and second gate lines parallel along a second direction, the second direction perpendicular to the first direction; and
first, second and third interconnect lines over the first and second gate lines, the first, second and third interconnect lines parallel along the second direction, wherein the first and second interconnect lines are electrically connected to the first and second gate lines at locations of the first and second gate lines over one or more of the first, second, third and fourth three-dimensional semiconductor bodies, wherein the third interconnect line electrically couples together a pair of gate electrodes of the memory bit cell or electrically couples together a pair of trench contacts of the memory bit cell, and wherein one of the first, second or third interconnect lines is vertically overlapping with one of the first or second gate lines.