Patent ID: 11971741
Assignee: QUALCOMM INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 0:
1. A system, comprising:
a multiplexer having a first input, a second input, a select input, and an output, wherein the first input of the multiplexer is configured to receive a clock signal;
a signal path having an input and an output, wherein the input of the signal path is coupled to the output of the multiplexer; and
a controller coupled to the second input of the multiplexer and the select input of the multiplexer, wherein the controller has an indicator input, and the controller is configured to:
receive a mode indicator signal at the indicator input;
if the mode indicator signal has a first logic value, instruct the multiplexer to select the first input of the multiplexer; and
if the mode indicator signal has a second logic value, instruct the multiplexer to select the second input of the multiplexer, output a control signal to the second input of the multiplexer, and alternately set the control signal high and low over multiple consecutive idle periods.