Patent ID: 11928412
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 3:
4. The design method of claim 3, wherein obtaining the parasitic resistance of each of the preset capacitor units based on the parasitic resistance equivalent test structure comprises:
selecting one of the preset capacitor units as a target preset capacitor unit, defining an equivalent conductive layer of the preset capacitor units by using a preset interface of the conductive layer, on which adjacent preset capacitor units are located, as a separation boundary;
acquiring minimum distances between a boundary of the target preset capacitor unit and a boundary of the equivalent conductive layer on which the target preset capacitor unit is located;
acquiring characteristic quantities of the unit capacitors in the target preset capacitor unit in the arrangement direction of the preset capacitor units and a direction perpendicular to the arrangement direction of the preset capacitor units, the characteristic quantities comprising a number of the unit capacitors, spacings between the unit capacitors, and a line width of each of the unit capacitor; and
acquiring a parasitic resistance of the target preset capacitor unit based on the minimum distances and the characteristic quantities.