Patent ID: 11947835
Assignee: BLACK SESAME TECHNOLOGIES INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. A method performed by an on-chip memory controller, wherein the memory controller is configured to control memory access to a shared memory accessible for a plurality of hardware components that are configured to perform computations, the shared memory comprising a plurality of memory bank groups, each of the memory bank groups comprising one or more memory banks, the method comprising:
communicatively coupling at least a first arbitration controller to a memory bank group of the plurality of memory bank groups, using a first data bus, and a first group of hardware components of the plurality of hardware components, using a second data bus, wherein a first arbitration controller and hardware components of the first group of hardware components are communicatively coupled using a first memory access protocol, wherein a first arbitration controller is configured to:
perform bus arbitrations to determine whether a first hardware component of the first group of hardware components can access the memory bank group, wherein the determination is based at least in part on a priority level associated with the first hardware component, and
in response to determining that the first hardware component can access the memory bank group, determine respective memory banks of the memory bank group for the first hardware component to access using the first memory access protocol;

communicatively coupling a second arbitration controller to the memory bank group using a third data bus, and a second group of hardware components of the plurality of hardware components, using a fourth data bus, wherein the second arbitration controller and hardware components of the second group of hardware components are communicatively coupled using a second memory access protocol distinct from the first memory access protocol, the second memory access protocol including an advanced extensible interface (AXI), wherein the third data bus and fourth data bus are distinct from the first data bus and the second data bus, and wherein the second arbitration controller is configured to:
perform bus arbitrations to determine whether a second hardware component of the second group of hardware components can access the memory bank group, wherein the determination is based at least in part on a priority level associated with the second hardware component; and
in response to determining that the second hardware component can access the memory bank group, determine respective memory banks of the memory bank group for the second hardware component to access using a second memory access protocol different from the first memory access protocol; and

generating instructions for the first hardware component and the second hardware component, determined by the respective bus arbitrations, to access the memory bank group based on the respective priorities of the first hardware component and the second hardware component.