Patent ID: 11870400
Assignee: RICHTEK TECHNOLOGY CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 18:
19. A class-D amplifier circuit, which is configured to operably receive an analog input signal from an analog input node, and to operably convert the analog input signal, thus generating an output signal; the class-D amplifying system comprising:
a pulse width modulator, which is configured to operably generate a pulse width modulation (PWM) signal according to the analog input signal;
an H-bridge (full-bridge) power stage circuit, which is configured to operably generate an output signal according to the PWM signal, wherein the H-bridge power stage circuit is powered by a driving power supply;
a feedback device, which is configured to operably feedback the output signal to the analog input node; and
a common mode (CM) current type digital-to-analog converter (DAC), which is coupled to the analog input node and which is configured to operably generate a CM adjustment current, wherein the CM adjustment current is correlated with one of the following parameters:
(1) a CM voltage of the analog input signal;
(2) the driving power supply; or
(3) the CM voltage of the analog input signal and the driving power supply;
wherein the CM current type DAC is configured to operably determine which of the parameters (1)-(3) that the CM adjustment current is to be correlated with according to one of the following states:
(A) a level state of the output signal;
(B) a level state of the PWM signal; or
(C) the level state of the output signal and the level state of the PWM signal;
wherein in an adaptive voltage position mode, the CM adjustment current is further correlated with a predetermined voltage difference, wherein the predetermined voltage difference is correlated with an amplitude of the output signal, a slope of the output signal and a resistance of the feedback device, wherein in the adaptive voltage position mode, a target value of the CM voltage of the analog input signal is synchronous with and correlated with a CM voltage of the output signal.