Patent ID: 11867584
Assignee: PSEMI CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  B  H | IPC B  G  H

Claim 0:
1. A sensor system subject to a variable parasitic capacitance, the sensor system comprising:
a sensor comprising a sense capacitor with a variable sense capacitance, wherein when an input pressure is sensed by the sensor, the variable sense capacitance is modulated, thereby generating one or more digital output signals indicative of the input pressure;
a readout circuit comprising a converter having an analog input connected to the sense capacitor, and
an offset capacitor operatively charged and discharged out of phase with respect to the sense capacitor;
wherein:
the sensor system uses the offset capacitor, based on an auto-zeroing technique, to sample the analog input of the converter prior to a charging phase of the sensor system so that some effects of the variable parasitic capacitance on the one or more digital output signals are reduced.