Patent ID: 11923001
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
performing a programming operation on a first set of memory cells addressable by a first wordline (WL), wherein the first set of memory cells is comprised by an open translation unit (TU) of memory cells;
determining a difference between a recorded time stamp for a most recently programmed set of memory cells comprised by the open TU and a current time stamp for the open TU;
determining that a current temperature for the open TU and the difference between the recorded time stamp and the current time stamp satisfy a threshold criterion, wherein satisfying the threshold criterion is indicative of a second set of memory cells comprised by the open TU being in a coarse programming state, wherein the second set of memory cells is addressable by a second WL;
reducing a programming state verify level associated with the second WL by a verify level offset;
reducing a programming state gate step size associated with each WL of the open TU by a predefined value; and
performing, using the reduced programming state verify level and the reduced programming state gate step size, a programming operation on the second set of memory cells.