Patent ID: 11886366
Assignee: QUALCOMM INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 22:
23. A data communication apparatus, comprising:
a line driver configured to couple the data communication apparatus to a single-wire serial bus; and
a protocol controller configured to:
determine a duration of a first pulse on the single-wire serial bus;
drive the single-wire serial bus from a first signaling state to a second signaling state through initiating a second pulse during a timeslot associated with the data communication apparatus in an arbitration window that follows the first pulse on the single-wire serial bus when the first pulse has a first duration that corresponds to a first type of sequence start condition (SSC);
present a high impedance to the single-wire serial bus after initiating the second pulse;
receive a Manchester encoded command from a bus master device over the single-wire serial bus when the first pulse has a second duration that corresponds to a second type of SSC; and
respond to the command when the command is addressed to the data communication apparatus.