Patent ID: 11861483
Assignee: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 8:
9. A spike neural network circuit comprising:
a synapse configured to generate an operation signal based on an input spike signal and a weight; and
a neuron configured to generate an output spike signal using a comparator configured to compare a current of a membrane signal generated based on the operation signal with a bias current generated based on a bias signal,
wherein the comparator includes a bias circuit configured to conditionally supply the bias current depending on a voltage of the membrane signal,
wherein the bias current is supplied to the comparator when the voltage of the membrane signal is higher than a threshold voltage, and the supplying of the bias current to the comparator is blocked when the voltage of the membrane signal is lower than the threshold voltage,
wherein the bias circuit includes:
a first transistor connected between a first power supply voltage and a first node and configured to be turned on or turned off depending on the membrane signal;
a second transistor connected between the first node and an output node through which the output spike signal is generated;
a third transistor connected to the output node and configured to generate the bias current; and
a fourth transistor connected between the third transistor and a second power supply voltage and configured to be turned on or turned off based on the voltage of the membrane signal and the threshold voltage.