Patent ID: 11934676
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A method comprising:
receiving a host read memory command that references a set of logical block addresses associated with a set of transfer units of a memory device;
converting the set of logical block addresses to a set of physical block addresses for the set of transfer units of the memory device;
generating a set of device read memory commands based on the set of physical block addresses, wherein each device read memory command in the set of device read memory commands references at least one physical block address in the set of physical block addresses;
generating a first aggregated device read memory command based on a first device read memory command and a second device read memory command in response to determining that the first device read memory command is associated with the second device read memory command;
transferring, by a first level of firmware of a memory subsystem controller, metadata associated with the second device read memory command to a second level of firmware of the memory subsystem controller;
determine, by the second level of firmware of the memory subsystem controller, that the second device read memory command is a last in a series of device read memory commands based on the metadata; and
transferring, in response to the second level of firmware determining that the second device read memory command is the last in the series of device read memory commands, the first aggregated device read memory command to the memory device.