Patent ID: 11862611
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor die assembly, comprising:
a support substrate;
a base semiconductor die on the support substrate;
two or more semiconductor dies stacked on the base semiconductor die;
a molded wall having parallel vertical surfaces on opposing sides of the stacked two or more semiconductor dies and at least partially defining a cavity spaced apart from the stacked two or more semiconductor dies, and wherein the molded wall extends upward from the support substrate; and
a thermal transfer structure (TTS) over and directly attached to a top portion of the molded wall, wherein
the TTS at least partially defines an upper boundary for the cavity and is configured to dissipate heat away from the base semiconductor die and the stacked two or more, semiconductor dies,
the TTS further comprising a first portion extending in a first direction and a second portion extending in a second direction, wherein (1) the first and second directions are different, and (2) the second portion is directly coupled to the base semiconductor die via an adhesive.