Patent ID: 11875844
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device comprising:
a memory cell array including a plurality of static random access memory cells arranged in rows and columns;
a plurality of row decoders connected with the plurality of memory cells through a plurality of word lines;
a plurality of data input/output circuits connected with the plurality of memory cells through a plurality of bit lines; and
control logic including a clock generator configured to generate an internal clock and a tracking circuit configured to track a number of the rows and a number of the columns based on the internal clock,
wherein the tracking circuit includes:
a driver connected with a first wire including a first capacitor corresponding to a length of one of the plurality of word lines and a first resistor corresponding to the length of the one of the plurality of word lines, the driver configured to output a first signal based on a value of the first resistor and a capacitance of the first capacitor;
a first inverter including a first end connected with a second wire including a second resistor corresponding to a length of one of the plurality of bit lines and a second end connected with a third wire including a second capacitor corresponding to the length of the one of the plurality of bit lines, the first inverter configured to output a second signal based on a value of the second resistor, a capacitance of the second capacitor, and the first signal; and
a second inverter configured to output a third signal in response to the second signal,
wherein the second wire and the third wire are identical to a wire through which a power supply voltage is supplied to the plurality of memory cells.