Patent ID: 11903191
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A method comprising:
recessing a semiconductor portion of a semiconductor substrate to form a recess in a memory array region of the semiconductor substrate, the semiconductor substrate having an upper surface in a non-recessed region of the semiconductor substrate, wherein a bottom surface of the recess is a surface of the semiconductor substrate;
depositing a bottom dielectric layer on the bottom surface of the recess;
forming a charge storage layer over the bottom dielectric layer, wherein a portion of the charge storage layer is in the recess;
planarizing the charge storage layer and the bottom dielectric layer;
forming a top dielectric layer over and physically contacting the charge storage layer and the bottom dielectric layer, the top dielectric layer being above the upper surface of the semiconductor substrate;
forming a high-k dielectric layer over the top dielectric layer, wherein after forming the high-k dielectric layer, the top dielectric layer is above a topmost surface of the bottom dielectric layer;
forming a conductive gate over the high-k dielectric layer; and
forming a source region and a drain region in the semiconductor substrate and on opposite sides of the bottom dielectric layer to form a memory device, wherein an array of memory devices is formed in the memory array region when the memory device is formed.