Patent ID: 11870612
Assignee: INTEL CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. An apparatus, comprising:
a host having a host input-output (IO) interface including,
a host transmitter with an adjustable host transmitter termination resister (Rtx_h); and
a host receiver with an adjustable host receiver resister (Rrx_h);

a device having a device IO interface including,
a device transmitter with an adjustable device transmitter termination resister (Rtx_d); and
a device receiver with an adjustable device receiver resister (Rrx_d);

a bi-directional communication link comprising a downlink channel coupled between the host transmitter and the device receiver and an uplink channel coupled between the device transmitter and the host receiver,
wherein the apparatus is configured to calibrate Rtx_h and Rrx_d during link training of the downlink channel and calibrate Rtx_d and Rrx_h during link training of the uplink channel, and wherein the apparatus is configured to set the resistance value of the Rtx_h to a predetermined value and set the resistance value of the Rtx_d to a predetermined value prior to calibrating the Rrx_d and Rrx_h.