Patent ID: 11972192
Assignee: SYNOPSYS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. A system, comprising at least one processor and at least one non-transitory computer storage medium for storing instructions that, when executed by the at least one processor, cause the system to:
receive an integrated circuit (IC) design comprising a plurality of transistor devices;
receive a design rule check (DRC) rules set;
route a segment of a path associated with a first one of the plurality of transistor devices to a first position;
responsive to identifying, by a processor and based at least in part on the DRC rules set, that routing the segment beyond the first position creates a design rule violation, determine whether a force mode input has been received, wherein the force mode causes the routing to bypass the DRC rules set;
responsive to determining that the force mode input has been received, enable the routing of the segment beyond the first position; and
generate an interactive routing interface comprising a graphical indication that the routing of the segment beyond the first position is associated with the design rule violation.