Patent ID: 11934696
Assignee: MICROCHIP TECHNOLOGY INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A method for meeting quality of service (QoS) requirements in a flash controller that includes one or more instruction queues and a neural network engine, the method comprising:
receiving a configuration file for a QoS neural network at the flash controller, the configuration file including weight and bias values for the QoS neural network;
loading the configuration file for the QoS neural network into the neural network engine;
receive a current command at the one or more instruction queue;
identifying feature values corresponding to commands in the one or more instruction queues and loading the identified feature values into the neural network engine;
performing a neural network operation of the QoS neural network in the neural network engine using as input to the neural network operation the identified feature values to predict latency of the current command, wherein the predicted latency of the current command is the latency to complete the current command and includes the latency for performing all commands in the one or more instruction queues that are scheduled to be performed prior to the current command;
comparing the predicted latency to a first latency threshold;
when the predicted latency exceeds the first latency threshold
identifying a potential to the commands in the one or more instruction queues, the potential change defining a plurality of potential-commands;
generating potential-command feature sets corresponding to respective potential-commands;
performing neural network operations using as input to the respective neural network operations feature values of the generated potential-command feature sets to predict a respective potential-latency of the respective potential-commands and comparing the predicted respective potential latency of the respective potential-commands to a second latency threshold to identify a reduced-noise-instruction-queue pattern, and
modifying one or more of the commands in the one or more instruction queues or changing a scheduling order in the one or more instruction queues to correspond to the reduced-noise-instruction-queue pattern:

when the predicted latency does not exceed the latency threshold, not modifying the commands in the one or more instruction queues; and
performing a next command in the one or more instruction queues.