Patent ID: 11892503
Assignee: TOSHIBA TEC KABUSHIKI KAISHA
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 18:
19. A test method for a packaged semiconductor device including an internal wiring connecting a first pad on a first semiconductor chip to a second pad on a second semiconductor chip, the test method comprising:
receiving a test signal at a third pad on the second semiconductor chip, the third pad being electrically connected to a control circuit on the second semiconductor chip;
outputting a first control signal from the control circuit to a power supply circuit on the second semiconductor chip in response to the receiving of the test signal at the third pad, the first control signal causing the power supply circuit to output a current to a wiring connected to the second pad;
outputting a second control signal from the control circuit to a switch in response to the receiving of the test signal at the third pad, the switch being on the wiring connecting the second pad and the power supply circuit and controlling whether current from the power supply circuit reaches the internal wiring via the second pad;
measuring a voltage between a power supply pad and a ground pad, the first pad being electrically connected to a node between the power supply pad and the ground pad; and
detecting a connection state of the internal wiring based on the measuring of the voltage.