Patent ID: 11861484
Assignee: QUALCOMM INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. A neural processing unit (NPU) chip, comprising:
an NPU direct memory access (NDMA) core comprising:
a read engine having a read buffer; and
a write engine having a write buffer;

a bus bridge coupled to the NDMA core;
a network on chip (NoC) coupled to the bus bridge;
a write client coupled to a first memory interface of the NDMA core, the write client comprising a write client buffer used to store NDMA data of the NDMA core;
a read client coupled to a second memory interface of the NDMA core, the read client comprising a read client buffer used to store the NDMA data of the NDMA core; and
a controller coupled to the NDMA core and configured to direct the NDMA core to move data stripes of an image, block by block, from external memory to the read buffer and to the external memory from the write buffer, and configured to direct the NDMA core to perform hardware pre-processing of NDMA data before the read client buffer and post-processing of NDMA data in the write buffer on blocks of a data stripe to process tensors in artificial neural networks.