Patent ID: 11879939
Assignee: NXP B.V.
Field: Measurement (Instruments)
Classification: CPC G  H | IPC G  H

Claim 2:
3. The IC of claim 1, wherein the testing system comprises a counter that is configured to:
receive a third clock signal that is generated based on (i) the first clock signal and (ii) at least one of a group consisting of a first pipeline enable signal and a first division enable signal, wherein the first pipeline enable signal is asserted based on the activation of the capture phase, and during the capture phase, the first pipeline enable signal is de-asserted based on the transition of the first clock enable signal, and wherein during the capture phase, the first division enable signal is asserted based on an assertion of the first clock pulse and de-asserted based on an assertion of the second clock pulse; and
generate a count value based on the third clock signal, wherein when the third clock signal is generated based on the first pipeline enable signal, (i) the third clock signal is same as the first clock signal based on the assertion of the first pipeline enable signal, and the count value is incremented for each clock pulse of the third clock signal, and (ii) the count value when the first pipeline enable signal is de-asserted corresponds to the first count, and wherein when the third clock signal is generated based on the first division enable signal, (i) the third clock signal is same as the first clock signal based on the assertion of the first division enable signal, and the count value is incremented for each clock pulse of the third clock signal, and (ii) the count value when the first division enable signal is de-asserted corresponds to the second count.