Patent ID: 11914515
Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A cache memory device, comprising:
a reservation station, outputting a load instruction; and
a memory order buffer (MOB) circuit, coupled to the reservation station,
wherein the MOB circuit comprises:
a first address generation circuit (AGC), generating a virtual address based on the load instruction from the reservation station;
a compression circuit, coupled to the first AGC, obtaining a higher part of the virtual address from the first AGC and generating a target hash value based on the higher part of the virtual address;
a second AGC, generating a lower part of the virtual address based on the load instruction;
a virtual tag array, coupled to the second AGC, obtaining the lower part of the virtual address from the second AGC and selecting a set of memory units from the virtual tag array; and
a comparator circuit, coupled to the compression circuit and the virtual tag array, comparing the target hash value to a hash value stored by each memory unit of the set of memory units to generate a virtual tag hit signal or a virtual tag miss signal, wherein when the comparator circuit generates the virtual tag miss signal; the MOB circuit transmits the virtual tag miss signal to the reservation station.