Patent ID: 11869967
Assignee: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A method of making an iT-FET semi-conductor device comprising:
a) forming an epitaxial layer doped with impurities of a second conductivity type on a substrate heavily doped with impurities of a first conductivity type wherein the first conductivity type is opposite of the second conductivity type, wherein the substrate acts as a source layer;
b) forming a gate trench through the epitaxial layer and into the source layer;
c) lining the gate trench with an insulating material and forming a gate electrode in the gate trench;
d) forming a heavily doped drain region doped with impurities of the first conductivity type in the epitaxial layer;
d′) forming a drift region doped with impurities of first conductivity type in the epitaxial layer below the heavily doped drain region;
e) forming a shield trench in the epitaxial layer through the heavily doped drain region, and drift region;
f) heavily doping a body contact region with impurities of the second conductivity type at the bottom of the shield trench;
g) lining the shield trench with an insulating material;
h) deepening the shield trench into the source layer through the body contact region and forming a shield structure in the shield trench wherein the shield structure extends upward from the source layer in the shield trench electrically shorting the source region and the body region and wherein the shield structure extends upward into a heavily doped drain region and is insulated from the drain contact region to act as a shield electrode;
i) forming a drain on top of the epitaxial layer.