Patent ID: 11915773
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 18:
19. A nonvolatile memory device, comprising:
a plurality of first metal pads in a cell region;
a plurality of second metal pads in a peripheral region disposed under the cell region, wherein the peripheral region is vertically connected to the cell region by the first metal pads and the second metal pads;
a memory cell array in the cell region and including memory cells and a plurality of wordlines connected to the memory cells;
a voltage generator in the peripheral region and configured to generate a wordline voltage applied to the plurality of wordlines;
a voltage path circuit in the peripheral region, connected between the voltage generator and the memory cell array and configured to transfer the wordline voltage to the plurality of wordlines; and
a wordline defect detection circuit in the peripheral region, connected to a measurement node between the voltage generator and the voltage path circuit and configured to
measure a path leakage current of the voltage path circuit based on a measurement voltage of the measurement node to generate an offset value corresponding to the path leakage current in a compensation mode, and
determine, for each of the plurality of wordlines, whether a defect exists based on the offset value and the measurement voltage in a defect detection mode.