Patent ID: 11910595
Assignee: FUJIAN JINHUA INTEGRATED CIRCUIT CO., LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor memory device, comprising:
a substrate;
a plurality of bit lines arranged on the substrate and arranged along a first direction, wherein each bit line comprises a conductive part and the conductive part comprises four sidewalls, wherein the four sidewalls comprises two ends and two long sides;
a spacer covers parts of the four sidewalls of the bit line, wherein the spacer includes two short spacers covering the two ends of the conductive part and two long spacers covering the two long sides of the conductive part; and
a plurality of storage node contact isolations (SCISOs) located between any two adjacent bit lines, wherein at least one storage node contact isolation contacts and covers at least one of the short spacers of the bit lines.