Patent ID: 11881517
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 17:
18. A computing device, comprising:
a circuit board; and
a memory device coupled to the circuit board and including a memory array, wherein the memory array includes a plurality of memory cells, a memory cell of the plurality of memory cells includes a transistor and a storage cell, and wherein the transistor includes:
a gate electrode above a substrate and coupled to a word line of the memory array;
a channel layer above the substrate, separated from the gate electrode by a gate dielectric layer;
a source electrode in contact with a source area of the channel layer, and coupled to a bit line of the memory array, wherein the channel layer has a channel area with a thickness that is larger than a source area thickness of the source area of the channel layer, and wherein the source area of the channel layer has a bottommost surface at a same level as a bottommost surface of the channel area of the channel layer;
a drain electrode in contact with a drain area of the channel layer, and coupled to a first electrode of the storage cell, wherein the drain area has a drain area thickness that is same as the source area thickness, and wherein the drain area of the channel layer has a bottommost surface at a same level as a bottommost surface of the channel area of the channel layer; and

the storage cell further includes a second electrode coupled to a source line of the memory array.