Patent ID: 11949771
Assignee: nan
Field: Digital communication (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. An integrated circuit comprising:
a central processing unit coupled to a system bus;
a network interface configured to interface with an external device; and
a crypto neuromorphic core coupled to the system bus, the crypto neuromorphic core comprising a processor, an internal bus, and a non-transitory computer-readable memory,
wherein the crypto neuromorphic core is configured to:
store a private key in the non-transitory computer-readable memory accessible to the crypto neuromorphic core but not accessible to the central processing unit and the network interface;
add first data to a blockchain using the private key via the network interface; and
read second data from the blockchain via the network interface, wherein:

the crypto neuromorphic core is configured to operate as either a cold cryptographic wallet or a hot cryptographic wallet,
the private key are not accessible to the crypto neuromorphic core when operating as the cold cryptographic wallet and the private key are accessible to the crypto neuromorphic core when operating as the hot cryptographic wallet, and
the crypto neuromorphic core enters a low power mode when operating as the cold cryptographic wallet and enters a high power mode when operating as the hot cryptographic wallet.