Patent ID: 11862547
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. The substrate of claim 11, wherein the first conductive pad is below the second dielectric layer, wherein the first via vertically extends from the first conductive pad to the third conductive layer, wherein the first via conductively couples the first conductive pad to the first conductive line in the third conductive layer, wherein the second via vertically extends from the third conductive layer to the first conductive layer, wherein the second via conductively couples the first conductive line to the second conductive line in the first conductive layer, wherein the second conductive line conductively couples the second via to the second conductive pad, wherein the second conductive pad is on the second conductive line and the first dielectric layer, and wherein the first dielectric layer is over the second conductive line of the first conductive layer.