Patent ID: 11972154
Assignee: ALLEGRO MICROSYSTEMS, LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A configurable variable-length shift register circuit for adjusting an output data format to a desired bit-length for data communication, the circuit comprising:
a plurality of flip-flops connected in a serial configuration, wherein the plurality of flip-flops is connected to a serial-in line and a clock line, wherein in each flip-flop includes a data input, a clock input configured to receive a clock signal from the clock line, and a data output, and wherein the plurality of flip-flops includes a serial-out line;
a plurality of multiplexers connected to the plurality of flip-flops, wherein each multiplexer includes first and second data inputs and a control input, wherein one of the first and second data inputs is connected to the serial-in line, wherein the control input selects between the data inputs, and wherein each multiplexer includes an output connected to the input of a respective flip-flop;
a nonvolatile memory connected to the plurality of multiplexers and configured to receive a register-length indication, wherein the register-length indication corresponds to a selected number of flip-flops selected for enablement; and
a programming interface connected to the nonvolatile memory and configured to allow a user to input the register-length indication;
wherein the nonvolatile memory is operative to configure the plurality of multiplexers to enable a plurality of enabled flip-flops corresponding in number to the register-length indication, and
wherein the plurality of enabled flip-flops of the variable-length shift register is configured to produce a data output with an output data format having a desired bit-length corresponding to the number of enabled flip-flops.