Patent ID: 11914524
Assignee: QUALCOMM INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. The method of claim 4, wherein:
the respective processor includes one of more of: an instruction fetch unit (IFU) for fetching instructions and associated data from a first memory to a second memory faster than the first memory, a load/store unit (LSU) for executing load and store instructions and generating virtual addresses, a rename/retire/dispatch unit (REU) for register renaming and instruction retirement and dispatching, a memory management unit (MMU) for managing memory access to caches and memory of the one or more processors, and a prefetch engine for fetching instructions or data from the first memory to the second memory in advance; and
the IFU, LSU, REU, MMU, and prefetch engine of the respective processor are withheld from using the respective data item.