Patent ID: 11943207
Assignee: INTEL CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC H  G  Y | IPC G  H

Claim 18:
19. At least one non-transitory machine-readable storage device comprising instructions stored thereupon, which when executed by processing circuitry of an edge computing system, cause the processing circuitry to perform operations comprising:
performing a secure exchange with an edge computing device to negotiate a shared symmetric encryption key, based on a request for data received from the edge computing device;
generating an inline encryption command based on completion of the secure exchange, the inline encryption command including a first address associated with a storage location storing the data, a second address associated with a memory location in at least one memory device, and the shared symmetric encryption key;
retrieving the data from the storage location using the first address of the inline encryption command;
encrypting the data based on the shared symmetric encryption key; and
storing the encrypted data in the at least one memory device using the second address.