Patent ID: 11921578
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 9:
10. The semiconductor device of claim 7, wherein the core circuit includes:
a first memory region configured to output the first internal data stored in the first memory region through a word line activated by the internal read signal and the first failure address that are generated during the read modify write operation, and store the error-corrected first internal data in the first memory region through a word line activated by the internal write signal and the first failure address; and
a second memory region configured to output the second internal data stored in the second memory region through a word line activated by the internal read signal and the second failure address that are generated during the read modify write operation, and store the error-corrected second internal data in the second memory region through a word line activated by the internal write signal and the second failure address.