Patent ID: 11914511
Assignee: APPLE INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A load/store unit comprising:
a store queue configured to queue one or more store memory operations that write data to one or more memory locations; and
an execution circuit coupled to the store queue and configured to execute a load memory operation having an operation size that is larger than an atomicity size implemented for compliance with a memory ordering model, wherein the execution circuit is configured to detect that the load memory operation reads at least one byte that is written by a first store memory operation represented in the store queue, and wherein the load memory operation has a plurality of registers as targets for data read during execution of the load memory operation, and wherein the execution circuit is configured to permit forwarding of data from the first store memory operation in the store queue for the load memory operation in the case that the data from the store queue is partial data for the load memory operation and remaining data for the load memory operation is sourced from a different source than that first store memory operation as long as each register of the plurality of registers obtains a complete set of data from a single source.