Patent ID: 11936390
Assignee: ZHEJIANG UNIVERSITY
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  Y | IPC H

Claim 1:
2. The low-power fractional-N phase-locked loop circuit according to claim 1, wherein when the phase detector is a constant slope sampling circuit, a timing logic of the phase detector is as follows:
when a rising edge of one of the feedback signal or the reference signal arrives, a charging signal controls the charging switch to be turned on, so that the current source charges the charging capacitor;
when the rising edge of the other one of the feedback signal or the reference signal arrives, the charging signal controls the charging switch to be turned off and stops the current source from charging the charging capacitor, while a sampling signal controls the holding switch to be turned on, and the holding capacitor samples and holds a voltage on the charging capacitor;
after the sampling and holding is completed, the sampling signal controls the holding switch to be turned off, a pre-charging signal controls the pre-charging switch to be turned on, an output of the digital-to-voltage converter is connected to the charging capacitor, and the digital-to-voltage converter receives a compensation signal of the digital logic processor to adjust an initial charging voltage on the charging capacitor; after pre-charging is completed, the pre-charging signal controls the pre-charging switch to be turned off and waits for the charging switch to be turned on.