Patent ID: 11868258
Assignee: APPLE INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. A coherent agent circuit comprising:
one or more caches to cache memory data; and
a control circuit coupled to the one or more caches, wherein:
the control circuit is configured to receive a message from a coherency controller circuit when the one or more caches has a cached copy of a first cache block that has been requested by a different coherent agent circuit,
the message requests a state change in the state of the cached copy in the one or more caches,
the message includes an identifier of a first state in the one or more caches according to a directory in the coherency controller circuit,
the control circuit is configured to compare the first state of the first cache block to a second state of the first cache block in the one or more caches, and
the control circuit is configured to delay processing of the message based on the first state not matching the second state until the second state is changed to the first state.