Patent ID: 11894926
Assignee: KANDOU LABS, S.A.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 28:
29. An apparatus comprising:
a digital data buffer circuit having an input and a plurality of digital digital data buffer outputs, the digital data buffer configured to obtain a set of information bits at the input, and to sequentially allocate data bytes of the stream of information bits to the plurality of digital data buffer outputs;
a plurality of parallel FEC-encoders, each FEC-encoder connected to a respective digital data buffer output, the plurality of parallel FEC-encoders configured to generate a plurality of parallel FEC-encoded data bytes;
an analog physical layer (PHY) circuit comprising a plurality of transport channels; and
a plurality of multiplexing circuits configured to:
output, in a first interleaved order, a first set of FEC-encoded bytes obtained from the plurality of FEC encoders to respective transport channels of the plurality of transport channels for parallel transmission during a plurality of signaling intervals; and
output, in a second interleaved order, a second set of FEC-encoded data bytes obtained from the plurality of FEC encoders to respective transport channels of the plurality of transport channels for parallel transmission during a subsequent plurality of signaling intervals.