Patent ID: 11963357
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 19:
20. A nonvolatile memory device comprising:
a first mold structure including a first surface and a second surface opposite to each other, the first mold structure including a plurality of first gate electrodes stacked sequentially in a first direction from the first surface toward the second surface;
a source structure extending along the first surface of the first mold structure, and formed on the first surface of the first mold structure;
a channel hole extending from the second surface toward the first surface, and penetrating the first mold structure;
an impurity pattern connected to the source structure, and formed in the channel hole;
a semiconductor pattern extending from the impurity pattern toward the second surface of the first mold structure, and formed in the channel hole;
a second mold structure including a third surface and a fourth surface opposite to each other, the second mold structure including a plurality of second gate electrodes stacked sequentially in a first direction from the third surface toward the fourth surface;
a bit line disposed between the first mold structure and the second mold structure;
a substrate facing the fourth surface of the second mold structure;
a peripheral circuit element formed on the substrate;
a first inter-wiring insulation film which covers a first bonding pad, and is formed on the fourth surface of the second mold structure; and
a second inter-wiring insulation film which covers a second bonding pad bonded to the first bonding pad and is interposed between the substrate and the first inter-wiring insulation film,
wherein the impurity pattern includes a first region contacting with the source structure, side walls extending along the channel hole and a second region facing the first region and contacting with the semiconductor pattern.