Patent ID: 11869579
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. A page buffer circuit comprising:
a plurality of page buffers connected to a plurality of bitlines,
wherein each of the plurality of page buffers comprises a bitline selection transistor configured to connect a corresponding bitline of the plurality of bitlines to a sensing node, a precharge circuit configured to precharge the sensing node, and a dynamic latch circuit configured to store data in a storage node,
wherein each of the plurality of page buffers is configured to refresh the data stored in the storage node through charge sharing between the storage node and the sensing node,
wherein the dynamic latch circuit includes a read transistor and a write transistor, the read transistor is configured to connect the sensing node to a storage transistor in response to a read signal, the write transistor is configured to connect the sensing node to the storage node in response to a write signal, and the storage transistor is configured to connect the read transistor to a ground voltage in response to a voltage of the storage node,
wherein each of the plurality of page buffers is configured to perform at least one of
a first refresh operation that, in a case where the data stored in the storage node represent a first state, stores inverted data representing a second state in the storage node, and
a first refresh process that, in a case where the data stored in the storage node represent the second state, stores inverted data representing the first state in the storage node,

wherein, to perform the first refresh operation that stores inverted data representing the second state in the storage node,
the precharge circuit is configured to precharge the sensing node to a power supply voltage in response to a load signal, the read transistor is configured to turn on in response to the read signal to provide a turned-on read transistor,
the storage transistor is configured to be turned on by a first voltage corresponding to the first state of the data of the storage node to provide a turned-on storage transistor,
the turned-on read transistor and the turned-on storage transistor are configured to provide the ground voltage to the sensing node such that the inverted data representing the second state are stored in the sensing node,
the write transistor is configured to turn on in response to the write signal to provide a turned-on write transistor, and
the turned-on write transistor connects the sensing node to the storage node such that the inverted data representing the second state are stored in the storage node by the charge sharing between the storage node and the sensing node, and

wherein, to perform the first refresh process that stores inverted data representing the first state in the storage node,
the precharge circuit is configured to precharge the sensing node to the power supply voltage in response to the load signal,
the read transistor is configured to turn on in response to the read signal to provide the turned-on read transistor,
the storage transistor is configured to be turned off by a second voltage corresponding to the second state of the data of the storage node to provide a turned-off storage transistor,
the ground voltage is not provided to the sensing node by the turned-off storage transistor such that the sensing node maintains the power supply voltage corresponding to the inverted data having the first state, and
the write transistor is configured to turn on in response to the write signal to provide the turned-on write transistor and the turned-on write transistor connects the sensing node to the storage node such that the inverted data representing the first state are stored in the storage node by the charge sharing between the storage node and the sensing node.