Patent ID: 11934691
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 18:
19. A system comprising:
a first device including a first interconnect part including at least one receiver and at least one transmitter, the first interconnect part performing link communication through an available transmission lane connected to the at least one transmitter and an available reception lane connected to the at least one receiver; and
a second device including a second interconnect part including at least one receiver and at least one transmitter, the second interconnect part performing link communication through an available transmission lane connected to the at least one transmitter and an available reception lane of the at least one receiver;
wherein the performing of the link communication between the first device and the second device comprises:
performing initialization in a high speed mode, in both directions, between the first device and the second device, based on a high speed link up message transmitted by the first device;
discovering connected data lanes between the first device and the second device, based on a first trigger event on the available transmission lanes transmitted by both of the first and second devices, the first trigger event including a physical lane number of the available transmission lane of each of the first device and the second device;
realigning data lanes between the first device and the second device, based on a second trigger event on the available transmission lanes transmitted by both of the first and second devices, the second trigger event including information about connected transmission lanes of each of the first device and the second device;
matching logical data lane numbers of the connected data lanes between the first device and the second device, based on a third trigger event on the available transmission lanes transmitted by both of the first and second devices, the third trigger event including logical lane numbers of the connected transmission lanes of each of the first device and the second device; and
exchanging information about a capability of a counterpart device on the available transmission lanes between the first device and the second device,
wherein the high speed link up message includes transitioning a line in the connected data lane of the first device from a zero differential line voltage DIF-Z to an activate period having a negative differential line voltage DIF-N, and
wherein, when a length of the activate period is less than a first time, the first device and the second device enter the high speed mode.