Patent ID: 11901009
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. An address decoding circuit, comprising: a plurality of decoding unit each corresponding to a bank group, wherein
each decoding unit comprises a plurality of first Negated AND (NAND) gates, an address selection signal outputted by each first NAND gate is configured to control a corresponding bank in the bank group corresponding to the decoding unit, and the first NAND gate includes a first input end connected to an address signal of a bank corresponding to the first NAND gate and a second input end connected to an output end of a second NAND gate or an output end of a third NAND gate;
the second NAND gate includes a first input end connected to an enable signal and a second input end connected to a control signal, and the third NAND gate includes a first input end connected to the enable signal and a second input end connected to an inverted signal of the control signal.