Patent ID: 11923043
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: nan (nan)
Classification: CPC nan | IPC G  H

Claim 2:
3. The memory of claim 1, wherein the integral unit is configured to:
when the first input terminal of the integral unit receives one of the first internal signal and the second internal signal, and the second input terminal of the integral unit receives another one of the second internal signal and the first internal signal,
in response to an inversion identification signal being at a low level, receive, through the first input terminal, the first internal signal, and in response to the inversion identification signal being at a high level, receive, through the first input terminal, the second internal signal; and
in response to the inversion identification signal being at the low level, receive, through the second input terminal, the second internal signal, and in response to the inversion identification signal being at the high level, receive, through the second input terminal, the first internal signal;, or,
when the first input terminal of the integral unit receives one of the first oscillation signal and the second oscillation signal, and the second input terminal of the integral unit receives another one of the second oscillation signal and the first oscillation signal,
in response to the inversion identification signal being at the low level, receive, through the first input terminal, the first oscillation signal, and in response to the inversion identification signal being at the high level, receive, through the first input terminal, the second oscillation signal; and
in response to the inversion identification signal being at the low level, receive, through the second input terminal, the second oscillation signal, and in response to the inversion identification signal being at the high level, receive, through the second input terminal, the first oscillation signal.