Patent ID: 11861232
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. A storage system, comprising:
a processor, configured to:
enter a write data copy mode in response to a write-copy enable signal,
define at least two groups of data in multiple groups of data exported from multiple data ports as a category in the write data copy mode when the at least two groups of data are the same,
generate an identification signal that is used to indicate a data copy, a first drive signal and a second drive signal in response to the write-copy enable signal and the multiple groups of data, and
send the identification signal to a memory array;

multiple data channels, wherein:
each of the multiple data channels is a transmission path for transmitting a group of data between an interface of multiple interfaces of the memory array and a data port of the multiple data ports;
a data channel corresponding to one group of data in the category is activated in response to the first drive signal to transmit the one group of data in the category to one interface of the memory array; and
a data channel corresponding to another group of data in the category is disconnected in response to the second drive signal to disconnect a transmission path between a data port corresponding to the another group of data in the category and another interface of the memory array;

wherein the memory array, in response to the write-copy enable signal and the identification signal, copies the one group of data in the category to the another interface that is of the memory array and that corresponds to the another group of data in the category.