Patent ID: 11962309
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G  Y | IPC H

Claim 5:
6. The phase adjusting circuit of claim 1, wherein the phase adjusting circuit is applied to a memory, and the comparison circuit comprises a duty cycle sub-circuit, a preprocessing sub-circuit, and a sampling sub-circuit; wherein,
the duty cycle sub-circuit is configured to receive the first detection signal and the second detection signal, and perform duty cycle comparison of the first detection signal and the second detection signal to obtain a comparison result signal; wherein the comparison result signal is in a first level state in response to a duty cycle of the first detection signal being higher than a duty cycle of the second detection signal, or the comparison result signal is in a second level state in response to a duty cycle of the first detection signal being lower than a duty cycle of the second detection signal;
the preprocessing sub-circuit is configured to receive a main clock signal of the memory, and perform frequency division of the main clock signal to obtain a sampling clock signal; and
the sampling sub-circuit is configured to receive the sampling clock signal and the comparison result signal, and perform sampling of the comparison result signal based on the sampling clock signal to obtain the counting indication signal.