Patent ID: 11886347
Assignee: XI'AN JIAOTONG UNIVERSITY
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. Computing architecture, comprising an off-chip memory, an on-chip cache unit, a transmitting unit, a pre-recombination network, a post-recombination network, a main computing array, a data dependence controller and a global scheduler, wherein
the off-chip memory is configured to store all large-scale data in a format of tiles, wherein the large-scale data is divided into a plurality of tiles of the same size;
the on-chip cache unit is configured to store data of the tiles and dependence data required for computing;
the transmitting unit is configured to read the data of the tiles from the on-chip cache unit according to a sequence specified by a scheduling algorithm and sending the data of the tiles to the pre-recombination network;
the main computing array is configured to compute data of the tiles from the pre-recombination network;
the pre-recombination network is configured to carry out arbitrary data recombination on the data of the tiles before the data of the tiles is computed;
the post-recombination network is configured to carry out arbitrary data recombination on the data of the tiles after the data of the tiles is computed;
the data dependence controller is configured to process a data dependence relationship between the data of the tiles; and
the global scheduler is configured to execute a preset scheduling algorithm to control prefetching, transmitting, computing, data recombination and data dependence relationship processing of the data of the tiles.