Patent ID: 11887975
Assignee: DAICEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 2:
3. The semiconductor device manufacturing method according to claim 2, the method further comprising prior to the multilayering step:
a preparation step of preparing at least one additional reinforced wafer having a laminated structure that includes a wafer including an element forming surface and a back surface opposite therefrom, a supporting substrate, and a temporary adhesive layer forming temporary adhesion, the temporary adhesive layer being provided between the supporting substrate and a side of the element forming surface of the wafer;
a step of forming a thinned wafer by grinding the wafer in each of the additional reinforced wafers from a side of the back surface of the wafer;
at least one additional bonding step in which the side of the back surface of the thinned wafer in the additional reinforced wafer is bonded through an adhesive to the side of the element forming surface of the thinned wafer of at least one of the first wafer laminates; and
a removal step of removing the supporting substrate of the first wafer laminate that has been subjected to the additional bonding step.