Patent ID: 11860734
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 12:
13. The semiconductor memory device of claim 9, wherein the ECC decoder comprises:
a syndrome generation circuit configured to generate a syndrome based on the parity check matrix, the main data, and the first parity data in the normal mode, and to generate the syndrome based on the modified parity check matrix, the main data, and the second parity data in the poison mode;
a modified syndrome generator configured to generate a modified syndrome by selectively replacing a first syndrome bit of the syndrome with the first parity bit and by replacing second syndrome bits associated with the first parity vector that was changed among syndrome bits of the syndrome except the first syndrome bit with a result of performing an XOR operation on each of the second parity bits and the first parity bit;
an error locator configured to detect an error in the main data or detect an error in the main data and the poison flag based on the modified syndrome and configured to output an error vector indicating a position of the error that was detected; and
an error corrector configured to correct the error in the main data or correct the error in the main data and the poison flag based on the error vector and configured to output a corrected main data or a corrected poison flag.