Patent ID: 11916574
Assignee: MARVELL ASIA PTE LTD
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 39:
40. A receiver circuit comprising:
a first detector configured i) to detect presence of errors among codeword bits that are recovered from a set of decisions, the set of decisions constituting estimates of bit values transmitted to the receiver circuit, and ii) to generate an enable signal indicative of whether errors have been detected among the recovered codeword bits, without identifying or correcting decisions of the set of decisions that are in error;
an error correction circuit configured to receive the set of decisions, and in response to the enable signal: i) to detect bit error sequences in the set of decisions; each of the bit error sequences being defined by respective predetermined patterns of error bits; ii) to determine for respective bit error sequences a likelihood of the respective bit error sequences occurring; iii) to select one or more of the detected bit error sequences most likely to include an actual error; and iv) to correct the errors in the recovered codeword bits among the one or more detected bit error sequences selected as most likely to include the actual error;
a demapper configured to invert a mapping of symbols to decisions to generate the recovered codeword bits from the set of decisions; and
a selector configured, based on the enable signal, to select an output of the demapper or an output of the error correction circuit.