Patent ID: 11869835
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A method of manufacturing a semiconductor package, the method comprising:
forming a protective insulating layer;
forming a first insulating layer having a first opening on the protective insulating layer;
forming a pad having an upper portion and a lower portion, the upper portion of the pad being located on the first insulating layer and the lower portion of the pad being located in the first opening, and the upper portion having a greater horizontal maximum length than the lower portion;
forming a second insulating layer on the first insulating layer and the pad;
forming a first conductive pattern on the second insulating layer and the pad, the first conductive pattern including a first line portion and a first via portion protruding downward from the first line portion, the first via contacting the pad;
forming a third insulating layer on the second insulating layer and the first conductive pattern;
forming a second conductive pattern on the third insulating layer, the second conductive pattern including a second line portion and a second via portion protruding downward from the second line portion, the second via portion contacting the first line portion of the first conductive pattern;
attaching a semiconductor chip electrically connected to the second conductive pattern on third insulating layer and the second conductive pattern;
forming a second opening in the protective insulating layer; and
forming a bump, a portion of the bump being located in the second opening;
wherein a lower surface of the first insulating layer and a lower surface of the lower portion of the pad are coplanar.