Patent ID: 11894432
Assignee: STMICROELECTRONICS S.R.L.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. A process for manufacturing a vertical-conduction semiconductor device, the process comprising:
providing a silicon substrate having a front face and a rear face;
forming a front-side structure on the front face of the silicon substrate, the front-side structure having at least one current-conduction region at a respective front face; and
forming a back side metal structure on the rear face of the silicon substrate and in electrical contact with the silicon substrate, the back side metal structure including an overlapped stack of metal layers,
the forming of the back side metal structure including:
forming a first metal layer and a silicide region, the silicide region being between the rear face of the silicon substrate and the first metal layer, the silicide region being in electrical contact with the rear face of the silicon substrate, the forming of the first metal layer being carried out by PVD (Physical Vapour Deposition), which is controlled to reach a temperature that triggers formation, during the PVD, of the silicide region; and
forming a second metal layer on the first metal layer.