Patent ID: 11882691
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A semiconductor device comprising:
a substrate;
word lines buried in the substrate;
bit line structures disposed on the substrate, each bit line structure, of the bit lines structures, including a bit line and a mask pattern on the bit line, the mask pattern having a lower mask pattern and an upper mask pattern on the lower mask pattern;
storage node contacts between the bit line structures;
a spacer on a sidewall of the bit line structures;
landing pads on the storage node contacts; and
a capacitor on the landing pad, the capacitor including lower electrodes, upper electrode, and dielectric layer between the lower electrodes and the upper electrode, wherein
a first width of the lower mask pattern in a first direction is greater than a second width of an upper portion of the upper mask pattern in the first direction, the first direction being parallel to a surface of the substrate,
the upper mask pattern is thicker than the lower mask pattern in a second direction, the second direction being perpendicular to the surface of the substrate,
the lower mask pattern has a first line shape and the upper mask pattern has a second line shape that is aligned with the lower mask pattern,
levels of bottom surfaces of the bit lines are at a same height,
levels of top surfaces of the bit lines are at a same height,
a thickness of the mask pattern in the second direction is greater than a thickness of the bit line in the second direction, and
the upper mask pattern is above the lower mask pattern.