Patent ID: 11908820
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 16:
17. A method, comprising:
providing a first structure comprising a first solder metallurgy on a first bond pad of a die;
providing a second structure comprising a second solder metallurgy on the first structure;
contacting the second structure to a second bond pad of an integrated circuit (IC) package;
reflowing, prior to underfill, the second structure at a first temperature below a liquidus temperature of the first structure to form a first solder joint between the second structure and the second bond pad;
forming an underfill material between the die and the IC package and adjacent the first solder joint; and
reflowing, after said forming the underfill material, the first and second structures at a second temperature above the liquidus temperature of the first structure to form a second solder joint between the first bond pad and the second bond pad.