Patent ID: 11894060
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A non-volatile memory device, comprising:
a control circuit configured to connect to one or more arrays, each array comprising a plurality of blocks each of a plurality of non-volatile memory cells, the control circuit configured to:
receive a write command to program a first set of data to a first of the one or more arrays in a first format;
determine whether the write command is a host write command;
in response to determining that the write command is a host write command, write the first set of data into the first array in the first format using a first programming algorithm;
determine whether the write command is a background write command;
in response to determining that the write command is a background write command, write the first set of data into the first array in the first format using a second programming algorithm, the second programming algorithm being of a slower write speed than the first programming algorithm; and
maintain, for each of the blocks of the first array, a count of a number of program/erase cycles experienced by the block, where a write to the block using the first programming algorithm is weighted more in the count than a write to the block using the second programming algorithm.