Patent ID: 11922131
Assignee: APPLIED MATERIALS, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 15:
16. An apparatus for performing vector-matrix multiplication, the apparatus comprising:
a plurality of one-bit digital to analog converters (DACs) that convert an input vector comprising a plurality of binary-encoded values into a plurality of analog signals;
means for sequentially performing, using an analog vector matrix multiplier and based on bit-order, vector-matrix multiplication operations using a weighting matrix for the plurality of analog signals to generate analog outputs of the analog vector matrix multiplier;
means for sequentially performing an analog-to-digital (ADC) operation on the analog outputs of the analog vector matrix multiplier to generate binary partial output vectors; and
means for combining the binary partial output vectors to generate a result of the vector-matrix multiplication.