Patent ID: 11908528
Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. An integrated circuit, comprising:
a memory array including a plurality of memory cells;
a mode selector coupled to the memory cells and configured to output a mode selection code to select a charge pump operating mode from a plurality of charge pump operating modes;
a logic circuit coupled to the mode selector and configured to receive the mode selection code and to output switch control signals based on the charge pump mode selection code;
a charge pump coupled to the memory array and including a plurality of charge pump stages; and
a plurality of switches configured to receive the switch control signals from the logic circuit and to selectively couple the charge pump stages in series, in parallel, and in parallel groups of series coupled charge pump stages based on the switch control signals, wherein the logic circuit includes a plurality of level shifters each coupled to an output of a respective charge pump stage and configured to receive at least a portion of the selection code and to shift the at least a portion of the selection code to a level of the respective charge pump stage.