Patent ID: 11899985
Assignee: DREAMBIG SEMICONDUCTOR INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G

Claim 7:
8. A method to control a content addressable memory circuit that includes a memory device array including multiple memory devices coupled for simultaneous access to memory address locations that share a memory address, the method comprising:
storing multiple data sets;
wherein each data set includes key values is stored within a different assigned memory address range within the memory array;
storing multiple virtual hash tables in one or more non-transitory memories;
wherein each virtual hash table associates hash values with memory addresses within a different one of the assigned memory address ranges;
using an information structure to indicate different assigned memory address ranges for two or more of the data sets;
receiving a key value and a data set identifier;
determining a hash value, based upon a received key value and upon an assigned memory address range indicated in the information structure for a data set identified by a received data set identifier; and
using a virtual hash table, that associates hash values with memory addresses within the assigned memory address range indicated in the information structure for the data set identified by the received data set identifier, to access a memory address based upon the determined hash value.