Patent ID: 11907141
Assignee: QUALCOMM INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. A computing device, comprising:
means for receiving a first memory access command and a first address at which to implement the first memory access command in a logical rank;
means for generating a first signal configured to indicate to a first memory device of the logical rank to implement the first memory access command via a first partial channel;
means for sending the first signal to the first memory device;
means for generating a second signal configured to indicate to a second memory device of the logical rank that is different from the first memory device to implement the first memory access command via a second partial channel;
means for sending the second signal to the second memory device; and
means for determining whether the first address at which to implement the first memory access command in the logical rank is at the logical rank,
wherein means for generating the first signal, means for sending the first signal, means for generating the second signal, and means for sending the second signal are implemented in response to determining that the first address at which to implement the first memory access command in the logical rank is at the logical rank.