Patent ID: 11961582
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. A driving method of a shift register unit according claim 1, comprising a first driving cycle and/or a second driving cycle;
wherein in the first driving cycle, the driving method comprises:
in a first input phase, loading a first level signal to the input signal terminal, loading the first level signal to the first clock signal terminal, loading a second level signal to the second clock signal terminal, loading the first level signal to the first control signal terminal, and loading the second level signal to the second control signal terminal;
in a first output phase, loading the second level signal to the input signal terminal, loading the second level signal to the first clock signal terminal, loading the first level signal to the second clock signal terminal, loading the first level signal to the first control signal terminal, and loading the second level signal to the second control signal terminal; and
in a first reset phase, loading the second level signal to the input signal terminal, loading the first level signal to the first clock signal terminal, loading the second level signal to the second clock signal terminal, loading the first level signal to the first control signal terminal, and loading the second level signal to the second control signal terminal; and
in the second driving cycle, the method comprises:
in a second input phase, loading the first level signal to the input signal terminal, loading the first level signal to the first clock signal terminal, loading the second level signal to the second clock signal terminal, loading the second level signal to the first control signal terminal, and loading the first level signal to the second control signal terminal;
in a second output phase, loading the second level signal to the input signal terminal, loading the second level signal to the first clock signal terminal, loading the first level signal to the second clock signal terminal, loading the second level signal to the first control signal terminal, and loading the first level signal to the second control signal terminal; and
in a second reset phase, loading the second level signal to the input signal terminal, loading the first level signal to the first clock signal terminal, loading the second level signal to the second clock signal terminal, loading the second level signal to the first control signal terminal, and loading the first level signal to the second control signal terminal, wherein the first level signal is a low level signal and the second level signal is a high level signal.