Patent ID: 11906573
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Measurement (Instruments)
Classification: CPC G | IPC G

Claim 7:
8. A testing module for a semiconductor wafer-form package, comprising:
a circuit board structure, comprising two edge regions and a main region disposed therebetween;
first connectors, disposed over the edge regions and connected to the circuit board structure;
a first connecting structure, disposed over and distant from the circuit board structure;
second connectors and third connectors, disposed over and in contact with the first connecting structure, wherein the third connectors are configured to transmit electric signals for testing the semiconductor wafer-form package being placed over the main region; and
a first bridge connector, electrically coupling the circuit board structure and the first connecting structure by connecting the second connectors and the first connectors,
wherein a projection of the semiconductor wafer-form package is overlapped with the third connectors along a stacking direction of the circuit board structure and the first connectors.