Patent ID: 11963358
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A semiconductor memory device, comprising:
a peripheral logic structures including a peripheral circuit on a base substrate;
a horizontal conductive substrate extending along an upper surface of the peripheral logic structure;
a stacked structure including a plurality of metal lines stacked in a first direction on the horizontal conductive substrate, the plurality of metal lines including an uppermost metal line;
a semiconductor conduction line on the uppermost metal line of the plurality of metal lines, the semiconductor conduction line including polycrystalline silicon;
a vertical structure including an upper vertical structure penetrating the semiconductor conduction line and a lower vertical structure penetrating the stacked structure, and connected to the horizontal conductive substrate, a stacked structure of the upper vertical structure being different from a stacked structure of the lower vertical structure; and
a cutting line through the plurality of metal lines and the semiconductor conduction line, the cutting line including:
an upper cutting line through the semiconductor conduction line, and
a lower cutting line through the plurality of metal lines, a width of the upper cutting line being greater than a width between two extension lines extending from sidewalls of the lower cutting line on a lower surface of the semiconductor conduction line.