Patent ID: 11948626
Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 9:
10. A semiconductor device comprising:
a driver circuit comprising a plurality of transistors using a silicon substrate for channels; and
an element layer provided by stacking a plurality of transistor layers,
wherein the element layer comprises a first transistor layer and a second transistor layer comprising a plurality of transistors using a metal oxide for channels,
wherein the first transistor layer and the second transistor layer are over the silicon substrate,
wherein the first transistor layer comprises a first memory cell comprising a first transistor and a first capacitor,
wherein the first transistor is electrically connected to a first local bit line,
wherein the second transistor layer comprises a second transistor whose gate is electrically connected to the first local bit line and a first correction circuit electrically connected to the second transistor,
wherein the first correction circuit is electrically connected to a first global bit line, and
wherein the first correction circuit is configured to hold a voltage corresponding to a threshold voltage of the second transistor in the gate of the second transistor.