Patent ID: 11907827
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. A method, comprising:
for a plurality of layers of a deep neural network inference:
updating configuration descriptor registers used to describe a schedule for a current layer of the plurality of layers;
based at least in part on the configuration descriptor registers, loading tensor data into a plurality of processing engines;
using the loaded tensor data, performing computations using the plurality of processing engines for the deep neural network inference;
after the computations are performed, extracting output data; and
reorganizing the extracted output data to memory banks based on a schedule for a next layer of the plurality of layers by reshaping the extracted output data for storage in the memory banks to reduce a number of accesses to the memory banks for the next layer by changing a shape of how the extracted output data is stored in the memory banks based at least in part on a type of the next layer.