Patent ID: 11924312
Assignee: MICROCHIP TECHNOLOGY INCORPORATED
Field: Digital communication (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. An EtherCAT device configured to be included in an EtherCAT network with an EtherCAT master node, the EtherCAT device comprising:
a processor configured to operate in a sleep mode and in a normal operating mode; and
a network interface card (NIC) including circuitry configured to:
receive incoming EtherCAT packets from the EtherCAT network originally issued by the EtherCAT master node; and
while the processor is in the sleep mode:
parse the incoming EtherCAT packets;
determine whether a given incoming EtherCAT packet is a wake-on-LAN (WoL) packet by:
a determination that the given incoming EtherCAT packet includes an address of another EtherCAT device;
a determination that the given incoming EtherCAT packet includes a predetermined value within a payload;
a determination that the given incoming EtherCAT packet includes an address of the EtherCAT device;
a determination that the given incoming EtherCAT packet includes an address of another EtherCAT device; or
a determination that the given incoming EtherCAT packet includes an address of the EtherCAT master node;

based on a determination that the given incoming EtherCAT packet is a WoL packet, generate a wake signal to the processor; and
forward the given incoming EtherCAT packet to another node in the EtherCAT network.