Patent ID: 11894059
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. The memory system according to claim 11,
wherein the plural non-volatile memory cells in the memory device are coupled to each other via a single word line,
wherein each of the plural non-volatile memory cells is coupled to a different bit line, and
wherein the memory device further includes a string including:
a first transistor configured to operate in response to a first control voltage applied to a drain select line (DSL);
a second transistor configured to operate in response to a second control voltage applied to a string select line (SSL);
a non-volatile memory cell among the plural non-volatile memory cells; and
the other non-volatile memory cells coupled serially to the non-volatile memory cell between the first transistor and the second transistor, and
wherein the memory device programs multi-bit data in the string in an order from a memory cell connected to the first transistor to another memory cell connected to the second transistor of the string.