Patent ID: 11954582
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 9:
10. The neural network accelerator of claim 9, further comprising:
a fourth bit operator configured to generate fourth product bits of a multiplication of second feature bits of the second input feature data and second weight bits of the second weight data,
wherein the first bit shift extent is a result of a corresponding summation of a fifth bit position difference between a least significant bit of the second feature bits in the second input feature data, and a least significant bit of the second input feature data, and a sixth bit position difference between a least significant bit of the second weight bits in the second weight data, and a least significant bit of the second weight data, and
wherein the summation includes a summing of the first product bits, the second product bits, the third product bits, and the fourth product bits.