Patent ID: 11862633
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 9:
10. A method of forming an integrated chip comprising:
forming a first plurality of channel structures over a substrate and extending in parallel between a first source/drain region and a second source/drain region;
forming a second plurality of channel structures arranged laterally beside the first plurality of channel structures and extending in parallel between a third source/drain region and a fourth source/drain region;
forming a dummy mask on the first plurality of channel structures and the second plurality of channel structures;
etching the dummy mask to remove the dummy mask from laterally outside of the first plurality of channel structures and the second plurality of channel structures, wherein the dummy mask remains vertically between the first plurality of channel structures and the second plurality of channel structures after the etching is completed;
forming a first gate electrode layer on the first plurality of channel structures and the second plurality of channel structures;
covering the first plurality of channel structures with a mask;
removing the first gate electrode layer from the second plurality of channel structures with the mask covering the first plurality of channel structures; and
forming a second gate electrode layer on the second plurality of channel structures.