Patent ID: 11880249
Assignee: THALES DIS FRANCE SAS
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 5:
6. An electronic system (1) comprising:
a plurality of sub blocks (21, 22, . . . ), each one being required to be supplied with a different power supply output voltage (VDD1, VDD2, . . . ),
a voltage regulation loop with a transistor feedback connected to a first output of a differential amplifier and to a second input of the differential amplifier, said loop comprising a first transistor (40) and a variable resistor (5) external to the differential amplifier (3),
the differential amplifier (3) having a plurality of outputs, an input reference voltage (VRF) being applied to a first input of the differential amplifier (3);
wherein said differential amplifier (3) includes a last stage comprising at least one component among a resistance, a diode, a MOS transistor, or a switched capacitor that is internal to the differential amplifier (3);
wherein the at least one component said differential amplifier (3) to drive multiple different power supply output voltages; and

a plurality of additional transistors (41, 42, . . . ), each output of the differential amplifier being connected to a gate or base of one of said additional transistors and the drain, source, emitter or collector of each additional transistor being connected to one of said sub-blocks,
wherein:
the input reference voltage (VRF) and the variable resistor are configured such that a first sub block (21) is supplied with its required power supply output voltage (VDD1) by the transistor it is connected to, and
said differential amplifier is configured to output on each of its outputs a power supply reference voltage (VG1, VG2) such that each sub block (22, . . . ) other than the first sub block is supplied with its required power supply output voltage (VDD2 . . . ) by the transistor it is connected to;
wherein the at least one component in the last stage of said differential amplifier (3) generates a resistor offset (Roffset) between an output transistor NOUT and a current source Iref of the differential amplifier (3) to generate a first power supply reference voltage VG1 at a drain of the output transistor NOUT and generate a voltage offset Voff leading to a voltage VG2=VG1+Voff at its terminal connected to the current source Iref.