Patent ID: 11908891
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A method of forming an integrated chip, comprising:
forming an isolation structure within a substrate;
etching the substrate and the isolation structure to form a gate base recess within the substrate;
forming a gate dielectric within the gate base recess and over the isolation structure;
etching the gate dielectric and the isolation structure to form a gate extension trench extending outward from the gate base recess;
forming a conductive material within the gate base recess and the gate extension trench;
performing a planarization process to remove a part of the conductive material from over the substrate and to form a gate electrode; and
forming a source region and a drain region on opposing sides of the gate electrode.