Patent ID: 11889682
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 17:
18. A semiconductor memory device, comprising:
a substrate comprising a memory cell region, a peripheral region, and a dummy cell region between the memory cell region and the peripheral region;
a plurality of active regions in the memory cell region, each of the plurality of active regions extending in a long axis direction, the long axis direction being a diagonal direction with respect to a first horizontal direction and a second horizontal direction orthogonal to the first horizontal direction, each of the plurality of active regions having a first width, and the plurality of active regions repeat with a first pitch, the first width and the first pitch in a short axis direction orthogonal to the long axis direction;
at least one logic active region disposed in the peripheral region;
a plurality of dummy active regions in the dummy cell region, each of the plurality of dummy active regions extending in the long axis direction, each of the plurality of dummy active regions having a second width greater than the first width, and the plurality of dummy active regions repeat with a second pitch greater than the first pitch, the first width and the second width in the short axis direction;
a device isolation structure defining the plurality of active regions, the at least one logic active region, and the plurality of dummy active regions;
a plurality of word lines extending parallel to each other in the first horizontal direction across the plurality of active regions and the plurality of dummy active regions;
a plurality of bit lines that extending parallel to each other in the second horizontal direction, the plurality of bit lines on the substrate;
a plurality of buried contacts filling a lower portion of a space between the plurality of bit lines on the substrate;
a plurality of landing pads filling an upper portion of the space between the plurality of bit lines and extending onto the plurality of bit lines; and
a plurality of capacitors connected to the plurality of landing pads, wherein
at least one of the plurality of dummy active regions defines a plurality of sidewall recesses filled with the device isolation structure on sidewalls of the at least one of the plurality of dummy active regions.