Patent ID: 11861216
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus, comprising:
a buffer;
a memory device comprising memory cells; and
a controller coupled with the buffer and the memory device, the controller configured to cause the apparatus to:
write, to the buffer, data for a set of commands that is associated with a barrier command;
determine, based at least in part on a portion of the data to be flushed from the buffer, whether to update an indication of a last barrier command for which all of the associated data has been written to the memory device;
perform a flushing operation based at least in part on determining whether to update the indication of the last barrier command, the flushing operation comprising transferring the portion of the data from the buffer to the memory device; and
validate, during a recovery operation, the portion of the data stored in the memory device based at least in part on determining the barrier command is associated with the portion of the data and on updating the indication of the last barrier command to indicate the barrier command.