Patent ID: 11956965
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 14:
15. An electronic system, comprising:
a memory device; and
a controller configured to control the memory device, the controller being electrically connected to the memory device through an input/output pad of the memory device,
wherein the memory device includes:
a substrate;
a peripheral circuit pattern on the substrate;
a first insulation layer on the peripheral circuit pattern;
a ground selection line on the first insulation layer, a cutting portion cutting the ground selection line;
an uppermost first insulation layer and a first word line stacked immediately above the ground selection line;
second insulation layers and second word lines alternately stacked on the first word line; and
the input/output pad, the input/output pad being electrically connected to the peripheral circuit pattern,

wherein the first word line includes a first portion laterally offset from the cutting portion and a second portion overlying the cutting portion,
wherein the first portion of the first word line has a first thickness,
wherein the second portion of the first word line has a second thickness less than the first thickness,
wherein each of the second word lines has the first thickness,
wherein the cutting portion includes an opening passing through the uppermost first insulation layer, cutting the ground selection line, and extending into a portion of the first insulation layer,
wherein a lower insulation pattern fills the opening, the lower insulation pattern having an upper surface protruding above a lower surface of the first word line at the first portion of the first word line and having a lower surface protruding below a lower surface of the ground selection line, and
the uppermost first insulation layer has a thickness that is about 2 times to about 5 times a thickness of the first insulation layer.