Patent ID: 11894048
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 12:
13. The control amplifying circuit of claim 12, wherein the first signal establishing circuit comprises n second inverters, and the second signal establishing circuit comprises m third inverters; wherein
an input end of each second inverter is connected with a respective one of first control input signals, and an output end of each second inverter is configured to output the respective one of first reference control signals; wherein a first reference control signal of each eleventh switching transistor is output through one of the n second inverters; and
an input end of each third inverter is connected with the respective one of second control input signals, and an output end of each third inverter is configured to output the respective one of second reference control signals; wherein a second reference control signal of each twelfth switching transistor is output through one of the m third inverters.