Patent ID: 11929766
Assignee: QUALCOMM INCORPORATED
Field: Telecommunications (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A device comprising:
one or more transceivers configured to receive analog signals;
an analog-to-digital converter (ADC) configured to generate ADC samples;
a switch operatively connected to the one or more transceivers and the ADC; and
one or more processors configured to:
operate the switch in a first mode to route a system clock from an oscillator to an input of the ADC;
determine a first ADC output timing based on a first set of ADC samples generated by the ADC;
operate the switch in a second mode to route analog signals from the one or more transceiver to the input of the ADC; and
obtain a second set of ADC samples generated by the ADC based on the analog signals.