Patent ID: 11935833
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A method of forming an integrated circuit structure, the method comprising:
forming a first power rail and a second power rail at a power rail level, the first power rail and the second power rail being oriented in a power rail direction;
forming a plurality of first metal segments at a first metal level above the power rail level, the plurality of first metal segments being oriented in a first metal direction perpendicular to the power rail direction, each first metal segment of the plurality of first metal segments overlapping one or both of the first power rail or the second power rail;
forming a plurality of first vias between the power rail level and the first metal level, each first via of the plurality of first vias being positioned at a location where a corresponding first metal segment of the plurality of first metal segments overlaps the first power rail or the second power rail;
forming a plurality of second metal segments at a second metal level above the first metal level, each second metal segment of the plurality of second metal segments being oriented in the power rail direction, the forming a plurality of second metal segments including aligning corresponding ones of the plurality of second metal segments to form first and second sets relative to the first metal direction, the first set of second metal segments overlapping the first power rail but being free from overlapping the second power rail relative to the first metal direction, and the second set of second metal segments overlapping the second power rail but being free from overlapping the first power rail relative to the first metal direction;
forming a plurality of second vias between the first metal level and the second metal level, each second via being positioned at a location above a corresponding first via of the plurality of first vias;
forming a first power strap level at a power strap level above the second metal level;
forming a second power strap at the power strap level; and
wherein:
the forming the IC structure further includes:
configuring the IC structure to electrically connect the first power strap to the first power rail and to electrically connect the second power strap to the second power rail;

the forming the plurality of first metal segments includes:
forming each first metal segment of the plurality of first metal segments having a width corresponding to a predetermined minimum width for the first metal level;

the forming the first power strap includes:
forming the first power strap having a width greater than a predetermined minimum width for the power strap level; and

the forming the second power strap includes:
forming the second power strap having the width greater than the predetermined minimum width for the power strap level.