Patent ID: 11950426
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. A method comprising:
forming memory cell including:
forming a first transistor including a first channel region, and a charge storage structure separated from the first channel region; and
forming a second transistor including a second channel region over the charge storage structure; and
forming a first conductive line, such that the first conductive line electrically separated from a first side of the first and second channel regions by a first dielectric material and spanning across part of the first and second channel regions;
forming a second conductive line, such that the second conductive line is electrically separated from a second side of the first and second channel regions by a second dielectric material and spans across part of the first and second channel regions; and
forming a data line over and contacting the first channel region and the second channel region, such that the data line includes a portion adjacent the first channel region and separated from the first channel region by a portion of a dielectric material.