Patent ID: 11935612
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. The memory of claim 7, wherein the first sub-output circuit comprises:
an eleventh transistor configured to enable to a source to be electrically connected to the first voltage, and a gate to be electrically connected to the second voltage node;
a twelfth transistor configured to enable a drain to be electrically connected to the drain of the eleventh transistor, and a gate to be electrically connected to each of the second voltage node and the gate of the eleventh transistor;
a thirteenth transistor configured to enable a source to be grounded, a drain to be electrically connected to the source of the twelfth transistor, and a gate to be electrically connected to the second data line; and
a fourteenth transistor configured to enable a source to be electrically connected to the first voltage, a drain to be electrically connected to each of the second complementary data line and the drain of the eleventh transistor, and a gate to be electrically connected to the second data line.