Patent ID: 11961743
Assignee: ZHUHAI ACCESS SEMICONDUCTOR CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A substrate manufacturing method for realizing three-dimensional packaging, comprising:
preparing a base plate, wherein the base plate comprises a dielectric material layer, a first sidewall pad and a first through-hole pillar arranged on the dielectric material layer, and a cavity penetrating both sides of the dielectric material layer, the cavity is filled with a first metal block, an anti-etching barrier layer is arranged between the first metal block and the dielectric material layer and at a bottom portion of the first metal block, the cavity is provided with at least one plane sidewall, and the first sidewall pad is located at one side of the plane sidewall and connected with the anti-etching barrier layer;
processing a first circuit layer and a second circuit layer on the base plate, wherein the first circuit layer comprises a first padding plate and a second metal block, the second circuit layer comprises a second padding plate and a plurality of pin pads, positions of the first padding plate and the second padding plate are all matched with the first through-hole pillar, the second metal block covers above the cavity, and the plurality of pin pads are located at a bottom portion of the cavity;
processing and laminating interlayer through-hole pillars on the first circuit layer to produce a semi-finished product, wherein the interlayer through-hole pillars comprise a first interlayer through-hole pillar, a second interlayer through-hole pillar, a third interlayer through-hole pillar and a fourth interlayer through-hole pillar, the first interlayer through-hole pillar is arranged on the first padding plate, the second interlayer through-hole pillar is arranged on the second metal block, the third interlayer through-hole pillar is arranged on the second padding plate, and the fourth interlayer through-hole pillar is arranged on at least one of the pin pads;
processing a third circuit layer and a fourth circuit layer on the semi-finished product obtained after laminating, wherein the third circuit layer comprises a second sidewall pad, a position of the second sidewall pad is matched with the first sidewall pad, and the second sidewall pad is connected with the first interlayer through-hole pillar, the fourth circuit layer comprises a routing circuit, and the routing circuit is respectively connected with the third interlayer through-hole pillar and the fourth interlayer through-hole pillar; and
etching the second interlayer through-hole pillar, the second metal block, the first metal block and the anti-etching barrier layer respectively to expose the first sidewall pad, the second sidewall pad and the pin pads.