Patent ID: 11860732
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. The system of claim 8, wherein the operations further comprise:
determining, based on the first logical address, a virtual fault tolerant stripe associated with the first host data and a virtual management unit (vMU) associated with the host data;
providing an indication of the virtual fault tolerant stripe and the redundancy factor as input to a first function and an indication of the vMU and the redundancy factor as input to a second function; and
obtaining a first output of the first function and a second output of the second function, wherein the first output comprises an indication of the fault tolerant stripe and the second output comprises an indication of a management unit (MU) of the fault tolerant stripe;
determining, based on the indication of the fault tolerant stripe and the indication of the MU, a first physical address associated with the first set of memory cells.