Patent ID: 11954582
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 5:
6. The neural network accelerator of claim 2, further comprising:
a third bit operator configured to generate third product bits of a multiplication of second feature bits of the first input feature data and the first weight bits of the first weight data, or a multiplication of the first feature bits of the first input feature data and second weight bits of the first weight data, or a multiplication of the second feature bits of the first input feature data and the second weight bits of the first weight data;
a second shifter configured to generate a second bit-shifted value by second bit-shifting a value, dependent on the third product bits, by a second bit shift extent; and
an accumulator configured to generate output feature data dependent on the first sum bits and based on the second bit-shifted value,
wherein the first shifter is configured to selectively operate, including being selected to not perform the first bit-shifting when X and Y are zero.