Patent ID: 11961807
Assignee: SILICON WORKS CO., LTD.
Field: Electrical machinery, apparatus, energy (Electrical engineering)
Classification: CPC H  Y | IPC H

Claim 13:
14. A semiconductor package comprising:
a support part;
a first semiconductor chip and a second semiconductor chip provided on the support part and each including a plurality of signal pads;
a plurality of electrode pads provided to be spaced apart from the support part outside the support part;
a wire including a first wire connecting one of the signal pads of the first semiconductor chip and one of the signal pads of the second semiconductor chip, a second wire connecting another signal pad of the first semiconductor chip and one of the electrode pads, and a third wire connecting another signal pad of the second semiconductor chip and another electrode pad;
a buffer layer provided on the first semiconductor chip;
an adhesive layer provided on the buffer layer;
a pressure-reducing layer provided on the adhesive layer; and
a mold layer provided on the pressure-reducing layer.