Patent ID: 11907545
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. The non-volatile memory device of claim 14, further comprising:
an internal data bus connecting the plurality of sets of internal data latches to the input-output interface,
wherein the plurality of data buffers are first in, first out data buffers (FIFOs) and the input-output interface further includes:
logic circuitry;
and
multiplexing circuitry, and

wherein the one or more control circuits are further configured to:
receive the compressed results of the read operation at the logic circuitry from the internal data bus;
perform the re-ordering of the bits of the compressed results in the logic circuitry; and
perform the replacement of the compressed results of the read operation from defective ones of the regular columns with corresponding compressed results of the read operation from spare columns by the multiplexing circuitry on the re-ordered bits of the compressed results.