Patent ID: 11877457
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A memory device, comprising:
a memory layer including a vertical three-dimensional (3D) memory array of memory cells formed therein, wherein a memory cell of the array is configured to be accessed through a word line and a digit line that are orthogonal to each other, and the digit line is in a form of a conductive pillar extending vertically, wherein respective storage elements of vertically adjacent memory cells are isolated from each other;
a pillar selection layer formed under the memory layer and having at least one thin film transistor (TFT) formed therein for accessing memory cells of the array; and
a peripheral circuit layer formed under the pillar selection layer and having a sense amplifier and decoding circuitry for word lines and bit lines associated with the array of memory cells, wherein a TFT of the at least one TFT is configured for the conductive pillar.