Patent ID: 11887891
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A method of fabricating an integrated circuit structure, the method comprising:
forming a first structure above a substrate, the substrate comprising silicon, the first structure comprising a first gate dielectric and a first gate electrode;
forming a first spacer adjacent to a first side of the first structure;
forming a second spacer adjacent to a second side of the first structure;
forming a second structure above the substrate, the second structure comprising a second gate dielectric and a second gate electrode;
forming a third spacer adjacent to a first side of the second structure;
forming a fourth spacer adjacent to a second side of the second structure;
forming a source or drain region between the second spacer and the third spacer;
forming a trench contact on the source or drain region;
forming a first inter-layer dielectric (ILD) layer directly on and vertically over the first spacer, the first structure, the second spacer, the third spacer, the second structure, and the fourth spacer, wherein the first ILD layer has a first opening vertically over the source or drain region, and wherein the first ILD layer is a planar ILD layer; and
forming a second ILD layer on the first ILD layer, wherein the second ILD layer has a second opening vertically over the first opening.