Patent ID: 11915746
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device, comprising:
a memory cell;
a word line (WL), connected to the memory cell, that is configured to provide a first WL pulse for the memory cell;
a bit line (BL) connected to the memory cell;
a first tracking WL coupled to the WL to emulate capacitive coupling between the WL and the BL so as to provide a second WL pulse;
a first tracking BL, coupled to the first tracking WL, that is configured to emulate the BL and increase a width of the first WL pulse based on the second WL pulse;
a second tracking BL configured to emulate the BL; and
a transistor gated to the first tracking WL, drained to the second tracking BL, and sourced to ground, the transistor configured to decrease a voltage of the second tracking BL, which causes a rising edge of the second WL pulse to present a decreased slope.