Patent ID: 11881860
Assignee: SK HYNIX INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. The multi-phase clock signal alignment circuit of claim 10, wherein during the first operation:
the clock selection circuit selects the first clock signal as the alpha clock signal and the second clock signal as the beta clock signal,
the first clock delay circuit provides the first selection clock signal by outputting the alpha clock signal delayed by the first interval,
the second clock delay circuit provides the second selection clock signal by outputting the beta clock signal,
the phase detection circuit detects a first phase difference between a rising edge of the first selection clock signal and a rising edge of the second selection clock signal, and
the phase control circuit controls a first phase delay circuit so that a rising edge of the second clock signal is adjusted according to the first phase difference.