Patent ID: 11915743
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 0:
1. A method of forming a latch circuit, comprising:
providing a first memory cell comprising:
a word line;
first and second bit lines;
first and second inverters, the first inverter having an output directly connected to an input of the second inverter by a first cross-coupling line, the second inverter having an output directly connected to an input of the first inverter by a second cross-coupling line;
a first pass gate transistor coupled between the first bit line and the output of the second inverter and having a gate coupled to the word line;
a second pass gate transistor coupled between the second bit line and the output of the first inverter and having a gate coupled to the word line;

cutting the first cross-coupling line to decouple the output of the first inverter from the input of the second inverter;
cutting the second cross-coupling line to decouple the output of the second inverter from the input of the first inverter;
directly coupling the input of the first inverter to the first bit line by a first coupling line;
directly coupling the input of the second inverter to the second bit line by a second coupling line; and
coupling the word line to receive a clock signal.