Patent ID: 11966480
Assignee: NVIDIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 10:
11. A method comprising:
receiving, by an accelerator circuit, a first descriptor of a first data transfer of a first size associated with a first application, the first descriptor specifying a first index in secure memory corresponding to the first application;
splitting, by the accelerator circuit, the first data transfer into a first set of portions, each portion being less than or equal to the first size and required to complete execution before a context switch to another application;
during a first period, executing, by the accelerator circuit, a first subset of the first set of portions sequentially using an authenticated encryption algorithm with a first initialization vector (IV) and a first encryption key associated with the first application, and storing, by the accelerator circuit, a first computed hash key and a first block counter in the secure memory at the specified first index; and
during a second period subsequent to the first period, executing, by the accelerator circuit, a second subset of the first set of portions sequentially using the first computed hash key and the first block counter stored in the secure memory at the specified first index, and storing, by the accelerator circuit, a first authentication tag associated with the first data transfer.