Patent ID: 11916122
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 0:
1. A method, comprising:
forming a stack of semiconductor nanosheets corresponding to channel regions of a gate all around transistor;
forming a plurality of sacrificial semiconductor nanosheets between the semiconductor nanosheets and having a first composition;
forming a sacrificial semiconductor cladding in contact with the stack of semiconductor nanosheets and the sacrificial semiconductor nanosheets and having a second composition different than the first composition;
exposing a portion of the semiconductor nanosheets by recessing the sacrificial semiconductor cladding with a first etching process;
forming a cladding inner spacer on the portion of the semiconductor nanosheets exposed by recessing the sacrificial semiconductor cladding;
removing a portion of each sacrificial semiconductor nanosheet by recessing the sacrificial semiconductor nanosheet with a second etching process; and
forming a respective sheet inner spacer in place of a recessed portion of each sacrificial semiconductor nanosheet.