Patent ID: 11869800
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A device comprising:
a semiconductor substrate;
a well feature disposed in the substrate;
an isolation feature disposed in the semiconductor substrate and interfacing with the well feature, the isolation feature having a top surface facing away from the semiconductor substrate, the top surface of the isolation feature extending along a first plane;
a first silicon-containing layer disposed directly on the well feature such that a first interface is formed between the first silicon-containing layer and the well feature, the first interface positioned at a first height in the device, the first silicon-containing layer having a bottom surface facing the semiconductor substrate and an opposing top surface facing away from the semiconductor substrate;
a second silicon-containing layer disposed directly on the first silicon-containing layer; the second silicon-containing layer being formed of a different material than the first silicon-containing layer, wherein the first silicon-containing layer and the second silicon-containing layer do not extend above the first plane that the top surface of the isolation feature extends along;
a gate stack disposed over and interfacing with the second silicon-containing layer; and
a first source/drain feature disposed in the semiconductor substrate on a first side of the gate stack, wherein first source/drain feature is disposed directly on the well feature such that a second interface is formed between the first source/drain feature and the well feature, the second interface positioned at a second height in the device, the second height being less than the first height, wherein the first source/drain feature is further disposed directly on the top surface of the first silicon-containing layer.