Patent ID: 11862227
Assignee: SEMIBRAIN INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. An information processing system that includes at least one memory device, the memory devices including a driver circuit for operating a memory cell, adapted to be coupled to at least one memory cell through a respective output node, said driver circuit including:
a first circuit for supplying the memory cell with a first read reference voltage through the output node;
a second circuit for supplying the memory cell with a second read reference voltage through the output node; and
a third circuit for controlling an operation of the second circuit,
wherein a range of the second read reference voltage at the output node is wider than a range of the first read reference voltage at the output node during a read operation on the memory cell,
wherein the second circuit includes a plurality of PMOS transistors stacked in series between a connected voltage supply node and the output node, each of said PMOS transistors having a gate terminal coupled to a gate control node connected to the third circuit.