Patent ID: 11862665
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A method of forming a semiconductor structure including a MIM capacitor, comprising:
forming a stack structure comprising a bottom electrode layer, a lower insulating layer, a middle electrode layer, an upper insulating layer and a top electrode layer over a dielectric structure;
forming a mask layer over the top electrode layer;
performing a first etching process to remove portions of the top electrode layer and the upper insulating layer exposed by the mask layer;
performing a first trimming process on the mask layer to form a first trimmed mask layer having a width less than that of the mask layer, such that a portion of the top electrode layer is further exposed by the first trimmed mask layer;
performing a second etching process to remove portions of the top electrode layer, the upper insulating layer, the middle electrode layer and the lower insulating layer exposed by the first trimmed mask layer;
performing a second trimming process on the first trimmed mask layer to form a second trimmed mask layer;
performing a third etching process to remove portions of the top electrode layer, the upper insulating layer, the middle electrode layer, the lower insulating layer, and the bottom electrode layer exposed by the second trimmed mask layer;
forming contact vias and conductive lines connected to the top electrode layer, the middle electrode layer and the bottom electrode layer from above the stack structure; and
forming conductive plugs connected to the conductive lines, wherein the conductive plugs are laterally spaced apart from the stack structure, and extend from above the stack structure to further below a bottom side of the stack structure.