Patent ID: 11862715
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A method for fabricating an integrated circuit (IC) structure, the method comprising:
epitaxially growing a source material over a substrate material, and adjacent to a sidewall of an isolation material;
forming a channel material on a first portion of the source material, wherein forming the channel material further comprises epitaxially growing the channel material on the source material and adjacent to a sidewall of the isolation material;
forming a drain material on a first portion of the channel material;
forming a gate dielectric on a second portion of the channel material, and laterally adjacent to the drain material; and
forming a gate electrode on the gate dielectric, with a sidewall of the gate electrode laterally adjacent to a sidewall of the drain material.