Patent ID: 11950523
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 16:
17. A method for manufacturing a memory device, comprising:
sequentially forming a first bottom electrode layer, a second bottom electrode layer, a resistance variable material layer and a top electrode layer over a semiconductor substrate;
disposing a hard mask on the top electrode layer;
performing at least one anisotropic etching process by using the hard mask as a mask, to pattern the top electrode layer, the resistance variable material layer, the second bottom electrode layer and the first bottom electrode layer, wherein the top electrode layer is patterned to form a top electrode, the resistance variable material layer is patterned to form a resistance variable layer, the second bottom electrode layer is patterned to form an upper bottom electrode, and the first bottom electrode layer is patterned to form a lower bottom electrode; and
performing an isotropic etching process to laterally recess the upper bottom electrode.