Patent ID: 11889342
Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 17:
18. An apparatus implemented at a first device, comprising:
a processor; and
a memory coupled to the processor, said memory containing instructions executable by said processor, whereby said processor is operative to:
determine one or more sub latency targets corresponding to one or more intermediate devices along an uplink or downlink route between a second device and a third device based on an uplink or downlink route total latency target and an uplink or downlink latency of one hop along the uplink or downlink route of each of the one or more intermediate devices;
send the one or more sub latency targets to the one or more intermediate devices, wherein a sum of the one or more sub latency targets is less than or equal to the uplink or downlink route total latency target; and
obtain a report comprising configuration information comprising at least one of: a configuration of supported one or more numerologies, a slot duration, or a configuration of a time division duplex pattern.