Patent ID: 11862706
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 5:
6. A memory device, comprising:
a first pull-down transistor, a first pull-up transistor, a first pass-gate transistor, and a read pass-gate transistor sharing a first gate electrode; and
a second pass-gate transistor, a second pull-up transistor, a second pull-down transistor, and a read pull-down transistor sharing a second gate electrode,
wherein the first pass-gate transistor and the second pass-gate transistor comprise a first gate dielectric layer, the first pull-down transistor and the second pull-down transistor comprise a second gate dielectric layer, the read pass-gate transistor comprises a third gate dielectric layer, and the read pull-down transistor comprises a fourth gate dielectric layer,
wherein the first gate dielectric layer, the second gate dielectric layer, the third gate dielectric layer comprise hafnium oxide,
wherein the first gate dielectric layer, the second gate dielectric layer, the third gate dielectric layer further comprises lanthanum,
wherein the fourth gate dielectric layer is substantially free of lanthanum.