Patent ID: 11914532
Assignee: APPLE INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 10:
11. A method, comprising:
initiating, by a memory controller for a multi-bank memory operation, a cadence that includes:
scheduling, for a given memory bank of a plurality of memory banks in a memory device, a first activate command, a second activate command, and a type command specifying a type of command, wherein the second activate command is scheduled to occur two cycles after the first activate command, wherein the type command is scheduled to occur a first time period after the second activate command, and wherein the first time period is equal to two clock cycles plus a minimum timing delay specified for the memory device; and
scheduling, for a next memory bank of the plurality of memory banks, a third activate command, a fourth activate command, and the type command, wherein the fourth activate command is scheduled to occur two cycles after the third activate command, wherein the type command is scheduled to occur a second time period after the fourth activate command, and wherein the second time period is equal to the minimum timing delay; and
repeating, by the memory controller, the cadence for additional pairs of memory banks in the memory device to continue the multi-bank memory operation.