Patent ID: 11870880
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. The digital clock data recovery circuit of claim 2, further comprising:
a third deserializer configured to output third even deserialized signals based on the up/down signals for even pulses from the phase detector;
a third vote circuit connected at an output of the third deserializer and configured to generate a third even up/down signal based on the third even deserialized signals;
a third DAC connected at an output of the third vote circuit and configured to control a voltage of the VCO based on the third even up/down signal from the third vote circuit;
a fourth deserializer configured to output fourth odd deserialized signals based on the up/down signals for odd pulses from the phase detector;
a fourth vote circuit connected at an output of the fourth deserializer and configured to generate a fourth odd up/down signal based on the fourth odd deserialized signals; and
a fourth DAC connected at an output of the fourth vote circuit and configured to control the voltage of the VCO based on the fourth odd up/down signal from the fourth vote circuit.