Patent ID: 11972966
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 18:
19. A method of manufacturing a semiconductor package, the method comprising:
encapsulating a plurality of semiconductor chips in a carrier to provide encapsulated semiconductor chips, a first surface of each of the encapsulated semiconductor chips including chip pads exposed from a first surface of the carrier, the carrier not covering the first surface of the encapsulated semiconductor chips such that the first surface of the carrier exposes the first surface of each of the encapsulated semiconductor chips;
measuring an alignment error of each of the encapsulated semiconductor chips with respect to the carrier;
forming a redistribution wiring structure on the first surface of the carrier, the forming the redistribution wiring structure including reflecting correction values for each layer of the redistribution wiring structure in order to correct the alignment error while forming the redistribution wiring structure such that exposure processes reflecting the correction values for each layer of the redistribution wiring structure are shifted based on the correction values that have been reflected to correct the alignment error, the redistribution wiring structure having redistribution wirings electrically connected to the chip pads of the encapsulated semiconductor chips, the redistribution wirings being shifted in a reverse direction of the alignment error based on the correction values that have been reflected to correct the alignment error, the redistribution wiring structure having outermost redistribution wirings among the redistribution wirings; and
forming outer connection members on the redistribution wiring structure, the outer connection members being electrically connected to the outermost redistribution wirings,
wherein the forming the outer connection members on the redistribution wiring structure is performed in a global alignment manner according to a position of a global reference target on the carrier, and
wherein the correction values for each layer of the redistribution wiring structure are equal.