Patent ID: 11861197
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 4:
5. The memory system of claim 2, wherein:
the data map has a hierarchical structure including at least a first hierarchy corresponding to the first fragment tables, and a second hierarchy higher than the first hierarchy, and further includes a second fragment table corresponding to the second hierarchy; and
the second fragment table stores third information and fourth information associated with each of the first fragment tables, the third information being information to refer to the first fragment table, the fourth information collectively indicative of the validity of the data having the predetermined size when the validity of each data having the predetermined size written in a range of physical address allocated to the first fragment table is common; and
the controller is configured to select the third block as the write destination block when the size of the write data is an integral multiple of the total data validity of which is collectively indicated by the fourth information.