Patent ID: 11923018
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A semiconductor memory device comprising:
a memory cell array including a plurality of memory cells;
a peripheral circuit configured to perform a program operation on selected memory cells among the plurality of memory cells; and
a control logic configured to control the program operation of the peripheral circuit,
wherein the program operation includes a plurality of program loops,
wherein the control logic is configured to control the peripheral circuit to apply a program voltage to a select word line that is connected to the selected memory cells, apply a first under drive voltage that is determined based on at least one verify voltage to the select word line, and apply the at least one verify voltage to the select word line in each of the plurality of program loops,
wherein the program voltage, the first under drive voltage and the at least one verify voltage are sequentially applied to the select word line, and
wherein the first under drive voltage is at a lower voltage level than the at least one verify voltage.