Patent ID: 11887670
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 0:
1. An apparatus, comprising;
a first voltage source configured to output a program-inhibit voltage signal to unselected bit lines among a plurality of bit lines during a program operation, the plurality of bit lines are connected to respective NAND strings in a set of NAND strings, and the NAND strings comprise memory cells; and
a control circuit configured to connect to the first voltage source, the control circuit is configured to:
control a ramp up of the program-inhibit voltage signal based on a number of bits per memory cell to program into selected memory cells of the respective NAND strings including ramping up at a first rate when programming a first number of bits per memory cell and ramping up at a second rate when programming a second number of bits per memory cell, the first number is less than the second number and the first rate is less than the second rate.