Patent ID: 11973084
Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 4:
5. An array substrate manufacturing method, comprising steps as follows:
providing a substrate;
manufacturing several first thin film transistors and several second thin film transistors on the substrate, wherein the step of manufacturing several first thin film transistors and second thin film transistors comprises:
manufacturing a first gate electrode layer of the first thin film transistors;
manufacturing a layer of gate electrode insulation material on the first gate electrode layer, wherein the gate electrode insulation material is silicon nitride material;
etching the gate electrode insulation material and a first insulation layer to form a contact hole corresponding to a first active layer and a metal layer, and annealing at a temperature from 350 to 400 degrees Celsius;
manufacturing a second gate electrode layer of the first thin film transistors and a third gate electrode layer of the second thin film transistors on the gate electrode insulation material; and
etching the gate electrode insulation material by using self-alignment of the second gate electrode layer and the third gate electrode layer, and acquiring a gate electrode insulation layer;
wherein after the step of acquiring the gate electrode insulation layer, the method further comprises steps as follows:
manufacturing a first dielectric layer on the first insulation layer, wherein the first dielectric layer covers the first gate electrode layer, the gate electrode insulation layer, the second gate electrode layer, and the third gate electrode layer;
manufacturing a second active layer of the second thin film transistors on the first dielectric layer;
manufacturing a layer of a second insulation layer on the first dielectric layer, wherein the second insulation layer covers the second active layer;
manufacturing a fourth gate electrode layer on the second insulation layer, wherein the fourth gate electrode layer corresponds to the third gate electrode layer;
manufacturing a second dielectric layer on the second insulation layer, wherein the second dielectric layer covers the fourth gate electrode layer;
etching the second dielectric layer, the second insulation layer, the first dielectric layer, and the first insulation layer to form several first via holes and second via holes, wherein the first via holes correspond to the first active layer of the first thin film transistors, and the second via holes correspond to the metal layer and the second active layer of the second thin film transistors; and
manufacturing a first source and drain electrode and a second source and drain electrode on the second dielectric layer, wherein the first source and drain electrode penetrates the first via holes and is connected to the first active layer, and the second source and drain electrode penetrates the second via holes and is connected to the metal layer and the second active layer.