Patent ID: 11862557
Assignee: APPLE INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A multi-die structure comprising:
a first front-end-of-the line (FEOL) die area of a first die patterned into a semiconductor substrate and a second FEOL die area of a second die patterned into the semiconductor substrate, the second FEOL die area separate from the first FEOL die area;
a first selection device within the first FEOL die area;
a second selection device within the second FEOL die area; and
a back-end-of-the-line (BEOL) build-up structure spanning over the first FEOL die area and the second FEOL die area, the BEOL build-up structure comprising:
a chip-level die-to-die routing connecting the first selection device with the second selection device;
a first inter-chip routing connected to the first selection device; and
a second inter-chip routing with the second selection device.