Patent ID: 11908802
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. An apparatus comprising:
a plurality of dielectric layers forming a substrate;
a plurality of first conductive contacts having a first pitch spacing on a top surface of the substrate;
a plurality of second conductive contacts having a second pitch spacing on the top surface of the substrate;
a plurality of first conductive interconnects disposed within the substrate to couple the plurality of first conductive contacts on the top surface of the substrate with a plurality of conductive contacts having a third pitch spacing on a bottom surface of the substrate; and
a plurality of second conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings comprise signal traces and the conductive interconnects to couple the second groupings comprise one or more conductive sheets.