Patent ID: 11882774
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A memory device, comprising:
a first portion, comprising:
a first patterned layer comprising an electrode material;
a second patterned layer comprising a memory material; and
a third patterned layer comprising a thermal barrier material;

a second portion comprising:
a fourth patterned layer comprising a plurality of vias through a dielectric material, the fourth patterned layer extending to a height that exceeds a height of the thermal barrier material in the third patterned layer; and

a conductive material over the first portion and the second portion, wherein a thickness of the conductive material over the first portion is larger than a thickness of the conductive material over the second portion, and wherein the conductive material is in contact with the dielectric material of the fourth patterned layer.