Patent ID: 11966582
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 1:
2. A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, wherein the controller is configured to:
receive a read command to read data from the memory device or a write command to write data to the memory device from a host device;
determine whether a bottleneck exists in a data/control path between the host device and the memory device, wherein the bottleneck exists either in an input queue corresponding to a hardware module of a plurality of hardware modules or in the hardware module of the plurality of hardware modules;
either:
compare a current number of commands in the input queue corresponding to the hardware module of the plurality of hardware modules to a threshold number of commands, or
determine that a first-in first-out (FIFO) full indication of the input queue corresponding to the hardware module of the plurality of hardware modules exists; and

execute a bottleneck release operation when the bottleneck exists in the data/control path between the host device and the memory device, wherein the bottleneck release operation is dependent on whether the bottleneck exists in the input queue or in the hardware module, wherein:
the bottleneck release operation comprises sending the read command or the write command to a different hardware module of the plurality of hardware modules having an input queue comprising a number of commands that is less than the threshold number of commands; and
the different hardware module is a same type of hardware module as the hardware module corresponding to the input queue having either the current number of commands being greater than the threshold number of commands or the FIFO full indication.