Patent ID: 11948292
Assignee: MAKINAROCKS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A server for providing methods for detecting flaws, including:
a processor including one or more cores;
a memory; and
wherein the processor is configured to perform operations comprising:
extracting a flaw patch from a first flaw image including a flaw, wherein the first flaw image comprises one or more flaw regions and the operation of extracting the flaw patch comprises at least one of:
extracting the flaw patch so that at least one of the flaw regions is included in a center of the flaw patch;
extracting the flaw patch so that the at least one of the flaw regions is included in a boundary of the flaw patch; or
extracting the flaw patch so that a predetermined number or more of flaw regions placed side by side continuously are included in the flaw patch;

preprocessing at least one of the first flaw image or a non-flaw image not including a first flaw;
extracting a non-flaw patch from at least one of the preprocessed first flaw image or non-flaw image;
training a neural network model for classifying patches to flaw or non-flaw with a training data set comprising the flaw patch and the non-flaw patch; and
determining, using the trained neural network model, a flaw threshold number indicating a minimum number of flaw patches included in an image for the image to be classified as a flaw image.