Patent ID: 11935600
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. A memory controller comprising:
an interface configured to receive a request for a programmable atomic operator, the request including a memory address;
circuitry configured to:
read a lock value based on the memory address in the request, the lock value indicating a lock for the programmable atomic operator;
hold the request based on the lock value indicating the lock for the programmable atomic operator, the hold preventing the request from being scheduled; and
release the request based on the lock value indicating that there is no lock, the lock value being changed based on a result of another request for the programmable atomic operator;

scheduler circuitry configured to schedule the request to a programmable atomic unit; and
a programmable atomic unit configured to invoke the programmable atomic operator based on the request.