Patent ID: 11894376
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 5:
6. The method according to claim 1, wherein forming the gate stack structure comprises:
forming a first interfacial layer in the first gate space;
forming a first gate insulating layer on the first interfacial layer in the first gate space; and
forming the first conductive metal nitride layer on the first gate insulating layer in the first gate space, and
forming the isolation stack structure comprises:
forming a second interfacial layer in the second gate space simultaneously with the forming of the first interfacial layer;
forming a second gate insulating layer in the second gate space simultaneously with the forming of the first gate insulating layer;
forming the second conductive metal nitride layer on the second gate insulating layer in the first gate space; and
doping the second conductive metal nitride layer with Si atoms while the first conductive metal nitride layer has a mask pattern thereon.