Patent ID: 11908838
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A three-dimensional device structure comprising:
a first die comprising a first semiconductor substrate;
a second die disposed on the first die and comprising a second semiconductor substrate;
a dielectric encapsulation (DE) layer disposed on the first die and surrounding the second die;
a redistribution layer structure disposed on the second die and the DE layer; and
deep trench capacitor (DTC) disposed in a trench formed in the DE layer and electrically connected to the first die and the redistribution layer structure, the DTC comprising:
a first conductive layer electrically connected to the first die;
a second conductive layer electrically connected to the redistribution layer structure; and
a first dielectric layer disposed between the first conductive layer and the second conductive layer.