Patent ID: 11877438
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. An array of memory cells comprising:
a plurality of capacitors in rows along a row direction and in columns along a column direction; the capacitors individually comprising a first capacitor electrode, a second capacitor electrode laterally-outward of the first capacitor electrode, and a capacitor insulator between the first and second capacitor electrodes;
a plurality of vertical transistors in the rows and columns above the plurality of capacitors; the vertical transistors individually comprising a top source/drain region, a bottom source/drain region, and a channel region vertically there-between; individual of the vertical transistors being directly electrically coupled to individual of the first capacitor electrodes, a plurality of gate lines that are individually operatively laterally-proximate the channel regions along individual of the rows;
a plurality of digitlines that are individually above the gate lines and electrically coupled to the top source/drain regions along individual of the columns; and
a plurality of conductive lines that are individually longitudinally-elongated in and extend along the row direction aside and are directly against the capacitor insulator and that are below the gate lines, individual of the conductive lines comprising the second capacitor electrode of individual of the capacitors, the individual conductive lines comprising a shared of the second capacitor electrodes of immediately-row-adjacent of the capacitors and interconnecting the individual second capacitor electrodes longitudinally along immediately-adjacent of the rows.