Patent ID: 11875847
Assignee: STMICROELECTRO (CROLLES 2) SAS
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. The sense circuit of claim 1, wherein the capacitor circuit comprises:
a current mirror having an input coupled to a bit line of the selected cell of the array of memory cells and an output coupled to a first node;
wherein the input capacitor is coupled between a first supply voltage and the first node to store the input voltage;
an input reset transistor coupled between the first supply voltage and the first node, the input reset transistor being controlled by an input reset control signal;
a reference capacitor coupled between the first supply voltage and a second node to store the reference voltage;
a reference reset transistor coupled between the first supply voltage and the second node, the reference reset transistor being controlled by a reference reset control signal; and
a transmission gate coupled between the first and second nodes, the transmission gate being controlled by a share control signal.