Patent ID: 11867745
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A method for detecting a parasitic capacitance in a semiconductor device, the semiconductor device being provided with sources, drains, active layers, gates located on the active layers, and wires connected to the sources and the drains, the method for detecting the parasitic capacitance in the semiconductor device comprising:
providing a plurality of semiconductor devices for testing, all the semiconductor devices being the same in a number of sources, a number of drains, a number of active layers, a number of gates, a number of wires and a cross-sectional area of the wire, all the semiconductor devices being different in a length of the wire therein;
obtaining a total capacitance value of each of the plurality of semiconductor devices and the length of the wire in the each semiconductor device;
determining a capacitance between the wire per unit length and the gate in the semiconductor device according to the plurality of total capacitance values and the lengths of the plurality of the wire of the plurality of semiconductor devices, the capacitance between the wire per unit length and the gate being considered as a parasitic capacitance per unit length;
determining a corresponding wire length of a to-be-detected semiconductor device; and
determining a parasitic capacitance of the to-be-detected semiconductor device according to the parasitic capacitance per unit length and the corresponding wire length of the to-be-detected semiconductor device.