Patent ID: 11887975
Assignee: DAICEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A semiconductor device manufacturing method, the method comprising:
a preparation step of preparing at least four reinforced wafers each having a laminated structure that includes a wafer including an element forming surface and a back surface opposite therefrom, a supporting substrate, and a temporary adhesive layer forming temporary adhesion, the temporary adhesive layer being provided between the supporting substrate and a side of the element forming surface of the wafer;
a thinning step of grinding a side of the back surface of the wafer of each reinforced wafer to thin the wafer;
a bonding step of bonding the sides of the back surface of the wafers of two reinforced wafers that have been subjected to the thinning step, and forming at least two wafer double-layer bodies having the supporting substrate;
a removal step of removing at least one supporting substrate of each of the wafer double-layer bodies; and
a multilayering step of bonding the sides of the element forming surface of the wafers of the at least two wafer double-layer bodies, forming a wafer multi-laminate, the sides of the element forming surface thereof being exposed by being subjected to the removal step, wherein
the wafer laminate obtained through the multilayering step has a laminated configuration that is symmetrical in a thickness direction thereof.