Patent ID: 11959939
Assignee: NANYA TECHNOLOGY CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 11:
12. The chip testing method of claim 11, wherein forming the chip socket comprising the plurality of clamp structures and the plurality of electrical contacts comprises:
providing a pedestal;
forming a plurality of conductive traces in the pedestal;
forming the plurality of clamp structures on a first surface of the pedestal, wherein at least one of the plurality of clamp structures is coupled to a corresponding conductive trace of the plurality of conductive traces; and
forming the plurality of electrical contacts on a second surface of the pedestal, wherein at least one of the plurality of electrical contacts is coupled to a corresponding clamp structure of the plurality of clamp structures through a corresponding conductive trace of the plurality of conductive traces.