Patent ID: 11955095
Assignee: LAPIS TECHNOLOGY CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 2:
3. The output circuit according to claim 1,
wherein the third voltage control circuit, when the first PMOS transistor switch is controlled such that the first PMOS transistor switch is brought into an on state, sets the voltage of the source or the drain of the first PMOS transistor switch as a first voltage and supplies a second voltage obtained by shifting the level of the first voltage to a high potential side to the back gate of the first PMOS transistor switch, and when the first PMOS transistor switch is controlled such that the first PMOS transistor switch is brought into an off state, supplies the reference power supply voltage to the back gate of the first PMOS transistor switch, and
wherein the fourth voltage control circuit, when the first NMOS transistor switch is controlled such that the first NMOS transistor switch is brought into an on state, sets the voltage of the source or the drain of the first NMOS transistor switch as a third voltage and supplies a fourth voltage obtained by shifting the level of the third voltage to a low potential side to the back gate of the first NMOS transistor switch, and when the first NMOS transistor switch is controlled such that the first NMOS transistor switch is brought into an off state, supplies the reference power supply voltage to the back gate of the first NMOS transistor switch.