Patent ID: 11928467
Assignee: APPLE INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. An apparatus comprising:
a predictor circuit configured to generate a prediction of whether or not an atomic operation will complete successfully, wherein the atomic operation specifies a load operation from a memory location, a data operation on first data from the load operation, and a store operation to write second data to the memory location, wherein the store operation is conditional on a result of the data operation, and wherein the atomic operation is defined to complete unsuccessfully based on the store operation not being performed; and
an execute circuit coupled to the predictor circuit and configured to perform the atomic operation, wherein the execute circuit is configured to associate the prediction from the predictor circuit with the store operation, and wherein the execute circuit is configured to select the second data as predicted result data accessed by a subsequent load operation based on the prediction of successful completion by the predictor circuit, and wherein the execute circuit is configured to select data from the memory location is the predicted result data based on the prediction of unsuccessful completion by the predictor circuit.