Patent ID: 11862241
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 38:
39. A variable resistive memory device comprising:
a memory cell including a bit line, a resistive layer, and a word line;
a first hierarchical bit line structure including a plurality of first conductive lines that are selectively connected between the bit line and a first voltage terminal, a plurality of first switches that are connected between the first conductive lines, and a first discharge switch that is connected between any one of the first conductive lines and a discharge terminal;
a first hierarchical word line structure including a plurality of second conductive lines that are selectively connected between the word line and a second voltage terminal, a plurality of second switches that are connected between the second conductive lines, and a second discharge switch that is connected between any one of the second conductive lines and the discharge terminal;
a second hierarchical word line structure including a plurality of third hierarchical conductive lines that are selectively connected between the word line and the first voltage terminal, a plurality of third switches that are connected between the third hierarchical conductive lines, and a third discharge switch that is connected between any one of the third hierarchical conductive lines and the discharge terminal; and
a second hierarchical bit line structure including a plurality of fourth hierarchical conductive lines that are selectively connected between the bit line and the second voltage terminal, a plurality of fourth switches that are connected between the fourth hierarchical conductive lines, and a fourth discharge switch that is connected between any one of the fourth hierarchical conductive lines and the discharge terminal,
wherein a voltage difference for forming a conductive path in the resistive layer is formed between a first voltage that is provided from the first voltage terminal and a second voltage that is provided from the second voltage terminal,
wherein the first switches and the first discharge switch in the first hierarchical bit line structure and the third switches and the third discharge switch in the second hierarchical word line structure comprise first conductive type transistors, and
wherein the second switches and the second discharge switch in the first hierarchical word line structure and the fourth switches and the fourth discharge switch in the second hierarchical bit line structure comprise second conductive type transistors that are opposite to the first conductive type transistors.