Patent ID: 11955095
Assignee: LAPIS TECHNOLOGY CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. The output circuit according to claim 7,
wherein the second current source is connected between the back gate of the first NMOS transistor switch and a negative power supply voltage terminal that receives a negative power supply voltage,
wherein the second back gate control switch is connected between the back gate of the first NMOS transistor switch and a reference power supply voltage terminal that receives the reference power supply voltage, and
wherein the second load element is composed of an MOS transistor having a diode connection configuration connected between the source or the drain of the first NMOS transistor switch and the back gate of the first NMOS transistor switch, or
an NMOS source follower transistor in which a gate receives the voltage of the source or the drain of the first NMOS transistor switch as the third voltage and a source is connected to the back gate of the first NMOS transistor switch.