Patent ID: 11935867
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A semiconductor package, comprising:
a package substrate that extends in a first direction and a second direction perpendicular to the first direction and that includes, when viewed in a plan view, a plurality of edge regions and a central region between the edge regions;
a plurality of logic dies and a memory stack structure on the package substrate, the logic dies being on the edge regions, and the memory stack structure being on the central region;
an interposer substrate including wiring lines mounted in the package substrate, the wiring lines electrically connecting the memory stack structure to at least one of the logic dies;
a plurality of first connection terminals that electrically connect the logic dies to the package substrate;
a plurality of second connection terminals that electrically connect the logic dies to the interposer substrate; and
a plurality of third connection terminals that electrically connect the memory stack structure to the interposer substrate,
wherein a pitch between the first connection terminals is greater than a pitch between the second connection terminals,
wherein the pitch between the first connection terminals is greater than a pitch of the third connection terminals,
wherein a bottom surface of the interposer substrate is in contact with the package substrate,
wherein the interposer substrate does not include a conductive structure providing an electrical connection between the wiring lines of the interposer substrate and the bottom surface of the interposer substrate, and
wherein the entirety of the memory stack structure vertically overlaps the interposer substrate.