Patent ID: 11910607
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. A three-dimensional semiconductor memory device, comprising:
first source conductive patterns on a substrate, the first source conductive patterns being spaced apart from each other in a first direction;
second source conductive patterns on the first source conductive patterns, the second source conductive patterns being spaced apart from each other in the first direction;
stacks on the second source conductive patterns, the stacks being spaced apart from each other in the first direction, and the stacks including a plurality of gate electrodes stacked on each of the second source conductive patterns; and
vertical channel portions penetrating the stacks and the first and second source conductive patterns, each of the vertical channel portions being in contact with a side surface of each of the first source conductive patterns,
wherein a distance between the first source conductive patterns adjacent in the first direction is a first width,
wherein a distance between the second source conductive patterns adjacent in the first direction is a second width, and
wherein the first width is larger than the second width.