Patent ID: 11972979
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A method of fabricating a semiconductor device, the method comprising:
forming a first interlayer dielectric (ILD);
forming a plurality of source/drain (S/D) contacts in the first ILD;
forming a first mask layer on the plurality of S/D contacts;
forming a plurality of gate electrodes in the first ILD, wherein the plurality of gate electrodes and the plurality of S/D contacts are arranged in an alternating pattern, and wherein top surfaces of the plurality of gate electrodes are below top surfaces of the plurality of S/D contacts so that a plurality of channels defined by sidewall surfaces of the first ILD is positioned over each of the plurality of gate electrodes;
forming a second mask layer partially filling a first channel of the plurality of channels over a first gate electrode of the plurality of gate electrodes, wherein the first mask layer is vertically between a S/D contact of the plurality of S/D contacts and the second mask layer; and
forming a fill metal filling a second channel of the plurality of channels over a second gate electrode of the plurality of gate electrodes that is adjacent to the first gate electrode.