Patent ID: 11868262
Assignee: MARVELL ASIA PTE LTD
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A system, comprising:
a first processor;
a plurality of clusters coupled to the first processor, wherein each cluster of the plurality of clusters comprises a plurality of core processors and a plurality of caches;
an interconnect interface that interconnects the clusters of the plurality of clusters;
a plurality of memory controllers coupled to the interconnect interface; and
a plurality of memories coupled to the memory controllers, wherein each memory of the plurality of memories comprises a plurality of bank groups;
wherein the system is configured to perform operations comprising:
receiving a plurality of memory requests comprising a plurality of addresses, wherein each memory request of the plurality of memory requests comprises a respective address of the plurality of addresses; and
hashing the addresses of the memory requests using a plurality of hashes to distribute the memory requests among the plurality of caches, the plurality of memory controllers, the plurality of memories, and the plurality of bank groups;
wherein each hash of the plurality of hashes is respectively programmed to achieve a specific distribution of the plurality of memory requests among the plurality of caches, the plurality of memory controllers, the plurality of memories, and the plurality of bank groups.