Patent ID: 11961570
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A method for NOR flash cell-array programming in a neural circuit comprising:
erasing a cell array;
programming a set of reference cells of a reference cell array to a target reference threshold voltage (Vt_ref);
generating, with the reference cells, a current or voltage, reference signal;
using the reference signal to bias a neural cells during verification of program state of the neural cells to achieve their respective target threshold voltages (Vt_cell); and
programming a set of neural cells of a neural cell array to their respective target threshold voltages, wherein a neural cell comprises a flash-cell system, wherein an equation for a neural cell comprises Eqneuron≡Σ(xi*yi)+b, where, xi is the set of input vectors, yi is parameter which is related to a threshold voltage of individual flash cells, and b is a bias variable,

wherein the cells are first programmed to a pre-final threshold values (Vt_initial_1) as defined in yi in a first sequence on program and program verify pulses as defined in xi,
wherein the cells are then programmed to a second pre-final threshold values (Vt_initial_2) as defined in yi in a second subsequent sequence of program and program verify pulses as defined in xi, and where the second pre-final threshold values are larger than the final target threshold values, and
wherein the cells are then weak erased to the final target threshold values as defined in yi with a sequence of erase pulses and erase verify pulses,
wherein the final threshold value is considered reached if the threshold value is close to (less than or equal to) the final target threshold value,
wherein the weak erase comprises an erase voltage level only detraps a plurality of shallow traps in an oxide layer or a nitride layer of the flash cell without effectively changing the threshold voltage.