Patent ID: 11876032
Assignee: MURATA MANUFACTURING CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. The semiconductor device according to claim 1, further comprising:
a foundation semiconductor layer disposed between the bond layer and the semiconductor element, wherein
the foundation semiconductor layer includes, in the plan view, a plurality of conducting regions and an element isolating region other than the conducting regions,
the collector layer of the first transistor is electrically coupled to the metal region of the bond layer by using one of the conducting regions of the foundation semiconductor layer,
the bond layer includes, in the plan view, an insulating region disposed in an outer side portion of the metal region,
the foundation semiconductor layer further includes a fourth conducting region disposed above the insulating region of the bond layer,
the semiconductor element further includes a diode disposed on the fourth conducting region, and
the diode includes a lower layer and an upper layer, the lower layer being disposed on the fourth conducting region and configured of a semiconductor of a first conductor type, the upper layer being disposed on the lower layer and configured of a semiconductor of a second conductor type opposite from the first conductor type, and

an upper electrode disposed on the upper layer and electrically coupled to the upper layer; and
a lower electrode disposed, in the plan view, in an inner side portion of the fourth conducting region and in an outer side portion of the diode and electrically coupled to the fourth conducting region.