Patent ID: 11914508
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory controller comprising:
a first port to couple to nonvolatile memory having a plurality of erase units, each erase unit including nonvolatile access units, specified by respective nonvolatile-access-unit addresses, to store data over time, the data stored over time including eldest data;
a second port to couple to a volatile memory having volatile access units, each volatile access unit specified by a respective volatile-access-unit address;
a head register to store, as a head nonvolatile address, the nonvolatile-access-unit address of a next one of the nonvolatile access units to receive write data; and
a tail register to store, as a tail nonvolatile address, the nonvolatile-access-unit address of one of the nonvolatile access units in the one of the erase units storing the eldest data, the head register and the tail register defining between them a group of the erase units with valid data and invalid data, wherein the group includes the one of the erase units storing the eldest data;
the memory controller to compare the head nonvolatile address with the tail nonvolatile address to initiate a garbage-collection process that erases the eldest data.