Patent ID: 11923293
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A method comprising:
forming a first interconnect dielectric layer over a substrate;
forming an interconnect wire within and extending through the first interconnect dielectric layer;
forming a barrier structure directly on the interconnect wire;
forming an etch stop layer over the first interconnect dielectric layer and the barrier structure;
forming a second interconnect dielectric layer over the etch stop layer;
performing a first removal process to form a cavity extending through the second interconnect dielectric layer to expose an upper surface of the etch stop layer;
performing a second removal process to extend the cavity through an upper portion of the etch stop layer to expose an upper surface of the barrier structure; and
forming a conductive material within the cavity to form an interconnect via coupled to the interconnect wire;
wherein after the second removal process, a middle surface of the etch stop layer is formed, wherein the middle surface is between a topmost surface and a bottommost surface of the etch stop layer.