Patent ID: 11917819
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A three-dimensional semiconductor memory device, comprising:
a substrate;
a stack structure including insulating patterns and gate electrodes, which are alternately and repeatedly stacked on the substrate;
a separation structure extending in at least one of a first direction and a second direction crossing the first direction, and dividing the stack structure;
a contact structure between the stack structure and the separation structure; and
a peripheral contact plug penetrating the separation structure,
wherein the separation structure includes:
first mold layers which are stacked in a third direction perpendicular to a top surface of the substrate;
second mold layers which are interposed between a corresponding pair of the first mold layers adjacent to each other in the third direction; and
third mold layers which are provided between the first mold layers adjacent to each other in the third direction and are horizontally spaced apart from each other by respective one of the second mold layers interposed therebetween,
wherein the stack structure has a rectangular shape with four side regions, at least one of the side regions of the stack structure having a staircase structure,
wherein the separation structure extends from one side region of the stack structure to another side region of the stack structure, opposing to the one side region,
wherein at least one of end portions of the separation structure has a staircase structure.