Patent ID: 11966786
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 3:
4. The system of claim 1, further comprising:
a quad management engine QME comprising one or more QME static random access memories (SRAM), the QME operably coupled to the one or more processor cores and the hardware-based control loop, wherein the QME SRAM is configured to maintain a table of processor throttling states resident thereon, the table of processor throttling states being empirically generated, wherein at least a portion of the table of processor core throttling states defines a substantially linear relationship with respect to associated power consumption values of the at least one processor core of the one or more processor cores; and
the hardware-based control loop is further configured to modulate the respective processor core throttling state to configure the at least one processor core of the one or more processor cores to consume the power value associated with the processor core throttling state.