Patent ID: 11893243
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. A storage system comprising:
a memory comprising memory cells configured to store X number of bits per memory cell, wherein X is a positive integer and wherein the memory is organized into a plurality of wordlines, wherein each wordline comprises a plurality of programming segments;
means for, for each of a plurality of program cycles, changing, in each of the plurality of wordlines and with respect to a prior wordline, which of the plurality of programming segments is a last programming segment programmed;
means for, after the plurality of program cycles, observing a pattern showing that an error repeatedly occurred on a certain programming segment of the plurality of programming segments;
means for, based on the observed pattern, selecting the certain programming segment to be the last programming segment programmed;
means for detecting a number of program disturb errors in the memory; and
means for correcting the program disturb errors using the error correction operation.