Patent ID: 11881771
Assignee: NXP USA, INC.
Field: Electrical machinery, apparatus, energy (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 15:
16. The method of claim 13, further comprising:
during a falling phase of the half-bridge voltage, the controller circuit comparing a value of the multi-bit status signal with a second higher limit value corresponding to a second upper limit voltage, to determine whether the half-bridge voltage is higher than the second upper limit voltage; and
the low-side delay circuit generating the low-side control signal using the delay control signal to reduce a predetermined delay time from a current third delay time in response to the half-bridge voltage being higher than the second upper limit voltage;
wherein the method further comprises: the low-side switch being on in response to the low-side control signal by applying the third delay time;
and wherein the method further comprises:
during the falling phase of the half-bridge voltage, the high-side delay circuit generating the high-side control signal using the delay control signal to add a predetermined delay time into a current fourth delay time in response to the half-bridge voltage being higher than the second upper limit voltage; and
the high-side switch being off in response to the high-side signal by applying the fourth delay time.