Patent ID: 11948978
Assignee: QUALCOMM INCORPORATED
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A field-effect transistor (FET), comprising:
a semiconductor body comprising a semiconductor material, the semiconductor body comprising a first edge;
a gate disposed above the semiconductor body, the gate comprising:
a central gate region disposed above a first region of the semiconductor body to form a central conduction channel in the first region of the semiconductor body,
the central gate region disposed along a first longitudinal axis and having a first end and a second end opposite the first end, the central gate region having a first length along a second longitudinal axis orthogonal to the first longitudinal axis; and

an edge gate region overlying the first edge of the semiconductor body to form an edge conduction channel around the first edge of the semiconductor body,
the edge gate region disposed in a direction of the second longitudinal axis orthogonal to the first longitudinal axis, and disposed adjacent to the first end of the central gate region, the edge gate region having a second length longer than the first length, wherein a work function of the edge gate region is equal to a work function of the central gate region;

a source region of a first polarity within the semiconductor body and disposed on a first side of the central conduction channel along a third longitudinal axis parallel to the first longitudinal axis;
a drain region of the first polarity within the semiconductor body and disposed on a second side of the central conduction channel opposite the first side of the central conduction channel and along a fourth longitudinal axis parallel to the third longitudinal axis;
a central transistor defined by the central gate region disposed over the semiconductor body, the central transistor having a first threshold voltage;
an edge transistor defined by the edge gate region disposed over the semiconductor body, the edge transistor having a second threshold voltage; and
an implant of a second polarity opposite the first polarity, the implant comprising:
a central implant region coupled to the semiconductor body and disposed along a fifth longitudinal axis parallel to the third longitudinal axis and adjacent to one of the source region and the drain region, the central implant region having a first end and a second end opposite the first end; and
an edge implant region coupled to the first end of the central implant region and underlying at least a portion of the edge gate region, the edge implant region disposed along a sixth longitudinal axis parallel to the second longitudinal axis,
wherein the central implant region of the implant comprises a body connection implant electrically coupled to one of the source region and the drain region, and the semiconductor body and wherein a ratio of current leakage of the edge transistor to current leakage of the central transistor is at least 5.0.