Patent ID: 11962312
Assignee: NVIDIA CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A computing system comprising:
an external oscillator that generates a system clock; and
a die coupled to the external oscillator, the die comprising:
an internal oscillator to generate multiple local clocks of multiple different phases;
a sampling circuit to oversample, using the multiple local clocks, the system clock to generate multiple samples of the system clock; and
digital logic comprising:
a glitch detector to monitor a variation in pulse width of the system clock based on counting the multiple samples and to report a glitch in response to detecting a variation in the pulse width exceeds a threshold value; and
a loop filter coupled between the glitch detector and the internal oscillator, the loop filter to variably adjust the internal oscillator based on a frequency of each of the multiple samples to control an output frequency of each of the multiple different phases of the internal oscillator.