Patent ID: 11961579
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 10:
11. A method of manufacturing a memory device, the method comprising:
aligning memory cell wafer contact pads of a memory cell wafer including bit lines with complementary metal-oxide-semiconductor (CMOS) wafer contact pads of a CMOS wafer including sense amplifier circuitry, the bit lines including primary bit lines and secondary bit lines, each of the secondary bit lines extending in parallel proximate to a corresponding one of the primary bit lines, a cross intersection of a first primary bit line of the primary bit lines with a first secondary bit line of the secondary bit lines located proximate to a parity intersection of a second primary bit line of the primary bit lines with a second secondary bit line of the secondary bit lines, the first primary bit line adjacent to the second primary bit line;
adjusting alignment of the memory cell wafer contact pads relative to the CMOS wafer contact pads responsive to a determination that the memory cell wafer contact pads are not properly aligned with the CMOS wafer contact pads; and
testing electrical conductivity of the memory device to determine whether the memory cell wafer contact pads are properly aligned with the CMOS wafer contact pads.