Patent ID: 11916804
Assignee: INTEL CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A device, the device comprising processing circuitry coupled to storage, the processing circuitry configured to:
maintain, at an upper layer, a self-ordering queue associated with one or more time sensitive packets associated with times sensitive traffic streams; wherein a quality of service (QoS) map element included in a data frame associated with the one or more time sensitive packets indicates a multi-link device (MLD) identifier (ID) or a bitmap of ordered MLD IDs, and wherein the QoS map element indicates that packets with value user priority (UP) 0 mapped to corresponding differentiated services code point (DSCP) range is assigned to an MLD;
transmit the one or more time sensitive packets from the self-ordering queue to a TSN queue at a lower layer;
control one or more enhanced distributed channel access (EDCA) queues by using a control function; and
transmit the one or more time sensitive packets to a first station device.