Patent ID: 11968830
Assignee: WINBOND ELECTRONICS CORP.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A patterning method, comprising:
sequentially forming a control structure, a hard mask layer, and a mask pattern on a target layer, wherein the control structure comprises a plurality of stop layers and a plurality of oxide layers stacked alternately;
forming a photoresist layer in the mask pattern on the hard mask layer;
by using the photoresist layer and the mask pattern as a mask, removing a portion of the hard mask layer and a portion of the control structure to form a plurality of first openings;
removing the photoresist layer and the hard mask layer there-below to form at least one second opening, wherein the second opening has a bottom surface higher than bottom surfaces of the plurality of first openings; and
performing one or more etching processes so that the plurality of first openings and the second opening extend into the control structure and the target layer, thereby dividing the target layer and the control structure into a plurality of stack structures.