Patent ID: 11947451
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. A memory system, comprising:
one or more memory arrays; and
one or more controllers coupled with the one or more memory arrays and configured to cause the memory system to:
receive a read command comprising a logical address of a memory array of the one or more memory arrays of data requested by the read command;
determine whether the logical address is absent from a first cache, the first cache comprising mappings between a first set of logical addresses and of a first set of physical addresses of the memory array;
identify a descriptor associated with the logical address and that is stored in a second cache based at least in part on determining that the logical address is absent from the first cache, the second cache comprising one or more descriptors between a second set of logical addresses and a second set of physical addresses of the memory array, wherein the descriptor identifies a starting physical address of the second set of physical addresses, a starting logical address of the second set of logical addresses, and a length indicating a quantity of logical addresses associated with the descriptor; and
retrieve the data from the memory array based at least in part on the descriptor stored in the second cache.