Patent ID: 11972839
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. A memory package comprising:
a semiconductor memory configured to output first data and a data strobe signal during a read operation of the first data; and
an interface circuit configured to receive a command and the data strobe signal from a controller and output the command and the data strobe signal to the semiconductor memory,
wherein the interface circuit is further configured to receive the first data and the data strobe signal from the semiconductor memory and output the first data and the data strobe signal to the controller during the read operation of the first data, and
wherein the interface circuit stores second data during the read operation of the second data, and the interface circuit blocks the first data received from the semiconductor memory and outputs the second data in synchronization with the data strobe signal to the controller.