Patent ID: 11973046
Assignee: SJ SEMICONDUCTOR(JIANGYIN) CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 5:
6. A semiconductor structure, comprising: a Si substrate having a groove, an insulating layer disposed in the groove at side walls and a bottom surface of the groove, wherein the insulating layer covers side walls and an entire bottom surface of the groove, and a Cu post disposed on the insulating layer in the groove followed by a wet etch process removing Cu residues and a part of the Cu post; wherein a first height difference is arranged between a top surface of the Cu post and a top surface of the insulating layer, wherein a second height difference is arranged between a top surface of the Si substrate and the top surface of the insulating layer, and wherein the second height difference is greater than the first height difference, and wherein the first height difference is in a range of 0.1 μm to 0.5 μm, and the second height difference is in a range of 2 μm to 3 μm.