Patent ID: 11923285
Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An electronic device package, comprising:
a circuit structure comprising:
a first dielectric layer;
a pad embedded in the first dielectric layer and having a first surface exposed by a bottom surface of the first dielectric layer and a second surface opposite to the first surface;
a first wiring layer disposed over the second surface of the pad; and
a first conductive via disposed between the first wiring layer and the pad; and

a first solder contacting the first surface of the pad, wherein a thickness of the pad is greater than a sum of a thickness of the first wiring layer and a thickness of the first conductive via;
wherein the bottom surface of the first dielectric layer defines an opening exposing the first surface of the pad, the first dielectric layer has an inner sidewall aligned with a lateral surface of the pad, the inner sidewall including a continuous curved surface extending from the second surface of the pad to the bottom surface of the first dielectric layer, and a width of the opening is less than a width of the first surface of the pad.