Patent ID: 11971782
Assignee: SK HYNIX NAND PRODUCT SOLUTIONS CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An erasure coding (EC) controller, comprising:
one or more substrates;
EC controller memory; and
logic coupled to the one or more substrates, the logic configured to control access to a persistent storage media and, in response to one or more commands, the logic is further configured to:
determine an intermediate parity value based on a first parity calculation,
store, in the EC controller memory, the intermediate parity value, and
determine a final parity value based on the intermediate parity value and a second parity calculation,
wherein to determine the intermediate parity value comprises sending a uni-directional command to:
read an old data value from a first address indicated in the uni-directional command;
perform an exclusive-or operation on the old data value and a new data value indicated in the uni-directional command to determine the intermediate parity value; and
store in the persistent storage media the intermediate parity value at a first location associated to a first index indicated in the uni-directional command.