Patent ID: 11930648
Assignee: MONOLITHIC 3D INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC H

Claim 7:
8. A semiconductor device, the device comprising:
a first level comprising a plurality of first memory arrays,
wherein said first level comprises a plurality of first transistors and a plurality of first metal layers;

a second level disposed on top of said first level,
wherein said second level comprises a plurality of second memory arrays;

a third level disposed on top of said second level,
wherein said third level comprises a plurality of third transistors and a plurality of third metal layers,
wherein said third level is bonded to said second level,
wherein said bonded comprises oxide to oxide bonding regions and a plurality of metal to metal bonding regions,
wherein said first level comprises first filled holes,
wherein said second level comprises second filled holes,
wherein said third level comprises a plurality of decoder circuits,
wherein said second filled holes are aligned to said first filled holes with a more than 1 nm but less than 40 nm alignment error, and
wherein at least one of said first transistors comprise a metal gate.