Patent ID: 11886341
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. The apparatus of claim 12, wherein the controller is further configured to:
receive a third read request, the third read request comprising a third logical address of the memory system;
load into the memory of the controller, a third mapping between logical addresses and physical addresses associated with a third region of the memory system associated with the third read request based at least in part on receiving the third read request, wherein the third region of the memory system comprises the third logical address of the third read request;
determining whether the first cache is full;
removing a fifth entry from the first cache based at least in part on determining that the first cache is full;
store a fourth entry comprising the third mapping to the first cache based at least in part on removing the fifth entry from the first cache; and
transmit data from a third physical address associated with the third logical address of the third read request based at least in part on storing the fourth entry.