Patent ID: 11955153
Assignee: KEPLER COMPUTING INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 22:
23. An apparatus comprising:
a first transistor having a first gate terminal coupled to a word-line, a first source terminal couple to a bit-line, and a first drain terminal coupled to a storage node;
a second transistor coupled to the first transistor, wherein the second transistor includes a second gate terminal coupled to the storage node, a second source terminal couple to a sense line, and a second drain terminal coupled to a bias;
a metal plane coupled to the storage node through a via; and
a plurality of memory elements having bottom electrodes coupled to the metal plane, wherein an individual memory element of the plurality of memory elements has a top electrode which is coupled to an individual plate-line via an individual switch, wherein the plurality of memory elements are planar memory elements that are arranged in a staggered configuration on the metal plane such that a first memory element of the plurality of memory elements is offset along a horizontal plane diagonally from a second memory element of the plurality of memory elements, and wherein the first memory element and the second memory element are on the horizontal plane.