Patent ID: 11972139
Assignee: PHISON ELECTRONICS CORP.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. The memory control circuit unit according to claim 13, wherein in the operation of performing the second data read operation according to the read level tracking table and the association information recorded in the transient look-up table,
the memory management circuit is further configured to obtain a second optimal read voltage level of a second physical unit among the physical units from the read level tracking table when the second data read operation instructs to read data of the second physical unit, and
the memory management circuit is further configured to look up the transient look-up table according to the second optimal read voltage level or an index corresponding to the second optimal read voltage level to sequentially obtain the second read voltage level corresponding to the count value as an initial read voltage level for performing the second data read operation according to a sequence of a plurality of count values from large to small.