Patent ID: 11934954
Assignee: SHANGHAITECH UNIVERSITY
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A pure integer quantization method for implementing a lightweight neural network (LNN) in an application specific integrated circuit (ASIC) or a field-programmable gate array (FPGA), comprising the following steps:
step 1: setting, by the ASIC or FPGA, a feature map with N channels, N≥1, and acquiring a maximum value of each pixel in each of N channels of a first feature map of a current layer:
step 2: processing, by the ASIC or FPGA, each pixel in each of the N channels of the first feature map as follows:
dividing, by the ASIC or FPGA, a value of each pixel in au n-th channel of the first feature map by a t-th power of a maximum value in the n-th channel acquired in step 1, t∈[0,1]; and
acquiring, by the ASIC or FPGA, N groups of weights corresponding to N channels of a second feature map of a next layer, wherein each of the N groups of the weights comprises N weights corresponding to the N channels of the first feature map of the current layer, and processing each of the N groups of the weights as follows:
multiplying, by the ASIC or FPGA, the N weights in an n-th group respectively by the maximum value of each pixel in the N channels acquired in step 1;
step 3: convolving, by the ASIC or FPGA, the first feature map processed in step 2 with the N groups of the weights processed in step 2 to acquire the second feature map of the next layer; and
step 4: obtaining by the ASIC or FPGA, a quantization accuracy based on a result of step 3, and tuning, by the ASIC or FPGA, the t value to obtain a maximum quantization accuracy.