Patent ID: 11973086
Assignee: AU OPTRONICS CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A display panel, comprising:
a first substrate including a display region and a peripheral region adjacent to each other;
a plurality of pixel units disposed on the first substrate and located in the display region;
a control circuit disposed on the first substrate, located in the peripheral region and electrically connected to the pixel units;
a planarization layer disposed on the first substrate, extending from the display region to the peripheral region and covering the pixel units and the control circuit; and
a bonding pad disposed on the first substrate and located above the planarization layer;
a projection area of the bonding pad on the first substrate and a projection area of the control circuit on the first substrate have an overlapped region;
the control circuit includes:
a first semiconductor layer disposed on the first substrate, and having a first doped region, a second doped region, and a first channel region located between the first doped region and the second doped region;
a gate insulating layer covering the first semiconductor layer;
a first metal layer disposed on the gate insulating layer and corresponding to the first channel region;
a first insulating layer covering the first metal layer; and
a second metal layer disposed on the first insulating layer and connected to the first doped region or the second doped region;
the planarization layer covers the first metal layer, the second metal layer and the first insulating layer;
the bonding pad includes:
a third metal layer disposed on the planarization layer;
a second insulating layer covering the third metal layer and formed with a bonding pad opening; and
a fourth metal layer disposed in the bonding pad opening and connected to the third metal layer;
wherein the pixel units include a plurality of thin film transistors, each of the thin film transistors including:
a second semiconductor layer disposed on the first substrate, and having a third doped region, a fourth doped region, and a second channel region located between the third doped region and the fourth doped region, wherein the gate insulating layer covers the second semiconductor layer;
a gate metal layer disposed on the gate insulating layer and corresponding to the second channel region, the first insulating layer covering the gate metal layer, wherein the gate metal layer and the first metal layer are made of the same material;
a source/drain metal layer disposed on the first insulating layer and connected to the third doped region or the fourth doped region, the planarization layer covering the source/drain metal layer and the first insulating layer, respectively, and the second insulating layer covering the planarization layer, wherein the source/drain metal layer and the second metal layer are made of the same material;
a common electrode disposed on the planarization layer; and
a pixel electrode disposed on the second insulating layer and electrically connected to the source/drain metal layer, wherein the pixel electrode and the fourth metal layer are made of the same material.