Patent ID: 11910606
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of forming an integrated assembly, comprising:
forming a vertical stack of alternating first and second levels; the first levels comprising first material and the second levels comprising second material;
forming an opening to extend through the stack;
forming channel material within the opening;
forming slits to extend through the stack, with the slits being laterally offset from the channel material;
after forming the slits, removing the second material to leave voids;
forming first conductive structures within the voids; the first conductive structures having proximal regions adjacent the channel material and having distal regions adjacent the slits;
removing the distal regions to form cavities adjacent the proximal regions;
forming second conductive structures within the cavities and directly against the proximal regions of the first conductive structures; and
forming a high-k dielectric material along upper and lower surfaces of the proximal regions of the first conductive structures, the high-k material being absent from upper and lower surfaces of the second conductive structures, the second conductive structure having a vertical thickness equal to a combined thickness of the first conductive structure and the high-k dielectric material along the upper and lower surfaces of the first conductive structure.