Patent ID: 11876622
Assignee: INTEL CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A forward-error-correction (FEC) encoder that is suitable for generating FEC data for use with hard-decision input at a receiver and for use with soft-decision input at the receiver, comprising:
Low-Density Parity-Check (LDPC) parity encoder circuitry configured to generate parity bits from payload bits using an LDPC code; and
puncturing/shortening circuitry configured to puncture and/or shorten the parity bits and/or the payload bits to generate the FEC data,
wherein the LDPC parity encoder circuitry and the puncturing/shortening circuitry are configured to generate the FEC data either:
a) using a single LDPC code that is suitable for use with soft-decision input and hard-decision input at the receiver, wherein the LDPC parity encoder circuitry and the puncturing/shortening circuitry are configured to generate the FEC data using the same LDPC code for use with hard-decision input at the receiver and for use with soft-decision input at the receiver, and the FEC data is generated using a single LDPC code that uses a first set of puncturing bits and/or a first set of shortening bits for use with soft-decision input at the receiver and a second set of puncturing bits and/or a second set of shortening bits for use with hard-decision input at the receiver, or
b) using one of two LDPC codes that are suitable for soft-decision input and hard-decision input, respectively, wherein one of the two LDPC codes is used for use with soft-decision input at the receiver and the other of the two LDPC codes is used for use with hard-decision input at the receiver.