Patent ID: 11942474
Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 2:
3. The method according to claim 2, wherein,
patterning the semiconductor stack into a predetermined shape comprises selectively etching at least those of the source/drain layers to be in contact with the second electrically conductive channel, such that those source/drain layers are recessed inward at least at the first range with respect to those of the source/drain layers to be in contact with the first electrically conductive channel and recessed inward at least at the third range with respect to the gate stack,
patterning the semiconductor stack into a predetermined shape further comprises selectively etching at least those of the source/drain layers to be in contact with the first electrically conductive channel, such that those source/drain layers are recessed inward at least at the second range with respect to those of the source/drain layers to be in contact with the second electrically conductive channel and recessed inward at least at the third range with respect to the gate stack, and
forming gate stacks comprises patterning the gate stacks to be recessed inward at least at the first range with respect to those of the source/drain layers to be in contact with the first electrically conductive channel and recessed inward at least at the second range with respect to those of the source/drain layers to be in contact with the second electrically conductive.