Patent ID: 11907369
Assignee: VENTANA MICRO SYSTEMS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. The method of claim 8, further comprising:
receiving, by the at least one execution pipeline, a store operation that is older than the first load operation;
detecting, by the at least one execution pipeline, a second condition in which the store operation generates a need for an architectural exception, the second load operation misses in the cache memory, and the second load operation is newer in program order than the store operation; and
preventing, by the at least one execution pipeline, state of the cache memory from being affected by the miss of the second load operation by inhibiting the fill request generation logic from generating a fill request for the second load operation or by canceling the fill request for the second load operation if the fill request generation logic has already generated the fill request for the second load operation.