Patent ID: 11887211
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. A method comprising:
caching texels, defined by textures represented using at least one texture image stored in a memory system, in a texture cache comprising a plurality of banks of cache storage;
for cached texels corresponding to a given chunk of texels of a given texture image, controlling access to the cached texels in the texture cache according to a selected bank mapping selected from among a plurality of bank mappings, each bank mapping corresponding to a different mapping of the respective texels of the given chunk of texels to the plurality of banks of cache storage of the texture cache; and
performing texture mapping operations using cached texels obtained from the texture cache; in which:
in at least one operating mode, the selected bank mapping to use for the given chunk of texels of the given texture image is selected depending on:
at least one of a first chunk position coordinate and a second chunk position coordinate associated with the given chunk of texels, where the first chunk position coordinate is indicative of a position of the given chunk of texels within the given texture image with respect to a first texture axis, and the second chunk position coordinate is indicative of a position of the given chunk of texels within the given texture image with respect to a second texture axis; and
at least one further texture attribute associated with the given texture image.