Patent ID: 11874775
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory system comprising:
a memory device suitable for storing data; and
a controller in communication with the memory device through a memory interface, suitable for generating L2P map data which includes mapping relationships between a plurality of logical addresses of a host and a plurality of physical addresses of the memory device and a total number of consecutive physical addresses with each of the plurality of physical addresses, and suitable for transmitting the L2P map data therefrom to the host,
wherein, when a read request is received with logical information and physical information from the host, the controller performs an access operation on a physical address range calculated based on the logical information and the physical information,
wherein the physical information includes a reference physical address that is corresponded to a reference logical address included in the logical information, and a consecutive physical address number that is the total number of consecutive physical addresses associated with the reference physical address,
wherein the logical information includes a logical address range for indicating consecutive logical addresses with the reference logical address,
wherein the controller determines that a sequential read operation is performable when a number of the consecutive logical addresses is less than or equal to the consecutive physical address number, and
wherein the controller determines that a sequential prefetch operation is performable when the number of the first consecutive physical addresses is less than the consecutive physical address number.