Patent ID: 11915937
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A method comprising:
forming first nanostructures and second nanostructures over a substrate;
removing the first nanostructures;
forming a first gate dielectric around the second nanostructures;
tuning a breakdown voltage of the first gate dielectric, the tuning the breakdown voltage comprising:
forming a protective material over the first gate dielectric, the protective material comprising a metal nitride;
forming a fluorine-containing layer over the protective material;
diffusing fluorine from the fluorine-containing layer through the protective material and into the first gate dielectric; and
removing the protective material; and

forming a first conductive material over the first gate dielectric.