Patent ID: 11972111
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. A memory device comprising:
a memory cell array comprising a plurality of single level cells configured to store one bit per cell;
a voltage generator configured to generate voltages for one or more program operations and a first verify operation, the one or more program operations and the first verify operation being performed on the memory cell array;
a control logic configured to perform a control operation on the memory cell array so that a first program loop and a second program loop are performed, the first program loop comprising a first program operation among the one or more program operations, the second program loop comprising a second program operation among the one or more program operations, the second program operation being performed based on a compensation voltage level determined based on a result of the first verify operation; and, a plurality of bit lines connected to the memory cell array,
wherein the first verify operation comprises obtaining first count values based on a difference between a first even sensing and a second even sensing on an even-numbered bit line among the plurality of bit lines, obtaining a second count value based on a difference between a first odd sensing and a second odd sensing on an odd-numbered bit line among the plurality of bit lines, and determining whether the first count value and the second count value satisfy a plurality of pass conditions.