Patent ID: 11956376
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A memory system comprising:
a plurality of memory cells at intersections between a plurality of word lines and a plurality of bit lines; and
a plurality of bit line sense amplifiers connected to the plurality of bit lines, the plurality of bit line sense amplifiers configured to write data to or read data from the plurality of memory cells through the plurality of bit lines, a portion of bit line sense amplifiers among the plurality of bit line sense amplifiers configured to generate a physically unclonable function (PUF) key including a random digital value, the random digital value being determined according to threshold voltage distributions of transistors included in the portion of bit line sense amplifiers, and the threshold voltage distributions being different from one another,
wherein each of the portion of bit line sense amplifiers is a defective bit line sense amplifier selected among the plurality of bit line sense amplifiers based on a threshold voltage distribution of transistors included in each of the plurality of bit line sense amplifiers,
wherein the portion of bit line sense amplifiers are replaced with redundancy bit line sense amplifiers for data sense operation in a normal operation mode.