Patent ID: 11929425
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 14:
15. A semiconductor device comprising:
a substrate;
a channel region including a plurality of nanowire structures over the substrate;
a gate structure over the channel region, the gate structure comprising a gate dielectric and a gate electrode, the gate structure being interposed between adjacent ones of the plurality of nanowire structures;
an outer spacer laterally adjacent the gate structure;
inner spacers adjacent the gate structure, each of the inner spacers being interposed between adjacent ones of the plurality of nanowire structures, the inner spacers extending below the channel region; and
a first source/drain region and a second source/drain region on opposing sides of the channel region, wherein a first nanowire structure of the plurality of nanowire structures extends past a lateral boundary of the outer spacers toward the first source/drain region.