Patent ID: 11942390
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 0:
1. A method comprising:
forming a transistor on a semiconductor substrate;
thinning the semiconductor substrate to expose a source/drain region of the transistor;
after thinning the semiconductor substrate, forming a first interconnect structure on a backside of the transistor, wherein forming the first interconnect structure comprises:
depositing a first dielectric layer on a backside of the transistor;
forming a contact through the first dielectric layer, the contact is electrically connected to a source/drain region of the transistor;
forming a conductive line electrically connected to the contact; and
forming a thermal dissipation path from the conductive line to a surface of the first interconnect structure opposite the transistor, wherein the thermal dissipation path comprises a dummy via; and

forming an external connector over the first interconnect structure, the external connector is thermally connected to the conductive line through the dummy via.