Patent ID: 11956943
Assignee: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. The memory according to claim 8, wherein the primary gate is located between the substrate and the semiconductor layer, and the secondary gate is located on one side of the semiconductor layer away from the substrate;
the transistor further comprises a first insulating layer, a first via hole and a second via hole;
the first insulating layer is located on one side of the secondary gate away from the substrate;
the one of the bit lines is located on one side of the first insulating layer away from the secondary gate;
the first via hole passes through the first insulating layer and the second dielectric layer, respectively, and is connected to the one of the bit lines and the source contact region of the semiconductor layer, respectively, and at least part of an entirety including the first via hole and the source contact region of the semiconductor layer forms the source; and
the second via hole passes through the first insulating layer and the second dielectric layer, and is connected to the secondary gate and the drain contact region of the semiconductor layer, respectively, and at least part of an entirety including the second via hole and the drain contact region of the semiconductor layer forms the drain.