Patent ID: 11862592
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An integrated chip (IC), comprising:
a semiconductor substrate;
an interconnect structure disposed over the semiconductor substrate;
a first dielectric layer disposed over the interconnect structure, wherein an upper surface of a conductive feature of the interconnect structure is at least partially disposed between opposite sidewalls of the first dielectric layer;
a sidewall spacer disposed along the opposite sidewalls of the first dielectric layer;
a conductive structure electrically coupled to the conductive feature of the interconnect structure, wherein the conductive structure is disposed over the first dielectric layer, over the sidewall spacer, and over the upper surface of the conductive feature of the interconnect structure; and
a second dielectric layer disposed between the first dielectric layer and the interconnect structure, wherein the conductive structure is disposed along a first sidewall of the second dielectric layer and along a second sidewall of the second dielectric layer, wherein the second sidewall is opposite the first sidewall, wherein the first sidewall and the second sidewall are laterally spaced a first distance apart along a first plane, wherein the first sidewall and the second sidewall are laterally spaced a second distance apart along a second plane, wherein the first plane extends laterally in parallel with the second plane, wherein the first plane is disposed between the second plane and the semiconductor substrate, and wherein the second distance is greater than the first distance.