Patent ID: 11954588
Assignee: UNIVERSITY OF DAYTON
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. An analog neuromorphic system that implements a plurality of resistive memories to execute a convolution layer in identifying a pixel image, comprising:
a plurality of input voltages applied to an analog neuromorphic circuit, wherein each input voltage represents a pixel value that corresponds to each pixel included in a partition of an image;
a plurality of complemented input voltages applied to the analog neuromorphic circuit, wherein each complemented input voltage represents a complemented pixel value that corresponds to each pixel included in the partition of the image;
a plurality of resistive memories with each resistive memory configured to:
provide a resistance value to each corresponding input voltage and complemented input voltage, wherein the plurality of resistive memories is a filter that the partition of the image is multiplied by the filter, and
multiply in parallel the filter to each partition of the image as each current from a plurality of currents propagates along each corresponding vertical wire to generate each dot product operation value and complemented dot product operation value as the output of each corresponding vertical wire, wherein each dot product operation value and each complemented dot product operation value that corresponds to each vertical wire represents a corresponding feature map generated from the multiplication of the filter simultaneously to each partition of the pixel image; and

a dot-product operation value and a complemented dot-product operation value generated from the multiplication of the filter to the partition of the image, wherein the dot-product operation value and the complemented dot-product operation value represents a feature map generated from the multiplication of the filter to the partition of the pixel image.