Patent ID: 11915979
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A device comprising:
a semiconductor region;
a high-k gate dielectric layer over and extending along sidewalls of the semiconductor region, the high-k gate dielectric layer comprising fluorine; and
a gate stack over and along sidewalls of the high-k gate dielectric layer, wherein the gate stack comprises:
an n-type work function metal layer comprising aluminum and fluorine;
a capping layer over the n-type work function metal layer, wherein the capping layer comprises aluminum in at least a lower region of the capping layer, and wherein an upper region of the capping layer comprises aluminum at a lower concentration than the lower region of the capping layer;
an adhesion layer over the capping layer; and
a first fill metal over the adhesion layer wherein the first fill metal is free of fluorine.