Patent ID: 11910613
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor memory device, comprising:
a mold structure including a plurality of wordlines, which are sequentially stacked on a front side of a first substrate, and a string selection line and a stopper line, which are sequentially stacked on the plurality of wordlines;
a channel structure extending in a vertical direction, which intersects the front side of the first substrate, to penetrate the mold structure;
a block separation structure extending in a first direction, which intersects the vertical direction, to cut the mold structure;
a protective structure interposed between the block separation structure and the stopper line, and not between the block separation structure and the string selection line and not between the block separation structure and the plurality of wordlines;
a string separation structure extending in the first direction to cut the string selection line and the stopper line;
a bitline extending in a second direction, which intersects the vertical direction and the first direction, on the mold structure; and
a bitline contact connecting the channel structure and the bitline,
wherein the protective structure has a lowermost surface located at a depth above the string selection line, and the block separation structure directly contacts the string selection line and the plurality of word lines below the protective structure.