Patent ID: 11887838
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. An integrated circuit structure, comprising:
a nanowire comprising silicon;
a plurality of gate structures over the nanowire and completely surrounding a channel region of the nanowire, individual ones of the plurality of gate structures along a direction orthogonal to the nanowire and having a pair of dielectric sidewall spacers;
a trench contact structure above the nanowire and between the dielectric sidewall spacers of a first pair of the plurality of gate structures; and
a contact plug above the nanowire and between the dielectric sidewall spacers of a second pair of the plurality of gate structures without an intervening trench contact structure between the dielectric sidewall spacers of the second pair of the plurality of gate structures, the contact plug comprising a lower dielectric material and an upper hardmask material, the upper hardmask material having a rounded bottom surface.