Patent ID: 11903331
Assignee: nan
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 1:
2. The digital circuit of claim 1, further comprising:
a complementary logic gate comprising:
an input node;
an output node;
a pull-down network comprising the one or more QWRTTs; and
a pull-up network comprising the one or more QWRTTs,
wherein the pull-down network and the pull-up network form dual networks, in which a parallel connection of the one or more QWRTTs in the pull-down network corresponds to a series connection of the one or more QWRTTs in the pull-up network, or in which a series connection of the one or more QWRTTs in the pull-down network corresponds to a parallel connection of the one or more QWRTTs in the pull-up network.