Patent ID: 11903191
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method comprising:
recessing a portion of a semiconductor substrate in a first region of the semiconductor substrate to form a recess;
depositing a bottom dielectric layer over the semiconductor substrate and along a bottom surface of the recess;
forming a charge storage layer over the bottom dielectric layer, wherein a portion of the charge storage layer is in the recess and below a top surface of the semiconductor substrate;
performing a planarization to give the charge storage layer and the bottom dielectric layer level top surfaces;
forming a first dielectric layer over and physically contacting the charge storage layer;
forming a second dielectric layer over a second region of the semiconductor substrate, wherein after forming the first dielectric layer and after forming the second dielectric layer:
the second region is free of the first dielectric layer; and
the first region is free of the second dielectric layer;

forming a third dielectric layer over the first dielectric layer and the second dielectric layer;
after forming the third dielectric layer, patterning the first dielectric layer and the second dielectric layer to form a first stack of layers directly above the recess and a second stack of layers directly above the second region of the semiconductor substrate; and
forming a metal layer over the first dielectric layer in the first region and over the second dielectric layer in the second region, wherein after patterning and after forming the metal layer, a first portion of the metal layer comprises a first gate electrode directly above the recess and a second portion of the metal layer comprises a second gate electrode directly above the second region of the semiconductor substrate.