Patent ID: 11915743
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 6:
7. The circuit of claim 3, further comprising:
a complementary clock input terminal configured to receive a complementary clock signal;
third and fourth bit lines;
a second latch circuit comprising:
third and fourth inverters, the third inverter having an input terminal coupled to the third bit line, the fourth inverter having an input terminal coupled to the fourth bit line; and
third and fourth pass gate transistors, the third pass gate transistor coupled between an output terminal of the fourth inverter and the third bit line, the fourth pass gate transistor coupled between an output terminal of the third inverter and the fourth bit line, the third and fourth pass gate transistors each having a gate terminal coupled to the complementary clock input terminal;
third and fourth cross-coupled PMOS transistors;
wherein the third cross-coupled PMOS transistor is coupled between the first voltage terminal and the fourth bit line, and has a gate coupled to the third bit line;
wherein the fourth cross-coupled PMOS transistor is coupled between the first voltage terminal and the third bit line, and has a gate terminal coupled to the fourth bit line.