Patent ID: 11942144
Assignee: ALMA MATER STUDIORUM—UNIVERSITA' DI BOLOGNA
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. An in-memory computation circuit, comprising:
a memory array including a plurality of memory cells arranged in a matrix with plural rows and plural columns, each row including a first word line connected to the memory cells of the row, and each column including a first bit line connected to the memory cells of the column, wherein computational weights for an in-memory compute operation are stored in the memory cells;
a word line control circuit configured to simultaneously actuate the plurality of first word lines in response to input signals providing coefficient data for said in-memory compute operation by applying word line signal pulses to the first word lines; and
a column processing circuit connected to the first bit lines and configured to process analog signals developed on the first bit lines in response to the simultaneous actuation of the plurality of first word lines to generate multiply and accumulate output signals for said in-memory compute operation;
wherein each row includes the first word line and a second word line connected to the memory cells of the row, and each column includes the first bit line and a second bit line connected to the memory cells of the column;
wherein each memory cell comprises:
a first sub-cell connected to the first bit line and the first word line; and
a second sub-cell connected to the second bit line and the second word line; and

wherein the first word line is asserted with the word line signal pulse if the input signal coefficient data value has a positive sign and the second word line is asserted with the word line signal pulse if the input signal coefficient data value has a negative sign;
wherein the column processing circuit comprises:
a first voltage regulator for each column configured to regulate a voltage applied to the first bit line;
a second voltage regulator for each column configured to regulate a voltage applied to the second bit line; and
an integrator circuit configured to positively integrate a current of the analog signal that is developed on the first bit line and negatively integrate a current of the analog signal that is developed on the second bit line.