Patent ID: 11907547
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G  H

Claim 0:
1. A memory device, comprising:
an array of memory cells;
a node for connection to a signal line;
a plurality of registers, wherein one register of the plurality of registers is configured to store an expected peak current magnitude of the memory device and a priority token of the memory device, and wherein remaining registers of the plurality of registers are each configured to store a respective expected peak current magnitude of a respective different memory device; and
a controller for access of the array of memory cells, wherein the controller is configured to cause the memory device to:
determine whether the memory device is waiting to initiate a next phase of an access operation on the array of memory cells;
in response to determining that the memory device is waiting to initiate the next phase of the access operation:
determine whether there is sufficient available current budget to initiate the next phase of the access operation in a selected operating mode in response to at least:
the priority token of the memory device;
the respective expected peak current magnitudes of the remaining registers of the plurality of registers; and
an expected peak current magnitude for the next phase of the access operation in the selected operating mode; and

in response to determining that there is sufficient available current budget to initiate the next phase of the access operation in the selected operating mode, output the expected peak current magnitude for the next phase of the access operation in the selected operating mode to the node and store the expected peak current magnitude for the next phase of the access operation in the selected operating mode to the one register of the plurality of registers.