Patent ID: 11862622
Assignee: WINBOND ELECTRONICS CORP.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC H

Claim 0:
1. An integrated circuit layout, comprising:
a first standard cell, comprising:
two first vertical cell boundaries arranged in parallel in a first direction and extending along a second direction, wherein the first direction and the second direction are perpendicular;
two first lateral cell boundaries arranged in parallel in the second direction and extending along the first direction;
a plurality of first active region patterns between the two first vertical cell boundaries and extending along the first direction and arranged in parallel along the second direction, wherein the first active regions have different lengths along the first direction; and
a plurality of first gate lines arranged along the first direction and on the plurality of first active region patterns, wherein the first gate lines respectively comprise a first gate line width and are distanced from each other by a default gate line pitch;

a second standard cell, comprising:
two second vertical cell boundaries arranged in parallel in the first direction and extending along the second direction;
two second lateral cell boundaries arranged in parallel in the second direction and extending along the first direction;
a plurality of second active region patterns between the two second vertical cell boundaries and extending along the first direction and arranged in parallel along the second direction; and
a plurality of second gate lines and arranged along the first direction on the plurality of second active region patterns, wherein the second standard cell is abutted to a side of the first standard cell by overlapping one of the two first lateral cell boundaries and one of the two second lateral cell boundaries, the second gate lines respectively comprise a second gate line width and are distanced from each other by the default gate line pitch, the first gate line width and the second gate line width are different, a first cell width between the two first vertical cell boundaries and a second cell width between the two second vertical cell boundaries are integral multiples of the default gate line pitch, and at least some of the second gate lines and at least some of the first gate lines are aligned along the second direction; and

a plurality of dummy gate lines respectively overlapping the first vertical cell boundaries and the second vertical cell boundaries, wherein at least one of the first active region patterns has one distal end overlapped by one of the dummy gate lines and another distal end overlapped by one of the first gate lines.