Patent ID: 11954061
Assignee: BEIJING TSINGMICRO INTELLIGENT TECHNOLOGY CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A mapping method for a reconfigurable array, comprising steps:
S1: obtaining a data dependence graph, and analyzing the data dependence graph to obtain a maximum time step count (TS_max) and a minimum initial interval;
S2: using the minimum initial interval as a start value of an initial interval;
S3: obtaining a reconfigurable architecture, wherein the reconfigurable architecture comprises at least one processing element and a corresponding link, the link includes an output link and an input link, a relationship between the processing element and the output link is indicated by a first adjacency matrix, and a relationship between the input link and the processing element is indicated by a second adjacency matrix;
S4: copying the first adjacency matrix and the second adjacency matrix to form a mapping space with a same number of layers as a value of the TS_max;
S5: setting a constraint condition to establish an integer linear programming model, and mapping, with the integer linear programming model, a processing vertex, an intra-cycle edge that is a dependency within a cycle of a circular structure in the data dependence graph, and an inter-cycle edge that is a dependence across different cycles of the circular structure in the data dependence graph, to the mapping space, respectively, wherein, in the integer linear programming model, the intra-cycle edge modulo of the TS_max is performed, and the inter-cycle edge modulo of the initial interval is performed;
S6: determining whether the mapping between the data dependence graph which represents the cycles of the circular structure, and the reconfigurable architecture has a solution in the integer linear programming model, performing S8 if yes, and performing S7 if no;
S7: adding 1 to the initial interval, and performing S5;
S8: obtaining a mapping relationship from the processing vertex and the edge in the data dependence graph to the processing element and the link of extended TS_max layers; and
S9: generating configuration information by the mapping relationship modulo of the initial interval, generating, according to the configuration information, a configuration file that is input to the reconfigurable architecture, and performing an operation by the reconfigurable architecture according to the configuration file.