Patent ID: 11892502
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 7:
8. The integrated circuit of claim 6, wherein the output control unit comprises a third transistor, a second inverter and a second spare transistor, each of the third transistor and the second spare transistor comprising a control terminal, a first terminal and a second terminal, the second inverter comprising a first terminal and a second terminal,
wherein the first terminal of the second inverter is coupled to a first output of the decoder, the second terminal of the second inverter is coupled to the control terminal of the third transistor,
the first terminal of the third transistor is coupled to the first terminal of the second spare transistor, the second terminal of the third transistor is coupled to the output of the operational TSV,
the control terminal of the second spare transistor is coupled to a second output of the decoder, the second terminal of the second spare transistor is coupled to the output of the spare TSV.