Patent ID: 11948843
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC B  H

Claim 3:
4. A method, comprising:
forming first and second semiconductor strips extending upwardly from a substrate, the first and second semiconductor strips each having a length extending along a first direction;
forming a dummy fin structure extending upwardly above the substrate and laterally between the first and second semiconductor strips;
forming an isolation dielectric laterally surrounding the first and second semiconductor strips and a lower portion of the dummy fin structure;
forming a plurality of first channel layers extending in the first direction above the first semiconductor strip and arranged in a second direction substantially perpendicular to the substrate;
forming a plurality of second channel layers extending in the first direction above the second semiconductor strip and arranged in the second direction;
forming a gate structure surrounding each of the first and second channel layers;
forming a plurality of source/drain structures above the first and second semiconductor strips and on either side of the gate structure;
forming a first crystalline hard mask layer extending upwardly from the dummy fin structure and having a U-shaped cross section; and
forming a first amorphous hard mask layer on the first crystalline hard mask layer, wherein the first amorphous hard mask layer has having a U-shaped cross section conformal to the U-shaped cross section of the first crystalline hard mask layer.