Patent ID: 11942479
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method comprising:
forming a fin structure over a substrate, wherein the fin structure comprises first semiconductor layers and second semiconductor layers alternately stacked;
depositing an isolation structure over the substrate;
forming a dummy gate structure over the fin structure;
removing a portion of the fin structure uncovered by the dummy gate structure;
growing a source/drain epitaxial structure on a side of remaining portions of the second semiconductor layers;
replacing the dummy gate structure and the first semiconductor layers with a metal gate structure;
removing the substrate to expose a bottom surface of the isolation structure;
forming an opening in the isolation structure and exposing a gate electrode of the metal gate structure;
forming a gate via in the opening such that the gate via is connected to the metal gate structure and embedded in the isolation structure; and
forming a spacer structure in the opening prior to forming the gate via.