Patent ID: 11961837
Assignee: THE BOARD OF TRUSTEES OF THE LELAND STANFORD JUNIOR UNIVERSITY
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method comprising:
forming
a diamond layer section;
a GaN-based substrate including GaN and AlGaN and including a dielectric layer; and

forming an integrated circuit that includes
a GaN-based field effect transistor (FET) integrated with a portion of the GaN-based substrate,
a diamond-based FET (“diamond FET”) integrated with a portion of the diamond layer section, the diamond FET being electrically coupled to the GaN-based FET and situated over or against a surface region of the GaN-based substrate, and
interconnects to electrically interconnect the GaN-based FET and the diamond-based FET, wherein the dielectric layer is formed on the diamond layer section and the dielectric layer is to facilitate stability during operation of the integrated circuit at temperatures greater than 250° C. by at least one of: having a selected thickness to mitigate dielectric layer leakage current or breakdown of the dielectric layer; and being formed using a sufficiently-high deposition temperature of greater than 350° C.