Patent ID: 11967529
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor chip comprising:
a semiconductor substrate comprising an integrated circuit region and a cut region for separating the integrated circuit region;
a plurality of multilayer metal patterns in the cut region, the plurality of multilayer metal patterns comprising a first metal pattern at a first level, a second metal pattern at a second level, and a vertical via connecting the first metal pattern to the second metal pattern; and
an interlayer insulating film comprising a first insulating film layer at the first level, a second insulating film layer at the second level, and a material film between the first insulating film layer and the second insulating film layer,
wherein the material film comprises a material different from the first insulating film and the second insulating film,
a number of the plurality of multilayer metal patterns at the second level is less than a number of the plurality of multilayer metal patterns at the first level, and
an upper surface of the first metal pattern at the first level contacts the vertical via and is spaced apart from upper surfaces of remaining ones of the plurality of multilayer metal patterns at the first level.