Patent ID: 11864373
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for manufacturing a semiconductor structure, comprising:
providing a substrate, the substrate comprising a core region, and a peripheral region located outside the core region and adjacent to the core region, a preset barrier layer being further formed on the substrate and covering the core region and the peripheral region;
removing at least a part of the preset barrier layer corresponding to the peripheral region, so as to expose a part of the substrate, and to take a reserved part of the preset barrier layer as a first barrier layer;
successively forming a dielectric layer and a first conductive layer, which are laminated, on the first barrier layer and the substrate; and
removing a part of the dielectric layer and a part of the first conductive layer on the first barrier layer, to reserve a part of the dielectric layer and a part of the first conductive layer on the first barrier layer closer to the peripheral region, wherein an orthographic projection of the dielectric layer on the substrate partially overlaps an orthographic projection of the first barrier layer on the substrate to form an overlapped region, and a width of the overlapped region is in a range of 20 nm to 100 nm.