Patent ID: 11928414
Assignee: INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 8:
9. The chip according to claim 8, wherein allocating respective line-out layer for the pins of the chip in the circuit board comprises:
allocating first line-out layers corresponding to the power supply pins in an intermediate layer on the circuit board;
taking all the first line-out layers as a whole first line-out layer, allocating second line-out layers corresponding to the low-speed pins evenly in upper and lower layers of the whole first line-out layer;
taking all the first line-out layers and all the second line-out layers as a whole second line-out layer, allocating third line-out layer corresponding to the RX pin in the upper layer of the whole second line-out layer, and allocating the third line-out layer corresponding to the TX pin to the lower layer of the whole second line-out layer; and
allocating a ground layer for the upper and lower layers of each second line-out layer and each third line-out layer, respectively, wherein all ground layers are connected together through via holes and serve as line-out layers of the ground pins at a same time.