Patent ID: 11960728
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 2:
3. The storage device of claim 1, wherein the interface circuit includes:
a plurality of registers configured to store plural pieces of command information, respectively, the plural pieces of command information corresponding to a plurality of memory dies including the first memory die and the second memory die, respectively;
a demultiplexer circuit configured to provide input command information to a selected register among the plurality of registers according to at least one of a first address or a first chip selection signal, the input command information received from the memory controller; and
a multiplexer circuit configured to receive output command information from the selected register among the plurality of registers and output the output command information according to at least one of a second address or a second chip selection signal.