Patent ID: 11868770
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A system comprising:
a processor comprising:
a cache to store data; and
a plurality of cores coupled to the cache, at least one core of the plurality of cores comprising:
execution circuitry to execute one or more instructions to perform a matrix multiplication with a first source matrix and a second source matrix to generate a result matrix, the execution of the one or more instructions comprising:
converting a first plurality of data elements of the first source matrix and a second plurality of data elements of the second source matrix from a single-precision floating point format to a reduced precision floating point format having fewer mantissa bits than the single-precision floating point format and a same number of exponent bits as the single-precision floating point format; and
performing a plurality of parallel fused multiply-add operations to multiply the first plurality of data elements in the reduced precision floating point format by corresponding data elements of the second plurality of data elements in the reduced precision floating point format to generate a plurality of products, and to add the plurality of products to accumulated values to generate single-precision floating point data elements of the result matrix;

a data storage device coupled to the plurality of cores;
a memory controller coupled to the plurality of cores; and
a system memory coupled to the memory controller, the system memory to store the first source matrix, the second source matrix, and the result matrix.