Patent ID: 11923310
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A package structure, comprising:
a first through via structure formed in a substrate;
a second through via structure formed adjacent to the first through via structure;
a semiconductor die formed below the first through via structure and the second through via structure;
a conductive structure formed over the first through via structure;
wherein the conductive structure comprises a first via portion and a second via portion, wherein the second via portion is between and above the first through via structure and the second through via structure, and the second via portion is electrically connected to the first via portion through a first metal portion and a second metal portion, and the second metal portion has a recessed top surface; and
an under bump metallization (UBM) layer formed on and in direct contact with the recessed top surface of the second metal portion.