Patent ID: 11961879
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of forming an integrated circuit (IC), comprising:
forming stacked metal layers on a semiconductor substrate including circuitry with nodes, the stacked metal layers including a first metal layer and a second metal layers located under the first metal layer; and
forming a segmented isolation capacitor, including:
forming a bottom plate of the segmented isolation capacitor based on the second metal layer, the bottom plate including a plurality of spaced apart segments, wherein a first segment of the plurality of spaced apart segments is electrically connected to a first node of the nodes, and wherein a second segment of the plurality of spaced apart segments is electrically connected to a second node of the nodes;
forming a capacitor dielectric layer of the segmented isolation capacitor over the bottom plate; and
forming a top plate of the segmented isolation capacitor based on the first metal layer, the top plate covering at least a portion of the plurality of spaced apart segments, wherein the top plate is electrically connected to a third node of the nodes.