Patent ID: 11869833
Assignee: QUALCOMM INCORPORATED
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. An apparatus comprising:
a substrate comprising:
a plurality of interconnects comprising:
a first via interconnect with a first width;
a first trace interconnect directly coupled to a side portion of the first via interconnect; and
a second trace interconnect directly coupled to a first surface of the first via interconnect;

wherein the first trace interconnect includes a second width that is less than the first width and the second trace interconnect includes a third width that is less than the first width; and
at least one dielectric layer at least partially surrounding the plurality of interconnects; and

an integrated device coupled to the substrate, wherein the at least one dielectric layer and the plurality of interconnects are located in planes underneath the integrated device.