Patent ID: 11894383
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC B  H

Claim 16:
17. A method of manufacturing a semiconductor structure, comprising:
forming a source region and a drain region of a first transistor horizontally arranged at a first elevation;
forming a source region and a drain region of a second transistor horizontally arranged at the first elevation;
forming a source region and a drain region of a third transistor horizontally arranged at a second elevation higher than the first elevation and vertically aligned with the second transistor;
forming a source region and a drain region of a fourth transistor horizontally arranged at the second elevation;
forming a first semiconductive component at the first elevation and vertically aligned with the source region or the drain region of the fourth transistor;
forming a second semiconductive component at the second elevation and vertically aligned with the source region or the drain region of the first transistor;
forming a gate structure of the first transistor extending in and stopped at the first elevation; and
forming a gate structure being common to the second transistor and the third transistor.