Patent ID: 11963346
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor structure, comprising:
a substrate;
a trench, located in the substrate;
a bit line contact structure, the bit line contact structure located in the trench, wherein an upper surface of the bit line contact structure is lower than an upper surface of the substrate, the bit line contact structure extends along a first direction;
a bit line structure, the bit line structure located on the bit line contact structure, and at least partially located in the trench;
a bit line protection structure, the bit line protection structure comprising a top dielectric layer and a sidewall structure, wherein the top dielectric layer is located on the bit line structure and forms a laminated structure together with the bit line structure; the sidewall structure covers part of sidewalls of the laminated structure on the substrate, the sidewall structure has a first air gap; and
an isolation pattern structure, wherein the isolation pattern structure has a second air gap, the isolation pattern structure extends along a second direction, the second direction intersects with the first direction, to form a capacitance contact hole between the adjacent bit line protection structures and the adjacent isolation pattern structures.