Patent ID: 11962303
Assignee: STEVE DAO
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A flip-flop circuit, comprising:
a first latch operating in a first voltage domain, wherein the first latch comprises:
four clock-activated transistors comprising at least a first clock-activated transistor and a second clock-activated transistor;
a first output node; and
a second output node;

a second latch operating in the first voltage domain, wherein the second latch comprises:
a first keeper pull-up sub-circuit coupled to the first output node,
wherein the first keeper pull-up sub-circuit is electrically coupled to the first-clock-activated transistor of the first latch and the first clock-activated transistor is a clock-gated device for the first keeper pull-up sub-circuit;
a second keeper pull-up sub-circuit coupled to the second output node,
wherein the second keeper pull-up sub-circuit is electrically coupled to the second clock-activated transistor of the first latch and the second clock-activated transistor is a clock-gated device for the second keeper pull-up sub-circuit;
a first pull-down network; and
a second pull-down network,
wherein the second latch is configured to merge pull-up functionality of the first keeper pull-up sub-circuit with the first clock-activated transistor of the first latch and to merge pull-up functionality of the second keeper pull-up sub-circuit with the second clock-activated transistor of the first latch.