Patent ID: 11862267
Assignee: NETLIST, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. A memory module operable in a computer system including a system memory controller coupled to a system memory bus having a bit width N, where N is a positive integer, the memory module comprising:
a printed circuit board (PCB) including a connector that fits into a corresponding slot connector of the computer system whereby the memory module is operatively coupled to the system memory controller of the computer system via the system memory bus;
memory devices mounted on the PCB and organized in one or more N-bit-wide ranks, the memory devices having address and control ports and data ports;
a data module coupled between the data ports of the memory devices and the connector, the data module including a plurality of data handlers in respective physically separate integrated circuit packages mounted on respective portions of the PCB and coupled to respective n-bit-wide segments of the memory devices, where n is a positive integer smaller than N; and
a control circuit mounted on the PCB and coupled to the connector, the data module, and address and control ports of the memory devices;
wherein, during a normal memory read or write operation, the control circuit is configurable to receive system address and control signals from the system memory controller via the connector and to output registered memory address and control signals for the normal memory read or write operation, and each respective data handler of the data module is configurable to propagate respective read or write data signals associated with the normal memory read or write operation between a respective n-bit-wide segment of the memory devices and a respective n-bit-wide segment of the system memory bus, the respective read or write data signals being output or received by at least one memory device in the respective n-bit-wide segment of the memory devices in response to the registered memory address and control signals; and
wherein, during testing of the memory module, the control circuit is configurable to output test address and control signals to the memory devices and a command to the data module, the data module is configurable to isolate data paths from the memory controller to the memory devices through the data handlers, the each respective data handler of the data module is configurable to output respective test data signals to the respective segment of the memory devices in response to the command from the control module, and the respective test data signals including test data to be received by and written into one or more memory devices in the respective segment of the memory devices in response to the test address and control signals from the control circuit.