Patent ID: 11948935
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 2:
3. The method of claim 2, wherein the generating the tap cell layout pattern further comprises:
generating a second implant layout pattern adjacent to the first implant layout pattern, the second implant layout pattern corresponding to fabricating a second set of implants of the integrated circuit structure, each implant of the second set of implants having the second dopant type, and at least one implant of the second set of implants being configured to be coupled to a second supply voltage,
the second implant layout pattern overlapping the second jog pattern, and continuously extending from the second jog pattern through the tap cell layout pattern and the standard cell layout pattern along the X direction, and
the second implant layout pattern having a second length in the Y direction, the second length having a substantially uniform length along the X direction, and the second length substantially equal to the first length.