Patent ID: 11875859
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A memory device, comprising:
an array of memory cells; and
control circuitry configured to cause the memory device to:
compare input data to data stored in a plurality of memory cells of the array of memory cells connected to a data line, wherein the input data comprises a plurality of digits, and wherein each digit of the input data corresponds to a respective pair of memory cells of the plurality of memory cells;
in response to a mismatch between one digit of the input data and the data stored in the respective pair of memory cells for the one digit of the input data, cause a first level of current to flow from the data line through the respective pair of memory cells for the one digit of the input data;
in response to a mismatch between a different digit of the input data and the data stored in the respective pair of memory cells for the different digit of the input data, cause a second level of current, different than the first level of current, to flow from the data line through the respective pair of memory cells for the different digit of the input data;
compare a representation of a level of current in the data line to a reference;
deem the input data to potentially match the data stored in the plurality of memory cells in response to the representation of the level of current in the data line being less than the reference; and
deem the input data to not match the data stored in the plurality of memory cells in response to the representation of the level of current in the data line being greater than the reference;

wherein the control circuitry being configured to cause the memory device to compare the input data to the data stored in the plurality of memory cells connected to the data line comprises the control circuitry being configured to cause the memory device to respectively compare different digits of the input data to data stored in different strings of series-connected memory cells of the plurality of memory cells while each of the different strings of series-connected memory cells is connected to the data line;
wherein the control circuitry is further configured to cause the memory device to cause different levels of current to respectively flow through the different strings of series-connected memory cells from the data line in response to the different digits of the input data respectively mismatching the data stored in the different strings of series-connected memory cells; and
wherein the control circuitry being configured to cause the memory device to cause the different levels of current to respectively flow through the different strings of series-connected memory cells from the data line comprises the control circuitry being configured to cause the memory device to set a first resistor connected in series with a first string of series-connected memory cells of the different strings of series-connected memory cells to a first resistance, and to set a second resistor connected in series with a second string of series-connected memory cells of the different strings of series-connected memory cells to a second resistance different than the first resistance.