Patent ID: 11915128
Assignee: TOKYO ARTISAN INTELLIGENCE CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 1:
2. A neural network circuit device including at least an input layer, one or more intermediate layers, and an output layer, the one or more intermediate layer including a first intermediate layer and a second intermediate layer, the neural network circuit device comprising, in each of the first intermediate layer and the second intermediate layer:
a convolution operation circuit configured to receive a weight Wi and perform a convolution operation thereof;
a sum circuit configured to take a sum of operation values each subjected to the convolution operation and a bias W0; and
an activating function circuit configured to convert a signal Y generated by taking the sum, using an activating function f(u),
wherein, in the convolution operation circuit in the first intermediate layer, a tri-state {−multibit, 0, +multibit} weight Wi skips a zero weight, and a convolution operation is performed based on a nonzero weight and an input value Xi corresponding thereto, and
wherein, in the convolution operation circuit in the second intermediate layer, a ternary {−1, 0, +1} or a binary {−1, +1} weight Wi skips a zero weight, and a convolution operation is performed based on a nonzero weight and an input value Xi corresponding to the nonzero weight.