Patent ID: 11971832
Assignee: INFINEON TECHNOLOGIES AG
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. An integrated circuit (IC) device, comprising:
a first command-address (CA) bus input that includes a plurality of first parallel CA inputs;
a second CA bus input that includes a plurality of second parallel CA inputs;
a plurality of nonvolatile memory (NVM) cell arrays;
a first command decoder configured to detect commands received at the first CA bus input[s], including express read (NVR) command sequences,
a second command decoder configured to detect commands received at the second CA bus input, including NVR command sequences,
each NVR command sequence including no more than two consecutive NVR read commands distinguishable from other read commands by bit values of the NVR command, and
each NVR command sequence terminates with a receipt of a command that is not an NVR command or an end to a receipt of consecutive NVR read commands;

first access circuits configured to access a first of the NVM cell arrays and output first read data in response to a first NVR command sequence received on the first CA input;
second access circuits configured to access a second of the NVM cell arrays and output second read data in response to a second NVR command sequence received on the second CA bus input; and
a data bus input/output (I/O) including a plurality of parallel data I/Os configured to receive the first read data and second read data in synchronism with rising and falling edges of a timing clock; wherein
the second NVR command sequence follows the first NVR command sequence with no intervening command data, and
the second read data follows the first read data with no intervening read data.