Patent ID: 11879939
Assignee: NXP B.V.
Field: Measurement (Instruments)
Classification: CPC G  H | IPC G  H

Claim 4:
5. The IC of claim 4, wherein the testing system further comprises:
a first logic gate that is coupled to the clocking system, and configured to generate a third pipeline enable signal based on the first clock enable signal and the first pipeline enable signal, wherein the third pipeline enable signal is asserted based on the assertion of the first clock enable signal and the first pipeline enable signal, and the third pipeline enable signal is de-asserted based on the de-assertion of at least one of a group consisting of the first pipeline enable signal and the first clock enable signal; and
a first clock gate that is coupled to the clocking system, the first logic gate, and the first flip-flop, and configured to generate the fourth clock signal based on the first clock signal and the third pipeline enable signal, and provide the fourth clock signal to the first flip-flop, wherein the fourth clock signal is de-asserted based on the de-assertion of the third pipeline enable signal, and the fourth clock signal is same as the first clock signal based on the assertion of the third pipeline enable signal.