Patent ID: 11893332
Assignee: SYNOPSYS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A non-transitory storage medium storing instructions, which when executed by a processor, cause the processor to:
assign a respective variation amount to each class of circuit elements in a plurality of classes of circuit elements in a circuit design, wherein each respective variation amount is a random sample obtained by randomly sampling a variation model which models random parameter variations of a class of circuit elements in the circuit design;
modify a parameter value of each circuit element in a pair of launch path and capture path of a circuit design by a variation amount corresponding to a class of circuit elements to which the circuit element belongs, wherein a first circuit element in the launch path and a second circuit element in the capture path belong to a same class of circuit elements, and wherein the modifying comprises modifying a first parameter value of the first circuit element and a second parameter value of the second circuit element by a same variation amount; and
compute a timing slack for the pair of launch path and capture path based on the modified parameter values.