Patent ID: 11967362
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device, comprising:
a plurality of memory cells configured to store data;
a plurality of digit lines each configured to carry data to and from a respective memory cell of the plurality of memory cells; and
a plurality of sense amplifiers each selectively coupled to respective digit lines of the plurality of digit lines and comprising first and second NMOS transistors and first and second gut nodes that are respectively coupled to the first and second NMOS transistors, wherein each sense amplifier is configured to:
charge a first voltage on the first gut node that at least partially compensates for threshold voltage fluctuations of the first NMOS transistor due to process, voltage, or temperature fluctuations and is proportional to the threshold voltage of the first NMOS transistor;
charge a second voltage on the second gut node that at least partially compensates for threshold voltage fluctuations of the second NMOS transistor due to process, voltage, or temperature fluctuations and is proportional to the threshold voltage of the second NMOS transistor;
amplify a differential voltage between the first and second gut nodes by charging the first gut node and discharging the second gut node based at least in part on respective charges from the plurality of digit lines; and
send the amplified differential voltage to respective digit lines of the plurality of digit lines as a differential signal.