Patent ID: 11928329
Assignee: NXP B.V.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A register management method, comprising:
receiving, by a register management system, a write address and functional data for a write operation to be performed on a register, wherein the functional data comprises (i) a set of write bits and (ii) a set of mask bits associated with the set of write bits, respectively, wherein the set of mask bits comprises one or more mask bits having a first logic state, wherein a number of write bits and a number of mask bits are each half a number of bits in the register, and wherein the one or more mask bits having the first logic state indicate that associated one or more write bits of the set of write bits are to be written to the register, respectively;
selecting, by the register management system, based on the write address, a set of storage elements of the register to perform the write operation, wherein the set of storage elements corresponds to one of a group consisting of a first half of bits in the register and a second half of bits in the register; and
writing, by the register management system, the one or more write bits associated with the one or more mask bits having the first logic state to one or more storage elements of the set of storage elements, respectively.