Patent ID: 11914887
Assignee: MACRONIX INTERNATIONAL CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A storage device, comprising:
a memory circuit, configured to store a plurality of first bits in a first page, a plurality of second bits in a second page and a plurality of third bits in a third page, wherein the memory circuit includes a plurality of multi-level cells, each of the multi-level cells is of a same type and configured to store a same number of bits of data which include at least a corresponding first bit of the plurality of first bits in the first page, a corresponding second bit of the plurality of second bits in the second page, and a corresponding third bit of the plurality of third bits in the third page, such that the plurality of multi-level cells store the first page, the second page, and the third page; and
a control circuit, configured to:
encode weight data with parity fields placed after data fields of the weight data and store the encoded weight data in the plurality of first bits in the first page;
extend normal data with padding in locations to correspond to locations of the parity fields and store the extended normal data in the plurality of second bits in the second page and in the plurality of third bits in the third page; and
read the plurality of first bits according to a one-time reading operation related to the corresponding first bit of each multi-level cell, read the plurality of second bits according to M reading operations related to the corresponding second bit of each multi-level cell, and read the plurality of third bits according to N reading operations related to the corresponding third bit of each multi-level cell, wherein a magnitude of a difference between M and N is less than or equal to 1,
wherein the weight data is used in a multiplication and accumulation operation, and the normal data is data other than weight data.