Patent ID: 11869623
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A device, comprising:
an input stage circuit configured to generate a first input signal having a peak voltage equal to a first voltage and a second input signal based on a third input signal,
wherein the input stage circuit further comprises:
a first inverter configured to generate, in response to the third input signal, the first input signal for outputting a first output signal;
a second inverter configured to generate, in response to the third input signal, a fourth input signal; and
a third inverter configured to generate the second input signal in response to the fourth input signal for outputting a second output signal;

a switching circuit configured to operate in response to a first control signal, and to adjust a voltage level of a first data line from a second voltage, different from the first voltage, to the first voltage in response to an increasing voltage level of the first output signal and a voltage level of a second data line according to the second output signal;
a first latch circuit coupled to the switching circuit by the first data line and the second data line, wherein the first latch circuit is configured to latch a data in response to the first control signal and a second control signal, and configured to adjust the voltage level of the first data line from the first voltage to a third voltage different from the first and second voltages, the first and second control signals having different logic values,
wherein when the first latch circuit latches the data, the first control signal and the first input signal have a same voltage; and
a second latch circuit comprising first to fourth transistors coupled in series between first and second voltage terminals, wherein gates of the first and fourth transistors are coupled to the second data line to receive the second output signal, a gate of the second transistor is configured to receive a third control signal, and a gate of the third transistor is configured to receive the second control signal, the third control signal being different from the first and second control signals, wherein the second latch circuit is configured to generate a third output signal.