Patent ID: 11901025
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. A method of operating a semiconductor memory device including a memory cell array that includes a plurality of memory cell rows, each including a plurality of volatile memory cells, the method comprising:
storing a portion of access addresses by using first repair controllers, which are unused for storing defective addresses, among from a plurality of repair controllers, each including a defective address storage;
generating, by at least one of the first repair controllers, a matching signal based on a comparison of a target access address and stored access addresses therein;
providing, by a connection logic, the matching signal to a corresponding counter in a row hammer management circuit;
storing, by the row hammer management circuit, a counting value of the corresponding counter in an access storage;
determining, by the row hammer management circuit, a hammer address based on comparing the counting value with a reference number; and
performing, by a refresh control circuit, a hammer refresh operation on victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address.