Patent ID: 11901011
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 10:
11. The semiconductor storage device according to claim 1, wherein
the control circuit is further configured to:
after the fourth write operation, perform a fifth write operation to the memory cells formed at the intersections of the third word line and the first and fourth memory pillars;
after the fifth write operation, perform a sixth write operation to the memory cells formed at the intersections of the third word line and the second and third memory pillars;
after the sixth write operation, perform a seventh write operation to the memory cells formed at the intersections of the fourth word line and the first and second memory pillars;
after the seventh write operation, perform an eighth write operation to the memory cells formed at the intersections of the fourth word line and the third and fourth memory pillars;
after the eighth write operation, perform a ninth write operation to the memory cells formed at the intersections of the first word line and the first and fourth memory pillars;
after the ninth write operation, perform a tenth write operation to the memory cells formed at the intersections of the first word line and the second and third memory pillars;
after the tenth write operation, perform an eleventh write operation to the memory cells formed at the intersections of the second word line and the first and second memory pillars; and
after the eleventh write operation, perform a twelfth write operation to the memory cells formed at the intersections of the second word line and the third and fourth memory pillars.