Patent ID: 11907724
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. A system of a processor, the system comprising:
an instruction pipeline comprising a plurality of units; and
a trace controller comprising circuitry to perform operations comprising:
assigning a first group of one or more units of the instruction pipeline of the processor as a frontend group;
assigning a second group of the one or more units of the instruction pipeline of the processor as a backend group;
performing a frontend logout to transfer one or more trace records from the first group to a trace controller during an in-memory trace of an instruction after the first group completes processing;
performing a backend logout to transfer one or more trace records from the second group to the trace controller during the in-memory trace of the instruction after the second group completes processing;
starting a next instruction in the first group of the instruction pipeline before the backend logout completes; and
suppressing generation of one or more new trace records by at least one of the one or more units of the instruction pipeline based on the trace controller sending a new trace record inhibit signal to the one or more units, wherein the suppressing generation of the one or more new trace records is performed to prevent the next instruction from generating one or more new trace records in the first group until after the backend logout completes for the instruction.