Patent ID: 11956376
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 14:
15. The memory device according to claim 14, wherein the processing circuitry is configured to:
drive one of the pair of PMOS transistors and the pair of NMOS transistors of the first bit line sense amplifier having a smaller threshold voltage distribution before driving another of the pair of PMOS transistors and the pair of NMOS transistors of the first bit line sense amplifier; and
drive one of the pair of PMOS transistors and the pair of NMOS transistors of each of the second bit line sense amplifiers having a higher threshold voltage distribution before driving another of the pair of PMOS transistors and the pair of NMOS transistors of each of the second bit line sense amplifiers.