Patent ID: 11961814
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A method comprising:
forming a first grounding feature, a second grounding feature, and first transmission lines on a first dielectric layer, the first transmission lines disposed between the first grounding feature and the second grounding feature;
forming a first conductive via and a second conductive via on, respectively, the first grounding feature and the second grounding feature;
molding a second dielectric layer on the first conductive via, the second conductive via, the first transmission lines, and the first dielectric layer;
planarizing the second dielectric layer to expose the first conductive via and the second conductive via, a top surface of the second dielectric layer being planar with a top surface of the first conductive via and a top surface of the second conductive via; and
forming first grounding plane on the second dielectric layer, the first conductive via, and the second conductive via.