Patent ID: 11963352
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. The semiconductor structure of claim 10, further comprising:
a semiconductor material layer located between the alternating stack and the at least one set of vertical field effect transistors and comprising at least one of a horizontal semiconductor channel and a source region;
metal interconnect structures electrically connecting the electrical nodes of the three-dimensional NAND memory array to the respective one of the at least one set of vertical field effect transistors;
drain regions located within the memory opening fill structures and contacting an end portion of a respective one of the vertical semiconductor channels;
bit lines electrically connected to a respective subset of the drain regions through a respective set of drain contact via structures; and
upper-electrode-connection metal lines located between the alternating stack and the at least one set of vertical field effect transistors.