Patent ID: 11923308
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. An interconnect structure die, comprising:
a plurality of conductive bumps;
a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer;
a first dielectric layer between the first and second metal layers;
a second dielectric layer between the second and third metal layers; and
a third dielectric layer between the third and fourth metal layers,
wherein:
the first and third metal layers include a ground plane within a footprint of the plurality of conductive bumps and signal traces outside the footprint of the plurality of conductive bumps,
the first metal layer includes two signal traces for an individual ground trace in the first metal layer, and
the second metal layer is between the first and third metal layers and includes a ground plane outside the footprint of the plurality of conductive bumps and includes signal traces within the footprint of the plurality of conductive bumps.