Patent ID: 11874897
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. The device of claim 6, further comprising:
local memory coupled to the set of computing logic; and
a connection between the random access memory and the set of computing logic;
wherein the local memory and the set of computing logic are configured as a deep learning accelerator on a first integrated circuit die of a field-programmable gate array (FPGA) or application specific integrated circuit (ASIC);
wherein the local memory is configured to cache matrix operands used by the first unit; and
wherein the random access memory is formed on one or more second integrated circuit dies;
wherein the connection between the random access memory and the set of computing logic is configured with a bandwidth sufficient to load matrix operands from the random access memory to the local memory during a time period in which the first unit performs operations on two matrix operands.