Patent ID: 11921388
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Optics (Instruments)
Classification: CPC G | IPC G

Claim 0:
1. An array substrate, comprising a first base substrate, a plurality of data lines, and a plurality of sub-pixels connected to the plurality of data lines, at least one of the plurality of sub-pixels comprising:
a first insulating layer located on one side of the first base substrate;
a gate located between the first base substrate and the first insulating layer;
an active layer located on one side of the first insulating layer away from the gate;
a pixel electrode located on one side of the first insulating layer away from the first base substrate;
a first electrode located on one side of both the active layer and the pixel electrode away from the first base substrate, wherein the first electrode is connected to the active layer and in contact with the pixel electrode;
a second electrode spaced apart from the first electrode, and connected to the active layer and a data line of the plurality of data lines;
a second insulating layer located on one side of the pixel electrode, the first electrode and the second electrode away from the first base substrate, and defining a first opening, wherein an orthographic projection of the first opening on the first base substrate partially overlaps with an orthographic projection of the pixel electrode on the first base substrate, and partially overlaps with an orthographic projection of the first electrode on the first base substrate;
a connection electrode in contact with the pixel electrode and the first electrode through the first opening, wherein the connection electrode is at least partially located in the first opening; and
a common electrode located on one side of the second insulating layer away from the pixel electrode and spaced apart from the connection electrode;
wherein:
the plurality of sub-pixels comprises a plurality of rows of sub-pixels;
the array substrate further comprises a plurality of common voltage lines connected to the plurality of rows of sub-pixels, and a common voltage line of the plurality of common voltage lines is configured to apply a common voltage to the common electrode;
the common voltage line comprises a first common voltage line portion, a second common voltage line portion and a third common voltage line portion, the third common voltage line portion is located between the first common voltage line portion and the second common voltage line portion, the third common voltage line portion is adjacent to the first common voltage line portion and the second common voltage line portion respectively, a length of the second common voltage line portion in a first direction perpendicular to a second direction in which the common voltage line extends is greater than a length of the first common voltage line portion in the first direction, and the length of the first common voltage line portion in the first direction is greater than a length of the third common voltage line portion in the first direction; and
the common electrode is in contact with the second common voltage line portion through a second opening of the second insulating layer.