Patent ID: 11882707
Assignee: STMICROELECTRONICS (ROUSSET) SAS
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A method, comprising:
forming a first row of transistors arranged along a first direction, the forming the first row of transistors including:
forming a first conduction region having a first dopant type;
forming a common base on the first conduction region, the common base having a second dopant type opposite the first dopant type;
forming a plurality of second conduction regions on the common base, the plurality of second conduction regions having the first dopant type, each of the transistors of the first row including a respective second conduction region;
forming an insulating trench extending in the first direction and in contact with each of the plurality of the transistors of the first row of transistors, the insulating trench extending entirely across the common base and at least partially into the first conduction region; and
forming a plurality of insulation walls extending along a second direction and positioned between adjacent ones of the second conduction regions, the second direction being transverse to the first direction; and

forming a plurality of first conductive layers extending along the second direction, each of the plurality of first conductive layers extending through a respective insulation wall and contacting the common base.