Patent ID: 11950425
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A semiconductor memory device comprising:
mold structures stacked on a first substrate and spaced apart from each other, wherein each of the mold structures includes gate electrodes and first insulating patterns alternately stacked;
block cutting areas extending in a first direction and separating the mold structures into memory cell blocks and a dummy block, wherein each of the memory cell blocks and the dummy block includes a cell region and an extension region;
channel structures that penetrate one of the mold structures in the cell region of the memory cell block and the dummy block;
through structures that penetrate the one of the mold structures in the extension region of the memory cell block;
extension through structures that penetrate the one of the mold structures in the extension region of the dummy block;
a second substrate including peripheral circuit elements respectively corresponding to the mold structures; and
lower metal lines disposed between the peripheral circuit elements and the first substrate,
wherein both one end of the extension through structure is connected to an upper metal line and another end of the extension through structure is connected to one of the lower metal lines to transmit a target signal to each one of the peripheral circuit elements.