Patent ID: 11908514
Assignee: STMICROELECTRONICS (GRENOBLE 2) SAS
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A decoding method for a non-volatile memory device comprising a memory array including a plurality of memory portions, each memory portion comprising a respective plurality of memory cells arranged in rows and columns, wherein the memory portions is arranged in groups, each group of memory portions comprising a plurality of respective memory portions arranged in a row and a plurality of respective wordlines that extend through the respective memory portions, and wherein the memory cells of the memory portions of the group is coupled to the respective wordlines, the method comprising:
selecting, by a pre-decoding stage, a wordline that extends through a group of memory portions and deselecting the other wordlines that extend through the group of memory portions;
subsequently deselecting all the wordlines that extend through the group of memory portions; and
executing for each group of memory portions, wherein executing comprises:
decoupling from or coupling to, by a shared pull-up stage, a node at a first reference potential each wordline that extends through the group of memory portions when the wordline is respectively selected or deselected to impose on each wordline, when deselected, a deselection voltage;
locally coupling, by each pull-down stage of a plurality of pull-down stages distributed along the group of memory portions, each wordline that extends through the group of memory portions when selected, to a node at a second reference potential to impose locally a selection voltage on the wordline;
locally decoupling, by each pull-down stage of the plurality of pull-down stages from the node at the second reference potential, each wordline that extends through the group of memory portions when deselected;
controlling a number of local pull-up stages distributed along the group of memory portions, each local pull-up stage comprising, for each wordline that extends through the group of memory portions, a corresponding local pull-up transistor of an NMOS type, wherein controlling comprises:
controlling the local pull-up transistors of each local pull-up stage so that the local pull-up transistors locally decouple the corresponding wordlines from the node at the first reference potential when one of the wordlines that extend through the group of memory portions is selected; and
controlling the local pull-up transistors of each local pull-up stage so that the local pull-up transistors locally couple the corresponding wordlines to the node at the first reference potential when all the wordlines that extend through the group of memory portions are deselected to restore locally the deselection voltage on the wordline previously selected.