Patent ID: 11894369
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 15:
16. A semiconductor device, comprising:
a substrate;
a plurality of active patterns on the substrate, the plurality of active patterns extending in a first direction and being aligned with each other in a second direction that intersects the first direction;
a device isolation layer between the plurality of active patterns;
a plurality of gate structures spaced apart from each other in the first direction, the plurality of gate structures running across the plurality of active patterns and extending in the second direction;
a plurality of source/drain patterns on opposite sides of each gate structure of the plurality of gate structures;
a plurality of channel patterns between adjacent source/drain patterns of the plurality of source/drain patterns, the plurality of channel patterns protruding upwardly from the device isolation layer;
a plurality of first isolation patterns that respectively penetrate the plurality of gate structures and are aligned with each other along the first direction, each first isolation pattern of the plurality of first isolation patterns separating two gate structures of the plurality of gate structures such that the two gate structures of the plurality of gate structures are spaced apart from each other in the second direction;
a second isolation pattern that extends between adjacent source/drain patterns of the plurality of source/drain patterns and in the second direction from one first isolation pattern of the plurality of first isolation patterns, the second isolation pattern penetrating at least one gate structure of the plurality of gate structures;
a lower dielectric layer between the plurality of gate structures and extending between adjacent first isolation patterns of the plurality of first isolation patterns;
an upper dielectric layer on the lower dielectric layer; and
a plurality of first contacts that penetrate the upper dielectric layer and the lower dielectric layer and correspondingly connect with the plurality of source/drain patterns,
wherein each gate structure of the plurality of gate structures includes:
a gate electrode;
a gate capping pattern on the gate electrode;
a gate dielectric pattern that extends along a bottom surface of the gate electrode; and
a plurality of gate spacers on opposite sidewalls of the gate electrode, and

wherein top surfaces of the plurality of first isolation patterns and a top surface of the second isolation pattern are each located at a level the same as or higher than a level of a top surface of the gate capping pattern of each gate structure of the plurality of gate structures.