Patent ID: 11876517
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An electrical circuit comprising:
a driver circuit; and
a receiver circuit, wherein the receiver circuit includes an evaluation circuit, an adaptive circuit, and a keeper circuit;
wherein the adaptive circuit comprises a first adaptive circuit electrical path that includes a first NFET and a second NFET, and a second adaptive circuit electrical path that includes a first PFET and a second PFET, wherein the first NFET and the first PFET are connected to an adaptive circuit voltage supply, wherein the second NFET and the second PFET are connected to a pull-up transistor of the keeper circuit, wherein a gate of the first NFET and a gate of the second NFET are connected to a differential voltage of the driver circuit, and wherein a gate of the first PFET and a gate of the second PFET are connected to a gate of the pull-up transistor of the keeper circuit;
wherein the evaluation circuit receives a clock signal and an input pulse from the driver circuit during a pre-charge phase;
wherein the evaluation circuit generates an output pulse based on the clock signal and the input pulse during an evaluation phase; and
wherein the keeper circuit maintains a charge of the output pulse until another evaluation phase, wherein the keeper circuit is adapted to the driver circuit by gating a first voltage supply of the driver circuit with a second voltage supply of the keeper circuit.