Patent ID: 11968879
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  Y | IPC H

Claim 10:
11. A display substrate, comprising: a silicon base substrate and a color film layer disposed on the silicon base substrate, the silicon base substrate containing a plurality of metal traces for connecting a display area and a cathode ring with a bonding area respectively; the color film layer comprising a first align mark, and the first align mark having a hollowed-out structure,
wherein a projection of the first align mark on the silicon base substrate and projections of the metal traces on the silicon base substrate comprise overlapping areas,
wherein a length of the first align mark is 50 to 150 microns, a width of the first align mark is 20 to 50 microns; a width of the metal trace is 50 to 150 nanometers, and a spacing between adjacent metal traces is 30 to 50 nanometers, and
wherein a ratio of an area of the metal traces exposed by the first align mark to an area of the first align mark is greater than or equal to 80%.