Patent ID: 11972788
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. A system comprising:
a controller configured to provide a command along with a row address, wherein the controller includes a sample timing circuit configured to provide a sample command signal different from the command; and
a memory comprising a refresh control circuit separate from the controller, wherein the refresh control circuit is configured to detect the row address responsive to the sample command signal provided by the sample timing circuit included in the controller, wherein the refresh control circuit is configured to detect the row address responsive to internal sampling logic of the refresh control circuit, wherein the refresh control circuit is configured to determine if the detected row address is an aggressor address, wherein the memory further comprises an aggressor address storage structure configured to store first aggressor addresses identified by the refresh control circuit and further configured to store second aggressor addresses received from the controller, wherein the second aggressor addresses are identified as aggressor addresses by the controller.