Patent ID: 11908750
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A device comprising:
a first fin extending from a substrate;
a first gate stack over and along sidewalls of the first fin;
a first gate seal spacer along a sidewall of the first gate stack;
a first spacer footing over the first gate seal spacer;
a protection layer disposed along a sidewall of the first gate seal spacer and a top surface of the first spacer footing;
a first gate spacer disposed over the protection layer and the first spacer footing; and
a first source/drain region in the first fin and adjacent the first gate spacer footing, the first spacer footing being between first gate seal spacer and the first source/drain region.