Patent ID: 11882702
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A three-dimensional memory device, comprising:
an alternating stack of insulating layers and electrically conductive layers having a staircase region, a memory array region and an access transistor region located between the staircase region and the memory array region;
memory opening fill structures comprising a respective vertical semiconductor channel and a respective vertical stack of memory elements extending through the alternating stack in the memory array region;
via contact structures contacting the stepped surfaces of the electrically conductive layers at each step in the staircase region;
a vertical stack of access transistors located in the access transistor region; and
a plurality of trenches extending through the alternating stack, wherein the plurality of trenches separate the alternating stack into a plurality of finger regions in the memory array regions but not in the staircase region, and each of the finger regions comprises one of the respective memory blocks.