Patent ID: 11881860
Assignee: SK HYNIX INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. The multi-phase clock signal alignment circuit of claim 11, wherein during a first portion of the second operation:
the clock selection circuit selects the first clock signal as the alpha clock signal and the second clock signal as the beta clock signal,
the first clock delay circuit provides the first selection clock signal by outputting the alpha clock signal passed through one inverter,
the second clock delay circuit provides the second selection clock signal by outputting the beta clock signal,
the phase detection circuit detects a second phase difference between a rising edge of the first selection clock signal and a rising edge of the second selection clock signal, and
the phase control circuit controls a second phase delay circuit so that a falling edge of the first clock signal is adjusted according to the second phase difference.