Patent ID: 11894086
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 18:
19. A control circuit, comprising:
a first clock generator to generate a mission mode clock (MDCK) signal according to an input clock signal and a chip enable (CE) signal; and
a second clock generator to generate a design for testability (DFT) mode clock (DDCK) signal according to the input clock signal and provide the first clock generator with a DFT enable (DFTEN) signal; and
a logic gate to generate an output clock signal according to the MDCK signal or the DDCK signal;
wherein in response to the DFTEN signal being in a high logic state, the output clock signal follows the DDCK signal, and wherein in response to the DFTEN signal being in a low logic state, the output clock signal follows the MDCK signal.