Patent ID: 11894277
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 12:
13. A method comprising:
forming gate spacers on sidewalls of a dummy gate;
etching an opening in the dummy gate, the opening exposing surfaces of the gate spacers;
performing a passivation treatment on the surfaces of the gate spacers exposed by the opening;
extending the opening through the dummy gate using an etch process, the etching process removes first portions of the gate spacers that have been passivated by the passivation treatment without removing second portions of the gate spacers, wherein after extending the opening through the dummy gate, an upper portion of the gate spacers is thinner than a lower portion of the gate spacers;
filling the opening with a dielectric material; and
replacing the dummy gate with a functional gate stack.