Patent ID: 11954366
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A data storage device comprising:
a memory including a plurality of memory dies, the memory configured to:
read data from the plurality of memory dies using one or more multi-commands, and
perform asynchronous independent plane reads (AIPR) on the plurality of memory dies;

a data storage controller including a flash interface module (FIM) configured to communicate with the memory using a bus and channel transfers on the bus,
wherein the channel transfers include a plurality of data transfers of the data that is read and a plurality of overheads associated with performing the AIPR on the plurality of memory dies, and
wherein a number of the plurality of overheads is less than a number of the plurality of data transfers; and
circuitry configured to:
determine whether a current parallelism at the plurality of memory dies is enough to saturate the FIM,
determine whether new commands are issued after a time window, and
hold the new commands for a period of time in response to determining that the current parallelism at the plurality of memory dies is enough to saturate the FIM and in response to determining that the new commands are issued after the time window.