Patent ID: 11907544
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device comprising:
at least one memory array comprising multiple memory cells;
at least one buffer memory;
error logic coupled to the at least one memory array and the at least one buffer memory, the error logic configured to:
determine that data for a read operation includes at least one error, the data corresponding to an address that is associated with the at least one memory array; and
store at least part of the address in the at least one buffer memory based on the at least one error; and

refresh control circuitry coupled to the at least one memory array and configured to:
determine a refresh address for a refresh operation on the at least one memory array; and
write corrected data at the address of the at least one memory array based on the refresh address at least partially matching the address stored in the at least one buffer memory.