Patent ID: 11935622
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A data path architecture, comprising:
a clock generator configured to generate a clock signal that is split into a data path clock signal and a high-speed clock signal; and
a data buffer configured to:
receive data stored in a memory array, wherein the received data is synchronized with the data path clock signal;
receive the high-speed clock signal; and
flush the received data responsive to receiving the high-speed clock signal,

wherein the flushed data includes one or more bytes of invalid data based on a delay difference between the high-speed clock signal and the data path clock signal, and
wherein a controller-side delay is introduced to cause the one or more bytes of invalid data to be ignored or discarded from the flushed data prior to outputting the data from the data path architecture.