Patent ID: 11971780
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A data transmission circuit, comprising:
a first data signal line, configured to transmit odd data and even data, wherein the even data and the odd data are alternately transmitted at intervals, and there is a first time interval between a time of arrival of the even data and a time of arrival of the odd data; and
the data error correction circuit of claim 1, having an input terminal connected to the first data signal line, and an output terminal connected to an output bus, wherein the output bus is electrically connected to a memory block, and
the data error correction circuit is configured to perform error correction on the odd data or the even data when the odd data or the even data is written into the memory block.