Patent ID: 11928465
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A computing system, comprising:
a storage device to store an input value;
a processor to execute an application comprising an instruction for evaluating an elementary function with respect to the input value;
an accelerator circuit, communicatively coupled to the processor, comprising:
a successive cumulative rotation circuit comprising a reconfigurable inner stage to perform a successive cumulative rotation recurrence; and
a determination circuit to:
receive the instruction and the input value;
determine a type of the elementary function based on the instruction; and
responsive to determining that the input value is a fixed-point number, configure the reconfigurable inner stage to a configuration for evaluating the type of the elementary function, wherein the successive cumulative rotation circuit is to calculate an evaluation of the elementary function using the reconfigurable inner stage performing the successive cumulative rotation recurrence; and
an approximation circuit, wherein the determination circuit is further to:
responsive to determining that the input value is a floating-point number, determine whether the input value belongs to a small value range;
responsive to determining that the input value is outside the small value range,
convert the floating-point number into a fixed-point number; and
configure the reconfigurable inner stage to the configuration for evaluating the type of the elementary function, wherein the successive cumulative rotation circuit is to calculate the evaluation of the elementary function using the reconfigurable inner stage performing the successive cumulative rotation recurrence; and
wherein the approximation circuit is to:
responsive to determining that the input value belongs to the small value range, receive the input value and calculate an approximation of the elementary function with respect to the input value.