Patent ID: 11870247
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of providing electrostatic discharge (ESD) protection, comprising:
receiving an input current from an input/output (I/O) pin of a plurality of I/O pins;
responding to an ESD event when a voltage threshold at the I/O pin is met and clamping a voltage to a holding voltage;
during the ESD event, the ESD protection operating in either pull to VDD (PD) mode or pull to VSS (PS) mode;
wherein the PS mode is configured to clamp the voltage at the holding voltage by an ESD path from the I/O pin to VSS through a first series of diodes,
wherein the PD mode is configured to clamp the voltage at a second holding voltage through an ESD path from the I/O pin to VDD through a second series of diodes, and
wherein the first series of diodes include a plurality of shared diodes shared among the plurality of I/O pins.