Patent ID: 11881480
Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 0:
1. A semiconductor structure, comprising:
a substrate including a first region and a second region;
a first isolation structure on the first region, and a first nanostructure and a second nanostructure on two sides of the first isolation structure respectively, wherein the first nanostructure includes a plurality of first nanowires discrete from each other along a direction perpendicular to a surface of the substrate, a first groove is located between adjacent first nanowires, the second nanostructure includes a plurality of second nanowires discrete from each other along a direction perpendicular to the surface of the substrate, and a second groove is located between adjacent second nanowires;
a second isolation structure on the second region, and a third nanostructure and a fourth nanostructure on two sides of the second isolation structure, wherein a top of the second isolation structure is lower than a top of the first isolation structure, the third nanostructure includes a plurality of third nanowires discrete from each other along a direction perpendicular to the surface of the substrate, a third groove is located between adjacent third nanowires, the fourth nanostructure includes a plurality of fourth nanowires discrete from each other along a direction perpendicular to the surface of the substrate, and a fourth groove is located between adjacent fourth nanowires;
a first gate structure and a second gate structure on the first region, wherein the first gate structure is on the first nanostructure and in the first groove, the second gate structure is on the second nanostructure and in the second groove, and the first gate structure and the second gate structure together expose a top surface of the first isolation structure; and
a third gate structure and a fourth gate structure on the second region, wherein the third gate structure is on the third nanostructure and in the third groove, the fourth gate structure is on the fourth nanostructure and in the fourth groove, and the third gate structure and the fourth gate structure are in contact with each other on a top surface of the second isolation structure.