Patent ID: 11895218
Assignee: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. A phase-locked loop comprising:
a power-gating injection-locked frequency multiplier-based phase detector (PG-ILFM PD),
wherein the PG-ILFM PD comprises:
a replica voltage controlled oscillator (R-VCO) configured to cut off the power supply of the R-VCO repeatedly based on a reference signal SREF; and
a fundamental sampling phase detector (FSPD) configured to receive an output signal SILFM of the R-VCO as a reference signal for sampling and detect a phase error of a main voltage controlled oscillator (M-VCO), wherein the phase-locked loop further comprises a frequency offset canceller (FOC) configured to remove a frequency deviation between the R-VCO of the PG-ILFM PD and the M-VCO.