Patent ID: 11876650
Assignee: CADENCE DESIGN SYSTEMS, INC.
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. A method of interpreting an input signal expressing a series of symbols, each of the symbols representing one of a set of possible symbol values, the method comprising:
equalizing the series of symbols to produce a first equalized series of symbols and a second equalized series of symbols;
delaying the first equalized series of symbols to produce a delayed equalized series of symbols;
sampling the second equalized series of symbols to obtain high-confidence symbol decisions and low-confidence symbol decisions;
equalizing the high-confidence symbol decisions and the low-confidence symbol decisions; and
combining the first delayed equalized series of symbols with the high-confidence symbol decisions and the low-confidence symbol decisions to produce a third equalized series of symbols.