Patent ID: 11924785
Assignee: QUALCOMM INCORPORATED
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. An apparatus for wireless communication, comprising:
at least one processor; and
at least one memory coupled to the at least one processor, the at least one memory comprising code executable by the at least one processor to cause the apparatus to:
determine a synchronization signal block (SSB) pattern that identifies SSB positions for a network entity to sweep a set of SSB beams over multiple SSB bursts with gaps between at least some of the SSB positions, wherein the SSB pattern identifies a different subset of the set of SSB beams to use per SSB burst in a periodicity among the multiple SSB bursts;
receive a message indicating which SSBs are to be transmitted in which SSB burst of the multiple SSB bursts; and
monitor SSBs over the multiple SSB bursts in accordance with the SSB pattern and the message, wherein each of the multiple SSB bursts is monitored in a different half frame.