Patent ID: 11955521
Assignee: KYOCERA SLD LASER, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A partially completed semiconductor device for processing, comprising:
a plurality of dies arranged in an array and overlying a surface region of a substrate, each of the plurality of dies comprising an epitaxial material, the epitaxial material comprising a release material overlying the substrate and at least an intrinsic-type or unintentionally doped gallium and nitrogen containing region overlying the release material or at least an n-type gallium and nitrogen containing region overlying the release material or at least a p-type gallium and nitrogen containing region overlying the release material or at least a combination of one or more of the n-type gallium and nitrogen containing region, the p-type gallium and nitrogen containing region, and the intrinsic-type or unintentionally doped gallium and nitrogen containing region overlying the release material, wherein adjacent ones of the plurality of dies in the array are separated by a first pitch;
interface regions overlying the epitaxial material of the plurality of dies, each of the interface regions comprising a metal, a semiconductor, dielectric, oxide, glass, or a polymer, wherein at least a portion of the interface regions are bonded to a carrier wafer to form a bonded structure;
wherein the plurality of dies provided on the substrate are releasable to transfer at least the portion of the plurality of dies to the carrier wafer, wherein adjacent pairs of the transferred dies are configured with a second pitch on the carrier wafer, the second pitch being equal to or greater than the first pitch.