Patent ID: 11934942
Assignee: REBELLIONS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. A neural processing device comprising processing circuitry comprising:
at least one processing engine group comprising a plurality of processing engines,
wherein at least one of the plurality of processing engines comprises a plurality of processing elements,
the plurality of processing elements is reconfigurable,
the processing circuitry is configured to provide the plurality of processing engines with hardware resources,
a compiler stack configured to quantize a deep learning graph to generate a binary code based on a preset calculation code,
wherein the compiler stack comprises a first compiler configured to compile operations of the plurality of processing engines and a second compiler configured to compile operations of a first memory, an interconnection and the at least one of the plurality of processing engines, and
wherein the first compiler is further configured to determine a dimension of the plurality of processing engines and perform, on a circuit, optimization scheduling of the plurality of processing engines; and
wherein at least one of the plurality of processing elements comprises:
an instruction queue configured to receive an instruction including a precision, a source, an opcode, and a destination;
a first register configured to receive the source and the precision from the instruction queue;
a second register configured to receive the opcode from the instruction queue and configured to determine an operator; and
a third register configured to receive the destination and the precision from the instruction queue,
wherein the at least one of the plurality of processing elements is configured to determine an operand through the source and configured to perform precision conversion through the precision.