Patent ID: 11907228
Assignee: ORACLE INTERNATIONAL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A system, comprising:
one or more processors; and
a memory configured to store computer-executable instructions that, when executed by the one or more processors, cause the one or more processors to:
load a plurality of events corresponding to a time interval to a staging area, the staging area implemented in a random access memory (RAM) of a computing device;
identify that a first event and a second event of the plurality of events correspond to the time interval and share a value of a key attribute;
cause to be generated a combined database record in the random access memory (RAM) of the computing device, the combined database record comprising a combination of at least:
attribute information from the first event or the second event; or
the value of the key attribute; and

transmit a single message to update a database, the single message based at least in part on the combined database record.