Patent ID: 11935609
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 17:
18. The method of claim 10, wherein, when executing the linked XOR flash data protection scheme, the data storage controller is further configured to:
generating a plurality of linked XOR parity buffers including a plurality of full XOR parity buffers including the first full XOR parity buffer and a plurality of reduced XOR parity buffers including the first reduced XOR parity buffer;
controlling a memory to store the plurality of linked XOR parity buffers;
determining whether a defect in flash data of the memory is a die page failure; and
responsive to determining that the defect is the die page failure, performing ascending accumulation of linked XOR parity buffers starting from a closest final full XOR parity buffer to a closest reduced XOR parity buffer affected with the die page failure; and
correcting the defect based on the ascending accumulation of the linked XOR parity buffers.