Patent ID: 11868210
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device, comprising:
an array of memory cells;
control circuitry coupled to the array, wherein the control circuitry is configured to:
generate a first plurality of sets of parity data that each protect data stored in a row of memory cells of the array;
generate a second plurality of sets of parity data that each protect data stored in a column of memory cells of the array;
send the first plurality and the second plurality of sets of parity to a host; and
receive ECC data from the host based on the first plurality and the second plurality of sets of parity data; wherein the host generates the ECC data using crossed matrix parity values and the crossed matrix parity values are generated using the first plurality and the second plurality of sets of parity data.