Patent ID: 11899936
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 3:
4. A data transmission circuit, comprising:
a delay module generating a delayed read command after a first preset time delay when a mode register read command is received; and
a mode register data processing unit, connecting to the delay module, wherein the mode register data processing unit reads setting parameters from the mode register in response to the mode register read command, and outputs the setting parameters in response to the delayed read command;
wherein the delay module comprise:
a first delay unit;
a second delay unit, which is connected to an output terminal of the first delay unit; and
a third delay unit, which is connected to an output terminal of the second delay unit and an input terminal of the mode register data processing unit;
wherein the first delay unit generates a first delayed read command after a second preset time delay, when the mode register read command is received;
wherein the second delay unit generates a second delayed read command after a third preset time delay when the first delayed read command is received, and wherein the third preset time equals to an operation delay of a column selection control module;
wherein the third delay unit comprises:
a first sub-delay unit, which is connected to the output terminal of the second delay unit; and
a second sub-delay unit, which is connected to an output terminal of the first sub-delay unit and the input terminal of the mode register data processing unit,
wherein the first sub-delay unit generates a third delayed read command after a fifth preset time delay, when the second delayed read command is received, wherein the fifth preset time is equal to an operation delay of a read-write amplifier;
wherein the second sub-delay unit delays a sixth preset time and then generates the delayed read command when the third delayed read command is received;
wherein, a sum of the fifth preset time and the sixth preset time is equal to the fourth preset time;
wherein the third delay unit delays a fourth preset time and generates the third delayed read command, when the second delayed read command is received; and
wherein, a sum of the second preset time, the third preset time, and the fourth preset time is equal to the first preset time.