Patent ID: 11935949
Assignee: MONOLITHIC 3D INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 14:
15. A 3D semiconductor device, the device comprising:
a first level comprising a first single crystal layer, said first level comprising a plurality of first transistors and at least one first metal layer,
wherein said at least one first metal layer overlays said first single crystal layer, and
wherein said at least one first metal layer comprises interconnects between said first transistors thus comprising forming first control circuits;

a second metal layer overlaying said at least one first metal layer;
a second level overlaying said second metal layer, said second level comprising a plurality of second transistors;
a third level overlaying said second level, said third level comprising a plurality of third transistors,
wherein said second level comprises a plurality of first memory cells, said first memory cells each comprising at least one of said second transistors,
wherein said third level comprises a plurality of second memory cells, said second memory cells each comprising at least one of said third transistors,
wherein at least one of said second memory cells is at least partially disposed atop of said first control circuits, and
wherein said first control circuits are connected to control data written to at least one of said second memory cells;

a third metal layer disposed above said third level;
a fourth metal layer disposed above said third metal layer;
wherein said second transistors comprise second transistor channels,
wherein said third transistors comprise third transistor channels,
wherein at least one of said second transistor channels is aligned to at least one of said third transistor channels with a greater than 1 nm but less than 40 nm alignment error,
wherein at least one of said third transistor channels comprises polysilicon, and
wherein said fourth metal layer has an average thickness which is at least twice an average thickness of said second metal layer; and

a conductive path from said fourth metal layer to said second metal layer,
wherein said conductive path comprises a via disposed through said third level, and
wherein said via has a diameter of less than 1 micron.