Patent ID: 11909388
Assignee: SHENZHEN PANGO MICROSYSTEMS CO., LTD
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 8:
9. A chip, comprising: a field programmable gate array (FPGA) chip body and a terminal resistance circuit;
wherein a high-speed differential I/O pair of the FPGA chip body comprises a first interface and a second interface; and
wherein the terminal resistance circuit comprises:
two resistance circuits connected in series, wherein an end of the series-connected two resistance circuits is electrically connected to the first interface, another end of the series-connected two resistance circuits is electrically connected to the second interface, a wire connected between the two resistance circuits has a target node thereon, and the two resistance circuits are symmetrically arranged with respect to the target node; and
a control circuit, electrically connected to the two resistance circuits and configured to control the two resistance circuits each to be in a turn-off state during powering-on of the chip.