Patent ID: 11928578
Assignee: POSTECH RESEARCH AND BUSINESS DEVELOPMENT FOUNDATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. A sparsity-aware neural processing unit, comprising:
an index matching unit (IMU) comprising a buffer memory comprising a weight buffer memory configured to store weight input channel indices having a non-zero value of a weight and an input activation (IA) buffer memory configured to store IA input channel indices having input activations (IAs), and a comparator array configured to match an index of the non-zero value of the weight to an index of one of the IAs;
a p-way priority encoder configured to receive a maximum of p matched IA/weight pairs in the comparator array; and
a first-in-first-out (FIFO) configured to receive matched IA/weight pairs from the p-way priority encoder one by one to deliver the matched IA/weight pairs to a multiplier one,
wherein the IMU is configured to remove a weight delivered to the FIFO by the p-way priority encoder from the weight buffer memory and rearrange weights not delivered to the FIFO by the p-way priority encoder, as the maximum of the p matched IA/weight pairs are delivered to the p-way priority encoder.