Patent ID: 11972132
Assignee: XILINX, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A device, comprising:
a data processing engine array having a plurality of data processing engines organized in a grid having a plurality of rows and a plurality of columns;
wherein each data processing engine includes a core, a memory module including a memory, and a direct memory access engine;
wherein each data processing engine includes a stream switch, wherein the stream switch of each data processing engine is connected to the core and the direct memory access engine in a same data processing engine, and the stream switch of one or more adjacent data processing engines;
wherein each memory module includes a first memory interface directly coupled to the core in the same data processing engine and one or more second memory interfaces directly coupled to the core of each of the one or more adjacent data processing engines;
wherein each data processing engine further comprises a hardware synchronization circuit including a plurality of hardware locks configured to control access to the memory module in the same data processing engine; and
wherein the hardware synchronization circuit is configured to arbitrate access to the memory module between cores of the one or more adjacent data processing engines with direct access and one or more non-adjacent data processing engines coupled via the stream switch and the direct memory access engine.