Patent ID: 11942142
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. An apparatus comprising:
a memory cell block;
a first subword driver block coupled to the memory cell block, the first subword driver block including:
a first subword driver coupled to a first main word line and a first common transistor, and configured to drive a first even-numbered word line; and
a second subword driver coupled to a second main word line and the first common transistor, and configured to drive a second even-numbered word line; and

a second subword driver block coupled to the memory cell block, the second subword driver block including:
a third subword driver coupled to the first main word line and a second common transistor, and configured to drive a first odd-numbered word line; and
a fourth subword driver coupled to the second main word line and the second common transistor, and configured to drive a second odd-numbered word line, wherein

the first and second subword driver blocks are arranged on opposite sides of the memory cell block.