Patent ID: 11947596
Assignee: QLIKTECH INTERNATIONAL AB
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. The apparatus of claim 6, wherein the first symbol map comprises a first state associated with the first worker node indicative of the first worker node being in a stand-by state, and wherein the processor-executable instructions further cause the apparatus to at least one of:
cause, by the master node, based on the first state, the second worker node to be instantiated;
receive, by the master node from the second worker node, capability information associated with the second worker node;
send, by the master node to the second worker node, based on the capability information and a determination that the first worker node is unavailable, the second task; or
cause, by the master node, based on the first state, the second worker node to generate a second symbol map, wherein the second symbol map bidirectionally indexes the first portion of the data model.