Patent ID: 11906584
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 1:
2. The simulation method according to claim 1, further comprising:
setting a connection between first module data terminals for each of the first semiconductor memory devices of the PCB and first memory data terminals of each of the first semiconductor memory devices, a connection between second module data terminals for each of the second semiconductor memory devices of the PCB and second memory data terminals of each of the second semiconductor memory devices, a connection between third module data terminals for each of the third semiconductor memory devices of the PCB and third memory data terminals of each of the third semiconductor memory devices, and a connection between fourth module data terminals for each of the fourth semiconductor memory devices of the PCB and fourth memory data terminals of each of the fourth semiconductor memory devices, through the GUI, and
wherein, in response to a module test execution command applied through the GUI, executing the test program to apply the control signals to the control signal terminals, to apply test pattern data to first data terminals to fourth data terminals of the PCB, to perform a write operation on a plurality of memory cells of each of the first semiconductor memory devices to the fourth semiconductor memory devices, to perform a read operation of reading data written to the plurality of memory cells of each of the first semiconductor memory devices to the fourth semiconductor memory devices, and to compare the test pattern data and read data output through the first memory data terminals of the first semiconductor memory devices to the fourth memory data terminals of the fourth semiconductor memory devices or read data of inner nodes of each of the first semiconductor memory devices to each of the fourth semiconductor memory devices, and to create a module test result.