Patent ID: 11862219
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 7:
8. A memory cell, comprising:
a write bit line;
a write word line;
a read word line;
a write transistor of a first type, coupled to the write bit line, the write word line and a first node, the write transistor configured to be enabled or disabled in response to a write word line signal; and
a read transistor of the first type, the read transistor comprising:
a drain terminal of the read transistor is directly connected to the read word line; and
a gate terminal of the read transistor coupled to the write transistor by the first node; and
a ferroelectric layer having a polarization state that corresponds to a stored data value in the memory cell;
wherein the write transistor is configured to set the stored data value in the memory cell by a write bit line signal that adjusts the polarization state of the ferroelectric layer.