Patent ID: 11929325
Assignee: QUALCOMM INCORPORATED
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor device, comprising: a routing layer comprising a first track set and a second track set, the first track set comprising a plurality of first tracks and the second track set comprising a plurality of second tracks, wherein within the first track set, a pitch between each pair of adjacent first tracks is a first pitch, wherein within the second track set, a pitch between each pair of adjacent second tracks is a second pitch greater than the first pitch, and wherein the routing layer is a layer within a same intellectual property (IP) block, and wherein within the first track set, a width/spacing (W/S) ratio of at least one first track is a first W/S ratio, wherein within the second track set, a W/S ratio of at least one second track is a second W/S ratio different than the first W/S ratio, and wherein a W/S ratio of a track is a ratio of a width of the track to a spacing between the track and an adjacent track.