Patent ID: 11928067
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 4:
5. The read operation circuit according to claim 1, wherein the data determination module comprises:
a data determination unit, an input terminal of the data determination unit being connected to the memory bank, an output terminal of the data determination unit being connected to the inversion flag signal line, and the data determination unit being configured to set the inversion flag data to High if the number of bits of the low data in the read data is greater than a preset value, and set the inversion flag data to Low if the number of bits of the low data in the read data is less than or equal to the preset value; and
a data selector, an input terminal of the data selector being connected to the data determination unit to receive the read data through the data determination unit, and the input terminal of the data selector being configured to receive the inversion flag data through the inversion flag signal line, an output terminal of the data selector being connected to the global bus, and the data selector being configured to output inverted data of the read data as the global bus data if the inversion flag data is High, and output original read data as the global bus data if the inversion flag data is Low.