Patent ID: 11961587
Assignee: MONTAGE TECHNOLOGY (KUNSHAN) CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. A method for clocking a memory device, wherein the method comprises:
detecting, via a control module, toggling of a plurality pairs of input clock signals and generating an input selection signal and an output selection signal based on a detection result of the toggling of the plurality pairs of input clock signals;
selectively outputting, via an input multiplexer, one pair of the plurality pairs of input clock signals according to the input selection signal;
generating, via a phase locking loop (PLL), a PLL clock signal based on the pair of input clock signals received from the input multiplexer; and
outputting, via at least two sets of output multiplexers, the PLL clock signal as a set of output clock signals to at least one group of memory chips to drive the at least one group of memory chips.