Patent ID: 11894062
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. The controller as set forth in claim 11, wherein the controller, during a neutralization period of time, is further configured to simultaneously:
instruct the memory apparatus to apply an inhibiting voltage to unselected ones of the plurality of bit lines associated with the ones of the memory cells connected to the at least one dummy word line having the threshold voltage not being below the predetermined detection voltage threshold following the erase operation to inhibit programming;
instruct the memory apparatus to ground selected ones of the plurality of bit lines associated with the ones of the memory cells connected to the at least one dummy word line having the threshold voltage being below the predetermined detection voltage threshold following the erase operation to encourage programming;
instruct the memory apparatus to apply a general drain-side voltage to selected ones of the at least one drain-side select gate transistor associated with the ones of the memory cells connected to the at least one dummy word line having the threshold voltage being below the predetermined detection voltage threshold to allow the selected ones of the at least one drain-side select gate transistor to conduct while applying approximately zero volts to unselected ones of the at least one drain-side select gate transistor associated with the ones of the memory cells connected to the at least one dummy word line having the threshold voltage not being below the predetermined detection voltage threshold to prevent the unselected ones of the at least one drain-side select gate transistor from conducting;
instruct the memory apparatus to apply a pass voltage to the at least one dummy word line associated with the ones of the memory cells connected to the at least one dummy word line having the threshold voltage not being below the predetermined detection voltage threshold;
instruct the memory apparatus to apply the at least one programming pulse of the maintenance program voltage to the at least one dummy word line to program the ones of the memory cells connected to the at least one dummy word line having the threshold voltage being below the predetermined detection voltage threshold; and
instruct the memory apparatus to apply approximately zero volts to the at least one source-side select gate transistor to turn off the at least one source-side select gate transistor.