Patent ID: 11948916
Assignee: RENESAS ELECTRONICS CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 0:
1. An electronic device comprising:
a first semiconductor device having a logic circuit;
a second semiconductor device electrically connected to the first semiconductor device and having a memory circuit; and
a wiring substrate on which the first semiconductor device and the second semiconductor device are mounted,
wherein the first semiconductor device has:
a first surface arranged so as to face the wiring substrate; and
a plurality of terminals arranged on the first surface,

wherein the plurality of terminals includes:
a plurality of differential pair terminals electrically connected to the second semiconductor device, differential signals being transmitted to the plurality of differential pair terminals, respectively;
a plurality of reference potential terminals, wherein a reference potential is to be supplied to each of the plurality of reference potential terminals; and
a plurality of first power source terminals, wherein a first power source potential is to be supplied to each of the plurality of first power source terminals,

wherein the first surface includes:
a first side extending in a first direction;
a first region in which the plurality of first power source terminals is arranged; and
a second region arranged between the first side and the first region,

wherein, in the second region, the plurality of differential pair terminals is arranged along the first side,
wherein the plurality of differential pair terminals includes:
a first differential pair terminal constituted by a pair of terminals arranged along a second direction orthogonal to the first direction;
a second differential pair terminal constituted by a pair of terminals arranged along the second direction; and
a third differential pair terminal constituted by a pair of terminals arranged along the second direction, and arranged so as to be adjacent to the first differential pair terminal in the first direction,

wherein the first differential pair terminal and the second differential pair terminal among the plurality of differential pair terminals are arranged so as to be adjacent to each other in the second direction,
wherein a terminal other than the plurality of differential pair terminals is arranged between the first differential pair terminal and the third differential pair terminal,
wherein the wiring substrate has a plurality of wiring layers,
wherein a first wiring layer among the plurality of wiring layers has:
a first power source pattern which is a conductor pattern, wherein the first power source potential is to be supplied to the conductor pattern;
a plurality of through-hole wirings penetrating the plurality of wiring layers in a thickness direction of the wiring substrate; and
a plurality of signal wirings, signals that differ from the differential signals are to be transmitted to the plurality of signal wirings, respectively,

wherein the plurality of through-hole wirings includes:
a differential pair through-hole wiring electrically connected to each of the plurality of differential pair terminals;
a plurality of first power source through-hole wirings connected to the first power source pattern, wherein the first power source potential is to be supplied to each of the plurality of first power source through-hole wirings; and
a plurality of reference potential through-hole wirings, wherein the reference potential is to be supplied to each of the plurality of reference potential through-hole wirings,

wherein the plurality of differential pair through-hole wirings includes:
a first differential pair through-hole wiring constituted by a pair of through-hole wirings arranged along the second direction;
a second differential pair through-hole wiring constituted by a pair of through-hole wirings arranged along the second direction; and
a third differential pair through-hole wiring constituted by a pair of through-hole wirings arranged along the second direction, and arranged so as to be adjacent to the first differential pair through-hole wiring in the first direction,

wherein the first differential pair through-hole wiring and the second differential pair through-hole wiring are arranged along the second direction,
wherein a portion of the first power source pattern is arranged between the first differential pair through-hole wiring and the third differential pair through-hole wiring,
wherein the first power source potential is to be supplied to each of the first semiconductor device and the second semiconductor device,
wherein the first wiring layer has:
a third region overlapping the first semiconductor device in plan view; and
a fourth region overlapping the second semiconductor device in plan view, and

wherein the first power source pattern extends so as to connect the third region and the fourth region.