Patent ID: 11915933
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A manufacturing method of a semiconductor structure, comprising:
providing an initial structure comprising a base, a mask layer formed on the base, and a spacer formed on the mask layer;
forming a filling layer covering the spacer on the initial structure;
removing a filling layer with a first preset thickness through a first etching process, wherein the remaining filling layer after the first etching process covers the spacer, and a first etching rate is adopted in the first etching process;
removing a filling layer with a second preset thickness through a second etching process, and exposing the partial spacer to remove carbon-based polymers at a boundary of at least the partial filling layer, or a boundary of the filling layer and the spacer, or the boundary of at least the partial filling layer and the boundary of the filling layer and the spacer, wherein a second etching rate is adopted in the second etching process, and the second etching rate is smaller than the first etching rate; and
patterning the filling layer and the spacer.