Patent ID: 11940924
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. A memory system comprising:
a nonvolatile memory including a plurality of blocks; and
a memory controller configured to access to the nonvolatile memory in response to an instruction from a host device to manage write and erase of the nonvolatile memory and control a first table, a second table, a first storage area, and a second storage area, wherein
the first table is managed in units of map segments associated with at least one of the plurality of blocks and is used to acquire a physical address of any of the plurality of blocks using a logical address as an index,
the second table includes a plurality of first entries associated with a plurality of map segments included in the first table, and each of the first entries is a 1-bit entry indicating whether a trimming process for deleting invalid data is reserved for the associated map segments,
the first storage area is configured to store a change history of the first table,
the second storage area is configured to store a physical address of a block that is a storage destination of a copy of a changed map segment and a change history of the second table,
the memory controller is further configured to perform, after a power loss occurs, a backup operation to cause the nonvolatile memory to store a copy of the first storage area and a copy of the second storage area; and
the memory controller is further configured not to cause the nonvolatile memory to store a copy of the second table in the backup operation.