Patent ID: 11907115
Assignee: RED HAT, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A system comprising:
a memory;
a processor in communication with the memory;
a hypervisor; and
a guest operating system (OS) configured to:
generate a list including a plurality of hints for a corresponding plurality of memory pages allocated to the guest OS, wherein an order in which each hint of the plurality of hints appears in the list indicates an order in which the guest OS is permitted to free memory pages of the corresponding plurality of memory pages, wherein order of the hints of the plurality of hints is independent of an order of the memory pages of the corresponding plurality of memory pages in the memory, wherein the order in which the guest OS is permitted to free memory pages of the corresponding plurality of memory pages indicates a first memory page and a last memory page and which indicates that the last memory page is not to be freed before the first memory page is freed, wherein each hint of the plurality of hints includes an address value associated with one memory page of the corresponding plurality of memory pages,
store the list in the last memory page, and
pass the list to the hypervisor, wherein the hypervisor is configured to:
free the first memory page according to the order in which each hint of the plurality of hints appears in the list, and
free the last memory page according to the order in which each hint of the plurality of hints appears in the list.