Patent ID: 11893393
Assignee: TESLA, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. A method implemented by a microprocessor system, the method comprising:
receiving an operation for a computational array, wherein the computational array includes a hardware arbiter and a plurality of computation units, wherein each of the plurality of computation units operates on a corresponding value addressed from memory, and wherein the operation is queued in a control queue and causes performance of one or more convolutions associated with weight data and input data;
causing, by the hardware arbiter, a plurality of memory requests associated with the operation to be queued in a single queue, the memory requests being for a subset of the corresponding values, wherein the memory requests are queued with respective metadata identifying, at least, that the memory requests are for weight data or input data, wherein the hardware arbiter is configured to dequeue a particular of the memory requests out-of-order based on a priority associated with the metadata queued with the particular of the memory request; and
triggering, by the hardware arbiter using a control signal, the operation based on granting of the memory requests, wherein the control signal triggers dequeuing of the operation from the control queue.