Patent ID: 11895845
Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. The method for manufacturing a memory device, comprising:
providing, on a substrate, a stack of a plurality of first sacrificial layers and a plurality of second sacrificial layers that are alternately stacked;
forming a plurality of vertical holes penetrating the stack;
forming a first gate dielectric layer corresponding to each first sacrificial layer and a second gate dielectric layer corresponding to each second sacrificial layer on a sidewall of each vertical hole;
filling a semiconductor material in the plurality of vertical holes to form active regions;
replacing the each first sacrificial layer with a first electrode layer; and
replacing the each second sacrificial layer with a second electrode layer,
wherein a first effective work function of a combination of the first electrode layer and the first gate dielectric layer is different from a second effective work function of a combination of the second electrode layer and the second gate dielectric layer.