Patent ID: 11961857
Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 1:
2. The manufacturing apparatus according to claim 1, wherein the vertical transistor manufacturing apparatus is configured to:
form a groove by etching a semiconductor substrate;
implant a conductive impurity into the groove;
form a gate insulating film in the groove, the gate insulating film having a thickness corresponding to a hierarchical level in the groove;
remove the gate insulating film until reaching a depth corresponding to the hierarchical level; and
form a gate electrode in a groove formed in the gate insulating film,
wherein a final thickness of the gate insulating film varies in a stepwise fashion in a direction toward a transfer destination of the electric charge and is formed by repeating the formation of the gate insulating film and the removal of the gate insulating film.