Patent ID: 11881860
Assignee: SK HYNIX INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. The multi-phase clock signal alignment circuit of claim 9, wherein the duty ratio adjustment operation comprises:
a first operation comprising controlling an interval between the first clock signal and the second clock signal and an interval between the third clock signal and the fourth clock signal to be a first interval corresponding to a sum of half a period of the first clock signal and a delay amount of m inverters,
a second operation comprising controlling a falling edge of the first clock signal and a falling edge of the third clock signal to adjust duty ratios of the first clock signal and the third clock signal, and
a third operation comprising controlling a falling edge of the second clock signal and a falling edge of the fourth clock signal to adjust duty ratios of the second clock signal and the fourth clock signal.