Patent ID: 11882688
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 1:
2. The semiconductor memory device of claim 1, further comprising:
a third lower electrode group on the substrate and comprising a plurality of third lower electrodes; and
a third support pattern on side walls of each of the third lower electrodes and connecting each of the third lower electrodes,
wherein the third support pattern is immediately adjacent to the first and second support patterns,
the plurality of third lower electrodes consists of six third edge lower electrodes arranged at respective vertices of a third hexagonal shape and free of electrodes between the respective vertices of the third hexagonal shape, and one third center lower electrode that is centrally positioned within the third hexagonal shape, and
the third center lower electrode is spaced apart from the first center lower electrode in a fifth direction different from the first, second, third, and fourth directions.