Patent ID: 11862280
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 15:
16. An apparatus, comprising:
a first memory array comprising a first plurality of electrodes at a first layer and a first plurality of memory cells at a second layer; and
a plurality of transistors configured to select electrodes from the first plurality of electrodes, the plurality of transistors each comprising:
a semiconductor material at the first layer;
a gate electrode at the second layer;
a dielectric plug that extends through the first layer and the second layer, wherein the semiconductor material at the first layer and the gate electrode at the second layer each at least partially surround the dielectric plug; and
an ohmic material at the first layer that is in contact with the semiconductor material and in contact with an electrode from the first plurality of electrodes.