Patent ID: 11960424
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. A device comprising:
a lane group including a first lane and a second lane to provide communications, each lane being configured to form a link for communicating with a host;
a command queue storing commands for at least one direct memory access (DMA) device, the commands generated based on a request of the host;
a power controller configured to, in response to detecting an event that an amount of the commands stored in the command queue being less than or equal to a reference value, change an operation mode from a first power mode to a second power mode consuming less power than the first power mode, deactivate the second lane, and set the first lane to have a power state different from a power state of the second lane in the second power mode;
a clock controller configured to provide, to the at least one DMA device, an operation clock in the second power mode, the operation clock having a frequency less than a frequency of an operation clock provided in the first power mode based on the number of activated lanes; and
a link controller configured to maintain a state of the link as a normal link state in the second power mode.