Patent ID: 11894856
Assignee: REALTEK SEMICONDUCTOR CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A digital-to-analog conversion (DAC) apparatus having signal calibration mechanism, comprising:
a DAC circuit to receive an input digital signal having an input digital codeword from a signal source to perform digital-to-analog conversion to generate an output analog signal;
an echo transmission circuit to process the output analog signal to generate an echo signal;
a calibration circuit to receive the input digital signal and perform mapping from a codeword offset mapping table according to the input digital codeword to generate an offset signal, wherein the codeword offset mapping table comprises a plurality of correspondence relations each corresponds to a codeword and a codeword offset;
an echo-canceling circuit to process the offset according to a group of echo-canceling coefficients to generate an echo-canceling signal;
an error calculating circuit to perform subtraction between the echo signal and the echo-canceling signal to generate an error signal;
an inverted error calculating circuit to perform one-dimensional inversion on the echo-canceling coefficients and further perform calculation on the inverted echo-canceling coefficients and the error signal to generate an inverted error value; and
an offset updating circuit to update the codeword offset of one of the correspondence relation in the codeword offset mapping table according to the inverted error value based on a path delay of the echo-canceling circuit and the inverted error calculating circuit.