Patent ID: 11889705
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An integrated chip, comprising:
a first interconnect within a first inter-level dielectric (ILD) layer over a substrate;
a memory device disposed over the first interconnect and surrounded by a second ILD layer;
sidewall spacers arranged along opposing sides of the memory device;
an etch stop layer arranged on the sidewall spacers, wherein a top portion of each of the sidewall spacers has an upper surface leveled with an upper surface of the memory device; and
a second interconnect extending from a top of the second ILD layer to the upper surfaces of the memory device, the sidewall spacers, and the etch stop layer, wherein a portion of each of the sidewall spacers adjacent to the top portion of this sidewall spacer is in direct contact with the second interconnect.