Patent ID: 11907681
Assignee: RENESAS ELECTRONICS CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A semiconductor system, comprising:
a data processor;
an accelerator;
a first data transfer circuit;
a second data transfer circuit; and
a central processing unit configured to store descriptors in an external memory, the descriptors instructing operations of the accelerator and the first and second data transfer circuits,
wherein the data processor is configured to 1) sequentially receive first input data, 2) perform data processing on the first input data, and 3) sequentially output first output data as a result of the data processing to the first data transfer circuit,
wherein the first data transfer circuit is configured to 1) receive the first output data from the data processor and 2) output the first output data to a plurality of arithmetic units grouped as a first arithmetic unit group among a plurality of arithmetic units in a parallel arithmetic part of the accelerator, in accordance with the descriptors from the external memory,
wherein the first arithmetic unit group of the parallel arithmetic part of the accelerator is configured to 1) sequentially receive, from the first data transfer circuit, the first output data, 2) perform arithmetic operation in parallel between the first output data and each of a plurality of predetermined data, and 3) output a plurality of arithmetic operation results to the second data transfer circuit, in accordance with the descriptors from the external memory, and
wherein the second data transfer circuit is configured to 1) receive the plurality of arithmetic operation results from the accelerator and 2) output, to the data processor, the plurality of arithmetic operation results in order as the first input data, in accordance with the descriptors from the external memory,
wherein the data processor is configured to sequentially output second output data in parallel with the first output data,
wherein the first data transfer circuit is further configured to selectively output the second output data to a plurality of arithmetic units grouped as a second arithmetic unit group different from the first arithmetic unit group among the plurality of arithmetic units in the parallel arithmetic part of the accelerator, in accordance with the descriptors from the external memory,
wherein the second arithmetic unit group is configured to 1) sequentially receive the second output data from the first data transfer circuit and 2) perform arithmetic operation in parallel between the second output data and each of the plurality of predetermined data, in accordance with the descriptors from the external memory,
wherein the first data transfer circuit is set to a first mode or a second mode based on processing speed of the accelerator with respect to the processing speed of the data processor,
wherein, when the first data transfer circuit is set to the first mode, the first data transfer circuit outputs the first output data and the second output data to the first arithmetic unit group and the second arithmetic unit group, respectively, in accordance with the descriptors from the external memory, and
wherein, when the first data transfer circuit is set to the second mode, the first data transfer circuit selects sequentially the first output data and the second output data and outputs selected results to the first arithmetic unit group and the second arithmetic unit group in accordance with the descriptors from the external memory.