Patent ID: 11869859
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A three-dimensional device structure comprising:
a first die comprising a first semiconductor substrate;
a second die comprising a second semiconductor substrate;
a dielectric encapsulation (DE) layer disposed on a first surface of the first die and surrounding the second die;
a redistribution layer (RDL) structure disposed on the DE layer and the second die;
a through-dielectric via structure that extends through the DE layer and electrically connects the first die to the RDL structure;
a bonding dielectric structure (BDS) comprising a bonding polymer and that bonds the first die and the second die;
a bonding interconnect structure (BIS) that extends through the BDS to bond and electrically connect the first die and the second die; and
a bonding dummy pattern (BDP) that extends through the BDS to bond the first die and the second die, wherein the BDP is electrically conductive and is electrically floated,
wherein a pattern density of the BDP in the BDS is from 80% to 40%.