Patent ID: 11934303
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. An apparatus, comprising:
a memory device; and
a controller coupled with the memory device and configured to cause the apparatus to:
receive, from a host system, a write command that indicates a first set of contiguous logical addresses for a first set of data and a second set of contiguous logical addresses for a second set of data, the first set of contiguous logical addresses being discontiguous with the second set of contiguous logical addresses;
determine, based at least in part on the write command, that the first set of data and the second set of data are included in a sequence of data; and
write, to a non-volatile memory of a memory system, a first set of metadata for the first set of data and a second set of metadata for the second set of data, the first set of metadata indicating that the first set of data is included in the sequence of data and the second set of metadata indicating that the second set of data included in the sequence of data.