Patent ID: 11922846
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. The gate driving circuit according to claim 1, wherein each shift register comprises: an input circuit, a reset circuit, a first control circuit, a second control circuit, a first output circuit, a second output circuit and a frame start circuit; wherein
the input circuit is configured to control a potential of a first node in response to a signal input by the input signal terminal;
the reset circuit is configured to provide a signal input by a first reference signal terminal to the first node in response to a signal input by the reset signal terminal;
the first control circuit is configured to provide the signal of the first reference signal terminal to a second node in response to the signal input by the input signal terminal, control the potentials of the first node and the second node in response to a signal input by a first control signal terminal, provide a signal of a second reference signal terminal to the gate signal output terminal in response to a potential of the second node, and provide the signal of the first reference signal terminal to the output control terminal in response to the potential of the second node;
the second control circuit is configured to provide the signal of the first reference signal terminal to a third node in response to the signal input by the input signal terminal, control the potentials of the first node and the third node in response to a signal input by a second control signal terminal, provide a signal of a second reference signal terminal to the gate signal output terminal in response to a potential of the third node, and provide the signal of the first reference signal terminal to the output control terminal in response to the potential of the third node;
the first output circuit is configured to provide a signal of the clock signal terminal to the gate signal output terminal in response to the potential of the first node;
the second output circuit is configured to provide the signal of the clock signal terminal to the output control terminal in response to the potential of the first node; and
the frame start circuit is configured to provide the signal of the first reference signal terminal to the first node in response to a signal input by a frame start signal terminal.