Patent ID: 11963467
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A method for fabricating an electronic device including a semiconductor memory, the method comprising:
forming first to fourth memory cells arranged in a matrix form along a first direction and a second direction crossing the first direction, each memory cell having a pillar structure that extends vertically from a surface of a substrate and includes a lower portion and an upper portion over the lower portion, the upper portion having a protruding portion that protrudes laterally beyond a sidewall of the lower portion;
forming a liner layer along the surface of the substrate and an entire side surface of each of the first to fourth memory cells without fully filling spaces between the lower portions of the first to fourth memory cells,
wherein the liner layer has a first liner portion disposed over a first protruding portion of the first memory cell, a second liner portion disposed over a second protruding portion of the second memory cell, a third liner portion disposed over a third protruding portion of the third memory cell, and a fourth liner portion disposed over a fourth protruding portion of the fourth memory cell,
wherein among the first to fourth memory cells, two neighboring memory cells in the first direction or the second direction contact each other at a contact portion through corresponding liner portions among the first to fourth liner portions so as to provide spaces located under and over the contact portion, and
wherein an opening space is defined by the first to fourth liner portions in a plan view and surrounded by the first to fourth liner portions; and

providing an insulating material through the opening space so that the insulating material fills the spaces located under and over the contact portion and the opening space, the insulating material having a lower thermal conductivity than the liner layer.