Patent ID: 11881276
Assignee: SK HYNIX INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H  Y | IPC G  H

Claim 14:
15. An error correcting code (ECC) decoder, comprising:
a memory comprising a memory region;
a first converter configured to transmit a hard bit, received from a channel, to the memory to store the hard bit in the memory region during a hard decoding operation, and determine a soft reliability value corresponding to a soft bit set received from the channel and transmit the soft reliability value to the memory to store the soft reliability value in the memory region during a soft decoding operation, the soft bit set including a plurality of soft bits;
a second converter configured to output a hard reliability value corresponding to the hard bit, received from the memory region, during the hard decoding operation, and output the soft reliability value received from the memory region during the soft decoding operation; and
a variable node configured to perform the hard decoding operation using the hard reliability value outputted from the second converter, and perform the soft decoding operation using the soft reliability value outputted from the second converter when the hard decoding operation has failed.