Patent ID: 11880330
Assignee: SHANGHAI CAMBRICON INFORMATION TECHNOLOGY CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 3:
4. The data processing circuit of claim 1, wherein the transmission circuit includes: a second transmission interface, a read/write processing circuit connected to the second transmission interface, and an arbitration circuit connected to the read/write processing circuit, wherein
the read/write processing circuit is configured to receive a data operation signal sent by the at least one machine learning unit through the transmission interface and the second transmission interface, transmit the data operation signal to the arbitration circuit, and return data obtained by the arbitration circuit from the shared memory to the machine learning unit corresponding to the data operation signal through the second transmission interface and the shared data receiving interface; and
the arbitration circuit is configured to arbitrate the data operation signal received from the read/write processing circuit according to a preset arbitration rule, and operate the data in the shared memory according to the data operation signal that has been successfully arbitrated.