Patent ID: 11923369
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 8:
9. An integrated circuit comprising:
a first power rail on a back-side of a substrate, and extending in a first direction;
a first flip-flop coupled to at least the first power rail, and including a first region, the first region comprising:
a first inverter coupled to the first power rail;
a second inverter having a first output pin; and
a first input pin coupled to the first inverter;

a second flip-flop coupled to at least the first power rail, and including a second region, the second region abutting the first region at a first boundary and comprising:
a third inverter coupled to the first power rail;
a fourth inverter having a second output pin; and
a second input pin coupled to the third inverter; and

a first conductive structure on a first metal layer, extending in a second direction different from the first direction, overlapping the first boundary, and electrically coupling the first output pin and the second output pin together, each of the second inverter and the fourth inverter being configured to output a clock signal on the first conductive structure;
wherein the first flip-flop and the second flip-flop are on a front-side of the substrate opposite from the back-side; and
wherein the first input pin and the second input pin are offset from the first boundary in the second direction.