Patent ID: 11917806
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 4:
5. The method of manufacturing a semiconductor structure according to claim 4, wherein the step of forming multiple active pillars on the substrate comprises:
sequentially forming an etching sacrificial layer and a photoresist layer, wherein the etching sacrificial layer and the photoresist layer are stacked on the substrate;
removing a part of the photoresist layer and a part of the etching sacrificial layer, such that a retained photoresist layer and a retain etching sacrificial layer form multiple second grooves arranged at intervals, and each of the second grooves exposes a top surface of one bit line; and
forming the active pillars in the second grooves, wherein the top surface of each of the active pillars is flush with a top surface of the etching sacrificial layer.