Patent ID: 11942433
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A structure comprising:
a die stack comprising:
a first integrated circuit die;
first conductive vias on the first integrated circuit die;
a second integrated circuit die adjacent the first conductive vias, the second integrated circuit die comprising through-substrate vias;
first reflowable connectors bonding the second integrated circuit die to the first integrated circuit die; and
a first encapsulant encapsulating the second integrated circuit die and the first conductive vias, the first encapsulant physically contacting sidewalls of the first conductive vias, surfaces of the first encapsulant, the second integrated circuit die, and the first conductive vias being coplanar.