Patent ID: 11881251
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A system, comprising:
a host device, and
a memory device coupled with the host device, the memory device comprising:
a memory array having a row and a set of columns associated with the row; and
peripheral circuitry coupled with the memory array, the peripheral circuitry configured to:
receive, from the host device, a command directed to the row;
activate the row in response to receiving the command;
write, to two or more columns of the set, local data not received from the host device in connection with the command, wherein to write the local data to the two or more columns of the set, the peripheral circuitry is configured to write a pattern of bits retrieved from a single register of the memory device to each column of the two or more columns; and
deactivate the row based, at least in part, on writing the data to the two or more columns of the set.