Patent ID: 11960412
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G  H

Claim 12:
13. An apparatus that manages data in a NAND flash storage system, comprising:
a processor; and
a memory, coupled to the processor, comprising instructions that when executed by the processor are configured to:
receive an empty data segment directive from a host at a storage controller, the empty data segment directive includes a logical identifier associated with a physical storage location;
return a data string comprising predetermined data in response to a read command that requests to read data associated with the logical identifier included in the empty data segment directive;
maintain an index of mapping between the logical identifier and the physical storage location;
in response to the empty data segment directive, update the index to indicate data at the physical storage location does not need to be preserved;
monitor one or more physical storage locations, including the physical storage location, to determine a percentage of the one or more physical storage locations that do not need to be preserved; and
initiate garbage collection on the one or more physical storage locations in response to the percentage reaches a threshold,
wherein at least two of the following conditions individually trigger garbage collection: a lack of available storage capacity in one or more blocks of the one or more physical storage locations, a percentage of the physical storage locations that do not need to be preserved exceeds a first threshold, and an error detection rate for the one or more physical storage locations exceeds a second threshold.