Patent ID: 11972838
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. The signal processing circuit according to claim 14, wherein:
the first latch comprises a first inverter and a second inverter; a head end of the first inverter is connected to a tail end of the second inverter, and a tail end of the first inverter is connected to a head end of the second inverter; and a control terminal of the second inverter is further connected to the even clock;
the first latch further comprises a third inverter; and a control terminal of the third inverter receives the command address signal and the even clock, and an output terminal of the third inverter is connected to a control terminal of the first inverter;
the first latch further comprises a fourth inverter, and a control terminal of the fourth inverter is connected to an output terminal of the first inverter and the even clock;
the first latch further comprises a fifth inverter, and a control terminal of the fifth inverter is connected to an output terminal of the fourth inverter; and
the first latch further comprises a sixth inverter; and a control terminal of the sixth inverter is connected to an output terminal of the fifth inverter and the even clock, and an output terminal of the fifth inverter serves as an output terminal of the first signal latch circuit.