Patent ID: 11889694
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A semiconductor structure comprising a memory die, wherein the memory die comprises:
an alternating stack of insulating layers and electrically conductive layers overlying a substrate and laterally extending through a series of regions that comprises, in a spatial order along a first horizontal direction, a first contact region, a first memory array region, an auxiliary contact region, a second memory array region, and a second contact region;
arrays of memory openings located in the first memory array region and the second memory array region; and
arrays of memory opening fill structures located within the arrays of memory openings and comprising a respective vertical stack of memory elements, wherein:
the alternating stack of insulating layers and electrically conductive layers comprises a lower layer stack including a first subset of the insulating layers and a first subset of the electrically conductive layers located underneath a horizontal plane, and an upper layer stack including a second subset of the insulating layers and a second subset of the electrically conductive layers located above the horizontal plane;
the first contact region and the second contact region comprise first contact via structures contacting a respective electrically conductive layer of the first subset of the electrically conductive layers; and
the auxiliary staircase region comprises second contact via structures contacting a respective electrically conductive layer of the second subset of the electrically conductive layers.