Patent ID: 11880225
Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 4:
5. A data transfer system comprising:
a slave device; and
a host device that is connected to the slave device via at least a power supply line, a clock line, a command line, and a data line, wherein
the host device supplies a power to the slave device via the power supply line after being connected to the slave device,
the host device supplies a first clock having a first frequency and a first voltage value to the slave device via the clock line,
the host device drives the command line at a high level to a low level,
the host device stops the supply of the first clock,
the host device supplies a second clock having a second frequency and a second voltage value to the slave device via the clock line in a state where the data line is driven to a low level,
the slave device drives the data line to a high level within a first predetermined period after the supply of the second clock, and transmits a plurality of tuning blocks to the host device from the slave device via the data line within a second predetermined period at an interval of at least a third predetermined period,
the host device performs tuning for adjusting punching timing by using the plurality of tuning blocks received via the data line,
the host device receives boot data from the slave device via the data line and performs activation using the received boot data, and
the third predetermined period is defined by a clock period between data blocks at a time of continuously transmitting the data blocks after activation of the slave device and by a clock period defined by a data structure of a block pattern included in the plurality of tuning blocks.