Patent ID: 11928441
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 16:
17. A semiconductor memory device comprising:
a memory cell region including a first conductive element;
a peripheral circuit region which includes a second conductive element vertically connected to the first conductive element, and is vertically connected to the memory cell region through the first and second conductive elements;
a plurality of cell strings each of which includes a plurality of memory cells in the memory cell region, the plurality of cell strings including a plurality of word lines connected to the plurality of memory cells, a plurality of bit lines connected to one end of the plurality of cell strings, and a ground selection line connected to the other end of the plurality of cell strings;
a state machine configured to output a plurality of state signals in response to operation commands of the plurality of cell strings inside the peripheral circuit region, the plurality of state signals including a first state signal output from a first output terminal, and a second state signal output after the output of the first state signal from a second output terminal different from the first output terminal;
a logical sum calculator configured to perform a logical sum calculation based on at least one of the first state signal and the second state signal; and
control logic including an accumulation circuit configured to receive the output of the logical sum calculator as a clock signal, and to output a toggle signal to one probing pad in response to the clock signal, the accumulation circuit being connected to the probing pad through a Through Hole Via (THV) penetrating the memory cell region.