Patent ID: 11901445
Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. A method of fabricating a transistor, the method comprising:
forming source and drain contacts on a buffer layer;
forming a barrier layer on the buffer layer, between the source and drain contacts;
forming a conductive member on the barrier layer, wherein the conductive member comprises a p-doped III-V compound;
forming a dielectric stack on the barrier layer and on the conductive member, wherein the dielectric stack comprises a first dielectric layer and a second dielectric layer on the first dielectric layer;
forming a first trench and a second trench in the dielectric stack, wherein the first trench penetrates through the first dielectric layer and the second dielectric layer such that a top surface of the conductive member, at least one sidewall of the first dielectric layer and at least one sidewall of the second dielectric layer are exposed in the first trench, wherein the first dielectric layer contacts the top surface of the conductive member, and wherein the second trench penetrates through the second dielectric layer such that a top surface of the first dielectric layer and at least one sidewall of the second dielectric layer are exposed in the second trench; and
forming a gate metal on the dielectric stack, wherein the gate metal contacts the conductive member through the first trench, and wherein the gate metal contacts the first dielectric layer through the second trench.