Patent ID: 11876647
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A method for controlling a semiconductor system,
the semiconductor system including:
a first memory device that includes
a first memory core configured to store data,
four first input/output terminals, and
four first circuits each configured to calibrate an output impedance at a corresponding one of the first input/output terminals;

a second memory device that includes
a second memory core configured to store data,
four second input/output terminals each connected to a corresponding one of the first input/output terminals, and
four second circuits each configured to calibrate an output impedance at a corresponding one of the second input/output terminals;

a third memory device that includes
a third memory core configured to store data,
four third input/output terminals each connected to a corresponding one of the first input/output terminals and a corresponding one of the second input/output terminals, and
four third circuits each configured to calibrate an output impedance at a corresponding one of the third input/output terminals;

a fourth memory device that includes
a fourth memory core configured to store data,
four fourth input/output terminals each connected to a corresponding one of the first input/output terminals, a corresponding one of the second input/output terminals, and a corresponding one of the third input/output terminals, and
four fourth circuits each configured to calibrate an output impedance at a corresponding one of the fourth input/output terminals; and

four signal lines each connected to a corresponding one of the first input/output terminals, a corresponding one of the second input/output terminals, a corresponding one of the third input/output terminals, and a corresponding one of the fourth input/output terminals, the method comprising:
sending a first calibration command including an address of the first memory device to the signal lines, thereby causing the first circuits of the first memory device to start a first calibration operation to calibrate the output impedance at the first input/output terminals while issuing a signal indicating that the first memory device is in a busy state, and to terminate the first calibration operation while issuing a signal indicating that the first memory device is in a ready state upon elapse of a first period from when the first calibration operation has started; and
after the signal indicating that the first memory device is in the ready state is issued, sending a second calibration command including at least the address of the first memory device to the signal lines, thereby:
causing the second circuits of the second memory device to start a second calibration operation to calibrate the output impedance at the second input/output terminals while issuing a signal indicating that the second memory device is in the busy state, and to terminate the second calibration operation while issuing a signal indicating that the second memory device is in the ready state upon elapse of a second period from when the second calibration operation has started,
causing the third circuits of the third memory device to start a third calibration operation to calibrate the output impedance at the third input/output terminals while issuing a signal indicating that the third memory device is in the busy state, and to terminate the third calibration operation while issuing a signal indicating that the third memory device is in the ready state upon elapse of a third period from when the third calibration operation has started, and
causing the fourth circuits of the fourth memory device to start a fourth calibration operation to calibrate the output impedance at the fourth input/output terminals while issuing a signal indicating that the fourth memory device is in the busy state, and to terminate the fourth calibration operation while issuing a signal indicating that the third memory device is in the ready state upon elapse of a fourth period from when the third calibration operation has started, wherein

during the second calibration operation, one of the second circuits of the second memory device establishes an electric connection with one of the first circuits of the first memory device via one of the signal lines,
during the third calibration operation, one of the third circuits of the third memory device establishes an electric connection with another one of the first circuits of the first memory device via another one of the signal lines,
during the fourth calibration operation, one of the fourth circuits of the fourth memory device establishes an electric connection with still another one of the first circuits of the first memory device via still another one of the signal lines,
the second, third, and fourth calibration operations start at the same time in response to the second calibration command, and
each of the second, third, and fourth periods is being shorter than the first period.