Patent ID: 11963347
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A memory device comprising:
a transistor over a substrate and comprising:
a semiconductor fin over the substrate and extending in a first direction in a top view;
a first gate structure over the substrate and covering the semiconductor fin; and
a first source/drain region and a second source/drain region on the semiconductor fin and on opposite sides of the first gate structure;

an anti-fuse element over the substrate, wherein the transistor and the anti-fuse element are arranged in the first direction in the top view, and the anti-fuse element comprises:
the semiconductor fin; and
a second gate structure across the semiconductor fin and adjacent to the first source/drain region;

a first gate via connected to the first gate structure; and
a second gate via connected to the second gate structure, wherein a minimum distance between the first gate via and the semiconductor fin is greater than a minimum distance between the second gate via and the semiconductor fin in a cross-sectional view.