Patent ID: 11862516
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A semiconductor structure manufacturing method, comprising the following steps of:
providing a semiconductor substrate;
forming a plurality of first reaction layers and a plurality of second reaction layers on the semiconductor substrate, the plurality of first reaction layers and the plurality of second reaction layers being alternately arranged;
thermally reacting at least a portion of each of the plurality of first reaction layers with at least a portion of each of the plurality of second reaction layers adjacent to at least one of the plurality of first reaction layers, to form an amorphous diffusion barrier layer between each adjacent first reaction layer and each adjacent second reaction layer; and
forming a conductive layer on an unreacted region of an uppermost layer of the plurality of first reaction layers and the plurality of second reaction layers, the unreacted region being an adhesion layer or a seed layer for the conductive layer;
wherein, before forming the conductive layer on the unreacted region of the uppermost layer, the method further comprises:
removing a portion of the unreacted region along a thickness direction; and

wherein a ratio of a thickness of each of the plurality of first reaction layers to a thickness of each of the plurality of second reaction layers ranges from 1:0.5 to 1:4.