Patent ID: 11961557
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A memory device comprising:
a first interconnect;
a second interconnect;
a memory cell coupled between the first interconnect and the second interconnect and including a variable resistance element and a switching element, the variable resistance element including a first ferromagnetic layer, a second ferromagnetic layer, and an insulating layer between the first ferromagnetic layer and the second ferromagnetic layer; and
a first circuit configured to:
perform a first operation and a second operation;
apply a first voltage to the first interconnect, bring the first interconnect into a floating state after the application of the first voltage, and apply a second voltage to the second interconnect while the first interconnect is in the floating state, in the first operation, the second voltage being lower than the first voltage; and
apply a third voltage to the second interconnect, bring the second interconnect into a floating state after the application of the third voltage, and apply a fourth voltage to the first interconnect while the second interconnect is in the floating state, in the second operation, the third voltage being different from the first voltage, the fourth voltage being lower than the third voltage.