Patent ID: 11900885
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 10:
11. The display panel according to claim 10, wherein the gate drive circuit further includes a plurality of blanking input circuits; a blanking input circuit is electrically connected to at least two adjacent shift registers;
the blanking input circuit is configured to, during a blanking period of the frame display phase, control a corresponding shift register to input a blanking control signal to pixel drive circuits in a corresponding row, so that the pixel drive circuits obtain sensing signals;
the blanking input circuit includes:
a selection control circuit electrically connected to a selection control signal terminal, a shift signal terminal, a second voltage signal terminal, and a first blanking node; and the selection control circuit being configured to transmit a shift signal received at the shift signal terminal to the first blanking node under control of a selection control signal transmitted by the selection control signal terminal;
a second input circuit electrically connected to the first blanking node, a second blanking node, and a second clock signal terminal or the first voltage signal terminal; and the second input circuit being configured to transmit a second clock signal received at the second clock signal terminal or the first voltage signal received at the first voltage signal terminal to the second blanking node under control of a voltage of the first blanking node; and
at least two transmission circuits, a transmission circuit being electrically connected to the pull-up node of a corresponding shift register; the transmission circuit being further electrically connected to the second blanking node and the second clock signal terminal; and
the transmission circuit being configured to transmit the second clock signal or the first voltage signal received at the second blanking node to the pull-up node under control of the second clock signal transmitted by the second clock signal terminal;
wherein the second input circuit and the transmission circuit each include at least one device group; and each of device groups included in the second input circuit and the transmission circuit is located in a region between two adjacent sub-pixels in a row of sub-pixels where a corresponding shift register is located; and
at least one device group used to be electrically connected to the second blanking node in the second input circuit and at least one device group used to be electrically connected to the second blanking node in the at least two transmission circuits are electrically connected to the second blanking node through a node voltage transmission line.