Patent ID: 11923251
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  C | IPC C  H

Claim 0:
1. An integrated circuit device comprising:
a bulk semiconductor substrate;
a first semiconductor fin and a second semiconductor fin protruding higher than the bulk semiconductor substrate;
a dielectric region between the first semiconductor fin and the second semiconductor fin, wherein the dielectric region comprises:
a contact etch stop layer (CESL); and
an inter-layer dielectric (ILD) over and contacting a bottom portion of the CESL, wherein the CESL and the ILD are formed of different materials, and wherein the CESL continuously extends from a first level lower than a bottom surface of the ILD to a top surface of the ILD;

a first Fin Field-Effect Transistor (FinFET) comprising a first gate stack on sidewalls and a top surface of the first semiconductor fin, wherein the first FinFET comprises a first source/drain region contacting a first sidewall of the dielectric region;
a second FinFET comprising a second gate stack on sidewalls and a top surface of the second semiconductor fin, wherein the second FinFET comprises a second source/drain region contacting a second sidewall of the dielectric region, and wherein the first sidewall and the second sidewall are opposing sidewalls of the dielectric region;
a dielectric hard mask over and contacting the dielectric region, wherein a first edge of the dielectric hard mask is aligned to a respective second edge of the first gate stack;
a gate hard mask over and contacting the first gate stack, wherein a third edge of the gate hard mask contacts the first edge of the dielectric hard mask to form a vertical interface; and
a gate contact plug over and contacting the first gate stack, wherein the gate contact plug penetrates through the gate hard mask.