Patent ID: 11954035
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 13:
14. A memory device, comprising:
a memory array comprising a first set of memory cells;
a cache comprising a second set of memory cells; and
one or more processors coupled with the memory array and the cache, the one or more processors configured to cause the memory device to:
read information from the memory array;
write the information to an address of the cache based at least in part on reading the information from the memory array;
store, based at least in part on reading the information from the memory array, an indication that the address of the cache is not available for eviction;
perform a quantity of access operations on the memory array after storing the indication; and
remove the indication that the address of the cache is not available for eviction based at least in part on the quantity of access operations performed on the memory array after storing the indication being greater than a threshold quantity of access operations.