Patent ID: 11962309
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G  Y | IPC H

Claim 0:
1. A phase adjusting circuit, comprising a detection circuit, a comparison circuit, a counter, and an adjustment circuit that are connected in sequence; wherein,
the detection circuit is configured to detect a phase difference between a first clock signal and a second clock signal to obtain a first detection signal and a second detection signal;
the comparison circuit is configured to perform duty cycle comparison of the first detection signal and the second detection signal to obtain a counting indication signal;
the counter is configured to count a number of pulses of a preset counting clock signal based on the counting indication signal to obtain a count value; and
the adjustment circuit is configured to perform phase adjustment of the second clock signal based on the count value, so that the phase difference between the first clock signal and the second clock signal is a preset value.