Patent ID: 11899800
Assignee: VERACODE, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. An apparatus comprising:
a processor; and
a non-transitory computer-readable medium having instructions stored thereon that are executable by the processor to cause the apparatus to,
train and test a set of classifiers with k-fold cross validation on a first dataset comprising labels and vectors representing software components,
wherein each label indicates whether a respective one of the software components has a vulnerability or flaw,
wherein a set of probability values generated for each of the vectors by the set of classifiers from the testing is stored;

train a logistic regression model with the stored sets of probability values and the labels; and
combine the trained set of classifiers and the trained logistic regression model to generate an ensemble that indicates whether a software component has a flaw.