Patent ID: 11960728
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. A method of interfacing a plurality of memory dies, comprising:
receiving at least one of a first address and a first chip selection signal;
selecting, based on the at least one of the first address and the first chip selection signal, a first register of a plurality of registers corresponding to the plurality of memory dies, respectively;
providing, based on first information stored in the first register, a first command to a data operation control circuit connected to the plurality of dies;
receiving a second command, at least one of a second address and a second chip selection signal;
selecting, based on the at least one of the second address and the second chip selection signal, a second register of the plurality of registers; and
storing, based on the second command, second information in the second register,
wherein the selecting the second register comprises providing, based on the at least one of the second address and the second chip selection signal, a second control signal to a demultiplexer connected to the plurality of registers.