Patent ID: 11942371
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 17:
18. A method, comprising:
forming source/drain regions over a substrate;
forming a gate structure laterally between the source/drain regions;
forming gate spacers on opposite sidewalls of the gate structure;
forming a dielectric cap over the gate structure;
forming source/drain contacts over the source/drain regions, the source/drain contacts having top surfaces higher than a bottom surface of the dielectric cap;
forming an oxide-based etch-resistant layer over the dielectric cap;
forming a nitride-based etch stop layer over the oxide-based etch-resistant layer, wherein the oxide-based etch-resistant layer is separated from a top surface of one of the gate spacers by a first distance, and the oxide-based etch-resistant layer is separated from a top surface of the gate structure by a second distance greater than the first distance;
forming an interlayer dielectric (ILD) layer over the nitride-based etch stop layer; and
forming a via structure extending through the ILD layer, the nitride-based etch stop layer, and the oxide-based etch-resistant layer to electrically connect with one of the source/drain contacts.