Patent ID: 11887687
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. A memory device of comprising:
a memory array comprising a plurality of memory cells configured to store first data, wherein the first data is output from the memory array based at least in part on the memory device receiving a first command;
a first buffer coupled with the memory array and configured to buffer the first data based at least in part on the first data being output from the memory array, wherein the first buffer comprises a first-in first-out (FIFO) buffer having a first depth;
a register configured to store second data, wherein the second data is output from the register based at least in part on the memory device receiving a second command different than the first command;
a second buffer coupled with the register and configured to buffer the second data based at least in part on the second data being output from the register, the second buffer comprising a FIFO buffer having a second depth different than the first depth, wherein a buffer depth is associated with a quantity of data bursts that a respective buffer can store during a duration; and
a multiplexer coupled with the first buffer, the second buffer, and a data bus, wherein the multiplexer is configured to output the first data and the second data on the data bus during consecutive sets of clock cycles.