Patent ID: 11901436
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 17:
18. A method comprising:
forming a first fin and a second fin, the first and second fins each comprising alternately stacking first semiconductor layers and second semiconductor layers;
forming dummy gate structures across the first and second fins, respectively;
forming gate spacers on either side of the dummy gate structures;
removing the dummy gate structures and the first semiconductor layers to form a plurality of spaces between corresponding ones of the second semiconductor layers;
depositing in sequence a first gate dielectric layer and a second gate dielectric layer into the plurality of spaces between corresponding ones of the second semiconductor layers;
performing an atomic layer deposition (ALD) process to form a hard mask layer on the second gate dielectric layer, the ALD process comprising pulsing a first precursor into a deposition chamber for a first pulse time, and purging the first precursor from the deposition chamber for a first purge time, the first purge time being at least a time within a range of twelve times the first pulse time to eighteen times the first pulse time;
patterning the hard mask layer to expose a portion of the second gate dielectric layer; and
etching the exposed portion of the second gate dielectric layer.