Patent ID: 11955174
Assignee: ARISTA NETWORKS, INC.
Field: Digital communication (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 7:
8. An apparatus for selectively connecting memory to processing nodes, said apparatus comprising:
a content-addressable memory (CAM) having an interface;
a plurality of processing nodes, each node having an interface;
a connection matrix;
a first data bus that connects the connection matrix to the interface of the CAM;
a plurality of additional data buses, wherein each additional data bus connects the connection matrix to the interface of one of the plurality of processing nodes; and
a control interface in communication with the connection matrix,
wherein, in response to receiving a first control input from the control interface, the connection matrix establishes a first electrical path between the CAM and a first processing node among the plurality of processing nodes,
wherein in response to receiving a second control input from the control interface, the connection matrix disconnects the first electrical path between the CAM and the first processing node and establishes a second electrical path between the CAM and a second processing node among the plurality processing nodes.