Patent ID: 11915941
Assignee: TOKYO ELECTRON LIMITED
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 4:
5. The method of claim 1, wherein said adjusting the purge time of the first purge step and/or the purge time of the second purge step comprises:
reducing the purge time of the first purge step and/or the purge time of the second purge step during one or more first cycles of the wet ALE process to increase the etch rate achieved during the one or more first cycles; and
increasing the purge time of the first purge step and/or the purge time of the second purge step during one or more second cycles of the wet ALE process to reduce the post-etch surface roughness achieved during the one or more second cycles, wherein the one or more second cycles are performed after the one or more first cycles.