Patent ID: 11916012
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A manufacturing method for a semiconductor structure, wherein the manufacturing method comprises:
providing a first semiconductor die, wherein the first semiconductor die comprises:
a first semiconductor substrate;
a first interconnect structure formed on the first semiconductor substrate;
a first bonding conductor formed on the first interconnect structure; and
a conductive via extending from the first interconnect structure toward a back surface of the first semiconductor substrate;

thinning the first semiconductor substrate to expose the conductive via so as to form a through semiconductor via of the first semiconductor die; and
bonding a second semiconductor die to the first semiconductor die, wherein the second semiconductor die comprises:
a second semiconductor substrate comprising an active surface facing the back surface of the first semiconductor substrate;
a second interconnect structure between the second semiconductor substrate and the first semiconductor substrate; and
a second bonding conductor between the second interconnect structure and the first semiconductor substrate and bonded to the through semiconductor via of the first semiconductor die, wherein the second bonding conductor is substantially aligned with the first bonding conductor and is smaller than the through semiconductor via.