Patent ID: 11901913
Assignee: MITSUBISHI ELECTRIC CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An error correction decoding apparatus to perform error correction decoding, the apparatus comprising:
a parity bit syndrome circuit to perform a syndrome operation of parity bits included in a multilevel modulation symbol, the multilevel modulation symbol having being error correction coded by the error correction coding apparatus using, as an error correction code sequence, a frame of m bits×n parallel symbols defining a multilevel symbol and input in m-bit parallel where m and n are positive integers, the parity bits being error correction coded, the error correction coding apparatus replacing known bits assigned to a bit sequence specified in the error correction code sequence, with the parity bits, the multilevel modulation symbol being input in m-bit parallel;
an information bit syndrome circuit to perform a syndrome operation of information bits and the known bits included in the multilevel modulation symbol, the known bits replacing the parity bits included in the multilevel modulation symbol; and
an error correction decoding circuit to perform error correction decoding, using syndrome data calculated by the parity bit syndrome circuit and the information bit syndrome circuit.