Patent ID: 11930635
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 6:
7. The method of manufacturing the semiconductor structure according to claim 1, wherein etching the insulation layer, the metal conductive layer, and the non-metal conductive layer to form the bitline structure comprises:
forming a second hard mask layer on the insulation layer, the second hard mask layer having a second graphical target pattern, the second graphical target pattern defining the bitline structure;
with the metal conductive layer serving as an etching stop layer, using the second hard mask layer as a mask to etch the insulation layer to transfer the second graphical target pattern to the insulation layer;
removing the second hard mask layer; and
with the insulation layer serving as a mask, etching the metal conductive layer and the non-metal conductive layer to form the bitline structure.