Patent ID: 11935835
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A method of manufacturing a semiconductor device, the method comprising:
forming transistors on a substrate such that each of the transistors includes a gate structure and a source/drain layer adjacent thereto;
forming a first insulating interlayer on the substrate to cover the transistors;
forming first and second contact plugs through the first insulating interlayer to contact the source/drain layers, respectively;
removing upper portions of the first contact plugs;
implanting ions into an upper portion of the first insulating interlayer;
forming a second insulating interlayer on the first insulating interlayer and the first and second contact plugs; and
forming third and fourth contact plugs through the first and second insulating interlayers such that the third contact plug contacts one of the gate structures and the fourth contact plug commonly contacts at least one of the gate structures and the second contact plug adjacent thereto.