Patent ID: 11973044
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An integrated memory assembly apparatus, comprising:
a first semiconductor die comprising:
a first non-volatile memory structure adjacent a second non-volatile memory structure with a gap between the first non-volatile memory structure and the second non-volatile memory structure, the first non-volatile memory structure having a stack of alternating conductive and dielectric layers forming a first staircase at an edge of the first non-volatile memory structure facing the second non-volatile memory structure, the second non-volatile memory structure having a stack of alternating conductive and dielectric layers forming a second staircase at an edge of the second non-volatile memory structure facing the first non-volatile memory structure,
a first top metal layer positioned above the first non-volatile memory structure and the second non-volatile memory structure,
a first bottom metal layer positioned below the first non-volatile memory structure and the second non-volatile memory structure, and
a first metal interlayer segment positioned in the gap, positioned between the first staircase and the second staircase, connected to the first top metal layer and connected to the first bottom metal layer; and

a second semiconductor die physically connected to the first semiconductor die, the second semiconductor die comprising:
an electrical circuit, and
a metal transmission layer connected to the electrical circuit and the first metal interlayer segment via the first bottom metal layer, the metal transmission layer is configured to communicate a signal from the first top metal layer to the electrical circuit.