Patent ID: 11955568
Assignee: MURATA MANUFACTURING CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A capacitor structure, comprising:
a silicon substrate having a trench structure formed therein;
a dielectric layer disposed over a surface of the trench structure, conformal to said surface of the trench structure; and
a filling layer disposed over the dielectric layer and into the trench structure, the filling layer comprising:
a conductive layer;
a polymer layer; and
a further conductive layer disposed over the polymer layer and into the trench structure,

wherein the conductive layer is disposed between the dielectric layer and the polymer layer, and
wherein a trench depth of the trench structure ranges between 10 and 100 microns, an aspect ratio of the trench structure ranges between 1:10 and 1:60, a thickness of the dielectric layer ranges between 0.6 and 1.5 microns, a thickness of the conductive layer ranges between 10 and 500 nanometers, a thickness of the polymer layer ranges between 150 and 2000 nanometers, and a thickness of the further conductive layer ranges between 10 and 50 nanometers.