Patent ID: 11908785
Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A semiconductor device comprising:
a first board that has a first end surface and a second end surface opposite to the first end surface;
a second board that is attached to the second end surface of the first board;
a plurality of first electrodes that are provided on the first end surface;
a second electrode that is provided on the second end surface and electrically coupled to an electrode of the second board;
an internal wiring that is provided inside the first board and electrically coupled to the second electrode;
a plurality of third electrodes that are provided inside the first board and electrically couple the first electrodes to the internal wiring; and
a strain sensor that is provided inside the first board and measures a strain generated in the first board,
wherein a linear expansion coefficient of each of the third electrodes is larger than a linear expansion coefficient of the first board,
the first board includes a plurality of layers that are laminated,
the linear expansion coefficient of each of the third electrodes is larger than a linear expansion coefficient of the internal wiring,
the strain sensor is provided inside a strain sensor forming layer, the strain sensor forming layer including two insulating layers and a semiconductor layer that forms the strain sensor, the semiconductor layer being provided between the two insulating layers, and
the plurality of third electrodes pass through one of the two insulating layers.