Patent ID: 11887952
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A package structure, comprising:
a first dielectric layer;
a first semiconductor device over the first dielectric layer;
a first redistribution line in the first dielectric layer;
a first molding material surrounding the first semiconductor device;
a conductive ball over the first molding material;
a second dielectric layer over the conductive ball;
a second semiconductor device over the second dielectric layer;
a second redistribution line in the second dielectric layer and electrically connected to the conductive ball;
a conductive through-via over the second dielectric layer;
a second molding material surrounding the second semiconductor device and the conductive through-via; and
a buffer layer on a top surface of the first molding material, wherein the conductive ball extends upward through the buffer layer to a position below a bottom surface of the second dielectric layer.