Patent ID: 11916548
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. An integrated circuit (IC) device package comprising:
an overvoltage protection circuit configured to output a first reset signal on a first redistribution layer (RDL) of the IC device package; and
an IC chip comprising:
a first contact pad coupled to the first RDL;
a second contact pad coupled to a second RDL of the IC device package configured to have a power supply voltage;
a third contact pad coupled to a third RDL of the IC device package configured to have a reference voltage; and
a buffer circuit comprising:
an input terminal configured to receive the first reset signal from the first contact pad;
an output terminal;
an inverter; and
a resistor-capacitor (RC) circuit coupled in series with the inverter between the input terminal and the output terminal,

wherein
the RC circuit comprises:
an NMOS transistor coupled between an RC circuit output terminal and a reference node coupled to the third contact pad;
a resistor coupled between the RC circuit output terminal and a power supply node coupled to the second contact pad; and
a capacitor coupled between the RC circuit output terminal and one of the power supply node or the reference node, and

the inverter and the RC circuit are configured to generate a second reset signal at the output terminal based on the first reset signal.