Patent ID: 11894062
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 18:
19. The method as set forth in claim 18, further including, during the neutralization period of time, the steps of:
applying a general drain-side voltage to selected ones of the at least one drain-side select gate transistor associated with the ones of the memory cells connected to the at least one dummy word line having the threshold voltage being below the predetermined detection voltage threshold to allow the selected ones of the at least one drain-side select gate transistor to conduct while applying approximately zero volts to unselected ones of the at least one drain-side select gate transistor associated with the ones of the memory cells connected to the at least one dummy word line having the threshold voltage not being below the predetermined detection voltage threshold to prevent the unselected ones of the at least one drain-side select gate transistor from conducting;
applying a pass voltage to the at least one dummy word line associated with the ones of the memory cells connected to the at least one dummy word line having the threshold voltage not being below the predetermined detection voltage threshold; and
applying approximately zero volts to the at least one source-side select gate transistor to turn off the at least one source-side select gate transistor.