Patent ID: 11955197
Assignee: ROBERT BOSCH GMBH
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 4:
5. The memory device as recited in claim 4, further comprising:
word lines which are each respectively connected to multiple memory cells, an application of a word line voltage to a word line enabling access via the bit lines to the memory cells that are connected to the word line;
wherein for numbers p and q in the range from 0 to S−1, where q differs from p, the controller is configured to:
prompt an application of the word line voltage on one of the word lines,
transfer the bit shift circuit into the pth circuit state,
subsequent to transferring the bit shift circuit to the pth circuit state, transfer the bit shift circuit into the qth circuit state, and
terminate the application of the word line voltage.