Patent ID: 11947379
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 11:
12. The host interface of claim 10, wherein the positive edge detector includes; a first positive edge synchronizer that allows a first-positive synchronizer signal to toggle at a next positive edge of the internal clock signal in response to toggling of the response, a second positive edge synchronizer that allows a second-positive synchronizer signal to toggle at a next positive edge of the internal clock signal in response to toggling of the first-positive synchronizer signal, a third positive edge synchronizer that allows a third-positive synchronizer signal to toggle at a next positive edge of the internal clock signal in response to toggling of the second-positive synchronizer signal, and a positive-logic-operation AND gate that performs a logical AND operation on the third-positive synchronizer signal and an inverted version of the second-positive synchronizer signal to generate the positive edge detection signal, and
the negative edge detector includes; a first negative edge synchronizer that allows a first-negative synchronizer signal to toggle at a next negative edge of the internal clock signal in response to toggling of the response, a second negative edge synchronizer that allows a second-negative synchronizer signal to toggle at a next negative edge of the internal clock signal in response to toggling of the first-negative synchronizer signal, a third negative edge synchronizer that allows a third-negative synchronizer signal to toggle at a next negative edge of the internal clock signal in response to toggling of the second-negative synchronizer signal, and a negative-logic-operation AND gate that performs a logical AND operation on the third-negative synchronizer signal and an inverted version of the second-negative synchronizer signal to generate the negative edge detection signal.