Patent ID: 11869627
Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 14:
15. A semiconductor device comprising:
a first control circuit comprising a first transistor;
a second control circuit over the first control circuit, the second control circuit comprising a second transistor;
a memory circuit over the first control circuit, the memory circuit comprising a third transistor; and
a global bit line and an inverted global bit line, each of which being configured to transmit a signal between the first control circuit and the second control circuit,
wherein a channel of the first transistor is provided in a silicon substrate,
wherein a channel of the second transistor comprises a first metal oxide,
wherein a channel of the third transistor comprises a second metal oxide,
wherein the first control circuit comprises a sense amplifier,
wherein the sense amplifier comprises an amplifier circuit, an output terminal, an inverted output terminal, a first switch, a second switch, and a signal inverter circuit,
wherein the first switch is provided between the global bit line and the output terminal,
wherein the second switch is provided between the inverted global bit line and the inverted output terminal,
wherein the signal inverter circuit is configured to supply an inverted potential of logic data corresponding to the potentials of the global bit line and the inverted global bit line to the output terminal and the inverted output terminal that are electrically connected to the amplifier circuit,
wherein in a first period for reading data from the memory circuit to the first control circuit, the second control circuit is configured to control whether electric charge precharged to the global bit line and the inverted global bit line is discharged or not in accordance with the data read from the memory circuit,
wherein in the first period, the first switch and the second switch are turned off, and the inverted potential of logic data corresponding to the potentials of the global bit line and the inverted global bit line is supplied to the output terminal and the inverted output terminal that are electrically connected to the amplifier circuit, and
wherein in a second period for refreshing the data read from the memory circuit, the first switch and the second switch are turned on, and potentials of the output terminal and the inverted output terminal, which are amplified by the amplifier circuit, are supplied to the global bit line and the inverted global bit line.