Patent ID: 11869574
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 15:
16. The semiconductor memory device of claim 14,
wherein the third unit cell comprises a first p-channel metal-oxide semiconductor (PMOS) transistor and a first n-channel metal-oxide semiconductor (NMOS) transistor connected in series between the power supply voltage and the ground voltage, wherein each gate of the first PMOS transistor and the first NMOS transistor is configured to receive the intermediate clock signal,
wherein each of the plurality of fourth unit cells comprises a second PMOS transistor, a third PMOS transistor, a second NMOS transistor, and a third NMOS transistor connected in series between the power supply voltage and the ground voltage,
wherein each gate of the second PMOS transistor and the third NMOS transistor is configured to receive the intermediate clock signal, and
wherein each gate of the third PMOS transistor and the second NMOS transistor is configured to receive a corresponding bit of a second inverted control code set obtained by inverting the second control code set.