Patent ID: 11881858
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 11:
12. A memory, comprising:
a clock generation circuit, the clock generation circuit comprising:
an oscillation circuit, configured to generate a first oscillation signal and a second oscillation signal, wherein a frequency of the first oscillation signal is same as a frequency of the second oscillation signal, and a phase of the first oscillation signal is opposite to a phase of the second oscillation signal;
a comparison unit, configured to receive the first oscillation signal and the second oscillation signal, and compare at least one of: a duty cycle of the first oscillation signal or a duty cycle of the second oscillation signal; and
a logical unit, connected to the comparison unit and the oscillation circuit, and configured to control the oscillation circuit according to an output result of the comparison unit, so that the duty cycle of the first oscillation signal and the duty cycle of the second oscillation signal reach a preset range;

wherein the comparison unit comprises:
an integral unit, having a first input end for receiving one of the first oscillation signal or the second oscillation signal, and a second input end for receiving another one of the second oscillation signal or the first oscillation signal; and
a comparator, connected to an output end of the integral unit; and

wherein the integral unit is configured such that:
the first input end of the integral unit receives the first oscillation signal when a turnover identification signal is at a low level, and receives the second oscillation signal when the turnover identification signal is at a high level; and
the second input end of the integral unit receives the second oscillation signal when the turnover identification signal is at the low level, and receives the first oscillation signal when the turnover identification signal is at the high level.