Patent ID: 11916077
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A method, comprising:
coupling a first reference metal line to a first/source drain terminal of a first transistor with a first gate terminal, the first source/drain terminal, and a second source/drain terminal;
coupling a second reference metal line to a third source/drain terminal of a second transistor with a second gate terminal, the third source/drain terminal, and a fourth source/drain terminal;
coupling, at a same interconnect level as the first and second reference metal lines, a local interconnect structure to the first and second gate terminals;
coupling, above an interconnect level of the local interconnect structure, a first interconnect structure to the second source/drain terminal;
coupling, above the interconnect level of the local interconnect structure, a second interconnect structure to the third source/drain terminal; and
routing, above the interconnect level of the local interconnect structure and at a same interconnect level as the first and second interconnect structures, a third interconnect structure.