Patent ID: 11929323
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 14:
15. The method of claim 12, wherein forming a memory array wafer comprises:
forming a preliminary stack structure above doped epitaxial silicon, the preliminary stack structure comprising sacrificial material vertically interleaved with the insulative material;
forming openings extending through the preliminary stack structure and the doped epitaxial silicon and into the base structure;
annealing the doped epitaxial silicon to form the doped semiconductive material therefrom;
forming the cell pillar structures within the openings;
forming slots extending through the preliminary stack structure;
replacing the sacrificial material with the conductive material after forming the slots to form the stack structure; and
forming the digit lines over the pillar structures after replacing the sacrificial material with the conductive material.