Patent ID: 11862464
Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 7:
8. The method for manufacturing the three-dimensional semiconductor device according to claim 7, wherein the plurality of semiconductor pillars consists of at least a first semiconductor pillar, a second semiconductor pillar, and a third semiconductor pillar being adjacent and aligned in a first direction or a second direction orthogonal to the first direction,
the method comprising steps of:
forming a first gate insulating layer surrounding side surfaces of the first semiconductor pillar, the second semiconductor pillar, and the third semiconductor pillar; and
forming a first gate conductor layer surrounding the first gate insulating layer,
wherein the first gate conductor layer is formed filling between at least two of the first semiconductor pillar, the second semiconductor pillar, and the third semiconductor pillar.