Patent ID: 11860225
Assignee: RENESAS ELECTRONICS CORPORATION
Field: Measurement (Instruments)
Classification: CPC G | IPC G

Claim 6:
7. The method of manufacturing the semiconductor device according to claim 1,
wherein the test board includes a plurality of the terminals,
wherein the first semiconductor package includes a plurality of the first external terminals,
wherein the second semiconductor package includes a plurality of the second external terminals,
wherein the unit houses a plurality of the probe pins,
wherein, in the (c), the plurality of first external terminals of the first semiconductor package is brought into contact with the first tip portions of the plurality of probe pins, respectively, and the second tip portions of the plurality of probe pins are brought into contact with the plurality of terminals of the test board, respectively, thereby performing the electrical test of the first semiconductor package, and
wherein, in the (f), the plurality of second external terminals of the second semiconductor package is brought into contact with the second tip portions of the plurality of probe pins, respectively, and the first tip portions of the plurality of probe pins is brought into contact with the plurality of terminals of the test board, respectively, thereby performing the electrical test of the second semiconductor package.