Patent ID: 11947769
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 4:
5. The system of claim 1, wherein the one or more processors are further configured to:
receive a second set of pin data comprising a second plurality of locations;
define a second set of geofence boundaries based on the second plurality of locations;
define a second local map comprising at least the second set of geofence boundaries, wherein defining compares the second set of geofence boundaries to standard map boundaries;
define a third set of geofence boundaries based on comparing the first local map to the second local map identify a second pin area, wherein the third set of geofence boundaries contain both the first set of geofence boundaries and the second set of geofence boundaries; and
define a second local map comprising at least the third set of geofence boundaries, wherein defining compares the third set of geofence boundaries to standard map boundaries.