Patent ID: 11923283
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A semiconductor package comprising:
a first package substrate;
a first semiconductor chip on a top surface of the first package substrate;
a second package substrate on a top surface of the first semiconductor chip;
a second semiconductor chip on a top surface of the second package substrate;
an interposer spaced apart from the first semiconductor chip and between the first semiconductor chip and the second package substrate;
a first connection member between the first package substrate and the interposer, the first connection member electrically connecting the first package substrate to the interposer;
a molding layer on the top surface of the first package substrate, the molding layer covering the first connection member and the first semiconductor chip; and
a second connection member between the interposer and the second package substrate, the second connection member electrically connecting the interposer to the second package substrate,
wherein the interposer includes an interposer trench recessed from a bottom surface of the interposer and an interposer hole penetrating the interposer, the bottom surface of the interposer facing both the top surface of the first semiconductor chip and the top surface of the first package substrate,
the molding layer fills the interposer trench and the interposer hole,
a bottommost surface of the interposer is directly above the top surface of the first semiconductor chip, based on the top surface of the first package substrate, and
a maximum width of the interposer trench is smaller than a maximum width of the first semiconductor chip.