Patent ID: 11899829
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 13:
14. A memory comprising:
a processor;
a memory array;
a cache register configured to store an access code for the memory array; and
a non-transitory computer readable medium stored with executable instructions that, when executed by the processor, causes the memory to perform operations comprising:
obtaining, at access logic, a memory command comprising a physical memory address and a provided access code associated with a particular memory region of a plurality of memory regions of a plurality of memories including the memory;
comparing, at the access logic, the provided access code with the access code stored in the cache register to determine that the access code is a match; and
responsive to the match determination, providing the physical memory address to an I/O control unit coupled to the memory array;
obtaining, at a control logic of the memory, a control signal indicative of the memory command;
responsive to the match determination, obtaining, at the control logic of the memory, an additional control signal indicative that data is to be accessed at the physical memory address; and
responsive to the additional control signal indicative, asserting a Ready/Busy (R/B) pin of the control logic.