Patent ID: 11871572
Assignee: nan
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 2:
3. The method of claim 1 further comprising forming the high-k dielectric material within the first voids to line the first voids; wherein the forming of the conductive levels comprises forming conductive material within the lined first voids; wherein the forming of the second voids exposes portions of the high-k dielectric material above and below the conductive material; wherein the second voids have a vertical thickness; and further comprising;
removing the exposed portions of the high-k dielectric material;
forming sacrificial material within the second voids to narrow said vertical thickness;
after the vertical thickness is narrowed, extending the second voids through the charge-blocking material and then through the charge-storage material to divide the charge-storage material into the vertically-spaced segments;
removing the sacrificial material; and
after removing the sacrificial material, at least partially filling the second voids with insulative material.