Patent ID: 11955978
Assignee: BLUE CHEETAH ANALOG DESIGN, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 11:
12. The circuit of claim 1, wherein the first transistor comprises a first transistor gate terminal arranged to receive a first control signal, the fourth transistor comprises a fourth transistor gate terminal arranged to receive a second control signal, the fifth transistor comprises a fifth transistor gate terminal arranged to receive the second control signal, the first switch is arranged to receive a third control signal, the second switch is arranged to receive the third control signal, the third switch is arranged to receive a fifth control signal, the fourth switch is arranged to receive a fourth control signal, and the fifth switch is arranged to receive the fourth control signal, wherein the first control signal, the second control signal, the third control signal, the fourth control signal, and the fifth control signal comprise clock signals configured to:
pre-charge to the bias voltage the first node, the second node, and the third node during a first operating phase;
sample the first input voltage at the fourth node and sample the second input voltage at the fifth node during a second operating phase;
pull-up the second node and the third node from the bias voltage to a supply voltage during a third operating phase; and
pull-down the first node from the bias voltage to a ground during a fourth operating phase.