Patent ID: 11966582
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. A data storage device, comprising:
memory means; and
a controller coupled to the memory means, wherein the controller is configured to:
identify a bottleneck that is occurring in a data/control path between a host device and the memory device, wherein the bottleneck occurs either in an input queue corresponding to a hardware module of a plurality of hardware modules or in the hardware module of the plurality of hardware modules; and
execute a predefined bottleneck release operation based on the identified bottleneck, wherein the plurality of hardware modules comprises:
a flash translation layer;
a plurality of random access memories (RAMs), wherein the plurality of RAMs is two or more different types of RAMs;
one or more encoders;
one or more decoders;
a plurality of low level flash sequencers (LLFS) central processing units (CPUs), each configured to generate one or more commands;
a host interface module (HIM);
a flash interface module (FIM); and
a plurality of data path CPUs, wherein a data path CPU is configured to track a state of a respective location of the memory means.