Patent ID: 11910590
Assignee: SK HYNIX INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. A semiconductor memory device, comprising:
a substrate; and
a memory cell array including memory cells stacked along a direction vertical to the substrate,
wherein each of the memory cells comprises:
a bit line vertically oriented to the substrate;
a capacitor laterally spaced apart from the bit line;
an active layer laterally oriented between the bit line and the capacitor; and
a word line disposed on an upper portion of the active layer and laterally oriented to intersect with the active layer,
a bit line contact node disposed between one side of the active layer and the bit line;
a bit line side-ohmic contact disposed between the bit line contact node and the bit line;
a storage contact node disposed between another side of the active layer and the capacitor; and
a storage node side-ohmic contact disposed between the storage contact node and the capacitor,
wherein the active layer includes a thin-body channel, a thickness of the thin-body channel is smaller than a thickness of the word line.