Patent ID: 11972793
Assignee: MAVAGAIL TECHNOLOGY, LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An integrated circuit device, comprising:
an array of memory cells arranged in a plurality of rows and columns;
an array power control circuit providing at least one first end power select control signal and at least one second end power control signal;
a first end power select circuit disposed at a first end of the array of memory cells and coupled to receive the at least one first end power select control signal, the first end power select circuit includes at least one controllable impedance path coupled between a power supply potential and at least one array power line;
a second end power select circuit disposed at a second end opposite the first end of the array of memory cells and coupled to receive the at least one second end power select control signal, the second end power select circuit includes at least one controllable impedance path coupled between a power supply potential and the at least one array power line; and
a row decoder circuit coupled to activate one of a plurality of word lines to become an active one of a plurality of word lines in a first mode of operation
wherein during at least a portion of the first mode of operation, the controllable impedance path of the first end power select circuit is set in a low impedance state in response to the at least one first end power select control signal when the active one of the plurality of word lines is physically closer to the second end of the array of memory cells and is set in a high impedance state in response to the at least one first end power select control signal when the active one of the plurality of word lines is physically closer to the first end of the array of memory cells.