Patent ID: 11972832
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 11:
12. The command decoder circuit of claim 9, wherein the enable signal generation unit is further configured to:
generate a low-level enable signal in response to the first command signal being at a high level and the second command signal or the timing signal being at a high level; or
generate a high-level enable signal in response to the first command signal, the second command signal, or the timing signal being at a low level, and wherein
the clock gate is further configured to:
cut off the dynamic clock signal in response to the chip select signal or the enable signal being at a low level; or
generate the dynamic clock signal based on the system clock signal in response to the chip select signal and the enable signal being at a high level.