Patent ID: 11960400
Assignee: CADENCE DESIGN SYSTEMS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus, comprising:
a plurality of first-level cache memory circuits configured to store respective pluralities of cache lines;
a second-level cache memory circuit configured to:, send a plurality of probe requests regarding a particular cache line to the plurality of first-level cache memory circuits in response to receiving an acquire request for the particular cache line from a particular first-level cache memory circuit of the plurality of first-level cache memory circuits;
in response to a determination that a different first-level cache memory circuit of the plurality of first-level cache memory circuits is evicting a local copy of the particular cache line: receive the local copy of the particular cache line from the different first-level cache memory circuit,
write the local copy of the particular cache line to a higher-level memory circuit; and send a prefetch request for a new copy of the particular cache line to the higher-level memory circuit while the different first-level cache memory circuit responds to a corresponding one of the plurality of probe requests, wherein the second-level cache memory circuit includes a control circuit, and a plurality of banks, wherein the control circuit is configured to select a particular bank of the plurality of banks, wherein the particular bank includes an input queue circuit and a plurality of pipeline stages configured to perform corresponding operations, and wherein the second-level cache memory circuit is further configured to transfer the acquire request from the input queue circuit to an initial pipeline stage of the plurality of pipeline stages based on a length of time since the acquire request was received.