Patent ID: 11894264
Assignee: NANYA TECHNOLOGY CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for fabricating a semiconductor device, comprising:
providing a substrate;
forming a sacrificial structure above the substrate;
forming a supporting liner covering the sacrificial structure by the steps of:
forming a top segment of the supporting liner to cover a top surface of the sacrificial structure;
forming side segments of the supporting liner to cover sidewalls of the sacrificial structure; and
forming a bottom segment of the supporting liner to cover a top surface of the substrate;
forming an energy-removable layer covering the top segment, the side segments, and the bottom segment of the supporting liner;
performing a planarization process to remove a top portion of the energy-removable layer and the top segment of the supporting liner until the top surface of the sacrificial structure is exposed;
performing an etch process to remove the sacrificial structure and concurrently form a first opening in the energy-removable layer;
forming covering liners on sidewalls of the first opening and on a top surface of the energy-removable layer by the steps of:
forming a side segment of each of the covering liners to cover on the sidewall of the first opening; and
forming a top segment of each of the covering liners to cover the top surface of the energy-removable layer, wherein the top segment of the covering liner is integrally extended from the side segment thereof end-to-end;
forming a first conductive feature in the first opening; and
applying an energy source to transform the energy-removable layer into a porous insulating layer.