Patent ID: 11914718
Assignee: STMICROELECTRONICS (GRAND OUEST) SAS
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. A data processing device comprising:
a monotonic counter configured to:
generate a first count value for a first boot phase; and
after generating the first count value, generate a second count value for a second boot phase, wherein the second count value is greater than the first count value; and

a memory including an access control circuit and containing first and second boot codes, wherein the access control circuit is configured to:
read, based on the first count value during the first boot phase, the first boot code;
prevent, based on the second count value during the second boot phase, reading of the first boot code; and
read, based on the second count value during the second boot phase, the second boot code.