Patent ID: 11961787
Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. The method according to claim 16, wherein forming the interconnection wire layer and the via hole layer comprises:
forming a dielectric material with a first height on the carrier substrate;
forming an interconnection wire on the dielectric material with the first height, wherein the first height is set so that an interconnection wire and a corresponding conductive structure in the vertical stack are at a substantially same height;
forming a dielectric material with a second height on the carrier substrate, wherein the second height is set so that an interconnection wire formed thereon subsequently and a corresponding conductive structure in the vertical stack are at a substantially same height; and
forming a via hole in the dielectric material with the second height.