Patent ID: 11877457
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 8:
9. A method for accessing a memory cell of a vertical three-dimensional (3D) memory array of memory cells formed in a memory layer of a memory device, the memory device including a peripheral circuit layer having a sense amplifier and decoding circuitry for word lines and bit lines associated with the array of memory cells, comprising:
applying a first voltage to a selected word line associated with the memory cell, while other word lines are at a predetermined voltage, wherein the memory cell is configured to be accessed through the selected word line and a digit line that are orthogonal to each other, the digit line being in a form of a conductive pillar extending vertically, wherein the memory device has a plurality of thin film transistors (TFTs) formed in a pillar selection layer for accessing memory cells of the array, wherein the pillar selection layer is formed under the memory layer, and the peripheral circuit layer is formed under the pillar selection layer, and wherein a TFT of the plurality of TFTs is configured for the conductive pillar;
applying a second voltage to gate regions of a subset of TFTs of the plurality of TFTs, the subset of TFTs being associated with other memory cells that share the selected word line with the memory cell;
applying the second voltage to source regions of the subset of TFTs, while source regions of the other TFTs of the plurality of TFTs are at the predetermined voltage; and
applying a third voltage to a gate region of a TFT of the plurality of TFTs that is associated with the memory cell.