Patent ID: 11864024
Assignee: HUAWEI TECHNOLOGIES CO., LTD.
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An apparatus, comprising:
one or more processors;
a memory coupled to the one or more processors, wherein the non-transitory memory stores a program to be executed by the one or more processors, the program including instructions to:
receive L pieces of first data, wherein L is an integer greater than 1;
determine a reception statuses for the L pieces of first data;
receive second data, wherein the second data is data obtained after N pieces of first data are encoded, the N pieces of first data are included in the L pieces of first data, and N is a positive integer less than or equal to L, wherein the receiving the second data comprises: decoding the second data by using L2 pieces of first data in the L1 pieces of first data, to obtain L3 pieces of first data that are in the L pieces of first data and that are different from the L1 pieces of first data, wherein the L2 pieces of first data are included in the N pieces of first data, L2 is a positive integer less than or equal to L1, L3 is a nonnegative integer less than or equal to L, and a sum of L1 and L3 is less than or equal to L;
generate feedback information based on the reception statuses for the L pieces of first data and the second data, wherein the feedback information indicates one or more reception statuses for M pieces of first data, the M pieces of first data are included in the L pieces of first data, and M is a positive integer less than or equal to L, wherein the feedback information comprises first feedback information or second feedback information, wherein the first feedback information indicates that the L3 pieces of first data are correctly received, L3=M; wherein the second feedback information indicates that the L1+L3 pieces of first data are correctly received, L1+L3=M; and
send the feedback information.