Patent ID: 11968819
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 8:
9. An integrated circuit (IC) structure, comprising:
a logic standard cell including a first active region having a first dopant type and a second active region having a second dopant type that is opposite the first dopant type, the first active region and the second active region oriented lengthwise along a first direction and spaced from each other along a second direction substantially perpendicular to the first direction,
wherein the first active region includes a first plurality of vertically stacked channel layers having a width W1 measured along the second direction, and
wherein the second active region includes a second plurality of vertically stacked channel layers having a width W2 measured along the second direction, the width W1 being different than the width W2; and

a gate structure oriented lengthwise along the second direction, wherein the gate structure engages with the first plurality of vertically stacked channel layers to form a first device having a second conductivity type and with the second plurality of vertically stacked channel layers to form a second device having a first conductivity type that is opposite the first conductivity type.