Patent ID: 11961577
Assignee: NXP USA, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 8:
9. The method of claim 8, wherein the testing the second set of ADCs using pairs of calibration codes corresponding to the reduced M-bit resolution of the DAC comprises:
generating a second DAC input code;
accessing a second address line of the on-chip memory addressed by N−1 upper significant bits of the second DAC input code, wherein the N−1 upper significant bits of the second DAC input code is capable of addressing only a first portion of memory locations of the on-chip memory; and
providing a selected pair of calibration codes corresponding to the received second DAC input code from predetermined byte locations of the second accessed line to calibrate the DAC during testing the second set of ADCs.