Patent ID: 11928284
Assignee: CYPRESS SEMICONDUCTOR CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A device comprising:
one or more processors configured to:
receive measurements obtained from a plurality of first electrodes and a plurality of second electrodes using a designated integration window, wherein the plurality of first electrodes and the plurality of second electrodes are orthogonal to each other;
determine a plurality of variance values based on the plurality of measurements and based on a distance computation associated with adjacent sense locations, the plurality of variances values identifying variances in the plurality of measurements between the adjacent sense locations defined by the plurality of first electrodes and the plurality of second electrodes;
determine if a defect is present based, at least in part, on a comparison of the plurality of variance values with the plurality of threshold values; and
perform one or more corrective operations in response to determining a defect is present.