Patent ID: 11901369
Assignee: AU OPTRONICS CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A pixel array substrate, comprising:
a base, having an active region and a first peripheral region outside of the active region;
a plurality of pixel structures, disposed at the active region of the base;
a plurality of data lines, electrically connected to the plurality of pixel structures and arranged in a first direction;
a plurality of scan line groups, wherein each of the scan line groups comprises a plurality of scan lines, the plurality of scan lines are arranged in a second direction, the first direction and the second direction are staggered, and the plurality of scan lines of the plurality of scan line groups are electrically connected to the plurality of pixel structures;
a plurality of transfer line groups, wherein each of the transfer line groups comprises a plurality of transfer lines, and the transfer lines are arranged in the first direction and are electrically connected to the plurality of scan lines of a corresponding scan line group;
a plurality of connection terminal groups, disposed on the first peripheral region of the base, wherein each of the connection terminal groups comprises a plurality of connection terminals; and
a plurality of bridge line groups, disposed on the base and are structurally separated from each other, wherein each of the bridge line groups is electrically connected to a corresponding transfer line group and a corresponding connection terminal group,
wherein the plurality of connection terminals of each of the connection terminal groups comprise a first connection terminal to an n-th connection terminal sequentially arranged in the first direction, where n is a positive integer greater than or equal to 2, the plurality of transfer lines of a transfer line group corresponding to the each of the connection terminal groups comprise a first transfer line to an n-th transfer line respectively electrically connected to the first connection terminal to the n-th connection terminal, and an arrangement sequence of the first connection terminal to the n-th connection terminal in the first direction is different from an arrangement sequence of the first transfer line to the n-th transfer line in the first direction,
wherein the plurality of pixel structures are arranged as a plurality of pixel rows, the plurality of pixel structures in each of the pixel rows are arranged in the first direction, and in a top view of the pixel array substrate, the plurality of first bridge lines of the each of the bridge line groups are respectively disposed corresponding to the plurality of pixel rows.