Patent ID: 11900539
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. A graphics processing unit (GPU), comprising:
a cache memory to store object data and associated control data for objects to be rendered via tile-based immediate-mode rendering;
sequencer circuitry to:
generate a plurality of batches of objects to be rendered, each of the plurality of batches sized according to a size of a cache memory of the graphics processing unit;
determine tiles intersected by objects in each of the plurality of batches;
maintain lit transaction information for the plurality of batches based on the intersected tiles;
perform a play sequencing of each of the objects based on the lit transaction information, wherein object data and associated control data are stored to the cache memory for use during play sequencing; and

rasterization circuitry to rasterize the objects into pixel data based on the play sequencing, wherein to perform the play sequencing includes to select, based on the lit transaction information, a cache aware tile-walk pattern and walk lit tiles according to the tile-walk pattern, wherein to walk a lit tile includes to process primitive commands for objects in the plurality of batches of objects that are associated with the lit tile.