Patent ID: 11876050
Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A method for manufacturing an interconnect structure, the method comprising:
providing a substrate structure comprising a substrate, a first dielectric layer on the substrate, a metal interconnect line extending through the first dielectric layer, and a first barrier layer between the substrate and the first dielectric layer, the metal interconnect line extending through the first dielectric layer and the first barrier layer;
removing a portion of the first dielectric layer on the metal interconnect line to form a recess exposing a surface of the metal interconnect line;
forming a graphene layer on the exposed surface of the metal interconnect line;
forming a second dielectric layer filling the recess and covering the graphene layer; and
forming an amorphous carbon layer between the first barrier layer and the second dielectric layer.