Patent ID: 11923295
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A method of forming a semiconductor structure, the method comprising:
depositing a first dielectric layer over a first interconnect layer, the first interconnect layer comprising a first conductive line in a logic area;
forming a high resistance layer over the first dielectric layer, the high resistance layer extending over the logic area and a high resistance area;
depositing a second dielectric layer over the high resistance layer;
patterning the second dielectric layer and the high resistance layer using an etching process, the etching process removing a portion of the high resistance layer in the logic area, wherein after the etching process a first portion of the first dielectric layer in the logic area has a first thickness and a second portion of the first dielectric layer in the high resistance area under a remaining portion of the high resistance layer has a second thickness, the first thickness being less than the second thickness, and wherein after the etching process, a remaining portion of the second dielectric layer has a thickness equal to the first thickness of the first dielectric layer;
depositing a low-k dielectric layer over the second dielectric layer and the first dielectric layer, the low-k dielectric layer extending over the logic area and the high resistance area;
forming a first conductive via in the logic area through the low-k dielectric layer and the first dielectric layer, the first conductive via physically contacting the first conductive line;
forming a second conductive via in the high resistance area through the low-k dielectric layer and the second dielectric layer, the second conductive via extending into the remaining portion of the high resistance layer;
forming a third conductive via in the high resistance area through the low-k dielectric layer and the second dielectric layer, the third conductive via extending into the remaining portion of the high resistance layer, wherein forming the first conductive via, forming the second conductive via, and forming the third conductive via are performed simultaneously, and wherein the first conductive via, the second conductive via, and the third conductive via have same contact resistances; and
forming a second conductive line in the low-k dielectric layer, the second conductive line physically contacting the first conductive via and the second conductive via, an interface between the second conductive line and the first conductive via being above a bottommost surface of the second conductive via.