Patent ID: 11962332
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. An apparatus comprising:
a first stage comprising a 7:1 decoder, wherein the 7:1 decoder decodes a first input to produce a first output; and
a second stage configured to;
receive the first output from the first stage,
receive a second input,
convert the first output and the second input from a first code to a second code based on the second input and the first output, and
a first plurality of two input port AND gates, each one of the first plurality of two input port AND gates having a first input port respectively connected to one of seven output nodes of the 7:1 decoder and a second input port connected to an inverse of an input bit.