Patent ID: 11973050
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for forming an integrated chip, the method comprising:
depositing a passivation structure over a conductive wire;
depositing a first conductive layer over the passivation structure;
depositing a dielectric layer over the first conductive layer;
performing a patterning process on the passivation structure, the first conductive layer, and the dielectric layer to form an opening above the conductive wire, wherein the patterning process forms a metal oxide along a top surface of the conductive wire;
performing a cleaning process on the dielectric layer and the conductive wire to remove the metal oxide from along the top surface of the conductive wire;
depositing a second conductive layer over the dielectric layer and the conductive wire such that the second conductive layer lines the opening and contacts the conductive wire; and
etching the second conductive layer, the dielectric layer, and the first conductive layer to form an upper conductive structure over the conductive wire.