Patent ID: 11928441
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 10:
11. A semiconductor memory device comprising:
a memory cell array;
a state machine configured to output a plurality of state signals in response to operation commands of the memory cell array, and that includes a first flip-flop which outputs a first state signal among the plurality of state signals, and a second flip-flop which outputs a second state signal which is output after the output of the first state signal among the plurality of state signals;
a logical sum calculator configured to perform a logical sum calculation based on at least one of the first state signal or the second state signal; and
an accumulation circuit configured to receive an output of the logical sum calculator as a clock signal and output a toggle signal, the output of the accumulation circuit being fed back and provided to the accumulation circuit.