Patent ID: 11871553
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 10:
11. A semiconductor device, comprising:
a substrate including a logic cell region and a connection region;
a dummy transistor on the connection region;
an intermediate connection layer on the dummy transistor;
a first metal layer on the intermediate connection layer;
an etch stop layer between the intermediate connection layer and the first metal layer; and
a penetration contact extended from the first metal layer toward a bottom surface of the substrate penetrating the connection region,
wherein an upper portion of the penetration contact protrudes above the etch stop layer,
the first metal layer includes a first interconnection line, a second interconnection line, and a via below the second interconnection line,
the via penetrates the etch stop layer and connects the second interconnection line to the intermediate connection layer,
a top surface of the penetration contact is in direct contact with a bottom surface of the first interconnection line,
a top surface of the via is in direct contact with a bottom surface of the second interconnection line, and
the lowermost level of the bottom surface of the first interconnection line is lower than the lowermost level of the bottom surface of the second interconnection line.