Patent ID: 11940940
Assignee: GRAPHCORE LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 12:
13. A method implemented in a data processing device, the method comprising:
storing a first local program in a first processor and a second local program in a second processor, the first local program and second local program together providing at least part of a computer program, wherein the first local program comprises a first schedule defining, for different phases of execution of the computer program, which of a plurality of interfaces of the data processing device the first processor is scheduled to connect to;
wherein the second local program comprises a second schedule defining, for the different phases of execution of the computer program, which of a plurality of interfaces of the data processing device the second processor is scheduled to connect to;
receiving via the plurality of interfaces, a plurality of ingress data packets;
transporting ones of the ingress data packets on a plurality of buses of a switching fabric, each one of the interfaces being associated with a respective one of the buses;
in dependence upon the first schedule:
controlling switching circuitry associated with the first processor to, during a first of the phases of execution of the computer program, connect to a first one of the buses so as to enable reception, at the first processor, of a first set of the ingress data packets from a first of the interfaces that is associated with the first one of the buses; and
controlling the switching circuitry to, during a second of the phases of execution of the computer program, connect to a second one of the buses so as to enable reception, at the first processor, of a second set of the ingress data packets from a second of the interfaces that is associated with the second one of the buses,
wherein the different phases of execution are exchange phases, wherein the plurality of processors are configured to alternate between operation in compute phases and the exchange phases, the compute phases and the exchange phases being separated by barrier synchronisations enforced between at least some of the processors.