Patent ID: 11928472
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. A system comprising:
memory to store one or more instructions;
a processor, having one or more cores, to execute the one or more instructions;
predecode circuitry to predecode an entry in a cache to generate a predecoded branch operation, the entry being associated with a cold branch operation, wherein the cold branch operation corresponds to an operation that is detected for a first time after storage in an instruction cache and wherein the cold branch operation remains undecoded since it is stored at a location in a cache line prior to a subsequent location of a branch operation in the cache line; and
a Branch Prefetch Buffer (BPB) to store the predecoded branch operation in response to a cache line fill operation of the cold branch operation in an instruction cache.