Patent ID: 11922993
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 8:
9. A device comprising:
an array of memory cells comprising a first word line coupled to at least a subset of the array of memory cells; and
control logic coupled to the first word line, the control logic to perform operations comprising:
accessing a set of first read commands to read first data from a first lower page of a first subset of an array of memory cells, the array of memory cells being configured as one of multi-level-cell (MLC) memory, triple-level cell (TLC) memory, quad-level cell (QLC) memory, or penta-level cell (PLC) memory, wherein the first subset of the array is coupled to a word line of the array;
causing a voltage applied to the word line to move to a target value;
causing a page buffer to sense a first portion of the first data from a first bit line coupled to the first lower page and to sense a second portion of the first data from a second bit line coupled to the first lower page of the first subset of the array; and
causing the voltage applied to the word line to again move to the target value.