Patent ID: 11930635
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 7:
8. The method of manufacturing the semiconductor structure according to claim 7, wherein using the insulation layer as the mask to etch the metal conductive layer and the non-metal conductive layer comprises:
with a metal barrier material layer serving as an etching stop layer, using the insulation layer as a mask to etch metal material to transfer the second graphical target pattern to the metal conductive layer;
with the non-metal conductive layer serving as an etching stop layer, using the insulation layer as the mask to etch the metal barrier material layer to transfer the second graphical target pattern to the metal barrier material layer; and
using the insulation layer as the mask to etch the non-metal conductive layer to transfer the second graphical target pattern to the non-metal conductive layer.