Patent ID: 11894037
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 14:
15. A method, comprising:
prior to accessing memory cells of an array, initializing the array, where each of the memory cells comprise a programmable resistive element connected in series with a threshold switching selector, the array having a cross-point architecture in which each of the memory cells is connected between a corresponding word line and a corresponding bit line, wherein initializing the array comprises:
applying an initialization voltage with a first polarity between the corresponding one or more word lines and the corresponding one or more bit lines of one or more memory cells selected for initialization;
concurrently with applying the initialization voltage with a first polarity, biasing word lines of the array not corresponding the memory cells selected for initialization to a first voltage level intermediate to the initialization voltage and a low voltage level; and
concurrently with applying the initialization voltage with a first polarity, biasing bit lines of the array not corresponding the memory cells selected for initialization to a second voltage level intermediate to the initialization voltage and the low voltage level, wherein first voltage level and the second voltage level are different.