Patent ID: 11862605
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor structure comprising:
a die stack bonded to a base structure, the die stack comprising a first integrated circuit die, the first integrated circuit die being a farthest integrated circuit die of the die stack from the base structure, and comprising a first bonding surface having first electrical contacts embedded with a first bonding dielectric layer, respective top surfaces of the first electrical contacts and the top surface of the first bonding dielectric layer being coplanar;
a die structure bonded to the die stack, the die structure comprising a second integrated circuit die comprising a second bonding surface that includes second electrical contacts embedded within a second bonding dielectric layer, respective top surfaces of the second electrical contacts and the top surface of the second bonding dielectric layer being coplanar, the first bonding dielectric layer being direct bonded to the second bonding dielectric layer, and the respective first electrical contacts being direct bonded to the second electrical contacts;
a heat dissipation structure bonded to the die structure adjacent the die stack, a sidewall of the heat dissipation structure being substantially coplanar with a sidewall of the die structure; and
a first encapsulant extending along sidewalls of the die stack.