Patent ID: 11908515
Assignee: HEFEI RELIANCE MEMORY LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 18:
19. An apparatus comprising:
multiple memory cells each comprising two transistors and a resistive memory element, wherein:
a first transistor of a first memory cell is electrically coupled to a first transistor of a second memory cell and a source line,
a first transistor of a third memory cell is electrically coupled to a first transistor of a fourth memory cell and the source line,
the resistive memory element of the first memory cell is coupled to the resistive memory element of the second memory cell and a first bit line,
the resistive memory element of the third memory cell is coupled to the resistive memory element of the fourth memory cell and a second bit line,
a first word line is electrically coupled to a second transistor of the first memory cell and a second transistor of the third memory cell,
a second word line is electrically coupled to a second transistor of the second memory cell and a second transistor of the fourth memory cell,
a third word line is electrically coupled to the first transistor of the first memory cell and the first transistor of the third memory cell, and
a fourth word line is electrically coupled to the first transistor of the second memory cell and the first transistor of the fourth memory cell; and

a row driver circuit current mirror configured to apply a voltage to the second word line and the fourth word line during a form or set operation of the second and fourth memory cells.