Patent ID: 11954585
Assignee: ZJU-HANGZHOU GLOBAL SCIENTIFIC AND TECHNOLOGICAL INNOVATION CENTER
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. The multi-mode array structure for in-memory computing according to claim 7, wherein when the conductance of the first memristor in the memory cell is set to be greater than the conductance of the second memristor, and the first memristor is connected to the positive input end of the differential amplifier via the first transistor while the second memristor is connected to the negative input end of the differential amplifier via the second transistor, the analogue signal or the pulse signal is input to the first memristor and the second memristor through the corresponding function line, so as to obtain a weight value corresponding to the memory cell as the positive weight value; when the conductance of the first memristor in the memory cell is set to be less than the conductance of the second memristor, and the first memristor is connected to the positive input end of the differential amplifier via the first transistor while the second memristor is connected to the negative input end of the differential amplifier via the second transistor, the analogue signal or the pulse signal is input to the first memristor and the second memristor through the corresponding function line, so as to obtain a weight value corresponding to the memory cell as the negative weight value;
when the conductance of the first memristor in the memory cell is set to be greater than the conductance of the second memristor, and the first memristor is connected to the negative input end of the differential amplifier via the first transistor while the second memristor is connected to the positive input end of the differential amplifier via the second transistor, the analogue signal or the pulse signal is input to the first memristor and the second memristor through the corresponding function line, so as to obtain a weight value corresponding to the memory cell as the negative weight value; when the conductance of the first memristor in the memory cell is set to be less than the conductance of the second memristor, and the first memristor is connected to the negative input end of the differential amplifier via the first transistor while the second memristor is connected to the positive input end of the differential amplifier via the second transistor, the analogue signal or the pulse signal is input to the first memristor and the second memristor through the corresponding function line, so as to obtain a weight value corresponding to the memory cell as the positive weight value.