Patent ID: 11899611
Assignee: GE AVIATION SYSTEMS LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A data synchronizer for an avionics system, the data synchronizer operable to manage communications involving a lockstep processing system comprising at least a first processor and a second processor, the data synchronizer configured to:
receive a first signal at a first processing lane of the data synchronizer;
transmit the first signal to a second processing lane of the data synchronizer;
transmit the first signal from the first processing lane to the lockstep processing system; and
transmit the first signal from the second processing lane to the lockstep processing system,
wherein the first processing lane and the second processing lane are communicatively coupled to one another via a cross-channel interface,
the data synchronizer further configured to:
receive a second signal at the first processing lane, the second signal from the lockstep processing system;
receive a third signal at the second processing lane, the third signal from the lockstep processing system;
transmit the second signal to a compare logic of the second processing lane; and
transmit the third signal to a compare logic of the first processing lane,
wherein the lockstep processing system generates both the second signal and the third signal in response to receiving the first signal, and
wherein the first processing lane and the second processing lane include a compare logic, and wherein the compare logic of both the first processing lane and the second processing lane comprises an exclusive OR gate.