Patent ID: 11915757
Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 0:
1. A memory device through use of a semiconductor device, including a plurality of pages arrayed in a column direction, each of the pages being composed of a plurality of memory cells arrayed on a substrate in a row direction, wherein
each of the memory cells included in each of the pages has,
a semiconductor base standing in a vertical direction or extending in a horizontal direction on the substrate with respect to the substrate,
a first impurity layer and a second impurity layer located on opposite ends of the semiconductor base,

a first gate insulating layer that surrounds part or whole of a side surface of the semiconductor base between the first impurity layer and the second impurity layer, and is in contact with or proximate to the first impurity layer,
a second gate insulating layer that surrounds the side surface of the semiconductor base, connects to the first gate insulating layer, and is in contact with or proximate to the second impurity layer,
a first gate conductor layer that covers part or whole of the first gate insulating layer,
a second gate conductor layer that covers the second gate insulating layer, and
a channel semiconductor layer in which the semiconductor base is covered by the first gate insulating layer and the second gate insulating layer,

the memory device controls voltages to be applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer to perform a page write operation and a page erase operation,
the first impurity layer of the each of the memory cells is connected to a source line, the second impurity layer is connected to a bit line, one of the first gate conductor layer and the second gate conductor layer is connected to one of word lines, and the other is connected to a first driving control line, and
the first driving control line is provided in common for adjacent ones of the pages, and when in the page erase operation, the memory device applies pulsed voltages to one of the word lines which performs the page erase operation and the first driving control line, and applies a fixed voltage to another one of the word lines which is not selected to perform the page erase operation.