Patent ID: 11948515
Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 5:
6. A display device comprising a first layer and a second layer that are stacked,
wherein the first layer comprises a potential supply circuit, a data driver circuit, and an addition circuit,
wherein the data driver circuit comprises a pass transistor logic circuit,
wherein the addition circuit comprises a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a first capacitor, a second capacitor, a comparator circuit, a control circuit, and a retention circuit,
wherein the second layer comprises a display portion in which pixels are arranged in a matrix,
wherein the display portion comprises a region overlapping with the data driver circuit and the addition circuit,
wherein an output terminal of the pass transistor logic circuit is directly connected to one terminal of the first switch,
wherein the one terminal of the first switch is electrically connected to one terminal of the second switch,
wherein the other terminal of the second switch is electrically connected to one terminal of the third switch,
wherein the other terminal of the first switch is directly connected to the pixel,
wherein the other terminal of the first switch is electrically connected to one terminal of the fourth switch, one terminal of the fifth switch, and one terminal of the sixth switch,
wherein the other terminal of the fifth switch is electrically connected to one terminal of the first capacitor,
wherein the other terminal of the sixth switch is electrically connected to one terminal of the second capacitor,
wherein the other terminal of the first capacitor and the other terminal of the second capacitor are electrically connected to the one terminal of the third switch,
wherein the other terminal of the fourth switch is electrically connected to one of a non-inverting input terminal and an inverting input terminal of the comparator circuit,
wherein the potential supply circuit is configured to supply a plurality of kinds of potentials to the pass transistor logic circuit,
wherein the pass transistor logic circuit is configured to output any one of the plurality of kinds of potentials as analog data on the basis of digital data input to the pass transistor logic circuit,
wherein the addition circuit is configured to generate and retain third analog data by adding second analog data output in response to input of second digital data to the pass transistor logic circuit, to first analog data output in response to input of first digital data to the pass transistor logic circuit,
wherein the control circuit is configured to generate a digital signal for controlling on and off of the fifth switch and on and off of the sixth switch,
wherein the control circuit is configured to update or determine a digital value of the digital signal on the basis of a signal output from the comparator circuit, in the case where the addition circuit retains the third analog data, and
wherein the retention circuit is configured to retain a determined digital value of the digital signal.