Patent ID: 11942161
Assignee: NUVOTON TECHNOLOGY CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G  H

Claim 9:
10. The erase method as defined in claim 8, wherein the memory device further comprises a security register configured to store a first security control signal and a second security control signal, wherein the first sub-memory and the second sub-memory respectively operate in a locked state according to the first security control signal and the second security control signal, wherein when the memory device completes an initialization procedure, the first security control signal and the second security control signal are written from the main memory to the security register, wherein when the first sub-memory and/or the second sub-memory is/are erased, the first sub-memory and/or the second sub-memory operate(s) in an unlocked state according to the first security control signal and/or the second security control signal respectively.