Patent ID: 11907547
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G  H

Claim 22:
23. A memory device, comprising:
an array of memory cells; and
a controller for access of the array of memory cells, wherein the controller is configured to cause the memory device to:
determine whether the memory device is waiting to initiate a next phase of an access operation on the array of memory cells;
in response to determining that the memory device is waiting to initiate the next phase of the access operation:
determine whether the memory device has a particular priority token of a plurality of priority tokens;
in response to determining that the memory device has the particular priority token:
determine whether there is sufficient available current budget to initiate the next phase of the access operation in a selected operating mode, wherein the available current budget is equal to a total current budget available to a plurality of memory devices comprising the memory device;
in response to determining that there is sufficient available current budget to initiate the next phase of the access operation in the selected operating mode, change its priority token to a lesser priority token of the plurality of priority tokens, and broadcast an expected peak current magnitude for the selected operating mode and the lesser priority token to remaining memory devices of the plurality of memory devices; and
in response to determining that there is insufficient available current budget to initiate the next phase of the access operation in a normal operating mode, broadcast an expected peak current magnitude for the normal operating mode and the particular priority token to the remaining memory devices of the plurality of memory devices.