Patent ID: 11967388
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus comprising:
a memory structure comprising non-volatile memory cells and word lines associated with the memory cells; and
one or more control circuits in communication with the memory structure, wherein the one or more control circuits are configured to:
erase a group of the memory cells;
for one or more selected word lines, generate an enhanced e-field between a presently selected word line connected to memory cells presently being programmed and an adjacent word line connected to already programmed memory cells adjacent to the presently selected word line to create stress in the group of memory cells, wherein the enhanced e-field is greater than an e-field generated in a normal program operation used to program user data; and
determine whether the group of memory cells passes a test criterion after the stress.