Patent ID: 11900988
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An electronic device comprising:
a clock divider circuit configured to:
generate a first internal clock including pulses which are generated in synchronization with odd pulses of a clock, and
generate a second internal clock including pulses which are generated in synchronization with even pulses of the clock; and

a command decoder configured to generate an odd precharge command and an even precharge command based on a counting signal which is toggled by a chip selection signal and a command and address (command/address) signal for performing a precharge operation in synchronization with the first internal clock or toggled by the chip selection signal and the command/address signal for performing the precharge operation in synchronization with the second internal clock,
wherein the command decoder is configured to:
generate a pulse of the odd precharge command as a pulse corresponding to two or more periods of the clock, and
generate a pulse of the even precharge command as a pulse corresponding to two or more periods of the clock.