Patent ID: 11901296
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A die interconnect substrate, comprising:
a bridge die having a top side above a bottom side, and a first sidewall and a second sidewall between the top side and the bottom side, the first sidewall laterally opposite the second sidewall, the bridge die having a bridge die pad;
a first conductive structure laterally spaced apart from the first sidewall of the bridge die;
an insulating filler structure laterally between the substrate interconnect and the bridge die, the insulating filler structure in contact with the first sidewall of the bridge die;
an insulating layer on and in direct contact with the substrate interconnect, on the insulating filler structure, and on the bridge die pad;
a first metallization layer comprising a second conductive structure in a first opening in the insulating layer, the second conductive structure on the first conductive structure, and the first metallization layer comprising a via portion in a second opening in the insulating layer, the via portion on the bridge die pad;
a second metallization layer above the first metallization layer, the second metallization layer comprising a first conductive wiring on the second conductive structure and on the insulating layer, and the second metallization layer comprising a second conductive wiring on the via portion and on the insulating layer; and
a third metallization layer above the second metallization layer, the third metallization layer comprising a first contact interface structure on the first conductive wiring, and the third metallization layer comprising a second contact interface structure on the second conductive wiring.