Patent ID: 11928356
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. An apparatus comprising:
a memory device comprising a plurality of memory components arranged to form a stackable cross-gridded array of interleaved non-volatile memory cells; and
a processing device coupled to the plurality of memory components, the processing device to perform operations comprising:
selecting a source block in a first plane of a first die of a particular memory component among the plurality of memory components for a memory management operation;
selecting a destination block in a second plane of the particular memory component;
determining the destination block is in an incomplete superblock;
responsive to determining that the destination block is the incomplete superblock, selecting a metadata block in a third plane of the particular memory component that is a threshold number of dies away from the second plane;
storing metadata indicative of an address of the source block in the metadata block; and
performing the memory management operation to transfer data from the source block to the destination block.