Patent ID: 11875861
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A memory, comprising:
a data line;
an array of memory cells comprising a string of series-connected memory cells selectively connected to the data line;
a common source selectively connected to the string of series-connected memory cells;
a sensing device selectively connected to the data line; and
a controller for access of the array of memory cells, wherein the controller is configured to cause the memory to:
precharge the data line;
selectively connect the data line to the common source through a selected memory cell of the string of series-connected memory cells while applying a verify voltage level to a control gate of the selected memory cell, and while the common source is configured to receive a first voltage level;
connect the data line to a voltage node through a p-type field-effect transistor (pFET) while a control gate of the pFET receives a second voltage level configured to place the pFET in a cut-off state in response to the data line having a third voltage level lower than the first voltage level, wherein the voltage node is configured to receive a fourth voltage level lower than the third voltage level;
determine whether the selected memory cell has an intended threshold voltage in response to a voltage level developed on the data line while connected to the voltage node and selectively connected to the common source.