Patent ID: 11860786
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. The cache system of claim 15, wherein when the configurable data bit is in the first state, the logic circuit is configured to:
provide commands to the second command bus for accessing the memory system via the first cache, when an execution type identified by the execution-type signal line is the first type; and
provide commands to the second command bus for accessing the memory system via the second cache, when the execution type is the second type;
wherein when the configurable data bit is in the second state, the logic circuit is configured to:
provide commands to the second command bus for accessing the memory system via the second cache, when the execution type is the first type; and
provide commands to the second command bus for accessing the memory system via the first cache, when the execution type is the second type.