Patent ID: 11880597
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A read operation method used in a semiconductor memory, comprising:
determining an initial state of a global bus according to an enable signal and current read data;
determining, according to number of bits of a data change between previous read data and the current read data, whether to invert the current read data to output global bus data for transmission through a global bus and inversion flag data for transmission through an inversion flag signal line;
determining whether to invert the global bus data according to the inversion flag data to output cache data; and
performing parallel-to-serial conversion on the cache data to generate output data of a Data Queue (DQ) port;
wherein the outputting inverted data of the current read data as the global bus data and setting the inversion flag data to High if the number of bits of high data in change flag data is greater than a preset value, and outputting original current read data as the global bus data and setting the inversion flag data to Low if the number of bits of the high data in the change flag data is less than or equal to the preset value comprise:
the change flag data and the global bus data are both divided into M groups, the inversion flag data having M bits, the M-bit inversion flag data being corresponding to the M groups of change flag data one to one, and the M-bit inversion flag data being corresponding to the M groups of global bus data one to one, wherein the M is an integer greater than 1.