Patent ID: 11923372
Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 11:
12. A semiconductor device comprising:
a first layer;
a first insulating layer over the first layer;
a conductive layer over the first insulating layer;
a second insulating layer over the conductive layer;
a second layer over the second insulating layer;
a first opening and a second opening each penetrating the first insulating layer, the conductive layer and the second insulating layer;
a third insulating layer in contact with a sidewall of the first opening;
a fourth insulating layer in contact with a sidewall of the second opening;
a transistor comprising:
an oxide semiconductor layer embedded in the first opening, the oxide semiconductor layer comprising a first region, a second region and a third region;
a first electrode layer configured to function as one of a source electrode and a drain electrode in contact with the first region of the oxide semiconductor; and
a second electrode layer configured to function as the other of the source electrode and the drain electrode in contact with the second region of the oxide semiconductor; and

a capacitor comprising:
a dielectric layer embedded in the second opening;
the first electrode layer configured to function as a first electrode of the capacitor; and
a third electrode layer in the second layer, the third electrode layer configured to function as a second electrode of the capacitor,

wherein the first region of the oxide semiconductor layer is located below than the third region of the oxide semiconductor layer,
wherein the second region of the oxide semiconductor layer is located above than the third region of the oxide semiconductor layer, and
wherein a channel direction is perpendicular to a top surface of a substrate.