Patent ID: 11869609
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. A method for testing a memory, comprising:
writing first data into each of memory cells of a memory array having a plurality of columns;
enabling a data mask mode, and latching the first data into predetermined memory cells;
writing second data only into other memory cells other than the predetermined memory cells;
enabling a leakage mode, and writing the first data into a memory cell corresponding to a column under test of the plurality of columns;
after preset leakage time, disabling the leakage mode, and reading data from the memory cell corresponding to the column under test for testing;
reading data from the memory cells corresponding to columns of the plurality of columns; and
determining whether at least two columns of the plurality of columns include first data
wherein when determining that there are at least two columns simultaneously turned on
in the memory array, a row decoder of the memory is determined abnormal.