Patent ID: 11894437
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A structure, comprising:
a substrate with a gate structure and a source/drain (S/D) structure disposed thereon;
a bottom dielectric surrounding a lower portion of the gate structure and the S/D structure;
an etch stop layer on the bottom dielectric;
a first dielectric on the gate and S/D structures;
a second dielectric on the first dielectric; and
a shared conductive structure in the first dielectric contacting the gate structure and the S/D structure, wherein the shared conductive structure comprises:
a ruthenium liner on a bottom surface and sidewall surfaces of the shared conductive structure and contacting the first dielectric and etch stop layer;
a first thickness of the ruthenium liner on the bottom surface contacting the S/D structure and a second thickness of the ruthenium liner on the bottom surface contacting the first dielectric between the S/D structure and the gate structure, wherein the first thickness is greater than the second thickness; and
a cobalt metal in contact with the ruthenium liner.