Patent ID: 11909384
Assignee: GAN SYSTEMS INC.
Field: Electrical machinery, apparatus, energy (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. The power semiconductor switching device of claim 12 comprising:
a high-side switch and a low-side switch connected in series in a half-bridge configuration, between a high voltage DC bus (rail) and a low voltage DC bus (rail), the high side switch being connected to the low side switch at a switching node, wherein:
the high-side switch is a normally-off switch wherein a first normally-on GaN transistor switch (Q1) is connected in series with a normally-off Si MOSFET switch (M1); and
the low side switch is a normally-on switch, comprising a second normally-on GaN transistor switch (Q2); wherein:
Q1 has a source, a drain and a gate, wherein the drain of Q1 is connected to the high voltage DC bus and the source of Q1 is connected to a drain of M1, and the gate of Q1 is connected to a first gate drive terminal for directly driving the gate of Q1; the source of M1 is connected to the switching node, a gate of M1 is connected to an enable (control) terminal for directly driving the gate of the M1; a high-side ground terminal is connected to the source of M1; and a voltage sense terminal is connected a common point between the source of Q1 and the drain of M1; and
Q2 has a source, a drain and a gate, the drain of Q2 is connected to the switching node and the source of Q2 is connected to the low voltage DC bus, and the gate of Q2 is connected to a second gate drive terminal for directly driving the gate of Q2; and a low-side ground terminal is connected to the source of Q2;
a half-bridge driver circuit comprising:
a high-side driver for directly driving a gate of Q1;
a low-side driver for directly driving a gate of Q2;
wherein the high-side driver and the low-side driver are driven by PWM input signals INH and INL respectively; and

a control circuit for driving M1, wherein the control circuit comprises a gate driver for providing an enable (control) signal for directly driving the gate of M1 in response to a gate input signal PGOOD,
a voltage sense input Vsen from a voltage sense terminal connected to a node between the source of Q1 and the drain of M1,
a UVLO signal input, and circuitry for determining a power status and operational mode for M1,
circuitry for comparing the voltage sense input Vsen to a reference OCP limit voltage VOCP_limit and triggering OCP if Vsen exceeds the OCP limit voltage;
wherein said enable signal provides that
M1 is OFF during start-up until UVLO is off;
M1 is ON for normal operation;
M1 is turned-off during a fault condition if UVLO is turned-on;
and
if OCP is triggered, M1 is ON and Q1 and Q2 are turned-off.