Patent ID: 11908511
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 15:
16. A semiconductor memory device comprising:
a memory string that includes a plurality of memory transistors connected in series;
a plurality of first wirings connected to gate electrodes of the plurality of memory transistors;
a plurality of second wirings electrically connected to the plurality of first wirings; and
a first bonding pad electrode to which a first voltage is applied, wherein
a first read operation is executed in response to an input of a first command set,
a second read operation is executed in response to an input of a second command set,
when an execution period of the second read operation in a case where the second read operation is executed after an execution of the first read operation is assumed to be a first period, and an average value of a current flowing to the first bonding pad electrode during the execution of the second read operation is assumed to be a first current,
when an execution period of latter one of the second read operation in a case where the second read operation is executed after an execution of the second read operation is assumed to be a second period, and an average value of a current flowing to the first bonding pad electrode during the execution of the latter one of the second read operation is assumed to be a second current,
the first period is smaller than the second period, or the first current is smaller than the second current,
a second voltage is applied to the plurality of second wirings at a first timing at which the first read operation ends,
a third voltage is applied to the plurality of second wirings at a second timing at which the second read operation ends, and
the second voltage is larger than the third voltage.