Patent ID: 11950523
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 12:
13. A method for manufacturing a memory device, comprising:
sequentially forming a first bottom electrode layer, a second bottom electrode layer, a resistance variable material layer and a top electrode layer over a semiconductor substrate;
disposing a hard mask on the top electrode layer;
performing a first anisotropic etching process by using the hard mask as a mask, to pattern the top electrode layer and the resistance variable material layer, wherein the top electrode layer is patterned to form a top electrode, and the resistance variable material layer is patterned to form a resistance variable layer;
performing an isotropic etching process to pattern the second bottom electrode layer, wherein the second bottom electrode layer is patterned to form an upper bottom electrode covered by the resistance variable layer and laterally recessing with respect to the resistance variable layer; and
performing a second anisotropic etching process by using the hard mask, the top electrode, the resistance variable layer and the upper bottom electrode as a mask, to pattern the first bottom electrode layer, wherein the first bottom electrode layer is patterned to form a lower bottom electrode.