Patent ID: 11875840
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 9:
10. An operation method of a semiconductor device comprising:
reading data from a first memory cell of a first sub-array onto a first bit line connected to the first memory cell;
connecting the first bit line to a second bit line of a second sub-array;
performing an equalization operation using a second sense amplifier to set a value of a third bit line according to a value of the data on the second bit line;
performing a precharge operation using the first sense amplifier of at least the second bit line while the second sense amplifier is turned off;
performing a write operation according to the value of the third bit line using the second sense amplifier while the first sense amplifier is turned off;
performing a read operation on a plurality of memory cells of the first sub-array;
connecting a plurality of bit lines connected to the plurality of memory cells in common; and
amplifying a voltage of the plurality of bit lines by activating a plurality of sense amplifiers connected to the plurality of bit lines.