Patent ID: 11972817
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. The method as set forth in claim 19, further including the steps of:
determining whether the one of the plurality of verify loops associated with the earlier one of the plurality of data states has been triggered based on an even earlier bitscan count of the memory cells associated with an even earlier one of the plurality of data states having the threshold voltage exceeding an even earlier verify level for the even earlier one of the plurality of data states exceeding a predetermined even earlier bitscan threshold, the even earlier one of the plurality of data states corresponding to the threshold voltage of the memory cells being lower than for the earlier one of the plurality of data states; and
determining whether the another of the plurality of verify loops associated with the selected one of the plurality of data states using the verify low reference voltage and the verify high reference voltage for the selected one of the plurality of data states has been triggered based on an earlier bitscan count of the memory cells associated with the earlier one of the plurality of data states having the threshold voltage exceeding the verify high reference voltage for the earlier one of the plurality of data states exceeding a predetermined earlier bitscan threshold.