Patent ID: 11948914
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A package structure, comprising:
a package substrate;
a semiconductor chip disposed over the package substrate, wherein the semiconductor chip has a lower surface facing the package substrate and is electrically connected to the package substrate through conductive structures; and
an integrated device located below and bonded to the lower surface of the semiconductor chip, wherein the integrated device is laterally surrounded by the conductive structures, and the integrated device and the conductive structures are located within boundaries of the semiconductor chip when viewed in a direction perpendicular to the lower surface of the semiconductor chip,
wherein the package substrate has an upper surface facing the lower surface of the semiconductor chip and a cavity formed on the upper surface, wherein the cavity is configured to accommodate the integrated device.