Patent ID: 11900990
Assignee: R&D 3 LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device comprising:
a memory array comprising:
a plurality of memory cells, each memory cell having an impedance that varies in accordance with a respective data value stored therein, and wherein each respective data value corresponds to a plurality of bits; and
one or more tracking memory cells, each tracking memory cell having an impedance based on a respective tracking data value stored therein; and

a read circuit coupled to the memory array, the read circuit configured to:
receive output from a selected memory cell of the plurality of memory cells and from a selected tracking memory cell of the one or more tracking memory cells;
determine an impedance of the selected memory cell with reference to the impedance of the selected tracking memory cell; and
determine, using a single memory read access and based on the impedance of the selected memory cell, the respective data value stored in the selected memory cell, wherein the respective data value can be any one of all the possible data values corresponding to the plurality of bits.