Patent ID: 11881260
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A neuromorphic computing device comprising:
a first memory cell array including a plurality of resistive memory cells, configured to store a plurality of data, configured to generate a plurality of read currents based on a plurality of input signals and the plurality of data, and configured to output the plurality of read currents through a plurality of bitlines or a plurality of source lines;
a second memory cell array including a plurality of reference resistive memory cells and at least one offset resistor, and configured to output at least one reference current through at least one reference bitline or at least one reference source line; and
an analog-to-digital converting circuit configured to convert the plurality of read currents into a plurality of digital signals based on the at least one reference current, and
wherein the at least one offset resistor is connected between the at least one reference bitline and the at least one reference source line.