Patent ID: 11887971
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 18:
19. A semiconductor package comprising:
a lower connection structure including a lower insulating layer, a lower via penetrating the lower insulating layer, and a lower pad disposed on a lower surface of the lower insulating layer and connected to the lower via;
an external connection terminal on a lower surface of the lower pad;
a semiconductor chip including a body on an upper surface of the lower connection structure;
a sealing layer covering an upper surface of the lower connection structure and an upper surface of the semiconductor chip;
an upper connection structure including an upper insulating layer on the sealing layer, an upper conductive pattern layer on the upper insulating layer, and an upper via penetrating an upper part of the upper insulating layer and connecting the upper conductive pattern layer, and
an intermediate connection structure penetrating the sealing layer and a lower part of the upper insulating layer, the intermediate connection structure connecting between the upper conductive pattern layer and the lower via,
wherein an upper surface of the intermediate connection structure is protrudes upward from the upper surface of the sealing layer,
wherein the upper insulating layer contacts a portion of an upper surface of the intermediate connection structure and a side surface of an upper part of the intermediate connection structure,
wherein a lower surface of the intermediate connection structure and an upper surface of the lower insulating layer are located on the same vertical level,
the lower surface of the intermediate connection structure is located at a lower vertical level than a lower surface of the body of the semiconductor chip, and
an upper surface of the intermediate connection structure is located at a higher vertical level than an upper surface of the body of the semiconductor chip.