Patent ID: 11879939
Assignee: NXP B.V.
Field: Measurement (Instruments)
Classification: CPC G  H | IPC G  H

Claim 7:
8. The IC of claim 3, wherein the testing system further comprises:
a first logic circuit configured to generate a counter enable signal based on the first pipeline enable signal and the first division enable signal, wherein during the capture phase, the counter enable signal is asserted based on the assertion of at least one of a group consisting of the first pipeline enable signal and the first division enable signal, and the counter enable signal is de-asserted based on the de-assertion of the first pipeline enable signal and the first division enable signal; and
a third clock gate that is coupled to the first logic circuit and the counter, and configured to generate the third clock signal based on the first clock signal and the counter enable signal, wherein the third clock signal is de-asserted based on the de-assertion of the counter enable signal, and the third clock signal is same as the first clock signal based on the assertion of the counter enable signal.