Patent ID: 11935587
Assignee: CEREMORPHIC, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A memory array comprising:
a top memory cell array accessed by activating a wordline which causes the top memory cell array to output data onto one or more top bitlines;
a bottom memory cell array accessed by activating a wordline which causes the bottom memory cell array to output data onto one or more bottom bitlines;
a wordline controller configured to examine output data from the top bitlines and/or the bottom bitlines, the wordline controller modifying a wordline signal pulse width until at least one of the following four error states occurs:
a high error rate where an MSB of a memory word has an error rate in the range of 2% to 15%, or approximately 10%;
a moderate error rate where an MSB of a memory word has an error rate in the range of 0.5% to 2%, or approximately 1%;
a low error rate where an MSB of a memory word has an error rate in the range of 0.005% to 0.5%, or approximately 0.1%; and
a nearly error-free error rate where an MSB of a memory word has an error rate less than 0.00034%.