Patent ID: 11947975
Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. A non-transitory computer-readable medium storing a computer program configured to cause an offload server to offload specific processing of an application to a Graphics Processing Unit (GPU) or a Programmable Logic Device (PLD), the offload server comprising: one or more hardware processors; a storage section, implemented using one or more of the one or more hardware processors, configured to store, in a code pattern database, libraries usable for offloading the specific processing to the GPU and Intellectual Property UP) cores usable for offloading the specific processing to the PLD; an application code analysis section, implemented using one or more of the one or more hardware processors, configured to analyze a source code of the application to detect external library calls included in the source code; a replacement function detection section, implemented using one or more of the one or more hardware processors, configured to, using the detected external library calls as keys, search the code pattern database to retrieve, of the libraries and IP cores, those corresponding to the detected external library calls as replacement-destination libraries/IP cores, thereby to identify the external library calls corresponding to the retrieved replacement-destination libraries/IP cores as offloadable replacement sources; a replacement processing section, implemented using one or more of the one or more hardware processors, configured to replace processing descriptions of the offloadable replacement sources with processing descriptions of the replacement-destination libraries/IP cores and to generate interfaces that interface a central processing unit (CPU) to the replacement-destination libraries/IP cores;
an offload pattern generation section, implemented using one or more of the one or more hardware processors, configured to generate one or more offload patterns, each of which designates, for each of the offloadable replacement sources, whether to offload the processing to be performed by the offloadable replacement source;
an execution file generation section, implemented using one or more of the one or more hardware processors, configured to, for each of the one or more offload patterns, compile the application according to the offload pattern to generate an execution file; and
a performance measurement section, implemented using one or more of the one or more hardware processors, configured to, for each generated execution file, deploy the generated execution file to an accelerator verification device and perform processing for a measurement of a performance obtained when offloading to the GPU and/or the PLD is performed,
wherein the execution file generation section is configured to select an offload pattern with a highest processing performance from the one or more offload patterns on the basis of a result of the performance measurement by the processing for the measurement of the performance, and compile the application according to the offload pattern with the highest processing performance to generate a final execution file.