Patent ID: 11955457
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor package, comprising:
a first substrate having a first surface;
a second substrate having a second surface generally orthogonal to the first surface; and
at least one die over the first surface, wherein each of the at least one die includes a die surface generally orthogonal to the second surface, wherein contact points on two or more of the first surface, the second surface, and the at least one die are electrically coupled to each other;
a third substrate having a third surface;
a fourth substrate having a fourth surface;
a fifth substrate having a fifth surface, wherein the third, fourth and fifth surfaces are each generally orthogonal to the first surface;
a plurality of first wirebonds extending from the second surface of the second substrate to at least one of (a) the first surface of the first substrate, or (b) an outermost surface of the at least one die;
a plurality of second wirebonds extending from the third surface to at least one of (a) the first surface of the first substrate, or (b) the outermost surface of the at least one die;
a plurality of third wirebonds extending from the fourth surface to at least one of (a) the first surface of the first substrate, or (b) the outermost surface of the at least one die; and
a plurality of fourth wirebonds extending from the fifth surface to at least one of (a) the first surface of the first substrate, or (b) the outermost surface of the at least one die.