Patent ID: 11960734
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 14:
15. A system, comprising:
programmable logic comprising a plurality of configuration memory and a register; and
control circuitry disposed between portions of the programmable logic and on a same board, wherein the control circuitry is configured to:
receive a data packet from a data path; and
generate, using a finite state machine, a plurality of control signals to read stored data from the register of a microsector at least in part by a shifting the read stored data from the register to a buffer using a quasi-delay insensitive (QDI) shift register in response to the data packet, wherein the QDI shift register is configured to transmit the read stored data based at least in part on handshaking operations.