Patent ID: 11908542
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus comprising:
a first logic configured to determine whether burst mode is enabled for writing data to a memory, wherein:
the memory includes N number of slices; and
each slice includes M number of bit cells coupled to a word line, and each of the M bit cells is also coupled to a bit line (BL), an inverse of bit line (BL #), write column selectors, and read column selectors;

a second logic configured to generate one pre-charge pulse and M word line pulses for the M bit cells of the N number of slices to perform M number of write operations after it is determined that the burst mode is enabled, wherein the one pre-charge pulse is applied to the M bit cells prior to applying the M word line pulses for the M bit cells;
a third logic configured to determine whether an equalization mode is enabled prior to writing data to the memory; and
a fourth logic configured to, for each of the M bit cells, equalize the bit line and the inverse bit line of the bit cell prior to writing data into the bit cell if the equalization mode is enabled.