Patent ID: 11862635
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A method of fabricating an integrated circuit structure, the method comprising:
forming a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate, the nanowires of the second vertical arrangement of nanowires having a horizontal width greater than a horizontal width of the nanowires of the first vertical arrangement of nanowires;
forming a first gate stack over the first vertical arrangement of nanowires;
forming a second gate stack over the second vertical arrangement of nanowires;
forming first epitaxial source or drain structures at ends of the first vertical arrangement of nanowires;
forming second epitaxial source or drain structures at ends of the second vertical arrangement of nanowires, wherein neighboring ones of the first epitaxial source or drain structures and of the second epitaxial source or drain structures have a laterally merged region there between;
removing the laterally merged region to disjoin the neighboring ones of the first epitaxial source or drain structures and of the second epitaxial source or drain structures; and
forming an intervening dielectric structure between the neighboring ones of the first epitaxial source or drain structures and of the second epitaxial source or drain structures.