Patent ID: 11925031
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. An array of ferroelectric memory cells individually comprising a ferroelectric capacitor above a transistor, comprising:
rows and columns of vertical transistors, a gateline line interconnecting multiple of the transistors along individual of the rows in a row direction, a plurality of digitlines with each digitline interconnecting multiple of the transistors along individual of the columns in a column direction, the transistors individually comprising a lower source/drain region directly electrically coupled with individual of the digitlines, the transistors individually comprising an upper source/drain region;
a plurality of horizontally-spaced groups individually comprising a plurality of horizontally-spaced lower capacitor electrodes, individual of the lower capacitor electrodes being directly above and directly electrically coupled to individual of the upper source/drain regions, immediately adjacent of the horizontally-spaced groups being horizontally spaced apart from one another by a gap that is horizontally elongated in the column direction;
a ferroelectric capacitor insulator over the lower capacitor electrodes;
an upper capacitor electrode that is common to all capacitors in individual groups comprised by the plurality of horizontally-spaced groups; the capacitors in the individual groups individually comprising one of the lower capacitor electrodes, the capacitor insulator, and the common upper capacitor electrode in the respective individual group;
a horizontally-elongated conductive line atop and directly electrically coupled with the upper capacitor electrode in the individual groups; and
horizontally-spaced pillars in the gap between immediately-adjacent of the individual groups, the pillars being of a same size and shape relative to the lower capacitor electrodes and being circuit inoperative.