Patent ID: 11870441
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: nan (nan)
Classification: CPC nan | IPC G  H

Claim 10:
11. The clock gating circuit of claim 8, further comprising:
a first transistor of the first type, the first transistor including a second gate terminal, a second drain terminal and a second source terminal, the second gate terminal being coupled to at least the second node, and configured to receive the second control signal, the second drain terminal being coupled to the output node, and the second source terminal being coupled to the third node and the first drain terminal of the first pull-up transistor; and
a first pull-down transistor of a second type different from the first type, the first pull-down transistor including a third gate terminal, a third drain terminal and a third source terminal, the third gate terminal being configured to receive the inverted clock input signal, the third drain terminal being coupled to at least the output node and the second drain terminal of the first transistor, and the third source terminal being coupled to a reference voltage supply, the first pull-down transistor being configured to adjust the clock output signal responsive to the inverted clock input signal.