Patent ID: 11923286
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A package substrate comprising:
an insulating layer having a mounting surface;
a wiring pattern extending in the insulating layer; and
a chip bonding pad provided on the mounting surface of the insulating layer and connected to the wiring pattern,
wherein the chip bonding pad comprises:
a connection portion having a uniform horizontal cross-sectional area in a vertical direction with respect to the mounting surface of the insulating layer; and
a bonding portion having a tapered shape in which a horizontal cross-sectional area of the bonding portion decreases away from the mounting surface of the insulating layer in the vertical direction,

wherein a vertical cross-section of the bonding portion of the chip bonding pad has a trapezoidal shape in which a length of a top side of the bonding portion is less than a length of a bottom side of the bonding portion,
wherein the top side of the bonding portion has a length of about 5 μm to about 25 μm, and
wherein the bottom side of the bonding portion has a length which is greater than the length of the top side of the bonding portion and is in a range of about 20 μm to about 30 μm.