Patent ID: 11942180
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. The memory system according to claim 3, wherein
N semiconductor memory devices are disposed, when K is set to an integer of 2 or more, N is an integer of K×2, and
the memory system further includes:
a first signal line connected to the first pad of each of a first to a K-th semiconductor memory devices;
a second signal line connected to the first pad of each of a K+1-th to an N-th semiconductor memory devices;
a plurality of third signal lines each connected to the plurality of second pads of each of the first to the N-th semiconductor memory devices;
a fourth signal line connected to the third pad of each of the first to the N-th semiconductor memory devices; and
a fifth signal line connected to the fourth pad of each of the first to the N-th semiconductor memory devices, and

the control device is capable of controlling voltage levels of the first to the fifth signal lines.