Patent ID: 11961563
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 14:
15. A non-volatile storage system comprising
a three-dimensional memory structure comprising a plurality of vertically oriented NAND strings having memory cells having control gates, the three-dimensional memory structure comprising a plurality of word lines, wherein each word line is connected to the control gates of memory cells on a group of the NAND strings, wherein ramping a voltage to the word lines associated with a group of the NAND strings at a default ramp rate during a verify phase when programming a selected word line has a default peak current; and
one or more control circuits configured to:
program memory cells on a selected group of the NAND strings in the three-dimensional memory structure; and
ramp voltages applied to respective word lines associated with the selected group of the NAND strings during verify phases of programming the memory cells connected to a first selected word line at a first rate that is faster than the default ramp rate in response to the first selected word line having a first default peak current for the default ramp rate that is below a target peak current while keeping a peak current during the verify phases within the target peak current.