Patent ID: 11929110
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 6:
7. The memory circuit of claim 1, further comprising:
a first global pre-decoder line extending in at least a first direction, overlapping at least the first local control circuit, being coupled to the global control circuit and the first set of repeater circuits, and being configured to supply the first set of global pre-decoder signals;
a second global pre-decoder line extending in at least the first direction, overlapping at least the first local control circuit, being coupled to the global control circuit and the first set of repeater circuits, and being configured to supply the second set of global pre-decoder signals;
a first local pre-decoder line extending in at least the first direction, overlapping at least the first local control circuit, being coupled to the first set of repeater circuits, and being configured to supply the first set of local pre-decoder signals; and
a second local pre-decoder line extending in at least the first direction, overlapping at least the first local control circuit, being coupled to the first set of repeater circuits, and being configured to supply the second set of local pre-decoder signals.