Patent ID: 11880265
Assignee: NVIDIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. A method comprising:
receiving, at a device comprising a counter and a logic device, a first set of data frames;
performing, at the device, an error detection operation on each data frame of the first set of data frames received;
updating, at the counter, a counter value to a first count value corresponding to a number of errors detected in response to performing the error detection operation on each data frame;
receiving, at the counter, a period marker signal from the logic device at an end of a programmable period;
resetting the first count value to zero in response to receiving the period marker signal and a decrement signal having a zero value; or
reducing the first count value to a second count value in response to receiving the period marker signal from the logic device and the decrement signal having a non-zero value; or
resetting the first count value to zero in response to receiving a reset signal; and
outputting a first interrupt responsive to the first count value or the second count value satisfying a threshold number of errors.