Patent ID: 11901015
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. An apparatus, comprising:
a plurality of memory cells arranged in an array that includes a plurality of channels that are in electrical communication with a source line; and
an erasing means for erasing the memory cells in at least one erase pulse, during the at least one erase pulse, the erasing means being configured to
drive the source line to an elevated voltage that is equal to an erase voltage Vera plus a kick voltage V_kick for a duration t_kick, and then
reduce the voltage of the source line to the erase voltage Vera such that a voltage of the channel remains elevated during the entire erase pulse,

wherein the kick voltage V_kick is in the range of 2 and 3 V and the duration t_kick is in the range of 1 and 10 μs.