Patent ID: 11922108
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 4:
5. The method of claim 1, wherein the generating the first set of memory cell layout patterns or the second set of memory cell layout patterns comprises:
generating a set of selector element layout patterns corresponding to fabricating a set of selector elements arranged in the first column of memory cells or the second column of memory cells, each layout pattern of the set of selector element layout patterns being separated from an adjacent layout pattern of the set of selector element in the first direction and being located on a first set of layout levels; and
generating a set of resistive switching element layout patterns corresponding to fabricating a set of resistive switching elements arranged in the first column of memory cells or the second column of memory cells, each layout pattern of the set of resistive switching element layout patterns being separated from an adjacent layout pattern of the set of resistive switching element layout patterns in the first direction, and being located on a second set of layout levels above the first set of layout levels.