Patent ID: 11876698
Assignee: VIAVI SOLUTIONS INC.
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An apparatus comprising:
at least one hardware processor;
a memory storing machine readable instructions, the machine readable instructions, when executed by at least one hardware processor, cause the at least one hardware processor to:
receive, from a speed test control application installed on the apparatus, speed test control instructions and data connection instructions for the apparatus to perform a high-speed test associated with network traffic of a network; and
forward the speed test control instructions and the data connection instructions to a speed test control server; and

a hardware-based traffic analyzer comprising a data port to, based on the speed test control instructions and the data connection instructions forwarded to the speed test control server, establish a connection with the speed test control server, and perform the high-speed test associated with the network traffic of the network by transmitting and receiving relatively high bit-rate data to and from the speed test control server, and a control port to transmit relatively slow-speed control traffic to the speed test control application,
wherein the at least one hardware processor is further to:
receive results of the high-speed test from the speed test control server; and
transmit the results of the high-speed test to the speed test control application.