Patent ID: 11929352
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC H

Claim 6:
7. The memory chip of claim 6, further comprising:
a set of second word lines, which are stacked along the first direction and extend in the first region and the second region of the memory chip along the second direction;
another pillar including:
another semiconductor layer extending through the second word lines along the first direction in the first region, and
another insulating layer between the another semiconductor layer and the second word lines;

another set of memory cells in the first region, each of which is disposed at a corresponding intersection of the another pillar and one of the second word lines; and
another set of transistors in the second region, each of which is electrically connected between a corresponding one of the second word lines and a corresponding one of the signal lines.