Patent ID: 11901241
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A device, comprising:
a first active region and a second active region each disposed over a substrate;
a first gate structure disposed over the first active region, wherein the first gate structure includes: a gate dielectric layer, a first layer disposed over the gate dielectric layer, an n-type work function layer disposed over the first layer, a second layer disposed over the n-type work function layer, and a p-type work function layer disposed over the second layer; and
a second gate structure disposed over the second active region, wherein the second gate structure includes: the gate dielectric layer, the first layer disposed over the gate dielectric layer, and the p-type work function layer disposed over the first layer;
wherein:
the n-type work function layer includes Ti, Al, Ag, Mn, Zr, TiAl, TiAlC, TaC, TaCN, TaSiN, TaAl, TaAlC, or TiAlN; and
the p-type work function layer includes RuO2 or IrO2.