Patent ID: 11960755
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 3:
4. The semiconductor memory device of claim 3, wherein the order controller comprises:
first order determination logic configured to determine the output or non-output and the first output order of each of the first addresses according to whether each of the ‘K’ counting values reaches a reference value and an order in which each of the ‘K’ counting values reaches the reference value; and
second order determination logic configured to determine the second output order by dividing the first addresses by ‘A’ and putting ‘B’ second addresses between the divided ‘A’ first addresses, based on a number of inputs of a target refresh command input for control of the target refresh operation, wherein ‘A’ and ‘B’ are natural numbers equal to or greater than 1.