Patent ID: 11887650
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A semiconductor memory device, comprising:
a memory cell array including a plurality of memory banks, each of the memory banks including memory cells arranged in a plurality of rows;
a row decoder connected to the memory cell array;
a refresh area storage unit configured to store refresh information which classifies the plurality of rows into one of refresh area and refresh skip area, the refresh area being a first group of rows among the plurality of rows in which memory cells connected to the first group of rows to be refreshed and the memory skip area being a second group of rows among the plurality of rows in which memory cells connected to the second group of rows not to be refreshed; and
a refresh control circuit connected to the row decoder, and configured to control a refresh operation for each row of the refresh area to be refreshed and control the refresh operation for each row of the refresh skip area not to be refreshed,
wherein at least one memory bank among the plurality of memory banks includes both the refresh area and the refresh skip area.