Patent ID: 11973006
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A method comprising:
etching a through-substrate via (TSV) in a substrate from a backside of the substrate up to a frontside of the substrate, the substrate having an insulator layer disposed on the frontside of the substrate and including a metal pad;
depositing an insulating liner on a sidewall and a bottom of the TSV;
forming a self-aligned mask lining the sidewall of the TSV, the self-aligned mask being a spacer material;
etching a contact opening in the insulator layer at the bottom of the TSV through the self-aligned mask to expose the metal pad inside the insulator layer; and
with the self-aligned mask in place on the sidewall of the TSV, disposing a conductive material layer in the contact opening and on the sidewall of the TSV to form a tubular vertical interconnection to the metal pad, the tubular vertical interconnection including a tubular section in the TSV and a solid cylindrical section in the contact opening to the metal pad.