Patent ID: 11940914
Assignee: QUALCOMM INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. An apparatus for performing a partial cache collapse procedure, comprising:
memory comprising computer-executable instructions; and
one or more processors configured to execute the computer-executable instructions and cause the apparatus to:
count a number of cache lines that satisfy an eviction criteria based on a deterministic cache eviction policy in each cache way of a group of cache ways;
select at least one cache way from the group for collapse, based on its corresponding number of cache lines that satisfy the eviction criteria, wherein to select the at least one cache way, the one or more processors are configured to cause the apparatus to:
select, for collapse, one cache way having a highest number of cache lines that satisfy the eviction criteria, or
select multiple cache ways having highest numbers of cache lines that satisfy the eviction criteria; and

perform the partial cache collapse procedure based on the at least one cache way selected from the group for collapse.