Patent ID: 11973070
Assignee: SJ SEMICONDUCTOR(JIANGYIN) CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for making a double-layer stacked 3D fan-out packaging structure, comprising:
providing a first supporting substrate;
disposing a separation layer on the first supporting substrate;
placing a second rewiring layer on the separation layer;
forming a metal connecting pillar on the second rewiring layer by a wire bonding process, wherein the metal connecting pillar is electrically connected to the second rewiring layer;
providing a first semiconductor chip and bonding the first semiconductor chip to a first surface of the second rewiring layer, wherein the first surface is opposite to the second surface;
forming a packaging material layer on the first surface of the second rewiring layer, wherein the packaging material layer fills a gap between the first semiconductor chip and the metal connecting pillar and packages the first semiconductor chip and the metal connecting pillar, wherein the packaging material layer includes a first surface and a second surface opposite to the first surface, wherein the second surface of the packaging material layer is in contact with the first surface of the second rewiring layer, and the first surface of the packaging material layer exposes the metal connecting pillar;
forming a first rewiring layer on the first surface of the packaging material layer, wherein a first surface of the first rewiring layer is disposed on and electrically connected to the first semiconductor chip and the metal connecting pillar;
forming a solder bump on a second surface of the first rewiring layer, wherein the solder bump is electrically connected to the first rewiring layer;
providing a second supporting substrate and bonding the second supporting substrate to the second surface of the first rewiring layer;
removing the first supporting substrate and the separation layer to expose the second rewiring layer;
providing a second semiconductor chip and electrically connecting the second semiconductor chip to the second surface of the second rewiring layer;
forming an underfill layer between the second semiconductor chip and the second surface of the second rewiring layer, wherein the underfill layer is arranged at a part of a periphery area of the second semiconductor chip; and
removing the second supporting substrate.