Patent ID: 11948646
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. A semiconductor memory comprising:
a plurality of memory cell transistors, a threshold voltage of each of the memory cell transistors being changeable to store multi-bit data;
a word line which is electrically connected to gates of the memory cell transistors;
a plurality of bit lines which are electrically connected to first ends of the memory cell transistors, respectively;
a source line which is electrically connected to second ends of the memory cell transistors;
a plurality of sense amplifier units which are electrically connected to the bit lines, respectively, each of the sense amplifier units including a sense amplifier and a plurality of latches, the latches including a first latch; and
a controller, wherein
wherein the sense amplifier in each of the sense amplifier units includes:
a sense node,
a connection transistor having a first end electrically connected to a corresponding one of the bit lines and a second end electrically connected to the sense node,
a first voltage supply path capable of supplying a first voltage to a corresponding one of the bit lines based on data stored in the first latch, and
a second voltage supply path capable of supplying a second voltage to the sense node based on data stored in one of the latches.