Patent ID: 11916561
Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 7:
8. A clock generator comprising:
a first clock generator configured to receive an input clock signal, and generate two or more first-level clock signals of a track-and-hold circuit;
a phase interpolator configured to generate an interpolated clock signal, wherein the interpolated clock signal is generated based on the two or more first-level clock signals, wherein the phase interpolator comprises:
a first multiplexer configured to receive even-numbered first-level clock signals of the two or more first-level clock signals;
a second multiplexer configured to receive odd-numbered first-level clock signals of the two or more first-level clock signals; and

a second clock generator configured to generate two or more second-level clock signals based on the interpolated clock signal, wherein the phase of the two or more second-level clock signals relative to the phase of a respective first-level clock signal is determined, at least in part, by the phase of the interpolated clock signal.