Patent ID: 11862609
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A semiconductor package comprising:
a first die comprising:
a first semiconductor substrate;
a first dielectric structure comprising a substrate oxide layer disposed directly on a front side of the first semiconductor substrate and inter-layer dielectric (ILD) layers disposed on the substrate oxide layer;
a first interconnect structure embedded in the first dielectric structure;
a first through-substrate via (TSV) structure extending through the first semiconductor substrate; and
a first fuse structure embedded in the substrate oxide layer and electrically connecting the first TSV structure to the first interconnect structure, wherein the first fuse structure comprises:
a contact structure electrically connected to the first interconnect structure; and
a resistance control layer electrically connected to the contact structure.