Patent ID: 11887657
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. The amplifier circuit according to claim 1, wherein the sensing amplification circuit comprises:
a first P-type transistor, with one of a source or a drain coupled to the first node, the other one of the source or the drain coupled to the complementary readout node, and a gate coupled to the readout node;
a second P-type transistor, with one of a source or a drain coupled to the first node, the other one of the source of the drain coupled to the readout node, and a gate coupled to the complementary readout node;
a first N-type transistor, with one of a source or a drain coupled to the second node, the other one of the source or the drain coupled to the complementary readout node, and a gate coupled to the bit line; and
a second N-type transistor, with one of a source or a drain coupled to the second node, the other one of the source or the drain coupled to the readout node, and a gate coupled to the complementary bit line; and
the isolation circuit comprises:
a first isolation transistor, with one of a source or a drain coupled to the bit line, the other one of the source or the drain coupled to the readout node, and a gate used for receiving an isolation signal, wherein
the first isolation transistor is configured to be turned on based on the isolation signal at the sensing amplification stage to couple the readout node to the bit line; and
a second isolation transistor, with one of a source or a drain coupled to the complementary bit line, the other one of the source or the drain coupled to the complementary readout node, and a gate used for receiving the isolation signal, wherein
the second isolation transistor is configured to be turned on based on the isolation signal at the sensing amplification stage to couple the complementary readout node to the complementary bit line.