Patent ID: 11862232
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 1:
2. The circuit for data transmission of claim 1, wherein the mode register decoding module is disposed corresponding to a receiver, and the receiver comprises a mask receiver and a plurality of data receivers; the mode register read-write module comprises a first class mode register read-write module disposed corresponding to the data receiver and a second class mode register read-write module disposed corresponding to the mask receiver; and the logic gate module comprises:
a first logic gate unit, electrically connected to a plurality of first class mode register read-write modules, and configured to calculate an OR value of the data outputted by each first class mode register read-write module electrically connected with the first logic gate unit and to output the OR value; and
a second logic gate unit, configured such that: a first type input end is electrically connected to an output end of the first logic gate unit, a second type input end is electrically connected to the second class mode register read-write module, and an output end is electrically connected to the first cache module and configured to calculate an OR value of data received by the second logic gate unit and output the OR value.