Patent ID: 11864383
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A vertical-type memory device, comprising:
a peripheral circuit region comprising a lower substrate and circuit devices on the lower substrate; and
a cell region on the peripheral circuit region,
wherein the cell region comprises:
a plurality of gate electrodes stacked on a substrate; and
a vertical channel structure that penetrates the plurality of gate electrodes in a first direction, perpendicular to an upper surface of the substrate,

wherein the vertical channel structure comprises:
a channel layer extending in the first direction;
a first liner overlapping at least a portion of an upper internal side wall of the channel layer, wherein the first liner comprises n-type impurities; and
a pad on the first liner and in contact with the first liner,

wherein a bottom surface of the first liner is convexly rounded toward the upper surface of the substrate,
wherein the bottom surface of the first liner is lower than a lower surface of an uppermost first gate electrode among the plurality of gate electrodes and is higher than an upper surface of a second gate electrode directly below the first gate electrode, and
wherein a bottom surface of the pad is convexly rounded toward the upper surface of the substrate.