Patent ID: 11901023
Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. The memory device of claim 6, wherein the processing circuitry is further configured to:
apply a gate voltage with a first gate voltage level on an unselected TSG, and subsequently lower the gate voltage applied on the unselected TSG from the first gate voltage level to a second gate voltage level that is effective to turn off the unselected TSG;
increase a bias voltage applied on an unselected word line layer that is below the selected word line layer or adjacent to and above the selected word line layer from an initial voltage level to a target voltage level while applying the gate voltage with the first gate voltage level on the unselected TSG layer and subsequently lowering the gate voltage applied on the unselected TSG layer from the first gate voltage level to the second gate voltage level; and
continue to increase the bias voltage applied on the unselected word line layer that is below the selected word line layer or adjacent to and above the selected word line layer after the gate voltage applied on the unselected TSG layer reaches the second gate voltage level that is effective to turn off the unselected TSG and before the end of the pre-pulse stage.