Patent ID: 11948251
Assignee: ADVANCED MICRO DEVICES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. An apparatus comprising:
a set of registers configured to store information, based on tessellation factors generated by a hull shader circuitry, indicating domain shader circuitry latencies estimated for thread groups launched by the hull shader circuitry and stored in a buffer;
a first counter that is incremented in response to launching a thread group from the buffer and has a total count value representative of a primitive launch time interval for a domain shader circuitry;
a second counter that has a value based on a measured domain shader circuitry latency, wherein the value of the second counter is used to modify the first counter; and
a comparison circuitry configured to throttle launching thread groups from the hull shader circuitry based on the primitive launch time interval.