Patent ID: 11955972
Assignee: EPINOVATECH AB
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 1:
2. The FPGA device according to claim 1, wherein the logic inverter is a cascode inverter, wherein the logic inverter comprises at least two HEMTs, wherein each HEMT comprises:
a Si substrate;
an AlyGay-1N layer structure;
a GaN layer structure; and

a crystal transition layer structure arranged on the Si substrate, wherein the crystal transition layer comprises:
a plurality of vertical nanowire structures perpendicularly arranged on the Si substrate, and
an AlxGax-1N layer structure, wherein 0≤x<1, wherein the AlxGax-1N layer structure is arranged to vertically and laterally enclose the vertical nanowire structures.