Patent ID: 11942469
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 7:
8. An integrated circuit comprising:
a first-type active-region structure and a second-type active-region structure extending in a first direction on a substrate;
a front-side first-layer conducting line in a first connection layer above the substrate;
a plurality of gate-conductors extending in a second direction below the first connection layer, and wherein two adjacent gate-conductors are separated by a pitch distance equal to a contacted poly pitch (“CPP”),
circuit cell having a first vertical boundary and a second vertical boundary extending in the second direction perpendicular to the first direction, wherein each of the first vertical boundary and the second vertical boundary crosses at least one boundary isolation region;
a backside horizontal conducting line extending in the first direction in a backside first conducting layer below the substrate;
a backside vertical conducting line extending in the second direction in a backside second conducting layer below the backside first conducting layer;
a pin-connector for the circuit cell directly connected between the backside horizontal conducting line and the backside vertical conducting line at an overlap region between the backside horizontal conducting line and the backside vertical conducting line; and
wherein the backside vertical conducting line has a first portion covering the overlap region and a second portion outside the overlap region, and wherein a first width of the first portion along the first direction is larger than a second width of the second portion along the first direction.