Patent ID: 11967392
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. An apparatus for testing failure of a memory, comprising:
a data write circuit configured to write preset storage data into a storage array of the memory;
a test circuit configured to raise a bit line voltage, control a part of word lines of the storage array to enter a test mode, and exit the test mode after waiting for preset time;
a data read circuit configured to turn off sense amplifiers corresponding to a preset part of bit lines, and read data from a remaining part of the bit lines;
a comparison circuit configured to compare the data read from the remaining part of the bit lines with the preset storage data to obtain a comparison result; and
a determination circuit configured to determine a failure state of the memory according to the comparison result.