Patent ID: 11881442
Assignee: SHANGHAI INTEGRATED CIRCUIT MANUVACTURING INNOVATION CENTER CO., LTD
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An SOI active interposer for three-dimensional packaging, comprising:
an SOI substrate;
a CMOS inverter, including a PMOS transistor and an NMOS transistor and formed on the SOI substrate;
an SOI via hole formed between the PMOS transistor and the NMOS transistor and penetrating through the SOI substrate;
a first insulating medium covering the PMOS transistor and the NMOS transistor;
a second insulating medium formed on the sidewall of the SOI via hole and the surface of the first insulating medium; and
source, drain and gate via holes respectively formed on a source, drain and gate of the PMOS transistor and the NMOS transistor, and penetrating through the first insulating medium and the second insulating medium;
wherein the second insulating medium is disposed on the first insulating medium and in direct contact with the first insulating medium, and the side wall of the SOI via hole is continuously covered by the second insulating medium;
wherein the sidewall of the SOI via hole is formed with a copper diffusion barrier layer and a seed layer, the inside thereof is filled with copper, the top thereof is formed with an adhesion layer/seed layer laminated film and a micro bump, and the bottom thereof is formed with an adhesion layer/seed layer laminated film and a C4 bump; and
the bottoms and the sidewalls of the source, drain and gate via holes are formed with a copper diffusion barrier layer and a seed layer, the insides thereof are filled with copper, and the tops thereof are formed with an adhesion layer/seed layer laminated film and micro bumps.