Patent ID: 11948616
Assignee: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 15:
16. The manufacturing method of a semiconductor structure according to claim 15, wherein the control terminal of the transistor is a gate, the first terminal of the transistor is a drain, the second terminal of the transistor is a source, and the selection line is a source line;
while the first interconnecting hole is formed in the first dielectric layer, an eighth interconnecting hole is further formed in the first dielectric layer, wherein the eighth interconnecting hole exposes the second terminal of the transistor;
while the first interconnecting structure is formed in the first interconnecting hole, an eighth interconnecting structure is further formed in the eighth interconnecting hole; and
while the first conductor layer is formed on the upper surface of the first dielectric layer, a source line is further formed on the upper surface of the first dielectric layer, wherein the source line is electrically connected to the second terminal of the transistor through the eighth interconnecting structure, and a gap exists between the source line and the first conductor layer.