Patent ID: 11880682
Assignee: AMAZON TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A systolic array processor organized in rows and columns, each row comprising:
a reducer, the reducer configured to convert 32-bit input data elements into reduced 22-bit input data elements, the reducer comprising:
a trailing bit reducer configured to reduce a quantity of bits representing a significand portion of a 32-bit input data element of the 32-bit input data elements to produce a reduced significand portion of the 32-bit input data element;
a rounder configured to round the reduced significand portion of the 32-bit input data element to produce a rounded significand portion; and
an exponent expander configured to increase a quantity of bits representing an exponent portion of the 32-bit input data element to produce an increased exponent portion,
wherein the reducer produces a reduced 22-bit input data element based on the rounded significand portion and the increased exponent portion; and

a plurality of processing elements, the plurality of processing elements configured to receive the reduced 22-bit input data elements from the reducer and to receive weights for performing multiply-accumulate operations.