Patent ID: 11908404
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. A pixel circuit, comprising:
a storage capacitor circuit, a first terminal of the storage capacitor circuit being electrically coupled to a first node, a second terminal of the storage capacitor circuit being electrically coupled to a second node;
a light-emitting element;
a driving transistor having a control electrode electrically coupled to the first node;
a writing circuit electrically coupled to the storage capacitor circuit and configured to receive a writing control signal and write a data voltage into the storage capacitor circuit according to the writing control signal;
a reset circuit electrically coupled to the first node and the second node, the reset circuit being configured to receive a reset control signal and reset the first node and the second node according to the reset control signal;
a threshold compensation circuit electrically coupled to the first node and the driving transistor, the threshold compensation circuit being configured to receive a compensation control signal and write a compensation voltage into the first node according to the compensation control signal, wherein the compensation voltage includes at least a threshold voltage of the driving transistor; and
a light-emitting control circuit electrically coupled to the driving transistor and the light-emitting element and being configured to receive a light-emitting control signal and control the light-emitting element to emit light according to the light-emitting control signal, wherein the driving transistor controls the light-emitting element to emit light according to a voltage of the first node, and the voltage of the first node in a driving stage is a voltage generated by adding the data voltage and the compensation voltage,
wherein the reset circuit is configured to receive the reset control signal supplied through a reset control line, and the reset circuit comprises:
a first transistor having a first electrode electrically coupled to the first node, a second electrode electrically coupled to a first power supply line, and a control electrode electrically coupled to the reset control line, wherein the first power supply line is configured to supply a first voltage to the reset circuit;
a second transistor having a first electrode electrically coupled to the second node, a second electrode electrically coupled to a second power supply line, and a control electrode electrically coupled to the reset control line, wherein the second power supply line is configured to supply a second voltage to the reset circuit, and
wherein the reset circuit further comprises a potential holding circuit electrically coupled to the second node, the reset circuit is configured to receive the compensation control signal and write the second voltage to the second node according to the compensation control signal, wherein the compensation control signal is supplied to the potential holding circuit through a compensation control line, and the potential holding circuit comprises:
a third transistor having a first electrode electrically coupled to the second node, a second electrode electrically coupled to the second power supply line, and a control electrode electrically coupled to the compensation control line.