Patent ID: 11923016
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device comprising:
NAND memory; and
logic coupled to one or more substrates, wherein the logic is at least partly implemented in one or more of configurable or fixed-functionality hardware, and the logic coupled to the one or more substrates is to:
resume a program operation with respect to the NAND memory during a first tier in response to a suspension counter reaching a first threshold;
resume the program operation with respect to the NAND memory during a second tier in response to the suspension counter reaching a second threshold;
resume the program operation with respect to the NAND memory during a third tier in response to the suspension counter reaching a third threshold; and
service one or more read operations with respect to the NAND memory until the suspension counter reaches the first threshold during the first tier, until the suspension counter reaches the second threshold during the second tier, and until the suspension counter reaches the third threshold during the third tier.