Patent ID: 11881255
Assignee: NVIDIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A multi-rank circuit system comprising:
a plurality of ranks;
a shared input/output (IO) channel;
a plurality of IO circuits coupled to the ranks via the shared IO channel;
at least one control circuit for the IO circuits;
a plurality of multi-bit digital busses;
a first stage comprising a plurality of selectors coupled to input the digital busses;
a second stage comprising one or more selectors coupled to receive outputs of the first stage of selectors and to individually select one of the outputs of the first stage of selectors to the control circuit; and
logic configured to switch one of the ranks to be an active rank on the shared IO channel, and to operate the first stage of selectors to select one of the digital busses to the second stage of selectors in advance of switching a next active rank to the shared IO channel.