Patent ID: 11973071
Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor module, comprising:
a low side switch;
a high side switch, wherein the low side switch and the high side switch are arranged laterally adjacent one another and coupled in series between a ground package pad and a voltage input (VIN) package pad arranged on a first side of the semiconductor module and form a half bridge configuration having an output node;
a first capacitor pad coupled to ground potential; and
a second capacitor pad coupled to a VIN potential,
wherein the first capacitor pad is arranged vertically above the low side switch and the second capacitor pad is arranged vertically above the high side switch,
wherein the low side switch comprises a first side and a second side opposing the first side, a source pad on the first side, and a drain pad on the second side,
wherein the source pad of the low side switch is mounted on and electrically connected to a first conductive layer,
wherein the high side switch comprises a first side and a second side opposing the first side, a source pad on the first side, and a drain pad on the second side,
wherein the drain pad of the high side switch is mounted on and electrically connected to a second conductive layer that is substantially coplanar with the first conductive layer,
wherein the output node is formed by a third conductive layer extending between and electrically coupled to the drain pad of the low side switch and the source pad of the high side switch, and
wherein the third conductive layer comprises a first opening in which the first capacitor pad is arranged and a second opening in which the second capacitor pad is arranged, or a single opening in which the first capacitor pad and the second capacitor pad are arranged,
wherein the first capacitor pad and the second capacitor pad are each spaced apart from side walls defining the respective first opening, second opening, or single opening in which each of the first capacitor pad and the second capacitor pad is arranged.