Patent ID: 11948638
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. An apparatus, comprising:
a plurality of pillars extending vertically through a plurality of tiers of memory cells, each pillar of the plurality of pillars coupled with two memory cells at each tier of the plurality of tiers;
a plurality of bit lines;
a plurality of sets of pillar selectors, each set of pillar selectors associated with a respective conductive line configured to control activation of the set of pillar selectors, wherein activation of a set of pillar selectors couples a subset of pillars of the plurality of pillars with the plurality of bit lines; and
a plurality of word line drivers coupled with a plurality of sets of word lines, each tier of memory cells coupled with two sets of word lines of the plurality of sets of word lines, wherein a word line driver of the plurality of word line drivers is configured to:
bias, during a first duration and to a first voltage, a first set of word lines of the plurality of sets of word lines coupled with the word line driver and a first tier of memory cells of the plurality of tiers of memory cells, wherein, during the first duration, at least one memory cell of a first subset of the first tier of memory cells thresholds based at least in part on biasing the first set of word lines to the first voltage;
bias, during a second duration after the first duration, the first set of word lines to a second voltage, wherein, during the second duration, at least one memory cell of a second subset of the first tier of memory cells thresholds and the at least one memory cell of the first subset of the first tier of memory cells is written to a first logic state based at least in part on biasing the first set of word lines to the second voltage; and
bias, during a third duration after the second duration, the first set of word lines to a third voltage, wherein, during the third duration, the at least one memory cell of the second subset of the first tier of memory cells is written to a second logic state based at least in part on biasing the first set of word lines to the third voltage.