Patent ID: 11923329
Assignee: nan
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 14:
15. A method for making a semiconductor die assembly, the method comprising:
electrochemically plating metal by an electrochemical plating process onto an array of first pillars extending from a first region of a major surface of a semiconductor die; and
simultaneously electrochemically plating metal by the electrochemical plating process onto an array of second pillars extending from a non-overlapping second region of the major surface of the semiconductor die,
wherein—
a difference between a minimum lateral spacing between the first pillars and a minimum lateral spacing between the second pillars has a first effect on relative metal deposition rates of the electrochemical plating process at the first and second regions of the major surface of the semiconductor die, or
a difference between an average width of the first pillars and an average width of the second pillars has a second effect on the relative metal deposition rates of the electrochemical plating process at the first and second regions of the major surface of the semiconductor die.