Patent ID: 11967389
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. A semiconductor apparatus comprising:
a plurality of memory banks divided into a plurality of bank groups, the plurality of bank groups including at least a first bank group and a second bank group;
a plurality of sense amplifiers configured to sense and amplify data output from memory banks connected to the plurality of sense amplifiers among the plurality of memory banks, and to transmit the amplified data;
a first storage circuit located outside the plurality of memory banks and connected to the plurality of sense amplifiers;
an error correction circuit configured to correct an error bit of data output from the plurality of memory banks;
a first sub-read path, one side terminals of the first sub-read path are connected to the first bank group and the first storage circuit in common and other side terminals of the first sub-read path are connected to the error correction circuit;
a second sub-read path, one side terminals of the second sub-read path are connected to the second bank group and the first storage circuit in common and other side terminals of the second sub-read path are connected to the error correction circuit;
a second storage circuit connected to an output terminal of the error correction circuit; and
a control circuit configured to control the amplified data to be simultaneously stored in the first storage circuit by deactivating the first sub-read path and the second sub-read path during a first sub-test section, and to control the data stored in the first storage circuit to be sequentially stored in the second storage circuit after being subjected to an error correction operation through the error correction circuit by sequentially activating the first sub-read path and the second sub-read path during a second sub-test section.