Patent ID: 11881262
Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A resistive random access memory (ReRAM) device comprising:
an array of memory cells each connected to a first supply line set at a first supply potential, each cell of said array being provided with at least one first resistive element of variable resistivity and in series with at least one first selection transistor,
a read circuit associated with a column of cells of the array, the read circuit comprising:
a sense amplifier of the latch type consisting of cross-connected inverters and equipped with a first read node and a second read node, said inverters respectively forming a first branch and a second branch each connected on one side to a second supply line set at a second supply potential, different from said first supply potential,
at least one first coupling transistor connecting another side of said first branch to a first bit line coupled to the first respective resistive elements of the cells of said column,
at least one second coupling transistor connecting another side of said second branch either to a second bit line coupled to the second resistive elements of the cells of said column, or to a reference line delivering a reference current;
a circuit for controlling read operations on the array by way of signals for controlling switch elements, said control circuit being configured to, during a read operation carried out on a given cell of said column:
according to a waiting phase, charge said first bit line to a potential equal or close or substantially equal to said first supply potential, then,
according to a reset phase of said sense amplifier, by way of at least one reset transistor connect the first read node and the second read node, so as to equalise the potentials of the first read node and of the second read node;
according to a partial discharge phase, connect the first bit line to the second supply line and when the device includes the second bit line connect the second bit line to the second supply line, so as to partially discharge said first bit line or said bit lines and obtain at the terminals of the cells of said column a non-zero difference of potentials while being lower, and in particular much lower, than a difference of potentials between the first supply potential and said second supply potential, the reset phase being triggered during the partial discharge phase; then
according to a comparison phase, during which said first and second coupling transistors are rendered conducting, and said at least one reset transistor is rendered non-conducting, in order to make possible a circulation of a first current through said first branch of said sense amplifier, the first bit line and a first resistive element of said cell and a circulation of a second current through said second branch of said sense amplifier as well as either the reference line or the second bit line and a second resistive element of said cell, until a toggling of said sense amplifier according to a difference between said first and second currents.