Patent ID: 11917206
Assignee: LENOVO (SINGAPORE) PTE. LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. The apparatus of claim 15, wherein the at least one processor is configured to indicate the allocated coding rates out of the rate-compatible superset  for individual CBGs or mTBs forming a UEP coded TB by means of a bit field configuration enclosed within at least one of:
a DM-RS signaling resource;
a DCI scheduling a PDSCH or PUSCH containing the CBGs or mTBs of the UEP coded TB;
a UCI request for a corresponding PUSCH scheduling or scheduling update wherein the CBGs or mTBs of the UEP coded TB are contained;
a UCI associated with a PUSCH transmission containing the CBGs or mTBs of the UEP coded TB;
a DCI periodic information signaling aligned with a slot format indicator (“SFI”); and
a front-loaded information field of the UEP coded TB encoded with a predetermined FEC code.