Patent ID: 11930643
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 6:
7. The memory device of claim 6, wherein:
each memory cell of a first plurality of memory cells of the first memory array is associated with a respective third transistor at the first level operable to couple the memory cell with a digit line of the first plurality of digit lines, each of the third transistors comprising a respective channel portion comprising a respective set of one or more third semiconductor pillars overlapping, along a height dimension relative to the substrate, with the first semiconductor pillars; and
each memory cell of a second plurality of memory cells of the second memory array is associated with a respective fourth transistor at the second level operable to couple the memory cell with a digit line of the second plurality of digit lines, each of the fourth transistors comprising a respective channel portion comprising a respective set of one or more fourth semiconductor pillars overlapping, along the height dimension relative to the substrate, with the second semiconductor pillars.