Patent ID: 11901033
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. An operating method of a memory device including first page buffers connected to a first bit line group, second page buffers connected to a second bit line group, third page buffers connected to a third bit line group, and fourth page buffers connected to a fourth bit line group, the operating method comprising:
receiving an address for memory access from a memory controller;
determining whether a column address in the address is a defect address;
when the column address is not the defect address, outputting first data received from the first page buffers according to first column repair information in response to a first selection signal corresponding to the first bit line group being in an enabled state, and outputting second data received from the second page buffers according to second column repair information in response to a second selection signal corresponding to the second bit line group being in the enabled state; and
when the column address is the defect address, outputting third data received from the third page buffers according to third column repair information in response to a third selection signal corresponding to the third bit line group being in the enabled state, and outputting fourth data received from the fourth page buffers according to fourth column repair information in response to a fourth selection signal corresponding to the fourth bit line group being in the enabled state,
wherein the first and second page buffers are connected to normal memory cells and collinear in a first direction,
the third and fourth page buffers are connected to redundant memory cells and collinear in the first direction,
a first width of a region including the first bit line group is the same as a width of a first gate in a first transistor of a second direction, the first transistor included in each of the first page buffers,
a second width of a second region including the second bit line group is the same as a width of a second gate of a second transistor in the second direction, the second transistor included in each of the second page buffers, and
the first transistor in the first page buffers and the second transistor included in the second page buffers are collinear in the first direction.