Patent ID: 11934305
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. The memory system according to claim 5, wherein
each of the plurality of third circuits is connected to the second circuit via a plurality of queues,
the management information is divided into a plurality of management information segments to which third serial numbers are respectively assigned,
the second memory includes a cache memory configured to cache the management information in units of management information segments, and
the second circuit is configured to:
receive the plurality of first sub-commands in the order of issuance;
transmit, when a first management information segment that is a management information segment required to identify a location of data in the first data unit related to one first sub-command among the plurality of received first sub-commands is cached in the cache memory, the one first sub-command to one of the plurality of third circuits via a queue corresponding to the third serial number given to the first management information segment among the plurality of queues; and
execute refill of the first management information segment when the first management information segment is not cached in the cache memory, and then transmit the one first sub-command to the one of the plurality of third circuits via the queue corresponding to the third serial number given to the first management information segment among the plurality of queues.