Patent ID: 11921578
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 10:
11. The semiconductor device of claim 10,
wherein the first memory region is configured to output the first internal data stored in the first memory region through the word line activated by the read signal and the address signal to the input/output line during the read operation, store the first internal data in the first memory region through the word line activated by a write signal and the address signal during a write operation, and perform the refresh operation in which multiple word lines are sequentially activated by a refresh address signal, and
the second memory region is configured to output the second internal data stored in the second memory region through the word line activated by the read signal and the address signal to the input/output line during the read operation, store the second internal data in the second memory region through a word line activated by the write signal and the address signal during the write operation, and perform the refresh operation in which the multiple word lines are sequentially activated by the refresh address signal.