Patent ID: 11942137
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A semiconductor memory device comprising:
a memory cell array including a plurality of memory cell rows, each including a plurality of volatile memory cells;
a row hammer management engine configured to:
predict a first probability of occurrence of a row hammer in which at least one of the plurality of memory cell rows is intensively accessed by a first row access pattern on at least a second portion on the plurality of memory cell rows during a first reference time interval posterior to a first refresh interval during which at least a first portion of the plurality of memory cell rows are refreshed, based on machine learning, and
generate a hammer address associated with the row hammer, an outcast row list, and an alert signal indicating that the row hammer occurs, the outcast row list being associated with outcast memory cell rows from among the plurality of memory cell rows which are excluded from a hammer refresh operation for coping with the row hammer; and

a refresh control circuit configured to receive the hammer address, the alert signal and the outcast row list, configured to perform the hammer refresh operation on one or more victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address, and configured to perform a target refresh operation on the outcast memory cell rows based on the outcast row list.