Patent ID: 11930644
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A semiconductor structure, comprising:
multiple first active regions that are separate from one another and located in a substrate;
connection pads, each of the connection pads connecting ends of adjacent first active regions of the multiple first active regions; and
magnetic tunnel junctions, each of the magnetic tunnel junctions being connected with a respective one of the connection pads;
wherein each of the multiple first active regions connected with a respective one of the connection pads is located in a first region of the substrate, and
the semiconductor structure further comprises;
second active regions located in a second region of the substrate; and
capacitor storage structures, each of the capacitor storage structures being connected with an end of a respective one of the second active regions by a capacitor contact plug.