Patent ID: 11877441
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 12:
13. The method of fabricating a memory according to claim 11, wherein, after forming the bitline contact plunger in each concave hole, the method further comprises:
forming a second layer of polysilicon on the bitline contact plunger, a top surface of the second layer of polysilicon being flush with a top surface of the separation layer;
forming a protective layer on the separation layer that remains and the second layer of polysilicon; and
removing part of the protective layer, part of the second layer of polysilicon, and part of the separation layer to form wordline grooves, wherein the wordline grooves are arranged along a fourth direction and extend along the first direction, the fourth direction is set perpendicular to the first direction, the second layer of polysilicon that remains forms an active region located at both sides of the wordline grooves, in the protective layer that remains are formed node plunger slots communicative with the wordline grooves, and widths of the node plunger slots are greater than widths of the wordline grooves.