Patent ID: 11928523
Assignee: GRAPHCORE LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A processing device comprising a processing unit comprising a plurality of processors, wherein the plurality of processors comprises a first set of processors and a second set of processors,
wherein each processor of the first set of processors is configured to participate in a first barrier synchronisation enforced between a first synchronisation group comprising the first set of processors and a third set of processors belonging to a first further processing device, wherein the first barrier synchronisation separates a compute phase for the first synchronisation group from a first exchange phase for the first synchronisation group,
wherein each of at least some of the processors of the first set of processors is configured to, during the first exchange phase, exchange data with the third set of processors,
wherein each processor of the second set of processors is configured to participate in a second barrier synchronisation enforced between a second synchronisation group comprising the second set of processors and a fourth set of processors belonging to a second further processing device, wherein the second barrier synchronisation separates a compute phase for the second synchronisation group from a second exchange phase for the second synchronisation group,
wherein each of at least some of the processors of the second set of processors is configured to, during the second exchange phase, exchange data with the fourth set of processors,
wherein the first exchange phase overlaps in time with the second exchange phase, and
wherein the processing device comprises an external sync controller comprising circuitry configured to:
coordinate the first barrier synchronisation between processors of the first synchronisation group by exchanging first sync messages with the first further processing device; and
coordinate the second barrier synchronisation between processors of the second synchronisation group by exchanging second sync messages with the second further processing device.