Patent ID: 11882688
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. A semiconductor memory device comprising:
a substrate;
a plurality of lower electrodes on the substrate; and
a plurality of support patterns connected to the lower electrodes,
wherein the plurality of lower electrodes comprises a first lower electrode line and a second lower electrode line extending in a first direction,
wherein each of the first and second lower electrode lines are adjacent to each other in a second direction different from the first direction,
wherein one of the lower electrodes of the second lower electrode line is offset in the second direction with respect to one of the lower electrodes of the first lower electrode line, and
wherein the plurality of support patterns comprises a first support pattern line extending in a third direction different from the first direction and the second direction,
wherein respective subsets of lower electrodes consist of six edge lower electrodes arranged along a periphery of each of the support patterns at respective vertices of a hexagonal shape and free of electrodes between the respective vertices, and one center lower electrode that is centrally positioned within the periphery without electrodes between the central lower electrode and the edge lower electrodes, and wherein respective distances between the center lower electrode and each of the edge lower electrodes are the same.