Patent ID: 11894103
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 0:
1. An apparatus, comprising:
a first word line tile comprising a first plurality of word line plates stacked in a vertical direction, the first plurality of word line plates comprising a first word line plate that includes a plurality of first word lines in a first plane, each first word line of the plurality of first word lines coupled with one or more respective memory cells of a plurality of first memory cells;
a second word line tile comprising a second plurality of word line plates stacked in the vertical direction, the second plurality of word line plates comprising a second word line plate that includes a plurality of second word lines in the first plane, each second word line of the plurality of second word lines coupled with one or more respective memory cells of a plurality of second memory cells;
a first set of electrodes coupled with a first word line decoder and each coupled with a respective word line plate of the first plurality of word line plates, the first word line decoder operable to activate one of the first plurality of word line plates based at least in part on applying a first voltage to a respective electrode of the first set of electrodes;
a first electrode of the first set of electrodes that is coupled with the first word line plate, wherein the first word line decoder is operable to activate the first word line plate based at least in part on applying the first voltage to the first electrode;
a second set of electrodes coupled with a second word line decoder and each coupled with a respective word line plate of the second plurality of word line plates, the second word line decoder operable to activate one of the second plurality of word line plates based at least in part on applying a second voltage to a respective electrode of the second set of electrodes;
a first electrode of the second set of electrodes that is coupled with the second word line plate, wherein the second word line decoder is operable to activate the second word line plate based at least in part on applying the second voltage to the first electrode;
a plurality of first pillars extending through a stack of materials comprising the first word line plate and the second word line plate, each first pillar of the plurality of first pillars coupled with a respective memory cell of the plurality of first memory cells; and
a plurality of second pillars extending through the stack of materials, each second pillar of the plurality of second pillars coupled with a respective memory cell of the plurality of second memory cells;
wherein a first memory cell of the plurality of first memory cells and a second memory cell of the plurality of second memory cells are operable to be simultaneously accessed based at least in part on activating a first pillar of the plurality of first pillars, the first word line plate, a second pillar of the plurality of second pillars, and the second word line plate.