Patent ID: 11915736
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A memory system, comprising:
a plurality of memory cells arranged in rows and columns, each of the plurality of memory cells having a gate, a drain, a source, channel material situated adjacent the drain and the source, and ferroelectric material situated between the gate and the channel material;
a plurality of word lines, each of the word lines having a corresponding row, wherein each of the word lines is coupled to the gates of the memory cells in the corresponding row;
a plurality of bit lines and a plurality of source lines, each of the bit lines and each of the source lines having a corresponding column, wherein each of the bit lines is connected to the drain of the memory cells in the corresponding column and each of the source lines is connected to the source of the memory cells in the corresponding column;
wherein in a write operation, a first word line corresponding to a selected memory cell is configured to receive a first voltage, and a first bit line and a first source line of the selected memory cell are configured to receive a second voltage, and a second word line corresponding to an unselected memory cell is configured to receive a ground reference voltage, and a second bit line and a second source line of the unselected memory cell are configured to receive the second voltage; and
wherein one of the first voltage or the second voltage is a positive voltage and the other of the first voltage or the second voltage is a negative voltage.