Patent ID: 11907754
Assignee: MELLANOX TECHNOLOGIES, LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. The system according to claim 1, wherein:
the processing device includes a device clock;
the processing circuitry is configured to write the respective interrupt signaling messages to the memory over the interface responsively to respective hardware clock values of the hardware clock and a common schedule known to the processing device and the peripheral device;
the device processor is configured, responsively to the respective interrupt signaling messages being written to the memory, to:
retrieve respective device clock values from the device clock; and
find the respective hardware clock values at which the respective interrupt signaling messages were written to the memory responsively to the schedule; and
the device processor is configured to:
compute respective time differences between the retrieved respective device clock values and the found respective hardware clock values; and
discipline the device clock responsively to ones of the respective time differences.