Patent ID: 11923869
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 2:
3. The data storage device of claim 2, wherein the support circuitry further includes a re-organizer, and
wherein, to dynamically map the plurality of LDPC engines to the plurality of FCs, the support circuitry is further configured to:
dynamically allocate, with the dynamic allocator, the memory operations that are stored in the priority queue to the plurality of LDPC engines,
perform, with the plurality of LDPC engines, parity checking and error correction on the memory operations that have been dynamically allocated to the plurality of LDPC engines,
store, with the re-organizer, the memory operations that have been parity checked and error corrected in a plurality of memory buffers, each memory buffer corresponding to one of the plurality of FCs,
retrieve, with the each of the plurality of FCs, a memory operation that is stored in one of the plurality of memory buffers, and
perform, with the each of the plurality of FCs, the memory operation at the corresponding one of the plurality of memory dies.