Patent ID: 11948972
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 0:
1. A structure, comprising:
a substrate;
a stack of first and second nano-sheet layers disposed on the substrate, wherein the first and second nano-sheet layers are arranged in an alternating configuration, and wherein the first nano-sheet layers are narrower than the second nano-sheet layers;
an epitaxial structure abutting end-portions of the stack of first and second nano-sheet layers;
a spacer structure interposed between the first nano-sheet layers and the epitaxial structure;
a gate structure on a top surface and sidewall surfaces of the stack of first and second nano-sheet layers wherein the gate structure comprises:
a first dielectric disposed on a top surface of one of the second nano-sheet layers and in contact with the epitaxial structure, wherein sidewalls of the first dielectric are aligned with sidewalls of the one of the second nano-sheet layers; and
a second dielectric disposed on the first dielectric and thinner than the first dielectric; and

gate spacers disposed on and in contact with a top surface of the first dielectric.