Patent ID: 11900985
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A clock driver circuit comprising:
an internal clock generator circuit to receive an input clock from a source device, the input clock providing timing information associated with an input data signal, and the internal clock generator circuit to receive an internal clock control signal specifying a first selected reference edge of the input clock, and to generate an internal clock locked to the first selected reference edge of the input clock;
an output clock generator circuit to receive the input clock and an output clock control signal specifying a second selected reference edge of the input clock, and to generate an output clock locked to the second selected reference edge of the input clock, wherein the output clock has a predefined phase relationship to the input clock that is independent of the first and the second selected reference edges;
a sampling circuit to receive the input data signal from the source device and to sample the input data signal based on the internal clock to generate an output data signal; and
an output interface to output the output data signal and to output the output clock to a destination device, wherein the output clock provides timing information associated with the output data signal.