Patent ID: 11962676
Assignee: SYNOPSYS, INC.
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A method comprising:
receiving, at an input node, a first compensation value;
generating a first compensation signal based on the first compensation value by:
delaying, with a first delay element, the first compensation value; and
generating, with a summation element, a non-linearity signal from the first compensation value and the delayed first compensation value, wherein the first delay element is coupled between the input node and an input of the summation element and a second input of the summation element is coupled to the input node;

compensating for a first non-linearity within phase mixer (PMIX) circuitry based on the first compensation signal and a phase accumulator input update signal to generate a compensated signal; and
generating a clock signal based on the compensated signal by the PMIX circuitry.