Patent ID: 11864372
Assignee: LAM RESEARCH CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for reducing bending of word lines in a memory cell, comprising:
a) providing a substrate including a plurality of word lines arranged adjacent to one another and above a plurality of transistors;
b) depositing a layer of film on the plurality of word lines using a deposition process;
c) after depositing the layer of film, measuring word line bending;
d) comparing the word line bending to a threshold tolerance range;
e) based on the word line bending, adjusting at least one of nucleation delay and grain size of the deposition process; and
f) repeating b) to e) one or more times using one or more substrates, respectively, until the word line bending is within the threshold tolerance range.