Patent ID: 11862576
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A wafer chip scale package (WCSP) die, comprising:
a substrate having a semiconductor surface including circuitry,
a redistribution layer (RDL) above the semiconductor surface including a top metal layer above the semiconductor surface comprising top metal lines that are electrically connected through a metal stack including metal interconnects electrically connected to the circuitry, the top metal lines configured in a primary orientation that collectively represents at least 50% of a total length of all of the top metal lines in a first direction, the top metal layer including bond pads exposed from a passivation layer, and
metal features positioned in at least one of i) lateral to and not directly electrically connected to the top metal layer and ii) positioned on the passivation layer,
wherein at least a majority of a total area of the metal features is not over the metal interconnects, and
wherein the metal features have a length direction oriented in a second direction that is at least essentially perpendicular being in an angular range of 90° plus or minus 5° relative to the primary orientation.