Patent ID: 11967965
Assignee: SHAOXING YUANFANG SEMICONDUCTOR CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. A clock generation circuit for generating divided signals, said clock generating circuit comprising:
a phase locked loop (PLL) generating a PLL output having a frequency which is a desired multiple of that of a reference clock;
a divider circuit for dividing said PLL output by a respective divisor of a plurality of divisors to generate a corresponding divided signal of a plurality of divided signals, wherein said corresponding divided signal is offset from a common reference by at least an associated desired time offset; and
a multiplexer to select said reference clock or said time reference signal as said common reference in response to a select signal being in a first state or a second state respectively, wherein said select signal is in said first state when said reference clock is available and is in said second state when said reference clock is not available,
wherein said time reference signal is generated external to said reference clock.