Patent ID: 11908505
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 9:
10. A data processing device, comprising:
a plurality of wordlines (“WLs”);
a plurality of matchline-enable (“ML-enable”) lines;
a plurality of bitlines (“BLs”);
a plurality of selectlines (“SLs”);
a plurality of inputlines (“INs”);
a plurality of data storage units arranged logically in a plurality of rows and a plurality of columns, each of the rows of data storage units associated with a respective one of the WLs and respective one of the ML-enable lines, each of the columns of the data storage units being connected to a respective one of the BLs, a respective one of the SLs and a respective one of the INs, each of the data storage units comprising:
a matchline (“ML”) switching transistor having a gate, drain and source;
a ferroelectric field-effect transistor (“FeFET”) having a gate, drain and source; and
an input switching transistor having a gate, drain and source and being, with the drain connected to the source of the FeFET at a junction to form a serial combination between the input switching transistor and the FeFET, the gate of the FeFET being connected to the associated WL; a first end of the serial combination being connected to the associated BL; the junction between the input switching transistor and FeFET being connected to the associated SL; the gate of the input switch transistor being connected to the associated IN;

the ML switching transistors in each row of the data storage devices are connected to each other source-to-drain at the plurality of BLs, forming a matchline having an input end and an output end, the gates of the ML switching transistors in each row of the data storage devices are connected to the associated ML-enable line.