Patent ID: 11894381
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A semiconductor structure, comprising:
a substrate that includes:
a handle layer,
an insulation layer comprising silicon dioxide and arranged over the handle layer,
a buried layer arranged over the insulation layer, and
a plurality of trenches each of which extends downward from an upper surface of the buried layer and terminates in the handle layer,
wherein the buried layer is divided into a plurality of functional areas by the plurality of trenches;

a dielectric layer located on a bottom surface of each of the plurality of trenches and contacting the handle layer, wherein the dielectric layer comprises a first sub-layer and a second sub-layer;
a polysilicon region located in each of the plurality of trenches, wherein a first bottom surface and a first side surface of the polysilicon region contact the second sub-layer, wherein a second bottom surface and a second side surface of the second sub-layer contact the first sub-layer, and wherein a first top surface of the polysilicon region is lower than a second top surface of the first sub-layer and a third top surface of the second sub-layer; and
a plurality of transistors that are formed in the plurality of functional areas of the buried layer respectively and electrically connected through metal lines over the plurality of transistors during a charging process.