Patent ID: 11948888
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. A semiconductor device, comprising:
a semiconductor substrate including a first region and a second region;
a plurality of gate structures on the first region and the second region of the semiconductor substrate;
a plurality of metal contact patterns in a gap-fill insulation layer covering the plurality of gate structures, the plurality of metal contact patterns connected to the plurality of gate structures and a plurality of source/drain impurity layers;
an etch stop layer covering top surfaces of the plurality of metal contact patterns and including a sequentially stacked first insulation layer, second insulation layer, and third insulation layer;
a resistance structure on the etch stop layer on the second region;
an interlayer dielectric layer covering the resistance structure and the etch stop layer;
a buffer insulation layer between the resistance structure and the etch stop layer on the second region;
a first contact plug penetrating the interlayer dielectric layer and the etch stop layer and connected to at least one metal contact pattern of the plurality of metal contact patterns on the first region; and
a second contact plug penetrating the interlayer dielectric layer and connected to the resistance structure on the second region,
wherein:
the first insulation layer, second insulation layer, and third insulation layer include different insulating materials from each other,
the buffer insulation layer is spaced apart from the first contact plug,
the first insulation layer directly contacts top surfaces of the plurality or metal contact patterns and top surfaces of the plurality of gate structures, and
a thickness of the third insulation layer is greater than a thickness of the second insulation layer and a thickness of the first insulation layer.