Patent ID: 11869596
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 11:
12. The memory system of claim 11, wherein
the first memory cell is one of a plurality of first memory cells,
the plurality of first loops of the first programming operation includes a second loop and a third loop, the third loop being subsequent to the second loop, and
the peripheral circuit is further configured to:
apply the first program voltage to the plurality of first memory cells in the plurality of first loops of the first programming operation, a level of the first program voltage applied to the plurality of first memory cells in the third loop being higher than a level of the first program voltage applied to the plurality of first memory cells in the second loop; and
obtain the value of the first write parameter in one of the plurality of first loops in which a highest voltage of threshold voltage distribution of the plurality of first memory cells exceeds the second reference voltage.