Patent ID: 11955531
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A method of forming an integrated circuit device comprising:
forming a gate structure and a source/drain region on a substrate, wherein the source/drain region is on a first side of the gate structure;
forming an interlayer dielectric on the substrate to overlap the gate structure and the source/drain region;
forming a first contact hole that penetrates the interlayer dielectric to expose an upper surface of the source/drain region;
forming a first contact in the first contact hole, wherein the first contact is in contact with the upper surface of the source/drain region;
forming a contact capping layer on the first contact, the contact capping layer protruding outward with respect to a sidewall of the first contact;
forming a second contact hole penetrating the interlayer dielectric to expose an upper surface of the gate structure, wherein a sidewall of the contact capping layer is exposed to an inner wall of the second contact hole; and
forming a second contact in the second contact hole, wherein the second contact is in contact with the upper surface of the gate structure.