Patent ID: 11935612
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. The memory of claim 19, wherein the first writing circuit unit comprises:
a twenty-third transistor configured to enable a source to be electrically connected to the first voltage, and a drain to be electrically connected to the first data line;
a twenty-fourth transistor configured to enable a source to be grounded, and a drain to be electrically connected to each of the drain of the twenty-third transistor and the first data line;
a first NOR gate configured to enable an output end to be electrically connected to a gate of the twenty-third transistor;
a second NOR gate configured to enable an output end to be electrically connected to a gate of the twenty-fourth transistor;
a first NAND gate configured to enable an output end to be electrically connected to a first input end of the second NOR gate, a first input end to be electrically connected to the write enable signal, and a second input end to be electrically connected to the equalization signal;
a first AND gate configured to enable an output end to be electrically connected to a second input end of the first NOR gate, a first input end to be electrically connected to the write enable signal, and a second input end to be electrically connected to a second input end of the second NOR gate and the second data line; and
a first inverter configured to enable an output end to be electrically connected to a first input end of the first NOR gate, and an input end to be electrically connected to the equalization signal.