Patent ID: 11961777
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. The method of claim 15, wherein after performing the first planarization process the method further comprises:
forming an insulating layer on the first die, the second die, and the first encapsulant to fill in a plurality of pits in the first encapsulant;
performing a second planarization process to remove the insulating layer over the first encapsulant, so that a plurality of filling structures are formed in the first encapsulant;
forming a redistribution layer (RDL) structure on the first die, the second die, the first encapsulant, and the plurality of filling structures, wherein the plurality of filling structures are surrounded by the first encapsulant and the RDL structure; and
forming a plurality of conductive terminals electrically connected to the first die and the second die through the RDL structure.