Patent ID: 11968827
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of forming a three-dimensional memory device, comprising:
forming an alternating stack of insulating layers and sacrificial material layers over a substrate, wherein the sacrificial material layers comprise word-line-level sacrificial material layers and at least one drain-select-level sacrificial material layer that overlies the word-line-level sacrificial material layers;
forming drain-select-level openings vertically extending through the at least one drain-select-level sacrificial material layer;
replacing the at least one drain-select-level sacrificial material layer with at least one drain-select-level electrically conductive layer;
forming memory openings vertically extending through the at least one drain-select-level electrically conductive layer and the word-line-level sacrificial material layers by vertically extending the drain-select-level openings;
forming memory opening fill structures within the memory openings, wherein each of the memory opening fill structures comprises a memory film and a vertical semiconductor channel;
replacing the word-line-level sacrificial material layers with word-line-level electrically conductive layers;
forming drain-select-level isolation trenches and drain-select-level backside trenches through the at least one drain-select-level sacrificial material layer; and
forming drain-select-level isolation structures and drain-select-level dielectric rails in the drain-select-level isolation trenches and the drain-select-level backside trenches, respectively,
wherein the drain-select-level openings comprise sets of multiple rows of drain-select-level openings, wherein each set of multiple rows of drain-select-level openings is formed between a respective neighboring pair of the drain-select-level isolation structures and the drain-select-level dielectric rails.