Patent ID: 11929748
Assignee: STMICROELECTRONICS (GRENOBLE 2) SAS
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 11:
12. The device of claim 7, wherein,
the delay elements of the chain, when enabled, add a same delay time period to a received digital signal; and
the control circuitry comprises a frequency dividing circuit, which, in operation, enables the counter, and the control circuitry, in operation, generates a regulation control value H according to:, H
  =
  
   
    (
    
     Rf
     -
     M
    
    )
   
   ⁢
   
    
     (
     
      2
      *
      T_clk
      ⁢
      _ref
     
     )
    
    
     S
     *
     DIV, where:
Rf represents a number of rising edges of the reference clock signal during a sampling time period;
M represents a number of rising edges of the wobulated signal counted by the counter during the sampling time period;
S represents a duration of the delay time period of a delay element of the chain of delay elements;
T_clk_ref represents the period of reference signal Ref; and
DIV represents a number of rising edges measured by a frequency dividing circuit enabling the counter.