Patent ID: 11923864
Assignee: SHAOXING YUANFANG SEMICONDUCTOR CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A phase-locked loop (PLL) to generate an output clock locked to a first input clock at a frequency which is product of a first divisor and a frequency of said input clock in a normal mode of operation and to switch to a different frequency thereafter, wherein said different frequency is product of another divisor and said frequency of said input clock, said PLL comprising:
a first phase detector coupled to receive said first input clock on an input path and a feedback clock on a feedback path, said phase detector to generate an error signal representing a phase difference between said first input clock and said feedback clock;
a first low-pass filter with a first passband to generate a filtered error signal by filtering said error signal;
a first oscillator coupled to generate said output clock from said filtered error signal, wherein a frequency of said output clock is determined by a strength of said filtered error signal;
a first feedback divider to divide said output clock by said first divisor of a first value in said normal mode,
wherein said first phase detector, said first low-pass filter, said first oscillator and said first feedback divider together operate as a first PLL having a first bandwidth in generating said output clock,
wherein said first oscillator is implemented as a second PLL with a second bandwidth higher in magnitude compared to said first bandwidth, wherein said filtered error signal is provided as input signal to said second PLL and said second PLL provides said output clock,
wherein said first bandwidth is designed to cause said PLL to settle to said different frequency in a first duration upon a corresponding configuration change of said first PLL, but not that of said second PLL; and
a control unit to control operation of said first PLL and said second PLL, wherein to switch to said different frequency of said output clock said control unit changes, within an interval from each other less than said first duration, a configuration of each of said first PLL and said second PLL to generate said output clock at said different frequency,
wherein changing said configuration of said first PLL comprises operating said first feedback divider based on said another divisor and/or changing said frequency of said input clock to effectively provide said output clock with said different frequency,
wherein said output clock changes to operate at said different frequency in a second duration determined by said interval and the higher second bandwidth of said second PLL.