Patent ID: 11941397
Assignee: AMAZON TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A processor comprising:
a set of state registers to implement a workspace;
an instruction queue operable to store pending machine instructions; and
a processor execution unit operable to execute a set of machine instructions from the instruction queue to process a JPEG file, the set of machine instructions including:
a set of fuse input instructions to fuse multiple JPEG data blocks;
a first set of single instruction multiple data (SIMD) instructions to perform a column pass of a two-dimensional (2-D) inverse discrete cosine transform (IDCT) concurrently on the multiple JPEG data blocks;
a first set of vector-to-workspace instructions to move the multiple JPEG data blocks into the state registers;
a set of workspace-to-vector instructions to transpose the multiple JPEG data blocks from the state registers;
a second set of SIMD instructions to perform a row pass of the 2-D IDCT concurrently on the multiple JPEG data blocks;
a second set of vector-to-workspace instructions to move a result of the 2-D IDCT performed on the multiple JPEG data blocks into the state registers; and
a set of saturate-and-store instructions to store the result of the 2-D IDCT performed on the multiple JPEG data blocks from the state registers into memory.