Patent ID: 11929433
Assignee: GLOBALFOUNDRIES U.S. INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor device comprising:
an SOI layer above a substrate, the SOI layer comprising a source region, a channel region, a drift region and a drain region, wherein the drift region adjoins the drain region and the channel region;
the substrate comprising alternating first polarity and second polarity wells, the first polarity well is below the drain region and the drift region;
a gate structure on the channel region;
a multilayer source spacer on a source-facing sidewall of the gate structure, wherein the multilayer source spacer consists of a source spacer on the source-facing sidewall of the gate structure, and an outer spacer layer on the source spacer;
a multilayer drain spacer on a drain-facing sidewall of the gate structure, wherein the multilayer source spacer is shaped asymmetrically compared to the multilayer drain spacer, and wherein the multilayer drain spacer comprises at least three spacer layers overlying the drift region; and
the multilayer drain spacer covers the drift region.