Patent ID: 11916559
Assignee: SAMBANOVA SYSTEMS, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. The DLL of claim 1, wherein the retimer comprises:
a first flipflop with a D input coupled with the first retimer input, an inverting clock input coupled with the gater clock input, and a Q output;
a second flipflop with a D input coupled with the Q output of the first flipflop, an inverting clock input coupled with the gater clock input, and a Q output;
a third flipflop with a D input coupled with the Q output of the second flipflop, a clock input coupled with the gater clock input, and a Q output coupled with the first retimer output;
a fourth flipflop with a D-input coupled with the second retimer input, an inverting clock input coupled with the gater clock input, and a Q output;
a fifth flipflop with a D input coupled with the Q output of the fourth flipflop, an inverting clock input coupled with the gater clock input, and a Q output; and
a sixth flipflop with a D input coupled with the Q output of the fifth flipflop, a clock input coupled with the gater clock input, and a Q output coupled with the second retimer output.