Patent ID: 11894050
Assignee: QUALCOMM INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. A memory comprising:
a plurality of columns, each column in the plurality of columns including a pair of bit lines;
a sense amplifier including a pair of sense amplifier input nodes;
a read column multiplexer configured to select a selected column from the plurality of columns responsive to an assertion of a read multiplexer address signal to couple the pair of bit lines in the selected column to the pair of sense amplifier input nodes;
a self-timed memory circuit including a dummy bit line circuit configured to prevent the assertion of the read multiplexer address signal until an assertion of a dummy bit line circuit output signal; and
a first switch coupled between a node for the read multiplexer address signal and a power supply node, wherein the first switch is configured to open in response to the assertion of the dummy bit line circuit output signal.