Patent ID: 11908953
Assignee: WINBOND ELECTRONICS CORP.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A manufacturing method of a memory device, comprising:
forming a gate stacking structure over a substrate;
sequentially forming a first insulating layer, a second insulating layer and a mask material layer over the substrate to cover the gate stacking structure;
performing an ion implantation process on the mask material layer, to form a doped portion in the mask material layer, wherein the doped portion caps on a top portion of the gate stacking structure;
performing a first patterning process on the mask material layer by using the doped portion as a shadow mask, to remove a bottom portion of the mask material layer extending along a surface of the substrate; and
performing a second patterning process to remove the doped portion of the mask material layer and an exposed bottom portion of the second insulating layer surrounding the gate stacking structure, wherein a remained portion of the mask material layer forms a first spacer.