Patent ID: 11948616
Assignee: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 18:
19. The manufacturing method of a semiconductor structure according to claim 17, wherein while the first interconnecting hole and the eighth interconnecting hole are formed in the first dielectric layer, a ninth interconnecting hole is formed in the first dielectric layer, wherein the ninth interconnecting hole exposes the control terminal of the transistor;
while the first interconnecting structure is formed in the first interconnecting hole and the eighth interconnecting structure is formed in the eighth interconnecting hole, a ninth interconnecting structure is further formed in the ninth interconnecting hole; and
while the first conductor layer and the source line are formed on the upper surface of the first dielectric layer, a word line is further formed on the upper surface of the first dielectric layer, wherein the word line is connected to the control terminal of the transistor.