Patent ID: 11967622
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A method comprising:
forming a first insulating layer;
forming a first conductive feature in the first insulating layer, the first conductive feature having an upper surface level with an upper surface of the first insulating layer;
forming an inter block dielectric in the first conductive feature, the inter block dielectric having an upper surface level with the upper surface of the first conductive feature, the inter block dielectric having a bottom surface disposed between a bottom surface of the first conductive feature and the upper surface of the first conductive feature;
forming a second insulating layer over the first insulating layer;
forming a first contact in the second insulating layer, the first contact being electrically coupled to the first conductive feature; and
forming a second contact in the second insulating layer, the second contact being electrically coupled to the first conductive feature, wherein the inter block dielectric is laterally between the first contact and the second contact.