Patent ID: 11955487
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 9:
10. A semiconductor device, comprising:
a first channel pattern and a second channel pattern on a substrate, each of the first and second channel patterns including vertically-stacked semiconductor patterns;
a first source/drain pattern connected to the first channel pattern;
a second source/drain pattern connected to the second channel pattern, the first and second source/drain patterns having different conductivity types from each other;
a first contact plug inserted in the first source/drain pattern, and a second contact plug inserted in the second source/drain pattern;
a first interface layer interposed between the first source/drain pattern and the first contact plug; and
a second interface layer interposed between the second source/drain pattern and the second contact plug, a bottom portion of the second interface layer being positioned at a level that is lower than a bottom portion of the first interface layer,
wherein the first and second interface layers include different metallic elements from each other.