Patent ID: 11967526
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A method comprising:
forming a dielectric cap over a gate structure;
depositing a source/drain contact over a source/drain region adjacent to the gate structure;
after depositing the source/drain contact over the source/drain region, oxidizing a top of the source/drain contact and a top portion of the dielectric cap to form a metal-containing oxide region in the source/drain contact and an oxidized top portion in the dielectric cap while a bottom portion of the dielectric cap remains un-oxidized;
after oxidizing the top of the source/drain contact, forming an interlayer dielectric (ILD) layer covering the metal-containing oxide region of the source/drain contact;
forming a via opening in the ILD layer to expose the source/drain contact; and
filling a source/drain via in the via opening.