Patent ID: 11956946
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 12:
13. The method of forming the semiconductor structure according to claim 11, wherein the step of forming the bit line isolation layer covering the sidewalls of the diffusion barrier layer, the sidewalls of the bit line layer, the sidewalls and the top surface of the bit line cap layer, and the surface of the substrate isolation layer further comprises a step of:
depositing a first dielectric material on the sidewalls of the diffusion barrier layer, the sidewalls of the bit line layer, the sidewalls and the top surface of the bit line cap layer, and the surface of the substrate isolation layer to form a first sub-bit line isolation layer;
depositing a second dielectric material on a surface of the first sub-bit line isolation layer to form a second sub-bit line isolation layer; and
depositing a third dielectric material on a surface of the second sub-bit line isolation layer to form a third sub-bit line isolation layer.