Patent ID: 11942398
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A semiconductor device, comprising:
a circuit substrate, comprising a semiconductor substrate and a device layer over the semiconductor substrate;
a passivation layer, disposed over the device layer;
at least one through substrate via, passing through passivation layer, the device layer and the semiconductor substrate; and
a conductive layer, covering the passivation layer and an inner sidewall of the at least one through substrate via; and
an insulating liner, disposed between the conductive layer and the semiconductor substrate of the circuit substrate, wherein the insulating liner has a scallop-like sidewall facing the semiconductor substrate and a substantially smooth sidewall facing the conductive layer,
wherein an included angle between an upper opening of the inner sidewall of the at least one through substrate via and a bottom surface of the device layer is less than about 90 degrees.