Patent ID: 11887955
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. A method of forming a semiconductor structure including a semiconductor die, comprising:
forming dielectric material layers and metal interconnect structures over a semiconductor substrate, wherein the dielectric material layers comprise a pad-level dielectric material layer;
forming a connection via cavity through the pad-level dielectric material layer;
forming a connection pad-and-via structure over the dielectric material layers by depositing and patterning a metallic material having a thickness less than one half of a maximum lateral dimension of the connection via cavity in the connection via cavity and over the pad-level dielectric material layer, wherein a dimple that is not filled with the metallic material is formed within the connection via portion upon deposition of the metallic material, wherein the connection pad-and-via structure comprises a connection via portion that extends through the pad-level dielectric material layer and a pad portion that overlies the pad-level dielectric material layer;
forming a bump-level dielectric material layer over the connection pad-and-via structure, wherein the dimple is filled with a dielectric material of the bump-level dielectric material layer; and
forming a bump structure on the bump-level dielectric material layer, wherein the bump structure comprises a bump via portion extending through the bump-level dielectric material layer and contacting the pad portion and a bonding bump portion overlying the bump-level dielectric material layer, wherein a vertical axis passing through a geometrical center of the bump via portion is laterally offset from a vertical axis passing through a geometric center of the connection via portion of the connection pad-and-via structure.