Patent ID: 11935828
Assignee: STMICROELECTRONICS (ROUSSET) SAS
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An integrated circuit, comprising:
a semiconductor well;
an isolating region delimiting a working area of the semiconductor well;
a pair of trenches located in the working area, wherein each trench is filled by an electrically conductive central portion enclosed in an isolating enclosure;
a first doped region in a portion of the semiconductor well located between the pair of trenches;
a pair of strips overlying said pair of trenches, wherein each strip includes an electrically conductive layer insulated from a corresponding one of the trenches by a dielectric layer and a sidewall spacer, wherein the sidewall spacer extends over a side part of the portion of the semiconductor well located between the pair of trenches;
a layer of metal silicide located on the first doped region in the portion of the semiconductor well located between the pair of trenches which is not covered by the sidewall spacer;
a layer of metal silicide located on a part of the electrically conductive central portion;
a layer of metal silicide located on the electrically conductive layer;
a first electrical contact to said layer of metal silicide located on the first doped region forming a first electrode of a filler capacitor cell device; and
a second electrical contact to said layer of metal silicide located on the part of the electrically conductive central portion and on the electrically conductive layer forming a second electrode of the filler capacitor cell device.