Patent ID: 11948830
Assignee: QORVO US, INC.
Field: nan (nan)
Classification: CPC nan | IPC H

Claim 4:
5. The apparatus of claim 4 wherein:
the first active section is configured to provide a first NFET, and includes a first P-well with a first N-source and a first N-drain inside;
the second active section is configured to provide a second NFET and includes a second P-well with a second N-source and a second N-drain inside;
the first active section and the second active section are encapsulated and separated by the isolation portion; and
the contact layer includes a first gate structure extending from underneath the first N-source to underneath the first N-drain, a first source contact connected to the first N-source, a first drain contact connected to the first N-drain, a first gate contact connected to the first gate structure, a second gate structure extending from underneath the second N-source to underneath the second N-drain, a second source contact connected to the second N-source, a second drain contact connected to the second N-drain, and a second gate contact connected to the second gate structure, wherein the first N-source contact is electrically coupled to the second N-drain contact by one of the plurality of connecting layers and vias.