Patent ID: 11961557
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. The memory device of claim 8, wherein:
the first variable resistance includes:
a plurality of first transistors coupled in series between the first sub-interconnect and the second sub-interconnect;
a first switch coupled between the first sub-interconnect and the second sub-interconnect; and
a plurality of second switches each of which is coupled between the first sub-interconnect and a node to which two of the first transistors are coupled; and

the second variable resistance includes:
a plurality of second transistors coupled in series between the third sub-interconnect and the fourth sub-interconnect;
a third switch coupled between the third sub-interconnect and the fourth sub-interconnect; and
a plurality of fourth switches each of which is coupled between the third sub-interconnect and a node to which two of the second transistors are coupled.