Patent ID: 11960437
Assignee: T-HEAD (SHANGHAI) SEMICONDUCTOR CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 14:
15. A system, comprising:
a first set of parallel processing units (PPUs) included in a first compute node, wherein respective PPUs included in the first set of PPUs are included in separate respective chips;
a second set of parallel processing units (PPUs) included in a second compute node, wherein respective PPUs included in the second set of PPUs are included in separate respective chips; and
a plurality of interconnects in an inter-chip network (ICN) configured to communicatively couple the first set of PPUs and the second set of PPUs, wherein PPUs included in the first set of PPUs and the second set of PPUs communicate over the plurality of interconnects and corresponding communications are configured in accordance with routing tables that reside in storage features of respective ones of the PPUs included in the first set of PPUs and the second set of PPUs,
wherein the plurality of interconnects are configured to couple parallel communications from a first PPU in said first compute node to a second PPU in said second compute node over at least two paths, and
wherein balanced workloads are provided by multi-flow through minimal links and interleaving with flow ID and source parallel processing unit (PPU) ID.