Patent ID: 11955161
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 20:
21. An integrated-circuit memory control component (“memory control IC”) comprising:
a first clock output to output a command/address clock signal to an integrated-circuit memory component (“memory IC”);
a second clock output to output a data clock signal to the memory IC, the data clock signal having a frequency at least twice the frequency of the command/address clock signal; and
control circuitry to implement, by programming a first control value within a register of the memory IC, a configuration of the memory IC in which;
(i) distribution of the data clock signal within the memory IC is disabled for a power down event; and
(ii) distribution of the data clock signal within the memory IC is re-enabled in response to receipt of a read command; and

a receiver circuit to receive data from the memory IC, the data output by the memory IC in response to the read command.