Patent ID: 11907630
Assignee: SYNOPSYS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A method for performing power validation on an integrated circuit (IC) design based on a power assertion specification, the IC design being represented by a netlist that includes a subset of design signals in the IC design, the method comprising:
receiving, by a processor, the power assertion specification for the IC design, the power assertion specification including a predicted power consumption;
executing simulation of the IC design using the netlist to output waveforms for the subset of design signals;
reconstructing signals in the IC design that are not in the subset of design signals, using the output waveforms for the subset of design signals;
calculating a toggle rate of the reconstructed signals during the reconstructing of the signals, for a subset of the power assertions specified in the power assertion specification for the reconstructed signals;
comparing the calculated toggle rate of the reconstructed signals against a predicted toggle rate of the reconstructed signals for the subset of the power assertions specified during the reconstructing of the signals;
determining that the IC design is associated with a first power assertion failure based on results of the comparing the calculated toggle rate of the reconstructed signals against a predicted toggle rate of the reconstructed signals;
estimating, by the processor, power consumption of the IC design according to power assertions specified in the power assertion specification for the IC design;
comparing, by the processor, the estimated power consumption against the predicted power consumption included in the power assertion specification for the IC design;
determining, by the processor, that the IC design is associated with a second power assertion failure based on results of the comparing the estimated power consumption against the predicted power consumption; and
in response to determining that the IC design is associated with one or more of the first and the second power assertion failures, refining, by the processor, the IC design to remedy the one or more of the first and the second power assertion failures.