Patent ID: 11934696
Assignee: MICROCHIP TECHNOLOGY INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A flash controller including a write circuit, a decode circuit coupled to the write circuit, a program circuit and an erase circuit, the flash controller comprising:
a neural network engine;
an input and output (I/O) circuit to receive a configuration file for a Quality of Service (QoS) neural network, the configuration file including weight and bias values for the QoS neural network; and
a control circuit to load the configuration file of the QoS neural network into the neural network engine, to identify feature values corresponding to commands in one or more instruction queues and to load the identified feature values into the neural network engine,
the neural network engine to perform a neural network operation of the QoS neural network to predict latency of a current command, using as input to the neural network operation the identified feature values, wherein the predicted latency of the current command is the latency to complete the current command and includes the latency for performing all commands in the one or more instruction queues that are scheduled to be performed prior to the current command,
the control circuit to compare the predicted latency to a first latency threshold, and when the predicted latency of the current command exceeds the first latency threshold
the control circuit to identify a potential change to the commands in the one or more instruction queues the potential change defining a plurality of potential-commands,
the control circuit to generate potential-command feature sets corresponding to respective potential-commands,
the neural network engine to perform neural network operations using as input to the respective neural network operations feature values of the generated potential-command feature sets to predict a respective potential-latency of the respective potential-commands,
the control circuit to compare the predicted respective potential-latency of the respective potential-commands of to a second latency threshold to identify a reduced-noise-instruction-queue pattern, and
the control circuit to modify one or more of the commands in the one or more instruction queues or change a scheduling order in the one or more instruction queues to correspond to the reduced-noise-instruction-queue pattern;

the control circuit to not modify one or more of the commands in the one or more instruction queues when the predicted latency of the current command does not exceed the first latency threshold; and
one of the write circuit, the program circuit and the erase circuit to perform a next command in the one or more instruction queues.