Patent ID: 11910667
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 16:
17. The method of claim 16, further comprising,
providing a transistor on the substrate, wherein the transistor includes a semiconductor layer including a channel region, a source region and a drain region, a gate insulation layer formed on the semiconductor layer, a gate electrode formed on the gate insulation layer, an insulation interlayer formed on the gate electrode, wherein a first contact hole is formed through the insulation interlayer to overlap the source region and a second contact hole is formed through the insulation interlayer to overlap the drain region, a source electrode formed on the insulation interlayer and connected to the source region, and a drain electrode formed on the insulation interlayer and connected to the drain region,
wherein the source electrode, the drain electrode, the first pad and the second pad are simultaneously formed with each other.