Patent ID: 11908365
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 4:
5. A display device, comprising:
a display area including pixels connected to data lines and scan lines, wherein the display area includes a plurality of signal output lines connected to each of the scan lines through a plurality of contacts;
a data driver including a first data driving circuit disposed at a side of the display area to drive the data lines;
a scan driver disposed at the side of the display area to drive the scan lines; and
a timing controller for controlling the data driver and the scan driver,
wherein the display area includes first to third pixel blocks continuous in a first direction, and
each of the first to third pixel blocks includes first to k-th (where k is an integer greater than 2) data lines included in a driving region,
wherein the first data driving circuit comprises;
output buffers which respectively output data signals to the first to k-th data lines of the data lines; and
an output delay controller which transmits the data signals to the output buffers through first to k-th transmission lines, and controls delay times of the data signals output to the first to k-th transmission lines based on position information of a pixel row to which the data signals are to be supplied and a positional relationship between the contacts and the first to K-th data lines,
wherein the delay times increase in the first direction away from the contacts in the driving region or increase in a direction opposite the first direction away from the contacts in the driving region,
wherein times at which the data signals are output from the output buffers to the first to k-th data lines are respectively adjusted based on the delay times, and
wherein the output delay controller comprises:
a clock frequency divider which divides a frequency of a data transmission clock supplied from the timing controller to generate a reference clock;
a reference period generator which generates reference periods for delaying an output of the data signals based on a period of the reference clock;
a minimum delay selector which selects one of the reference periods as a minimum delay value based on the position information of the pixel row to which the data signals are to be supplied; and
a delay time determiner which determines the delay times based on the minimum delay value and a delay control signal, and delays and outputs the data signals by the delay times.