Patent ID: 11935616
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 8:
9. The comparison system of claim 1, wherein the second comparison module comprises:
a plurality of third comparison units, each configured to, during the read operation of the memory system, receive and compare a third subset of the N data in each of the M bytes, and output a first updated check code, wherein the third subset of the N data received by each of the third comparison units are from a respective different combination of bits in the M bytes;
a plurality of fourth comparison units, each configured to, during the read operation of the memory system, receive and compare all data in a fourth subset of the M bytes, and output a second updated check code, wherein the data received by each of the fourth comparison units are from a respective different subset of the M bytes;
a plurality of fifth comparison units, each configured to take a respective one of the X first check codes as the first signal and a respective one of the first updated check codes as the third signal, and output a respective one of the X first operation codes; and
a plurality of sixth comparison units, each configured to take a respective one of the Y second check codes as the first signal and a respective one of the second updated check codes as the third signal, and output a respective one of the Y second operation codes.