Patent ID: 11940922
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A high-bandwidth memory (HBM), the HBM comprising:
a DRAM; and
a logic component, comprising: a controller, an Arithmetic Logic Unit (ALU), and a SRAM configured as a scratchpad, wherein the logic component is configured to execute instructions that cause the logic component to:
coordinate the execution of an atomic operation of a FIM instruction received from an HBM memory controller of a processor, by the logic component using at least one of the DRAM, the controller, the ALU, or the SRAM, based on the FIM instruction, wherein the FIM instruction comprises the atomic operation and a FIM designator that identifies the FIM instruction as FIM, the atomic operation being generated by the processor by merging a first instruction of a first type and a second instruction of a second type into an atomic instruction.