Patent ID: 11860795
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 5:
6. An apparatus comprising:
a Memory Protection Unit (MPU) associated with a Random Access Memory (RAM) memory unit;
wherein the MPU is to enable access of an executable code during its runtime, only to an allowed portion of said RAM memory unit, the allowed portion being a part of the RAM memory unit;
wherein the MPU is to prevent access of said executable code during its runtime, to a forbidden portion of said RAM memory unit, said forbidden portion comprising all memory space that is not in said allowed portion, the forbidden portion being a blocked part of the RAM memory unit; and
an Iterative Memory-Boundaries Configurator unit, to iteratively modify a configuration of said MPU, by modifying in each iteration the size of the allowed portion of RAM that would be available to said executable code during runtime such that the blocked part of the RAM memory unit of the forbidden portion changes in size for each iteration.