Patent ID: 11963368
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 15:
16. A memory device, comprising:
a dielectric fin formed over a substrate, the dielectric fin having a first side surface and a second side surface opposite the first side surface;
a first memory cell disposed along and directly contacting a first flat surface of the first side surface of the dielectric fin, the first memory cell comprising: a first lower conductor layer, a first selector layer, a first resistive material layer, and a first upper conductor layer, wherein each of the first lower conductor layer, the first selector layer, the first resistive material layer, and the first upper conductor layer directly contact the first flat surface of the first side surface, wherein lower and upper boundaries of the first selector layer are each tilted away from the first flat surface by an angle, wherein the angle is less than 90 degrees; and
a second memory cell disposed along and directly contacting a second flat surface of the second side surface of the dielectric fin, the second memory cell comprising: a second lower conductor layer, a second selector layer, a second resistive material layer, and a second upper conductor layer, wherein each of the second lower conductor layer, the second selector layer, the second resistive material layer, and the second upper conductor layer directly contact the second flat surface of the second side surface; and
a capping layer disposed along and directly contacting each of the first lower conductor layer, the selector layer, the resistive material layer, and the first upper conductor layer such that the first memory cell is disposed directly between the capping layer and the dielectric fin.