Patent ID: 11948829
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A device structure, comprising:
a substrate comprising an n-type well region and a p-type well region;
a first fin and a second fin disposed over the n-type well region, wherein a bottom portion of the first fin comprises an n-type doped region, and a top portion of the first fin comprises a p-type doped region and in direct contact with the bottom portion of the first fin;
a third fin and a fourth fin disposed over the p-type well region, the third fin being closer to the second fin than the first fin, wherein a bottom portion of the third fin comprises a p-type doped region, and a top portion of the third fin comprises an n-type doped region and in direct contact with the bottom portion of the third fin;
a first gate structure wrapping over the top portion of the first fin;
a second gate structure wrapping over the top portion of the third fin, the second gate structure being isolated from the first gate structure;
a fin isolation feature extending from the bottom portion of the first fin to the bottom portion of the third fin, wherein a top surface of the fin isolation feature is even with an interface between the bottom portion of the first fin and the top portion of the first fin and an interface between the bottom portion of the third fin and the top portion of the third fin; and
a well isolation feature disposed below the fin isolation feature,
wherein the well isolation feature extends into the substrate and spans over an interface between the n-type well region and the p-type well region.