Patent ID: 11950412
Assignee: LONGITUDE FLASH MEMORY SOLUTIONS LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A NAND flash memory device comprising:
a plurality of NAND strings of memory transistors, the plurality of NAND strings of memory transistors comprising a first NAND string of memory transistors; and
a source select line;
the first NAND string of memory transistors comprising a base layer, a source select transistor, a first memory transistor, and a second memory transistor;
the first memory transistor comprising:
a first gate electrode; and
a first charge trapping layer disposed between the base layer and the first gate electrode; and
the second memory transistor comprising:
a second gate electrode; and
a second charge trapping layer disposed between the base layer and the second gate electrode;

the source select transistor electrically connected to the source select line comprising:
a source select gate electrode; and
a source select charge trapping layer disposed between the base layer and the source select gate electrode;

wherein the source select transistor is at one end of the first NAND string of memory transistors, the first memory transistor is adjacent to the source select transistor and the second memory transistor is adjacent to the first memory transistor;
wherein the first memory transistor and second memory transistor are separated by a first distance, which defines a first region;
wherein there is no diffusion region in the first region defined by the first distance;
wherein a conductive path is formed in the first region between the first and second memory transistors due to gate fringing field effects associated with the first and second memory transistors;
wherein the first memory transistor does not include a diffusion region for source and/or drain;
wherein the second memory transistor does not include a diffusion region for source and/or drain;
wherein the first memory transistor and the source select transistor are separated by a second distance, which defines a second region;
wherein there is no diffusion region in the second region defined by the second distance;
wherein a conductive path is formed in the second region between the first memory transistor and the source select transistor due to gate fringing field effects associated with the first memory transistor and the source select transistor; and
wherein the source select transistor does not include a diffusion region for source and/or drain.