Patent ID: 11916077
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A method, comprising:
routing a first reference metal line to couple to a first source/drain terminal of a first fin field effect transistor (finFET) with a first gate terminal, the first source/drain terminal, and a second source/drain terminal;
routing a second reference metal line to couple to a third source/drain terminal of a second finFET with a second gate terminal, the third source/drain terminal, and a fourth source/drain terminal;
routing a local interconnect structure to the first and second gate terminals;
routing, through the first reference metal line, a first interconnect structure to the second source/drain terminal;
routing, through the second reference metal line, a second interconnect structure to the third source/drain terminal;
routing, at a same interconnect level as the first and second interconnect structures, a third interconnect structure,
wherein the local interconnect structure, the first reference metal line, and the second reference metal line are routed at a first interconnect level, and
wherein the first interconnect structure, the second interconnect structure, and the third interconnect structure are routed at a second interconnect level.