Patent ID: 11862571
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A semiconductor package, comprising:
a lower semiconductor package; and
an upper semiconductor package on the lower semiconductor package;
wherein the lower semiconductor package includes:
a lower redistribution layer,
a lower semiconductor chip on the lower redistribution layer,
a capping insulation layer covering an upper surface and a side surface of the lower semiconductor chip,
a shielding layer covering an upper surface and a side surface of the capping insulation layer,
a lower mold layer covering an upper surface and a side surface of the shielding layer,
an upper redistribution layer on the lower mold layer, and
through-vias penetrating the lower mold layer and connecting the lower redistribution layer and the upper redistribution layer,

wherein the upper semiconductor package includes:
an upper package substrate,
an upper semiconductor chip on the upper package substrate, and
an upper mold layer covering the upper package substrate and the upper semiconductor chip,

wherein the capping insulation layer and the lower mold layer include an insulating material, and the shielding layer includes a metal material,
wherein the capping insulation layer and the shielding layer are spaced apart from the lower redistribution layer, and
wherein the lower mold layer is in contact with the lower redistribution layer.