Patent ID: 11875847
Assignee: STMICROELECTRONICS (ROUSSET) SAS
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. A memory circuit, comprising:
an array of memory cells arranged into bit lines and word lines;
a first reference word line comprised of a first series of reference bit cells set to a first alternating pattern of high resistance and low resistance states;
a second reference word line comprised of a second series of reference bit cells set to a second alternating pattern of high resistance and low resistance states;
a word line multiplexer having two inputs, and having a different output coupled to each different word line of the array of memory cells, wherein the word line multiplexer is controlled by a decoded word line address;
a first voltage regulator generating a first voltage as being equal to a regulated full voltage, the first voltage regulator being coupled to the first input of the word line multiplexer to provide the first voltage thereto;
a second voltage regulator generating a second voltage as being equal to a regulated fractional voltage, the second voltage regulator being coupled to the second input of the word line multiplexer to provide the second voltage thereto;
a bit line multiplexer having two inputs, and having a different output coupled to each different bit line of the array of memory cells, wherein the bit line multiplexer is controlled by a decoded bit line address;
wherein a first input of the bit line multiplexer is coupled to receive the second voltage, and wherein a second input of the bit line multiplexer is coupled to a sense amplifier;
wherein the sense amplifier comprises:
a regulation circuit configured to receive as input an input voltage from a bit line of a selected cell of the array of memory cells, a full read voltage from reading of the selected cell, and a fractional read voltage from unselected cells of the array of memory cells, the regulation circuit configured to generate the regulated voltage and the regulated fractional voltage based upon the input, wherein the regulated voltage and the regulated fractional voltage are used in reading of the selected cell of the array of memory cells;
a capacitor circuit configured to generate a reference voltage through charge sharing between an input capacitor and a reference capacitor; and
a comparator circuit configured to generate a data output signal based upon a comparison between the reference voltage and the input voltage.