Patent ID: 11899940
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. Apparatus to perform data processing operations, the data processing operations comprising loading data items from a memory system, the apparatus comprising:
address generation circuitry to generate addresses for load requests;
pending load buffer circuitry to buffer the load requests received from the address generation circuitry prior to the load requests being carried out to retrieve data items using the addresses of the load requests;
load handling circuitry responsive to a load request to retrieve from the memory system a series of data items comprising the data item identified by the load request;
coalescing circuitry to forward the load request buffered in the pending load buffer circuitry to the load handling circuitry and arranged to determine for a set of one or more subsequent load requests buffered in the pending load buffer circuitry whether an address proximity condition is satisfied,
wherein the address proximity condition is satisfied when all data items identified by the set of one or more subsequent load requests are comprised within the series of data items,
and wherein the coalescing circuitry is responsive to the address proximity condition being satisfied to suppress forwarding of the set of one or more subsequent load requests; and
decoalescing circuitry to receive the series of data items retrieved by the load handling circuitry and to return as the result of the load request the data item identified by the load request,
wherein the decoalescing circuitry is responsive to the address proximity condition being satisfied to return, for each of the subsequent load requests in the set of one or more subsequent load requests, one or more further data items identified by the one or more subsequent load requests from the series of data items as the results of the one or more subsequent load requests.