Patent ID: 11922131
Assignee: APPLIED MATERIALS, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 7:
8. A vector-matrix multiplier circuit, comprising:
a plurality of digital inputs, wherein each digital input receives a binary-encoded input value of an input vector;
a plurality of one-bit digital to analog converters (DACs), wherein:
each one-bit DAC is connected with a corresponding digital input of the plurality of digital inputs; and
each one-bit DAC outputs a binary-encoded analog signal for the corresponding digital input;

an analog vector matrix multiplier circuit that performs binary-encoded vector multiplication operations on a single bit-order at a time, wherein the analog vector matrix multiplier circuit receives the binary-encoded analog signal from each one-bit DAC of the plurality of one-bit DACs and generate analog outputs corresponding to the single bit-orders;
an analog-to-digital converter (ADC) that generates binary partial output vectors from the analog outputs; and
a binary-weighted summation circuit that combines the binary partial output vectors to generate a result for the vector-matrix multiplier circuit.