Patent ID: 11862721
Assignee: INNOSCIENCE (SUZHOU) TECHNOLOGY CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. The semiconductor device of claim 8, further comprising:
a plurality of first vias penetrating the first passivation layer to respectively connect to the S/D electrodes and the gate electrode;
a first patterned conductive layer on the first passivation layer and in contact with the first vias, respectively; and
a second passivation layer disposed on the first passivation layer and covering the metal lines;
a plurality of second vias penetrating the second passivation layer to connect to the first patterned conductive layer;
a second patterned conductive layer disposed on the second passivation layer and covering the second vias, wherein the conformal passivation layer extends downwardly from the position above the second patterned conductive layer.