Patent ID: 11955931
Assignee: MURATA MANUFACTURING CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A power amplifier unit comprising:
a power amplifier circuit that has a first input terminal and a first output terminal, the power amplifier circuit being configured to amplify a first radio-frequency signal containing a fundamental and input to the first input terminal and output a second radio-frequency signal containing a fundamental, an even-ordered harmonic, and an odd-ordered harmonic from the first output terminal;
a first impedance matching circuit that has a second input terminal and a second output terminal, the second input terminal being connected to the first output terminal of the power amplifier circuit, and the first impedance matching circuit being configured to output the second radio-frequency signal, input to the second input terminal, from the second output terminal as a third radio-frequency signal and converts an impedance between the second input terminal and the second output terminal;
a band select switch that has a fifth input terminal and a plurality of fifth output terminals, the fifth input terminal being connected to an output terminal of the first impedance matching circuit, and the band select switch being configured to select a propagation path of the third radio-frequency signal by connecting the fifth input terminal to at least one of the fifth output terminals in accordance with the frequency of the fundamental contained in the third radio-frequency signal;
a plurality of harmonic termination circuits respectively in association with the plurality of fifth output terminals of the band select switch, each of the plurality of harmonic termination circuits having a third input terminal and a third output terminal, the third input terminal being connected to an associated one of the third output terminals, each of the plurality of harmonic termination circuits being configured to reflect at least part of the even-ordered harmonic and the odd-ordered harmonic contained in the third radio-frequency signal input to the fifth input terminal to output the at least part of the even-ordered harmonic and the odd-ordered harmonic from the third input terminal as a fourth radio-frequency signal and outputs a fifth radio-frequency signal, containing the fundamental and the remainder of the even-ordered harmonic and the odd-ordered harmonic, from the third output terminal;
a plurality of filters respectively in association with the plurality of harmonic termination circuits, each of the plurality of filters having a fourth input terminal and a fourth output terminal, the fourth input terminal being connected to the third output terminal of an associated one of the harmonic termination circuits, each of the plurality of filters being configured to attenuate at least part of the even-ordered harmonic and the odd-ordered harmonic input to the fourth input terminal and contained in the fifth radio-frequency signal and outputs a sixth radio-frequency signal, containing the fundamental and the remainder of the even-ordered harmonic and the odd-ordered harmonic, from the fourth output terminal; and
a plurality of duplexers respectively in association with the plurality of filters, each of the duplexers having a seventh input terminal, a seventh output terminal, and an input/output terminal, the seventh input terminal being connected to the fourth output terminal of an associated one of the second impedance matching circuits, an eighth radio-frequency signal being output from the input/output terminal in accordance with the frequency of the sixth radio-frequency signal input to the seventh input terminal, and a tenth radio-frequency signal being output from the seventh output terminal in accordance with the frequency of a ninth radio-frequency signal input to the input/output terminal,
wherein
the fourth radio-frequency signal contains at least a second-order harmonic,
the second-order harmonic reaches the first output terminal of the power amplifier circuit with a first phase via the first impedance matching circuit,
each of the plurality of harmonic termination circuits is configured to operate at a different frequency, and each of the plurality of filters is configured to operate at a different frequency, and
each of the plurality of duplexers is configured to operate at a different frequency.