Patent ID: 11869572
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A device, comprising:
a memory array that operates with an applied core voltage;
a power gating circuit having only one power gating switch with a single transistor coupled in series between a core supply voltage and the memory array, wherein the single transistor receives the core supply voltage and provides the applied core voltage to the memory array, and wherein the single transistor has a single gate, and wherein the core supply voltage refers to a positive supply voltage; and
a biasing stage having a plurality of transistors arranged and coupled together to receive the applied core voltage from the single transistor and then selectively activate the single transistor by applying a feedback signal to the single gate of the single transistor based on sensing a changing voltage level of the applied core voltage,
wherein the biasing stage uses a leakage current drawn from a settled voltage level of the core supply voltage as a reference current to bias the biasing stage itself for regulating the applied core voltage without comparing the applied core voltage with an additional reference voltage.