Patent ID: 11955292
Assignee: WINBOND ELECTRONICS CORP.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A fabricating method of a parallel-connected capacitor structure, comprising:
providing a substrate;
forming a trench in the substrate, wherein an entirety of a sidewall of the trench is perpendicular to a top surface of the substrate;
forming a dielectric layer physically contacting a bottom and the sidewall of the trench;
performing a plurality of electroplating processes to form a plurality of electrode layers filling in the trench, wherein the plurality of electrode layers are independently formed by material selected from a group consisting of copper, tungsten, tantalum and Cu-Al alloy and wherein the steps of forming plurality of electrode layers comprise:
performing an nth electroplating process to form an nth electrode layer filling in and conformally covering the trench, wherein n is a positive integer from 1 to M, M is not less than 3, the nth electroplating process is performed from n equaling 1 to n equaling M, and an Mth electrode layer fills up a center of the trench;

after each of the nth electroplating process, forming a capacitor dielectric layer covering and contacting the nth electrode layer; and
forming a first conductive plug and a second conductive plug, wherein the first conductive plug contacting the nth electrode layer of the plurality of nth electrode layers with odd-numbered n, and the second conductive plug contacting the nth electrode layer of the plurality of nth electrode layers with even-numbered n, and wherein the first conductive plug and the second conductive plug are electrically connected to different conductive terminals.