Patent ID: 11908524
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. An apparatus comprising:
a memory die comprising a first memory cell; and
a controller connected to the memory die, the controller configured to:
apply a plurality of programming pulses to the first memory cell;
apply a plurality of first verify pulses to the first memory cell;
determine from the first verify pulses that the first memory cell has been programmed to a first programmed memory state;
apply a single second verify pulse to the first memory cell after determining that the first memory cell has been programmed to the first programmed memory state;
determine from the single second verify pulse that the first memory cell is no longer programmed to the first programmed memory state; and
apply an additional programming pulse to the first memory cell.