Patent ID: 11923024
Assignee: GLOBALFOUNDRIES U.S. INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A level-sensitive register unit, comprising:
a data latch for receiving data;
a flip-flop including a first latch and a second latch, wherein an output of the data latch is coupled to an input of the first latch of the flip-flop;
a first clock signal coupled to the data latch; and
a second clock signal, wherein a frequency of the first clock signal is 2× a frequency of the second clock signal,
wherein the second latch of the flip-flop is clocked by the second clock signal, and wherein the first latch of the flip-flop is clocked by an inverse of the second clock signal.