Patent ID: 11874897
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A device, comprising:
a set of computing logic having processing units configured to perform at least computations on matrix operands;
random access memory coupled to the set of computing logic and configured to store instructions executable by the set of computing logic and store matrices of an artificial neural network;
an interface operatable in a connection to a memory controller external to the device and distinct from the set of computing logic, the interface configured to facilitate access to the random access memory by the memory controller;
an integrated circuit package configured to enclose the device; and
a set of connectors configured to couple the interface to the memory controller located outside of the integrated circuit package;
wherein in response to an indication provided in the random access memory, the set of computing logic is configured to execute the instructions to apply a first input that is stored in the random access memory to the artificial neural network, generate a first output from the artificial neural network, and store the first output in the random access memory; and
wherein the processing units include a first unit configured to perform computations on two matrix operands of an instruction.