Patent ID: 11966287
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A memory device, comprising:
one or more memory arrays comprising a plurality of rows; and
one or more processors coupled with the one or more memory arrays and configured to cause the memory device to:
initiate a scrub operation on the plurality of rows;
determine whether to perform the initiated scrub operation using a first error control mode associated with correcting single-bit errors or using a second error control mode associated with correcting single-bit errors and detecting multiple-bit errors; and
perform the scrub operation based at least in part on determining to perform the scrub operation using the second error control mode, wherein to perform the scrub operation the one or more processors are configured to cause the memory device to:
read data and a first quantity of bits of error control information from each of the plurality of rows;
read a second quantity of bits of the error control information from a partition storing the error control information; and
compare bits of second error control information associated with data stored in each row with the first quantity of bits and the second quantity of bits of the error control information for the row to correct single-bit errors and detect multiple-bit errors in the data of each row.