Patent ID: 11908757
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A chip package structure, comprising:
at least one semiconductor die attached to a redistribution structure;
a first underfill material portion laterally surrounding a portion of the at least one semiconductor die;
a molding compound laterally surrounding at least one semiconductor die;
a package substrate attached to the redistribution structure; and
a second underfill material portion comprising:
an inter-substrate underfill portion laterally surrounding the redistribution structure and located within an outer periphery of the molding compound in a plan view, and

a peripheral material portion located outside the outer periphery of the molding compound in the plan view and comprising at least one cut region having an L-shaped vertical cross-sectional shape, wherein each of the at least one cut region has a vertically-extending portion having a uniform lateral width and a horizontally-extending portion wherein:
the molding compound has a rectangular outer periphery in the plan view; and
the at least one cut region comprises four cut regions located outside, and in proximity to, four corners of the rectangular outer periphery.