Patent ID: 11967352
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device, comprising:
a memory cell array including a plurality of memory cell rows;
a plurality of connectors for connecting the memory device to a device outside of the memory device;
a control logic circuit configured to perform a row operation, a write operation, a read operation, or a pre-charge operation on the plurality of memory cell rows in response to an active command, a write command, a read command, or a pre-charge command received from the outside; and
an input and output circuit configured to transmit data according to the write operation or the read operation to the plurality of connectors,
wherein the control logic circuit is further configured to: calculate a first count value by counting the active command and a second count value by counting the write command or the read command, with respect to a first memory cell row from among the plurality of memory cell rows, during a row hammer monitor time frame; determine a type of row hammer of the first memory cell row based on a ratio of the first count value to the second count value; and adjust a pre-charge preparation time between an active operation and the pre-charge operation, by changing a pre-charge operation time point according to the determined type of row hammer.