Patent ID: 11953975
Assignee: WIWYNN CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 10:
11. A peripheral component interconnect express (PCIe) device error reporting optimization system comprising:
a PCIe device;
a connector;
a processor coupled to the connector and configured to execute a basic input/output system (BIOS) and execute a removal detection process;
a baseboard management controller coupled to the processor and configured to receive error log data or filtered error log data processed by the processor; and
an advanced configuration and power interface coupled to the processor and configured to receive the error log data or the filtered error log data processed by the processor;
wherein the processor acquires advanced error reporting data of the PCIe device, the processor executes the removal detection process of the PCIe device for detecting if the PCIe device is plugged into the connector, the processor transmits the error log data of the PCIe device to the baseboard management controller and the advanced configuration and power interface according to the advanced error reporting data if the PCIe device is plugged into the connector, and the processor filters the error log data of the PCIe device so that the filtered error log data is received by the baseboard management controller and the advanced configuration and power interface if the PCIe device and the connector are electrically disconnected.