Patent ID: 11929030
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 2:
3. The display panel according to claim 2, wherein the plurality of clock signal lines is divided into two clock signal line groups, the two clock signal line groups comprise a first clock signal line group and a second clock signal line group, the first clock signal line group comprises a first clock signal line and a second clock signal line, and the second clock signal line group comprises a third clock signal line and a fourth clock signal line;
the plurality of shift register units is divided into two register unit groups, the two register unit groups comprise a first register unit group and a second register unit group, the first register unit group comprises odd-numbered shift register units sequentially arranged in the extension direction of the clock signal lines, and the second register unit group comprises even-numbered shift register units sequentially arranged in the extension direction of the clock signal lines;
for the plurality of shift register units cascaded in the first register unit group, a gate of the input transistor of an odd-numbered level of shift register units is electrically connected to the first clock signal line through a corresponding first connection line, and a first pole of the output transistor of the odd-numbered level of shift register units is electrically connected to the second clock signal line or the first power line through a corresponding second connection line; and, a gate of the input transistor of an even-numbered level of shift register units is electrically connected to the second clock signal line through a corresponding first connection line, and a first pole of the output transistor of the even-numbered level of shift register units is electrically connected to the first clock signal line or the first power line through a corresponding second connection line; and
for the plurality of shift register units cascaded in the second register unit group, a gate of the input transistor of an odd-numbered level of shift register units is electrically connected to the third clock signal line through a corresponding first connection line, and a first pole of the output transistor of the odd-numbered level of shift register units is electrically connected to the fourth clock signal line or the first power line through a corresponding second connection line; and, a gate of the input transistor of an even-numbered level of shift register units is electrically connected to the fourth clock signal line through a corresponding first connection line, and a first pole of the output transistor of the even-numbered level of shift register units is electrically connected to the third clock signal line or the first power line through a corresponding second connection line.