Patent ID: 11887901
Assignee: SILICON WORKS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 12:
13. The test apparatus of claim 11, wherein
the external resistor circuit includes:
an external resistor structure including at least one of a diffusion layer, a polysilicon layer, and a wiring layer that are disposed in the outer region of the chip,
an external transistor, and
a first test pad connected to the external transistor through the external resistor structure and disposed in a chip pad region, and

the internal resistor circuit includes:
an internal resistor structure disposed in the inner region of the chip and including at least one of a diffusion layer, a polysilicon layer, and a wiring layer,
an internal transistor, and
a second test pad connected to the internal transistor through the internal resistor structure and disposed in the chip pad region.