Patent ID: 11948930
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A method comprising:
testing a first set of connectors on a first side of a first substrate, the first set of connectors electrically coupled to a first set of via structures, the first substrate being a wafer;
removing solder caps from upper surfaces of the first set of connectors;
depositing a dielectric layer over and around the first set of connectors;
mounting the first side of the first substrate to a carrier by the dielectric layer;
thinning a second side of the first substrate to expose the first set of via structures, the second side opposite the first side;
attaching a device die to the second side of the first substrate, thereby electrically coupling the device die to the first set of via structures;
disposing an underfill between the device die and the first substrate; and
after attaching the device die, singulating the first substrate into multiple packages.