Patent ID: 11956947
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 9:
10. The OTP memory array of claim 9,
wherein a third OTP memory cell and a fourth OTP memory cell of the plurality of OTP memory cells are arranged in a second row of the plurality of rows, wherein the selection transistor of the third OTP memory cell is connected to the selection transistor of the fourth OTP memory cell;
the antifuse transistor of the third OTP memory cell has a first terminal that is a vacancy terminal and a second terminal that is connected to the selection transistor of the third OTP memory cell, and
the antifuse transistor of the fourth OTP memory cell has a third terminal that is a floating terminal including a contact structure and a fourth terminal that is connected to the selection transistor of the fourth OTP memory cell.