Patent ID: 11949012
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 17:
18. A semiconductor device, comprising:
a first negative capacitance field-effect transistor (NCFET) which comprises a first gate stack on a substrate, wherein the first NCFET includes a first nanosheet; and
a second NCFET which comprises a second gate stack on the substrate, wherein the second NCFET includes a second nanosheet,
wherein the first gate stack comprises a first interfacial layer disposed on the substrate, a first gate insulating layer disposed on the first interfacial layer, a high dielectric constant insulating layer and a conductive layer formed between the interfacial layer and the first gate insulating layer, a first work function layer disposed on the first gate insulating layer to contact the first gate insulating layer and a first tipper gate electrode disposed on the first work function layer,
wherein a thickness of the first gate insulating layer is greater than a thickness of the first work function layer,
wherein the second gate stack comprises a second interfacial layer disposed on the substrate, a second gate insulating layer disposed on the second interfacial layer, a second work function layer disposed on the second gate insulating layer to contact the second gate insulating layer and a second upper gate electrode disposed on the second work function layer,
wherein a structure of the first gate stack is different from a structure of the second gate stack,
wherein the first work function layer comprises the same material as the second work function layer, and the thickness of the first work function layer is different from a thickness of the second work function layer,
wherein the semiconductor device further comprises a third NCFET which comprises a third gate stack on the substrate, wherein the third NCFET includes a third nanosheet,
wherein the third gate stack comprises a third gate insulating layer disposed on the substrate, a third work function layer contacting the third gate insulating layer and a third upper gate electrode disposed on the third work function layer, and
wherein a thickness of the third gate insulating layer is less than a thickness of the third work function layer.