Patent ID: 11971992
Assignee: LATTICE SEMICONDUCTOR CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 10:
11. A secure programmable logic device (PLD) failure characterization system, comprising:
an external system comprising a processor and a memory and configured to be coupled to a secure PLD through a configuration input/output (I/O) of the secure PLD, wherein the memory comprises machine-readable instructions which when executed by the processor of the external system are adapted to cause the external system to perform a computer-implemented method comprising:
providing a failure characterization (FC) command and/or a debug configuration to the secure PLD over the configuration I/O; and
receiving a debug digest from the secure PLD associated with booting and/or execution of the debug configuration by a PLD fabric of the secure PLD;
determining an updated manufacturer trim based, at least in part, on the received debug digest; and
providing the updated manufacturer trim to the secure PLD over the configuration I/O.