Patent ID: 11881251
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. An apparatus, comprising:
a memory array including a row and a set of columns associated with the row; and
peripheral circuitry coupled with the memory array, the peripheral circuitry configured to:
receive a command directed to the row;
activate the row in response to receiving the command;
write, to two or more columns of the set, local data not received from a host device in connection with the command, wherein to write the local data to the two or more columns of the set, the peripheral circuitry is configured to write a pattern of bits retrieved from a single register of the apparatus to each column of the two or more columns; and
deactivate the row based, at least in part, on writing the local data to the two or more columns of the set.