Patent ID: 11914520
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A system comprising:
a memory device comprising a cache of a first type and a cache of a second type; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
retrieving data associated with a memory access workload of an application from a backing store; and
storing, based on the memory access workload, the data associated with the memory access workload and retrieved from the backing store in the memory device, wherein data associated with sequential read operations comprising a plurality of read requests received in order and directed to at least one of a same memory address or sequential memory addresses is stored at the cache of the first type, and wherein data associated with write and read operations is stored at the cache of the second types.