Patent ID: 11929389
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A method of manufacturing an integrated circuit device comprising:
forming a lower electrode on a substrate;
forming a lower portion of a first dielectric layer on the lower electrode, the lower portion of the first dielectric layer including a plurality of grains;
forming an upper portion of the first dielectric layer on the lower portion of the first dielectric layer, the upper portion of the first dielectric layer including a plurality of grains;
forming a second dielectric layer between the lower portion and the upper portion of the first dielectric layer;
forming an upper electrode on the upper portion of the first dielectric layer;
forming a first interface layer that is disposed between the lower electrode and the lower portion of the first dielectric layer; and
forming a second interface layer that is disposed between the upper portion of the first dielectric layer and the upper electrode,
wherein the second dielectric layer is formed in a grain boundary region between the lower portion and the upper portion of the first dielectric layer such that a width of the second dielectric layer in the middle portion is greater than a width of the second dielectric layer in at least one of the upper or lower portions when viewed in cross section,
the lower electrode includes titanium nitride,
the first interface layer includes titanium oxide and niobium oxide,
each of the lower portion and the upper portion of the first dielectric layer includes hafnium oxide and zirconium oxide,
the second dielectric layer includes aluminium oxide,
the second interface layer includes titanium oxide, and
the upper electrode includes titanium nitride.