Patent ID: 11929717
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. An output stage, comprising:
a low voltage (LV) metal oxide semiconductor (MOS) device; and
a current limit circuit configured to
sense a drain voltage of the LV MOS device; and
increase a clamping voltage for the LV MOS device when the drain voltage of the LV MOS device is less than a threshold voltage;

wherein LV MOS device is a first LV MOS device having a first gate, a first drain, and a second source, and wherein the current limit circuit comprises:
a second MOS device having a second gate, a second drain, and a second source, the second gate being coupled to a drain of the first LV MOS device;
a resistor coupled between the second drain and a ground;
a third MOS device having a third gate, a third drain, and a third source, the third gate being coupled to a threshold voltage source, the third source being coupled to the second source, and the third drain being coupled to a first current source,
the second MOS device configured to operate in an OFF mode when the drain voltage of the first MOS device is greater than the threshold voltage, and the second MOS device configured to operate in an ON mode when the drain voltage of the first MOS device is less than the threshold voltage;
a plurality of series-connected MOS devices, wherein a first voltage is generated across the plurality of series-connected MOS devices in response to a biasing current supplied to a drain of one of the plurality of series-connected MOS devices, wherein a source of another of the plurality of series-connected MOS devices is coupled to the resistor so that a combination of a first current flowing through the second MOS device and a second current flowing through the plurality of series-connected MOS devices generates a second voltage across the resistor, wherein a drain voltage of the one of the plurality of series-connected MOS devices is a sum of the first voltage and the second voltage; and
a voltage clamp circuit coupled between the drain of the one of the plurality of series-connected MOS devices and the first gate, wherein a gate-to-source voltage of the first MOS device is limited to the drain voltage of the one of the plurality of series-connected MOS devices.