Patent ID: 11907754
Assignee: MELLANOX TECHNOLOGIES, LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. The system according to claim 15, wherein:
the respective clock synchronization messages are respective interrupt signaling messages; and
the processing device includes an interface controller to detect the writing of the respective clock synchronization messages in the memory and interrupt processing of the device processor responsively to the detection of each of the respective clock synchronization messages being written to the memory, and cause the device processor to: retrieve the respective device clock values from the device clock responsively to the respective clock synchronization messages being written to the memory; compute the respective time differences between the respective hardware clock values included in the respective clock synchronization messages and the respective retrieved device clock values; and discipline the device clock responsively to the ones of the respective time differences.