Patent ID: 11886312
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 19:
20. A system comprising:
a hardware processor;
a transmitter port for transmitting flow control units (flits) across a serial interconnect;
a receiver port to receive flits from across a serial interconnect;
a protocol stack comprising:
forward error correction (FEC) logic to:
identify a correctable error in a first flit, and
correct the correctable error using three error correcting code (ECC) groups; and

an error log, the correctable error log to log a symbol number in the first flit corrected by each ECC group, and to log a magnitude of the correctable error corrected by each ECC group in the first flit; and

a configuration register to log link error correlation, the link error correlation comprising a indication of one or more bits in error in the first flit.