Patent ID: 11967552
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An interconnect structure, comprising:
a bottom via having a first thickness and disposed in a first dielectric layer;
a ruthenium-containing conductive line having a second thickness disposed over the bottom via, wherein the second thickness is less than the first thickness;
a second dielectric layer disposed over the ruthenium-containing conductive line and the first dielectric layer; and
a top via disposed in the second dielectric layer and over the ruthenium-containing conductive line,
wherein the ruthenium-containing conductive line includes a first conductive bulk layer and a first barrier layer conformally disposed over top and side surfaces of the first conductive bulk layer,
wherein the top via includes a second barrier layer and a second conductive bulk layer over the second barrier layer,
wherein the second barrier layer is disposed over the first barrier layer with a physical interface therebetween.