Patent ID: 11955184
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus comprising:
one or more control circuits configured to connect to a three-dimensional memory structure comprising a plurality of NAND strings having memory cells, the three-dimensional memory structure comprising blocks separated by isolation regions with each block having a plurality of word lines extending in a first direction, the three-dimensional memory structure comprising a plurality of bit lines extending in a second direction perpendicular to the first direction, each NAND string associated with a bit line, wherein the one or more control circuits are configured to:
program a group of the memory cells together that are connected to a selected word line in a selected block to one or more data states, the group of memory cells having a plurality of rows of memory cells that extend in the first direction, including applying for each data state a same number of program pulses to each memory cell being programmed to the data state, wherein the group comprises a first set of memory cells in a first one or more rows of the rows that program at a first speed and a second set of memory cells in a second one or more rows of the rows that program at a second speed that is different from the first programming speed, wherein the memory cells in the first set of memory cells are a different distance than the memory cells in the second set of memory cells to the isolation region that separates the selected block from an adjacent block;
read the first set of the memory cells with a first set of read parameters; and
read the second set of the memory cells with a second set of read parameters, wherein the first set of read parameters are different from the second set of read parameters to compensate for the different programming speeds.