Patent ID: 11869889
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 7:
8. An integrated circuit structure, comprising:
a first semiconductor fin having a cut along a longest length of the first semiconductor fin in a plan view perspective, the cut between a first portion of the first semiconductor fin and a second portion of the first semiconductor fin, the first portion of the first semiconductor fin along a same first axis as the second portion of the first semiconductor fin in the plan view perspective;
a second semiconductor fin having a cut along a longest length of the second semiconductor fin in the plan view perspective, the cut between a first portion of the second semiconductor fin and a second portion of the second semiconductor fin, the first portion of the second semiconductor fin along a same second axis as the second portion of the second semiconductor fin in the plan view perspective; and
a gate endcap isolation structure having a first portion between the first semiconductor fin and the second semiconductor fin, the first portion of the gate endcap isolation structure parallel with the longest lengths of the first and second semiconductor fins and laterally spaced apart from the first and second portions and the cut of each of the first and second semiconductor fins, and the gate endcap isolation structure having a second portion in a location of the cuts of the first and second semiconductor fins and in contact with the first and second semiconductor fins.