Patent ID: 11934654
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. An integrated circuit (IC) memory device comprising:
an array of storage cells configured into multiple banks;
interface circuitry to receive refresh commands from a host memory controller to refresh the multiple banks for a first refresh mode;
on-die refresh control circuitry to selectively generate local refresh commands to refresh the multiple banks in cooperation with the host memory controller during a designated hidden refresh interval in a second refresh mode;
mode register circuitry to store a value indicating whether the on-die refresh control circuitry is enabled for use during the second refresh mode;
wherein the on-die refresh control circuitry is configured to conditionally transmit a corrective action control signal during operation in the second refresh mode;
for the first refresh mode, a first timing interval between an Activate command and a corresponding memory access command is of a first duration;
for the second refresh mode, a second timing interval between the Activate command and the corresponding memory access command is of a second duration longer than the first duration; and
wherein the designated hidden refresh interval is based on the second timing interval.