Patent ID: 11929748
Assignee: STMICROELECTRONICS (GRENOBLE 2) SAS
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 8:
9. The device of claim 7, wherein,
the delay elements of the chain, when enabled, add a same delay time period to a received digital signal; and
the control circuitry, in operation, generates a regulation control value H according to:, H
  =
  
   
    (
    
     
      C
      Rf
     
     -
     
      C
      M
     
    
    )
   
   S, where:
C represents a sampling time period;
Rf represents a number of rising edges of the reference clock signal during the sampling time period;
M represents a number of rising edges of the wobulated signal counted by the counter during the sampling time period; and
S represents a duration of the delay time period of a delay element of the chain of delay elements.