Patent ID: 11929437
Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 2:
3. A semiconductor device comprising:
a first transistor, the first transistor comprising an oxide semiconductor in a channel formation region;
a second transistor;
a third transistor, the third transistor comprising silicon in a channel formation region;
a fourth transistor;
a first layer over a substrate, the first layer comprising the channel formation region of the third transistor;
a first insulating layer over the first layer;
a first gate electrode of the third transistor over the first insulating layer;
a first conductive layer over the first gate electrode of the third transistor, the first conductive layer functioning as a first gate electrode of the second transistor;
a second insulating layer over the first conductive layer;
a second layer comprising the oxide semiconductor over the second insulating layer;
a third insulating layer over the second layer;
a second conductive layer over the third insulating layer, the second conductive layer functioning as a second gate electrode of the second transistor; and
a third conductive layer in contact with a top surface of the second layer,
wherein a first wiring is electrically connected to one of a source electrode and a drain electrode of the first transistor,
wherein the other of the source electrode and the drain electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor,
wherein a second wiring is electrically connected to a first gate electrode of the first transistor,
wherein a third wiring is electrically connected to the first gate electrode of the second transistor,
wherein the other of the source electrode and the drain electrode of the second transistor is electrically connected to one of a source electrode and a drain electrode of the third transistor and one of a source electrode and a drain electrode of the fourth transistor,
wherein the first transistor comprises a second gate electrode overlapping with the first gate electrode of the first transistor, and
wherein the third conductive layer comprises a region extending below the second layer.