Patent ID: 11914439
Assignee: ROHM CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 9:
10. A digital processing device comprising:
a plurality of synchronous reset signal generation circuits including a first and a second synchronous reset signal generation circuit; and
a plurality of clock fault determination circuits including a first and a second clock fault determination circuit,
wherein
the synchronous reset signal generation circuit according to claim 1 is used as each of the first and second synchronous reset signal generation circuits,
the clock signal in the first synchronous reset signal generation circuit and the clock signal in the second synchronous reset signal generation circuit are a first clock signal and a second clock signal respectively,
the first clock fault determination circuit is configured to determine presence or absence of a fault in the first clock signal based on the first and second clock signals, and
the second clock fault determination circuit is configured to determine presence or absence of a fault in the second clock signal based on the second and first clock signals.