Patent ID: 11929422
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 0:
1. A semiconductor device, comprising:
a substrate:
first and second source/drain (S/D) regions disposed on the substrate, wherein each of the first and second S/D regions comprises a stack of first and second semiconductor layers arranged in an alternating configuration and an epitaxial region disposed on the stack of first and second semiconductor layers;
nanostructured channel regions disposed between the first and second S/D regions;
a passivation layer, wherein a first portion of the passivation layer is disposed between the epitaxial region and the stack of first and second semiconductor layers and a second portion of the passivation layer is disposed on sidewalls of the nanostructured channel regions and
a nanosheet (NS) structure wrapped around the nanostructured channel regions.