Patent ID: 11953981
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. A method of operation of a controller device to control a dynamic random access memory (DRAM) device having a plurality of memory cells, the method comprising:
transmitting, to a control interface of the DRAM device, a memory access command that specifies an access to the plurality of memory cells;
transmitting, to the control interface of the DRAM device, a first register access command that specifies a first register access;
transmitting, to a data interface of the DRAM device, data to be stored in the plurality of memory cells in response to the memory access command; and
transmitting, to the data interface of the DRAM device, at least one indicator that indicates to the DRAM device that the DRAM device is to store a device identification value in response to the first register access command.