Patent ID: 11862254
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. A semiconductor integrated circuit comprising:
a first signal line including a first part which a first signal is input in response to a first clock signal in a first period, and a second part;
a second signal line including a third part to which a second signal is input in response to a second clock signal in a second period after the first period, and a fourth part;
a first inverter arranged between the first part and the second part of the first signal line, and configured to receive the first signal from the first part and output a first inverted signal obtained by inverting a logic level of the first signal to the second part;
a second inverter arranged between the third part and the fourth part of the second signal line, and configured to receive the second signal from the third part and output a second inverted signal obtained by inverting a logic level of the second signal to the fourth part; and
a control circuit configured to bring the second signal line into a floating state in the first period, and bring the first signal line into a floating state in the second period, wherein
the first clock signal transitions between a first level and a second level different from the first level;
the second clock signal transitions between a third level and a fourth level different from the third level;
the first clock signal is brought into the first level and the second clock signal s brought into the fourth level in a third period as a part of the first period;
the first clock signal is brought into the second level and the second clock signal is brought into the fourth level in a fourth period as another part of the first period;
the first clock signal is brought into the second level and the second clock signal is brought into the third level in a fifth period as a part of the second period; and
the first clock signal is brought into the second level and the second clock signal is brought into the fourth level in a sixth period as another part of the second period.