Patent ID: 11948627
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 16:
17. A method, comprising:
receiving row address information associated with a first memory cell in a first portion of a memory array and a second memory cell in a second portion of the memory array;
controlling a reference voltage provided to a first bitline electrically coupled to the first memory cell and a second bitline electrically coupled to the second memory cell, wherein the second bitline is longer than the first bitline;
in response to the row address information being associated with the first memory cell, coupling the reference voltage to a first negative voltage with a first capacitive element, wherein the first negative voltage is applied to the first bitline coupled to the first memory cell in the first portion of the memory array; and
in response to the row address information being associated with the second memory cell, coupling the reference voltage to a second negative voltage with the first capacitive element and a second capacitive element, wherein the second negative voltage is lower than the first negative voltage and is applied to the second bitline coupled to the second memory cell in the second portion of the memory array.