Patent ID: 11909393
Assignee: SK HYNIX INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. The input/output circuit of claim 6,
wherein the first plurality of MOS transistors comprise a first MOS transistor, a second MOS transistor, and a third MOS transistor,
wherein the at least one internal node comprises a first internal node and a second internal node,
wherein the first internal node is coupled between the first MOS transistor and the second MOS transistor,
wherein the second internal node is coupled between the second MOS transistor and the third MOS transistor,
wherein the fixed voltage comprises a first fixed voltage and a second fixed voltage,
wherein a voltage level of the first internal node is set according to the first fixed voltage, and
wherein a voltage level of the second internal node is set according to the second fixed voltage.