Patent ID: 11960426
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. A method of concurrently servicing a first cable of a cable pair while a second cable of the cable pair remains operational and communicatively connects processing drawers of a multiprocessing (MP) system, the method comprising:
identifying a first pair of processing chips that are communicatively connected by a first data lane group operating in a degraded state comprised within a first cable that primarily communicatively connects the first pair of processing chips, the first cable further comprising a second data lane group that secondarily communicatively connects a second pair of processing chips;
identifying a third data lane group that is complementary to the first data lane group and communicatively connects the first pair of processing chips and is comprised within a second cable that secondarily communicatively connects the first pair of processing chips, the second cable further comprising a fourth data lane group complementary to the second data lane group and that primarily communicatively connects the second pair of processing chips, wherein the first data lane group and the fourth data lane group have more data lanes relative to the second data lane group and the third data lane group, respectively;
determining whether the third data lane group and fourth data lane group comprise at least a threshold number of data lanes are operational, respectively, wherein the threshold number of data lanes is a smallest majority of data lanes within the fourth data lane group;
disabling, in response to the third data lane group and the fourth data lane group respectively comprising at least the threshold number of data lanes, communicative connection of the first pair of processing chips through the first data lane group and disabling communicative connection of the second pair of processing chips through the second data lane group; and
evacuating the first cable while simultaneously maintaining communicative connection of the first pair of processing chips through the third data lane group and communicative connection of the second pair of processing chips through the fourth data lane group.