Patent ID: 11956955
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A method used in forming a memory array comprising strings of memory cells, comprising:
forming a conductor tier comprising conductor material on a substrate;
forming a stack comprising vertically-alternating first tiers and second tiers above the conductor tier, material of the first tiers being of different composition from material of the second tiers;
forming vertically-extending channel-material strings into the stack;
forming a liner laterally-outside of individual of the channel-material strings in one of the first tiers and in one of the second tiers;
after forming the vertically-extending channel-material strings, isotropically etching the liners to form void-spaces in the one second tier above the one first tier, individual of the void-spaces being laterally-between the individual channel-material strings and the second-tier material in the one second tier, the isotropically etching removing all material of the liners above the conductor tier such that none of the material of the liners remains above the void-spaces;
after the isotropically etching, forming conductively-doped semiconductive material against sidewalls of the channel material of the channel-material strings in the one first tier and that extends upwardly into the void-spaces in the one second tier; and
heating the conductively-doped semiconductive material to diffuse conductivity-increasing dopants therein from the void-spaces laterally into the channel material laterally there-adjacent and upwardly into the channel material that is above the void-spaces.