Patent ID: 11923343
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. A semiconductor package, comprising:
a package substrate including a cavity therein;
a first semiconductor chip mounted on the package substrate;
a second semiconductor chip mounted on a top surface of the first semiconductor chip;
a first under-fill layer filling a space between the package substrate and the first semiconductor chip, the first under-fill layer penetrates the package substrate and the cavity to extend onto a bottom surface of the package substrate, and the first under-fill layer fills the cavity;
a second under-fill layer filling a space between the first semiconductor chip and the second semiconductor chip; and
a molding layer on the package substrate, the molding layer surrounding the first semiconductor chip and the second semiconductor chip,
wherein a width of the first under-fill layer between the package substrate and the first semiconductor chip being less than a width of the second under-fill layer between the first semiconductor chip and the second semiconductor chip, and
wherein each of the first semiconductor chip and the second semiconductor chips includes:
a base layer having an integrated circuit formed therein;
a chip pad on a bottom surface of the base layer; and
a through electrode that vertically penetrates the base layer and is connected to the chip pad.