Patent ID: 11915754
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A memory device, comprising:
a first cell array comprising a first plurality of bit cells using a first variable resistance dielectric layer to transition between logic states;
a second cell array comprising a second plurality of bit cells using a second variable resistance dielectric layer to transition between logic states; and
a control logic circuit configured to cause a first information bit to be written into respective bit cells of the first cell array as an original logic state of the first information bit, and to cause a second information bit to be written into at least one bit cell of the second cell array as an original logic state of the second information bit,
wherein
the first variable resistance dielectric layer has a first diameter, and
the second variable resistance dielectric layer has a second diameter that is different from the first diameter.