Patent ID: 11860781
Assignee: AMAZON TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A system, comprising:
a dynamic random access memory (DRAM);
a plurality of requesting agents configured to issue memory write transactions;
a system level cache (SLC) coupled to the plurality of requesting agents via an interconnect fabric, the SLC being a write-back cache memory; and
a write cleaner circuit coupled to the interconnect fabric, the write cleaner circuit configured to:
determine that memory write transactions having sequential addresses have been issued within a time period by one or more requesting agents from the plurality of requesting agents to access memory locations corresponding to a memory page in the DRAM; and
generate a respective clean request to the SLC based on each of the memory write transactions corresponding to the memory page,

wherein the SLC is configured to:
perform each of the memory write transactions at a corresponding memory location in the SLC;
receive the respective clean request for each of the memory write transactions from the write cleaner circuit;
send respective update requests to the DRAM based on the respective clean requests; and
update a status of a respective cache line corresponding to the respective memory location from dirty to clean based on the respective clean requests, and

wherein the DRAM is configured to:
receive the respective update requests for each of the memory write transactions from the SLC;
download contents of the memory page corresponding to the sequential addresses once to a page buffer of the DRAM based on the respective update requests;
update the contents of the memory page in the page buffer based on the corresponding memory locations in the SLC; and
write the updated contents of the memory page from the page buffer back to the memory page in the DRAM.