Patent ID: 11957067
Assignee: STMICROELECTRONICS (ROUSSET) SAS
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A memory, comprising:
a semiconductor substrate;
a first insulating layer on the semiconductor substrate;
an active layer of a semiconductor material on the first insulating layer;
a control gate of a first selection transistor on the active layer and having a lateral flank;
a second insulating layer covering the lateral flank of the control gate;
a first conduction region and a second conduction region of the first selection transistor in the active layer;
a trench in the active layer and defined on a first side by a first lateral flank of the active layer and reaching the first insulating layer;
a heater layer of resistive material in the trench covering the first lateral flank of the active layer and in contact with the second insulating layer; and
a layer of a variable resistance material having a bottom surface above the trench and higher than a top of the second insulating layer, wherein the bottom surface is in contact with the heater layer, electrically coupled to the first conduction region, and the heater layer of resistive material is configured to heat the layer of the variable resistance material.