Patent ID: 11955155
Assignee: UIF (UNIVERSITY INDUSTRY FOUNDATION), YONSEI UNIVERSITY
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 34:
35. A latch configured to store data in a nonvolatile manner, comprising:
a first inverter;
a second inverter including a pull-up transistor, a pull-down transistor, and a ferroelectric field effect transistor having gate nodes connected to each other, and a restore transistor having one electrode connected to the ferroelectric field effect transistor, and cross-coupled to the first inverter;
a first transmission gate connected to an input node of the first inverter;, a second transmission gate having one electrode connected to an output node of the second inverter and the other electrode connected to the input node of the first inverter; and, a third inverter configured to invert and output an output of the first inverter, wherein when the ferroelectric field effect transistor is programmed to a low resistance state, a turning-on resistance of a pull-down path including the restore transistor and the ferroelectric field effect transistor is smaller than a turning-on resistance of a pull-up path including the pull-up transistor.