Patent ID: 11917045
Assignee: MELLANOX TECHNOLOGIES, LTD.
Field: Telecommunications (Electrical engineering)
Classification: CPC H | IPC G  H

Claim 5:
6. The system according to claim 1, wherein:
the frequency synthesizer includes at least one control input connector and at least one output connector;
the network devices are connected to the at least one control input connector and the at least one output connector;
a first network device of the network devices is configured to:
recover a first remote clock from a first data stream received by the first network device;
find a first clock frequency differential between the clock signal and the recovered first remote clock; and
provide a first control signal to the frequency synthesizer responsively to the first clock frequency differential, the first control signal causes the frequency synthesizer to adjust the clock signal so as to iteratively reduce an absolute value of the first clock frequency differential between the clock signal and the recovered first remote clock;

the frequency synthesizer is configured to: receive the first control signal from the first network device via the at least one control input connector; and output the clock signal via the at least one output connector;
a second network device of the network devices is configured to:
recover a second remote clock from a second data stream received by the second network device;
find a second clock frequency differential between the clock signal and the recovered second remote clock; and
provide a second control signal to the frequency synthesizer responsively to the second clock frequency differential, the second control signal causes the frequency synthesizer to adjust the clock signal so as to iteratively reduce an absolute value of the second clock frequency differential between the clock signal and the recovered second remote clock; and

the frequency synthesizer is configured to: receive the second control signal from the second network device via the at least one control input connector; and output the clock signal via the at least one output connector.