Patent ID: 11930639
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. A three-dimensional semiconductor memory device, comprising:
a peripheral circuit structure comprising a substrate and peripheral logic circuits formed with the substrate;
horizontal patterns disposed on the peripheral circuit structure and spaced apart from each other in a first direction;
memory structures provided on the horizontal patterns, respectively, each of the memory structures comprising memory cells, which are three-dimensionally arranged;
a separation structure disposed between adjacent ones of the horizontal patterns;
first and second penetrating insulating patterns provided between and contacting side surfaces of adjacent ones of the horizontal patterns; and
through plugs, which penetrate the first and second penetrating insulating patterns to operatively connect the memory structures to the peripheral circuit structure, wherein the separation structure comprises:
a dummy plug disposed between the horizontal patterns; and
a dummy spacer interposed between the dummy plug and the horizontal patterns,
wherein the dummy plug comprises a horizontal portion extending in a second direction and a vertical portion extending from the horizontal portion in a third direction perpendicular to the first and second directions,
wherein a width of the horizontal portion in the first direction is at least 1.5 larger than a width of the vertical portion in the first direction,
wherein the separation structure extends between and contacts the first and second penetrating insulating patterns, and
wherein a bottom surface of the separation structure is positioned at a level higher than bottom surfaces of the through plugs.