Patent ID: 11886738
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 1:
2. The memory system according to claim 1, further comprising:
a low-reliability location information memory arranged to store a-th low-reliability location information indicating a location of the read information determined to have low reliability among pieces of the read information for each of the M component codes, wherein
the memory controller is configured to:
determine the number of pieces of low-reliability location information, the number of pieces of low-reliability location information being the number of pieces of the a-th low-reliability location information for each of the M component codes according to the value based on the number of component codes;
determine a low-reliability location information address, the low-reliability location information address being an address on the low-reliability location information memory of the a-th low-reliability location information for each of the M component codes based on the number of pieces of the low-reliability location information;
calculate the a-th low-reliability location information before calculating the a-th soft-input value;

store the calculated a-th low-reliability location information in the low-reliability location information address of the low-reliability location information memory; and
calculate the a-th soft-input value based on the a-th correction information, the a-th reliability information, the syndrome value of the a-th component code, and the a-th low-reliability location information.