Patent ID: 11908520
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A memory device comprising:
a first chip; and
a second chip bonded to the first chip,
wherein the first chip includes a first substrate, a first circuit provided on the first substrate, a first electrode facing a bonding surface of the first chip and the second chip with the first electrode electrically connected to the first circuit, and a first memory cell array provided between the first substrate and the first electrode and electrically connected to the first circuit, and
the second chip includes a second substrate, a second circuit provided on the second substrate, a second electrode facing the bonding surface with the second electrode electrically connected to the second circuit and being in contact with the first electrode, and a second memory cell array provided between the second substrate and the second electrode with the second memory cell array electrically connected to the second circuit.