Patent ID: 11880309
Assignee: VMWARE LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. A computer system comprising:
processing hardware including one or more caches;
monitoring hardware connected to the processing hardware by a coherence interconnect, the monitoring hardware including local memory; and
system memory accessible connected to the processing hardware by a first bus and to the monitoring hardware by a second bus, wherein the system memory is different from the local memory and has a larger capacity and lower memory access speeds than the local memory,
wherein the monitoring hardware is configured to carry out a method of tracking state of cache lines that are transferred into the one or more caches of the processing hardware from and into the system memory, said method comprising:
storing a bitmap that indicates the state of the cache lines in the system memory;
monitoring the processing hardware for cache coherence events on a coherence interconnect that is connected between the processing hardware and monitoring hardware;
determining, based on the monitoring, that the state of a cache line has changed from a first state to a second state; and
updating a hierarchical data structure and a cache for the bitmap, both of which are stored in the local memory of the monitoring hardware, to indicate the change in the state of said cache line from the first state to the second state, wherein
the hierarchical data structure includes a first level data structure including a plurality of first bits, and a second level data structure including a plurality of second bits, each of the first bits associated with a group of the second bits, and
the updating includes setting one of the first bits and one of the second bits in the group corresponding to the first bit that is being set, according to an address of said cache line.