Patent ID: 11949004
Assignee: GLOBALFOUNDRIES U.S. INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. A method comprising:
forming a base region comprising an undoped intrinsic base region and a doped extrinsic base region below the undoped intrinsic base region;
forming a raised emitter region on a first side of and above the doped extrinsic base region;
forming a raised collector region on a second side of and above the doped extrinsic base region;
forming an extrinsic base contact wrapping around a semiconductor material of the doped extrinsic base region;
forming a gate structure comprising a gate dielectric material and a gate control in a same channel region as the doped extrinsic base region, and sidewall spacers extending along sidewalls of the gate control, and
forming insulator material in a cavity of the semiconductor material part of which comprises the doped extrinsic base region and the undoped intrinsic base region, the insulator material surrounding the doped extrinsic base region and underneath both the raised emitter region and the raised collector region,
wherein the raised emitter region and raised collector region extends above the gate dielectric material, and along the sidewall spacers of the gate structure, the sidewall spacers isolates the raised emitter region and the raised collector region from the gate control.