Patent ID: 11862530
Assignee: HYUNDAI MOTOR COMPANY
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A double-sided cooling power module comprising:
a first insulating layer;
a first upper metal plate disposed on an upper surface of the first insulating layer;
a first lower metal plate disposed on a lower surface of the first insulating layer;
a second insulating layer;
a second upper metal plate disposed on an upper surface of the second insulating layer;
a second lower metal plate disposed on a lower surface of the second insulating layer;
a semiconductor chip provided between the first lower metal plate and the second upper metal plate;
a signal lead through which a signal is transmitted to or received from the semiconductor chip;
a wire connecting the semiconductor chip and the signal lead; and
a spacer provided between the semiconductor chip and the first lower metal plate, to prevent a contact between the first lower metal plate and the wire,
wherein the spacer includes a plurality of first metal layers made of a first metal and provided as outermost layers and a second metal layer made of a second metal having a thermal expansion coefficient lower than a thermal expansion coefficient of the first metal and disposed between the plurality of first metal layers,
wherein a thermal expansion coefficient of the spacer is below a first threshold value and above the thermal expansion coefficient of the second metal,
wherein the first threshold value is between the thermal expansion coefficient of the first metal and the thermal expansion coefficient of the second metal,
wherein a thermal conductivity of the spacer is above a second threshold value and below a thermal conductivity of the first metal,
wherein the second threshold value is below a thermal conductivity of the second metal,
wherein one of the plurality of first metal layers that is forming an uppermost layer of the spacer is joined with the first lower metal plate through soldering,
wherein another one of the plurality of first metal layers that is forming a lowermost layer of the spacer is joined with the semiconductor chip through soldering, and
wherein the second metal has a solder wettability lower than a solder wettability of the first metal, and
wherein a thickness of the second metal layer accounts for 33% to 50% of a total thickness of the spacer.