Patent ID: 11894861
Assignee: PANASONIC HOLDINGS CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A bit interleaving method comprising:
receiving a codeword generated according to a repeat-accumulate quasi-cyclic low-density parity check coding scheme, the codeword including N bit groups each consisting of Q bits;
reordering the N bit groups, without reordering the bits within each N bit group;
reordering bits in the codeword after the N bit groups are reordered;
dividing the codeword into constellation words after the bits in the codeword are reordered, each of the constellation words being made up of M bits, wherein
N is not a multiple of M, X is a remainder of N divided by M, and N′ is equal to N-X,
bits of N′ bit groups are written into an M by Q matrix row-by-row and the written bits of the N′ bit groups are read from the M by Q matrix column-by-column in order to reorder the bits in the codeword, and
the method further comprises reordering a parity portion of the codeword before the N bit groups are reordered without reordering the bits within each N bit group.