Patent ID: 11962292
Assignee: TAIPEI ANJET CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 1:
2. The gate driving device according to claim 1, wherein the UVLO circuit comprises:
a first NPN bipolar junction transistor (BJT) having a base coupled to the UVLO voltage, a collector coupled to the positive power rail, and an emitter coupled to the low-voltage terminal through a second resistor;
a second NPN bipolar junction transistor (BJT) having an emitter coupled to a node between the emitter of the first NPN BJT and the second resistor and a collector coupled to the positive power rail through a third resistor, wherein a base of the second NPN BJT is coupled to the low-voltage terminal through a fourth resistor and coupled to the driving voltage through a fifth resistor; and
a PNP bipolar junction transistor (BJT) having a base coupled to a node between the third resistor and the collector of the second NPN BJT, an emitter coupled to the positive power rail, and a collector coupled to the multiplexer and coupled to the low-voltage terminal through a sixth resistor.