Patent ID: 11961843
Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A semiconductor device comprising:
a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a fifth transistor;
a sixth transistor;
a seventh transistor; and
an eighth transistor,
wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,
wherein one of a source and a drain of the second transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to a third wiring,
wherein a gate of the second transistor is electrically connected to a fourth wiring,
wherein one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to a fifth wiring,
wherein a gate of the third transistor is electrically connected to the fifth wiring,
wherein one of a source and a drain of the fourth transistor is electrically connected to the gate of the first transistor,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the third wiring,
wherein a gate of the fourth transistor is electrically connected to the fourth wiring,
wherein one of a source and a drain of the fifth transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the third wiring,
wherein one of a source and a drain of the sixth transistor is electrically connected to the gate of the first transistor,
wherein the other of the source and the drain of the sixth transistor is electrically connected to the third wiring,
wherein a gate of the sixth transistor is electrically connected to a gate of the fifth transistor,
wherein one of a source and a drain of the seventh transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the seventh transistor is electrically connected to the third wiring,
wherein one of a source and a drain of the eighth transistor is electrically connected to the gate of the first transistor,
wherein the other of the source and the drain of the eighth transistor is electrically connected to the third wiring,
wherein a gate of the eighth transistor is electrically connected to a gate of the seventh transistor,
wherein the first wiring is configured to output a first signal,
wherein the second wiring is configured to supply a clock signal,
wherein the fifth wiring is configured to supply a second signal, and
wherein the second signal is different from the clock signal.