Patent ID: 11955978
Assignee: BLUE CHEETAH ANALOG DESIGN, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 13:
14. A circuit for a voltage comparator comprising:
a first NMOS transistor comprising a first gate terminal, a first source terminal, and a first drain terminal, wherein the first drain terminal is connected to ground;
a second NMOS transistor comprising a second gate terminal arranged to receive a first input voltage, a second source terminal, and a second drain terminal connected to the first source terminal of the first NMOS transistor at a first node; and
a third NMOS transistor comprising a third gate terminal arranged to receive a second input voltage, a third source terminal, and a third drain terminal connected to the first node;
a first PMOS transistor comprising a fourth gate terminal, a fourth source terminal connected to a supply voltage, and a fourth drain terminal connected to the second source terminal of the second NMOS transistor at a second node;
a second PMOS transistor comprising a fifth gate terminal, a fifth source terminal connected to the supply voltage, and a fifth drain terminal connected to the third source terminal of the third NMOS transistor at a third node; and
one or more capacitors connected between a fourth node at the second gate terminal of the second NMOS transistor and the third node;
one or more capacitors connected between a fifth node at the third gate terminal of the third NMOS transistor and the second node;
a first switch connected to the fourth node;
a second switch connected to the fifth node;
a third switch connected to the first node;
a fourth switch connected to the second node; and
a fifth switch connected to the third node.