Patent ID: 11901912
Assignee: SILICON MOTION, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. A method of accessing a flash memory, for use in a memory controller of a data storage device, wherein a low-density parity check (LDPC) process performed by the memory controller comprises an initial phase, a decoding phase, and an output phase, the method comprising:
storing data to the flash memory of the data storage device via a storage procedure;
wherein during the initial phase, the method comprises:
obtaining a channel value, that is read from a flash memory, from a channel-value memory;
transmitting the channel value to the check-node circuit to calculate a syndrome; and
in response to the syndrome not being 0, setting a value of a register corresponding to each entry of a plurality of entries in a variable-node memory to 0, and entering the decoding phase;
wherein the method further comprises:
in response to the value of the register in the variable-node memory corresponding to a specific bit in a decoding result being 0, setting the channel value to the specific bit; and
in response to the value of the register in the variable-node memory corresponding to the specific bit of the decoding result being 1, calculating the specific bit by performing an XOR operation on the channel value and the variable-node symbol value corresponding to the specific bit.