Patent ID: 11862996
Assignee: NAVITAS SEMICONDUCTOR LIMITED
Field: Semiconductors (Electrical engineering)
Classification: CPC H  Y | IPC H

Claim 5:
6. An electronic component comprising:
a package base;
one or more semiconductor dies secured to the package base and comprising:
a first transistor having a first gate terminal, a first source terminal and a first drain terminal; and
a second transistor having a second gate terminal, a second source terminal and a second drain terminal;
wherein the first drain terminal is coupled to the second source terminal;
wherein the first transistor is a gallium nitride (GaN)-based lateral high electron mobility transistor (HEMT) and the second transistor is a GaN-based lateral HEMT;
wherein the one or more semiconductor dies comprise a first and second GaN-based dies and a third silicon-based die, and wherein the first transistor is disposed on the first GaN-based die, the second transistor is disposed on the second GaN-based die, and wherein the third silicon-based die comprises a first gate driver circuit coupled to the first gate terminal.