Patent ID: 11894102
Assignee: SK HYNIX INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 20:
21. The semiconductor device of claim 15, further comprising:
a second alignment circuit configured to align the read data in response to the first to fourth read clock signals received through the second clock transmission path, the read data received through the first data transmission path, and to transmit the first to fourth read clock signals and the read data through a third clock transmission path and a second data transmission path,
wherein each of first to fourth duty correction devices is configured to receive the first to fourth read clock signals transferred through the third clock transmission path, receive one of the first to fourth read clock signals as the reference clock signal and remaining ones of the first to fourth read clock signals as the first to third divided clock signals alternatively according to the phases of the first to fourth read clock signals, detect the phase difference between the reference clock signal and the first to third divided clock signals, and perform the duty correction operation on the reference clock signal.