Patent ID: 11860671
Assignee: WINBOND ELECTRONICS CORP.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 1:
2. The memory-control logic as claimed in claim 1, wherein when the binary array is the first value, the second value, the third value, and the fourth value, the available memory-size ratio is 100%, 50%, 25%, and 12.5%, respectively,
wherein there is a first number of the regions, and when a ratio of a number of good regions to the first number is between 75% and 100%, 50% and 75%, 25% and 50%, and 12.5% and 50%, the memory-control circuit programs the binary array of the first array to the first value, the second value, the third value, and the fourth value, respectively.