Patent ID: 11907831
Assignee: UNIVERSITY OF DAYTON
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. The analog neuromorphic circuit of claim 3, further comprising:
a plurality of horizontal wires positioned to intersect with a first pair of vertical wires forming a first wire grid so that each horizontal wire forms a row of the first wire grid and each vertical wire from the first pair of vertical wires forms a column of the first wire grid;
a first plurality of resistive memories with each resistive memory positioned at an intersection of the plurality of horizontal wires and the first pair of vertical wires and configured to:
provide a conductance to each input voltage applied to the each horizontal wire so that each input voltage of the first wire grid is multiplied by the corresponding conductance to generate a current relative to each row of the first wire grid that is conducted by a first vertical wire of the first pair of vertical wires and by a second vertical wire of the first pair of vertical wires,
add each current relative to each row of the first wire grid to generate a first accumulative current of the first wire grid that is conducted by the first vertical wire of the first pair of vertical wires and a second accumulative current of the first wire grid that is conducted by the second vertical wire of the first pair of vertical wires; and

a first comparator coupled to the first vertical wire of the first pair of vertical wires at a first input and to the second vertical wire of the first pair of vertical wires at a second input and configured to:
compare a first voltage associated with the first accumulative current of the first wire grid to a second voltage associated with the second accumulative current of the first wire grid, and
generate a first output signal when the first voltage is greater than the second voltage and a second output signal when the second voltage is greater than the first voltage.