Patent ID: 11881973
Assignee: QUALCOMM INCORPORATED
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. The network node of claim 15, wherein the one or more processors, to obtain the trellis diagram, are configured to:
identify, for each stage of the trellis diagram, one or more valid partial sums;
identify, for each valid partial sum of the one or more valid partial sums, one or more allowed symbols in a constellation associated with the trellis diagram, wherein an allowed symbol is a symbol that results in a valid partial sum at a next stage of the trellis diagram when combined with a valid partial sum at a current stage of the trellis diagram; and
identify, for each valid partial sum of the one or more valid partial sums, one or more proceeding paths, wherein a proceeding path is a path leading to a partial sum at the next stage where a difference between the partial sum at the next stage and a partial sum at the current stage is a constellation point in the constellation,
wherein a node in the current stage includes a valid partial sum, from the one or more valid partial sums and the one or more proceeding paths, wherein the node is associated with one or more edges corresponding to allowed symbols, from the one or more allowed symbols, for the valid partial sum.