Patent ID: 11968466
Assignee: BRILLNICS SINGAPORE PTE. LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G  H | IPC H

Claim 0:
1. A solid-state imaging device comprising:
a pixel part having pixels arranged in a matrix pattern, each pixel being configured to perform photoelectric conversion; and
a reading circuit having an analog-to-digital (AD) conversion function for analog-to-digital converting a pixel signal read out from the each pixel onto a signal line as a voltage signal,
wherein the pixel signal read out from the each pixel includes a read-out reset signal and a read-out signal sequentially read from the each pixel,
wherein the reading circuit includes:
an AD converting part for analog-to-digital converting the read-out reset signal and the read-out signal included in the pixel signal read onto the signal line into an n-bit digital pixel signal; and
a calculating part including an n-bit asynchronous counter having a retention circuit with a control logic function for obtaining a difference between an n-bit read-out reset signal and an n-bit read-out signal produced by the AD conversion performed by the AD converting part, and
wherein the calculating part:
places the asynchronous counter in a non-operational state, captures, in synchronization with a capture signal, each bit of the n-bit read-out reset signal produced by the AD conversion performed by the AD converting part, and holds the read-out reset signal in the retention circuit; and
subsequently places the asynchronous counter in an operational state, captures, in synchronization with a capture signal, each bit of the n-bit read-out signal produced by the AD conversion performed by the AD converting part, adds the captured read-out signal to the read-out reset signal held in the retention circuit, performs counting and performs an operation between a negative version of the read-out reset signal and a positive version of the read-out signal,
wherein the calculating part includes n asynchronous counter modules arranged in a one-to-one correspondence with bits of the digital pixel signal including the n-bit read-out reset signal and the n-bit read-out signal,
wherein the asynchronous counter modules are connected in cascade through a carry signal input/output line,
wherein each of the asynchronous counter modules includes:
a logic circuit; and
a D flip-flop serving as the retention circuit for performing an operation in response to a clock signal from the logic circuit,
wherein the logic circuit is configured to generate the clock signal based on the digital pixel signal captured in response to the capture signal and on a logical operation associated with a carry signal from a lower-order one of the asynchronous counter modules,
wherein, in the D flip-flop, a data output Q is connected to a signal output terminal, a data inverting output terminal QB is connected to a data input D of the D flip-flop and to a carry signal output terminal connected to a carry signal input terminal of a higher-order one of the asynchronous counter modules, and
a clock terminal is connected to a clock signal output terminal of the logic circuit.