Patent ID: 11921157
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 2:
3. A processor comprising a burn-in resilient integrated circuit comprising:
an inverter chain;
a plurality of inverter circuits on the inverter chain, wherein a number of the plurality of inverter circuits is odd;
a multiplexer comprising an output pin connected to a first inverter circuit included in the inverter chain, and comprising an enable pin, a first input pin, and a second input pin; and
a local clock block comprising a clock input connected in common with the first input pin of the multiplexer such that both the clock input and the first input pin are configured to receive a common global clock signal, the local clock block including a first clock output and a second clock to clock a plurality of sampled latches configured to pass sampled data received from the inverter chain; and
a selectable loop that provides an electrical connection for a feedback signal from an output of the inverter chain directly to the second input pin of the multiplexer the burn-in resilient integrated circuit configured to:
receive an engage signal at the enable pin indicating a burn-in operation is activated; and
based on receiving the engage signal indicating the burn-in operation is activated, activate the selectable loop, wherein activating the selectable loop causes the feedback signal in the burn-in resilient integrated circuit to oscillate,
wherein the burn-in resilient integrated circuit further configured to:
based on not receiving the engage signal at the enable pin indicating the burn-in operation is deactivated, deactivate the selectable loop,
wherein the feedback signal is not provided from the output of the inverter chain to the input of the inverter chain based on the selectable loop being deactivated.