Patent ID: 11937429
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of forming an integrated structure, comprising:
forming a vertical stack comprising first levels alternating with second levels, the first levels comprising a nitride material and the second levels comprising a dielectric material, an uppermost level of the stack being one of the first levels;
forming an insulative material over the uppermost level of the stack;
forming an etch-resistant material over the insulative material, the etch resistant material comprising silicon, nitrogen, and one or more substances selected from the group consisting of carbon, oxygen, boron and phosphorus, the material being in direct physical contact with the insulative material;
forming an opening extending through the etch resistant material, through the insulative material, and through at least some of the first and second levels;
removing the nitride material of the first levels without removing a remaining region of the etch-resistant material; and
replacing the nitride material with conductive material.