Patent ID: 11921623
Assignee: SECURED-IC SAS
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 4:
5. The device of claim 1 wherein the statistical tests comprise the AIS Poker Test which provide a sum value T2, the corresponding lower threshold L2 and the higher threshold H2 being equal to:, L
       2
      
      =
      
       
        (
        
         
          
           χ
           
            (
            
             
              2
              M
             
             -
             1
            
            )
           
           2
          
          ⁢
          
           (
           
            
             0
             .
             3
            
            ×
            α
           
           )
          
         
         +
         
          ⌊
          
           N
           M
          
          ⌋
         
        
        )
       
       ×
       
        
         ⌊
         
          N
          M
         
         ⌋
        
        
         2
         M
        
       
      
     
     ,
        
     and
    
   
  
  
   
    
     
      
       H
       2
      
      =
      
       
        (
        
         
          
           χ
           
            (
            
             
              2
              M
             
             -
             1
            
            )
           
           2
          
          ⁢
          
           (
           
            1
            -
            
             
              0
              .
              7
             
             ×
             α
            
           
           )
          
         
         +
         
          ⌊
          
           N
           M
          
          ⌋
         
        
        )
       
       ×
       
        
         ⌊
         
          N
          M
         
         ⌋
        
        
         2
         M
        
       
      
     
     ,
    
   
  
 

with M representing the length of the contiguous blocks in the bit sequence and a representing the error probability.