Patent ID: 11908906
Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A fabrication method of a semiconductor structure, comprising:
providing a substrate;
forming a first dielectric layer and a plurality of gate structures over the substrate, forming source-drain doped regions in the substrate on both sides of a gate structure of the plurality of gate structures, and forming a source-drain plug on a top surface of a source-drain doped region of the source-drain doped regions, wherein the first dielectric layer covers surfaces of the gate structure, the source-drain doped region and the source-drain plug;
forming a first plug in the first dielectric layer, wherein the first plug is in contact with one of a top surface of the source-drain plug and a top surface of the gate structure;
forming a second dielectric layer on a surface of the first dielectric layer, wherein the second dielectric layer covers a surface of the first plug;
forming a second plug material film in the first dielectric layer and the second dielectric layer, wherein the second plug material film is in contact with one of the top surface of the source-drain plug and the top surface of the gate structure; and
planarizing the second plug material film until the surface of the first dielectric layer and a top surface of the first plug are exposed, to form a second plug in the first dielectric layer, wherein the second plug is in contact with one of the top surface of the source-drain plug and the top surface of the gate structure.