Patent ID: 11876020
Assignee: SOITEC
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of fabricating a CFET device, comprising:
forming a double semiconductor-on-insulator substrate comprising, in succession, from its base to its surface: a carrier substrate, a first electrically insulating layer, a first single-crystal semiconductor layer, a second electrically insulating layer and a second single-crystal semiconductor layer;
forming trenches from the surface of the substrate, to the first electrically insulating layer, so as to form at least one fin (F), and
in each fin (F), forming a channel of a first transistor in the first semiconductor layer and a channel of a second transistor of opposite type to the first transistor in the second semiconductor layer,
the formation of the double semiconductor-on-insulator substrate comprising:
a first layer-transfer step to transfer the first electrically insulating layer and the first single-crystal semiconductor layer to the carrier substrate, so as to form a first semiconductor-on-insulator substrate, the first layer-transfer step comprising a heat treatment at a sufficiently high temperature to smooth the first single-crystal semiconductor layer to a roughness lower than 0.1 nm RMS, and
after the heat treatment, a second layer-transfer to transfer the second electrically insulating layer and the second single-crystal semiconductor layer to the first single-crystal semiconductor layer of the first semiconductor-on-insulator substrate.