Patent ID: 11886747
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A controller for controlling a memory device including a first memory region and a second memory region having a first bit-density and a second bit density, respectively, comprising:
a memory storing a logical address list including a number of received logical addresses;
a central processing unit (CPU) configured to insert a latest received logical address, received together with a write command and data from a host, into the logical address list;
a hotness determining circuit configured to assign a maximum weight to the latest received logical address, decrease weights of the received logical addresses included in the logical address list by a decay factor, and sum weights of the received logical addresses having values, equal to a value of the latest received logical address, to determine hotness of the latest received logical address;
a pattern detection circuit configured to determine a repeatability index of the received logical addresses included in the logical address list; and
a parameter adjustment circuit configured to decrease a magnitude of the decay factor based on the repeatability index, to upwardly adjust the weights of the received logical addresses,
wherein the CPU is further configured to control the memory device to store the data in the first memory region or the second memory region based on the hotness of the latest received logical address.