Patent ID: 11907715
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. The system of claim 1, wherein in a second iteration of at least a portion of the process, the processor is configured to:
input the second residual vector to the array of cells;
utilize the resistive processing unit to perform a third matrix-vector multiplication operation by multiplying the second residual vector with the preconditioning matrix in the array of cells to generate a second output vector of the plurality of output vectors;
combine the first augmented matrix with the second output vector to generate a second augmented matrix which is output from the array of cells;
perform a fourth matrix-vector multiplication operation by multiplying the second augmented matrix with a second weight vector; and
compute a third residual vector of the plurality of residual vectors based at least in part on the product of the fourth matrix-vector multiplication operation.