Patent ID: 11900985
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 11:
12. A method for operating a buffer circuit comprising:
receiving, by an internal clock generator circuit, an input clock from a source device, the input clock providing timing information associated with an input data signal, and receiving by the internal clock generator circuit, an internal clock control signal specifying a first selected reference edge of the input clock;
generating, by the internal clock generator circuit, an internal clock locked to the first selected reference edge of the input clock;
receiving, by an output clock generator circuit, the input clock and an output clock control signal specifying a second selected reference edge of the input clock;
generating, by the output clock generator circuit, an output clock locked to the second selected reference edge of the input clock, wherein the output clock has a predefined phase relationship to the input clock that is independent of the first and the second selected reference edges;
receiving, by a sampler circuit, the input data signal from the source device;
sampling, by the sampler circuit, the input data signal based on the internal clock to generate an output data signal; and
outputting, by an output interface, the output data signal with the output clock to a destination device, wherein the output clock provides timing information associated with the output data signal.