Patent ID: 11908697
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A method of forming an interconnect structure, the method comprising:
forming a first dielectric layer;
forming a first recess in the first dielectric layer;
forming a first conductive feature in the first recess, an upper surface of the first conductive feature being level with an upper surface of the first dielectric layer, the first conductive feature having a first void;
forming a second dielectric layer over the first dielectric layer;
after forming the second dielectric layer, forming a second recess through the second dielectric layer and into the first dielectric layer, wherein forming the second recess removes at least a portion of the first conductive feature to expose the first void;
forming a carbon-containing TaN layer along sidewalls of the second recess and sidewalls of the first void; and
forming a second conductive layer over the carbon-containing TaN layer.