Patent ID: 11901036
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. An apparatus comprising:
a bank comprising:
a first plurality of memory cells;
a second plurality of memory cells;
first sense amplifiers coupled to the first plurality of memory cells and further coupled to a first common power supply node;
second sense amplifiers coupled to the second plurality of memory cells and further coupled to a second common power supply node;
first transistor coupled to the first sense amplifiers at the first common power supply node, the first transistor comprises a first drive strength; and
a second transistor coupled to the second sense amplifiers at the second common power supply node, the second transistor comprises a second drive strength,

wherein the first and second transistors are configured to receive a control signal,
wherein the first and second transistors are configured to be activated responsive to the control signal in an active state, and
wherein the first drive strength and the second drive strength are different from each other.