Patent ID: 11960408
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 18:
19. The semiconductor memory device of claim 18, wherein:
even bit lines E0, E1, E4, and E5 of the even bit lines are electrically connected to the common column decoder block of the first page buffer pair,
odd bit lines O0, O1, O4, and O5 of the odd bit lines are electrically connected to the common column decoder block of the second page buffer pair,
even bit lines E2, E3, E6, and E7 of the even bit lines are electrically connected to the common column decoder block of the third page buffer pair, and
odd bit lines O2, O3, O6, and O7 of the odd bit lines are electrically connected to the common column decoder block of the fourth page buffer pair.