Patent ID: 11899564
Assignee: RENESAS ELECTRONICS CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. A debug apparatus for debugging target programs including a plurality of programs operating in a semiconductor device including a plurality of Central Processing Units (CPUs) and a plurality of temperature sensors, the debug apparatus comprising:
wherein the plurality of CPUs is configured to execute the target programs,
wherein, while the target programs are executed by the plurality of CPUs, the plurality of temperature sensors is configured to measure temperature of the semiconductor device,
wherein the debug apparatus comprises:
an information storage unit configured to store CPU position information, temperature sensor position information, CPU type information, and target program constraint information;
a debug control unit configured to instruct the semiconductor device to execute the target programs;
a temperature measurement control unit configured to acquire a plurality of temperature data measured by the plurality of temperature sensors;
a temperature data analysis unit configured to determine, from the plurality of CPUs, at least one CPU where a number of target programs executed is to be decreased, as a first change target CPU and at least one CPU where the number of target programs executed is to be increased, as a second change target CPU, based on the plurality of temperature data, the CPU position information, and the temperature sensor position information; and
a program allocation unit configured to change allocation of the target programs executed by the plurality of CPUs based on the first change target CPU, the second change target CPU, the CPU type information, and the target program constraint information,
wherein the CPU position information comprises information for identifying a position of the plurality of CPUs in the semiconductor device,
wherein the temperature sensors position information comprises information for identifying a position of the plurality of temperature sensors in the semiconductor device,
wherein the CPU type information comprises information for identifying a type of the plurality of CPUs, and
wherein the target program constraint information comprises information used in determining whether to change the allocation of the target programs executed by the plurality of CPUs.