Patent ID: 11875059
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 1:
2. The memory system according to claim 1, wherein
a power state of the memory system available in the low power mode includes at least a first non-operational power state and a second non-operational power state having lower power consumption than that of the first non-operational power state;
the first non-operational power state is a power state in which the supply of power to at least the nonvolatile memory is maintained, and the second non-operational power state is a power state in which the supply of power to each of the components of the controller except for the first interface circuit, the second interface circuit, and the first volatile memory is stopped, and the supply of power to the nonvolatile memory is stopped; and
the controller is configured to:
execute, when a power state designated by the host as the low power mode to which the memory system should transition is the second non-operational power state, a first operation of acquiring the first data from the nonvolatile memory and a second operation of storing the acquired first data in the first volatile memory before causing the memory system to transition from the normal mode to the low power mode; and
cause, when the power state designated by the host is the first non-operational power state, the memory system to transition from the normal mode to the low power mode without performing the first operation and the second operation when the power state designated by the host is the first non-operational power state.