Patent ID: 11955564
Assignee: NANYA TECHNOLOGY CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for fabricating semiconductor device, comprising:
providing a substrate;
forming a tunneling insulating layer over the substrate;
forming a floating gate over the tunneling insulating layer;
forming a dielectric layer over the floating gate;
forming a control gate over the dielectric layer;
performing a lateral oxidation process over the substrate to transform the dielectric layer into a lateral oxidized intervention layer, wherein a process temperature of the lateral oxidation process is between about 300° C. and about 600° C.;
forming a plurality of doped regions in the substrate and adjacent to sides of the tunneling insulating layer;
forming a plurality of lightly-doped regions in the substrate and adjacent to sides of the lateral oxidized intervention layer;
forming a plurality of diffusion regions in the substrate and between adjacent pairs of the plurality of lightly-doped regions;
forming a first well region in the substrate, wherein the plurality of doped regions are in the first well region; and
forming a second well region in the substrate and separated from the first well region, wherein the control gate, the plurality of lightly-doped regions, and the plurality of diffusion regions are in the second well region.