Patent ID: 11862258
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A memory device comprising:
a memory block including a plurality of memory cells connected to a plurality of word lines; and
a control circuit configured to:
program selected memory cells connected to a selected word line among the plurality of word lines by applying a program voltage to the selected word line,
apply a first verification pass voltage to unselected word lines while applying a first verification voltage to the selected word line to verify a first program state of the selected memory cells, and
apply a second verification pass voltage, which is higher than the first verification pass voltage to the unselected word lines while applying a second verification voltage, which is higher than the first verification voltage to the selected word line to verify a second program state higher than the first program state of the selected memory cells.