Patent ID: 11887670
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 15:
16. An apparatus, comprising:
a set of memory cells connected to a selected word line, each memory cell is arranged in a respective NAND string of a set of NAND strings;
a set of bit lines, each bit line is connected to a respective NAND string in the set of NAND strings; and
a first voltage source configured to apply a program-inhibit voltage signal to selected bit lines in the set of bit lines, the first voltage source is configured to increase the program-inhibit voltage signal from an initial voltage to a program-inhibit voltage and, when a program pulse is applied to the selected word line in a program operation, to maintain the program-inhibit voltage signal at the program-inhibit voltage, the increasing of the program-inhibit voltage signal is a function of a number of bits per memory cell to be stored in the set of memory cells in the program operation such that the program-inhibit voltage signal is increased at a first rate when programming a single bit per memory cell and increased at a second rate when programming multiple bits per memory cell, the first rate is less than the second rate.