Patent ID: 11910611
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 5:
6. A nonvolatile memory device comprising:
a substrate including a cell region and a peripheral circuit region;
a stacked structure on the cell region, the stacked structure including a ground selection line, a plurality of word lines and a string selection line stacked sequentially from a top surface of the substrate, the plurality of word lines including a first word line being a lowermost word line of the plurality of word lines and being a word line most adjacent to the ground selection line;
a semiconductor pattern penetrating through the stacked structure;
a peripheral circuit element on the peripheral circuit region;
an interlayer insulating film covering the stacked structure and the peripheral circuit region on the substrate;
a lower contact connected to the peripheral circuit element in the interlayer insulating film;
an upper contact being connected to the lower contact on the lower contact; and
a cell contact penetrating through the interlayer insulating film and connected to the ground selection line,
wherein a height of a top surface of the lower contact being higher than a top surface of the ground selection line, and being lower than or equal to a height of a bottom surface of the first word line, the upper contact has a bottom surface below the top surface of the lower contact and the bottom surface of the upper contact is within the lower contact, and
wherein a bottom surface of the cell contact is below the top surface of the lower contact and in direct contact with the ground selection line.