Patent ID: 11929424
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A method, comprising:
forming a nanostructured pedestal on a substrate, the nanostructured pedestal having a top surface and opposite side surfaces;
forming a dielectric layer wrapping around the top surface and the opposite side surfaces of the nanostructured pedestal;
forming a metal layer over the dielectric layer;
forming a dielectric cap over the metal layer;
forming doped epitaxial structures on the nanostructured pedestal and sandwiching the dielectric layer, the metal layer, and the dielectric cap;
performing a first zero bias plasma etching process to the dielectric cap; and
after performing the first zero bias plasma etching process, performing a first non-zero bias plasma etching process to the dielectric cap.