Patent ID: 11915928
Assignee: KIOXIA CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 3:
4. The semiconductor memory device according to claim 1, wherein
the plurality of interlayer insulating layers include a third interlayer insulating layer and a fourth interlayer insulating layer adjacent in the first direction, and
the plurality of conductive layers include a second conductive layer disposed between the third interlayer insulating layer and the fourth interlayer insulating layer, wherein
the second conductive layer includes:
a fifth region;
a sixth region disposed between the fifth region and the gate insulating film; and
a seventh region disposed between the fifth region and the third interlayer insulating layer, wherein

the fifth region to the seventh region contain a metal,
the seventh region contains silicon (Si),
the fifth region does not contain silicon (Si) or has a lower silicon (Si) content than a silicon (Si) content in the seventh region, and
the sixth region does not contain silicon (Si) or has a lower silicon (Si) content than the silicon (Si) content in the seventh region.