Patent ID: 11870448
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A phase locked loop (PLL) comprising:
a current source having a current input and a current output, wherein the current source is configured to output a current at the current output having a magnitude IC dependent on a center frequency FC of a PLL bandwidth;
a phase frequency detector (PFD) and charge pump (CP) having a clock input, a feedback input, and a CP output, wherein the PFD and CP is configured to receive a clock signal having frequency FCLK at the clock input and to receive a feedback signal at the feedback input, the PFD and CP is configured to couple the CP output to the current output or to a ground terminal responsive to a phase difference between the clock signal and the feedback signal;
a compensation network having a compensation input and including a capacitive element and a resistive element, wherein the resistive element has a resistance dependent on FC;
a transconductance stage having a transconductance input and a transconductance output, wherein the transconductance input is coupled to the CP output and the compensation input, and the transconductance stage has a transconductance dependent on FC and is configured to provide a current with magnitude Igm;
a current controlled oscillator having an oscillator input and an oscillator output, wherein the oscillator input is coupled to the transconductance output and to the current output, the oscillator output is coupled to the feedback input, and the oscillator is configured to generate the feedback signal with a frequency FFB responsive to IC and Igm; and
a voltage input terminal configured to receive an input voltage;
an error amplifier having first and second amplifier inputs and an amplifier output;
a constant voltage source having a constant voltage output coupled to the first amplifier input; and
a first transistor having first and second current terminal and a first control terminal, wherein the first current terminal is coupled to the voltage input terminal, the second current terminal is coupled to the ground terminal and to the second amplifier input;
wherein the resistive element is a second transistor having a second control terminal, and the second control terminal is coupled to the first control terminal and to the amplifier output.