Patent ID: 11947483
Assignee: XCONN TECHNOLOGIES HOLDINGS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 3:
4. A switch, comprising:
a plurality of ports through which transactions ingress and egress the switch;
a plurality of port logic modules coupled with the plurality of ports, each port logic module having core clock domain logic for a core clock domain specific to a corresponding port of the plurality of ports, wherein each port control logic module includes routing logic, the routing logic configured to allow a response transaction to bypass a request transaction and to prevent the request transaction from bypassing the response transaction, wherein the routing logic including a router, a request bypass queue coupled to the router, and an arbitrator coupled with the router and the request bypass queue, the router configured to route the response transaction to an interface coupled with the corresponding port, to route the request transaction to the arbitrator if the interface can receive transactions, and to route the request transaction to the request bypass queue if the interface cannot receive the transactions, the arbitrator configured to forward an older request transaction from the router or the request bypass queue;
a memory including a plurality of banks; and
a switch fabric, wherein the memory and the switch fabric have a system clock domain, the core clock domain for each of the plurality of port logic modules being different from the system clock domain.