Patent ID: 11934942
Assignee: REBELLIONS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. A neural processing device comprising processing circuitry comprising:
a plurality of processing engines, each of the plurality of processing engine including a processing element (PE) array of a plurality of processing elements interconnected by a mesh style network, at least one first memory configured to store data for the PE array, at least one second memory configured to provide instructions for operating the plurality of processing elements, and at least one load/store unit (LSU) configured to perform load and store for the data, wherein the plurality of processing elements being reconfigurable;
a third memory shared by the plurality of processing engines;
an interconnection configured to transmit data between the third memory and the plurality of processing engines; and
a compiler stack configured to quantize a deep learning graph to generate a binary code based on a preset calculation code; and
wherein the compiler stack comprises a first compiler configured to compile operations of the plurality of processing engines and a second compiler configured to compile operations of the first memory, the interconnection and the at least one of the plurality of processing engines, and
wherein the first compiler is further configured to determine a dimension of the plurality of processing engines and perform, on a circuit, optimization scheduling of the plurality of processing engines.