Patent ID: 11895832
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 6:
7. A memory integrated circuit, comprising:
a first DRAM array and a second DRAM array, disposed at the same height, and laterally spaced apart from each other by a spacing in between;
a driving circuit disposed below the first and second DRAM arrays, and comprising sense amplifiers; and
routing elements, connecting bit lines of the first and second DRAM arrays to input lines of the sense amplifiers through the spacing, and comprising connection patterns laterally extending between the driving circuit and the first and second DRAM arrays above the driving circuit, wherein the input lines and the bit lines extend along a first direction, the connection patterns each have a length along a second direction, and the length is equal to or greater than a pitch of the input lines.