Patent ID: 11894446
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A semiconductor device, comprising:
a plurality of semiconductor wires;
a bottom fin structure protruding from a semiconductor substrate, over which the plurality of semiconductor wires are disposed;
a gate dielectric layer wrapping around each of the plurality of semiconductor wires;
a gate electrode layer disposed over the gate dielectric layer;
a source/drain region which is a source/drain semiconductor fin structure;
a source/drain epitaxial layer wrapping the source/drain semiconductor fin structure;
an isolation insulating layer from which the source/drain semiconductor fin structure protrudes; and
sidewall spacers disposed on opposite side faces of the gate electrode layer,
wherein the bottom fin structure and the source/drain semiconductor fin structure are continuously formed of a same semiconductor material, wherein a cross sectional shape of an uppermost one of the plurality of semiconductor wires has a tear-drop shape and has a largest area among the plurality of semiconductor wires.