Patent ID: 11908430
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 4:
5. The display substrate according to claim 1, wherein the shift register unit further comprises a clock signal connection line extending along the second direction, the clock signal connection line is configured to provide a clock signal to the output circuit;
the output circuit comprises a fourth transistor and a first capacitor;
a gate electrode of the fourth transistor and a first electrode of the first capacitor are disposed in the first conductive layer, and the first electrode of the first capacitor is on a side of the gate electrode of the fourth transistor close to a display region of the display substrate;
a first electrode of the fourth transistor, a second electrode of the fourth transistor, a second electrode of the first capacitor, and the clock signal connection line are all disposed in the second conductive layer;
the gate electrode of the fourth transistor is electrically connected to the second electrode of the third transistor, the first electrode of the fourth transistor is connected to the clock signal connection line to receive the clock signal, and the second electrode of the fourth transistor is connected to the first electrode of the second transistor;
the first electrode of the first capacitor is connected to the gate electrode of the fourth transistor, and the second electrode of the first capacitor is connected to the second electrode of the fourth transistor;
the fourth transistor comprises a plurality of sub-transistors connected in parallel along the second direction, each of the plurality of sub-transistors comprises a gate electrode disposed in the first conductive layer, a first electrode and a second electrode disposed in the second conductive layer, and an active layer disposed in the semiconductor layer; and
gate electrodes of the plurality of sub-transistors are connected to each other, first electrodes of the plurality of sub-transistors are connected to each other, second electrodes of the plurality of sub-transistors are connected to each other, and active layers of the plurality of sub-transistors are sequentially arranged along the second direction and are independent and unconnected with each other.