Patent ID: 11881518
Assignee: WINBOND ELECTRONICS CORP.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A fabricating method of a gate structure, comprising:
providing a substrate divided into a N-type transistor region and a P-type transistor region, an interlayer dielectric covering the N-type transistor region and the P-type transistor region, a first trench disposed in the interlayer dielectric within the N-type transistor region, a second trench disposed in the interlayer dielectric within the P-type transistor region, and a gate dielectric layer covering the first trench and the second trench, wherein the gate dielectric layer in the first trench forms a U-shaped profile;
forming a P-type work function layer covering the second trench, wherein the P-type work function layer is not formed in the first trench;
performing a first removing process to remove the P-type work function layer at a upper portion of the second trench;
after performing the first removing process, forming a N-type work function layer covering the first trench and the second trench;
forming a metal layer on the N-type work function layer on the first trench and the second trench;
performing a second removing process to remove part of the gate dielectric layer, part of the metal layer, part of the N-type work function layer to make a topmost surface of the gate dielectric layer, a topmost surface of the metal layer and a topmost surface of the N-type work function layer lower than a top surface of the interlayer dielectric; and
performing a third removing process to remove part of the N-type work function layer, thin two ends of the gate dielectric layer in the first trench, and round the metal layer to make the metal layer protrude out of the N-type work function layer, and to make the metal layer in the first trench become a bullet-shaped profile under a cross-sectional view and the metal layer in the second trench become a mushroom-shaped profile under a cross-sectional view, and to make the gate dielectric layer in the first trench has two different thicknesses.