Patent ID: 11899944
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 4:
5. An apparatus, comprising:
a non-volatile memory;
a volatile memory configured to operate as a cache for the non-volatile memory; and
an interface controller coupled with the non-volatile memory and the volatile memory, the interface controller operable to cause the apparatus to:
receive, from a host device, a command indicating that the apparatus is to transition from a power state in which the apparatus operates the volatile memory in a power mode for the volatile memory and the non-volatile memory in a power mode for the non-volatile memory;
transition, based at least in part on the command, the volatile memory from the power mode for the volatile memory to an idle power mode for the volatile memory that consumes more power than the power mode for the volatile memory;
transition, based at least in part on the command, the non-volatile memory from the power mode for the non-volatile memory to a first idle power mode for the non-volatile memory that consumes more power than the power mode for the volatile memory and that consumes less power than a second idle power mode for the non-volatile memory;
determine that data associated with an access command from the host device is stored in the non-volatile memory based at least in part on determining that the data associated with the access command from the host device is not stored in the volatile memory, wherein a quantity of commands queued for the non-volatile memory is increased based at least in part on the determination;
determine that the quantity of commands queued for the non-volatile memory has increased from a first quantity to a second quantity; and
transition the non-volatile memory from the first idle power mode to the second idle power mode or an active mode that consumes more power than the second idle power mode based at least in part on determining that the quantity of commands queued for the non-volatile memory has increased from the first quantity to the second quantity.