Patent ID: 11967374
Assignee: HEFEI RELIANCE MEMORY LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory circuit comprising:
an array of random access memory cells;
a low-impedance voltage source configured to provide a precharge voltage;
a control circuit configured to precharge a bit line of one of the random access memory cells to the precharge voltage using the low-impedance voltage source prior to reading the one of the random access memory cells; and
an on/off switch disposed between the low-impedance voltage source and the bit line of the one of the random access memory cells;
wherein the control circuit is configured to control the on/off switch to electrically couple the low-impedance voltage source to the bit line until the bit line reaches the precharge voltage, and to electrically decouple the low-impedance voltage source from the bit line prior to reading the one of the random access memory cells.