Patent ID: 11869626
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 0:
1. An apparatus, comprising:
a substrate;
a first memory die on the substrate and coupled to the substrate via a first external data link;
a second memory die on the first memory die, the second memory die coupled to the first memory die via a first internal data link and configured to communicate signals indicative of data via the first internal data link;
a third memory die on the second memory die and coupled to the substrate via a second external data link; and
a fourth memory die on the third memory die, the fourth memory die coupled to the third memory die via a second internal data link and configured to communicate signals indicative of data via the second internal data link;
wherein the first memory die is configured to communicate via the first external data link:
signals indicative of data from the first memory die and the signals indicative of data from the second memory die via the first external data link;
a first signal indicative of data from the first memory die during a first portion of a burst length;
a second signal indicative of data from the second memory die during a second portion of the burst length;
a third signal indicative of data from the first memory die during a third portion of the burst length; and
a fourth signal indicative of data from the second memory die during a fourth portion of the burst length; and

wherein the third memory die is configured to communicate signals indicative of data from the third memory die and the signals indicative of data from the fourth memory die via the second external data link.