Patent ID: 11907377
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. A semiconductor apparatus comprising:
one or more substrates; and
logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable logic or fixed-functionality hardware logic, the logic coupled to the one or more substrates to:
set a write protection flag in a guest command buffer associated with a virtual machine,
inject a semaphore command into a shadow command buffer in response to a fault, wherein the fault is to correspond to a write of a graphics command to the guest command buffer by code executing in graphics hardware,
conduct a security scan of the graphics command in response to a context switch in the graphics hardware, wherein the context switch is to be associated with the semaphore command, and
overwrite the semaphore command with the graphics command if the security scan does not detect a security risk in the graphics command.