Patent ID: 11949415
Assignee: NANJING INSTITUTE OF INTELLIGENT TECHNOLOGY
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A logic operation circuit for computation in memory, comprising: an equivalent circuit input terminal, a reference circuit input terminal, a reset input terminal and an output terminal;
wherein the equivalent circuit input terminal is configured to input the equivalent voltage of a memory computing array, the reset input terminal is configured to input a reset voltage, and the reference circuit input terminal is configured to input a reference voltage;
the logic operation circuit for computation in memory outputs different output voltages according to the difference between the equivalent voltage and the reference voltage, and the output voltage is output through the output terminal;
wherein the logic operation circuit for computation in memory further comprises: a first NOR gate, a second NOR gate, a first inverter and a second inverter; wherein the output terminal comprises a first output terminal and a second output terminal;
wherein a first input terminal of the first NOR gate and a first input terminal of the second NOR gate are both connected to the reset input terminal, a second input terminal of the first NOR gate is connected to the equivalent circuit input terminal, a third input terminal of the first NOR gate is connected to the output terminal of the second NOR gate, a second input terminal of the second NOR gate is connected to the reference circuit input terminal, and a third input terminal of the second NOR gate is connected to the output terminal of the first NOR gate;
an output terminal of the first NOR gate is connected to an input terminal of the first inverter, an output terminal of the first inverter is connected to the first output terminal; an output terminal of the second NOR gate is connected to an input terminal of the second inverter, and an output terminal of the second inverter is connected to the second output terminal;
wherein when the reset input terminal is set to a high potential, the first output terminal and the second output terminal are both at a high potential, and the logic operation circuit for computation in memory keeps in a set state; when the reset input terminal remains at a low potential, the logic operation circuit for computation in memory enters a calculation state.