Patent ID: 11967357
Assignee: NATIONAL TSING HUA UNIVERSITY
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 10:
11. The memory unit with time domain edge delay accumulation for computing-in-memory applications of claim 10, wherein the at least one edge-delay cell multiplexor further comprises:
a third edge-delay cell multiplex transistor connected between the first-column local bit line and the selected local bit line;
a fourth edge-delay cell multiplex transistor connected between the first-column local bit line bar and the selected local bit line bar;
a fifth edge-delay cell multiplex transistor connected between the second-column local bit line and the selected local bit line; and
a sixth edge-delay cell multiplex transistor connected between the second-column local bit line bar and the selected local bit line bar;
wherein the third edge-delay cell multiplex transistor and the fourth edge-delay cell multiplex transistor are controlled by a first selecting signal, the fifth edge-delay cell multiplex transistor and the sixth edge-delay cell multiplex transistor are controlled by a second selecting signal, and the first selecting signal is opposite to the second selecting signal.