Patent ID: 11860716
Assignee: KABUSHIKI KAISHA TOSHIBA
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An information processing apparatus, comprising:
a processing circuit configured to
calculate a first input/output error related to normal data and a second input/output error related to pseudo abnormal data different from the normal data, for each autoencoder of a plurality of autoencoders, each autoencoder having a different network structure, wherein the normal data is data output by a factory machine or an inspection device of the factory machine when the factory device normally operates, and the pseudo abnormal data is data output by the factory machine or the inspection device when the factory device abnormally operates, and
for each autoencoder, output relational data indicating a relation between the network structure of the autoencoder and the first input/output error and the second input/output error,

wherein the processing circuit is further configured to
calculate first output data by applying the normal data to each of the plurality of autoencoders, and calculate the first input/output error based on the first output data and the normal data; and
calculate second output data by applying the pseudo abnormal data to each of the plurality of autoencoders, and calculate the second input/output error based on the second output data and the normal data.