Patent ID: 11929339
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC H  G  Y | IPC G  H

Claim 16:
17. An integrated circuit device comprising:
a first electrical trace;
a second electrical trace;
a first die, coupled to the first and second electrical traces, comprising a first plurality of package bumps; and
a second die, coupled to the first and second electrical traces, comprising a second plurality of package bumps, wherein the first plurality of package bumps in a first two-dimensional array and the second plurality of package bumps in a second two-dimensional array, the first two-dimensional array of package bumps having a first pitch in a first dimension of the first two-dimensional array being different than a second pitch of the second two-dimensional array, the first electrical trace couples a first package bump of the first plurality of package bumps with a second package bump of the second plurality of package bumps, and the second electrical trace couples a third package bump of the first plurality of package bumps with a fourth package bump of the second plurality of package bumps.