Patent ID: 11921667
Assignee: BEIJING ESWIN COMPUTING TECHNOLOGY CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. A reconfigurable computing chip, comprising:
a processing module comprising a plurality of processing cores sharing a first cache, wherein each of the plurality of processing cores includes a plurality of processing elements sharing a second cache, and each of the plurality of processing elements monopolizes a third cache corresponding to said processing element,
wherein the reconfigurable computing chip is dynamically configured to perform a convolution process on an input feature map and a convolution kernel to obtain an output feature map, and each of the plurality of processing elements is dynamically configured to perform a multiplication-plus-addition process on a part of the input feature map and a part of the convolution kernel to obtain a part of the output feature map.