Patent ID: 11941407
Assignee: GSI TECHNOLOGY INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. A unit for accumulating a plurality N of multiplied M bit values, the unit comprising:
a receiving unit to receive a pipeline of multiplicands A and B such that, at each cycle, a new set of multiplicands is received;
a bit-wise multiplier to bit-wise multiply bits of a current multiplicand A with bits of a current multiplicand B and to handle sum and carry values between bits; and
a bit-wise accumulator to accumulate output of said bit-wise multiplier thereby to accumulate said multiplicands during the pipelining process,
wherein said bit-wise multiplier comprises:
M rows of M multiplication units each, each multiplication unit to separately multiply each bit of said multiplicand A with each bit of said multiplicand B and to separately sum results from a previous row of said multiplication units; and
M rows of summing units following said M rows of multiplication units, each row comprising M summing units, each summing unit to separately sum results from a previous row of said summing units or said multiplication units, said rows summing output towards said bit-wise accumulator.