Patent ID: 11965931
Assignee: INVENTEC (PUDONG) TECHNOLOGY CORPORATION
Field: Measurement (Instruments)
Classification: CPC G | IPC G

Claim 5:
6. A dummy dual in-line memory module testing method based on boundary scan interconnect, wherein the dummy dual in-line memory module testing method is applied to boundary scan test environment where a dummy dual in-line memory module, a dummy dual in-line memory module under test, a test access port (TAP) device and a test device are disposed, and the dummy dual in-line memory module testing method comprises:
inserting the dummy dual in-line memory module into the test device to serve as a test fixture, wherein all functions of the test fixture are normal;
inserting the dummy dual in-line memory module under test into the test device to serve as a unit under test;
electrically connecting the test access port (TAP) device to a terminal machine executing a test program, to electrically connect signal pins of the test access port (TAP) device to the test device, and transmitting a control signal to the test device through the signal pins, wherein the signal pins comprise a test data in pin, a test data out pin, a test clock pin, and a test mode select pin;
connecting the test device to a DC power supply, wherein when the test program performs a test, the DC power supply continuously supplies power to the first slot and the second slot, and when the test is finished, the DC power supply stops supplying power to the first slot and the second slot;
receiving the control signal from the test access port (TAP) device, to control the test fixture to test the unit under test through the boundary scan, by the test device, wherein when the test program is executed, the data signal, which is collected from at least one boundary scan register, is transmitted to the test access port (TAP) device through the signal pin, to check a test result.