Patent ID: 11942523
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 19:
20. The method of claim 13 further comprising:
forming a plurality of semiconductor layers over a substrate;
patterning the semiconductor layers to form the first nanostructure, a second nanostructure, and a third nanostructure, the first nanostructure disposed between the second nanostructure and the third nanostructure;
patterning the substrate to form a fin, the first nanostructure disposed over the fin; and
removing portions of the second nanostructure and the third nanostructure to expose a top and a bottom of the first nanostructure, the gate stack being formed on the top and the bottom of the first nanostructure.