Patent ID: 11876782
Assignee: NVIDIA CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 9:
10. A system comprising:
a plurality of processors comprising a first processor and a second processor; and
memory comprising instructions that, when performed by the plurality of processors:
cause the first processor to at least receive a first set of network packet data from a network interface, analyze the first set of network packet data to determine one or more status values associated with the first set of network packet data, and transmit the one or more status values to the second processor; and
cause the second processor to at least receive a second set of network packet data from the network interface, update a set of rules based at least in part on the one or more status values, and process the second set of network packet data based, at least in part, on the set of rules, wherein the network interface received a received set of the first or second sets of network packet data and duplicated the received set to create another of the first or second sets of network packet data.