Patent ID: 11935580
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A device comprising:
memory having sense amplifiers and precharge blocks arranged in an array with a first side and a second side, wherein the first side includes first sense amplifiers and first precharge blocks coupled together with first bitlines, and wherein the second side includes second sense amplifiers and second precharge blocks coupled together with second bitlines;
a first delay block coupled to the first precharge blocks in the first side of the array, wherein the first delay block is configured to delay precharge of the first bitlines with a first precharge burst in a multi-burst precharge event;
a second delay block coupled to the second precharge blocks in the second side of the array, wherein the second delay block is configured to delay precharge of the second bitlines with a second precharge burst in the multi-burst precharge event; and
a control block that provides a precharge signal to the first precharge blocks in the first side of the array for precharging of the first bitlines to a supply voltage,
wherein the first precharge blocks are configured to provide the precharge signal to the second precharge blocks.