Patent ID: 11972121
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G

Claim 1:
2. The stacked-die memory component of claim 1 further comprising one or more additional memory dies coupled to the inter-die signaling path and disposed in a stack that includes the base die, each of the one or more additional memory dies having:
circuitry to receive the chip-identifier value via the one or more chip-identifier lines and to either assert or deassert an additional-memory-die control signal according to whether the chip-identifier value matches or does not match, respectively, a resident identifier value of the additional memory die;
circuitry to receive the command/address value via the one or more command/address lines if the additional-memory-die control signal is asserted and to disable reception of the command/address value if the additional-memory-die control signal is deasserted.