Patent ID: 11914998
Assignee: REALTEK SEMICONDUCTOR CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. The processing circuit of claim 7, wherein the instruction decode unit is further configured to decode a second load instruction included in the load instructions to generate a second decoding result, and the second load instruction is different from the first load instruction; the address generator is configured to generate a second address requested by the second load instruction according to the second decoding result; the data buffer comprises:
a control circuit, coupled to the address generator, the control circuit being configured to determine whether the second address matches the first address, and output the first address when the second address matches the first address; and
a logic circuit, coupled to the instruction detector, the address generator and the control circuit, the logic circuit being configured to store the first address and the trend of change when the instruction detector determines that the first load instruction is the prefetch candidate, and increment the count value when the second address outputted from the control circuit matches the first address.