Patent ID: 11909566
Assignee: SOOCHOW UNIVERSITY
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 3:
4. The method for designing a complex-valued channel equalizer according to claim 3, wherein a specific process of “appropriately adjusting the value of M according to a change trend of the optimal memory size selected in several previous iterations” comprises:
given a window size W, calculating a predicted value mf,t* of the memory size at the current iteration according to a formula, m
    
     f
     ,
     t
    
    *
   
   =
   
    
     
      m
      
       t
       -
       W
      
      *
     
     +
     
      m
      
       t
       -
       W
       +
       1
      
      *
     
     +
     ⋯
     +
     
      m
      
       t
       -
       1
      
      *
     
    
    W
   
  
  ,, wherein mt* denotes the optimal memory size at iteration t; and
given constants c1 and c2, if mf,t*<c1M, M=M−1; if mf,t*>(1−c2)M, M=M+1; or otherwise, M is kept unchanged.