Patent ID: 11862240
Assignee: GLOBALFOUNDRIES U.S. INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 7:
8. A circuit structure comprising:
a first latch having an input node and an output node;
a second latch having an input node and an output node, wherein the output node of the second latch is coupled to the input node of the first latch, and wherein the input node of the second latch is coupled to the output node of the first latch; and
a read/write (R/W) circuit including:
a first transistor having a first source/drain (S/D) terminal coupled to a bit line, a second S/D terminal coupled to the input node of the first latch, and a gate terminal coupled to a word line,
a second transistor having a first S/D terminal coupled to the bit line, a second S/D terminal coupled to the output node of the first latch, and a gate terminal coupled to the word line,
a third transistor having a first S/D terminal coupled to an inverted bit line, a second S/D terminal coupled to the input node of the second latch, and a gate terminal coupled to the word line, and
a fourth transistor having a first S/D terminal coupled to the inverted bit line, a second S/D terminal coupled to the output node of the second latch, and a gate terminal coupled to the word line,

wherein the R/W circuit is configured to write a same bit to the first latch and the second latch simultaneously.