Patent ID: 11901891
Assignee: KEPLER COMPUTING INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 12:
13. The apparatus of claim 11, wherein the gate comprises:
a first transistor, the first transistor having a first source region and a first drain region, and a first gate, wherein the first gate is controllable by a first control;
a second transistor, the second transistor having a second source region and a second drain region, and a second gate, wherein the second gate is controllable by a second control;
a first via is coupled to the first source region;
a second via is coupled to the first drain region;
a first metal layer over the first via, the first metal layer extending along an x-plane;
a second etch stop layer over the first metal layer;
a third via, over the first metal layer, and etched through the second etch stop layer, the third via in direct connection to the first metal layer;
a second metal layer extending along the x-plane, wherein the second metal layer is above the first metal layer, wherein the second metal layer couples the third via;
an interlayer dielectric between the first metal layer and the second metal layer;
a first pedestal filled with metal, wherein the first pedestal is coupled to the second metal layer;
a first plurality of layers to form a first planar capacitor, wherein the first plurality of layers includes a first ferroelectric dielectric material, wherein a first layer of the first plurality of layers is in contact with a top portion of the first pedestal, wherein a second layer of the first plurality of layers is coupled to a first input line, and wherein the first input line is coupled to the first input;
a fourth via in direct connection to the second metal layer;
a third metal layer over the fourth via, wherein the first plurality of layers is between the second metal layer and the third metal layer;
a second pedestal filled with metal, wherein the second pedestal is coupled to the third metal layer; and
a second plurality of layers to form a second planar capacitor, wherein the second plurality of layers includes a second ferroelectric dielectric material, wherein a first layer of the second plurality of layers is in direct contact with a top portion of the second pedestal, wherein a second layer of the second plurality of layers is coupled to a second input line, and wherein the second input line is coupled to the second input.