Patent ID: 11875874
Assignee: GROQ, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A memory structure, comprising:
a first memory substructure storing at least first data;
a second memory substructure that provides at least reconstructed data of the first data;
a first multiplexor having inputs connected to the first memory substructure and the second memory substructure, and an output connected to a first port;
a second multiplexor having inputs connected to the first memory substructure and the second memory substructure, and an output connected to a second port; and
a conflict control circuit to:
configure the first multiplexor to provide data of the first data to the first port, responsive to a read request to read data of the first data through the first port, regardless of whether there is a concurrent read request to read data of the first data through the second port;
configure the second multiplexor to:
provide reconstructed data of the first data to the second port, responsive to concurrent read requests to read data of the first data through the first port and through the second port, and
provide data of the first data to the second port responsive to a read request to read data of the first data through the second port if there is no concurrent read request to read data of the first data through the first port.