Patent ID: 11908505
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 6:
7. The data processing device of claim 6, further comprising:
a search data input interface input interface adapted to supply binary digital signals to the plurality of INs;
a storage data output interface adapted to supply to receive from the BLs signals indicative of the data stored in the data storage units; and
a match output interface adapted to receive signals from the output ends of the matchlines and generate an output signal indicative of the signals from the output ends of the matchlines,, wherein the storage data input interface and storage data output interface are adapted to:
simultaneously store binary “0”s in the FeFETs in the first storages units of a first subset of memory cells in a column of the memory cells in a first phase; and
simultaneously store binary “1”s in the FeFETs in the first storages units of a second subset of memory cells in the column of memory cells in a second phase, the first and second subset being mutually exclusive.