Patent ID: 11915045
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A processing unit, comprising:
a processor core capable of executing multiple simultaneous hardware threads;
a cache memory including a cache array: and
a store queue, disposed in the cache memory, for buffering store operations to be serviced by the cache array, wherein the store queue includes a plurality of store queue entries and is configured to perform:
receiving and buffering a store-type operation within a store queue entry among the plurality of store queue entries;
storing, in the store queue entry, a thread identifier indicating a particular hardware thread among the multiple hardware threads that issued the store-type operation;
storing, in the store queue entry, a first indication that the store queue entry is a most recently allocated store queue entry for buffering store-type operations of the particular hardware thread, wherein an extension of a duration of a store gathering window applicable to the store queue entry is based on the first indication and the store queue entry being the only one of the plurality of store queue entries currently allocated to buffer store-type operations of the particular hardware thread; and
performing store gathering within the store queue entry only for the particular hardware thread while prohibiting store gathering, within the store queue, for the other multiple threads during the store gathering window applicable to the store queue entry;
dispatching the store-type operation from the store queue entry for service by the cache memory after the store gathering window ends; and
updating the cache memory with the store data of the store-type operation.