Patent ID: 11887979
Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A method for manufacturing a transient voltage suppression device according to claim 1, wherein the method comprises:
forming a mask layer on the substrate of the second conductivity type, and then performing a lithography and etching the mask layer to expose a doping window of the first conductivity type well region;
doping the substrate with first conductivity type ions through the doping window of the first conductivity type well region to form a first region on a surface of the substrate;
growing an oxide layer as a doping blocking layer in the first region;
removing the mask layer, and doping areas of the surface of the substrate not covered by the doping blocking layer with second conductivity type ions to form a second region;
performing a thermal drive-in, so that a first diffusion occurs in the first region to form the first well, the second well, and the third well, and a second diffusion occurs in the second region to form the fourth well and the fifth well;
forming, by lithographing and doping with the second conductivity type ions, the Zener diode well region in the first well after the doping blocking layer is removed; and
forming, by lithographing and doping, respectively the first doped region, the second doped region, the third doped region, the fourth doped region, and the fifth doped region.