Patent ID: 11954580
Assignee: META PLATFORMS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 2:
3. The system of claim 2, wherein:
the cluster-level controller in the given cluster is configured to:
determine, based on the first multi-cycle instruction, (1) a first sequence of vector operations to be executed by the tensor processors in the given cluster and (2) address information usable to determine the respective spatial partition of an input tensor on which each tensor processor in the given cluster is to operate when performing each vector operation in the first sequence of vector operations; and
for each vector operation in the first sequence of vector operations:
generate, based on the address information, a common address offset, relative to a respective base address associated with each tensor processor in the given cluster, at which each tensor processor in the given cluster is to retrieve the respective spatial partition of the input tensor on which the tensor processor is to operate;
multicast the common address offset to the tensor processors in the given cluster; and
control the tensor processors in the given cluster to execute the vector operation in lock step;

each of the vector operations in the first sequence of vector operations comprises one or more of: a vector read operation, a vector addition operation, and a vector multiply operation; and
each tensor processor in the given cluster comprises a hardware compute array of multiply-and-accumulate (MAC) computation units configured to execute vector operations on the respective spatial partition of the input tensor on which the tensor processor is to operate when performing each vector operation in the first sequence of vector operations.