Patent ID: 11960887
Assignee: INTEL CORPORATION
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A system for packing variable length data comprising:
a shared memory to store a plurality of sequential pieces of data having variable bit lengths for packing, each piece of data comprising one or more bits including a lead bit, and at least some of the pieces of data having a corresponding bit shift value, each bit shift value to indicate a bit shift for each piece of current data to pack post-shift remainder bits from a piece of prior data before the lead bit of the piece of current data;
a graphics processing unit (GPU) having access to the shared memory, the GPU to execute, in parallel with individual ones of a plurality of execution units of the GPU, bit shift operations for each piece of current data having a bit shift value, wherein bit shift operations for each piece of current data are executed on a separate individual one of the execution units; and
a central processing unit (CPU) having access to the shared memory, the CPU to provide a first byte of packed variable length data to a CPU accessible memory, the first byte comprising the post-shift remainder bits from the piece of prior data packed with at least the lead bit of the piece of current data.