Patent ID: 11914523
Assignee: RADIAN MEMORY SYSTEMS, LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 25:
26. A storage device comprising:
flash memory having erase units, wherein the flash memory is to have one or more namespaces, one or more groups of subdivisions within at least one of the namespaces, each group having two or more of the subdivisions; and
logic to cause the storage device to:
transmit to a host, responsive to receipt of at least one command from the host, information to identify the specific one of the namespaces and the specific one of the groups; and
receive a first data write request and associated first address information from the host and a second data write request and associated second address information from the host;
responsive to the first data write request and associated first address information,
derive a first address portion from the associated address information, to identify the specific one of the namespaces,
perform one or more operations to subdivide the associated address information, to derive a second address portion and a third address portion,
identify the specific one of the groups from the second address portion,
obtain from the third address portion an identifier for a specific one of the subdivisions within the specific one of the groups,
map one or more of the erase units of the flash memory to the specific one of the subdivisions, and
write first data into one of the one or more erase units which are mapped to the specific one of the subdivisions;

responsive to the second data write request and associated second address information,
derive a first address portion from the associated second address information, to identify the specific one of the namespaces,
perform one or more operations to subdivide the associated second address information, to derive a second address portion and a third address portion,
identify the specific one of the groups from the second address portion which was derived from the associated second address information,
obtain from the third address portion the identifier,
write second data into one of the one or more erase units which are mapped to the specific one of the subdivisions;

wherein said logic comprises at least one of (1) instructional logic stored on a physical storage medium and (2) hardware logic.