Patent ID: 11881853
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. The circuit of claim 1, wherein the 1-bit compare circuit comprises at least:
a first part, which is logically combining the first input signal and the third input signal with a logical “A OR NOT B” operation creating a fifth signal;
a second part which is logically combining the second input signal and the fourth input signal with a logical “A OR NOT B” operation creating a sixth signal; and
a third part for logically combining the fifth signal and the sixth signal to a seventh signal as an output (CMP_R; CMP_R_C), with a logical NAND operation in the case of a precharge to “1” logic circuit to a seventh signal as an output (CMP_R), or with a logical NOR operation in the case of a precharge to “0” logic circuit to a seventh signal as an output (CMP_R_C).