Patent ID: 11899564
Assignee: RENESAS ELECTRONICS CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. A non-transitory computer-readable recording medium that stores a program to be executed in a debug apparatus that includes a processor and a memory, and debugs target programs including a plurality of programs operating in a semiconductor device including a plurality of Central Processing Units (CPUs) and a plurality of temperature sensors, the memory storing CPU position information, temperature sensor position information, CPU type information, and target program constraint information, the plurality of CPUs executing the target programs, the plurality of temperature sensors measuring temperature of the semiconductor device during execution of the target programs, the program performing a method comprising:
instructing the semiconductor device to execute the target programs;
acquiring a plurality of temperature data measured by the plurality of temperature sensors;
determining, from the plurality of CPUs, at least one CPU where a number of target programs executed is to be decreased, as a first change target CPU and at least one CPU where the number of target programs executed is to be increased, as a second change target CPU, based on the plurality of temperature data, the CPU position information, and the temperature sensor position information; and
changing allocation of the target programs executed by the plurality of CPUs based on the first change target CPU, the second change target CPU, the CPU type information, and the target program constraint information,
wherein the CPU position information comprises information for identifying a position of the plurality of CPUs in the semiconductor device,
wherein the temperature sensors position information comprises information for identifying a position of the plurality of temperature sensors in the semiconductor device,
wherein the CPU type information comprises information for identifying a type of the plurality of CPUs, and
wherein the target program constraint information comprises information used in determining whether to change the allocation of the target programs executed by the plurality of CPUs.