Patent ID: 11880687
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A system comprising:
an interconnection network;
a packet network;
a synchronous network;
a processor coupled to the interconnection network, the processor configured to generate and transmit a first work descriptor data packet on the interconnection network;
a plurality of configurable circuits arranged in an array, each configurable circuit of the plurality of configurable circuits coupled to the packet network and to the synchronous network, each configurable circuit of the plurality of configurable circuits comprising:
a configurable computation circuit; and
a configuration memory coupled to the configurable computation circuit, the configuration memory comprising:
a first instruction memory configured to store a first plurality of configuration instructions to configure the configurable computation circuit; and
a second instruction memory configured to store a second plurality of configuration instructions or instruction indices, the second plurality of configuration instructions or instruction indices comprising instructions or instruction indices for selection of a configuration instruction of the first plurality of configuration instructions from the first instruction memory and for selection of a synchronous network input from the synchronous network for receipt of the configuration instruction or a configuration instruction index from another configurable circuit of the plurality of configurable circuits of the array.