Patent ID: 11916561
Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 3:
4. The method of claim 3, wherein determining alignment between the first second-level clock signal and the first first-level clock signal further comprises:
receiving, at an input of a first phase-detector of a 2-bit phase detector, a replicated first first-level clock signal;
receiving, at an input of a second phase-detector of the 2-bit phase detector, a replicated second first-level clock signal, wherein the second first-level clock signal is phase shifted from the first first-level clock signal by a time-margin;
receiving, at the first and second phase-detectors, a replicated first second-level clock signal as a clock input;
producing a first phase-detector output indicative of a value of the first first-level clock signal; and
producing a second phase-detector output indicative of a value of the second first-level clock signal.