Patent ID: 11895835
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 15:
16. A method comprising:
forming a stack comprising an upper polysilicon-comprising layer, a lower polysilicon-comprising layer, a sacrificial-material layer vertically between the upper and lower polysilicon-comprising layers, an upper intermediate layer vertically between the upper polysilicon-comprising layer and the sacrificial-material layer, and a lower intermediate layer vertically between the lower polysilicon-comprising layer and the sacrificial-material layer;
the lower intermediate layer and the upper intermediate layer comprising at least one of (a), (b), and (c), where
(a): a hafnium oxide;
(b): a bilayer comprising silicon nitride and comprising silicon dioxide positioned vertically relative one another, the silicon nitride of the bilayer being closer to the sacrificial-material layer than is the silicon dioxide of the bilayer; and
(c): SiOxNy, where each of “x” and “y” is from 1 atomic percent to 90 atomic percent of the total of the Si, the O, and the N in the SiOxNy;

forming an opening through the upper polysilicon-comprising layer and the upper intermediate layer to the sacrificial-material layer; and
through the opening, selectively etching the sacrificial material of the sacrificial-material layer relative to the at least one of the (a), (b), and (c) to leave a void space vertically between the upper and the lower intermediate layers;
the lower intermediate layer and the upper intermediate layer comprising the (b); and
further comprising lining sidewalls of the opening with multiple layers individually comprising one of silicon nitride or silicon dioxide and sequentially etching away the multiple layers using different etching chemistries, one of the chemistries etching the silicon nitride of the multiple layers and another of the chemistries etching the silicon dioxide of the multiple layers.