Patent ID: 11886882
Assignee: MARVELL ASIA PTE LTD
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 22:
23. An integrated circuit for executing instructions, comprising:
a processor pipeline configured to execute instructions from two or more threads in parallel using execution units of the processor pipeline; and
means for managing dispatch of instructions, the managing comprising
detecting that a first instruction of a first thread has been dispatched into a pipeline stage of the processor pipeline,
responsive to detection of dispatch of the first instruction, blocking instructions of threads other than the first thread from being dispatched into one or more predetermined pipeline stages of the processor pipeline while the first instruction is being executed by an execution unit in at least one of the one or more predetermined stages of the processor pipeline and while one or more of the instructions of threads other than the first thread remain in the processor pipeline, and
responsive to completion of execution of the first instruction, enabling dispatch of instructions of threads other than the first thread into the one or more predetermined pipeline stages of the processor pipeline.