Patent ID: 11947889
Assignee: SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A chip placed in a full-custom layout, comprising a pipeline structure having a plurality of operation stages, wherein each operation stage includes:
a plurality of rows arranged sequentially in an X-direction parallel to a substrate of the chip and having a uniform row height in the X-direction, the plurality of rows including rows of a first type, each row of the first type including:
a first set of register modules, including a*b register modules arranged in the form of an array of a rows and b columns, wherein each register module has a first height in the X-direction, and the row height is a times of the first height, where a and b are positive integers; and
a first set of logical operation modules, including a*c logical operation modules arranged in the form of an array of a rows and c columns, wherein each logical operation module has the first height in the X-direction, where c is a positive integer;
wherein the first set of register modules and the first set of logical operation modules are adjacently provided in a Y-direction, and the first set of logical operation modules is used for processing data in the first set of register modules.