Patent ID: 11880933
Assignee: IMAGINATION TECHNOLOGIES LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. The graphics processing system of claim 11, further comprising coarse depth test logic circuitry comprising:
hidden depth test logic circuitry configured to:
receive a set of one or more primitives related to one of the plurality of tiles;
obtain a depth range for the tile, the depth range for the tile identifying a depth range based on primitives previously processed for the tile; and
for at least one primitive in the set of one or more primitives:
make a determination, based on the depth range for the tile, as to whether all or a portion of the primitive is hidden in the tile, wherein if a determination is made that at least a portion of the primitive is hidden in the tile, full resolution depth testing is not performed on that portion of the primitive in respect of the tile; and
in response to making a determination that at least a portion of the primitive is not hidden in the tile, outputting at least that portion of the primitive; and

front depth test logic circuitry configured to receive the primitives output by the hidden depth test logic circuitry, or one or more primitive fragments generated therefrom, and for at least one of the received primitives or at least one of the primitive fragments:
make a determination, based on the depth range for the tile, as to whether the primitive or primitive fragment has better depth than the primitives previously processed for the tile according to the depth compare mode; and
in response to making a determination that the primitive or primitive fragment has better depth than the primitives previously processed for the tile, identifying the primitive or primitive fragment as not requiring a read of a depth buffer to perform full resolution depth testing.