Patent ID: 11971316
Assignee: ROBERT BOSCH GMBH
Field: Measurement (Instruments)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A stress and/or strain measurement cell for a stress and/or strain measurement system, comprising:
a reference contact at which a reference current signal of the stress and/or strain measurement cell is provided;
a sensor contact at which a sensor current signal of the stress and/or strain measurement cell is provided; and
a first current mirror circuit integrated into a semiconductor material and having a first conduction path connectable or connected to the reference contact and a second conduction path connectable or connected to the sensor contact, wherein the first conduction path of the first current mirror circuit includes at least one first transistor, and the second conduction path of the first current mirror circuit includes at least one second transistor, a first gate terminal of the first transistor, a first drain terminal of the first transistor and a second gate terminal of the second transistor are at an identical potential;
wherein a first crystal direction of the semiconductor material oriented perpendicular to a first inversion channel of the first transistor is definable for the first inversion channel, and a second crystal direction of the semiconductor material oriented perpendicular to a second inversion channel of the second transistor is definable for the second inversion channel, wherein the first crystal direction of the semiconductor material is inclined relative to the second crystal direction of the semiconductor material,
wherein the first conduction path of the first current mirror circuit further includes a third transistor connected to the first drain terminal of the first transistor, and the second conduction path of the first current mirror circuit further includes a fourth transistor connected to a second drain terminal of the second transistor, and wherein a third gate terminal of the third transistor, a third drain terminal of the third transistor and a fourth gate terminal of the fourth transistor are at an identical potential,
wherein a third crystal direction of the semiconductor material oriented perpendicular to a third inversion channel of the third transistor, which is also oriented perpendicular to a fourth inversion channel of the fourth transistor, is definable for the third inversion channel.