Patent ID: 11900503
Assignee: IMAGINATION TECHNOLOGIES LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. The graphics processing unit of claim 11, wherein:
the first core comprises a slave unit, a first processing unit and a second processing unit;
the slave unit of the first core is configured to:
receive the first trigger,
split the first trigger into at least a third trigger and a fourth trigger, wherein the third trigger comprises an indication of a third starting primitive in the element buffer and an instruction to render a third number of primitives starting from the third starting primitive, and the fourth trigger comprises an indication of a fourth starting primitive in the element buffer and an instruction to render a fourth number of primitives starting from the fourth starting primitive,
send the third trigger to the first processing unit, and
send the fourth trigger to the second processing unit;

the first processing unit is configured to process the third trigger; and
the second processing unit is configured to process the fourth trigger.