Patent ID: 11881435
Assignee: BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G  B | IPC H

Claim 0:
1. A method for making multilayer nanostructures, the method comprising:
providing a semiconducting material comprising two or more layers;
patterning a catalyst layer on a surface of said semiconducting material, wherein said catalyst layer comprises ruthenium;
exposing said patterned catalyst layer to an etchant, wherein said patterned catalyst layer and said etchant cause etching of said semiconducting material to form vertical nanostructures, wherein said vertical nanostructures comprise two or more layers; and
selectively processing one or more of said two or more layers of said vertical nanostructures to either change its chemical composition or remove it.