Patent ID: 11869929
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 5:
6. The method for manufacturing a laminated capacitor of claim 2, wherein forming the connection structure on the sub-capacitor structure comprises:
forming the plurality of discrete bottom electrode connection spacers on the sub-capacitor structure;
forming the second isolation insulation spacer between the bottom electrode connection spacers, which has openings respectively exposing the top electrodes;
forming third isolation insulation columns respectively in the openings;
forming a sacrificial layer on the bottom electrode connection spacers, the second isolation insulation spacer, and the third isolation insulation columns; and
forming the sub-capacitor structure in the sacrificial layer, and forming the top electrode connection spacers respectively at locations of the third isolation insulation columns, wherein the top electrodes of the sub-capacitor structure and the top electrode connection spacers are integrally formed.