Patent ID: 11868298
Assignee: SIGMASENSE, LLC.
Field: Digital communication (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 10:
11. A non-transitory computer readable memory comprises:
a first storage section operable to store operational instructions that, when executed by a first processing entity, causes the first processing entity to:
obtain first data communication capabilities of a first host device, wherein the first host device and the first processing entity are associated with a first low voltage drive circuit;

a second storage section operable to store operational instructions that, when executed by a second processing entity, causes the second processing entity to:
obtain second data communication capabilities of a second host device, wherein the second host device and the second processing entity are associated with a second low voltage drive circuit; and

a third storage section operable to store operational instructions that, when executed by one or more of the first and second processing entities, causes the one or more of the first and second processing entities to:
reconcile the first and second data communication capabilities to produce reconciled data communication capabilities;
determine a data conveyance scheme for a one-to-one communication between the first and second low voltage drive circuits based on the reconciled data communication capabilities; and
determine a data communication scheme for the one-to-one communication between the first and second low voltage drive circuits based on the reconciled data communication capabilities.