Patent ID: 11869807
Assignee: APPLIED MATERIALS, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A processor-implemented method for forming fully self-aligned vias, the method comprising:
receiving data for a first configuration to control forming a first metallization line, the first metallization line having a first width;
receiving data for a second configuration to control forming an oversized via mask on a via metallization layer on the first metallization line, the oversized via mask comprising an extreme ultraviolet (EUV) trilayer on a hard mask layer, the via mask having a mask width and a mask length and the mask width greater than the first width of the first metallization line;
receiving data for a third configuration to control forming a via, the via having a via metal length that is equal to the mask width and having a via metal width that is equal to the first width; and
receiving data for a fourth configuration to control forming a second metallization line.