Patent ID: 11907061
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 9:
10. An apparatus, comprising:
a memory controller configured to cause the apparatus to:
identify a first set of data for communicating over a first channel between a memory device and a host device, the first channel associated with a channel width and the first set of data corresponding to a first burst length;
generate a first codeword for error correction or error detection based at least in part on at least a portion of the first set of data;
generate a second codeword for error correction or error detection based at least in part on the at least the portion of the first set of data and the first codeword; and
transmit, from the memory device or the host device, a second set of data that includes the first set of data, the first codeword, and the second codeword.