Patent ID: 11942474
Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 3:
4. The method according to claim 2, wherein,
patterning the semiconductor stack into a predetermined shape comprises:
forming a patterned hard mask layer on the semiconductor stack;
transferring the pattern of the hard mask layer to the semiconductor stack;
selectively etching the channel layers to recess the channel layers inward;
filling a sacrificial gate in a space formed by the recess of the channel layer below the hard mask layer;
forming, at least at the first range, a first shielding layer vertically extending along an outer periphery of hard mask layer so as to shield those of the source/drain layers to be in contact with the first electrically conductive channel;
with presence of the first shielding layer, selectively etching those of the source/drain layers to be in contact with the first electrically conductive channel to recess those source/drain layers inwards;
removing the first shielding layer, and filling an isolation material in a space formed by the recess of those source/drain layers to be in contact with the first electrically conductive channel below the hard mask layer;
forming, at least at the second range, a second shielding layer vertically extending along the outer periphery of hard mask layer so as to shield those of the source/drain layers to be in contact with the second electrically conductive channel;
with presence of the second shielding layer, selectively etching those of the source/drain layers to be in contact with the second electrically conductive channel to recess those source/drain layers inwards;
removing the second shielding layer, and filling an isolation material in a space formed by the recess of those source/drain layers to be in contact with the second electrically conductive channel below the hard mask layer;

wherein, forming gate stacks comprises:
removing the sacrificial gate by selective etching;
forming the gate stacks in a space formed by the removal of the sacrificial gate below the hard mask layer;
forming, at least at the third range, a third shielding layer vertically extending along the outer periphery of hard mask layer so as to shield the gate stacks;
with presence of the third shielding layer, selectively etching the gate stacks to recess the gate stacks inwards;
removing the third shielding layer, and filling an isolation material in a space formed by the recess of the gate stacks below the hard mask layer,

wherein the isolation materials filled below the hard mask layer constitute the isolation layer.