Patent ID: 11886874
Assignee: HITACHI ASTEMO, LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 2:
3. The arithmetic operation device according to claim 2, comprising
a storage unit that stores, for each of the convolution layers, a size of the filter, a bit number of the target data, and a bit number of a weight that is an element in the filter,
wherein the determiner acquires the size of the filter, the bit number of the target data, and the bit number of the weight that is an element in the filter in the convolution layer to be subjected to the convolution arithmetic operation from the storage unit, calculates a fourth bit number in which no overflow occurs in the convolution arithmetic unit, and determines whether an overflow occurs in the convolution arithmetic unit on the basis of the fourth bit number and a bit number of an adder in the convolution arithmetic unit.