Patent ID: 11862623
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 15:
16. A method, comprising:
arranging a first gate structure extending continuously above a first active region and a second active region of a substrate;
arranging a first separation spacer disposed on the first gate structure to isolate an electronic signal transmitted through a first gate via and a second gate via that are disposed on the first gate structure; and
arranging a first local interconnect between the first active region and the second active region, wherein the first local interconnect is electrically coupled to a first contact disposed above the first active region and a second contact disposed above the second active region,
wherein the first separation spacer overlaps the first local interconnect and has a width larger than a width of the first gate structure.