Patent ID: 11943919
Assignee: nan
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 17:
18. An electronic system, comprising:
an input device;
an output device;
a processor device operably coupled to the input device and the output device; and
a memory device operably coupled to the processor device and comprising:
a stack structure having tiers comprising conductive structures and insulating structures vertically neighboring the conductive structures, the stack structure comprising:
a staircase region comprising staircase structures having steps comprising horizontal ends of the tiers; and
a memory array region horizontally neighboring the staircase region;
contact structures on the steps of the staircase structures;
a microelectronic device electrically coupled to the contact structures and comprising transistors vertically overlying and within horizontal boundaries of the staircase region of the stack structure, each of the transistors comprising:
a channel region comprising a 2D material;
conductively doped regions neighboring opposing horizontal boundaries of the channel region and comprising the 2D material doped with at least one conductive dopant; and
a gate structure vertically overlying and at least partially horizontally aligned with the channel region; and
vertically extending strings of memory cells within the memory array region of the stack structure.