Patent ID: 11869590
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 15:
16. A memory device comprising:
a string of series-connected memory cells connected between a data line and a common source, the string of series-connected memory cells comprising a channel region;
a first select transistor connected between the data line and the string of series-connected memory cells;
a second select transistor connected between the common source and the string of series-connected memory cells;
a gate leakage transistor connected between the first select transistor and the second select transistor; and
control logic configured to, during an erase operation of the string of series-connected memory cells:
bias the data line and the common source to a first voltage level;
bias a control gate of the first select transistor to a second voltage level less than the first voltage level to turn off the first select transistor;
bias a control gate of the second select transistor to a third voltage level less than the first voltage level to turn off the second select transistor; and
bias a control gate of the gate leakage transistor to a fourth voltage level greater than the first voltage level to charge the channel region to a positive potential.