Patent ID: 11886733
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 3:
4. The circuit for testing a memory of claim 3, wherein the SWD further comprises:
a P-channel Metal Oxide Semiconductor (PMOS) transistor, a first end of the PMOS transistor being connected with a First WL Selection Signal (FTX) end, a second end of the PMOS transistor being connected with the drive signal output end, and a control end of the PMOS transistor being connected with a drive signal input end;
a first NMOS transistor, a first end of the first NMOS transistor being connected with the drive signal output end, a second end of the first NMOS transistor being connected with the discharge end, and a control end of the first NMOS transistor being connected with the drive signal input end; and
a second NMOS transistor, a first end of the second NMOS transistor being connected with the discharge end, a second end of the second NMOS transistor being connected with the WL signal end, and a control end of the second NMOS transistor being connected with a second WL selection signal end.