Patent ID: 11881256
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 17:
18. A method of controlling load of global input-output lines of a semiconductor memory device, comprising:
cutting a plurality of global input-output lines to transfer data between a plurality of data pads and a plurality of memory cells into a plurality of line segment groups;
connecting two line segment groups through a plurality of intra-bank switches, the two line segment groups included in one memory bank; and
controlling switching operations of the plurality of intra-bank switches based on a row address,
wherein the controlling the switching operations of the plurality of intra-bank switches includes turning on or turning off intra-bank switches that are included in the one memory bank based on the row address, and turning on the intra-bank switches that are not included in the one memory bank corresponding to the bank regardless of the row address.