Patent ID: 11910609
Assignee: KIOXIA CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 1:
2. The semiconductor memory device according to claim 1, comprising:
a plurality of first insulating layers arranged in the second direction alternately with the plurality of first conductive layers;
a plurality of second insulating layers arranged in the second direction alternately with the plurality of second conductive layers;
a plurality of third insulating layers arranged in the second direction alternately with the plurality of third conductive layers; and
a plurality of fourth insulating layers arranged in the second direction alternately with the plurality of fourth conductive layers, wherein
in a first cross-sectional surface extending in the first direction and the second direction and including at least one of the plurality of first contacts;
a fifth contact as one of the plurality of first contacts penetrates the plurality of third insulating layers, extends in the second direction, and is connected to the first conductive layer farthest from the plurality of third conductive layers among the plurality of first conductive layers; and
a first conductive layer of the plurality of first conductive layers disposed at a position closer to the plurality of third conductive layers than other ones of the first conductive, layers and has a larger distance to the fifth contact in the first direction than the other ones of the first conductive layers.