Patent ID: 11901018
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 10:
11. A method, comprising:
pre-charging a first sense node of a sense amplifier circuit;
discharging the first sense node through a first bit line at a rate dependent upon a conduction state of a first selected memory cell along the first bit line;
after discharging the first sense node through the first selected memory cell for a sensing interval, capacitively storing, on a first local data bus of the sense amplifier circuit, a sensed value based on a resultant charge level on the first sense node, the sense amplifier including a first plurality of data latches connected to the first local data bus;
subsequent to setting the sensed value on the first local data bus, performing, on a second local data bus of the sense amplifier circuit, a first plurality of logical operations between the sensed value and values latched in the first plurality of data latches, the sense amplifier circuit including a second plurality of data latches connected to the second local data bus and a second sense node, the second sense node connectable to a second bit line and connectable to the second local data bus and configured to capacitively store a sensed value on the second local data bus based on discharging the second sense node through the second bit line, performing the first plurality of logical operations including:
transferring one or more of the values latched in the first plurality of data latches between the first local data bus and the second local data bus;
performing one or more of the plurality of logical operation using the second plurality of data latches; and
transferring a result of the one or more of the plurality of logical operation using the second plurality of data latches to the first local data bus; and

concurrently with performing the first plurality of logical operations, pre-charging the first sense node for a second sensing operation,
subsequent to capacitively storing the first sensed value on the first local data bus, perform a plurality of logical operations between the first sensed value and values latched in the first plurality of data latches, where to perform the plurality of logical operations the control circuit is configured to:
transfer one or more of the values latched in the first plurality of data latches to the second local data bus over the connection circuit;
perform one or more of the plurality of logical operation using the second plurality of data latches; and
transfer a result of the one or more of the plurality of logical operation using the second plurality of data latches over the connection circuit to the first local data bus; and

concurrently with performing the plurality of logical operations, pre-charge the first sense node for a second sensing operation.