Patent ID: 11929118
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 11:
12. A non-volatile memory device comprising:
a plurality of word lines including a first word line relatively close to a substrate and a second word line relatively far from the substrate;
a memory cell array including a plurality of cell strings, each cell string extending in a vertical direction above the substrate and each cell string including a plurality of memory cells respectively connected to the word lines;
a page buffer circuit including a plurality of page buffers connected to the memory cell array, each page buffer being connected to a selected cell string through a bit line and including a bit line shut-off transistor configured to be driven in response to a bit line shut-off signal and a forcing latch configured to store forcing information; and
a control logic circuit configured to, during a program operation on a selected word line, control a delay interval in which a bit line shut-off voltage corresponding to the bit line shut-off signal maintains a voltage level corresponding to a ground voltage before a bit line forcing operation of transferring the forcing information to the selected cell string through the bit line is performed,
a length of the delay interval based on the selected word line corresponding to the first word line being longer than a length of the delay interval based on the selected word line corresponding to the second word line.