Patent ID: 11860714
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 22:
23. A method, comprising: receiving, at an interface controller of a memory system, a write command comprising first data and first parity information associated with the first data, wherein the interface controller comprises a host-driven logical block interface; acknowledging, via the host-driven logical block interface in response to receiving the write command, that the first data has been received based on determining that the first parity information matches second parity information generated from the first data; performing one or more operations on second data and third parity information associated with the second data, wherein the second data comprises the first data; identifying an error associated with performing the one or more operations on the second data after acknowledging that the first data has been received; and transmitting an indication of the error over a channel that is external to the host-driven logical block interface.