Patent ID: 11930628
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A device, comprising:
a substrate having a first semiconductor fin and a second semiconductor fin;
a pull-down transistor over the substrate, comprising:
a first gate structure crossing the first semiconductor fin; and
first source/drain regions in the first semiconductor fin and on opposite sides of the first gate structure;

a pass-gate transistor over the substrate;
a pull-up transistor over the substrate, comprising:
a second gate structure crossing the second semiconductor fin, wherein in a top view, the first gate structure is connected to the second gate structure; and
second source/drain epitaxy structures over the second semiconductor fin and on opposite sides of the second gate structure, wherein each of the second source/drain epitaxy structures comprises a rounded surface; and

a dielectric layer over the substrate, wherein in a cross-sectional view, the dielectric layer is in contact with a top surface of the first semiconductor fin and a top surface of one of the second source/drain epitaxy structures.