Patent ID: 11955557
Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor device comprising:
a first insulating layer;
an oxide semiconductor layer over the first insulating layer;
a gate electrode over the oxide semiconductor layer;
a first electrode in contact with an upper surface of the oxide semiconductor layer;
a second insulating layer in contact with the first electrode; and
a third insulating layer over the first electrode,
wherein the oxide semiconductor layer comprises indium, gallium, and zinc,
wherein the second insulating layer, the first electrode, and the oxide semiconductor layer overlap with one another in a direction perpendicular to the upper surface of the oxide semiconductor layer,
wherein the third insulating layer is in contact with the gate electrode, an upper surface and a side surface of the second insulating layer, a side surface of the first electrode, an upper surface of the first insulating layer, and the upper surface of the oxide semiconductor layer, and
wherein each of an end portion of the second insulating layer and an end portion of the first electrode has a tapered shape.