Patent ID: 11967383
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 3:
4. The non-volatile storage apparatus of claim 2, wherein:
the control circuit is configured to perform the programming process by performing multiple program loops, each program loop comprises the control circuit applying a program voltage pulse to the plurality of non-volatile memory cells and performing program verification for at least a subset of the plurality of non-volatile memory cells; and
the control circuit is configured to identify a slow plane of the multiple planes based on the first portion of the programming process by:
counting a number of program loops performed for each plane after all memory cells of the respective plane that are targeted to the first set of data states have completed the programming process and before all planes have completed the first portion of the programming process, and
identifying the slow plane as a plane with a smallest number of program loops performed after all memory cells of the respective plane that are targeted to the first set of data states have completed the programming process and before all planes have completed the first portion of the programming process.