Patent ID: 11869116
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 12:
13. A line interleaving controller comprising:
a buffer circuit configured to receive a first control signal and buffer a plurality of first image data lines included in a first image frame received through a first channel and a plurality of second image data lines included in a second image frame received through a second channel to selectively output each first image data line or each second image data line based on the first control signal;
a virtual line generator configured to
receive a second control signal, and
generate first virtual data lines corresponding the first image frame and second virtual data lines corresponding to the second image frame based on a determined number and the second control signal;

a multiplexer configured to receive a selection signal and output a stream signal by selecting an output of the buffer circuit and an output of the virtual line generator based on the selection signal; and
a control logic circuit configured to receive a first synchronization signal received through the first channel and a second synchronization signal received through the second channel and generate the first control signal, the second control signal and the selection signal to control the buffer circuit, the virtual line generator and the multiplexer based on the first synchronization signal and the second synchronization signal,
wherein the first virtual data lines are used to process one or more end image data lines included in an end portion of the first image frame, and the second virtual data lines are used to process one or more end image data lines included in an end portion of the second image frame.