Patent ID: 11972123
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. An apparatus, comprising:
a memory device; and
a circuit coupled with the memory device and configured to cause the apparatus to:
receive a first activate command that indicates a first set of bits of a row address;
store the first set of bits based at least in part on receiving the first activate command to obtain a first delayed signal of the first set of bits;
receive a second activate command that indicates a second set of bits of the row address;
store the second set of bits based at least in part on receiving the second activate command to obtain a first delayed signal of the second set of bits;
store the first delayed signal of the first set of bits based at least in part on receiving the second activate command to obtain a second delayed signal of the first set of bits; and
activate a page of memory based at least in part on receiving the second activate command, wherein the page of memory is addressed according to the second delayed signal of the first set of bits and the first delayed signal of the second set of bits.