Patent ID: 11862222
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 3:
4. The refresh circuit according to claim 3, wherein the asynchronous binary addition counter comprises a first counting terminal as a low order, a second counting terminal as a next high order, and a third counting terminal as a high order; and the regulating subunit comprises a first AND gate, a second AND gate, a third AND gate and a fourth AND gate;
the first AND gate has a first input terminal connected to the first counting terminal, a second input terminal connected to the second counting terminal, and a third input terminal connected to the third counting terminal;
the second AND gate has a first input terminal configured to receive a first temperature signal, a second input terminal connected to the second counting terminal, and a third input terminal connected to the third counting terminal;
the third AND gate has a first input terminal connected to the first counting terminal, a second input terminal configured to receive a second temperature signal, and a third input terminal connected to the third counting terminal; and
the fourth AND gate has a first input terminal connected to the first counting terminal, a second input terminal connected to the second counting terminal, and a third input terminal configured to receive a third temperature signal,
wherein the third temperature signal represents that a current temperature is less than or equal to a third temperature, the second temperature signal represents that the current temperature is less than or equal to a second temperature and greater than the third temperature, and the first temperature signal represents that the current temperature is less than or equal to a first temperature and greater than the second temperature.