Patent ID: 11867745
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 6:
7. The method for detecting the parasitic capacitance in the semiconductor device according to claim 1, wherein the determining the capacitance between the wire per unit length and the gate in the semiconductor device according to the plurality of total capacitance values and the lengths of the plurality of the wire of the plurality of semiconductor devices comprises:
the plurality of total capacitance values comprising a first total capacitance value of a first semiconductor device and a second total capacitance value of a second semiconductor device, the plurality of lengths of the wire comprising a first length of the wire in the first semiconductor device and a second length of the wire in the second semiconductor device;
determining a first difference between the first total capacitance value and the second total capacitance value;
determining a second difference between the first length and the second length;
obtaining the number of wires in each semiconductor device, the number of wires being used to represent the number of parasitic capacitances; and
determining the parasitic capacitance per unit length according to the first difference value, the second difference value and the number of wires.