Patent ID: 11929316
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 18:
19. A method of fabricating a semiconductor package, the method comprising:
forming a redistribution substrate that includes a dielectric pattern and a redistribution pattern buried in the dielectric pattern;
forming a mask pattern on the redistribution substrate, the mask pattern having a first opening with a first width and a second opening with a second width less than the first width;
forming a first substrate pad that fills the first opening and a second substrate pad that fills the second opening;
removing the mask pattern;
providing first and second connection members on first and second chip pads, respectively, of a semiconductor chip;
placing the semiconductor chip on the redistribution substrate to allow the first and second connection members to rest on the first and second substrate pads, respectively; and
performing a reflow process on the connection members to form a first connection terminal that connects the first substrate pad to the first chip pad and a second connection terminal that connects the second substrate pad to the second chip pad,
wherein each of the first chip pad and the second chip pad has a quadrilateral shape when viewed in cross-section,
wherein a maximum width of the first substrate pad is substantially the same as widths of the first and second chip pads,
wherein a maximum width of the second substrate pad is less than the widths of the first and second chip pads, and
wherein a volume of the first substrate pad is substantially the same as a volume of the second substrate pad.