Patent ID: 11936375
Assignee: CHIPONE TECHNOLOGY (BEIJING) CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 3:
4. A chip, comprising a buffer apparatus, the buffer apparatus comprising:
a voltage adjustment module comprising:
a first P-type metal-oxide-semiconductor field effect transistor (PMOS),
a first current source,
a first N-type metal-oxide-semiconductor field-effect transistor (NMOS),
a first resistor,
a second resistor,
a third resistor,
a fourth resistor, and
a first capacitor; and

a buffer module electrically connected to the voltage adjustment module and configured to receive an input signal, and buffer the input signal under the drive voltage to output the buffered signal;
wherein the voltage adjustment module is configured to receive an input voltage and adjust the input voltage with a threshold voltage for the first PMOS to output a drive voltage;
wherein a positive electrode of the first current source is electrically connected to a first terminal of the third resistor to receive the input voltage, and a negative electrode of the first current source is electrically connected to a source of the first PMOS, a gate of the first NMOS, and a first terminal of the first capacitor, wherein the input voltage is a supply voltage;
wherein a gate of the first PMOS is electrically connected to a drain of the first PMOS and a first terminal of the first resistor, and a second terminal of the first resistor is electrically connected to a first terminal of the second resistor;
wherein a second terminal of the third resistor is electrically connected to a drain of the first NMOS;
wherein a source of the first NMOS is electrically connected to a first terminal of the fourth resistor and the buffer module, to output the drive voltage; and
wherein a second terminal of the second resistor, a second terminal of the first capacitor, and a second terminal of the fourth resistor are grounded.