Patent ID: 11914416
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 5:
6. The transmitter circuit of claim 1, wherein each selection circuit of the plurality of selection circuits comprises:
an AND-OR-inverter circuit configured to receive the first parallel signal, a first target clock signal corresponding to the first parallel signal among the first clock signals, the second parallel signal, and a second target clock signal corresponding to the second parallel signal among the first clock signals and drive the first P-type transistor; and
an OR-AND-inverter circuit configured to receive the first parallel signal, a first inverted target clock signal obtained by inverting the first target clock signal, the second parallel signal, and a second inverted target clock signal obtained by inverting the second target clock signal and drive the first N-type transistor.