Patent ID: 11935925
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 5:
6. The method for manufacturing the semiconductor structure of claim 5, wherein said removing the exposed portion of the first conductive layer to retain the portion of the first conductive layer located below the primary gate pattern further comprises:
removing the exposed portion of the first conductive layer to expose the semiconductor substrate, wherein a side wall of the first conductive layer is exposed, and a portion of the first conductive layer covered by the primary gate pattern and the first conductive layer below the dielectric layer on the side wall of the primary gate pattern are retained; and
removing the first conductive layer below the dielectric layer on the side wall of the primary gate pattern from the side wall of the first conductive layer, wherein the first conductive layer covered by the primary gate pattern is retained.