Patent ID: 11961567
Assignee: PUFSECURITY CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. A key generation method, comprising:
generating a first setting voltage by a first setting circuit;
transmitting the first setting voltage to a first output transistor in a first inverter to generate a first logic value, wherein the first output transistor has a first threshold voltage;
generating a second setting voltage by a second setting circuit; and
transmitting the second setting voltage to a second output transistor in a second inverter to generate a second logic value, wherein the second output transistor has a second threshold voltage,
wherein an absolute value of the first threshold voltage is lower than an absolute value of the second threshold voltage,
wherein the first setting voltage is higher than the second setting voltage, and
wherein the first setting circuit and the second setting circuit comprises a first setting transistor and a second setting transistor, respectively, receiving a constant voltage at a control terminal.