Patent ID: 11909408
Assignee: SHENZHEN PANGO MICROSYSTEMS CO., LTD
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A SerDes module clock network architecture, comprising a reference clock input port, a plurality of data transmission channels, several user logic interfaces, several frequency division branches and a phase locked loop; wherein
the reference clock input port receives an input clock and conveys the input clock to the phase locked loop;
the phase locked loop receives the input clock and outputs a PLL output clock signal;
the PLL output clock signal is conveyed to the plurality of data transmission channels;
the PLL output clock signal is conveyed to the frequency division branches, and after frequency division, user interface clocks are output and conveyed to the user logic interfaces, wherein each of the frequency division branches is associated with a frequency division coefficient, and the frequency division coefficient of each of the frequency division branches is independent; and
the frequency division branches are in one-to-one correspondence with the user logic interfaces.