Patent ID: 11860782
Assignee: NEUROBLADE LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory unit comprising:
one or more memory banks;
a bank controller;
a plurality of address generators, the plurality of address generators including at least a first address generator and a second address generator;
wherein at least one of the plurality of address generators is configured to:
provide to the bank controller a current address of a current row to be accessed in an associated memory bank of the one or more memory banks, the current address being generated by the first address generator;
determine a predicted address of a next row to be accessed in the associated memory bank, the predicted address being generated by the second address generator within a predetermined time period after the first address generator has generated the current address; and
provide the predicted address to the bank controller before completion of an operation relative to the current row associated with the current address.