Patent ID: 11900988
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. The electronic device of claim 5, wherein the precharge decoder comprises:
a pre-decoder configured to:
generate a first decoding signal when the odd command/address signal has a logic level combination for performing the precharge operation in synchronization with the first internal clock, and
generate a second decoding signal when the even command/address signal has a logic level combination for performing the precharge operation in synchronization with the second internal clock;

a counting circuit configured to generate the counting signal which is toggled in synchronization with a rising edge of the first internal clock during a period in which the odd chip selection signal and the first decoding signal are input, and toggled in synchronization with a rising edge of the second internal clock during a period in which the even chip selection signal and the second decoding signal are input;
an alignment circuit configured to:
generate a first precharge alignment signal and a second precharge alignment signal by latching the counting signal in synchronization with a falling edge of the first internal clock, and
generate a third precharge alignment signal and a fourth precharge alignment signal by latching the counting signal in synchronization with a falling edge of the second internal clock; and

a precharge command generation circuit configured to:
generate the odd precharge command based on the first decoding signal and the first and third precharge alignment signals in synchronization with a rising edge of the first internal clock, and
generate the even precharge command based on the second decoding signal and the second and fourth precharge alignment signals in synchronization with a rising edge of the second internal clock.