Patent ID: 11903194
Assignee: MACRONIX INTERNATIONAL CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. An integrated circuit, comprising:
at least one first memory block and at least one second memory block respectively disposed on two sides of the integrated circuit, wherein each of the at least one first memory block and the at least one second memory block includes a memory cell array having a three-dimensional architecture; and
a pad disposing area, wherein the at least one first memory block and the at least one second memory block are symmetrically disposed about the pad disposing area, a plurality of pads are disposed in the pad disposing area, and the pads are respectively electrically coupled to the at least one first memory block and the at least one second memory blocks,
wherein each of the at least one first memory block and the at least one second memory block comprises a control circuit generating a control signal to control an access operation of the corresponding memory cell array,
wherein the control circuit of the at least one first memory block and the control circuit of the at least one second memory block are symmetrically disposed about the pad disposing area.