Patent ID: 11908507
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 16:
17. The memory system according to claim 16, wherein the command and address generator decodes the command and further generates a refresh command, and
wherein the memory further comprises:
a hammer refresh address generator configured to receive the row address in response to the active command, to detect a corresponding row address as an aggressor row address based on the same row address being applied a specific number of times or more, and to generate at least one victim row address adjacent to the aggressor row address as a hammer refresh row address together with a hammer refresh command;
a normal refresh address generator configured to a normal refresh row address in response to the refresh command;
a selection unit configured to select the hammer refresh row address in response to the hammer refresh command or to select the normal refresh row address in response to the refresh command, so as to generate a refresh row address; and
a row decoder configured to decode the row address in response to the active command and to decode the refresh row address in response to the refresh command or the hammer refresh command, so as to generate a plurality of main word line selection signals and a plurality of selection signals.