Patent ID: 11949419
Assignee: MICRON TECHNOLOGY, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 16:
17. A memory system, comprising:
one or more memory devices; and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
couple a set of signal lines associated with a set of signals to an input side of a set of buffers;
obtain a set of delayed signals on the set of signal lines based at least in part on coupling the set of signal lines to the set of buffers;
derive a set of clock signals from the set of delayed signals;
obtain a first integration signal for a first clock signal of the set of clock signals based at least in part on a first capacitance and a first resistance;
obtain a second integration signal for a second clock signal of the set of clock signals based at least in part on a second capacitance and a second resistance;
input the first integration signal to a first input of an amplifier and the second integration signal to a second input of the amplifier; and
bias, by an output of the amplifier, a control line of a transistor.