Patent ID: 11972808
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A memory apparatus, comprising:
a drain-side select gate transistor, which has a semi-circular shape, for coupling to a drain-side of each of a plurality of memory holes; and
a control means coupled to the drain-side select gate transistor of each of the plurality of memory holes and configured to:
determine whether a downshift recovery trigger event has occurred in a plurality of memory operations, and
in response to determining the downshift recovery trigger event has occurred, insert at least one of a predetermined idle time in one of the plurality of memory operations and a recovery pulse of a negative voltage to the drain-side select gate transistor of the plurality of memory holes of each of a plurality of strings of rows of the plurality of memory holes for a predetermined pulse period of time during the one of the plurality of memory operations.