Patent ID: 11972832
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 10:
11. The command decoder circuit of claim 10, wherein the enable signal generation unit comprises:
an OR gate, configured to determine an OR signal of the second command signal and the timing signal;
a first AND gate, configured to determine an AND signal of the first command signal and an AND signal output by a second AND gate, wherein the AND signal output by the first AND gate is the enable signal; and
the second AND gate, configured to determine an AND signal of the OR signal and the AND signal output by the first AND gate, and wherein
the clock gate comprises:
a NOT gate, configured to obtain a NOT signal of the chip select signal; and
an OR gate, configured to determine an OR signal of the NOT signal, the enable signal, and the system clock signal as the dynamic clock signal.