Patent ID: 11935784
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A memory device, comprising:
an alternating stack of insulating layers and word lines;
memory opening fill structures extending through the alternating stack, wherein each of the memory opening fill structures comprises a memory element, a vertical semiconductor channel and a drain region connected to an upper end of the semiconductor channel;
bit lines electrically connected to a respective subset of the drain regions, wherein the bit lines are embedded within a vertical layer stack including a bit-line-level dielectric layer and an etch stop dielectric layer, wherein each of the bit lines is contacted by a bottom surfaces of a respective capping dielectric strip;
at least one via-level dielectric layer overlying the vertical layer stack; and
a bit-line-contact via structure vertically extending through the at least one via-level dielectric layer and through one of the capping dielectric strips and contacting a top surface of a respective one of the bit lines, contacting a sidewall segment of the etch stop dielectric layer, and contacting a segment of a top surface of the etch stop dielectric layer.