Patent ID: 11880686
Assignee: AMPERE COMPUTING LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 20:
21. A method, in a device, of a conversion circuit providing a flow control unit (FLIT) to a link interface circuit of the device, the method comprising:
receiving, in a conversion circuit, a write instruction, at least a first cache line, and metadata associated with the at least a first cache line on a system bus;
generating a FLIT comprising:
a first header slot comprising write information based on the write instruction for transmitting the at least one first cache line on an external link coupled to the link interface circuit;
a first metadata slot comprising the metadata; and
at least two generic slots comprising cache line chunks, each cache line chunk comprising bytes of a cache line; and

providing the FLIT to the link interface circuit for transmission on the external link.