Patent ID: 11934564
Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 3:
4. The secure computation device according to claim 3,
wherein σ0 is positive integer that is the number of bits indicating a right shift amount and σ1 is positive integer that is the number of bits indicating a right shift amount, and
the fourth secure computation circuitry includes
public value calculation circuitry configured to obtain public values 2σ0/m0 and 2σ1/m1 using the multipliers m0 and m1 and the positive integer σ0 and the positive integer σ1;
fifth secure computation circuitry configured to perform, using the secret share value [a], the secret share value [q], the modulus p, and the public values 2σ0/m0 and 2σ1/m1 obtained by the public value calculation circuitry, secure computation of public value division [a+qp]/(2σ0/m0) and secure computation of public value division [a+qp]/(2σ1/m1) to obtain a secret share value [(a+qp)m0] of a value obtained by right-shifting (a+qp)m0 by σ0 bits and a secret share value [(a+qp)m1] of a value obtained by right-shifting (a+qp)m1 by σ1 bits; and
sixth secure computation circuitry configured to obtain and output [m0a]=[(a+qp)m0]−[q]pm0 and [m1a]=[(a+qp)m1]−[q]pm1 through secure computation using the secret share value [(a+qp)m0], the secret share value [(a+qp)m1], the secret share value [q], the modulus p, and the multipliers m0 and m1.