Patent ID: 11910596
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 20:
21. An integrated assembly, comprising:
a first memory region, a second memory region offset from the first memory region, and an intermediate region between the first and second memory regions;
first channel-material-pillars arranged within the first memory region;
second channel-material-pillars arranged within the second memory region;
conductive posts arranged within the intermediate region;
a panel extending across the first memory region, the intermediate region and the second memory region; the panel being laterally between a first memory-block-region and a second memory-block-region;
doped first semiconductor material within the first memory region, the second memory region and the intermediate region, and being directly adjacent the panel;
the doped first semiconductor material being at least part of conductive source structures within the first and second memory regions; and
rings laterally surrounding lower regions of the conductive posts and being between the conductive posts and the doped first semiconductor material; the rings comprising laminates of two or more materials; inner regions of the rings being spaced from the conductive posts by intervening regions which include second semiconductor material;
the doped first semiconductor material directly contacting outer lateral edges of the rings.