Patent ID: 11962309
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G  Y | IPC H

Claim 10:
11. The phase adjusting circuit of claim 10, wherein each of the first adjustment circuit, the second adjustment circuit, the third adjustment circuit, and the fourth adjustment circuit comprises a preset number of adjustment sub-circuits, the preset number being an even number;
each of the adjustment sub-circuits comprises a plurality of inverting sub-circuits, and is configured to: determine whether each of the plurality of inverting sub-circuits is turned on based on the preset fixed value or the count value; and perform inverting transmission processing for a corresponding one of the first clock signal, the second clock signal, the third clock signal and the fourth clock signal using the turned-on inverting sub-circuit;
wherein, at least one of the plurality of inverting sub-circuits in each adjustment sub-circuit is turned on; control terminals of the plurality of the inverting sub-circuits together form a control terminal of the adjustment sub-circuit, and a control terminal of one of the plurality of inverting sub-circuits is configured to receive one of bits of the count value or one of bits of the preset fixed value; and input terminals of the plurality of inverting sub-circuits together form an input terminal of the adjusting sub-circuit, and output terminals of the plurality of the inverting sub-circuits together form an output terminal of the adjustment sub-circuit.