Patent ID: 11966835
Assignee: NVIDIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A deep learning network acceleration method comprising:
receiving an input activation vector and a weight vector;
compressing the input activation vector and the weight vector to omit one or more missing or null values, thus generating a compressed input activation vector and a compressed weight vector;
providing the compressed input activation vector and the compressed weight vector to an array of computing elements configured spatially based on a particular coordinate dimension of the compressed input activation vector and the compressed weight vector;
providing channel indices for the compressed input activation vector and the compressed weight vector to a parallelism discovery unit, the channel indices oriented in an input channel direction;
operating the parallelism discovery unit on the channel indices to determine, via a comparison of the channel indices, matching pairs of channel inputs utilizing an array of comparators, each matching pair comprising a coordinate index for the compressed weight vector and a coordinate index for the compressed input activation vector; and
generating column selects and row selects from the matching pairs of channel inputs and providing the column selects and the row selects and a vector of validity bits along with the compressed input activation vector and the compressed weight vector to the array of computing elements to generate output activations for the deep learning network.