Patent ID: 11899959
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. A memory built-in self-test (MBIST) circuit for testing a memory device comprising a plurality of memory banks, the MBIST circuit comprising:
a test pattern generating (TPG) circuit configured to generate a plurality of test patterns, the plurality of test patterns including a double data rate (DDR) test pattern and a parallel bit test (PBT) test pattern;
a built-in redundancy analysis (BIRA) circuit configured to perform a repair operation for replacing a defective cell detected in a PBT test or a DDR test on the memory device with a redundancy cell, and store information regarding a fail cell address and a redundancy cell address in an address storage table (AST); and
a built-in self-repair (BISR) control circuit configured to output BISR signals to perform the repair operation in response to a fail flag signal indicating that the defective cell has been detected,
wherein the TPG circuit is further configured to perform a re-test on one or more memory cells including the defective cell among a plurality of memory cells to verify the repair operation through the BIRA circuit.