Patent ID: 11862247
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A semiconductor memory device comprising:
a first memory string including a first select transistor, a first memory cell, a first select element, a second memory cell, and a second select element in series, the first memory cell being provided between the first select transistor and the first select element, and the second memory cell being provided between the first select element and the second select element;
a second memory string including a second select transistor, a third memory cell, a third select element, a fourth memory cell, and a fourth select element in series, the third memory cell being provided between the second select transistor and the third select element, and the fourth memory cell being provided between the third select element and the fourth select element;
a first wiring connecting a gate of the first memory cell and a gate of the third memory cell;
a second wiring connecting a gate of the second memory cell and a gate of the fourth memory cell; and
a control circuit configured to set the second select transistor to an on state, and to set the third select element and the fourth select element to an off state, when reading data of the first memory cell.