Patent ID: 11954059
Assignee: SONY INTERACTIVE ENTERTAINMENT LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A signal processing system including a plurality of signal processing chips each including a plurality of signal processing blocks connected to each other by a signal line,
a first signal processing chip corresponding to at least one of the signal processing chips including at least
sampling means for sampling a signal on a first signal line between the signal processing blocks in the first signal processing chip, and
transmission means for transmitting, to another signal processing chip, a data frame including information indicating the signal sampled at a timing of satisfying a predetermined condition,
a second signal processing chip different from the first signal processing chip including at least
reception means for receiving, from the first signal processing chip, the data frame including the information regarding the signal on the first signal line between the signal processing blocks in the first signal processing chip, the signal having been sampled in the first signal processing chip, and
inverse sampling means for outputting a signal to a second signal line in the second signal processing chip on a basis of the data frame received; wherein
the sampling means samples the signal on the first signal line with a predetermined scheme irrespective of a protocol that is used by one of the signal processing blocks in the first signal processing chip when transmitting and receiving the signal to and from another of the signal processing blocks in the first signal processing chip via the first signal line;
the transmission means transmits the data frame with the predetermined scheme irrespective of the protocol; and
the predetermined scheme optimizes voltage amplitude.