Patent ID: 11966480
Assignee: NVIDIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 1:
2. The accelerator circuit of claim 1, wherein:
the scheduler circuit is further to:
receive, from a second application, a second descriptor of a second data transfer of a second size, the second descriptor specifying a second index in the secure memory corresponding to the second application; and
split the second data transfer into a second set of portions, each portion being less than or equal to the second size and required to complete execution before a context switch to another application;

the DMA circuit is further to:
during a third period, execute a first subset of the second set of portions sequentially using a second IV and a second encryption key associated with the second application;
at an end of the third period, store a second computed hash key and a second block counter in the secure memory at the specified second index;
during a fourth period subsequent to the third period, execute a second subset of the second set of portions sequentially using the second computed hash key and the second block counter stored in the secure memory at the specified second index; and
at an end of the fourth period, store a second authentication tag associated with the second data transfer.