Patent ID: 11901004
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A memory structure, comprising:
memory cells, formed on a substrate, and respectively comprising:
a write transistor, disposed on a surface of the substrate;
an electrically programmable non-volatile memory (NVM), disposed over the write transistor, wherein a first terminal of the electrically programmable NVM is electrically connected to a first source/drain structure of the write transistor, and a second terminal of the electrically programmable NVM is electrically connected to a bit line lying over the electrically programmable NVM; and
a capacitor, disposed over the write transistor, with a bottom electrode electrically connected to the first terminal of the electrically programmable NVM and the first source/drain structure of the write transistor.