Patent ID: 11864466
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Electrical machinery, apparatus, energy (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A semiconductor device including a magnetic random access memory (MRAM) cell, comprising:
a first interlayer dielectric (ILD) layer disposed over a substrate;
a lower contact embedded in the first ILD layer;
a magnetic random access memory (MRAM) cell structure disposed over the lower contact, and including a bottom electrode, a magnetic tunnel junction (MTJ) stack and a top electrode;
one or more sidewall insulating layers disposed over sidewalls of the MRAM cell structure;
a second ILD layer disposed over the one or more sidewall insulating layers; and
an upper contact passing through the second ILD layer and contacting the top electrode, wherein:
the lower contact includes a liner layer and a body layer disposed over the liner layer,
an upper surface of the first ILD layer comprises a recess having a lower level than an uppermost level of the first ILD layer,
a bottom of the upper contact is in contact with the top electrode and the one or more sidewall insulating layers, and
the first ILD layer includes a bottom layer and an upper layer having a greater thickness at the recess than the bottom layer.