Patent ID: 11971826
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 9:
10. The non-volatile memory device of claim 9, wherein:
the internal data bus further includes:
a third segment configured to transfer data between a third cache buffer corresponding to a third of the planes and the input-output interface and a fourth segment configured to transfer data between a fourth cache buffer corresponding to a fourth of the planes and the input-output interface;
a second tri-state buffer connecting the first segment and the third segment and configured to cut-off the first segment and the third segment from one another; and
a third tri-state buffer connecting the second segment and the fourth segment and configured to cut-off the second segment and the fourth segment from one another,

wherein the control circuit further comprises:
a third compression circuit configured to compress data received from the third segment; and
a fourth compression circuit configured to compress data received from the fourth segment; and

wherein the control circuit is further configured to:
concurrently transfer data between any of the first, second, third, and fourth cache buffer and the respective first, second, third, and fourth of the compression circuits over the respective first, second, third, and fourth segment.