Patent ID: 11972973
Assignee: nan
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 22:
23. The method of claim 15, wherein the conductive lines comprise input/output electrodes of transistors formed in the wafer, and the method further comprises forming the input/output electrodes, comprising:
forming an inter-layer dielectric layer over transistors that are formed in a substrate of the wafer;
forming a first silicate glass layer on the inter-layer dielectric layer;
forming a first silicon nitride (SiN) layer on parts of the first silicate glass layer that are disposed on first terminals of the transistors at a first depth;
forming a second silicate glass layer on the first silicate glass layer and the first SiN layer;
forming a second SiN layer on the second silicate glass layer;
forming first openings on second terminals of the transistors at a second depth that is deeper than the first depth;
depositing a first layer of electrode metal to fill the first openings;
removing exposed portions of the second silicate glass layer;
forming second openings on the first terminals of the transistors;
depositing a second layer of electrode metal to fill the second openings; and
removing the first SiN layer and the second SiN layer;
wherein the electrode metal comprises tungsten, cobalt or ruthenium.