Patent ID: 11882682
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for manufacturing a semiconductor structure, comprising the following steps:
providing a substrate, wherein a plurality of contact pads arranged in an array are provided in the substrate, and the plurality of contact pads protrude from an upper surface of the substrate;
forming a first barrier layer on the substrate and surfaces of the plurality of contact pads, wherein the first barrier layer is in direct contact with the substrate and surfaces of the plurality of contact pads;
forming a first conductive layer on a surface of the first barrier layer;
etching an upper surface of the first conductive layer to form a first recessed structure and a second recessed structure, wherein the first recessed structure extends downwards to the substrate, a projection of the first recessed structure on the substrate surrounds a given one of the plurality of contact pads, and the second recessed structure is formed in the first conductive layer and arranged above the corresponding contact pad; and
forming a first dielectric layer, a second barrier layer, and a second conductive layer sequentially on surfaces of the first conductive layer;
wherein the first conductive layer comprises a plurality of hollow cylindrical conductive columns surrounded by the first recessed structure and the second recessed structure, and the plurality of hollow cylindrical conductive columns correspond to the plurality of contact pads in terms of positions and numbers one by one, and an opening is provided above each of the plurality of hollow cylindrical conductive columns.