Patent ID: 11937420
Assignee: NANYA TECHNOLOGY CORPORATION
Field: nan (nan)
Classification: CPC H | IPC H

Claim 0:
1. A memory device, comprising:
a semiconductor substrate defined with an active area and including a recess extending into the semiconductor substrate; and
a word line disposed within the recess,
wherein the word line comprises a first insulating layer disposed within and conformal to the recess, a conductive layer surrounded by the first insulating layer, a conductive member enclosed by the conductive layer, a second insulating layer disposed over the conductive layer and conformal to the first insulating layer, a work function member surrounded by the second insulating layer, and a third insulating layer surrounded by the second insulating layer and disposed over the work function member;
wherein the conductive layer, having a hollow cross section, is constructed to have a top wall, a bottom wall, and two enclosing walls integrally extended between the top and bottom walls to form an enclosing cavity to enclose the conductive member therein, wherein a width of the top wall of the conductive layer is equal to a width of the bottom wall thereof, such that the conductive layer has a uniform width from top to bottom;
wherein the second insulating layer, having a U-shaped cross section, is constructed to have a second insulating layer wall disposed on the top wall of the conductive layer and two sidewalls integrally and upwardly extended from the second insulating layer wall to form the second insulating layer in one single integrated structure in order to receive the work function member between the sidewalls;
wherein the third insulating layer is integrally extended between the sidewalls of the second insulating layer to enclose the work function member within the second insulating layer wall, the sidewalls, and the third insulating layer.