Patent ID: 11950427
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 6:
7. A device comprising:
a semiconductor substrate;
a first memory cell over the semiconductor substrate, the first memory cell comprising a first transistor, wherein the first transistor comprises:
a first portion of a ferroelectric layer, the first portion of the ferroelectric layer being on a sidewall of a first word line, and the ferroelectric layer comprising a species with valence of 5, valence of 7, or a combination thereof; and
a first channel region on a sidewall of the ferroelectric layer, the first channel region comprising an oxide semiconductor layer, wherein a first interface between the first channel region and the first portion of the ferroelectric layer has a species having valence of 5, valence of 7, or a combination thereof, and;

a second memory cell over the first memory cell.