Patent ID: 11869854
Assignee: WINBOND ELECTRONICS CORP.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. A semiconductor structure, comprising:
a first semiconductor wafer, comprising a first semiconductor substrate and a first inductance layer, wherein the first inductance layer is disposed on the first semiconductor substrate, one side of the first inductance layer away from the first semiconductor substrate has a first bonding surface, and the first inductance layer comprises a start metal trace, a plurality of first metal traces, a plurality of first interconnect structures and a first insulating layer, wherein
the start metal trace and the plurality of first metal traces are arranged side by side, the start metal trace has an input terminal and a first terminal, and each of the plurality of first metal traces has a first connection terminal and a second connection terminal,
the first insulating layer covers the start metal trace and the plurality of first metal traces,
the plurality of first interconnect structures are embedded in the first insulating layer, and the first terminal, each of the first connection terminals, and each of the second connection terminals are each electrically connected to one of the plurality of first interconnect structures; and

a second semiconductor wafer, comprising a second semiconductor substrate and a second inductance layer, wherein the second inductance layer is disposed on the second semiconductor substrate, one side of the second inductance layer away from the second semiconductor substrate has a second bonding surface, and the second inductance layer comprises a plurality of second metal traces, a plurality of second interconnect structures and a second insulating layer, wherein
the plurality of second metal traces are arranged side by side, and each of the plurality of second metal traces has a third connection terminal and a fourth connection terminal,
the second insulating layer covers the plurality of second metal traces,
the plurality of second interconnect structures are embedded in the second insulating layer, and the third connection terminals and the fourth connection terminals are each electrically connected to one of the plurality of second interconnect structures,

wherein, the first semiconductor wafer and the second semiconductor wafer are coupled to each other, the first bonding surface of the first inductance layer is bonded to the second bonding surface of the second inductance layer, the first insulating layer on the first bonding surface and the second insulating layer on the second bonding surface form a first bond, the plurality of first interconnect structures on the first bonding surface and the plurality of second interconnect structures on the second bonding surface respectively form a second bond, and the start metal trace, the plurality of first metal traces, the plurality of first interconnect structures, the plurality of second metal traces and the plurality of second interconnect structures form a multi-circle continuous and non-intersecting path and constitute an inductance element.