Patent ID: 11967571
Assignee: FUJIAN JINHUA INTEGRATED CIRCUIT CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. A method of fabricating a semiconductor structure, the method comprising:
providing a substrate formed thereon with at least one semiconductor device and an interlayer dielectric layer covering the semiconductor device;
forming a contact hole in the interlayer dielectric layer, the contact hole extending through the interlayer dielectric layer to the semiconductor device;
forming a conductive material layer on the interlayer dielectric layer, the conductive material layer filling the contact hole and covering a top surface of the interlayer dielectric layer;
forming an interconnect structure and a second contact pad by patterning the conductive material layer, the interconnect structure comprising a contact plug filled in the contact hole and a first contact pad covering a top of the contact plug, the second contact pad spaced apart from a side edge of the first contact pad; and
performing an etching process on the interlayer dielectric layer between the first and second contact pads and stopping the etching process in the interlayer dielectric layer to form a trench.