Patent ID: 11875038
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A controller for a data storage device, comprising:
an input/output (I/O) to one or more memory devices comprising computer-readable instructions;
a processor coupled to the one or more memory devices configured to execute the computer-readable instructions and cause the controller to perform a method for allocating blocks to replace one or more defective blocks in a data storage device, the method comprising:
scanning a first free block list associated with a Chip Enable (CE) location in the data storage device responsive to detecting a defective block, wherein the CE location comprises a plurality of NAND group locations;
determining that there are no free blocks in the first free block list to replace the defective block, wherein:
the first free block list is refilled from a queue of free blocks from an unallocated block pool, wherein the first free block list is a subset of the unallocated block pool and distinct from the unallocated block pool; and
refilling the first free block list comprises selecting a free block from the unallocated block pool that has a same CE location as a free block allocated from the first free block list to refill the free block list;

scanning an unallocated block pool for a free block;
replacing the defective block with the free block allocated from the unallocated block pool when the free block is available from the unallocated block pool, wherein the defective block remains in a read-write mode;
allocating the free block responsive to receiving a write command for the CE location; and
programming data to the allocated free block, wherein the data is associated with the write command.