Patent ID: 11955989
Assignee: NANYA TECHNOLOGY CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC H

Claim 7:
8. The memory device according to claim 1, wherein in a test scheme for testing the syndrome decoder and the data corrector, the ECC circuit is configured to:
enter the third test mode during a first time period, and generate the parity information according to the normal data and write the parity information into the parity array by the parity/syndrome generator;
enter the first test mode during a second time period after the first time period, update the normal data with 1 bit error to obtain updated data, write the updated data to the data array and keep the parity information unchanged by the parity/syndrome generator; and
re-enter the third test mode during a third time period after the second time period, read the updated data in the data array to obtain readout data, and generate a test result by comparing the readout data with an expectation data.