Patent ID: 11954061
Assignee: BEIJING TSINGMICRO INTELLIGENT TECHNOLOGY CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 1:
2. The mapping method for the reconfigurable array according to claim 1, wherein the S5 comprises:
S51: setting a first group of binary mapping variables and a second group of binary mapping variables, where the first group of binary mapping variables are mapping variables from each processing vertex in the data dependence graph to each processing element of the reconfigurable architecture, and the second group of binary mapping variables are mapping variables from each edge in the data dependence graph to each link, which are between and connecting each processing element, of the reconfigurable architecture;
S52: setting an objective function to minimize a number of the links used for the mapping;
S53: setting each processing vertex in the data dependence graph to be mapped to one processing element, setting one processing element of one layer configuration to map at most one processing vertex;
S54: setting one processing vertex in the data dependence graph to be only mapped to the processing element that performs the operation;
S55: setting each edge in the data dependence graph to be mapped to at least one link;
S56: setting one link of one layer configuration to map at most one edge;
S57: setting a first connectivity constraint for the intra-cycle edge, wherein the first connectivity constraint is such that when an ith processing vertex is mapped to a jth processing element, an edge connected from the ith processing vertex is mapped to a link connected from the jth processing element, where i and j are positive integers;
S58: setting a second connectivity constraint for the intra-cycle edge, wherein the second connectivity constraint ensures that when the ith processing vertex is mapped to the jth processing element, an edge connected to the ith processing vertex is mapped to a link connected to the jth processing element;
S59: setting a third connectivity constraint for the inter-cycle edge, wherein the third connectivity constraint is such that when the ith processing vertex is mapped to the jth processing element, the edge connected from the ith processing vertex is mapped to the link connected from the jth processing element, and a target solution of the third connectivity constraint is an edge indicating a dependency across different cycles in the data dependence graph and a modulo of the initial interval;
S510: setting a fourth connectivity constraint for the inter-cycle edge, wherein the fourth connectivity constraint ensures that when the ith processing vertex is mapped to the jth processing element, an edge connected to the ith processing vertex is mapped to a link connected to the jth processing element, and a target solution of the fourth connectivity constraint is an edge indicating a dependency across different cycles in the data dependence graph and a modulo of the initial interval;
S511: setting a first continuity constraint for the intra-cycle edge, wherein when the first continuity constraint is for the jth processing element, if the ith processing vertex has one ath input edge and the ath input edge is mapped to one input link of the jth processing element, the ith processing vertex is mapped to the jth processing element, or the ath input edge is simultaneously mapped to one output link of the jth processing element;
S512: setting a second continuity constraint for the intra-cycle edge, wherein when the second continuity constraint is for the jth processing element, if the ith processing vertex has one ath output edge and the ath output edge is mapped to one output link of the jth processing element, the ith processing vertex is mapped to the jth processing element, or the ath output edge is simultaneously mapped to one input link of the jth processing element;
S513: setting a third continuity constraint for the inter-cycle edge, wherein when the third continuity constraint is for the jth processing element, if the ith processing vertex has one ath input edge and the ath input edge is mapped to one input link of the jth processing element, the ith processing vertex is mapped to the jth processing element, or the ath input edge is simultaneously mapped to one output link of the jth processing element, and a target solution of the third continuity constraint is an edge indicating a dependency across different cycles in the data dependence graph and a modulo of the initial interval;
S514: setting a fourth continuity constraint for the inter-cycle edge, wherein when the fourth continuity constraint is for the jth processing element, if the ith processing vertex has one ath output edge and the ath output edge is mapped to one output link of the jth processing element, the ith processing vertex is mapped to the jth processing element, or the ath output edge is simultaneously mapped to one input link of the jth processing element, and a target solution of the fourth continuity constraint is an edge indicating a dependency across different cycles in the data dependence graph and a modulo of the initial interval;
S515: setting that if one edge in the data dependence graph is simultaneously mapped to one input link and one output link of one processing element, the processing element cannot map the processing vertex in the data dependence graph; and
S516: setting one processing element of one layer configuration to map only one route.