Patent ID: 11923863
Assignee: INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 5:
6. A Field Programmable Gate Array (FPGA)-based design device for equally dividing an interval, comprising:
one or more processor; and
a memory storing computer-readable instructions executable on the one or more processor, the computer-readable instructions, when executed by the one or more processor, implementing the following steps:
dividing oscillation periods of a second pulse signal of a crystal oscillator clock of a FPGA board by a number of equally divided sampling pulses and obtaining a remainder thereof;
dividing the remainder by the number of the equally divided sampling pulses to serve as an error within each sampling interval; and
using a counter to count from the second pulse signal and stopping counting of the counter whenever the error within the sampling interval, which is accumulated within a second pulse interval, is greater than or equal to the oscillation period.