Patent ID: 11901892
Assignee: MEDIATEK INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. A level shifter, comprising:
an input pair, having a first input transistor and a second input transistor which are controlled by an input signal and an inverse input signal of the level shifter, respectively;
a cross-coupled output pair, having a first output transistor and a second output transistor, wherein the second output transistor pulls up an output terminal of the level shifter to an overdrive voltage in response to a high-level state of the input signal, and the first output transistor pulls up an inverting output terminal of the level shifter to the overdrive voltage in response to a low-level state of the input signal;
a first protection circuit, coupled between the inverting output terminal and the first input transistor; and
a second protection circuit, coupled between the output terminal and the second input transistor;
wherein:
the overdrive voltage is twice a nominal voltage of the level shifter plus a delta voltage;
the first protection circuit comprises a first voltage-drop circuit that compensates for the delta voltage, and a third series of transistors coupled between the inverting output terminal and the first voltage-drop circuit, wherein the third series of transistors each has a gate terminal biased by a specific voltage when the input signal is in the low-level state, and the specific voltage is divided from the overdrive voltage and greater than the nominal voltage, and, in response to the high-level state of the input signal, a lower transistor in the third series of transistors has connected gate and drain terminals; and
the second protection circuit comprises a second voltage-drop circuit that compensates for the delta voltage, and a fourth series of transistors coupled between the output terminal and the second voltage-drop circuit, wherein the fourth series of transistors each has a gate terminal biased by the specific voltage when the input signal is in the high-level state, and, in response to the low-level state of the input signal, a lower transistor in the fourth series of transistors has connected gate and drain terminals.