Patent ID: 11925033
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method comprising:
forming a first protection layer over a first substrate and a second protection layer over the first substrate;
forming a first nanosheet field effect transistor (NSFET) arranged over the first protection layer and comprising first nanosheet channel structures, a first source/drain region, a second source/drain region, and a first gate electrode;
forming a second NSFET over the second protection layer and comprising second nanosheet channel structures, the second source/drain region, a third source/drain region, and a second gate electrode;
forming a first interconnect structure over the first and second NSFETs, wherein the first interconnect structure comprises interconnect wires and interconnect vias embedded in an interconnect dielectric structure;
forming a bonding layer over the first interconnect structure;
bonding a carrier substrate to the bonding layer;
flipping the first substrate over to pattern a backside of the first substrate;
removing the first substrate completely to expose the first, second, and third source/drain regions and the first and second protection layers, wherein the first, second, and third source/drain regions overlie the first interconnect structure and have individual top surfaces elevated relative to individual top surfaces of the first and second protection layers at a beginning of the removing;
forming a dielectric layer over the first, second, and third source/drain regions and the first and second protection layers;
forming a contact plug structure extending through the dielectric layer and coupled to the second source/drain region that is arranged between the first and second NSFETs;
forming a memory structure over and coupled to the contact plug structure; and
forming a second interconnect structure over and coupled to the memory structure.