Patent ID: 11881480
Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 15:
16. The method according to claim 12, before forming the first dummy gate structure and the second dummy gate structure, further comprising:
forming a first isolation layer on the first region, wherein the first isolation layer is on a portion of a sidewall of the initial first nanostructure and a portion of a sidewall of the initial second nanostructure, and a top surface of the first isolation layer is lower than a top surface of the initial first nanostructure and a top surface of the initial second nanostructure; and
forming a second isolation layer on the second region, wherein the second isolation layer is on a portion of a sidewall of the initial third nanostructure and a portion of a sidewall of the initial fourth nanostructure, and a top surface of the second isolation layer is lower than a top surface of the initial third nanostructure and a top surface of the initial fourth nanostructure.