Patent ID: 11862232
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 6:
7. The circuit for data transmission of claim 1, wherein the mode register read-write module comprises a mode register read module, and the mode register read module comprises a plurality of first buffer units, an output driving unit, and a second buffer unit;
the first buffer unit is configured such that: an input end is configured to receive data cached by the mode register read-write module; and a control end is configured to receive the mode register read enable signal and output an inversion signal of a received signal according to the mode register read enable signal;
the second buffer unit is configured such that: an input end is electrically connected to a preset voltage; and a control end is configured to receive the mode register unselected enable signal and output an inversion signal of the preset voltage according to the mode register unselected enable signal; and
the output driving unit is configured such that: an input end is electrically connected to the second buffer unit and each first buffer unit; and an output end is electrically connected to the first cache module and configured to: output a selected data, and output an unselected data according to the inversion signal of the preset voltage after setting the unselected data to zero, to provide to the first cache module.