Patent ID: 11936378
Assignee: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. The interface circuit according to claim 6, wherein the driving bias generation circuit comprises two operational amplifiers comprising a second operational amplifier, and a third operational amplifier, a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6, wherein a positive end of the second operational amplifier is connected to the high level voltage VH, a negative end of the second operational amplifier is connected to drains of the fifth transistor M5 and the sixth transistor M6 and the fourth current, and a negative-phase output end of the second operational amplifier is connected to a gate of the first transistor M1 and outputs the first bias voltage Vb1; wherein a positive end of the third operational amplifier is connected to the low level voltage VL, a negative end of the third operational amplifier is connected to drains of the third transistor M3 and the fourth transistor M4 and the third current, and a positive-phase output end of the third operational amplifier is connected to a gate of the second transistor M2 and outputs the second bias voltage Vb2; and wherein gates of the third transistor M3 and the fourth transistor M4 are connected to a logic high level 1, and gates of the fourth transistor M4 and the sixth transistor M6 are connected to a logic low level 0.