Patent ID: 11862580
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor package, comprising:
a wiring substrate having a first surface and a second surface opposite to the first surface;
a semiconductor component disposed on the first surface of the wiring substrate and comprising semiconductor dies laterally spaced from each other by a die gap;
a molding material laterally surrounding and encapsulating the semiconductor dies and filling the die gap;
conductor terminals disposed on the second surface of the wiring substrate and electrically connected to the semiconductor component through the wiring substrate; and
a bottom stiffener disposed on the second surface of the wiring substrate and positioned between the conductor terminals, wherein the bottom stiffener extends along one or more side edges of the molding material.