Patent ID: 11897758
Assignee: ROBERT BOSCH GMBH
Field: Micro-structural and nano-technology (Chemistry)
Classification: CPC B | IPC B

Claim 13:
14. The method as recited in claim 9, wherein:
in a first pre-step, a structure is formed in a silicon layer of an SOI wafer or SOI chip;
in a second pre-step, after the first pre-step, a third insulator is situated at least partly in the structure, and a third insulating layer is situated above the silicon layer;
in a third pre-step, after the second pre-step, the third insulating layer is removed in a second contact region;
in a fourth pre-step, after the third pre-step, the conductor layer is situated on the third insulating layer, and in the second contact region, a direct contact is formed between the conductor layer and the silicon layer, the conductor layer being structured in such a way that the conductor region is formed, which is insulated from the further conductor region of the conductor layer by the second configuration of recesses;
in a fifth pre-step, after the fourth pre-step, a second insulating layer is situated on the conductor layer, a second insulator being situated in the second configuration of recesses; and
in a sixth pre-step, after the fifth pre-step and before the first step, the second insulating layer is removed in a first contact region at the conductor region.