Patent ID: 11955981
Assignee: MICRON TECHNOLOGY, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A memory device, comprising:
a clock input configured to receive a clock from a host device;
a command input configured to receive command and address bits from the host device; and
a plurality of die stacked in a three-dimensional stack, wherein a first die of the plurality of die comprises:
a first plurality of memory cells; and
first local control circuitry comprising:
division circuitry configured to:
receive the clock from the clock input;
generate a divided clock having a lower frequency than that of the clock; and
generate a plurality of component clocks from the divided clock with each of the plurality of component clocks having a lower frequency than the divided clock; and

one or more transmitters configured to transmit the plurality of component clocks using a plurality of inter-die interconnects between the plurality of die.