Patent ID: 11868262
Assignee: MARVELL ASIA PTE LTD
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A method, comprising:
receiving a plurality of memory requests comprising a plurality of addresses, wherein each memory request of the plurality of memory requests comprises a respective address of the plurality of addresses; and
hashing the addresses of the memory requests using a plurality of hashes to distribute the memory requests among a plurality of memory components of a computer system, wherein the plurality of memory components comprises a plurality of caches, a plurality of memory controllers coupled to the plurality of caches, and a plurality of memories coupled to the plurality of memory controllers, and wherein each memory of the plurality of memories comprises a plurality of bank groups;
wherein each hash of the plurality of hashes is respectively programmed to achieve a specific distribution of the plurality of memory requests among the plurality of memory components.