Patent ID: 11972827
Assignee: WINBOND ELECTRONICS CORP.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A semiconductor storage device, comprising:
a Not AND (NAND) chip, comprising an NAND-type memory array, a page buffer/sensing circuit, and a control member, wherein the page buffer/sensing circuit comprises a first latch and a second latch that are able to hold page data read from a memory array, the control member controls a read operation; and
an error checking and correcting (ECC) chip, comprising error detection and correction functions,
wherein the first latch comprises a first holding portion for holding a first data portion of the page data, and a second holding portion for holding a second data portion,
the second latch has a data size smaller than that of the first latch, and holds the second data portion transmitted from the second holding portion of the first latch,
after the control member transmits the first data portion held by the first holding portion of the first latch to the ECC chip, the control member transmits the second data portion held by the second latch to the ECC chip,
the ECC chip performs error detection and correction of the first data portion and the second data portion,
the control member reads a next page from the memory array in response to a timing when the ECC chip outputs the first data portion to the outside.