Patent ID: 11942396
Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A heterogeneous integration semiconductor package structure, comprising:
a heat dissipation assembly, having a connection surface, and comprising a two-phase flow heat dissipation device and a first redistribution structure layer embedded in the connection surface;
a plurality of chips, disposed on the connection surface of the heat dissipation assembly and electrically connected to the first redistribution structure layer;
a package assembly, disposed on the connection surface of the heat dissipation assembly and surrounding the chips, wherein the package assembly has an upper surface adjacent to the connection surface and a lower surface opposite to the upper surface and comprises a second redistribution structure layer disposed on the lower surface and a plurality of conductive vias electrically connected to the first redistribution structure layer and the second redistribution structure layer;
a plurality of connectors, disposed on the package assembly, and electrically connected to the second redistribution structure layer; and
a circuit substrate, electrically connected to the second redistribution structure layer of the package assembly through the connectors;
wherein the package assembly comprises a cover with a groove, the chips are located in the groove, the conductive vias and the second redistribution structure layer are embedded in the cover, and one end of each of the conductive vias and a surface of the second redistribution structure layer are exposed outside the cover; and
wherein there is an air gap between the connection surface of the heat dissipation assembly and a bottom surface of the groove.