Patent ID: 11954045
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. A non-transitory machine-readable storage medium including instructions that, when executed by one or more processors, causes the one or more processors to:
receive a first request to perform a memory access operation for an address range in a memory allocation containing data contents or code contents, wherein the address range includes at least one address in a first cacheline and at least one address in a second cacheline;
identify a first portion of the first cacheline, wherein the first portion of the first cacheline is to include some of the address range and is to be identified based at least in part on a first data bounds value stored in a metadata region located within the first cacheline, wherein the first data bounds value indicates a size of first data of the data contents or first code of the code contents contained within the first portion of the first cacheline;
generate a first integrity value based on the first portion of the first cacheline; and
prevent the memory access operation based on the first integrity value not corresponding to a second integrity value stored in the metadata region.