Patent ID: 11942368
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A method comprising:
depositing a first low-k dielectric layer over a semiconductor substrate;
forming, within the first low-k dielectric layer, a first via, a first metal line over the first via, a first metal ring coplanar with the first via, and a second metal ring coplanar with the first metal line and on the first metal ring;
depositing a second low-k dielectric layer over the first metal line;
forming, within the second low-k dielectric layer, a second via, a second metal line over the second via, a third metal ring coplanar with the second via and on the second metal ring, and a fourth metal ring coplanar with the second metal line and on the third metal ring; and
forming an opening, wherein the forming the opening includes etching the first low-k dielectric layer and the second low-k dielectric layer to form an opening extending through a center region of each of the first metal ring, the second metal ring, the third metal ring, and the fourth metal ring; and
filling the opening with conductive material.