Patent ID: 11894850
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 9:
10. The delay circuit according to claim 8, wherein the linear voltage regulator unit comprises a first output terminal and/or a second output terminal, wherein the first output terminal outputs the first power supply control signal, and the second output terminal outputs the second power supply control signal;
wherein the delay circuit further comprises a second capacitor and/or a third capacitor, wherein a first terminal of the second capacitor is connected to the first output terminal of the linear voltage regulator unit, and wherein a second terminal of the second capacitor is grounded; and
wherein a first terminal of the third capacitor is connected to the second output terminal of the linear voltage regulator unit, and wherein the second terminal of the second capacitor is grounded.