Patent ID: 11864371
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. A semiconductor structure, comprising:
a substrate, the substrate having a first surface and a second surface opposite to each other, a plurality of transistors being arranged on the second surface, and the transistors being arranged in an array; and
a conductive structure, the conductive structure comprising a conductive body and a plurality of conductive bumps arranged on the conductive body, the conductive body being arranged on the first surface, the conductive bumps and the transistors being arranged in one-to-one correspondence, and ends of the conductive bumps away from the conductive body passing through the substrate and sources of the transistors and then being communicated with channel regions of the transistors,
wherein the substrate is provided with a plurality of bit line structures arranged in a row direction of the transistors, top surfaces of the bit line structures are located on the second surface, and the sources of the transistors are connected to the bit line structures.