Patent ID: 11907156
Assignee: STMICROELECTRONICS (ALPS) SAS
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. A system-on-chip, comprising:
a slave device;
a master device coupled to the slave device, the master device configured to emit a first access request to the slave device;
a clock circuit coupled to the slave device, the clock circuit configured to clock an operation of the slave device;
a clock controller coupled to the slave device, the clock controller configured to activate or deactivate the clock circuit;
a power-on controller coupled to the slave device, the power-on controller configured to power-on or power-off the slave device; and
a control system configured to generate an interruption based on determining that the clock circuit is deactivated or the slave device is powered-off, and
wherein the master device is further configured to:
activate the clock circuit based on the control system determining that the clock circuit is deactivated in response to receiving the interruption,
power-on the slave device based on the control system determining that the slave device is powered-off in response to receiving the interruption, and
emit a second access request to the slave device after the clock circuit is activated or the slave device is powered-on.