Patent ID: 11894077
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. The controller as set forth in claim 10, wherein the predetermined threshold criteria includes a predetermined upper loop quantity threshold and a predetermined lower loop quantity threshold and the controller is further configured to:
determine whether the quantity of the plurality of smart verify loops is greater than or equal to the predetermined upper loop quantity threshold;
determine whether the quantity of the plurality of smart verify loops is less than or equal to the predetermined lower loop quantity threshold in response to the quantity of the plurality of smart verify loops not being greater than or equal to the predetermined upper loop quantity threshold; and
instruct the memory apparatus to end the program operation in response to the quantity of the plurality of smart verify loops not being less than or equal to the predetermined lower loop quantity threshold.