Patent ID: 11967624
Assignee: HITACHI, LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A semiconductor device comprising:
a semiconductor chip having a first gate pad and a second gate pad in a main surface;
a first wiring provided outside the semiconductor chip and electrically connected to the first gate pad;
a second wiring provided outside the semiconductor chip and electrically connected to the second gate pad; and
a first voltmeter connected between the first wiring and the second wiring,
wherein the semiconductor chip includes:
a substrate of a first conductivity type;
a source region of a second conductivity type different from the first conductivity type, which is formed in an upper surface of the substrate;
a drain region of the second conductivity type formed in a lower surface of the substrate;
a first gate electrode formed on the substrate and electrically connected to the first gate pad; and
a second gate electrode formed on the substrate and electrically connected to the second gate pad,
wherein the first gate electrode, the source region, and the drain region constitute a first field effect transistor,
wherein the second gate electrode, the source region, and the drain region constitute a second field effect transistor,
wherein a planar shape of each of the first gate electrode and the second gate electrode is comb-shaped, and
wherein the first gate electrode and the second gate electrode are disposed such that mutual comb-teeth parts mesh with each other.