Patent ID: 11914451
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus, comprising:
a first power node configured to receive a first power voltage;
a second power node configured to receive a second power voltage;
a first internal power node;
a second internal power node;
a first clamp circuit coupled to the first power node and the first internal power node, the first clamp circuit configured to hold the first internal power node at a first voltage level based on the first power voltage;
a second clamp circuit coupled to the first power node and the second internal power node, the second clamp circuit configured to hold the second internal power node at a second voltage level based on the first power voltage, the second voltage level greater than the first voltage level;
a third clamp circuit coupled to the second power node and the second internal power node, the third clamp circuit configured to hold the second internal power node at a third voltage level based on the second power voltage when the second power voltage reaches a trigger voltage level, the third voltage level greater than the first and second voltage levels.