Patent ID: 11914516
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A non-transitory machine readable medium including that, when executed by processing circuitry, cause the processing circuitry to perform operations comprising:
determining a cache set for a memory request, the cache set having multiple ways, each way corresponding to a cache line;
detecting that a way of the multiple ways is not ready for the memory request;
storing a representation of the memory request in a queue of multiple queues based on:
an interface upon which the memory request was received; and
present ways of the cache set;

dequeuing entries from the multiple queues in a defined order to determine a next memory request to process, the defined order giving priority to memory requests that match a present way over memory requests that do not match a present way, and the defined order giving priority to memory requests from an external interface over memory requests from an internal interface; and
processing the memory request in response to the representation of the memory request being dequeued.