Patent ID: 11923324
Assignee: KIOXIA CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 5:
6. The semiconductor memory device according to claim 1, further comprising:
a plurality of first driving circuits connected to the plurality of first bonding pad electrodes respectively, each of the plurality of first driving circuits including a plurality of transistors connected in parallel between the first bonding pad electrode of the plurality of first bonding pad electrodes and a voltage supply line; and
a plurality of second driving circuits connected to the plurality of first bonding pad electrodes respectively, each of the plurality of second driving circuits including a comparator connected to the first bonding pad electrode, wherein
the substrate includes a plurality of third regions disposed at positions away from the plurality of first regions and the plurality of second regions in the third direction, the plurality of third regions being arranged in the second direction, and
the plurality of third regions each include a plurality of transistors constituting one of the plurality of first driving circuits and a plurality of transistors constituting one of the plurality of second driving circuits.