Patent ID: 11972817
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. The controller as set forth in claim 8, wherein the memory apparatus further includes a first data latch configured to store a first status bit and a second data latch configured to store a second status bit and wherein the strings are each coupled to one of a plurality of bit lines and the controller is further configured to:
categorize the memory cells using the first status bit and the second status bit; and
update the first status bit and the second status bit based on sensing the memory cells targeted for the selected one of the plurality of data states identified as being faster to program than other ones of the memory cells targeted for the selected one of the plurality of data states during the one of the plurality of verify loops associated with the earlier one of the plurality of data states.