Patent ID: 11869829
Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor device, comprising:
a substrate having a top major surface and a bottom major surface opposite to the top major surface;
an electrically conductive pattern adjoining the top major surface;
conductive lands adjoining the bottom major surface and including a first conductive land, a second conductive land, a third conductive land, and a fourth conductive land;
conductive vias within the substrate and connecting part of the electrically conductive pattern to the conductive lands, the conductive vias including a first conductive via having a first width in a cross-sectional view and connected to the third conductive land;
conductive bumps;
a first semiconductor die mounted to the first conductive land and the second conductive land with the conductive bumps;
an electronic component electrically connected to the electrically conductive pattern of the substrate and mounted on the top major surface of the substrate;
a first package body encapsulating the first semiconductor die and comprising a bottom exterior surface distal to the bottom major surface of the substrate;
a second package body encapsulating the electronic component;
a first electrically conductive path physically and electrically connected to the third conductive land and extending to the bottom exterior surface of the first package body having a second width in the cross-sectional view that is greater than the first width; and
a second electrically conductive path physically and electrically connected to the fourth conductive land and extending to the bottom exterior surface of the first package body, wherein:
the first electrically conductive path comprises a first outer surface exposed from the bottom exterior surface of the first package body and configured as a first external electrical interconnect structure; and
the second electrically conductive path comprises a second outer surface exposed from the bottom exterior surface of the first package body and configured as a second external electrical interconnect structure.