Patent ID: 11903330
Assignee: NEW YORK UNIVERSITY
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A method, comprising:
providing a stack, the stack comprising:
a substrate;
a two-dimensional electron gas layer disposed on the substrate; and
a superconducting layer disposed on the two-dimensional electron gas layer;

etching the stack;
removing a portion of the superconducting layer to form a weak link region;
depositing a first dielectric layer on the stack;
depositing a first gate electrode on a first portion of the first dielectric layer, the first gate electrode configured to deplete charge carriers from a first portion of the two-dimensional electron gas layer; and
depositing a second gate electrode on a second portion of the first dielectric layer, the second gate electrode configured to deplete charge carriers from a second portion of the two-dimensional electron gas layer.