Patent ID: 11922992
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A memory device comprising:
a memory cell array including a plurality of memory cells connected to a plurality of sub word lines connected to a plurality of main word lines;
a main row decoder configured to generate a plurality of main word line driving signals based on a row address;
a sub row decoder configured to generate a plurality of sub word line signals based on the row address;
a sub word line driving signal generating circuit configured to generate a plurality of first sub word line driving signals by delaying the plurality of sub word line signals and generate a plurality of second sub word line driving signals by inverting the plurality of sub word line signals;
a sub word line driving signal encoder configured to generate a plurality of first encoded sub word line driving signals by outputting the plurality of first sub word line driving signals in different orders or generate a plurality of second encoded sub word line driving signals by outputting the plurality of second sub word line driving signals in different orders based on whether an odd main word line or an even main word line is driven by the plurality of main word line driving signals; and
a sub word line driving circuit configured to receive the plurality of main word line driving signals, receive the plurality of first encoded sub word line driving signals or the plurality of second encoded sub word line driving signals, and drive a target word line among the plurality of sub word lines at a first voltage level or a second voltage level.