Patent ID: 11864377
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 19:
20. A semiconductor structure, comprising:
a substrate and a first conductive layer disposed on the substrate;
a second conductive layer disposed on a surface of the first conductive layer away from the substrate; and
third conductive layers covering side walls of the first conductive layer and in contact with the second conductive layer, wherein contact resistance between the third conductive layers and the second conductive layer is less than contact resistance between the first conductive layer and the second conductive layer,
wherein each side wall of the first conductive layer comprises a first sub-side wall and a second sub-side wall which extend upward from a bottom of the first conductive layer; the first sub-side wall is disposed between the second sub-side wall and the bottom of the first conductive layer; and each third conductive layer covers a respective second sub-side wall.