Patent ID: 11967373
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 15:
16. An apparatus, comprising:
a memory array including a plurality of memory cells; and
decoder circuitry coupled to the array of memory cells, wherein the decoder circuitry comprises a p-type transistor having a first gate, a first n-type transistor having a second gate, and a second n-type transistor having a third gate; and
pre-decoder circuitry configured to provide a bias condition for the first gate, the second gate, and the third gate to provide a selection signal to one of the plurality of memory cells, wherein the pre-decoder circuitry includes a NAND logic gate, a first NOR logic gate, and a second NOR logic gate, wherein:
the NAND logic gate is configured to receive a first pre-decoded address signal having a pre-decoded high voltage value relative to a pre-decoded low voltage value and a second pre-decoded address signal having the pre-decoded high voltage value;
the first NOR logic gate is configured to receive a third pre-decoded address signal having a different pre-decoded high voltage value relative to a different pre-decoded low voltage value and a fourth pre-decoded address signal having the different pre-decoded high voltage value; and
the second NOR logic gate is configured to receive the third pre-decoded address signal and the fourth pre-decoded address signal.