Patent ID: 11880585
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A semiconductor memory, comprising:
at least one storage array, the storage array comprising a plurality of data storage units and a plurality of check bit storage units;
a check module, configured to receive written data and generate check data according to the written data; and
a data transmission module, respectively connected to the check module and the at least one storage array, the data transmission module being configured to transmit the written data to the plurality of data storage units and transmit the check data to the plurality of check bit storage units;
wherein a first transmission time duration of the check data is shorter than a second transmission time duration of the written data, the first transmission time duration being a time duration required for transmitting the check data from the data transmission module to the plurality of check bit storage units, and the second transmission time duration being a time duration required for transmitting the written data from the data transmission module to the plurality of data storage units;
wherein the check module comprises a first check unit and a second check unit, the data transmission module comprising a first transmission unit and a second transmission unit, one of two of the plurality of storage units positioned in adjacent columns being connected to the first check unit via the first transmission unit, and the other one of two of the plurality of storage units being connected to the second check unit via the second transmission unit.