Patent ID: 11949539
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 10:
11. The buffer IC of claim 10 wherein the sequence of sampling intervals is constituted by first and second subsets of sampling intervals, and wherein the sampling circuitry to sample the signaling link during each of the sequence of sampling intervals comprises circuitry to sample the signaling link during each sampling interval of the first subset and then sample the signaling link during each sampling interval of the second subset, and wherein the equalization circuitry to generate the equalization signal for each of the sampling intervals based on either the logic state of one or more previously generated data bits or one or more bit values having predetermined logic states comprises circuitry to generate, for an initial sampling interval of the second subset, an equalization signal based on (i) the logic state of a data bit generated for a trailing sampling interval of the first subset if the trailing sampling interval of the first subset and the initial sampling interval of the second subset transpire back-to-back and (ii) the one or more bit values having predetermined logic states if the trailing sampling interval of the first subset and the initial sampling interval of the second subset are separated by a time interval in which no data is conveyed to the buffer IC via the signaling link.