Patent ID: 11894052
Assignee: ALMA MATER STUDIORUM—UNIVERSITA' DI BOLOGNA
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. An in-memory computation circuit, comprising:
a memory array including a plurality of memory cells arranged in a matrix with plural rows and plural columns, the memory cells storing computational weights for an in-memory compute operation, each row including a word line connected to the memory cells of the row, and each column including a bit line connected to the memory cells of the column;
a switching circuit for each bit line, each switching circuit coupled between the bit line and a column output and controlled to turn on for a time duration corresponding to coefficient data for said in-memory compute operation;
wherein an analog signal at the column output is dependent on the coefficient data and computational weight; and
a column combining circuit configured to combine and integrate the analog signals generated at the column outputs of the switching circuits.