Patent ID: 11940835
Assignee: FMAD ENGINEERING (SNG) PTE. LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A method comprising:
receiving a signal indicative of an edge of a reference clock, wherein the reference clock has a fixed clock period, wherein a hardware clock signal generator ticks at a variable clock period, and wherein a local time value is increased by a local time increment on ticks of the hardware clock signal generator;
in response to receiving the signal, reading the local time value and writing it to a memory as a current time value;
determining a difference between the current time value and a previous time value that was written to the memory in response to receiving a previous signal from the reference clock, wherein the previous time value is based on a previous reading of the local time value;
based on the difference, determining an adjustment to the local time increment so that the local time value increases at a rate that is closer to that of the reference clock; and
modifying the local time increment by the adjustment.