Patent ID: 11917803
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 7:
8. A method, comprising:
receiving a workpiece comprising:
a substrate having a first area and a second area,
a first fin element disposed over the first area and comprising a first plurality of channel layers interleaved by a first plurality of sacrificial layers, the first fin element having a channel region and a source/drain region, and
a second fin element disposed over the second area and comprising a second plurality of channel layers interleaved by a second plurality of sacrificial layers, the second fin element having a channel region and a source/drain region;

forming a first dummy gate stack over the channel region of the first fin element and a second dummy gate stack over the channel region of the second fin element;
forming a first source/drain recess over the source/drain region of the first fin element and a second source/drain recess over the source/drain region of the second fin element;
selectively forming inner spacer features to interleave the first plurality of channel layers in the first area while the second area is covered by a first mask layer;
forming a first source/drain feature in the first source/drain recess and a second source/drain feature in the second source/drain recess;
removing the first dummy gate stack and the second dummy gate stack;
after the removing, selectively removing the first plurality of sacrificial layers in the channel region of the first fin element while the second area is covered by a second mask layer; and
forming a first gate structure to wrap around each of the first plurality of channel layers and a second gate structure over the channel region of the first fin element.