Patent ID: 11961801
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. Memory circuitry comprising strings of memory cells, comprising:
two memory-array regions having a stair-step region there-between;
memory blocks in each of the two memory-array regions that individually comprise a vertical stack comprising alternating insulative tiers and conductive tiers, channel-material strings of memory cells extending through the insulative tiers and the conductive tiers in the memory blocks in the two memory-array regions;
walls that are individually between immediately-adjacent of the memory blocks, the walls extending in a first direction from one of the two memory-array regions into the other of the two memory-array regions across the stair-step region;
the insulative tiers and the conductive tiers extending along the first direction from the two memory-array regions into the stair-step region, the conductive tiers individually comprising a conductive line that extends across the stair-step region along the first direction into and within individual of the memory blocks in each of the two memory-array regions;
first stair-step structures that alternate with second stair-step structures along the first direction within the stair-step region laterally between immediately-adjacent of the walls;
the first stair-step structures individually comprising two opposing first flights of stairs in a first vertical cross-section along the first direction, the stairs of the first flights each having multiple different-depth treads in a second vertical cross-section that is along a second direction that is orthogonal to the first direction; and
the second stair-step structures individually comprising two opposing second flights of stairs in the first vertical cross-section, the stairs in the second flights each having only a single one tread along the second direction.