Patent ID: 11935955
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method comprising:
forming a dummy gate over and along sidewalls of a fin extending upwards from a substrate;
forming a gate spacer along a sidewall of the dummy gate;
etching a recess in the fin adjacent the gate spacer;
epitaxially growing a source/drain region in the recess, comprising:
growing a first doped semiconductor layer lining the recess, the first doped semiconductor layer comprising a silicon-containing compound and a first n-type dopant; and
growing a second doped semiconductor layer on the first doped semiconductor layer, the second doped semiconductor layer comprising a second n-type dopant that is different from the first n-type dopant, wherein a portion of the second doped semiconductor layer is free of the first n-type dopant; and

replacing the dummy gate with a gate stack disposed over and along sidewalls of the fin.