Patent ID: 11948806
Assignee: STMICROELECTRONICS S.R.L.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A method, comprising:
arranging first and second semiconductor dice onto a die pad of a metallic leadframe, wherein the first semiconductor die and the second semiconductor die each have sets of bonding pads at their front surfaces which are opposed to the die pad;
forming a layer of laser-activatable material onto said first semiconductor die, said second semiconductor die, and a set of electrically-conductive leads of the metallic leadframe arranged around the die pad;
patterning a set of laser-activated lines in said layer of laser-activatable material to include:
i) a first subset of laser-activated lines configured to couple selected bonding pads of said first semiconductor die to selected electrically-conductive leads in said set of electrically-conductive leads;
ii) a second subset of laser-activated lines configured to couple selected bonding pads of said first semiconductor die to selected bonding pads of said second semiconductor die; and
iii) a third subset of laser-activated lines configured to couple each of said laser-activated lines in said second subset of laser-activated lines to at least one laser-activated line in said first subset of laser-activated lines;

depositing a first metallic layer onto said first, second, and third subsets of laser-activated lines to provide respective first, second, and third subsets of electrically-conductive lines;
selectively depositing a second metallic layer onto said first and second subsets of electrically-conductive lines to provide respective first and second subsets of electrically-conductive tracks; and
selectively removing said electrically-conductive lines in said third subset of electrically-conductive lines.