Patent ID: 11929282
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. The method for preparing the semiconductor structure of claim 1, wherein forming the bit line array comprises:
forming a first patterned photoresist layer on the upper surface of the second dielectric layer, the first patterned photoresist layer being provided with a first opening, and the first opening being configured to limit a shape and a position of each of the bit line structures; and
etching, by using the first patterned photoresist layer as a mask, the portion of the second dielectric layer, the portion of the first dielectric material layer, the portion of the second conductive material layer, the portion of the barrier material layer and the portion of the first conductive material layer to form a second trench, the second trench exposing the side wall of each of the bit line structures.