Patent ID: 11923234
Assignee: STMICROELECTRONICS (TOURS) SAS
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 22:
23. A method, comprising:
forming a plurality of trenches through a semiconductor substrate and an interconnection layer, each of the plurality of trenches extending through a first face of the semiconductor substrate and a second face of the semiconductor substrate that is opposite the first face, the interconnection layer being on the second face of the semiconductor substrate, the semiconductor substrate including a plurality of integrated circuits, the plurality of trenches delimiting laterally a plurality of chips each including an integrated circuit of the plurality of integrated circuits, the interconnection layer including at least one metal connection pad for each of the plurality of chips; and
electrically isolating flanks of each of the plurality of chips by forming an electrically isolating layer on the first face of the semiconductor substrate and lateral walls of the plurality of trenches, the electrically isolating layer disposed on lateral walls of the semiconductor substrate and of the interconnection layer in the plurality of trenches, the electrically isolating layer including at least one of alumina, silicon dioxide, or titanium dioxide.