Patent ID: 11908514
Assignee: STMICROELECTRONICS (GRENOBLE 2) SAS
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 2:
3. The non-volatile memory device according to claim 2,
wherein each deselection logic circuit comprises a respective first PMOS transistor and a respective second PMOS transistor, each of which has conduction terminals respectively coupled to the corresponding wordline and the node at the first reference potential, and
wherein each deselection logic circuit is configured to:
turn on the respective first PMOS transistor when the corresponding wordline is deselected;
turn off the respective first PMOS transistor when the corresponding wordline is selected; and
turn off the respective second PMOS transistor when one of the wordlines that extend through the group of memory portions is selected and turn on the respective second PMOS transistor otherwise.