Patent ID: 11972269
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 14:
15. A system comprising:
at least one memory;
machine readable instructions; and
processor circuitry to at least one of instantiate or execute the machine readable instructions to:
associate a first stock keeping unit with a processor platform including a plurality of processor cores, respective ones of the processor cores configurable to be active or dormant, the first stock keeping unit associated with a first number of processor cores of the processor platform configured to be active, remaining ones of the processor cores to be dormant processor cores;
command the processor platform to activate one or more of the dormant processor cores to cause the processor platform to provide a second number of processor cores configured to be active; and
generate a second stock keeping unit for the processor platform, the second stock keeping unit associated with the processor platform having the second number of processor cores configured to be active.