Patent ID: 11860417
Assignee: CISCO TECHNOLOGY, INC.
Field: Optics (Instruments)
Classification: CPC G | IPC G

Claim 8:
9. A method of fabricating a silicon-insulator-silicon capacitive (SISCAP) apparatus, the method comprising:
doping a first silicon layer to increase a doping level of the first silicon layer to a first doping level;
after doping the first silicon layer to the first doping level, applying a first hard mask layer above the first silicon layer, wherein the first hard mask layer includes a plurality of first features;
after applying the first hard mask layer, etching a first trench and a second trench partly through the first silicon layer to form a first optical waveguide that includes (i) a first ridge beneath a first feature of the plurality of first features and between the first trench and the second trench, (ii) a second ridge beneath a second feature of the plurality of first features, and (iii) a third ridge beneath a third feature of the plurality of first features, wherein the first trench is between the first ridge and the second ridge, wherein the second trench is between the first ridge and the third ridge, wherein a first bottom of the first trench is exposed, and wherein a second bottom of the second trench is exposed;
after etching the first trench and the second trench, conformally depositing a first spacer layer on the plurality of first features, the first trench, and the second trench such that spacers are formed on sidewalls of the first trench and the second trench;
after depositing the first spacer layer, etching through the first spacer layer to expose the first bottom and the second bottom, wherein a width of an exposed portion of the first bottom is defined by the spacers formed on the sidewalls of the first trench, and a width of an exposed portion of the second bottom is defined by the spacers formed on the sidewalls of the second trench;
after etching the first spacer layer, doping the exposed portion of the first bottom and the exposed portion of the second bottom to a second doping level greater than the first doping level while the first feature keeps the first ridge at the first doping level;
depositing a first dielectric layer above the first optical waveguide such that the first dielectric layer extends to the first bottom and the second bottom;
depositing a second silicon layer above the first dielectric layer;
applying a second hard mask layer above the second silicon layer, wherein the second hard mask layer includes a plurality of second features;
etching a plurality of second trenches partly through the second silicon layer to form a second optical waveguide, wherein a fourth ridge is formed in the second optical waveguide beneath one feature of the plurality of second features and between adjacent second trenches;
conformally depositing a second spacer layer above the plurality of second features and the plurality of second trenches, wherein spacers are formed on sidewalls of each second trench;
etching through the second spacer layer to expose a respective bottom of each second trench, wherein, for each respective bottom of each second trench, a width of the respective bottom is defined by the spacers formed on the sidewalls of the second trench corresponding to the respective bottom; and
depositing a second dielectric layer above the second optical waveguide, wherein dielectric material extends to the respective bottom of each second trench.