Patent ID: 11955171
Assignee: MAVAGAIL TECHNOLOGY, LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A method of operating an integrated circuit device including the steps of:
enabling a power control circuit to provide power control signals according to at least one row address signal when an assist enable signal has an assist enable logic level and the integrated circuit device is in a write mode of operation wherein data is written to at least one selected SRAM memory cell;
selectively controlling at least one impedance path between a power supply potential and an array power line electrically connected to provide power to the at least one selected SRAM memory cell in a memory array in response to the at least one power control signal; and
enabling the power control circuit to provide power control signals having the same logic level in a read mode of operation wherein data is read from at least one selected memory cell.