Patent ID: 11862273
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. The nonvolatile memory device of claim 1, further comprising:
a memory cell region including the memory cell array and a first metal pad; and
a peripheral circuit region including a second metal pad, the peripheral circuit region vertically connected to the memory cell region through the first metal pad and the second metal pad,
wherein the peripheral circuit region includes:
a voltage generator configured to generate word-line voltages based on control signals;
the address decoder coupled to the memory cell array through the word-lines, the address decoder configured to transfer the word-line voltages to the memory cell array based on a row address;
the page buffer circuit coupled to the memory cell array through the first bit-lines and the second bit-lines, the page buffer circuit configured to store the user data and the parity data in the memory cell array; and
the control circuit further configured to control the voltage generator.