Patent ID: 11971818
Assignee: CADENCE DESIGN SYSTEMS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A non-transitory machine-readable medium having machine-readable instructions, the machine-readable instructions comprising:
a memory view generator that evaluates a Liberty file characterizing a non-volatile memory (NVM) module to generate a memory view file for the NVM module the memory view file comprising:
a port alias identifying ports of the NVM module, wherein the port alias for a set of ports of the NVM module characterizes a type of port in the set of ports;
a port action identifying ports of the NVM module have a static value during access to the NVM module;
a port access identifying ports of the NVM module that have a dynamic value during access to the NVM module;
an address limit characterizing a number of words in the NVM module;
an address partition that characterizes address bits and data bits of the NVM module; and
a read delay that defines a number of clock cycles needed to hold an address bus stable after a strobe port transitions to an inactive state to enable proper reading of data from the NVM module.