Patent ID: 11966327
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. The memory system according to claim 8, wherein
the memory controller is further configured to, when executing the read operation in the first memory area, the read operation in the second memory area, and the read operation in the third memory area in parallel,
make priority of one of the second operation in the first memory area, the second operation in the second memory area, and the second operation in the third memory area the highest among the three, based on at least one of (A) the first total time period, (B) the second total time period, and (C) the third total time period; and
make priorities of the other two of the second operation in the first memory area, the second operation in the second memory area, and the second operation in the third memory, based on a round-robin manner.