Patent ID: 11921579
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. A method of operating a memory controller, the method comprising:
transmitting a read-modify-write command to a memory device;
receiving an error information signal indicating an error detected from data read from a memory cell array of the memory device, from the memory device;
determining whether the data read from the memory cell array comprises a multi-bit error based on the error information signal, by the memory controller; and
providing the memory device with a write-back block signal to control an error correction circuit of the memory device to block the memory device from writing back an error correction data obtained by correcting the detected error to the memory cell array, based on the error information signal indicating the detected error is the multi-bit error.