Patent ID: 11895833
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 15:
16. A semiconductor memory device comprising:
a substrate including a cell region, a core region, and a boundary region between the cell region and the core region;
a boundary element isolation layer in the boundary region, the boundary element isolation layer being in a boundary element isolation recess and including first and second boundary liner layers, and a boundary element isolation filling layer;
a first gate structure on the core region and at least a part of the boundary element isolation layer; and
a second gate structure on the core region,
wherein the first gate structure does not overlap the substrate of the cell region in a direction perpendicular to the top surface of the substrate,
wherein the first boundary liner layer extends along a bottom surface of the boundary element isolation recess and sidewalls of the boundary element isolation recess,
wherein the second boundary liner layer extends on the first boundary liner layer, and comprises silicon nitride,
wherein the boundary element isolation filling layer is disposed on the second boundary liner layer,
wherein the first gate structure includes a first high dielectric layer and a first gate insulating pattern below the first high dielectric layer with a top surface of the substrate being a base reference level,
wherein the second gate structure includes a channel layer containing silicon germanium and a second gate insulating pattern on the channel layer,
wherein the first gate insulating pattern does not overlap a top surface of the first boundary liner layer, and overlaps a topmost surface of the second boundary liner layer and a top surface of the substrate of the core region in the direction perpendicular to the top surface of the substrate,
wherein a thickness of the first gate insulation pattern is smaller than a thickness of the second gate insulation pattern,
wherein a portion of the first gate insulating pattern directly contacts the top surface of the substrate of the core region, and
wherein a portion of the second gate insulating pattern directly contacts the channel layer, and the second gate insulating pattern does not contact the substrate of the core region.