Patent ID: 11971836
Assignee: SHANGHAI CAMBRICON INFORMATION TECHNOLOGY CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. The method of claim 4, wherein the plurality of secondary processing circuits are distributed in an array; each secondary processing circuit is connected to other adjacent secondary processing circuits, and the primary processing circuit is connected to k of the plurality of secondary processing circuits, wherein the K secondary processing circuits are: n secondary processing circuits in a first row, n secondary processing circuits in an mth row, and m secondary processing circuits in a first column, where
the k secondary processing circuits forwards data and instructions between the primary processing circuit and the plurality of secondary processing circuits;
the primary processing circuit determines that the input neuron is broadcast data, the weight is distribution data, partitions the distributed data into a plurality of data blocks, and sends at least one of the plurality of data blocks and at least one of the plurality of operation instructions to the k secondary processing circuits;
the k secondary processing circuits convert data between the primary processing circuit and the plurality of secondary processing circuits;
the plurality of secondary processing circuits perform an operation on the received data block according to the operation instruction to obtain an intermediate result, and transfer the operation result to the k secondary processing circuits; and
the primary processing circuit performs subsequent processing on the intermediate results sent by the k secondary processing circuits to obtain the first operation result of the computation instruction, and sends the first operation result of the computation instruction to the controller unit.