Patent ID: 11972825
Assignee: SK HYNIX INC.
Field: nan (nan)
Classification: CPC nan | IPC G  H

Claim 6:
7. An integrated circuit chip comprising:
a first data node and a second data node;
a first latch circuit and a second latch circuit configured to store data inputted through the first and second data nodes, respectively; and
a transmission circuit configured to alternately transmit data stored in the first and second latch circuits to the first data node in response to a selection signal, during a test operation, the transmission circuit comprising:
a selector having first and second data inputs, a selection signal input, and a data output, the selector configured to operatively connect one of the first and second data inputs to the data output responsive to its receipt of the selection signal; and
a read driver configured to couple a data signal output from the selector to the first data node in response to a read data strobe signal;
the integrated circuit chip additionally comprising:
a selection signal generation circuit, which is configured to provide the selection signal responsive to a test operation signal, a repair signal and a read data strobe signal.