Patent ID: 11968910
Assignee: WINBOND ELECTRONICS CORP.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 1:
2. The method of claim 1, wherein the substrate comprises a magnetic random access memory (MRAM) region and a logic region, the method comprising:
forming a first inter-metal dielectric (IMD) layer on the substrate;
forming a first metal interconnection in the first IMD layer on the MRAM region;
forming a hard mask on the first SOT layer;
forming the MTJ on the first metal interconnection;
forming a cap layer on the hard mask and the first IMD layer;
forming a second IMD layer on the cap layer;
forming a second SOT layer on the hard mask and the second IMD layer;
patterning the second SOT layer;
forming a third IMD layer on the second SOT layer; and
forming a second metal interconnection on the logic region.