Patent ID: 11869606
Assignee: MICRON TECHNOLOGY, INC.
Field: nan (nan)
Classification: CPC nan | IPC G  H

Claim 7:
8. A method of operating a NAND memory device, the method comprising:
programming a first portion of a received data item into an array of NAND memory cells organized into multiple planes and addressable by multiple page lines at a first page line of the multiple page lines and at a first plane of the multiple planes;
programming a second portion of the received data item into the array at a second page line of the multiple page lines and at a second plane of the multiple planes, the second page line being adjacent to the first page line and the second plane being adjacent to the first plane;
programming a third portion of the received data item into the array at a third page line of the multiple page lines and at a third plane of the multiple planes, the third page line being adjacent to the second page line and the third plane adjacent to the second plane;
programming a fourth portion of the received data item into the array at a fourth page line of the multiple page lines and at a fourth plane of the multiple planes, the fourth page line being adjacent to the third page line and the fourth plane adjacent to the third plane; and
wherein each data portion of the received data item is programmed on a different page line than every other data portion.