Patent ID: 11908542
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A system comprising:
a memory comprising a number M of columns, wherein each column comprises P bit cells coupled to a bit line (BL), an inverse bit line (BL #), write column selectors, and read column selectors, and a bit cell from each of the M columns is coupled to a word line; and
a memory controller coupled to the memory, wherein the memory controller is to:
determine whether a burst mode is enabled for writing data to the memory; and
perform a write operation for the bit cells coupled to the word line, wherein the write operation comprises application of a single pre-charge pulse to the bit line and inverse bit line of each of the M columns concurrent with equalization of the bit line and inverse bit line of each of the M columns, followed by application of a first pulse to the word line to write to a bit cell of a first column of the M columns, followed by equalization of the bit line and inverse bit line of a second column of the M columns, followed by application of a pulse to the word line to write to a bit cell of the second column of the M columns.