Patent ID: 11972800
Assignee: EMEMORY TECHNOLOGY INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. The non-volatile memory cell array as claimed in claim 1, wherein the first non-volatile memory cell comprises:
a semiconductor substrate, wherein a N-well region and a P-well region are formed in a surface of the semiconductor substrate;
a first gate structure formed over the N-well region, wherein the first gate structure is connected with the first program word line;
a second gate structure formed over the N-well region;
a first p-type doped region formed in the N-well region, wherein the first p-type doped region is located beside a first side of the first gate structure, and the first p-type doped region is connected with the program source line;
a second p-type doped region formed in the N-well region, wherein the second p-type doped region is arranged between a second side of the first gate structure and a first side of the second gate structure;
a third p-type doped region formed in the N-well region, wherein the third p-type doped region is located beside a second side of the second gate structure, and the third p-type doped region is connected with the first program bit line;
a fourth p-type doped region formed in the N-well region, wherein the fourth p-type doped region is located beside the first side of the second gate structure, the fourth p-type doped region is connected with the read source line, and the fourth p-type doped region is not contacted with the second p-type doped region;
a fifth p-type doped region formed in the N-well region, wherein the fifth p-type doped region is located beside the second side of the second gate structure, and the fifth p-type doped region is not contacted with the third p-type doped region;
a third gate structure formed over the P-well region, wherein the third gate structure is connected with the first read word line;
a first n-type doped region formed in the P-well region, wherein the first n-type doped region is located beside a first side of the third gate structure;
a second n-type doped region formed in the P-well region, wherein the second n-type doped region is located beside a second side of the third gate structure, and the second n-type doped region is connected with the first read bit line; and
a metal layer, wherein the fifth p-type doped region and the first n-type doped region are connected with each other through the metal layer,
wherein the first gate structure, the first p-type doped region and the second p-type doped region are collaboratively formed as the first select transistor,
wherein the second gate structure, the second p-type doped region and the third p-type doped region are collaboratively formed as the first floating gate transistor,
wherein the second gate structure, the fourth p-type doped region and the fifth p-type doped region are collaboratively formed as the second floating gate transistor,
wherein the third gate structure, the first n-type doped region and the second n-type doped region are collaboratively formed as the second select transistor.