Patent ID: 11901911
Assignee: MICRON TECHNOLOGY, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 0:
1. A method comprising:
receiving a codeword from a memory device, the codeword including a plurality of bits;
flipping one or more of the plurality of bits in the codeword in each of a plurality of error correction iterations, wherein each bit is flipped using a first bit flipping criterion that includes comparing a first bit flipping threshold and an energy function of each bit;
determining a count of parity violations in the codeword after flipping the one or more of the plurality of bits;
determining the count of parity violations satisfies a parity violation count threshold;
determining a count of the plurality of iterations exceeds an iteration count threshold; and
responsive to the determining the iteration count threshold exceeds the iteration count threshold and the parity violation count threshold is satisfied, flipping one or more of the plurality of bits in the codeword using a second bit flipping criterion for one or more error correction iterations, wherein the second bit flipping criterion differs from the first bit flipping criterion.