Patent ID: 11967394
Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. The memory system of claim 1, wherein the memory array further comprises:
a third metal layer;
a fourth metal layer different from the third metal layer, the fourth metal layer comprising a plurality of second flying bit lines each coupled to the memory column access circuit;
a third memory sub-bank, comprising:
a plurality of third memory row circuits each comprising a plurality of third memory bit cell circuits each located in a respective third memory column circuit of a plurality of third memory column circuits; and
a plurality of third bit lines disposed in the third metal layer and each coupled to a third memory column circuit of the plurality of third memory column circuits, and the memory column access circuit;

a fourth memory sub-bank, comprising:
a plurality of fourth memory row circuits each comprising a plurality of fourth memory bit cell circuits each located in a respective fourth memory column circuit of a plurality of fourth memory column circuits; and
a plurality of fourth bit lines each disposed in the fourth metal layer and each coupled to a fourth memory column circuit of the plurality of fourth memory column circuits; and

a third memory row circuit of the plurality of third memory row circuits, comprising:
a plurality of second jumper cell circuits each coupled to a fourth bit line of the plurality of fourth bit lines in a fourth memory column circuit of the plurality of fourth memory column circuits in the third metal layer, and a first flying bit line of the plurality of first flying bit lines in the fourth metal layer.