Patent ID: 11894326
Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A method of fabricating a microelectronic component comprising:
forming a recess or opening in a surface of a substrate;
disposing a first conductive material having a first coefficient of theuiial expansion (CTE) within the recess or opening, the first conductive material at least partially filling the recess or opening and forming a first portion of an interconnect structure of the microelectronic component;
disposing a second conductive material having a second CTE different from the first CTE within the recess or opening and forming a second portion of the interconnect structure of the microelectronic component; and
planarizing the surface of the substrate, the first conductive material, and the second. conductive material and forming a planar bonding surface comprising the first portion and the second portion of the interconnect stricture and a planar dielectric surface.