Patent ID: 11929762
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A low density parity check (LDPC) decoder initializing variable nodes with a value of a codeword and outputting the variable nodes updated with reference to an irregular parity check matrix as decoded messages, comprising:
a plurality of unit logic circuits operating in a single mode in which all the unit logic circuits update one variable node group including at least one variable node, or a multi-mode in which each of the unit logic circuits updates a plurality of variable node groups in parallel by updating different variable nodes; and
a mode controller controlling the plurality of unit logic circuits to update a high-degree variable node group having a degree greater than a threshold degree among the variable node groups in the single mode, and update a low-degree variable node group having a degree less than or equal to the threshold degree among the variable node groups in the multi-mode.