Patent ID: 11868694
Assignee: SYNOPSYS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A system, comprising:
a host system comprising:
a memory; and
a processor configured to perform operations stored in the memory, wherein the processor executes the operations to:
analyze each of a first set of sequential elements of a plurality of sequential elements to determine an edge of a clock signal pattern of a clock associated with each of the first set of sequential elements causing an output change at corresponding one or more sequential elements of the first set of sequential elements;
discard one or more cycles of the clock signal pattern of the clock from emulation that do not include the edge of the clock signal pattern that causes at least one sequential element of the first set of sequential elements to change an output; and
replicate a clock tree to generate a replicated clock tree, wherein the clock tree and the replicated clock tree are fed adjacent cycles of the clock signal pattern of the clock.