Patent ID: 11908932
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 24:
25. A system, comprising:
at least one input device;
at least one output device;
at least one processor device operably coupled to the at least one input device and the at least one output device; and
an apparatus operably coupled to the at least one processor device, the apparatus comprising:
an array of memory cells comprising vertical transistors, one or more of the vertical transistors comprising:
a channel region comprising:
an upper region exhibiting a first width; and
a lower region extending downward from the upper region and exhibiting a second width, wherein the second width is smaller than the first width,
wherein an interface between the upper region and the lower region defines at least one overhang portion;

at least one gate electrode at least partially disposed vertically beneath the at least one overhang portion of the upper region of the channel region;
a gate dielectric material between the at least one gate electrode and the at least one overhang portion of the upper region and between the at least one gate electrode and the lower region of the channel region, wherein a portion of the at least one gate electrode proximal to the at least one overhang portion of the upper region is free of gate dielectric material; and
an insulative structure vertically separating the gate dielectric material from a conductive contact underlying the at least one gate electrode, outermost lateral boundaries of the gate dielectric material and the insulative structure substantially vertically aligned with one another.