Patent ID: 11916115
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. An integrated chip, comprising:
a gate structure overlying a substrate between a source region and a drain region;
a dielectric layer overlying the substrate;
a plurality of conductive vias disposed within the dielectric layer and overlying the substrate;
a plurality of conductive wires overlying the plurality of conductive vias;
a field plate disposed within the dielectric layer and spaced laterally between the gate structure and the drain region; and
wherein a first conductive wire in the plurality of conductive wires has a bottom segment that extends below a top surface of the field plate along outer sidewalls of the field plate and laterally surrounds the outer sidewalls of the field plate.