Patent ID: 11953973
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. The memory device of claim 10, wherein the read recovery operation is a first read recovery operation and the position is a primary position;
wherein the one or more components are configured to set the flag to the enabled state and reset the success counter based on the value of the success counter indicating that the first read recovery operation has succeeded a threshold quantity of times;
wherein the one or more components, to generate the second sequence, are configured to set the first read recovery operation to the ordinal first position in the second sequence based on the flag being set to the enabled state; and
wherein the one or more components are further configured to:
identify a second read recovery operation, of the set of read recovery operations, that results in successful recovery from a third read failure associated with the page type or the memory section;
increment the success counter based on the second read recovery operation resulting in successful recovery from the third read failure; and
generate a third sequence of read recovery operations that prioritizes the first read recovery operation and the second read recovery operation as compared to the first sequence.