Patent ID: 11942168
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 10:
11. A method of manufacturing an integrated circuit (IC) structure, the method comprising:
constructing a first plurality of fin structures extending in a first direction in a first active area and a second plurality of fin structures extending in the first direction in a second active area;
constructing a first plurality of gate structures extending over the first active area in a second direction perpendicular to the first direction, and a second plurality of gate structures extending over the second active area in the second direction;
forming an electrical fuse (eFuse) conductive segment extending in the first direction between the first and second active areas;
forming electrical connections from the eFuse conductive segment to each of the first and second pluralities of fin structures;
forming first and second signal lines extending in the first direction adjacent to the respective first and second active areas; and
forming electrical connections from the first signal line to the first plurality of gate structures and from the second signal line to the second plurality of gate structures.