Patent ID: 11923861
Assignee: QUALCOMM INCORPORATED
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. The apparatus of claim 11, further comprising:
a phase-frequency detector configured to generate a phase error signal based on a phase difference between a reference clock signal and a feedback clock signal;
a first charge pump configured to generate a first control signal based on the phase error signal;
a data sampler configured to sample an input data signal based on a VCO clock signal generated by the VCO to generate a sampled data signal;
a phase detector configured to generate a data phase alignment signal based on the sampled data signal;
a second charge pump configured to generate a second control signal based on the data phase alignment signal;
a loop filter configured to filter the first and second control signals to generate a PLL frequency control signal that controls the at least one first VCO frequency control circuit and the at least one second VCO frequency control circuit such that the VCO generates a VCO clock signal whose frequency is based on the PLL frequency control signal; and
a frequency divider configured to generate the feedback clock signal based on the VCO clock signal.