Patent ID: 11888038
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. An integrated circuit device comprising:
a substrate including an active area;
a bit line extending on the substrate in a first direction parallel to a top surface of the substrate and including a lower conductive pattern and an upper conductive pattern;
a direct contact disposed between the active area of the substrate and the bit line;
an electrically insulating spacer structure disposed on both sidewalls of the bit line to cover both sidewalls of the direct contact; and
a semi-insulating field passivation layer, which extends between both sidewalls of the direct contact and the spacer structure and forms a hetero-interface with the direct contact, said hetero-interface including a quantum well within the field passivation layer; and
wherein the quantum well within the field passivation layer is configured to induce an electron inversion layer within the direct contact, which increases the conductivity of the direct contact.