Patent ID: 11894074
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 1:
2. The device of claim 1, further comprising:
a plurality of bit lines coupled to the memory cell transistors, respectively,
wherein
in the verify operation, for each state of a write target, the controller is configured to:
set a memory cell transistor determined to have a threshold voltage equal to or lower than the verify low voltage, as a first program target;
set a memory cell transistor determined to have a threshold voltage exceeding the verify low voltage and being equal to or lower than the verify high voltage, as a second program target; and
set a memory cell transistor determined to have a threshold voltage exceeding the verify high voltage as program-inhibit, and
while a program voltage is being applied to the word line in the program operation, the controller is configured to:
apply a first voltage to a bit line coupled to the memory cell transistor of the first program target,
apply a second voltage higher than the first voltage to a bit line coupled to the memory cell transistor set as the second program target; and
apply a third voltage higher than the second voltage to a memory cell transistor set as program-inhibit.