Patent ID: 11876067
Assignee: NANYA TECHNOLOGY CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor package, comprising:
a package substrate comprising a first connection pad and a second connection pad;
a first semiconductor chip disposed over the package substrate, the first semiconductor chip comprising a first chip pad, a first bonding pad, and a first redistribution layer, wherein the first bonding pad is closer to a periphery of the first semiconductor chip than the first chip pad, and the first redistribution layer is connected between the first chip pad and the first bonding pad, wherein the first chip pad is a power pad or a ground pad through which power is supplied to the first semiconductor chip; and
a plurality of first bonding wires connected in parallel between the first connection pad and the first bonding pad;
wherein the first semiconductor chip further comprises a second chip pad electrically connected to the package substrate through a second bonding wire, and the second chip pad is a data signal pad or a command/address signal pad, wherein the first semiconductor chip further comprises a second bonding pad and a second redistribution layer, the second redistribution layer is connected between the second chip pad and the second bonding pad, wherein the second bonding wire is connected between the second connection pad and the second bonding pad, and the second bonding wire is the only conductive path between the second connection pad and the second bonding pad.