Patent ID: 11907004
Assignee: ETOPUS TECHNOLOGY INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 2:
3. The transmitter device of claim 1, wherein the plurality of registers included in each of the plurality of retimers includes:
a first set of registers, each register from the first set configured to receive a different portion of the input data and output a corresponding portion of the retimed input data according to the clock signal; and
a second set of registers including a plurality of pairs of second registers, a first register included in each pair of second registers configured to receive a different portion of the input data and output a corresponding portion of the retimed input data to a second register that is serially connected to the first register included in the pair, the second register in each pair delaying an output of the respective portion of the retimed input data according to the clock signal.