Patent ID: 11869596
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 7:
8. The memory device of claim 4, wherein
the plurality of first loops of the first programming operation includes a second loop and a third loop, the third loop being subsequent to the second loop,
the plurality of fourth loops of the second programming operation includes a fifth loop and a sixth loop, the sixth loop being subsequent to the fifth loop, and
the peripheral circuit is further configured to:
in the third loop of the first programming operation, apply, to the first memory cell, the first program voltage whose level is higher, by a first difference voltage, than a level of the first program voltage applied to the first memory cell in the second loop of the first programming operation;
receive the value of the second write parameter that includes a value of a second difference voltage that is larger than a value of the first difference voltage; and
in the sixth loop of the second programming operation, apply, to the second memory cell, the second program voltage whose level is higher, by the second difference voltage, than a level of the second program voltage applied to the second memory cell in the fifth loop of the second programming operation.