Patent ID: 11942155
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H  B | IPC G  H

Claim 18:
19. A memory device, comprising:
a memory cell that randomly presents either a first or second logic state, the memory cell comprising:
a plurality of first nanostructures and a plurality of second nanostructures each extending along a first lateral direction;
a dielectric fin structure disposed between the plurality of first and sedond nanostructures, wherein a first sidewall of each of the plurality of first nanostructures faces toward or away from a second lateral direction that is perpendicular to the first lateral direction and a second sidewall of each of the plurality of second nanostructures also faces toward or away from the second lateral direction;
a first gate structure wrapping around each of the plurality of first nanostructures except for the first sidewall; and
a second gate structure wrapping around each of the plurality of second nanostructures except for the second sidewall.