Patent ID: 11961798
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor structure, comprising at least two electrode layers, the at least two electrode layers being parallel to each other and arranged in different layers,
adjacent electrode layers of the at least two electrode layers overlap with each other and have an overlapping area, a dielectric layer is arranged between the adjacent electrode layers, and an air gap is arranged in the dielectric layer located in the overlapping area,
wherein the dielectric layer comprises at least two annular side walls and a filling layer covering the at least two annular side walls, and the air gap is arranged in a part in the filling layer located in each of the at least two annular side walls and a part located between adjacent annular side walls of the at least two annular side walls.