Patent ID: 11940492
Assignee: STMICROELECTRONICS S.R.L.
Field: Measurement (Instruments)
Classification: CPC G | IPC G

Claim 1:
2. The circuit of claim 1, wherein the control registers in the set of control registers are configured to receive test programming information from the test programming interface comprising:
a number of test sessions for which a test stimulus generator in the set of test stimulus generators is activated to produce the test stimulus signals for the at least one circuit under test,
a number of test cycles for which a test stimulus generator in the set of test stimulus generators is activated in a test session for the at least one circuit under test,
timed test mode activation information to activate a test stimulus generator in the set of test stimulus generators at programmed times, or
capture mode information indicative of a number of capture cycles of output test signals for the at least one circuit under test.