Patent ID: 11935885
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A device, comprising:
an integrated circuit comprising a standard cell, wherein the standard cell is selected for design of a layout of the integrated circuit, the standard cell comprising:
a first active region comprising a first source/drain region, a second source/drain region, a third source/drain region;
a second active region separate from the first active region comprising a fourth source/drain region, a fifth source/drain region, and a sixth source/drain region;
a first gate finger arranged between the first source/drain region and the second source/drain region;
a second gate finger arranged between the second source/drain region and the third source/drain region;
a third gate finger arranged between the fourth source/drain region and the fifth source/drain region; and
a fourth gate finger arranged between the fifth source/drain region and the sixth source/drain region,
wherein the first gate finger is configured to form a first transistor of an electrostatic discharge (ESD) protection circuit, the third gate finger is configured to form a second transistor of the ESD protection circuit, and the second transistor is connected to the first transistor in series.