Patent ID: 11881858
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 14:
15. The method for calibrating the clock duty cycle of claim 14, wherein the logical unit comprises a counter, a first register group and a second register group, and controlling, by the logical unit, the oscillation circuit according to the output result of the comparison unit comprises:
when the turnover identification signal is at the low level, counting, by the counter, from M to N, when a value of the counter is M, the duty cycle of the first oscillation signal is P %, when the value of the counter is N, the duty cycle of the first oscillation signal is Q %, and when the output result of the comparison unit changes from low level to high level, a counter value corresponding to the counter at this time is stored in the first register group; and
when the turnover identification signal is at the high level, counting from M to N, when the value of the counter is M, the duty cycle of the second oscillation signal is Q %, when the value of the counter is N, the duty cycle of the second oscillation signal is P %, and when the output result of the comparison unit changes from the high level to the low level, the counter value corresponding to the counter at this time is stored in the second register group;
wherein both M and N are integers, M is less than N, both P and Q are positive integers, P is less than 50, and Q is greater than 50.