Patent ID: 11962299
Assignee: HANGZHOU GEO-CHIP TECHNOLOGY CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  Y | IPC H

Claim 6:
7. A method of configuring a phase delay in a fractional frequency divider, applicable to the fractional frequency divider according to claim 1, the method comprising that:
a ratio of a clock period of a clock signal output by a delay module of the fractional frequency divider to a clock period of clock signals received by signal input terminals of a multiplexer of the frequency divider is (1+1/N), wherein N refers to the number of the signal input terminals, and a clock signal received by a selected signal input terminal comprises a low level section, a high level section and a low level section that are sequentially continuous;
any one rising edge is located in an intermediate time region between a first moment and a second moment;
the first moment is a waveform rising edge moment of last selected signal input terminal for a signal input terminal selected within a clock period of the second clock signal that follows said any one rising edge of the second clock signal, the waveform rising edge moment coming after said any one rising edge; and
the second moment is a waveform falling edge moment of a first signal input terminal within a first clock period of the second clock signal, the waveform falling edge moment preceding a first rising edge.