Patent ID: 11955511
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A semiconductor structure, comprising:
a substrate, wherein the substrate comprises an array area and a peripheral area adjacent to each other, and the array area comprises a buffer area connected to the peripheral area;
a first supporting layer and a second supporting layer, wherein the first supporting layer is arranged in the peripheral area, the second supporting layer is arranged in the array area, and the second supporting layer is higher than the first supporting layer; and
a groove-type lower electrode, wherein the groove-type lower electrode is arranged in the buffer area and penetrates through the second supporting layer, a bottom surface of the groove-type lower electrode is higher than a surface of the substrate and lower than the first supporting layer, or a bottom surface of the groove-type lower electrode is higher than the first supporting layer and lower than the second supporting layer.