Patent ID: 11961763
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 9:
10. A device, comprising:
a first channel layer disposed between first source/drain features over a substrate;
a first metal gate that surrounds the first channel layer;
a second channel layer disposed between second source/drain features over the substrate;
a second metal gate that surrounds the second channel layer;
a dielectric fin disposed between and separating the first metal gate and the second metal gate;
a first portion of a conductive layer over the first metal gate;
a second portion of the conductive layer over the second metal gate; and
an isolation layer between the first portion and second portion of the conductive layer and over the dielectric fin, wherein the first portion of the conductive includes a rounded terminal end abutting the isolation layer and disposed vertically over the first metal gate.