Patent ID: 11948634
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 3:
4. A memory device comprising:
a memory array comprising a plurality of memory elements;
a first circuit that when in operation selectively generates a first voltage to select a target memory cell as a first memory element of the plurality of memory elements when a location of the target memory cell is near in proximity to a row decoder of the memory device; and
a second circuit that when in operation selectively generates a second voltage to select the target memory cell as the first memory element of the plurality of memory elements when the location of the target memory cell is far in proximity to the row decoder of the memory device, wherein the second circuit when in operation receives a first trim signal as a control signal to generate the second voltage at a first time, wherein the second circuit comprises a first current mirror, wherein the first circuit when in operation receives a second trim signal as a second control signal to generate a third voltage at a second time subsequent to the target memory cell being selected, wherein the first circuit comprises a second current mirror.