Patent ID: 11966309
Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. An apparatus, comprising:
a testing card with a plurality of test ports;
a computing device with a plurality of PCIe slots,
wherein the plurality of test ports of the testing card are coupled to the plurality of PCIe slots of the computing device;
wherein the computing device is to generate a script for each test port of the plurality of test ports,
wherein the script indicates a series of read operations and write operations to be performed by the testing card on a non-volatile memory associated with the computing device;
wherein a respective test port, in parallel with a remainder of the test ports, is to run the script by executing the series of read operations and write operations indicated by the script,
thereby allowing saturation of a bandwidth and verification of link health of the plurality of PCIe slots of the computing device by the plurality of test ports of the testing card; and
wherein the computing device is associated with a display screen via which a user is to modify the script by adjusting parameters including at least one of a maximum payload size, a maximum read request size, and memory addresses associated with the read and write operations.