Patent ID: 11892906
Assignee: INFINEON TECHNOLOGIES AG
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. A processor for storing and reading data bits having at least one byte-filling bit in memory cells of a memory, the processor configured to:
code, in the at least one-byte-filling bit, at least one predefined functionality for a subset of the data bits;
store the data bits in the memory cells; and
read the data bits from the memory cells based on the at least one predefined functionality coded in the at least one byte-filling bit,
wherein the data bits are grouped, together with check bits, into bytes, wherein at least one of these bytes can be corrected based on a byte error code, wherein the data bits and the check bits are stored in the memory cells,
wherein, in an error-free case, the data bits and the check bits represent a code word of the byte error code or are parts of a code word of the byte error code,
wherein the byte error code has N check bytes having check bits,
wherein a byte comprises m bits,
wherein there is a byte which has K byte-filling bits and m−K data bits,
wherein m is determined as a smallest positive integer so that

m·(2m−1)≥n+(N·m)+K 

where m≤3, 1≤K≤m−1, N≥2 and n>(N+2)·m, and
where n is a number of data bits.