Patent ID: 11894375
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B  Y | IPC H

Claim 15:
16. A method of manufacturing a semiconductor device, comprising:
forming a first semiconductor stack, a first dielectric layer and a second semiconductor stack from bottom to top, wherein the first and second semiconductor stacks extend in a first direction;
forming a dummy gate over the second semiconductor stack and extending in a second direction perpendicular to the first direction;
growing a first epitaxial region on a first side of the dummy gate;
depositing a first insulation layer laterally surrounding the dummy gate and the first epitaxial region;
forming a second dielectric layer over the first insulation layer;
pattering the second dielectric layer to form a first conductive via over the first epitaxial region;
depositing a third dielectric layer over the second dielectric layer;
growing a second epitaxial region over the third dielectric layer on a second side of the dummy gate;
depositing a second insulation layer over the third dielectric layer and laterally surrounding the dummy gate and the second epitaxial region;
patterning the second insulation layer to expose the third dielectric layer;
patterning the third dielectric layer to form a first conductive line over the second dielectric layer, the first conductive line extending in the first direction and electrically connected to the first conductive via; and
patterning the third dielectric layer to form a second conductive via electrically connected to the first conductive line.