Patent ID: 11954366
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. An apparatus comprising:
means for reading data from a plurality of memory dies using one or more multi-commands;
means for performing asynchronous independent plane reads (AIPR) on the plurality of memory dies;
means for communicating the data that is read to a flash interface module (FIM) with a bus and channel transfers on the bus,
wherein the channel transfers include a plurality of data transfers of the data that is read and a plurality of overheads associated with performing the AIPR on the plurality of memory dies, and
wherein a number of the plurality of overheads is less than a number of the plurality of data transfers;
controlling issuance of a plurality of commands to the plurality of memory dies; and
maintaining a time window to issue new commands on a different plane,
wherein controlling the issuance of the plurality of commands to the plurality of memory dies further includes:
determining whether a saturation level of the FIM is one of undersaturated, saturated, or oversaturated, and
controlling the issuance of the plurality of commands to the plurality of memory dies based on the determination of whether the saturation level of the FIM is the one of the undersaturated, the saturated, or the oversaturated.