Patent ID: 11935875
Assignee: INFINEON TECHNOLOGIES AG
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A power semiconductor module arrangement comprising:
a power electronics substrate comprising a dielectric layer, and a first metallization layer disposed on an upper surface of the dielectric layer, the first metallization layer being structured to comprise a first DC voltage pad, a second DC voltage pad, a first load pad, and a second load pad;
first and second transistor dies mounted on the first load pad;
third and fourth transistor dies mounted on the first DC voltage pad,
wherein the first and second transistor dies collectively form a first switch that is connected between the second DC voltage pad and the first load pad,
wherein the third and fourth transistor dies collectively form a second switch that is connected between the first DC voltage pad and the second load pad,
wherein the first and second DC voltage pads are arranged such that a DC supply impedance for a first commutation loop that flows through the first and third transistor dies matches a DC supply impedance for a second commutation loop that flows through the second and fourth transistor dies,
wherein the third transistor die is connected to the second load pad by a first load connection,
wherein the fourth transistor die is connected to the second load pad by a second load connection, and
wherein an impedance of the first load connection is greater than an impedance of the second load connection.