Patent ID: 11955167
Assignee: NORTHWESTERN UNIVERSITY
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 6:
7. A convolutional neural network (CNN) accelerator, comprising:
an application-specific integrated circuit (ASIC);
a global weight static random access memory in communication with the application-specific integrated circuit;
an activation static random access memory in communication with the application-specific integrated circuit; and
at least one computing-in-memory (CIM) macro in communication with the application-specific integrated circuit,
wherein the at least one computing-in-memory macro comprises a dynamic-analog-RAM array comprising at least one three-transistors (3T) memory cell,
wherein the three-transistors (3T) memory cell comprises a read-access transistor M1 in electrical communication with a read bitline, a switch transistor M2 in electrical communication with the read-access transistor M1, a write-access transistor M3 in electrical communication with the read-access transistor M1 and a write bitline, and a memory node in electrical communication between the read-access transistor M1 and the write-access transistor M3, wherein the memory node is configured to store a 4-bit weight,
wherein the application-specific integrated circuit comprises an analog weight shifting mode wherein the weights are shifted down whenever a weight range in a column of the dynamic-analog-RAM (DARAM) array is not utilized.