Patent ID: 11875838
Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 2:
3. The memory device according to claim 2,
wherein the reading circuit comprises a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and a first circuit,
wherein the ninth transistor and the tenth transistor are n-channel transistors,
wherein the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are p-channel transistors,
wherein a second terminal of the first transistor is electrically connected to a first terminal of the third transistor, a first terminal of the fifth transistor, a gate of the fifth transistor, and a gate of the seventh transistor,
wherein a first terminal of the seventh transistor is electrically connected to a first terminal of the ninth transistor and an input terminal of the first circuit,
wherein a second terminal of the second transistor is electrically connected to a first terminal of the fourth transistor, a first terminal of the sixth transistor, a gate of the sixth transistor, and a gate of the eighth transistor,
wherein a first terminal of the eighth transistor is electrically connected to a first terminal of the tenth transistor, a gate of the tenth transistor, and a gate of the ninth transistor,
wherein the first circuit is configured to output a reading potential of the first data from an output terminal of the first circuit in accordance with a first potential of the input terminal of the first circuit, and
wherein the first potential is a potential based on the first current and the second current.