Patent ID: 11908831
Assignee: STMICROELECTRONICS PTE LTD
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A process, comprising:
producing a front end of line (FEOL) substrate wafer which includes a semiconductor substrate wafer having a first thickness and a back surface and a premetallization dielectric layer;
producing back end of line (BEOL) structures over the premetallization dielectric layer, said BEOL structures including a first passivation layer including openings for bonding pads;
forming a redistribution layer over said first passivation layer, where the redistribution layer electrically connects the bonding pads to underbump metallization pads;
forming a second passivation layer including openings for the underbump metallization pads, and thus produce a production wafer;
opening trenches from a top surface of the production wafer that extend down to a depth that is only partially through the semiconductor substrate wafer;
prior to performing a bumping process at said underbump metallization pads, attaching a first handle to the top surface of the production wafer;
thinning at the back surface of the semiconductor substrate wafer of the production wafer from a first thickness to a second thickness that reaches the trenches and forms a plurality of wafer level chip scale packages;
attaching a second handle to bottom surfaces of said plurality of wafer level chip scale packages;
removing said first handle to expose the underbump metallization pads; and
performing said bumping process to form a solder ball at each of the exposed underbump metallization pads.