Patent ID: 11907005
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G  H

Claim 15:
16. A multi-core system comprising:
a multi-core processor including a first processor core configured to operate based on a first core clock signal and a second processor core configured to operate based on a second core clock signal;
a function block configured to communicate with the multi-core processor based on an interface clock signal; and
a clock management circuit configured to:
generate the first core clock signal by selecting one of a first clock signal having a first frequency and a second clock signal having a second frequency different from the first frequency based on a first frequency selection signal,
generate the second core clock signal by selecting one of the first clock signal and the second clock signal based on a second frequency selection signal,
generate the interface clock signal based on the second clock signal, and
when at least one of a frequency of the first core clock signal and a frequency of the second core clock signal is changed, simultaneously deactivate the first core clock signal, the second core clock signal and the interface clock signal in a clock gating period.