Patent ID: 11875856
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 9:
10. A method of controlling a semiconductor memory device including a first memory cell, a second memory cell, a first word line, a second word line, a semiconductor layer and a first bit line, the first word line being coupled to the first memory cell, the second word line being coupled to the second memory cell, the semiconductor layer being interposed between the first memory cell and the second memory cell, the first bit line being capable of being electrically coupled to both the first memory cell and the second memory cell, the method comprising:
executing, in response to a write command for the first memory cell, a first operation, a second operation after executing the first operation, and a third operation after executing the second operation, the first operation including applying a first voltage to a word line corresponding to a non-selected memory cell, the second operation including applying a second voltage higher than the first voltage to the word line corresponding to the non-selected memory cell, and the third operation including applying a third voltage higher than the second voltage to the word line corresponding to the non-selected memory cell and applying a fourth voltage lower than both the third voltage and the second voltage to a word line corresponding to a selected memory cell; and
executing, in response to a write command for the second memory cell, the third operation,
wherein
data writing into the second memory cell is executed after data writing into the first memory cell is executed.