Patent ID: 11869773
Assignee: MITSUBISHI ELECTRIC CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of manufacturing a semiconductor device, comprising the steps of:
discretely forming a plurality of gate structures on a first main surface of the semiconductor substrate;
discretely forming a plurality of gate interlayer films covering the plurality of gate structures of the semiconductor substrate;
forming a first surface electrode being thinner than the gate interlayer films on the first main surface of the semiconductor substrate between the plurality of the gate interlayer films and on the plurality of the gate interlayer films; and
forming a second surface electrode directly on an upper surface of the first surface electrode by plating treatment, wherein
the following is satisfied:

(a−b)≤e, 

where a is a distance from an upper surface of the second surface electrode above the gate interlayer film to the first main surface, b is a distance from the upper surface above a portion of the first main surface between adjacent gate interlayer films to the first main surface, and e is the thickness of the gate interlayer film.