Patent ID: 11936538
Assignee: ROHDE & SCHWARZ GMBH & CO. KG
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A phase-shifted sampling circuit, comprising:
a primary sampler circuit including an analog signal input, a first signal path, and a second signal path, wherein the first signal path comprises a first analog sampling unit configured to sample an analog input signal received by the analog signal input, thereby generating a first pre-sampled analog input signal, and wherein the second signal path comprises a second analog sampling unit configured to sample the analog input signal in a phase-shifted manner compared to the first analog sampling unit, thereby generating a second pre-sampled analog input signal, wherein the first pre-sampled analog input signal and the second pre-sampled analog input signal each have a lower bandwidth than the analog input signal;
an analog-to-digital converter (ADC) circuit including a first analog-to-digital converter associated with the first signal path, wherein the first analog-to-digital converter is configured to sample the first pre-sampled analog input signal, thereby generating a first digital output signal, and including a second analog-to-digital converter associated with the second signal path, wherein the second analog-to-digital converter is configured to sample the second pre-sampled analog input signal in a phase-shifted manner compared to the first analog-to-digital converter, thereby generating a second digital output signal; and
an equalization circuit including a primary sampler equalizer sub-circuit, wherein the primary sampler equalizer sub-circuit is configured to compensate a mismatch between a transfer function associated with the first signal path and a transfer function associated with the second signal path based on the digital output signals, wherein the primary sampler equalizer sub-circuit is configured to compensate transfer function mismatches originating within the primary sampler circuit, and wherein filter coefficients of the primary sampler equalizer circuit are chosen such that deviations of sampling times of the first analog sampling unit and of the second analog sampling unit from respective ideal sampling times are compensated.