Patent ID: 11860775
Assignee: SILICON MOTION, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. The apparatus of claim 11, wherein the routing engine comprises:
a first static random access memory (SRAM), arranged operably to: allocate space for a status queue and an activation queue, wherein the status queue is used for the first processing unit to store the operation settings and the front-end parameter set of the first data-programming transaction; and
a first controller, coupled to the first SRAM, arranged operably to: pop the operation settings and the front-end parameter set of the first data-programming transaction out of the status queue; determine whether the front-end processing stage needs to be activated for the first data-programming transaction according to the operation settings; drive the host I/F to obtain the first data from the host side and store the first data in the first designated address of the RAM through the shared bus architecture according to the front-end parameter set when determining that the front-end processing stage needs to be activated for the first data-programming transaction; and store the activation message for the first data-programming transaction in the activation queue when the front-end process stage, or a portion of the front-end process stage for the first data-programming transaction has been completed.