Patent ID: 11929419
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A device, comprising:
a semiconductive fin having source and drain regions and a channel region between the source and drain regions;
an isolation dielectric layer surrounding a bottom of the semiconductive fin;
a gate feature over the channel region of the semiconductive fin;
a first spacer around the gate feature;
source and drain features respectively in the source and drain regions of the semiconductive fin;
a gate oxide layer extending from one of the source and drain features, through beneath the gate feature, to another one of the source and drain features;
an interlayer dielectric layer around the first spacer; and
a void between the first spacer and the interlayer dielectric layer and spaced apart from the gate feature and the source and drain features, wherein the void is directly above the gate oxide layer and has:
a first air gap portion directly above the semiconductive fin;
a second air gap portion directly above the isolation dielectric layer, wherein the first air gap portion and the second air gap portion have different heights; and
a contact etch stop layer between the first spacer and the interlayer dielectric layer, wherein a top surface of the contact etch stop layer is lower than a top surface of the interlayer dielectric layer.