Patent ID: 11916561
Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A method comprising:
generating, via a first clock generator, two or more first-level clock signals of a track and hold circuit based on an input clock signal, each of the two or more first-level clock signals separated by a phase offset of 1xT from a respective first-level clock signal of a neighboring phase;
generating, via a phase interpolator, an interpolated clock signal, wherein
generating the interpolated clock signal further comprises:
selecting an even-numbered first-level clock signal of the two or more clock signals;
selecting an odd-numbered first-level clock signal of the two or more clock signals, the odd-numbered first-level clock signal having a phase neighboring a phase of the even-numbered first-level clock signal;
generating the interpolated clock signal based on the even-numbered first-level clock signal and the odd-numbered first-level clock signal, wherein the interpolated clock signal has a phase within the 1xT phase offset between the even-numbered and odd-numbered first-level clock signals; and

generating, via a second clock generator, two or more second-level clock signals based on the interpolated clock signal, wherein the phase of the two or more second-level clock signals relative to the phase of a respective first-level clock signal is determined, at least in part, by the phase of the interpolated clock signal.