Patent ID: 11881283
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 0:
1. A semiconductor memory device comprising:
first and second memory cell arrays spaced apart from each other in a first direction;
a plurality of column selection transistors spaced apart from each other in a second direction which intersects the first direction, wherein the plurality of column selection transistors are between the first and second memory cell arrays, and wherein at least two of the column selection transistors comprise respective portions of a central gate pattern that intersects a central line extending in the first direction at a center of the first memory cell array and has a closed loop shape; and
first and second local input/output lines configured to provide electric potential through the first memory cell array to a local sense amplifier based on operations of the column selection transistors,
wherein the first and second local input/output lines extend in the second direction and are electrically connected to the central gate pattern, and
wherein the center line is spaced apart from, and does not intersect the first and second local input/output lines in a plan view.