Patent ID: 11862232
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 2:
3. The circuit for data transmission of claim 2, wherein the first class mode register read-write module comprises a first mode register read-write module, a second mode register read-write module, a third mode register read-write module, and a fourth mode register read-write module; the first logic gate unit comprises a first OR gate and a second OR gate; the second logic gate unit comprises a third OR gate and a fourth OR gate;
the first OR gate is configured such that: a first input end is electrically connected to the first mode register read-write module, and a second input end is electrically connected to the second mode register read-write module;
the second OR gate is configured such that: a first input end is electrically connected to the third mode register read-write module, and a second input end is electrically connected to the fourth mode register read-write module;
the third OR gate is configured such that: a first input end is electrically connected to an output end of the first OR gate, and a second input end is electrically connected to an output end of the second OR gate; and
the fourth OR gate is configured such that: a first input end is electrically connected to an output end of the third OR gate, and a second input end is electrically connected to the second class mode register read-write module.