Patent ID: 11928403
Assignee: FUJITSU LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A method of performing simulated annealing in an optimization apparatus which includes a plurality of annealing circuits, an exchange circuit, and a temperature adjustment circuit, each of the annealing circuits, the exchange circuit, and the temperature adjustment circuit being electronic circuits distinct from each other, and the annealing circuits being configured to operate in parallel to each other, the method comprising:
causing the plurality of annealing circuits having respective states and respective temperatures differing from each other to calculate respective evaluation function values responsive to the respective states, and to perform a state transition with probabilities responsive to the respective temperatures and the respective evaluation function values;
exchanging, by the exchange circuit, the temperatures or the states between the plurality of annealing circuits with probabilities of exchange, a probability of exchange between two annealing circuits being calculated based on temperatures and evaluation function values of the two annealing circuits; and
changing, by the temperature adjustment circuit, a post-exchange temperature of an annealing circuit of interest among the plurality of annealing circuits, the post-exchange temperature being a temperature immediately after exchange by the exchange circuit, such that a difference between the probability of exchange between the annealing circuit of interest and a first annealing circuit situated next thereto on a lower temperature side in a sequence arranged in order of temperature and the probability of exchange between the annealing circuit of interest and a second annealing circuit situated next thereto on a higher temperature side in the sequence arranged in order of temperature decreases.