Patent ID: 11935597
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 17:
18. The semiconductor device of claim 14, further comprising:
a pattern structure;
an input/output connection wiring disposed on a level higher than the gate electrode;
a plurality of upper interconnections disposed on a level higher than the input/output connection wiring and disposed on height levels different from each other; and
an input/output contact plug disposed to be in contact with the input/output connection wiring and the internal input/output conductive pattern between the input/output connection wiring and the internal input/output conductive pattern, wherein:
the memory cell array region includes a plurality of gate layers, stacked while being spaced apart from each other in a vertical direction, and a vertical memory structure penetrating through the plurality of gate layers,
the plurality of gate layers are disposed below the pattern structure, and
the vertical memory structure is in contact with the pattern structure.