Patent ID: 11860834
Assignee: EMC IP HOLDING COMPANY LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. An apparatus, comprising:
memory; and
at least one processing device, coupled to the memory, operative to implement the following steps:
when a given allocation unit in a storage system matches one or more predefined patterns, then (i) setting a corresponding pattern flag for said given allocation unit, and (ii) incrementing at least one pattern counter;
generating at least one snapshot of at least a portion of a file comprising said given allocation unit;
determining an upper bound of data reduction;
determining a lower bound of data reduction, wherein the lower bound of data reduction is determined using the upper bound; and
determining, using at least one processing device, a range of data reduction attributed to pattern matching based on said at least one pattern counter, wherein one extreme of said range of data reduction attributed to pattern matching excludes said one or more predefined patterns in said at least one snapshot, wherein the one extreme of the range represents the lower bound of the range; and wherein determining the range of data reduction attributed to pattern matching based on said at least one pattern counter, comprises:
summing the respective counts in the at least one pattern counter to produce a summed total of counts;
determining a total number of primary and replica files, wherein the primary files comprise the file and the replica files comprise the at least one snapshot; and
dividing the summed total of counts by the total number of primary and replica files to produce the lower bound of the range,

wherein space savings attributed to the pattern matching is represented by the range of data reduction,
wherein the range of data reduction comprises the upper bound and the lower bound.