Patent ID: 11894075
Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A memory device, comprising:
memory cells arranged in rows and columns, each memory cell comprising 2n logic states configured to store n-bit of data, wherein n is a whole number larger than 1; and
a periphery circuit coupled to the memory cells and configured to program a selected row of memory cells according to n logic pages of current programming data, wherein:
the periphery circuit comprises page buffers, each page buffer comprising n data latches and coupled to a column of memory cells through a bit line; and
the periphery circuit is further configured to:
release an nth data latch, by discarding an nth logic page of the current programming data stored in the nth data latch, before the programming the selected row of memory cells according to then logic pages of the current programming data is completed; and
recover, according to a programming failure signal, the discarded nth logic page of the current programing data using a single level cell (SLC) read, wherein the SLC read comprises:
separating the 2n logic states into a first group and a second group based on a read reference voltage, wherein:
 each logic state in the first group is distinct based on remaining logic pages of the current programming data; and
 each logic state in the second group is also distinct based on the remaining logic pages of the current programming data.