Patent ID: 11915774
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G  H

Claim 10:
11. A memory device, comprising:
a logic die containing control logic circuitry;
a stack of DRAM memory die, wherein each DRAM die of the stack of DRAM memory die is interconnected with at least one other DRAM die of the stack of DRAM memory die by multiple through wafer interconnects; and
the stack of DRAM memory die allocated according to a first partition state establishing multiple first partitions, each partition including one or more arrays from each of two or more DRAM die of the stack of DRAM memory die; and
wherein the control logic circuitry is operable to monitor portions of the stack of DRAM memory die to collect error data indicating a defective portion within one or more of the partitions, and to remove the defective portion from one or more of the multiple first partitions.