Patent ID: 11960728
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A storage device comprising:
a memory device including a first memory die, a second memory die, and an interface circuit; and
a memory controller configured to provide a first data operation command for the first memory die and a second data operation command for the second memory die,
wherein the interface circuit is configured to store at least one of the first data operation command or a first data operation control signal in response to the first data operation command, the first data operation control signal being generated based on the first data operation command,
the memory device is configured to,
perform a first data operation on the first memory die based on the at least one of the first data operation command or the first data operation control signal,
store the at least one of the first data operation command or the first data operation control signal at the interface circuit,
stop the first data operation and perform a second data operation on the second memory die in response to the second data operation command, and
after completion of the second data operation, perform a remaining portion of the first data operation in response to the at least one of the first data operation command or the first data operation control signal stored in the interface circuit, without receiving an additional resume command from an outside of the memory device,
the interface circuit is further configured to store a plurality of data operation commands including the first data operation command and the second data operation command, the plurality of data operation commands corresponding to a plurality of memory dies including the first memory die and the second memory die, respectively, and

the memory device further includes a control logic, the control logic configured to,
generate a data operation control signal based on the first data operation command in response to an input of at least one of an address or a chip selection signal from the memory controller, and
control the memory device to perform a data operation based on the data operation control signal, the address, and the chip selection signal indicating selection of the first memory die.