Patent ID: 11916074
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. A dual transmission gate, comprising:
a first pair of transistors including a first transistor that is situated along a first column or a second column from among a plurality of columns of an electronic device design real estate and a second transistor that is situated along the first column or the second column;
a second pair of transistors including a third transistor that is situated along the first column or the second column and a fourth transistor that is situated along the first column or the second column;
a first region situated along a first interconnection layer of a semiconductor stack along a first row from among a plurality of rows of the electronic device design real estate and connected to the first transistor and the fourth transistor;
a second region, corresponding to a first terminal of the dual transmission gate, situated along the first interconnection layer along a second row from among the plurality of rows of the electronic device design real estate and connected to the first transistor and the second transistor;
a third region situated along a second interconnection layer of the semiconductor stack along a second column from among the plurality of columns and connected to the first pair of transistors and the second pair of transistors;
a fourth region situated along the first interconnection layer along a third row from among the plurality of rows of the electronic device design real estate and connected to the second transistor and the third transistor; and
a fifth region, corresponding to a second terminal of the dual transmission gate, situated along the first interconnection layer along a fourth row from among the plurality of rows of the electronic device design real estate and connected to the third transistor and the fourth transistor.