Patent ID: 11910621
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Electrical machinery, apparatus, energy (Electrical engineering)
Classification: CPC H | IPC H

Claim 4:
5. A method for manufacturing a memory device comprising:
forming a bottom conductive line over a substrate;
after forming the bottom conductive line over the substrate, forming a dielectric layer over the bottom conductive line and the substrate, wherein the dielectric layer is in direct contact with a sidewall of the bottom conductive line;
forming a bottom electrode via opening in the dielectric layer to expose an inner sidewall of the dielectric layer and the bottom conductive line;
forming a selector in the bottom electrode via opening, in direct contact with the inner sidewall of the dielectric layer, and over the bottom conductive line, wherein after forming the selector in the bottom electrode via opening, the dielectric layer is a single piece of continuous material and in direct contact with both the selector and the sidewall of the bottom conductive line;
forming a memory layer over the selector such that a bottommost portion of the memory layer is above a top surface of the dielectric layer; and
forming a top conductive line over the memory layer.