Patent ID: 11922038
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory system comprising:
a nonvolatile memory including a plurality of blocks; and
a memory controller configured to:
set each of the blocks to be in one of a plurality of states, including a first state at which writing and reading are enabled, a second state at which writing is disabled and reading is enabled, a third state at which stored data is invalidated, and a fourth state which is an erased-state;
detect a predetermined condition related to at least one of an amount of data being written into blocks in the first state and state transition of a block;
upon detection of the predetermined condition, determine a maximum number of blocks to be in the fourth state based on a length of time during which each block in the fourth state has been in the fourth state; and
perform an erase operation to cause one or more blocks in the third state to transition to the fourth state when a current number of blocks in the fourth state is less than the maximum number.