Patent ID: 11887675
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A computing system comprising:
flash memory configured to store executable instructions via a floating gate memory array, wherein the flash memory comprises:
the floating gate memory array comprising a plurality of memory cells;
regulating circuitry configured to provide a pulsed wordline signal to a wordline of a memory cell of the plurality of memory cells during a read operation of the memory cell, wherein the pulsed wordline signal varies between a high voltage state and a low voltage state such that electrons that trap during the high voltage state detrap during the low voltage state; and
sense circuitry configured to determine a data value of the memory cell based on a bitline response of the memory cell;

one or more processors communicatively coupled to the flash memory via a data bus and configured to retrieve and execute the executable instructions to perform operations of the computing system; and
a power supply configured to supply power to the flash memory and the one or more processors.