Patent ID: 11950454
Assignee: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G  H | IPC H

Claim 12:
13. A display panel, comprising:
a base substrate; and
pixel circuits arranged in an array on the base substrate, wherein each row of pixel circuits comprises a gate line extending in a row direction, each column of pixel circuits comprises a data line extending in a column direction, the gate line and the data line are disposed on different layers,
wherein the display panel comprises a light transmittance region and a display region around the light transmittance region, the pixel circuits are disposed in the display region, the gate line of each row of m rows of pixel circuits is divided into a first gate line portion and a second gate line portion by the light transmittance region, the first gate line portion is connected to the second gate line portion by an auxiliary gate line, at least part of the auxiliary gate line extends along an edge of the light transmittance region, wherein m is a natural number and m≥2,
wherein the data line of each column of n columns of pixel circuits is divided into a first data line portion and a second data line portion by the light transmittance region, the first data line portion is connected to the second data line portion by an auxiliary data line, wherein n is a natural number and n≥2,
wherein the auxiliary gate line comprises an auxiliary gate line sub-portion, the auxiliary gate line sub-portion and the auxiliary data line have an overlapped region,
wherein the m rows of pixel circuits comprise at least two rows of pixel circuits, an overlapped area of the auxiliary gate line sub-portion of the auxiliary gate line for connecting the first gate line portion and the second gate line portion in one row of the at least two rows of pixel circuits and the auxiliary data line is different from an overlapped area of the auxiliary gate line sub-portion of the auxiliary gate line for connecting the first gate line portion and the second gate line portion in the other one row of the at least two rows of pixel circuits and the auxiliary data line,
wherein each row of pixel circuits further comprises an initialization signal line extending in the row direction, the initialization signal line, the gate line and the data line are located on different layers with, the initialization signal line of each row of the m rows of pixel circuits is divided into a first initialization signal line portion and a second initialization signal line portion by the light transmittance region, first initialization signal line portions and second initialization signal line portions of at least two rows of the m rows of pixel circuits are connected to an auxiliary initialization signal line, the auxiliary initialization signal line is disposed in the same layer with the initialization signal line, and is disposed around the light transmittance region.