Patent ID: 11915055
Assignee: THROUGHPUTER, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A multi-user multi-stage manycore processing system comprising:
at least one entry/exit stage processor to communicate via network data packets with a plurality of users remote to the system;
a plurality of hardware processor stages, each comprising
at least one reconfigurable logic region dynamically assignable by the system to a respective user of the plurality of users for instantiation on demand of at least one configurable application task associated with the respective user, and
a hardware controller comprising
hardware receive logic configured to receive multiplexed packets addressed to respective ones of multiple functions configured on that hardware processor stage, the multiplexed packets including first packets addressed to a first application task currently instantiated in the at least one reconfigurable logic region, and
hardware demultiplexing and buffering logic to buffer and direct the first packets to the first application task; and

an interstage packet switch coupled to respective input and output ports on the at least one entry/exit stage processor and on each of the plurality of hardware processor stages, for switching data packets between the at least one entry/exit stage processor and each of the plurality of hardware processor stages;
wherein the at least one entry/exit stage processor distributes user data packets through the interstage packet switch to the plurality of hardware processor stages in dependence at least in part on the first application task instantiated at each hardware processor stage; and
wherein, in at least a first dynamic configuration of the system, the respective user is the same user for each of the plurality of hardware processor stages, and, in at least a second dynamic configuration of the system, the respective user is a different user for at least two of the plurality of hardware processor stages, and,
wherein, on each hardware processor stage of the plurality of hardware processor stages, the hardware controller is at least partially instantiated in reconfigurable logic, other than the at least one reconfigurable logic region, on that hardware processor stage.