Patent ID: 11929122
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. A method for operating a memory system, the method comprising:
determining levels of an erase voltage and a gate voltage for erasing data stored in plural non-volatile memory cells, arranged in series between a bit line and a source line, in response to an erase command;
applying an erase voltage to a bulk in which the plural non-volatile memory cells are located and applying a negative voltage or a ground voltage of 0V to a word line coupled to the plural non-volatile memory cells;
controlling plural first discharge transistors, coupled in parallel to the source line for providing a first current path, and at least one second discharge transistor, coupled to the bit line for providing a second current path, for controlling the first and second current paths for discharging charges accumulated in a channel formed by the plural non-volatile memory cells through the bit line and the source line to synchronize a discharge rate or time through the bit line and the source line; and
verifying whether the data is erased.