Patent ID: 11870779
Assignee: MICRON TECHNOLOGY, INC.
Field: Digital communication (Electrical engineering)
Classification: CPC H  B | IPC B  H

Claim 0:
1. An apparatus, comprising:
a memory comprising a secure array; and
circuitry comprising one or more registers, wherein the circuitry is configured to:
define an address of the secure array via the one or more registers;
generate a cryptographic hash associated with the secure array responsive to defining the address of the secure array;
compare a run-time cryptographic hash with the cryptographic hash stored in the secure array;
determine an electronic control unit is unauthentic in response to the run-time cryptographic hash and the cryptographic hash being unequal;
receive an updated cryptographic hash in response to replacing the electronic control unit;
store the updated cryptographic hash in the secure array;
generate an updated run-time cryptographic hash based on an identification (ID) number of the replacement electronic control unit;
compare the updated run-time cryptographic hash with the updated cryptographic hash; and
validate the replacement electronic control unit in response to the updated run-time cryptographic hash and the updated cryptographic hash being equal.