Patent ID: 11862237
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A memory, comprising:
a bank, wherein
the bank comprises a plurality of sections, each of the plurality of sections comprises a plurality of word lines, a plurality of bit lines, and a plurality of storage units arranged in an array, each of the plurality of storage units being connected to one of the plurality of word lines and one of the plurality of bit lines; and
the bank is configured to: in a preset mode, in response to a control signal, activate each of a plurality of word lines in at least one target section of the bank, pull up or pull down a level of each of a plurality of bit lines in the target section, and pull a complementary bit line of each of the plurality of bit lines in the target section to a level opposite to a level of the plurality of bit lines, wherein the complementary bit line is a bit line in a section adjacent to the target section.