Patent ID: 11908855
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC B  H

Claim 0:
1. A semiconductor device, comprising:
a first external dummy area;
a second external dummy area; and
a circuit area between the first external dummy area and the second external dummy area,
wherein the circuit area includes circuit active regions, circuit gate lines, and circuit source/drain regions,
wherein the first external dummy area includes a first external dummy active region, and first external dummy gate lines overlapping the first external dummy active region in a vertical direction, the first external dummy gate lines spaced apart from the circuit gate lines,
wherein the second external dummy area includes a second external dummy active region and second external dummy gate lines overlapping the second external dummy active region in the vertical direction, the second external dummy gate lines spaced apart from the circuit gate lines,
wherein each dummy active region of the first external dummy active region and the second external dummy active region has
a linear shape extending in a first horizontal direction, or
a shape including active portions isolated from direct contact with each other and extending sequentially in the first horizontal direction,

wherein the circuit active regions are between the first external dummy active region and the second external dummy active region, and
wherein the circuit active regions include
a first plurality of circuit active regions extending sequentially in the first horizontal direction, and
a second plurality of circuit active regions extending sequentially in a second horizontal direction perpendicular to the first horizontal direction,

wherein each circuit active region of the circuit active regions includes a circuit active pattern and circuit active layers on the circuit active pattern, the circuit active layers spaced apart from each other in the vertical direction and adjacent to the circuit source/drain regions,
wherein the first external dummy active region includes a dummy active pattern and dummy active layers on the dummy active pattern, the dummy active layers spaced apart from each other in the vertical direction,
wherein at least one circuit gate line of the circuit gate lines extends in the second horizontal direction to cover an upper surface, a bottom surface and a side surface of each circuit active layer of the circuit active layers, and
wherein at least one first external dummy gate line of the first external dummy gate lines extends in the second horizontal direction to cover an upper surface, a bottom surface and a side surface of each dummy active layer of the dummy active layers.