Patent ID: 11941281
Assignee: NXP B.V.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. A system, comprising:
a memory device including an array of non-volatile memory cells; and
a memory controller connected to the array of non-volatile memory cells, the memory controller being configured to perform the steps of:
receiving a request to read a value of a memory flag, wherein the memory flag includes a 2-bit value stored in a first memory cell and a second memory cell of the array of non-volatile memory cells;
reading a first value of the first memory cell;
reading a second value of the second memory cell; and
determining the value of the memory flag based on the first value and the second value;
determining that the first value stored by the first memory cell indicates the first memory cell is in a set condition;
determining that the second value stored by the second memory cell indicates the second memory cell is in the set condition;
determining that the memory flag is in an unknown state;

determining that the second memory cell is in a weaker set state than the first memory cell; and
clearing the second memory cell.