Patent ID: 11934916
Assignee: NATIONAL TAIWAN UNIVERSITY
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  B | IPC B  G  H

Claim 14:
15. A method comprising:
forming a source region and a drain region in a substrate;
depositing a first gate dielectric layer to cover the source region and the drain region;
forming a first depletion gate and a second depletion gate over the first gate dielectric layer;
depositing a second gate dielectric layer to cover the first depletion gate and the second depletion gate;
forming an accumulation gate over the second gate dielectric layer;
forming an isolation layer to cover the accumulation gate;
forming a first opening in the isolation layer and the second gate dielectric layer to expose the first gate dielectric layer, wherein a first portion of the accumulation gate is between the first depletion gate and the first opening; and
forming a conductive resonator over the substrate, wherein a first portion of the conductive resonator fills in the first opening.