Patent ID: 11971773
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. A system comprising:
a processor core;
a memory subsystem that includes a first memory circuit and a second memory circuit;
a register coupled to the processor core that includes a first set of outputs configured to provide a first set of power state control signals and a second set of outputs configured to provide a second set of power state control signals;
a power controller coupled to the processor core that includes a set of outputs configured to provide a third set of power state control signals; and
a decode logic circuit that includes:
a first set of inputs coupled to the first set of outputs of the register;
a second set of inputs coupled to the second set of outputs of the register;
a third set of inputs coupled to the set of outputs of the power controller;
a first set of outputs coupled to the first memory circuit, wherein the decode logic circuit is configured to provide a fourth set of power state control signals via the first set of outputs that is based on the first set of power state control signals and the third set of power state control signals; and
a second set of outputs coupled to the second memory circuit, wherein the decode logic circuit is configured to provide a fifth set of power state control signals via the first set of outputs that is based on the second set of power state control signals and the third set of power state control signals.