Patent ID: 11862527
Assignee: TSMC CHINA COMPANY, LIMITED
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A device, comprising:
an oxide layer on a substrate top surface;
a layer of semiconductor material over the oxide layer;
a first thermal substrate contact extending through a first doped well in the layer of semiconductor material, wherein the first doped well surrounds the first thermal substrate contact in the layer of semiconductor material, and a depth of the first thermal substrate contact in the substrate is less than a thickness of the substrate; and
a second thermal substrate contact extending through a second doped well in the layer of semiconductor material, a channel region of a transistor being between the first doped well and the second doped well, wherein a depth of the second thermal substrate contact in the substrate is less than the thickness of the substrate.