Patent ID: 11899532
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. An apparatus, comprising:
a memory device comprising a plurality of memory cells, and
one or more controllers coupled with the memory device and configured to cause the apparatus to:
receive an indication of a timeout duration for a boot sequence of a host system;
store information for the boot sequence in a set of memory cells of the plurality of memory cells based at least in part on the timeout duration; and
access the information for the boot sequence that is stored in the set of memory cells based at least in part on an initialization of the boot sequence, wherein:
the timeout duration is for a first portion of the boot sequence,
the indication further comprises a second indication of a second timeout duration for a second portion of the boot sequence, and
the information stored in the set of memory cells is for the first portion of the boot sequence that precedes the second portion of the boot sequence.