Patent ID: 11894353
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. The driving substrate according to claim 1, comprising:
the base substrate;
a buffer layer located on the base substrate;
an active layer located on a side of the buffer layer away from the base substrate;
a gate insulation layer located on a side of the active layer away from the base substrate;
a gate of the driving thin film transistor located on a side of the gate insulation layer away from the base substrate;
an interlayer insulation layer located on a side of the gate away from the base substrate;
a source-drain metal layer located on a side of the interlayer insulation layer away from the base substrate, the source-drain metal layer comprising: a first electrode, a second electrode of the driving thin film transistor and a common electrode line, the first electrode and the second electrode being connected to the active layer through a via hole going through the interlayer insulation layer and the gate insulation layer;
a planarization layer located on a side of the source-drain metal layer away from the base substrate;
a passivation layer located on a side of the planarization layer away from the base substrate;
the pad layer is located on a side of the passivation layer away from the base substrate, comprising a plurality of first pads and a plurality of second pads, each of the first pads being connected to the first electrode of a corresponding driving thin film transistor through a via hole going through the planarization layer and the passivation layer, each of the second pads being connected to a corresponding common electrode line through a via hole going through the planarization layer and the passivation layer, the first pad and the second pad each comprising the pad body and the microstructure of hard conductive material provided on a side of the pad body away from the base substrate;
the plurality of buffer structures is provided on a side of the passivation layer away from the base substrate, each buffer structure surrounding a portion of a corresponding microstructure close to the base substrate, and a height of the buffer structure being lower than a height of the microstructure.