Patent ID: 11921645
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus, comprising one or more processor cores to be communicatively coupled to a cache memory, the one or more processor cores to:
encrypt a key identification (ID) and an encryption key into an encryption package unreadable by a virtual machine or a virtual machine manager;
provide the encryption package to trusted software to cause the key ID to be programmed by the virtual machine or the virtual machine manager into a direct data input output (DDIO) circuitry to be coupled to the one or more processor cores, the DDIO circuitry configured to transfer DDIO data between the cache memory and an accelerator circuitry and to encrypt and decrypt DDIO data for the accelerator circuitry;
after providing the encryption package to the trusted software, receive the encryption package with an unwrap command from the virtual machine or the virtual machine manager; and
execute the unwrap command by decrypting the encryption package and by sending a cryptographic response to the virtual machine or virtual machine manager verifying that the unwrap command was successfully executed.