Patent ID: 11908526
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 10:
11. A method of controlling a semiconductor memory device, the semiconductor memory device including a first memory cell arranged in a first region, and a second memory cell arranged in a second region, said method comprising:
obtaining first data based on a first read operation performed on the first memory cell, and second data based on the first read operation performed on the second memory cell;
obtaining third data based on a second read operation performed on the first memory cell, and fourth data based on the second read operation performed on the second memory cell, the second read operation being different from the first read operation in a read voltage;
setting a first value indicating likelihood of data stored in the first memory cell based on first information indicating that the first memory cell is arranged in the first region;
in a case where the fourth data is equal to the third data, setting a second value different from the first value, the second value indicating likelihood of data stored in the second memory cell based on second information indicating that the second memory cell is arranged in the second region; and
performing error correction on data read from the first memory cell using at least the third data and the first value, and performing error correction on data read from the second memory cell using at least fourth data and the second value.