Patent ID: 11967519
Assignee: INNOSCIENCE (SUZHOU) SEMICONDUCTOR CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An integrated semiconductor device, comprising:
a substrate;
a plurality of semiconductor circuit layers disposed above the substrate and having a plurality of device portions and one or more isolating portions located among the device portions, the isolating portions providing electrical isolation between adjacent said device portions;
a first insulating layer disposed on the semiconductor circuit layers;
a second insulating layer disposed on the first insulating layer; and
an interconnection layer disposed on the semiconductor circuit layers and penetrating the first and second insulating layers to electrically connect the device portions;, wherein some of the semiconductor circuit layers form at least one heterojunction, and the second insulating layer or the first and second insulating layers collectively form one or more trenches above each isolating portion of the semiconductor circuit layers, and the interconnection layer has a plurality of first circuits located above the device portions.