Patent ID: 11861234
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A system comprising:
a memory sub-system comprising:
a single-level cell (SLC) cache comprising a static SLC cache and a dynamic SLC cache, wherein the static SLC cache has a fixed size, wherein the dynamic SLC cache has a default maximum size corresponding to a first mode of operation and an enhanced maximum size greater than the default maximum size corresponding to a second mode of operation;
a multiple level cell (XLC) storage; and
a processing device, operatively coupled with the SLC cache and XLC storage, to perform operations comprising:
receiving data to write to the memory sub-system;
determining whether to initiate a write operation in the first mode;
in response to determining to initiate the write operation in the first mode, initiating the write operation in the first mode to write a first portion of the data to the SLC cache;
determining whether a logical saturation of the first portion of the data written to the SLC cache satisfies a first threshold condition based on the default maximum size; and
in response to determining that the logical saturation of the first portion of the data satisfies the first threshold condition, continuing the write operation in the second mode to write a second portion of the data to the SLC cache.