Patent ID: 11892506
Assignee: MEDIATEK SINGAPORE PTE. LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A multicycle path circuit comprising:
a logic circuit configured to operate with a first clock signal of a first time period;
a memory coupled to the logic circuit and configured to operate with a second clock signal of a second time period that is a multiple of the first time period; and
an on-chip clock controller coupled to the logic circuit and the memory and configured to provide the first clock signal to the logic circuit and the second clock signal to the memory,
wherein the multicycle path circuit is configured to operate in a functional mode in which the logic circuit controls read and/or write of the memory, and
wherein the multicycle path circuit is configured to operate in an at-speed test mode in which the logic circuit controls read and/or write of the memory to test a transition, over a plurality of clock cycles of the first clock signal, of a value output from the memory,
wherein the on-chip clock controller is configured to ensure clock paths to the logic circuit and the memory are the same for the functional mode and the at-speed test mode to avoid hold and setup timing conflict between the functional mode and test mode due to clock divergence.