Patent ID: 11942131
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. The processing apparatus of claim 18,
wherein each of the plurality of bit-cells further comprises a third switching element electrically connected to the pinned layer and the first region of the first magnetic resistor,
wherein, when the processing apparatus performs a write operation, the third switching element, the fourth switching element, and the fifth switching element of a bit-cell on which the write operation is performed are in an on status,
wherein a voltage corresponding to a first data line electrically connected to the fourth switching element is provided to the pinned layer as a first bias voltage via the fourth switching element,
wherein the first bias voltage is provided to the first region via the third switching element, and
wherein a voltage corresponding to a second data line electrically connected to the fifth switching element is provided to the second region as a second bias voltage via the fifth switching element and the first switching element.