Patent ID: 11928500
Assignee: CADENCE DESIGN SYSTEMS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. A non-transitory computer-readable medium comprising instructions that, when executed by a hardware processor of a device, cause the device to perform operations comprising:
accessing a tree data structure for a plurality of networks of a circuit design, each node of the tree data structure being associated with a different group of networks of the plurality of networks, the tree data structure being generated by iteratively partitioning and grouping the plurality of networks to generate the different groupings of networks for nodes of the tree data structure; and
performing, by the hardware processor, routing of the plurality of networks by a plurality of threads, the performing routing of the plurality of networks comprising assigning tasks for routing the plurality of networks, to threads of the plurality of threads, based on the tree data structure.