Patent ID: 11899532
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. An apparatus, comprising:
a memory device comprising a plurality of memory cells, and
one or more controllers coupled with the memory device and configured to cause the apparatus to:
receive an indication of a timeout duration for a boot sequence of a host system;
store information for the boot sequence in a set of memory cells of the plurality of memory cells based at least in part on the timeout duration;
access the information for the boot sequence that is stored in the set of memory cells based at least in part on an initialization of the boot sequence;
receive, subsequent to accessing the information for the boot sequence, a second indication of a second timeout duration for the boot sequence of the host system;
store the information for the boot sequence in a second set of memory cells of the plurality of memory cells based at least in part on the second timeout duration; and
access, after storing the information for the boot sequence in the second set of memory cells, the information stored in the second set of memory cells based at least in part on a subsequent initialization of the boot sequence.