Patent ID: 11934564
Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 2:
3. The secure computation device according to claim 2,
wherein d0=1/m0 and d1=1/m1 are divisors, p is a modulus of a positive integer, and q is a quotient of a positive integer, and
the first secure computation circuitry includes
third secure computation circuitry configured to obtain a secret share value [q] of a quotient q of a/p through secure computation using the secret share value [a] and a modulus p; and
fourth secure computation circuitry configured to obtain and output [m0a]=[a/d0]=[(a+qp)/d0]−[q]p/d0 and [m1a]=[a/d1]=[(a+qp)/d1]−[q]p/d1 through secure computation using the secret share value [a], the secret share value [q], the divisors d0 and d1, and the modulus p.