Patent ID: 11961798
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. The semiconductor structure of claim 1, wherein each of the at least two electrode layers comprises a first electrode block and a second electrode block that are arranged in a same layer and interval arranged, and the first electrode block and the second electrode block that are located in a same electrode layer are mutually insulated from each other, and
in two adjacent electrode layers of the at least two electrode layers, the two first electrode blocks that are adjacent to each other and arranged in different layers overlap with each other and have a second overlapping area, the first electrode block and the second electrode block that are adjacent to each other and arranged in different layers overlap with each other, have a third overlapping area and are electrically connected with each other by a contact window.