Patent ID: 11900039
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 7:
8. A circuit comprising:
first logic having first transistors coupled in series and activated with first signals, second transistors activated with the first signals, and third transistors configured with a first input coupled to the first transistors, a second input coupled to the second transistors, and a first output that provides a first output signal based on the first signals; and
second logic having fourth transistors coupled in series and activated with second signals including the first output signal, fifth transistors coupled in parallel and activated with the second signals including the first output signal, and sixth transistors configured with a third input coupled to the fourth transistors, a fourth input coupled to the fifth transistors, and a second output that provides a second output signal based on the second signals including the first output signal,
wherein the second output signal refers to an XOR logic output signal or an XNOR logic output signal.