Patent ID: 11901840
Assignee: GREE ELECTRIC APPLIANCES, INC. OF ZHUHAI
Field: Semiconductors (Electrical engineering)
Classification: CPC H  Y | IPC H

Claim 0:
1. A preparation method for a three-phase inverter power chip, comprising:
forming a channel layer and a potential energy barrier layer on a side surface of a substrate in sequence;
forming three active area pairs on the channel layer and the potential energy barrier layer along a first direction by an isolation process;
each of the three active area pairs comprising two active areas, wherein, among the two active areas comprised in each of the active area pairs, one active area is configured to form a high-side transistor therein, and the other active area is configured to form a low-side transistor therein;
forming an isolation area outside the active areas, and at a side of the channel layer and of the potential energy barrier layer away from the substrate;
forming a chip device layer on the potential energy barrier layer;
each portion of the chip device layer corresponding to each of the active areas comprising a source electrode, a drain electrode, and a gate electrode, and another portion of the chip device layer corresponding to the isolation area comprising a first bond pad, second bond pads configured to correspond one-to-one with the three active area pairs, third bond pads configured to correspond one-to-one with the three active area pairs, and fourth bond pads configured to correspond one-to-one with the active areas;
in each group of the three active area pairs, the first bond pad, the second bond pads the third bond pads, and the fourth bond pads, which correspond to each other, electrically connecting the drain electrode arranged in each of the active areas, configured to form the high-side transistor, to the first bond pad,
electrically connecting the source electrode arranged in each of the active areas, configured to form the high-side transistor, to each of the second bond pads, respectively,
electrically connecting the drain electrode arranged in each of the active areas, configured to form the low-side transistor, to each of the second bond pads, respectively,
electrically connecting the source electrode arranged in each of the active areas configured to form the low-side transistor, to each of the third bond pads, respectively, and
electrically connecting the gate electrode arranged in each of the active areas to each of the fourth bond pads, respectively;
forming a dielectric passivation layer on the chip device layer; and
etching the dielectric passivation layer, and exposing the first bond pad, the second bond pads, the third bond pads, and the fourth bond pads.