Patent ID: 11967527
Assignee: APPLIED MATERIALS, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of forming fully aligned vias, the method comprising:
forming a patterned fourth metal layer and patterned fourth etch stop layer on a third metal layer using a hard mask layer and a patterned photoresist;
forming a patterned third metal layer on top of a patterned metal liner on a second metal layer using the patterned fourth metal layer and patterned fourth etch stop layer as a mask, the second metal layer in electrical contact with a first metal layer, the patterned third metal layer and patterned metal liner misaligned from the second metal layer so that a portion of the top of the second metal layer is exposed through the openings in the patterned third metal layer and the patterned metal liner; and
recessing the second metal layer through the openings in the patterned third metal layer and patterned metal liner to lower the top of the second metal layer and expose sides of the second metal layer aligned with sides of the patterned third metal layer and a top surface of the second metal layer spaced a distance from a bottom surface of the metal liner, the top surface of the second metal layer spaced a distance in the range of about 5 Å to about 100 Å from the bottom surface of the metal liner.