Patent ID: 11922106
Assignee: SYNOPSYS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. A method for static timing analysis, the method comprising:
extracting information associated with constraints and clock information from a file of a circuit design;
determining, by at least one computer processor, a topological cone based on the extracted information for a partition of two or more partitions of the circuit design, the topological cone including objects associated with the partition of the two or more partitions of the circuit design, wherein determining the topological cone comprises:
adding one or more dangling stage logic and pre-dangling stage logic, wherein dangling stage logic are aggressors at a first stage and pre-dangling stage logic are aggressors of a second stage before the first stage; and

performing timing analysis on the partition of the two or more partitions based on the topological cone.