Patent ID: 11894424
Assignee: POSTECH RESEARCH AND BUSINESS DEVELOPMENT FOUNDATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. Method for manufacturing a fin field-effect transistor comprising:
(a) forming a channel, a gate, and an insulating layer in a predetermined region of a substrate so that the insulating layer is formed from both sides of the gate on an upper portion of the substrate,
(b) performing etching along side surfaces of the channel and the insulating layer so as to etch even an upper portion of one side of the substrate for forming source/drain regions, so that a designated region of the substrate is exposed and so that the insulating layer, patterned so as to wrap the exposed region of the substrate, is formed on the substrate, and
(c) forming the source/drain regions, in which growth in a width direction (Y-axis direction) is restricted through a selective epitaxial growth process, in the exposed region of the substrate.