Patent ID: 11901840
Assignee: GREE ELECTRIC APPLIANCES, INC. OF ZHUHAI
Field: Semiconductors (Electrical engineering)
Classification: CPC H  Y | IPC H

Claim 5:
6. A three-phase inverter power chip, comprising:
a substrate;
a channel layer and a potential energy barrier layer formed on a side surface of the substrate in sequence, three active area pairs being formed on the channel layer and the potential energy barrier layer along a first direction, each of the three active area pairs comprising two active areas arranged in a direction perpendicular to the first direction, wherein, among the two active areas in each of the three active area pairs, one active area is configured to form a high-side transistor therein, and the other active area is configured to form a low-side transistor therein;
an isolation region, formed outside the active areas and formed at a side of the channel layer and the potential energy barrier layer away from the substrate;
a chip device layer formed on a side of the potential energy barrier layer away from the channel layer, wherein: each portion of the chip device layer, which is corresponding to each of the active areas, comprises a source electrode, a drain electrode, and a gate electrode; another portion of the chip device layer corresponding to the isolation area comprises a first bond pad, second bond pads configured to correspond one-to-one with the active area pairs, third bond pads configured to correspond one-to-one with the active area pairs, and fourth bond pads configured to correspond one-to-one with the active areas; in the active area pairs, the drain electrodes in the active areas configured to form high-side transistors respectively are electrically connected to the first bond pad; in the active area pairs, the source electrodes arranged in the active areas configured to form high-side transistors are electrically connected to the second bond pads corresponding one-to-one with the active area pairs, respectively; in the active area pairs, the drain electrodes arranged in the active areas configured to form low-side transistors are electrically connected to the second bond pads corresponding one-to-one with the active area pairs, respectively; in each the active area pairs, the source electrodes arranged in the active area configured to form the low-side transistors are electrically connected to the third bond pads corresponding one-to-one with the active area pairs, respectively; and in the active area pairs, the gate electrodes arranged in the active areas are electrically connected to the fourth bond pads corresponding one-to-one with the active areas, respectively; and
the dielectric passivation layer formed on a side of the chip device layer away from the substrate, wherein portions of the dielectric passivation layer, which are opposite to the first bond pad, the second bond pads, the third bond pads, and the fourth bond pads, are respectively etched to expose the first bond pad, the second bond pads, the third bond pads and the fourth bond pads.