Patent ID: 11869614
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. A data storage device, comprising:
a controller;
a non-volatile memory (NVM) device coupled to the controller, the NVM device comprising a plurality of wordlines, each comprising a plurality of cells; and
a cell statistics generator (CSG) coupled to the NVM and comprising logic configured to cause the CSG to:
accumulate left error voltage values of each cell of the plurality of cells that are left of a hard decode voltage value within a left bin spacing;
accumulate right error voltage values of each cell of the plurality of cells that are right of the hard decode voltage value within a right bin spacing;
combine by a first combiner operating in additive mode to add accumulated left error voltage values and right error voltage values and an expectation constant to generate a deviation value operable to position the left bin spacing and right bin spacing, wherein based on a value of the deviation output, an optimizing and tuning unit is configured to shift the left error voltage values and the right error voltage values as a pair; and
calculate a dispersion output by a second combiner operating in subtractive mode to add the left error voltage values and the right error voltage values and subtract the expectation constant, wherein the expectation constant is an expected accumulation of left error voltages and the right error voltage.