Patent ID: 11935613
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A device, comprising:
a memory storing instructions; and
a processor adapted to be coupled to a Double Data Rate (DDR) flash memory by way of a Serial Peripheral Interface (SPI), the processor configured to execute the instructions stored in the memory to:
determine a first value of a reference clock delay (RD) cycle based on a comparison of results of a plurality of read transactions with the DDR flash memory, each read transaction performed using values of a transmit clock delay and a receive clock delay of one set of parameters and a test value of the RD cycle, wherein the test value of the RD cycle is a different value in each of the plurality of read transactions and the first value of the RD cycle is set to a smallest value of the RD cycle that results in a successful read transaction with the DDR flash memory;
determine a second value of the RD cycle based on a comparison of results of a plurality of read transactions with the DDR flash memory, each read transaction performed using values of the transmit clock delay and the receive clock delay of another set of parameters and a test value of the RD cycle, wherein the test value of the RD cycle is a different value in each of the plurality of read transactions and the second value of the RD cycle is set to the smallest value of the RD cycle that results in a successful read transaction with the DDR flash memory;
determine final largest and smallest successful values of a receive clock delay by:
determining first largest and smallest successful values of a receive clock delay at the first value of the transmit clock delay and determining second largest and smallest successful values of the receive clock delay at the second value of the transmit clock delay; and
setting the final largest successful value of the receive clock delay to a larger of the first and second largest values of the receive clock delay and setting the final smallest successful value of the receive clock delay to a smaller of the first and second smallest values of the receive clock delay;

determine final largest and smallest successful values of the transmit clock delay by:
determining first largest and smallest successful values of the transmit clock delay at a first value of the receive clock delay and determining second largest and smallest successful values of the transmit clock delay at a second value of the receive clock delay; and
setting the final largest successful value of the transmit clock delay to a larger of the first and second largest values of the transmit clock delay and setting the final smallest successful value of the transmit clock delay to a smaller of the first and second smallest values of the transmit clock delay;

set a first set of parameters for the SPI, the first set of parameters comprising the final largest value of the transmit clock delay, the final largest successful value of the receive clock delay, and a first value of the RD cycle;
set a second set of parameters for the SPI, the second set of parameters comprising the final smallest value of the transmit clock delay, the final smallest successful value of the receive clock delay, and a second value of the RD cycle;
select one of the first and second sets of parameters based on a determination of whether the first set of parameters is usable by the processor to read successfully from the DDR flash memory over a larger range of operating temperatures of the device than the second set of parameters; and
program the SPI using the selected one of the first and second sets of parameters.