Patent ID: 11967385
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A memory system comprising:
a semiconductor storage device including a first memory chip and a second memory chip; and
a controller configured to issue commands to the first memory chip and the second memory chip, wherein
the first memory chip includes a first memory cell, a first word line connected to the first memory cell, a first voltage step-up circuit, and a second voltage step-up circuit,
the second memory chip includes a second memory cell, a second word line connected to the second memory cell, a third voltage step-up circuit, and a fourth voltage step-up circuit,
the controller is configured to transmit a read status command to the second memory chip to check a status of the second memory chip after transmitting a read command to the first memory chip, and transmit an assist request command to the second memory chip based on the status obtained in response to the read status command, and
in response to the read command, the first and second voltage step-up circuits supply a first voltage to the first word line, and in response to the assist request command, the fourth voltage step-up circuit assists the first and second voltage step-up circuits in supplying the first voltage to the first word line, and wherein,
when a voltage of the first word line reaches a predetermined voltage, the first voltage step-up circuit continues to supply the first voltage to the first word line, and the second voltage step-up circuit and the fourth voltage step-up circuit stop supplying the first voltage to the first word line.