Patent ID: 11862570
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A semiconductor package comprising:
a substrate including a first insulating layer and first conductive patterns in the first insulating layer, an upper passivation film, first upper pads, and second upper pads;
an interposer disposed on a top surface of the substrate and including a second insulating layer and second conductive patterns in the second insulating layer;
connecting members contacting the substrate and the interposer, electrically connecting the first conductive patterns and the second conductive patterns;
supporting members including solder parts which are in contact with the top surface of the substrate and a bottom surface of the interposer, and core parts which are disposed in the solder parts and include a different material from the solder parts,
a semiconductor chip mounted on the top surface of the substrate and spaced apart from a bottom surface of the interposer; and
a molding formed to cover a top surface of the semiconductor chip and the bottom surface of the interposer,
wherein the upper passivation film, the first upper pads, and the second upper pads are formed on a top surface of the first insulating layer, the first upper pads in contact with the connecting members respectively, and the second upper pads in contact with the supporting members respectively,
wherein the upper passivation film covers at least parts of the first upper pads and the second upper pads so as to include a top surface that is at a higher vertical level in a direction perpendicular to the top surface of the substrate than top surfaces of the first upper pads and the second upper pads, and
wherein the supporting members do not electrically connect the first conductive patterns and the second conductive patterns.