Patent ID: 11888044
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 0:
1. A semiconductor device, comprising:
a lower channel pattern and an upper channel pattern stacked on a substrate in a first direction perpendicular to a top surface of the substrate, the lower channel pattern having a first side and a second side opposite the first side, the upper channel pattern having a third side and a fourth side opposite the third side;
lower source/drain patterns on the substrate and at the first side and the second side of the lower channel pattern;
upper source/drain patterns stacked on the lower source/drain patterns and at the third side and the fourth side of the upper channel pattern;
a first barrier pattern between the lower source/drain patterns and the upper source/drain patterns; and
a second barrier pattern between the first barrier pattern and the upper source/drain patterns,
wherein the first barrier pattern includes a first material and the second barrier pattern includes a second material,
wherein the first material and the second material are either i) different semiconductor materials having different conductivity types, or ii) different insulating materials with the second material being doped with a semiconductor element.