Patent ID: 11941371
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. An apparatus, comprising:
a memory device comprising a first register and a second register; and
a processing device configured to:
reduce a quantity of bits associated with at least a portion of bits of a result of a first arithmetic operation, or a first logical operation, or both;
cause a first value corresponding to the reduced quantity of bits of the result of the first arithmetic operation, the first logical operation, or both to be written to the first register;
cause a first factor used to reduce the quantity of bits of the result of the first arithmetic operation, the first logical operation, or both to be written to the second register;
set a quantity of bits for use by the first register to a quantity of bits substantially equal to a quantity of bits associated with the first arithmetic operation, the first logical operation, a second arithmetic operation, or a second logical operation, or any combination thereof; and
modify the quantity of bits for use by the first register responsive to determining that a result of a subsequent iteration of the first arithmetic operation, or the first logical operation, or both, contains a quantity of bits greater than a threshold quantity of bits.