Patent ID: 11934326
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus, comprising:
a memory array,
wherein the apparatus is configured to receive, from a command bus, a command as a corresponding plurality of bits, wherein the plurality of bits includes (a) a first set of bits usable to instruct the apparatus to execute an access operation and (b) a second set of bits usable to instruct the apparatus to execute a refresh operation,
wherein the apparatus is configured, in response to receiving the first set of bits of the command, to execute the access operation on a first portion of the memory array, and
wherein, in addition to executing the access operation in response to the first set of bits of the command, the apparatus is further configured, in response to the second set of bits of the command, to execute the refresh operation to refresh a second portion of the memory array.