Patent ID: 11880710
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. A system comprising:
a plurality of memory elements comprising a first memory element to store input data of a requested function and output data of the requested function;
a plurality of candidate compute elements operable to execute the requested function; and
a scheduling engine comprising circuitry, the scheduling engine to select a candidate compute element from the plurality of candidate compute elements based on a combined burden, the combined burden based on an estimated burden to execute the function by the candidate compute element, an estimated burden of data movement of the input data from the first memory element over at least one interconnect identified for the candidate compute element, and an estimated burden of data movement of the output data over the at least one interconnect to the first memory;
wherein the estimated burden of data movement over the at least one interconnect identified for the candidate compute element is based on a first estimated time to send input data over the at least one interconnect to the candidate compute element and a second estimated time to send output data from the candidate compute element over the at least one interconnect.