Patent ID: 11935853
Assignee: nan
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An apparatus, comprising:
a substrate of a memory die, the substrate comprising a frontside and a backside opposite the frontside;
control circuitry on the frontside of the substrate of the memory die;
a memory array on the memory die, the memory array over and electrically coupled to the control circuitry;
a through-silicon via (TSV) disposed under the memory array on the memory die, the TSV extending through the substrate of the memory die from the control circuitry to the backside of the substrate; and
a bond pad disposed on the backside of the substrate of the memory die and electrically coupled to the control circuitry via the TSV, wherein the bond pad, in connection with the TSV and the control circuitry, is configured to provide an interface between the memory array and one or more external components.