Patent ID: 11967833
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  B | IPC G  H

Claim 0:
1. A method for controlling a memory device, comprising:
performing a first erase operation of erasing data stored in a plurality of first memory cells in a first sub memory block, while erasing data stored in a plurality of second memory cells in a second sub memory block being prohibited,
wherein the memory device including
a memory cell array including a memory block, the memory block including the first sub memory block and the second sub memory block, the first sub memory block including the plurality of first memory cells, and the second sub memory block including the plurality of second memory cells;
a first drain side selective transistor electrically connected to the first memory cells;
a second drain side selective transistor electrically connected to the second memory cells;
a first source side selective transistor electrically connected to the first memory cells;
a second source side selective transistor electrically connected to the second memory cells;
a third source side selective transistor electrically connected to the first memory cells;
a fourth source side selective transistor electrically connected to the second memory cells;
a source line electrically connected to the first source side selective transistor and the second source side selective transistor;
a plurality of first word lines electrically connected to gates of the first memory cells;
a plurality of second word lines electrically connected to gates of the second memory cells;
a first source side select gate line electrically connected to a gate of the first source side selective transistor;
a second source side select gate line electrically connected to a gate of the second source side selective transistor;
a third source side select gate line electrically connected to a gate of the third source side selective transistor; and
a fourth source side select gate line electrically connected to a gate of the fourth source side selective transistor.