Patent ID: 11916060
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A method for forming an integrated chip (IC), the method comprising:
forming a gate dielectric structure over a semiconductor substrate;
forming a gate electrode structure overlying the gate dielectric structure;
forming a patterned masking layer over the semiconductor substrate, wherein the patterned masking layer comprises a plurality of drain openings on a first side of the gate dielectric structure and a source opening on a second side of the gate dielectric structure, wherein the second side of the gate dielectric structure is opposite the first side of the gate dielectric structure, and wherein each of the plurality of drain openings are formed on the first side of the gate dielectric structure;
with the patterned masking layer in place, performing a doping process to selectively implant first doping type dopants into the semiconductor substrate through the plurality of drain openings and through the source opening, thereby forming a drain region in the semiconductor substrate and on the first side of the gate dielectric structure and forming a source region in the semiconductor substrate and on the second side of the gate dielectric structure;
after the doping process is performed, removing the patterned masking layer;
after the patterned masking layer is removed, forming a silicide blocking layer over the semiconductor substrate and partially covering the drain region; and
with the silicide blocking layer in place over the semiconductor substrate, performing a silicide process on the semiconductor substrate to form a first silicide structure partially over the drain region.