Patent ID: 11925033
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 1:
2. The method of claim 1, wherein forming the first protection layer, the second protection layer, the first NSFET, and the second NSFET comprises:
forming spacer layers arranged between semiconductor layers over the first substrate;
forming a first dummy gate structure and a second dummy gate structure over the spacer layers;
removing portions of the spacer and semiconductor layers that do not directly underlie the first and second dummy gate structures, wherein a bottommost spacer layer is not removed and remains completely covered by a bottommost semiconductor layer;
removing outer portions of exposed spacer layers;
forming inner spacer structures on the exposed spacer layers;
removing portions of the bottommost semiconductor layer and the bottommost spacer layer that do not directly underlie the first and second dummy gate structures;
selectively removing the bottommost spacer layer;
forming the first protection layer directly between the first substrate and the bottommost semiconductor layer and directly below the first dummy gate structure;
forming the second protection layer directly between the first substrate and the bottommost semiconductor layer and directly below the second dummy gate structure;
forming the first, second, and third source/drain regions over the first substrate;
removing the first and second dummy gate structures and remaining portions of the spacer layers;
forming the first gate electrode over and between the semiconductor layers that are arranged over the first protection layer to form the first NSFET; and
forming the second gate electrode over and between the semiconductor layers that are arranged over the second protection layer to form the second NSFET.