Patent ID: 11955484
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. A semiconductor device, comprising:
a semiconductor substrate having a first region and a second region;
a first transistor in the first region, comprising:
a first semiconductor fin on the semiconductor substrate, wherein the first semiconductor fin comprises source/drain regions and a channel region, a width of the channel region of the first semiconductor fin is equal to widths of the source/drain regions of the first semiconductor fin, a dopant of the first semiconductor fin comprises boron, BF2, phosphorus, arsenic, or a combination thereof;
a plurality of first insulators disposed on the semiconductor substrate, wherein the first semiconductor fin is sandwiched by the plurality of first insulators;
a first gate stack over a portion of the first semiconductor fin and over a portion of the plurality of first insulators; and
a first S/D covering another portion of the first semiconductor fin; and

a second transistor in the second region, comprising:
a second semiconductor fin on the semiconductor substrate, wherein the second semiconductor fin comprises source/drain regions and a channel region, a width of the channel region of the second semiconductor fin is different from widths of the source/drain regions of the second semiconductor fin, a dopant of the second semiconductor fin comprises boron, BF2, phosphorus, arsenic, or a combination thereof, a dopant concentration within the second semiconductor fin ranges from 2×1012 atom/cm2 to 5×1014 atom/cm2 and the dopant concentration within the first semiconductor fin is less than the dopant concentration within the second semiconductor fin;
a plurality of second insulators disposed on the semiconductor substrate, wherein the second semiconductor fin is sandwiched by the plurality of second insulators;
a second gate stack over a portion of the second semiconductor fin and over a portion of the plurality of second insulators; and
a second S/D covering another portion of the second semiconductor fin.