Patent ID: 11875840
Assignee: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. A semiconductor device comprising:
a cell circuit including a plurality of memory arrays; and
a control circuit configured to control the cell circuit,
wherein a memory array of the plurality of memory arrays includes:
a plurality of sub-arrays having a first sub-array and a second sub array; and
an array connecting circuit configured to connect bit lines of the first sub-array to corresponding bit lines of the second sub-array, respectively, according to a copy signal,
where each of the plurality of sub-arrays includes:
a plurality of bit lines;
a plurality of word lines;
a cell array including a plurality of rows respectively corresponding to the plurality of word lines, each row comprising a plurality of memory cells respectively connected between the plurality of bit lines and the word line corresponding to that row; and
a plurality of sense amplifiers connected to the plurality of bit lines, and

wherein the semiconductor device performs a NOT operation on data of a first memory cell included in the first sub-array by:
reading the data of the first memory cell onto a first bit line connected to the first memory cell using a first sense amplifier, and
connecting the first bit line to a second bit line of the second sub-array using the array connecting circuit while the data of the first cell is present on the first bit line.