Patent ID: 11868704
Assignee: INFINERA CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 8:
9. A device comprising:
processing circuitry;
memory circuitry in communication with the processing circuitry;
the processing circuitry configured to parse a data container definition file to determine a packet format;
the processing circuitry further configured to generate a code file based on the data container definition file;
the processing circuitry further configured to insert the code file into a source tree of an application;
the processing circuitry further configured to compile the source tree to generate an executable file;
the processing circuitry further configured to execute the executable file to encode packets in the packet format, write the packets into a packet buffer, and transmit the packets from the packet buffer to a communication network for data exchange over the communications network;
the processing circuitry being configured to determine a number of pad bytes to be stored in the packet buffer; and
storing the packets in the packet buffer such that a length of the packet buffer is aligned at a boundary to provide padding, the packets being stored in the packet buffer prior to said transmitting the packet.