Patent ID: 11869800
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A device comprising:
a semiconductor substrate;
a well feature disposed in the semiconductor substrate;
a dielectric isolation structure disposed in the semiconductor substrate around the well feature, the dielectric isolation structure having a top surface facing away from the semiconductor substrate, the top surface of the dielectric isolation structure extending along a first plane, the dielectric isolation structure further having a sidewall surface facing the well feature and a portion of the semiconductor substrate that is free of the well feature, wherein the portion of the semiconductor substrate that is free of the well feature is disposed directly on the sidewall surface of the dielectric isolation structure;
a silicon-containing layer disposed directly on the well feature, wherein the silicon-containing layer has a bottom surface facing the semiconductor substrate and an opposing top surface facing away from the semiconductor substrate, the bottom surface of the silicon-containing layer interfacing with the well feature;
a semiconductor layer disposed directly on the first silicon-containing layer, wherein the semiconductor layer and the silicon-containing layer do not extend above the first plane that the top surface of the dielectric isolation structure extends along;
a gate structure disposed directly on the semiconductor layer; and
a source/drain feature disposed in the substrate and interfacing with the top surface of the silicon-containing layer and the semiconductor layer.