Patent ID: 11934264
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A data storage controller, comprising:
a memory interface configured to interface with a memory;
an error correction code (ECC) engine configured to perform ECC coding on data stored in the memory;
a controller memory including a flash translation layer (FTL) and a key-value (KV) database; and
an electronic processor communicatively connected to the ECC engine and the controller memory, the electronic processor, when executing the FTL, is configured to:
receive data to be stored in the KV database,
separate the data into a plurality of sub-code blocks, and
allocate parity bits generated by the ECC engine to each sub-code block of the plurality of sub-code blocks.