Patent ID: 11923849
Assignee: QUALCOMM INCORPORATED
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A divide-by-N frequency divider, comprising:
a differential clock source configured to cycle a positive input clock signal and a negative input clock signal at a first frequency, wherein the negative input clock signal is a complement of the positive input clock signal;
a plurality of N latches, each latch being configured to output a corresponding pair of overlapping clock signals from 2N overlapping clock signals that cycle at a second frequency that is 1/Nth of the first frequency and have approximately a 50% duty cycle, wherein N is an integer of 3 or greater; and
a plurality of 2N logic gates configured to output 2N non-overlapping clock signals that cycle at the second frequency and have approximately a (50/N) % duty cycle, each logic gate being configured to process two of the 2N overlapping clock signals with one of the negative input clock signal and the positive input clock signal to output a corresponding one of the 2N non-overlapping clock signals at an output terminal of the logic gate.