Patent ID: 11868872
Assignee: AMAZON TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 2:
3. The neural network accelerator of claim 2, wherein the hardware processor is further configured to execute instructions associated with the second neural network operation to:
control the DMA engine to fetch a second address mapping DMA descriptor from the address mapping DMA queue and to fetch a second address mapping to the programmable address translation table based on executing the second address mapping DMA descriptor;
program the programmable address translation table based on the second address mapping;
control the DMA engine to fetch the subset of the input data DMA descriptors from the input data DMA descriptor queue, and to translate the first indirect addresses of the subset of the input data DMA descriptors to third physical addresses of the host memory via the programmable address translation table based on the second address mapping;
control the DMA engine to transfer the second input data from the third physical addresses of the host memory to the local memory based on executing the subset of the input data DMA descriptors;
perform the second neural network operation based on the second input data from the local memory to generate the second output data, and to store the second output data at the local memory;
control the DMA engine to fetch the subset of the output data DMA descriptors from the output data DMA descriptor queue, and to translate the second indirect addresses of the subset of the output data DMA descriptors to fourth physical addresses of the host memory via the programmable address translation table and based on the second address mapping; and
control the DMA engine to transfer the second output data from the local memory to the fourth physical address of the host memory based on executing the subset of the output data DMA descriptors.