Patent ID: 11921642
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. A method of operating a cache memory, comprising:
storing first information associated with a first physical address in a first cache line in a cache line array on a die, the first physical address being one of a plurality of physical addresses each comprising at least first and second non-overlapping, distinct predefined portions;
updating a first entry in one or more tables to indicate that the first cache line has been allocated to store the first information, each table of the one or more tables including a plurality of entries indexed by the first portions of the plurality of physical addresses, the first entry corresponding to the first portion of the first physical address;
in response to receiving a memory access command, including a specified physical address, using logic circuitry coupled to the one or more tables, outputting a cache hit signal upon determining whether the one or more tables include a respective table entry corresponding to the first portion of the specified physical address and storing an indication that a respective cache line corresponding to the second portion of the specified physical address has been allocated to store information associated with the specified physical address; and
forwarding to a memory controller or processor the information associated with the specified physical address stored in the cache line at a location in the cache line array specified by the second portion of the specified physical address after receiving the cache hit signal output by the logic circuitry.