Patent ID: 11948636
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 9:
10. A memory device comprising:
a stacked structure including a plurality of conductive layers stacked to be apart from each other in a first direction;
a pillar structure including a resistance change portion extending in the first direction in the stacked structure, and a semiconductor portion which extends in the first direction in the stacked structure and which includes a first portion provided along the resistance change portion and a second portion extending from the first portion in at least one direction intersecting the first direction; and
a memory string including a plurality of cell transistors each including at least a part of one of the conductive layers and a part of the semiconductor portion, and a plurality of resistance change memory elements provided to correspond to the cell transistors, respectively, and each including a part of the resistance change portion,
wherein
the memory string includes a plurality of memory cells connected in series, each of the memory cells including one of the cell transistors and one of the resistance change memory elements corresponding to the one of the cell transistors, which are connected in parallel.