Patent ID: 11921642
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. The method of claim 14, wherein:
the first entry stores a first set of address bits and a first bit vector, the first bit vector including a first plurality of bits corresponding to respective ones of a first plurality of cache lines in the cache line array, the first plurality of cache lines including the first cache line, wherein the first set of address bits correspond to a first sub-portion of the second portion of the first physical address;
updating the first entry comprises updating at least a bit corresponding to the first cache line in the first bit vector;
the respective table entry stores a second set of address bits and a second bit vector, the second bit vector including a second plurality of bits corresponding to respective ones of a second plurality of cache lines in the cache line array, the second plurality of cache lines including the respective cache line, wherein the second set of address bits correspond to a first sub-portion of the second portion of the specified physical address, and wherein the indication that information is stored in the respective cache line is based at least in part on a value of a bit corresponding to the respective cache line in the second bit vector.