Patent ID: 11889694
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 19:
20. The method of claim 17, wherein:
each of the memory opening fill structures comprises a respective vertical semiconductor channel;
the memory die further comprises first bit lines electrically connected to end portions of a respective subset of the vertical semiconductor channels located in the first memory array region and second bit lines electrically connected to end portions of a respective subset of the vertical semiconductor channels located in the second memory array region; and
the logic die further comprises first bit line drivers located in a first bit line driver region and electrically connected to the first bit lines and second bit line drivers located in a second bit line driver region and electrically connected to the second bit lines, wherein:
the first bit line driver region is located entirely within an area of the first memory array region; and
the second bit line driver region is located entirely within an area of the second memory array region.