Patent ID: 11862584
Assignee: NXP USA, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 18:
19. A method for forming a wafer-scale die packaging device, comprising:
providing a first high-k dielectric carrier substrate comprising a first glass layer surrounding a first patterned ceramic layer in which a first millimeter waveguide region is located;
forming a first array of conductors in the first high-k dielectric carrier substrate to define a conductive first waveguide interface perimeter that is positioned to substantially surround the first millimeter waveguide region, thereby forming a top carrier device from the first high-k dielectric carrier substrate and the first array of conductors;
providing a bottom carrier device comprising a second high-k dielectric carrier substrate in which a second glass layer surrounds a second patterned ceramic layer in which a second millimeter waveguide region is located, a semiconductor die attached to a top surface of the second high-k dielectric carrier substrate over a die region, and a second array of conductors formed on a top surface of the second patterned ceramic layer to define a waveguide ring positioned to substantially surround the second millimeter waveguide region and a separate excitation element positioned to extend from the die region to a first interior side of the second millimeter waveguide region to be substantially surrounded by the waveguide ring;
positioning the top carrier device and the bottom carrier device in alignment so that the first millimeter waveguide region formed in the first patterned ceramic layer of the top carrier device is aligned with the second millimeter waveguide region formed in the second patterned ceramic layer of the bottom carrier device; and
attaching the bottom carrier device to the top carrier device by applying an adhesive or bonding layer to the bottom carrier device and/or top carrier device, thereby forming the wafer-scale die packaging device.