Patent ID: 11967573
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A semiconductor structure, comprising:
a conductive line embedded in an inter-metal dielectric layer;
a first dielectric layer over the conductive line and over the inter-metal dielectric layer;
a redistribution layer (RDL) over the first dielectric layer, wherein the RDL extends through the first dielectric layer to contact the conductive line, wherein the RDL includes a curved top surface;
a conductive feature disposed over and electrically coupled to the RDL, wherein a bottom surface of the conductive feature is below the curved top surface of the RDL, and a top surface of the conductive feature is substantially leveled; and
a solder layer over the top surface of the conductive feature.