Patent ID: 11874742
Assignee: NVIDIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. A system comprising:
a parallel processing memory storing a kernel;
a parallel processor coupled to the parallel processing memory;
one or more memories storing instructions; and
one or more primary processors coupled to the one or more memories that, when executing the instructions:
determines that the kernel executing on a plurality of parallel processing elements included in the parallel processor is tagged to indicate that the kernel is enabled for intra-kernel checkpointing and restart;
causing the plurality of parallel processing elements to stop executing a first plurality of instructions included in the kernel in accordance with a context before executing a next instruction included in the kernel;
causing the parallel processor to collect state data associated with the context;
generating a checkpoint based on the state data, wherein the checkpoint is stored in the parallel processing memory; and
causing the plurality of parallel processing elements to resume executing the first plurality of instructions included in the kernel at the next instruction in accordance with the checkpoint.