Patent ID: 11929761
Assignee: SEAGATE TECHNOLOGY LLC
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A memory device storing instructions that, when executed, cause a processor to perform a method comprising:
implementing a low density parity check (LDPC) decoder configured decode a codeword of bits, including:
providing a plurality of variable-to-check (v2c) message vectors from a variable node processor to an edge combiner in parallel, the plurality of v2c message vectors including estimates for a selected set of bits of the codeword;
generating, at the edge combiner, a plurality of output message vectors for a plurality of check node vectors based on the first plurality of v2c message vectors;
providing the plurality of output message vectors from the edge combiner to the plurality of check node vectors simultaneously;
updating the plurality of check node vectors at a check node processor based on the plurality of output message vectors; and
detecting a valid code word at a convergence checker circuit based on bit value estimates from the variable node processor.