Patent ID: 11870504
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Telecommunications (Electrical engineering)
Classification: CPC G  H | IPC H

Claim 12:
13. A memory system comprising:
a first memory chip including a first pin and a second pin;
a second memory chip including a third pin; and
a translation device configured to be connected between the first memory chip and the second memory chip, wherein the translation device comprises:
a plurality of first input/output (I/O) circuits connected to the first pin and the second pin and configured to transmit and receive first signals based on a pulse amplitude modulation (PAM)-M mode;
a second I/O circuit connected to the third pin and configured to transmit and receive a second signal based on a PAM-N mode; and
a translation circuit configured to translate the first signals into the second signal and configured to translate the second signal into the first signals, and
M and N are different integers of 2 or more,
wherein the first signals are received by the first pin and the second pin, translated into the second signal by the translation circuit, and transmitted through the third pin, and
the second signal is received by the third pin, translated into the first signals by the translation circuit, and transmitted through the first pin and the second pin.