Patent ID: 11968289
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A clock data recovery circuit comprising:
a phase detector configured to output a phase adjustment signal based on a clock signal of a first node and an input signal;
a charge pump electrically connected to the phase detector and configured to adjust a charge amount of a second node according to the phase adjustment signal received from the phase detector;
a first switch electrically connected to the charge pump, a first terminal of the first switch being electrically connected to the second node and a second terminal of the first switch being electrically connected to a third node;
a capacitor including a first electrode electrically connected to the third node; and
voltage control oscillators each including a control terminal connected to the third node and an output terminal,
wherein the first switch is configured to electrically connect the charge pump to the third node.