Patent ID: 11914972
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. The data processing apparatus as claimed in claim 7, wherein the dequeuing process further comprises:
reading the content of the unique set of dequeuing slots;
writing the null data item to the unique set of dequeuing slots other than the dequeuing-target slot; and
performing an atomic compare-and-swap operation to store the null data item to the dequeuing-target slot in the ring buffer contingent on an in-order marker not being present in the dequeuing-target slot and,
when the in-order marker is present in the dequeuing-target slot, determining that the content of the unique set of dequeuing slots is being removed from the ring buffer in-order, and
when the in-order marker is not present in the dequeuing-target slot, determining that the content of the unique set of dequeuing slots is being removed from the ring buffer out-of-order and concluding the dequeuing process.