Patent ID: 11874776
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. One or more non-transitory computer-readable media comprising one or more instructions that when executed on a processor configure the processor to perform one or more operations to:
store data in memory; and
execute an instruction, at execution circuitry of the processor, to program an inline memory expansion logic and a host memory encryption logic with one or more cryptographic keys,
wherein the inline memory expansion logic is to encrypt the data to be written to the memory and to decrypt encrypted data to be read from the memory, wherein the memory is coupled to the processor via an interconnect endpoint of a system fabric, wherein the memory is to be accessed in a block mode, wherein, for a received block mode transaction in the block mode, the inline memory expansion logic is to encrypt the data or decrypt the encrypted data based at least in part on a block size of the received block mode transaction and a tweak, wherein the tweak is to be based at least in part on an address of the received block mode transaction or a nonce associated with the received block mode transaction.