Patent ID: 11954585
Assignee: ZJU-HANGZHOU GLOBAL SCIENTIFIC AND TECHNOLOGICAL INNOVATION CENTER
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 2:
3. The multi-mode array structure for in-memory computing according to claim 2, wherein each memory cell comprises a first memristor, a second memristor, a first transistor, a second transistor, and the differential amplifier; a top electrode of the first memristor and a top electrode of the second memristor are connected to the function line; a bottom electrode of the first memristor is connected to a drain electrode of the first transistor; a bottom electrode of the second memristor is connected to a drain electrode of the second transistor; a gate electrode of the first transistor is connected to the third end of the memory cell; a gate electrode of the second transistor is connected to the fourth end of the memory cell; a source electrode of the first transistor is connected to a first input end of the differential amplifier; a source electrode of the second transistor is connected to a second input end of the differential amplifier; and output ends of the differential amplifier are connected to the fifth ends of the memory cells, respectively.