Patent ID: 11881267
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A semiconductor memory device comprising:
a substrate;
a plurality of gate electrodes arranged in a first direction intersecting with a surface of the substrate;
a semiconductor layer extending in the first direction and opposed to the plurality of gate electrodes;
an electric charge accumulating layer disposed between the plurality of gate electrodes and the semiconductor layer;
a conductive layer connected to one end portion in the first direction of the semiconductor layer; and
a control circuit electrically connected to the plurality of gate electrodes and the conductive layer, wherein
the plurality of gate electrodes include:
a plurality of first gate electrodes;
a plurality of second gate electrodes farther from the conductive layer than the plurality of first gate electrodes; and
a third gate electrode disposed between the plurality of first gate electrodes and the plurality of second gate electrodes, and

the control circuit is configured to be able to perform an erase operation, wherein
the erase operation includes:
at least one-time first operation that applies a first voltage to the conductive layer;
a second operation performed after the at least one-time first operation, the second operation applying a second voltage to the third gate electrode; and
at least one-time third operation performed after the second operation, the at least one-time third operation applying a third voltage same as or larger than the first voltage to the conductive layer.