Patent ID: 11972825
Assignee: SK HYNIX INC.
Field: nan (nan)
Classification: CPC nan | IPC G  H

Claim 10:
11. A memory device comprising:
a first integrated circuit chip; and
a plurality of second integrated circuit chips stacked over the first integrated circuit chip, wherein the first and second integrated circuit chips transmit/receive data through a plurality of through electrodes formed through the first integrated circuit chip and through the plurality of second integrated circuit chips,
wherein the first integrated circuit chip comprises:
a decoding circuit configured to generate a read data strobe signal by synchronizing a read command signal with a clock, during a read operation;
a divider circuit configured to generate a divided signal by dividing the read data strobe signal;
a transmission circuit comprising a selector having first and second data inputs, a selection signal input and a data output, the selector being configured to couple one of the first and second data inputs to the data output, in response to a selection signal received at the selection signal input; and
a read driver configured to couple a data signal output from the selector to one of two data lines, which are coupled to the first data node, in response to the read data strobe signal;
the memory device additionally comprising a selection signal generation circuit configured to provide the selection signal responsive to: a test operation signal, a repair signal and a read data strobe signal.