Patent ID: 11948872
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. A semiconductor package, comprising:
a redistribution substrate;
a first semiconductor chip on a top surface of the redistribution substrate;
a plurality of bumps between the redistribution substrate and the first semiconductor chip; and
a solder terminal on a bottom surface of the redistribution substrate,
wherein the redistribution substrate includes:
an under-bump pattern;
a dielectric layer on a sidewall of the under-bump pattern;
an under-bump seed pattern between the dielectric layer and the sidewall of the under-bump pattern, the under-bump seed pattern exposing a bottom surface of the under-bump pattern;
a first redistribution pattern on the under-bump pattern, the first redistribution pattern including a first via part and a first wiring part, the first via part being between the under-bump pattern and the first wiring part; and
a second redistribution pattern on the first redistribution pattern, the second redistribution pattern including a second via part and a second wiring part,

wherein a thickness of the under-bump pattern is greater than a thickness of the first wiring part and a thickness of the second wiring part,
wherein the under-bump pattern has a central region and an edge region when viewed in plan,
wherein a first top surface at the edge region of the under-bump pattern is at a level higher than a level of a second top surface at the central region of the under-bump pattern,
wherein the bottom surface of the under-bump pattern is at a level higher than a level of a bottom surface of the dielectric layer,
wherein an angle between the bottom surface of the under-bump pattern and the sidewall of the under-bump pattern is in a range of 110° to 140°,
wherein the solder terminal is on the bottom surface of the under-bump pattern, and
wherein the under-bump pattern does not extend onto a top surface of the dielectric layer.