Patent ID: 11940874
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. The apparatus of claim 7, wherein the controller is further configured to cause the apparatus to:
receive, at the memory system, the third command comprising the third data, wherein identifying the second expected latency for performing the error control operation on the third data is based at least in part on receiving the third command;
determine whether to assign the third command to the second queue associated with the second decoder based at least in part on identifying the second expected latency for performing the error control operation on the third data; and
assign the third command to the second queue associated with the second decoder based at least in part on the second expected latency for performing the error control operation on the third data satisfying a second threshold value, wherein processing the third data is based at least in part on assigning the third command to the second queue.