Patent ID: 11967373
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 5:
6. A method of operating memory, comprising:
providing a first positive configuration pre-decoded address signal and a second positive configuration pre-decoded address signal to a NAND logic gate of pre-decoder circuitry, wherein the first positive configuration pre-decoded address signal and the second positive configuration pre-decoded address signal have a high voltage value or a low voltage value;
providing a third positive configuration pre-decoded address signal and a fourth positive configuration pre-decoded address signal to a first NOR logic gate of the pre-decoder circuitry, wherein the third positive configuration pre-decoded address signal and the fourth positive configuration pre-decoded address signal have a different high voltage value or a different low voltage value; and
providing the third positive configuration pre-decoded address signal and the fourth positive configuration pre-decoded address signal to a second NOR logic gate of the pre-decoder circuitry.