Patent ID: 11900991
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. The integrated circuit of claim 14, wherein each write unit of the plurality of write units comprises a sixth NMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor;
a source of the sixth NMOS transistor is grounded, a gate of the sixth NMOS transistor receives the write control signal, and a drain of the sixth NMOS transistor is electrically connected to a source of the seventh NMOS transistor;
a gate of the seventh NMOS transistor is electrically connected to one of the plurality of complementary global data lines, and a drain of the seventh NMOS transistor is electrically connected to one of the plurality of local data lines; and
a source of the eighth NMOS transistor is electrically connected to the one of the plurality of complementary global data lines, a gate of the eighth NMOS transistor receives the write control signal, and a drain of the eighth NMOS transistor is electrically connected to one of the plurality of complementary local data lines.