Patent ID: 11922062
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. An operating method of a controller that controls a memory device, the operating method comprising:
fetching a write command received from a host;
storing, in a buffer, write data associated with the write command;
controlling a host write operation of the write data to the memory device in response to the fetched write command and a background operation onto the memory device;
generating a completion response in response to the write command;
determining a delay amount of time when a workload of athe background operation of the is greater than a workload of the host write operation and an available capacity of the buffer is smaller than a threshold capacity;
delaying the completion response by the delay amount of time;
providing the host with the delayed completion response; and
during the delay amount of time, performing the background operation onto the memory device and the host write operation such that the workloads of the processor are reduced, and, after the delay amount of time, a next command from the host is received by the host interface,
wherein the delay amount of time is determined based on a free buffer size as the available capacity and an estimated-required buffer size, and
wherein the estimated-required buffer size is determined based on a number of commands received from the host but unfetched, a ratio of the write commands among recently fetched commands and a data size of the fetched write command.