Patent ID: 11877237
Assignee: TRISPACE TECHNOLOGIES (OPC) PVT. LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC H  G  Y | IPC G  H

Claim 0:
1. A system (100) for optimizing power consumption in Multimedia Signal Processing in mobile devices, the system (100) comprising:
a. a sensor (Mic/camera) (101) integrated in the mobile device to capture the media (speech, audio, image, video) of different resolution (sampling frequency, sample resolution in bits, frame dimensions);
b. Pre-processing modules including, but not limited to, deblocking filter, echo cancellation, noise reduction, analytics, person detect/recognition, keyword/keyframe spotting, speaker recognition (102), wherein the Pre-processing module (102) is implemented in a DSP/VLIW processor;
c. a Media codec encoder module (103) configured to compress/encode media signals for efficient transmission over wireless channels, wherein the implementation is performed on a CPU with SIMD extensions, wherein the encoded signals are transmitted via network (105);
d. a Media codec decoder module (106) configured to decompress/decode the received compressed Media signal from network (105), wherein the Media codec decoder is implemented on a CPU with SIMD extensions, wherein the Media codec decoder module (106) is present at receiving end;
e. Post-processing modules including, but not limited to deblocking filter, noise reduction, Analytics, person detect/recognition, keyword spotting/recognition, speaker recognition, (107), wherein the decoded Media samples are processed on a DSP/VLIW core;
f. the SoC is designed to have CPU with SIMD extensions and DSP/VLIW processing core to have pipelined implementation of the Multimedia Signal Processing modules between the two cores; where in the Arithmetic Logic Unit (ALU) of CPU is designed without saturation in the critical instructions, wherein the critical instruction include but not limited to Multiply and Accumulate (MAC) and shift instructions;
g. the pipelined implementation between the CPU and DSP/VLIW core is via asynchronous RPC (non-blocking) mechanism acting at block or frame level of media data; and
h. a Media renderer (108) configured to render media frame samples from post-processing module (107).