Patent ID: 11949422
Assignee: BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 5:
6. The PWM circuit according to claim 5, wherein the input unit comprises: a first register, a second register, a third register, a fourth register, a first adder, and a second adder; the selection unit comprises: a first selector, a second selector, and a third selector; and the output unit comprises: a D flip-flop, a first inverter, and a second inverter;
the first adder and the second adder are connected to the control word providing circuit and the third register, respectively, the first adder, the first register, the second register and the first selector are sequentially connected, the second adder, the third register, the fourth register and the second selector are sequentially connected, the second register is further connected to a first clock signal terminal, and the first register, the third register and the fourth register are further respectively connected to a second clock signal terminal;
the first adder is configured to: add the first target frequency control word and information stored in the third register, and store a summation result in the first register at a rising edge of a second clock signal provided by the second clock signal terminal connected to the first register; the second register is configured to: store the summation result stored in the first register at a rising edge of a first clock signal provided by the first clock signal terminal connected to the second register, and output the summation result to the first selector; the second adder is configured to: add the second target frequency control word and the information stored in the third register, and store a summation result in the third register at the rising edge of the second clock signal provided by the second clock signal terminal connected to the third register; and the fourth register is configured to: store the summation result stored in the third register at the rising edge of the first clock signal provided by the first clock signal terminal connected to the fourth register, and output the summation result to the second selector;
the first selector and the second selector are further connected to the initial pulse generation module and the third selector, respectively, and the third selector is further connected to the first clock signal terminal and a first input terminal of the D flip-flop;
the first selector is configured to: select a first candidate pulse from the plurality of initial pulses in response to the summation result output by the second register, and output the first candidate pulse to the third selector; the second selector is configured to: select a second candidate pulse from the plurality of initial pulses in response to the summation result output by the fourth register, and output the second candidate pulse to the third selector; and the third selector is configured to: select one of the first candidate pulse and the second candidate pulse as the initial candidate pulse at the rising edge of the first clock signal provided by the first clock signal terminal connected to the third selector, and output the initial candidate pulse to the D flip-flop; and
a second input terminal of the D flip-flop is connected to an output terminal of the first inverter, an input terminal of the first inverter and an input terminal of the second inverter are both connected to an output terminal of the D flip-flop, and the D flip-flop is configured to: generate the target pulse signal based on the initial candidate pulse and output the target pulse signal to the output selection sub-circuit.