Patent ID: 11892501
Assignee: CADENCE DESIGN SYSTEMS, INC.
Field: Measurement (Instruments)
Classification: CPC G | IPC G

Claim 17:
18. A method for diagnosing faults and/or defects in a fabricated integrated circuit (IC) chip, the method comprising:
generating, by an IC test engine operating on a computing platform, N-cycle at-speed test patterns for testing for candidate faults and/or defects of a first set of transition faults and/or defects of an IC design, where N is an integer greater than or equal to two;
applying, by automatic test equipment (ATE) the N-cycle at-speed test patterns to a fabricated IC chip that is based on the IC design and provides test result data characterizing application of the N-cycle at-speed test patterns to the fabricated IC chip, in which the test result data includes a set of miscompare values characterizing a difference between an expected result and a result measured by the ATE for a given N-cycle at-speed test pattern of the N-cycle at-speed test patterns;
selectively fault-simulating, by a fault simulator of a diagnostics engine operating on the computing platform, a subset of the N-cycle at-speed test patterns against a fault model that includes multicycle transition faults and/or defects utilizing sim-shifting to diagnose a second set of transition faults and/or defects in the fabricated IC chip that are only detectable with multicycle test patterns having one or more additional initialization cycles than a corresponding one of the N-cycle at-speed test patterns; and
scoring, by the diagnostics engine candidate, faults and/or defects in the first set of transition faults and/or defects and the second set of transition faults and/or defects for applicable test patterns of the subset of the N-cycle at-speed test patterns to determine a most likely fault and/or defect present in the fabricated IC chip.