Patent ID: 11915979
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A device comprising:
a semiconductor fin extending above an isolation region;
a high-k gate dielectric layer over and extending along sidewalls of the semiconductor fin, the high-k gate dielectric layer comprising fluorine; and
a gate stack over and along sidewalls of the high-k gate dielectric layer, wherein the gate stack comprises:
a first work function metal layer comprising an n-type metal and fluorine;
a capping layer over the first work function metal layer, wherein the capping layer comprises the n-type metal, and wherein a concentration of the n-type metal in the capping layer decreases in a direction away from the first work function metal layer; and
a first fill metal layer over the capping layer wherein the first fill metal layer is free of fluorine.