Patent ID: 11902149
Assignee: GRAPHCORE LIMITED
Field: Digital communication (Electrical engineering)
Classification: CPC G  H | IPC H

Claim 9:
10. A system on chip comprising circuitry configured to:
receive a sync request originating from a first one of a plurality of computing devices and being a request for coordinating a barrier synchronisation between the plurality of computing devices;
in response to receipt of the sync request, propagate two further sync requests by:
propagating a first of the two further sync requests towards a first of two different nodes; and
propagating a second of the two further sync requests towards a second of the two different nodes;

following the propagation of the two further sync requests, receive from the first of the two different nodes, a first acknowledgment of the first of the two further sync requests; and
in response to the receipt of the first acknowledgment, cause a second acknowledgment to be returned to the first one of the plurality of computing devices,
wherein the two different nodes each belong to further system on chip devices.