Patent ID: 11908797
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An integrated circuit device comprising:
a bit line on a substrate, the bit line comprising a lower conductive layer and an upper conductive layer;
an insulating capping pattern on the bit line; and
a main insulating spacer on a sidewall of the bit line and a sidewall of the insulating capping pattern, the main insulating spacer comprising an extended portion opposite the upper conductive layer, the extended portion protruding toward the upper conductive layer compared to a portion of the main insulating spacer opposite the lower conductive layer,
wherein the extended portion of the main insulating spacer fills an undercut space corresponding to a sidewall of the upper conductive layer and a bottom surface of the insulating capping pattern, and
wherein the extended portion of the main insulating spacer and the portion of the main insulating spacer opposite the lower conductive portion form a continuous portion of a common material.