Patent ID: 11876118
Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor structure, comprising:
a substrate;
a channel layer on the substrate;
a barrier layer on the channel layer;
a gate structure on the substrate, comprising:
a gate electrode on the substrate; and
a gate metal layer on the gate electrode, wherein the gate metal layer has at least one notch, and the gate metal layer exposes the gate electrode from a top view projecting the gate electrode and the gate metal layer onto the substrate, wherein in a normal direction of the substrate, a side surface of the gate electrode and a side surface of the gate metal layer are coplanar;

a dielectric layer disposed in the at least one notch of the gate metal layer;
a source structure and a drain structure on opposite sides of the gate structure, wherein the source structure and the drain structure comprise a source electrode and a drain electrode, respectively, wherein the source electrode and the drain electrode both penetrate through the barrier layer and contact the channel layer, wherein an electric potential of the gate structure is different from an electric potential of the source structure; and
a doped compound semiconductor layer disposed on the substrate, wherein a side surface of the doped compound semiconductor layer is aligned with the side surface of the gate electrode and the side surface of the gate metal layer, wherein the doped compound semiconductor layer is doped with a p-type dopant or an n-type dopant,
wherein a top surface of the source electrode is coplanar with a top surface of the gate electrode, wherein the source electrode has the top surface wider than a bottom surface, wherein a combined thickness of the gate electrode and the doped compound semiconductor layer is less than a thickness of the source electrode.