Patent ID: 11907127
Assignee: SMART IOPS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. The storage system of claim 8, wherein the first and second controllers are configured such that when the first data is written to the at least one first partition of the second non-volatile memory configured as the first cache memory for processing and the processed first data is written to the at least one first partition of the first non-volatile memory configured as the first main memory, the processed first data in the at least one first partition of the second non-volatile memory configured as the first cache memory is erased or otherwise considered erased and available to be rewritten with new data such that:
a copy of the processed first data is not retained in the at least one first partition of the second non-volatile memory configured as the first cache memory; and
a loss in the storage capacity from retaining the copy of the processed first data in the at least one first partition of the second non-volatile memory configured as the first cache memory is absent.