Patent ID: 11892502
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. An integrated circuit (IC), comprising:
a plurality of operational TSVs;
a spare TSV;
a plurality of fault-tolerance control modules, each coupled to one of the plurality of operational TSVs and the spare TSV; and
a decoder, coupled to the plurality of fault-tolerance control modules,
wherein the plurality of fault-tolerance control modules are configured to deactivate one of the plurality of operational TSVs that is determined to be defective and activate the spare TSV based on a positioning code for the defective operational TSV from the decoder,
wherein each of the plurality of fault-tolerance control modules comprises:
an input control unit, coupled to an input of one of the plurality of operational TSVs and an input of the spare TSV,
wherein the input control unit is configured to deactivate the operational TSV that is determined to be defective and activate the spare TSV based on the positioning code for the defective operational TSV from the decoder.