Patent ID: 11923286
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. The package substrate of claim 1, wherein the insulating layer further comprises:
a base insulating layer having a top surface and a bottom surface, the first upper insulating layer being provided on the top surface of the base insulating layer; and
a first lower insulating layer on the bottom surface of the base insulating layer, and
wherein the wiring pattern comprises:
an upper wiring line pattern provided on the top surface of the base insulating layer, the upper wiring line pattern and extending in a horizontal direction and being surrounded by the first upper insulating layer;
a lower wiring line pattern provided on the bottom surface of the base insulating layer in the horizontal direction and surrounded by the first lower insulating layer;
a wiring via pattern passing through the base insulating layer in the vertical direction to connect the upper wiring line pattern to the lower wiring line pattern; and
an upper pad via pattern passing through the first upper insulating layer in the vertical direction and connecting the chip bonding pad to the upper wiring line pattern.