Patent ID: 11908919
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A method, comprising:
forming a stack of a first type and a second type epitaxial layers on a semiconductor substrate, the first type and second type epitaxial layers having different material compositions and the first type and second type epitaxial layers being alternatingly disposed in a vertical direction;
patterning the stack to form a fin-shape structure;
forming a sacrificial gate structure over the fin-shape structure;
etching the fin-shape structure in a region adjacent to the sacrificial gate structure to form a recess;
laterally etching the first type epitaxial layers from the recess;
depositing a first insulating layer on lateral ends of the first type epitaxial layers;
depositing a second insulating layer on the first insulating layer, wherein material compositions of the first and second insulating layers are different;
depositing a third insulating layer on the second insulating layer, wherein material compositions of the second and third insulating layers are different, and wherein the first and third insulating layers have a same material composition;
forming an epitaxial feature in the recess and in contact with lateral ends of the second type epitaxial layers, wherein the first, second, and third insulating layers interpose the epitaxial feature and the first type epitaxial layers;
completely removing the first type epitaxial layers to release the second type epitaxial layers; and
replacing the sacrificial gate structure with a metal gate structure.