Patent ID: 11899828
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G  H

Claim 6:
7. The PUF generator of claim 1, wherein:
each column of the PUF cell array includes a bit line and a bit bar line;
each bit line is electrically connected to a drain end of a first transistor, wherein a source end of the first transistor is electrically connected to a system ground, and wherein a gate end of the first transistor is controlled by a clear signal generated by the reset circuit based on the indication of the voltage tempering event; and
each bit bar line is electrically connected to a drain end of a second transistor, wherein a source end of the second transistor is electrically connected to a logic high voltage, and wherein a gate end of the second transistor is controlled by a clear bar signal that is a reverse of the clear signal.