Patent ID: 11937470
Assignee: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 0:
1. An array substrate, comprising:
a base substrate comprising a display area and a peripheral area surrounding the display area, wherein the peripheral area comprises a first peripheral area located on one side of the display area;
a plurality of sub-pixels located at the display area;
a plurality of data lines located at the display area, electrically connected to the plurality of sub-pixels, and configured to provide a data signal to the plurality of sub-pixels;
a plurality of control signal lines located at least at the first peripheral area;
a plurality of data signal input lines located at least at the first peripheral area; and
a multiplexing circuit located at least at the first peripheral area, located on one side of the plurality of control signal lines close to the display area, and comprising a plurality of multiplexing units, wherein at least one of the plurality of multiplexing units is electrically connected to the plurality of control signal lines, a data signal input line of the plurality of data signal input lines, and at least two data lines of the plurality of data lines, and comprises a plurality of switch transistors, wherein at least one of the plurality of switch transistors comprises:
a second active layer located on one side of the base substrate,
a second gate located on one side of the second active layer away from the base substrate, and comprising a first gate portion and a second gate portion that are spaced apart and electrically connected to a control signal line of the plurality of control signal lines,
two first electrodes located on one side of the second gate away from the base substrate and electrically connected to the second active layer and the data signal input line, and
a second electrode located on one side of the second gate away from the base substrate and electrically connected to the second active layer and one of the at least two data lines, wherein an orthographic projection of the second electrode on the base substrate is located between orthographic projections of the two first electrodes on the base substrate.