Patent ID: 11916544
Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
Field: Electrical machinery, apparatus, energy (Electrical engineering)
Classification: CPC H | IPC H

Claim 20:
21. A driver system configured to drive a load, the driver system comprising:
a half bridge circuit comprising a high-side transistor and a low-side transistor, wherein the high-side transistor includes a first control terminal configured to receive a first control voltage conduct a load current flowing in a positive flow direction based on the first control voltage, and wherein the low-side transistor includes a second control terminal configured to receive a second control voltage conduct the load current flowing in a negative flow direction based on the second control voltage;
a first overcurrent monitoring circuit configured to compare a first measurement signal that is representative of the load current flowing in the positive flow direction to a first comparator threshold that corresponds to a first overcurrent threshold, generate a first fault signal in response to the first measurement signal exceeding the first comparator threshold for a first time interval, and generate a second fault signal in response to the first measurement signal exceeding the first comparator threshold for a second time interval, wherein the second time interval is greater than the first time interval;
a second overcurrent monitoring circuit configured to compare a second measurement signal that is representative of the load current flowing in the negative flow direction to a second comparator threshold that corresponds to a second overcurrent threshold, generate a third fault signal in response to the second measurement signal exceeding the second comparator threshold for a third time interval, and generate a fourth fault signal in response to the second measurement signal exceeding the second comparator threshold for a fourth time interval, wherein the fourth time interval is greater than the second time interval;
a gate driver circuit coupled to the first control terminal and the second control terminal, the gate driver circuit configured to regulate the first control voltage to drive the high-side transistor between switching states to control the load current and regulate the second control voltage to drive the low-side transistor between switching states to control the load current, wherein the gate driver circuit is configured to regulate the first control voltage to turn off the high-side transistor in response to the first overcurrent monitoring circuit generating the second fault signal and regulate the second control voltage to turn off the low-side transistor in response to the second overcurrent monitoring circuit generating the fourth fault signal; and
a current limiting circuit connected to the first control terminal and the second control terminal,
wherein, in response to the first overcurrent monitoring circuit generating the first fault signal, the current limiting circuit is configured to adjust the first control voltage to a first adjusted voltage level in order to limit the load current to a first reduced current level that is preconfigured to be greater than the first overcurrent threshold, wherein the first adjusted voltage level is sufficient to maintain the high-side transistor in an on-state, and
wherein, in response to the second overcurrent monitoring circuit generating the third fault signal, the current limiting circuit is configured to adjust the second control voltage to a second adjusted voltage level in order to limit the load current to a second reduced current level that is preconfigured to be greater than the second overcurrent threshold, wherein the second adjusted voltage level is sufficient to maintain the low-side transistor in an on-state.