Patent ID: 11960743
Assignee: INNOVATIONS IN MEMORY LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory system, comprising:
a processor in communication with a plurality of memory modules; and
a group of memory modules of the plurality of memory modules;
the processor is configured to receive data;
the processor is configured to determine redundancy data for the received data;
the processor is configured to store the received data and the redundancy data in one or more memory modules of the group of memory modules;
the processor is configured to receive a read data request; and
on a condition that a write data operation or an erase data operation prevents a read data operation on the one or more memory modules where the requested data is stored, the processor is configured to read sufficient stored data and redundancy data from other memory modules of the group of memory modules to reconstruct the requested data, without waiting for a completion of the write data operation or the erase data operation.