Patent ID: 11860748
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory test method, comprising:
obtaining an accessible space of a central processing unit of a memory to-be-tested comprising obtaining an accessible capacity, based on a capacity of the memory to-be-tested, of the memory to-be-tested and that is accessible by the central processing unit, and obtaining an address of the accessible capacity of the memory to-be-tested and accessible by the central processing unit;
obtaining an accessible space of a graphics processing unit of the memory to-be-tested comprising obtaining an accessible capacity, based on the capacity of the memory to-be-tested, of the memory to-be-tested and that is accessible by the graphics processing unit, and obtaining an address of the accessible capacity of the memory to-be-tested and accessible by the graphics processing unit; and
driving the central processing unit to run a test program based on the accessible space of the central processing unit, to access the memory to-be-tested through a bus of memory to-be-tested, wherein
when the central processing unit runs the test program, the central processing unit controls the graphics processing unit to access the memory to-be-tested based on the accessible space of the graphics processing unit through the bus of memory to-be-tested, the central processing unit and the graphics processing unit serially access the memory to-be-tested simultaneously through the bus of memory to-be-tested; and the bus of memory to-be-tested is an advanced extensible interface bus comprising a predetermined transmission path.