Patent ID: 11894062
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. The method as set forth in claim 14, wherein the plurality of word lines and a plurality of dielectric layers extend horizontally and overlay one another in an alternating fashion in a stack, the memory cells comprise annular layers including a blocking oxide layer and a charge-trapping layer extending vertically through the stack, the blocking oxide layer separating the charge-trapping layer from the each of the plurality of word lines to block charges in the charge-trapping layer from reaching each of the plurality of word lines, the memory cells connected in series between at least one drain-side select gate transistor on a drain-side of the one or more strings and connected to one of a plurality of bit lines and at least one source-side select gate transistor on a source-side of the one or more strings and connected to a source line, the method further includes neutralizing holes accumulating in charge-trapping layer adjacent the at least one dummy word line prior to the holes migrating along the charge-trapping layer toward the drain-side select gate transistors.