Patent ID: 11881860
Assignee: SK HYNIX INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. The multi-phase clock signal alignment circuit of claim 6, wherein the multi-phase clock signals are four-phase clocks signals including a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal,
wherein the second clock signal has an opposite phase to the first clock signal, the third clock signal has a phase delayed by 90 degrees from a phase of the first clock signal, and the fourth clock signal has an opposite phase to the third clock signal,
wherein the plurality of phase mixing circuits includes:
a first phase mixing circuit configured to receive the first clock signal and the second clock signal and to generate a first output clock signal and a second output clock signal, and
a second phase mixing circuit configured to receive the third clock signal and the fourth clock signal and to generate a third output clock signal and a fourth output clock signal.