Patent ID: 11870581
Assignee: INTEL CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An apparatus comprising:
a processor configured to cause an Enhanced Directional Multi-Gigabit (DMG) (EDMG) wireless communication station (STA) to:
identify a plurality of sequences of an EDMG Orthogonal Frequency Division Multiplexing (OFDM) mode, the plurality of sequences comprising a first sequence and a second sequence,
wherein the first sequence comprises a sequence [Seq1left, 176, 0, 0, 0, Seq1right, 176],
wherein Seq1left, 176={−1 −j −j +1 +j −j +1 −1 +1 −j −1 +1 −1 +1 −j −1 −1 +j +j +j −1 −1 +1 +j +j −1 −j +j −1 +1 −1 +j +1 +1 −1 +1 −j −1 −1 +j +j +j −1 −1 +j −1 −1 −j +1 −1 −j +j −j −1 +j −j +j −j −1 +j +j +1 +1 +1 +j +j +j −1 −1 −j +1 −1 −j +j −j −1 +j +j −j +j +1 −j −j −1 −1 −1 −j −j +j −1 −1 −j +1 −1 −j +j −j −1 +j −j +j −j −1 +j +j +1 +1 +1 +j +j −j +1 +1 +j −1 +1 +j −j +j +1 −j −j +j −j −1 +j +j +1 +1 +1 +j +j −1 −j −j +1 +j −j +1 −1 +1 −j −1 +1 −1 +1 −j −1 −1 +j +j +j −1 −1 −1 −j −j +1 +j −j +1 −1 +1 −j −1 −1 +1 −1 +j +1 +1 −j −j −j +1 +1},
and Seq1right, 176={−1 −j −j +1 +j −j +1 −1 +1 −j −1 +1 −1 +1 −j −1 −1 +j +j +j −1 −1 +1 +j +j −1 −j +j −1 +1 −1 +j +1 +1 −1 +1 −j −1 −1 +j +j +j −1 −1 +j −1 −1 −j +1 −1 −j +j −j −1 +j −j +j −j −1 +j +j +1 +1 +1 +j +j +j −1 −1 −j +1 −1 −j +j −j −1 +j +j −j +j +1 −j −j −1 −1 −1 −j −j −j +1 +1 +j −1 +1 +j −j +j +1 −j +j −j +j +1 −j −j −1 −1 −1 −j −j +j −1 −1 −j +1 −1 −j +j −j −1 +j +j −j +j +1 −j −j −1 −1 −1 −j −j +1 +j +j −1 −j +j −1 +1 −1 +j +1 −1 +1 −1 +j +1 +1 −j −j −j +1 +1 +1 +j +j −1 −j +j −1 +1 −1 +j +1 +1 −1 +1 −j −1 −1 +j +j +j −1 −1},

wherein the second sequence comprises a sequence [Seq2left, 176, 0, 0, 0, Seq2right, 176],
wherein Seq2left, 176={+1 −j −j −1 +j −j −1 +1 −1 −j +1 +1 −j −j −1 +j −j −1 +1 −1 −j +1 +j +1 +1 −j −1 +1 −j +j −j +1 +j −j −1 −1 +j +1 −1 +j −j +j −1 −j +1 −1 +1 +j −1 −1 −j −j −j −1 −1 +1 −1 +1 +j −1 −1 −j −j −j −1 −1 +j −j +j −1 −j −j +1 +1 +1 −j −j −j +j −j +1 +j +j −1 −1 −1 +j +j +j +1 +1 −j −1 +1 −j +j −j +1 +j −j −1 −1 +j +1 −1 +j −j +j −1 −j −1 +j +j +1 −j +j +1 −1 +1 +j −1 −1 +j +j +1 −j +j +1 −1 +1 +j −1 −j +j −j +1 +j +j −1 −1 −1 +j +j +j −j +j −1 −j −j +1 +1 +1 −j −j +1 −1 +1 +j −1 −1 −j −j −j −1 −1 +1 −1 +1 +j −1 −1 −j −j −j −1 −1},
and Seq2right, 176={−1 +j +j +1 −j +j +1 −1 +1 +j −1 −1 +j +j +1 −j +j +1 −1 +1 +j −1 +j +1 +1 −j −1 +1 −j +j −j +1 +j −j −1 −1 +j +1 −1 +j −j +j −1 −j −1 +1 −1 −j +1 +1 +j +j +j +1 +1 −1 +1 −1 −j +1 +1 +j +j +j +1 +1 +j −j +j −1 −j −j +1 +1 +1 −j −j −j +j −j +1 +j +j −1 −1 −1 +j +j −j −1 −1 +j +1 −1 +j −j +j −1 −j +j +1 +1 −j −1 +1 −j +j −j +1 +j −1 +j +j +1 −j +j +1 −1 +1 +j −1 −1 +j +j +1 −j +j +1 −1 +1 +j −1 +j −j +j −1 −j −j +1 +1 +1 −j −j −j +j −j +1 +j +j −1 −1 −1 +j +j +1 −1 +1 +j −1 −1 −j −j −j −1 −1 +1 −1 +1 +j −1 −1 −j −j −j −1 −1}; and

transmit a field of an EDMG OFDM mode Physical Layer (PHY) Protocol Data Unit (PPDU) over a channel bandwidth of 2.16 Gigahertz (GHz) based on the plurality of sequences; and

a memory to store information processed by the processor.