Patent ID: 11862733
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 13:
14. A method of manufacturing a semiconductor device, comprising:
forming a stacked structure by alternately stacking sacrificial layers and first to third channel layers, the first to third channel layers being stacked sequentially on a substrate;
removing a portion of the stacked structure extending in a first direction; forming active regions extending in the first direction by removing a portion of the substrate;
forming isolation layers between the active regions, uppermost surfaces of the isolation layers being lower than an uppermost surface of the active regions to expose sidewalls of the active regions;
forming a sacrificial gate structure extending in a second direction to intersect the active regions, on the substrate;
removing a portion of the stacked structure exposed by the sacrificial gate structure and defining a channel structure including the first to third channel layers;
forming a source/drain region on the sidewalls and an upper surface of the active regions, on at least one side of the sacrificial gate structure; and
removing the sacrificial gate structure and forming a gate structure in a region in which the sacrificial gate structure is removed,
wherein the source/drain region has first protruding points at a first level and second protruding points at a second level, higher than the first level,
the source/drain region has a first width in the second direction between the first protruding points and a second width, smaller than the first width, in the second direction between the second protruding points, and
a protruding length of the first protruding points in the second direction is controlled by and is positively correlated with a contact length of the sidewalls of the substrate and the source/drain region.