Patent ID: 11862561
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 15:
16. A method of forming a semiconductor device, the method comprising:
forming transistors over a front-side of a semiconductor substrate, the transistors comprising a first transistor, a second transistor, and a third transistor;
forming a first interconnect structure over the front-side of the semiconductor substrate, the first interconnect structure being electrically connected to the transistors;
attaching a carrier substrate over the first interconnect structure;
planarizing the semiconductor substrate to expose a silicon germanium sacrificial material, the semiconductor substrate comprising crystalline silicon;
etching the semiconductor substrate to form a recess, the recess exposing a gate dielectric material of the first transistor;
depositing a dielectric material in the recess;
planarizing the dielectric material to be level with the silicon germanium sacrificial material;
selectively etching the silicon germanium sacrificial material to expose a first epitaxial region of the first transistor and a second epitaxial region of the second transistor through a back-side of the semiconductor substrate;
forming a first back-side via to the first epitaxial region and a second back-side via to the second epitaxial region;
exposing a gate structure of the third transistor through the back-side of the semiconductor substrate;
forming a third back-side via to the gate structure of the third transistor;
forming a second interconnect structure over and electrically connected to the first back-side via, the second back-side via, and the third back-side via; and
forming an external connector over and electrically connected to the second interconnect structure.