Patent ID: 11948919
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor package, comprising:
a plurality of first semiconductor structures stacked on a package substrate, wherein the first semiconductor structures of the plurality of first semiconductor structures are offset from each other in a first direction; and
a plurality of first adhesive layers disposed between pairs of first semiconductor structures of the plurality of first semiconductor structures,
wherein each of the plurality of first semiconductor structures includes a first sub-chip and a second sub-chip in contact with a part of a top surface of the first sub-chip,
wherein each of the plurality of first adhesive layers contacts the first sub-chip, and each of the plurality of first adhesive layers is spaced apart from the second sub-chip,
wherein a thickness of each of the plurality of first adhesive layers is less than a thickness of the second sub-chip, and
wherein the thickness of the second sub-chip is in a range of about 13 μm to about 20 μm.