Patent ID: 11893360
Assignee: CEREMORPHIC, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A process for a pipelined floating point multiplier-accumulator (MAC) receiving N pairs of floating point values, each pair comprising a floating point input and a floating point coefficient, each floating point input and floating point coefficient comprising a sign bit, a plurality of mantissa bits, and a plurality of exponent bits, the process configured to operate on at least one pipeline stage register and comprising:
identifying for each of the N pairs of floating point values a maximum exponent sum (MAX_EXP) value among N sums of input exponent and coefficient exponent bits;
outputting for each of the N pairs of floating point values an exclusive OR bit value of a sign bit of an input value and a sign bit of a corresponding coefficient value to the at least one pipeline stage register;
for each of the N pairs of floating point values, forming an integer multiplication product of mantissa bits of a corresponding floating point input value and mantissa bits of a corresponding floating point coefficient value, the integer multiplication product rounded and normalized to a fewer number of bits, thereby forming a normalized multiplication result to the at least one pipeline stage register, and asserting the EXP_INC bit if the most significant bit of the integer multiplication product is 1;
for each of the N pairs of floating point values, generating an exponent difference (EXP_DIFF) value as a difference between the MAX_EXP value and the sum of an exponent of a floating point input value and an exponent of a corresponding floating point coefficient value;
when the EXP_DIFF value is 0 and the EXP_INC bit is asserted, incrementing MAX_EXP and asserting a maximum increment (MAX_INC) bit;
when the EXP_DIFF value is not 0 and the EXP_INC bit is not asserted and the MAX_INC bit is asserted, incrementing the EXP_DIFF value;
when the EXP_DIFF value is not 0 and the EXP_INC bit is asserted and the MAX_INC bit is not asserted, decrementing the EXP_DIFF value;

for each of the N pairs of floating point values, performing a padding step of padding the normalized multiplication result to a greater number of bits than a number of bits in the normalized multiplication result to form a padded value, performing a complement step of replacing the padded value with a 2s complement of the padded value if a respective sign bit for the associated pair of floating point values is 1, and performing a shift step of shifting a result of the complement step by a number EXP_DIFF of bit positions to generate an integer form fraction value;
computing a sum of N integer form fraction values;
generating a floating point result by determining a sign of the adder stage sum to generate a resulting sign part, normalizing the sum to generate a resulting mantissa part, and generating the floating point result from the resulting sign part, an exponent derived from the MAX_EXP value, and the resulting mantissa part.