Patent ID: 11907712
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A method comprising:
sending a first block of instructions to a first decode cluster comprising a plurality of decoder circuits of a processor for decoding;
sending a second block of instructions younger in program order than the first block of instructions to a second decode cluster comprising a plurality of decoder circuits of the processor for decoding; and
arbitrating access, via an arbitration circuit of the processor, by the first decode cluster and the second decode cluster to a shared read port of a microcode sequencer comprising a memory that stores a plurality of micro-operations to allow the second decode cluster decoding the second block of instructions access to the shared read port instead of the first decode cluster decoding the first block of instructions when an instruction of the second block of instructions has a number of corresponding micro-operations in the microcode sequencer below an arbitration threshold.