Patent ID: 11948659
Assignee: REEXEN TECHNOLOGY CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G

Claim 2:
3. The MAC array of claim 2, further comprising a plurality of differential computing cells each comprising a differential complementary transmission gate, a differential computing capacitor and a first PMOS transistor,
wherein in each of the computing cells in the MAC array, the output of the CMOS inverter consisting of the MOS transistors M3, M4 in each conventional 6T SRAM cell is connected to an input of a respective differential complementary transmission gate, and all the differential complementary transmission gates connected to the respective CMOS inverters each consisting of the MOS transistors M3, M4 are connected at outputs thereof to a drain of a respective first PMOS transistor, the drain of the respective first PMOS transistor is connected to a bottom plate of a respective differential computing capacitor, the respective first PMOS transistor has a source connected to VDD,
wherein differential multiplication results are stored as bottom plate voltages of the respective differential computing capacitors, and
wherein top plates of the differential computing capacitors of the differential computing cells in each column are connected to a respective differential accumulation bus.