Patent ID: 11948926
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A method comprising:
bonding a first memory die to a wafer, the wafer comprising a processor die, the first memory die comprising first conductive vias;
forming a first dielectric layer around the first memory die;
planarizing the first dielectric layer and the first memory die to expose the first conductive vias of the first memory die;
forming a first redistribution structure over the first dielectric layer and the first memory die, the first redistribution structure comprising first metallization patterns electrically coupled to the first conductive vias of the first memory die; and
sawing the first redistribution structure, the first dielectric layer and the wafer to singulate the processor die, a sidewall of the first redistribution structure being laterally coterminous with a sidewall of the first dielectric layer and a sidewall of the processor die.