Patent ID: 11902132
Assignee: INTEL CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 16:
17. A method for generating a deterministic latency for a first data path that comprises a digital-to-analog converter circuit, the method comprising:
measuring a second latency of a second data path through the first data path and a third data path, wherein the third data path comprises an analog-to-digital converter circuit;
determining a third latency of the first data path using a variable latency circuit based on a first difference between the second latency of the second data path and a fourth latency of the third data path; and
generating the deterministic latency in a first output signal of the variable latency circuit based on a second difference between a maximum latency of the first data path and the third latency of the first data path.