Patent ID: 11935611
Assignee: REALTEK SEMICONDUCTOR CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory test circuit having repair information maintaining mechanism, comprising:
a memory built-in self repair (MBISR) circuit; and
a repairing control circuit configured to control the memory built-in self repair circuit to perform a built-in self-repair procedure on a memory circuit having a redundant structure, comprising:
a remapping storage circuit disposed in a scan chain and configured to receive and store repairing information generated by the memory built-in self repair circuit after the built-in self-repair procedure is finished; and
a latch storage circuit electrically coupled between the remapping storage circuit and a remapping circuit corresponding to the memory circuit, and configured to receive and store the repairing information from the remapping storage circuit, such that the remapping circuit accesses the repairing information when the remapping storage circuit performs a scan test based on the scan chain to perform remapping and repairing on the memory circuit based on the repairing information and the redundant structure.