Patent ID: 11972121
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G

Claim 0:
1. A stacked-die memory component comprising:
an inter-die signaling path;
a base die coupled to the inter-die signaling path and having:
a first signaling interface to receive a chip-select signal, chip-identifier value and command/address value from a source external to the stacked-die memory component;
circuitry to drive the chip-identifier value onto one or more chip-identifier lines of the inter-die signaling path during a first interval and to drive the command/address value onto one or more command/address lines of the inter-die signaling path during a second interval that commences a predetermined time after the first interval;

a memory die stacked on the base die and coupled to the inter-die signaling path, the memory die having:
circuitry to receive the chip-identifier value via the one or more chip-identifier lines and to either assert or deassert a control signal according to whether the chip-identifier value matches or does not match, respectively, a resident identifier value of the memory die;
circuitry to receive the command/address value via the one or more command/address lines if the control signal is asserted and to disable reception of the command/address value if the control signal is deasserted.