Patent ID: 11887647
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. A method, comprising:
storing, in an integrated circuit device, matrices of an artificial neural network and instructions executable by an accelerator for deep learning, the accelerator having:
at least one processing unit enclosed within the integrated circuit device to implement the artificial neural network using the matrices;
a control unit
local memory; and
a memory interface, wherein the integrated circuit device has a random access memory and at least two interfaces configured to access, via a connection between the memory interface of the accelerator and the random access memory, the random access memory concurrently by at least two devices that are external to the integrated circuit device, wherein the at least two interfaces includes a first interface configured for a central processing unit that is outside of the integrated circuit device, and a second interface configured for a direct memory access controller that is outside of the integrated circuit device;

storing, into the random access memory enclosed within the integrated circuit device and via the second interface configured for the direct memory access controller, first input to the artificial neural network, wherein the random access memory configured have:
a first region configured to store the instructions and the matrices of the artificial neural network;
a second region configured to store the first inputs to the artificial neural network; and
a third region configured to store first outputs generated by the accelerator autonomously executing the instructions to process, using the matrices stored in the first region, the first inputs in the second region;

loading, by the control unit, in response to the first inputs being written into the second region, the instructions from the first region of the random access memory for execution by the at least one processing unit
generating, from execution of the instructions, the first outputs in the third region; and
providing, through the first interface and to the central processing unit outside of the integrated circuit device, the first outputs from the random access memory in the integrated circuit device.