Patent ID: 11954358
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus, comprising:
a non-volatile memory;
a volatile memory comprising a plurality of banks; and
an interface controller coupled with the non-volatile memory and the volatile memory, the interface controller comprising, for each bank of the plurality of banks of the volatile memory, a respective first buffer of a plurality of first buffers of the interface controller and a respective second buffer of a plurality of second buffers of the interface controller, the respective first buffer and the respective second buffer both assigned to the each bank of the volatile memory, both configured for data transfers involving the each bank of the volatile memory, and both having a storage capacity that is equal to a page size of the volatile memory, the interface controller operable to:
receive a command from a host device to write first data to a memory address of the non-volatile memory, the memory address of the non-volatile memory associated with a set of memory cells in a bank of the plurality of banks of the volatile memory;
store the first data, based at least in part on the command, in the respective first buffer of the interface controller that is assigned to the bank of the volatile memory;
determine, after storing the first data in the respective first buffer of the interface controller that is assigned to the bank of the volatile memory, storage information for the set of memory cells in the bank of the volatile memory;
transfer, based at least in part on determining that the set of memory cells in the bank of the volatile memory stores second data, the second data from the set of memory cells in the bank of the volatile memory to the respective second buffer of the interface controller that is assigned to the bank of the volatile memory; and
transfer, after transferring the second data from the set of memory cells in the bank of the volatile memory to the respective second buffer of the interface controller that is assigned to the bank of the volatile memory, the first data from the respective first buffer of the interface controller that is assigned to the bank of the volatile memory to the set of memory cells in the bank of the volatile memory based at least in part on the determined storage information for the set of memory cells in the bank of the volatile memory.