Patent ID: 11923840
Assignee: NXP B.V.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 6:
7. The circuit of claim 6, wherein the power down signal generator further comprises:
a current generator configured to generate a reference current based on the second supply voltage;
a first bias transistor that comprises (i) a source terminal configured to receive the second supply voltage, (ii) a gate terminal configured to receive a reference voltage that is generated based on the reference current, and (iii) a drain terminal;
a second bias transistor that comprises (i) a drain terminal coupled to the drain terminal of the first bias transistor and the gate terminal of the protection transistor, (ii) a gate terminal coupled to the drain terminal of the second bias transistor, and (iii) a source terminal; and
a third bias transistor that comprises (i) a drain terminal coupled to the source terminal of the second bias transistor and the gate terminal of the compensation transistor, (ii) a gate terminal coupled to the drain terminal of the third bias transistor, and (iii) a source terminal coupled to the ground terminal,
wherein based on the reference voltage and a size of the first bias transistor, a first scaled version of the reference current passes through the second bias transistor and the third bias transistor,
wherein based on the first scaled version of the reference current, the second bias transistor is configured to generate the second bias voltage at the drain terminal thereof and the third bias transistor is configured to generate the first bias voltage at the drain terminal thereof, and
wherein the first bias voltage is less than the second bias voltage.