Patent ID: 11888495
Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 4:
5. The analog demultiplexer circuit according to claim 1, further comprising:
a differential input/differential output type first addition circuit configured to add first output signals of the first track-and-hold circuit and second output signals of the second track-and-hold circuit; and
a differential input/differential output type second addition circuit configured to add the first output signals of the first track-and-hold circuit and the second output signals of the second track-and-hold circuit, wherein
the clock distribution circuit outputs the first clock signals and the second clock signals in the form of respective differential signals;
the first track-and-hold circuit and the second track-and-hold circuit are differential input/differential output type circuits;
the differential input/differential output type first addition circuit is configured to add a first positive-phase-side output signal of the first track-and-hold circuit and a second positive-phase-side output signal of the second track-and-hold circuit, and adds a first negative-phase-side output signal of the first track-and-hold circuit and a second negative-phase-side output signal of the second track-and-hold circuit; and
the differential input/differential output type second addition circuit is configured to add the first positive-phase-side output signal of the first track-and-hold circuit and the second negative-phase-side output signal of the second track-and-hold circuit, and adds the first negative-phase-side output signal of the first track-and-hold circuit and the second positive-phase-side output signal of the second track-and-hold circuit.