Patent ID: 11966327
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A memory system comprising:
a nonvolatile memory that includes a plurality of memory areas including at least a first memory area, a second memory area different from the first memory area, and a third memory area different from the first memory area and the second memory area; and
a memory controller configured to control the nonvolatile memory,
wherein
a read operation includes a first operation of reading data from the memory cell array and a second operation of transmitting at least a part of the read data from the nonvolatile memory to the memory controller, and
the memory controller is configured to, when executing the read operation in the first memory area, the read operation in the second memory area, and the read operation in the third memory area in parallel;
compare (A) a first total time period required for the first operation and the second operation in the first memory area, (B) a second total time period required for the first operation and the second operation in the second memory area, and (C) a third total time period required for the first operation and the second operation in the third memory area; and
increase priorities of the second operation in the first memory area, the second operation in the second memory area, and the second operation in the third memory area in descending order of the first total time period, the second total time period, and the third total time period.