Patent ID: 11871584
Assignee: KEPLER COMPUTING INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 0:
1. A device comprising:
a first region comprising:
a first conductive interconnect within a first dielectric in a first level;
a second level above the first level, the second level comprising:
an electrode structure on at least a portion of the first conductive interconnect, the electrode structure comprising:
a first conductive hydrogen barrier layer; and
a first conductive fill material adjacent to the first conductive hydrogen barrier layer;

an insulator layer laterally surrounding the electrode structure;
a memory device on least a portion of the electrode structure, the memory device comprising a ferroelectric material or a paraelectric material;
a second dielectric spanning the first region, the second dielectric comprising an amorphous, greater than 90% film density hydrogen barrier material, wherein the memory device is directly adjacent to and embedded within the second dielectric; and
a via electrode on at least a portion of the memory device, the via electrode comprising:
a second conductive hydrogen barrier layer comprising a first lateral portion in contact with the memory device;
first substantially vertical portions directly adjacent to the second dielectric; and
a second conductive fill material adjacent to the second conductive hydrogen barrier layer;

a third level above the second level, the third level comprising:
a third dielectric comprising a first less than 90% film density material, wherein the third dielectric is on the second dielectric; and
a contact electrode structure on the via electrode, the contact electrode structure comprising:
a third conductive hydrogen barrier layer comprising a second lateral portion on the via electrode and second substantially vertical portions directly adjacent to the third dielectric; and
a third conductive fill material adjacent to the second conductive hydrogen barrier layer; and

a second region adjacent to the first region, the second region comprising:
a fourth dielectric comprising a second less than 90% film density material on the insulator layer, the fourth dielectric directly adjacent to the second dielectric,
a second conductive interconnect within the first dielectric in the first level;
a third conductive interconnect within the third level, wherein the third dielectric extends over the fourth dielectric and wherein the third dielectric laterally surrounds the third conductive interconnect; and
a via structure coupled between the second conductive interconnect and the third conductive interconnect, wherein a first portion of the via structure is adjacent to the insulator layer and a second portion of the via structure is adjacent to the fourth dielectric.