Patent ID: 11948616
Assignee: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 12:
13. The manufacturing method of a semiconductor structure according to claim 12, wherein the forming a third dielectric layer, a first magnetic memory structure, a second magnetic memory structure, and a fourth dielectric layer on the second dielectric layer comprises:
forming a pair of bottom electrodes spaced apart on the second dielectric layer, the pair of bottom electrodes are used as the bottom electrode of the first magnetic memory structure and the bottom electrode of the second magnetic memory structure respectively;
forming a third dielectric layer on the second dielectric layer, wherein the bottom electrode of the first magnetic memory structure and the bottom electrode of the second magnetic memory structure are both located in the third dielectric layer;
forming a magnetic tunnel junction structure and a top electrode on the bottom electrode; and
forming a fourth dielectric layer on the third dielectric layer, wherein the fourth dielectric layer covers the bottom electrode.