Patent ID: 11901452
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. A device comprising:
a first fin structure disposed over a substrate;
a gate structure disposed over the first fin structure;
a dielectric isolation structure disposed on the substrate; and
a source/drain feature disposed over the first fin structure, the source/drain feature including:
first and second semiconductor portions that are separated from each other by the dielectric isolation structure, wherein the first semiconductor portion physically contacts the first fin structure; and
a single upper semiconductor portion disposed over the first and second semiconductor portions, wherein the single upper semiconductor portion is merged from the first and second semiconductor portions, wherein the single upper portion has a top surface facing away from a top surface of the substrate, wherein the top surface of the single upper portion includes a first multi-facet surface and a first flat surface interfacing with the first multi-facet surface, the first multi-facet surface being positioned at a higher level above the substrate than the first flat surface and the first flat surface being parallel to the top surface of the substrate, and wherein the single upper semiconductor portion and the first and second semiconductor portions are formed of the same material.