Patent ID: 11922998
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A memory device, comprising:
a memory bank including a memory cell connected to a local bit line, a local bit line bar, and a word line;
a first local data latch connected to the local bit line, the first local data latch having a first local data latch enable terminal configured to receive a first local clock signal;
a second local data latch connected to the local bit line bar, the second local data latch having a second local data latch enable terminal configured to receive the first local clock signal;
a first global data latch connected to the first local data latch by a global bit line, the first global data latch configured to receive a first data bit and having a first global data latch enable terminal configured to receive a global clock signal;
a second global data latch connected to the second local data latch by a global bit line bar, the second global data latch configured to receive a complement of the first data bit and having a second global data latch enable terminal configured to receive the global clock signal;
a first OR gate having a first input connected to an output of the first global data latch, a second input connected to an output of the second global data latch, and an output connected to the global bit line; and
a second OR gate having a first input connected to the output of the second global data latch, a second input connected to the output of the first global data latch via an inverter, and an output connected to the global bit line bar.