Patent ID: 11887666
Assignee: ZENO SEMICONDUCTOR, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 14:
15. An integrated circuit comprising:
an array of semiconductor memory cells, the array comprising:
a plurality of said semiconductor memory cells arranged in a matrix of rows and columns, wherein each of said plurality of semiconductor memory cells includes:
a first bipolar device having a first floating base region, a first collector, and a first emitter; and
a second bipolar device having a second floating base region, a second collector, and a second emitter;
wherein said first floating base region is common to said second floating base region;
wherein said first collector is common to said second collector; and
wherein states of said semiconductor memory cells are maintained upon repeated read operations;

a region having a conductivity type the same as a conductivity type of said first and second collectors, said region being electrically connected to said first and second collectors;

a control circuit configured to apply back-bias to said first and second collectors; and
a second control circuit configured to access a selected memory cell selected from said semiconductor memory cells and perform a read or write operation on said selected memory cell.