Patent ID: 11914940
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A system for manufacturing a semiconductor device comprising:
an array edge detection tool configured to determine whether a first layout design of the semiconductor device includes a set of active cells or a set of dummy cells;
a layout versus schematic (LVS) tool configured to compare a schematic design of the semiconductor device to the first layout design of the semiconductor device; and
a dummy insertion tool configured to generate a second layout design of the semiconductor device based on the first layout design and the schematic design by revising a region of the set of dummy cells when the array edge detection tool determines that the first layout design includes the set of dummy cells, or inserting the set of dummy cells between the set of active cells and an outside edge of the semiconductor device when the array edge detection tool determines that the first layout design does not include the set of dummy cells.