Patent ID: 11936409
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. The data transceiving system as claimed in claim 9, wherein the internal operating clock performs transition between a first clock level and a second clock level,
in response to the internal operating clock that is the first clock level, one end of the first capacitor is connected to the first input node to receive any one of the differential pair of the recovery voltages and the other end of the first capacitor is connected to the second input node to receive the other one of the differential pair of the recovery voltages to allow the first capacitor to store charges based on the recovery voltages, and
in response to the internal operating clock that is the second clock level, one end of the first capacitor is opened to be connected to only the output node and the other end of the first capacitor is connected to the third input node to receive the common voltage to allow the first capacitor to amplify the amplitude of the output voltage and output the amplified amplitude to the output node.