Patent ID: 11934816
Assignee: THALES DIS FRANCE SAS
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A method for generating an executable file to be loaded in a non-volatile memory of a secure element, said executable file being derived from a parent executable file, said parent executable file comprising ranges of physical addresses referencing:
a second binary code of at least a native feature which is removable from the parent executable file;
bytecodes of at least a java feature;
wherein during the generation of the derived executable file:
selecting at least one native feature from a set of native features to be removed;
defining the range of physical addresses where the second binary code of said at least one selected native feature is stored in the parent executable file;
selecting at least one java feature from a set of java features to be relocated;
in the generated derived executable file, relocating the bytecodes of said at least one selected java feature in said defined range of physical addresses according to a predefined optimization relocation algorithm.