Patent ID: 11862571
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 17:
18. A semiconductor package, comprising:
a package substrate including a first surface and a second surface facing each other;
a semiconductor chip on the first surface of the package substrate;
a capping insulation layer covering an upper surface and a side surface of the semiconductor chip;
a shielding layer covering an upper surface and a side surface of the capping insulation layer;
a mold layer covering an upper surface and a side surface of the shielding layer; and
a plurality of external connection terminals provided on the second surface of the package substrate,
wherein:
the package substrate includes a first region that vertically overlaps with the semiconductor chip and a second region that surrounds the first region,
at least some of the external connection terminals are provided on the second region of the package substrate,
the capping insulation layer has a thickness of 1 μm to 20 μm,
the shielding layer has a thickness of 1 μm to 10 μm,
the capping insulation layer includes a polymer-containing layer and insulating particles dispersed therein,
the shielding layer includes at least one metal layer,
the polymer-containing layer includes epoxy or polyurethane,
the insulating particles include silicon oxide or aluminum oxide, and
the metal layer includes stainless steel (SUS), copper, or nickel.