Patent ID: 11869590
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 9:
10. A three-dimensional NAND memory array comprising:
a string of series-connected memory cells connected between a data line and a common source;
a semiconductor pillar providing a channel region of the string of series-connected memory cells;
a first select transistor connected between the data line and the string of series-connected memory cells;
a second select transistor connected between the common source and the string of series-connected memory cells; and
a gate leakage transistor connected between the first select transistor and the second select transistor, the gate leakage transistor configured to inject holes from a gate of the gate leakage transistor to the channel region during an erase operation of the string of series-connected memory cells.