Patent ID: 11937425
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor device comprising:
gate electrodes spaced apart from each other on a substrate and stacked perpendicularly to an upper surface of the substrate;
interlayer insulating layers alternately stacked with the gate electrodes on the substrate; and
channel structures passing through the gate electrodes and extending perpendicularly to the upper surface of the substrate,
wherein each of the channel structures comprises a channel layer extending perpendicularly to the upper surface of the substrate, a tunneling insulating layer on the channel layer and extending perpendicularly to the upper surface of the substrate, charge storage layers on the tunneling insulating layer in respective regions between the gate electrodes and a side surface of the tunneling insulating layer, and first blocking insulating layers on the charge storage layers, respectively,
wherein a first layer of the first blocking insulating layers is on an entirety of an upper surface and an entirety of a lower surface of a first layer of the charge storage layers, and is further on a side surface of the first layer of the charge storage layers facing a first electrode of the gate electrodes,
wherein a height of each of the charge storage layers is less than a distance between a pair of the interlayer insulating layers that are adjacent to each other, in a first direction perpendicular to the upper surface of the substrate,
wherein second blocking insulating layers are directly on upper, lower, and side surfaces of respective ones of the gate electrodes, and
wherein the first blocking insulating layers extend between the interlayer insulating layers and the gate electrodes.