Patent ID: 11880597
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 3:
4. The read operation circuit according to claim 1, wherein each group of change flag data has N bits, the N being an integer greater than 1, wherein the data determination module is configured to output inverted data of a group of change flag data inputted as a corresponding group of global bus data and set 1-bit inversion flag data corresponding to the group of change flag data inputted to High if the number of bits of high data in the group of change flag data inputted is greater than N/2, and output a group of change flag data inputted as a corresponding group of global bus data and set 1-bit inversion flag data corresponding to the group of change flag data inputted to Low if the number of bits of the high data in the group of change flag data inputted is less than or equal to N/2.