Patent ID: 11881280
Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 6:
7. An integrated circuit, comprising:
a memory array including a plurality of memory cells;
a charge pump having an output and coupled to the memory array;
a sense current generator coupled to the output of the charge pump, wherein the sense current generator includes:
a first transistor having a source terminal coupled to ground, a gate terminal, and a drain terminal coupled to the terminal;
a plurality of sense capacitors each having a first terminal coupled to an output terminal of the charge pump and a second terminal; and
a plurality of switches each coupled between the second terminal of a respective sense capacitor the drain terminal of the first transistor and configured to enable the corresponding sense capacitor to participate in generating a sense current;
a second transistor having a source terminal coupled to ground, a gate terminal coupled to the gate terminal of the first transistor, and a drain terminal;

a reference current generator coupled between a high supply voltage and a drain terminal of the second transistor and configured to generate a reference current;
a clock generator coupled to the charge pump and including:
a current controlled oscillator having an input directly coupled to the drain terminal of the second transistor and that receives, from the drain terminal of the second transistor, a difference current corresponding to a difference between the reference current and the sense current, wherein the current controlled oscillator generates an oscillating signal with a frequency based on the different current; and
a level shifter coupled to the output of the current controlled oscillator.