Patent ID: 11860751
Assignee: SYNOPSYS, INC.
Field: Measurement (Instruments)
Classification: CPC G | IPC G

Claim 15:
16. A serializer/deserializer (SERDES)-based design for test (DFT) system, comprising:
an automated test equipment (ATE) to send test packets comprising test pattern data to a design under test (DUT) coupled to the ATE via a SERDES connection;
the DUT, comprising:
a first circuit to receive the test packets comprising the test pattern data;
a second circuit to apply the test pattern data to the DUT using a set of scan chains and obtain test response data corresponding to the test pattern data;
a third circuit to receive the test response data at irregular time intervals; and
a fourth circuit to send response packets to the ATE at regular time intervals, wherein the response packets include encoded test response data obtained by encoding a portion of the test response data; and

wherein the ATE receives the encoded test response data and compares the encoded test response data with encoded expected response data.