Patent ID: 11894277
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 15:
16. A method comprising:
forming a first gate stack over a semiconductor substrate, the first gate stack being between a first gate spacer and a second gate spacer; and
forming a second gate stack over the semiconductor substrate, the second gate stack being between the first gate spacer and the second gate spacer, wherein the first gate stack and the second gate stack are separated by a dielectric material, the dielectric material is at least partially between the first gate spacer and the second gate spacer, a first width of an upper portion of the dielectric material is greater than a second width of a lower portion of the dielectric material, and a third width of an upper portion of the first gate spacer is less than a fourth width of a lower portion of the first gate spacer.