Patent ID: 11900980
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. An apparatus, comprising:
a memory array comprising a plurality of memory cells; and
a controller coupled with the memory array and operable to cause the apparatus to:
activate a memory cell of the plurality of memory cells during a first phase of an access operation cycle;
write, at a first time of the first phase of the access operation cycle, a first state to the memory cell;
write the first state or a second state to the memory cell at a second time during the first phase of the access operation cycle different from the first time;
maintain the first state or the second state at the memory cell during a second phase of the access operation cycle after the first phase of the access operation cycle; and
precharge the memory cell during a third phase of the access operation cycle after the second phase of the access operation cycle.