Patent ID: 11907005
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G  H

Claim 17:
18. The multi-core system of claim 16, wherein the clock management circuit is configured to generate a first core strobe signal and a second core strobe signal corresponding to the first core clock signal and the second core clock signal based on the first frequency selection signal and the second frequency selection signal, respectively,
wherein the first processor core is configured to communicate with the function block by the second frequency based on the first core clock signal and the first core strobe signal,
wherein the second processor core is configured to communicate with the function block by the second frequency based on the second core clock signal and the second core strobe signal, and
wherein the function block is configured to communicate with the first processor core and the second processor core by the second frequency based on the interface clock signal.