Patent ID: 11953548
Assignee: UNIVERSITY OF FLORIDA RESEARCH FOUNDATION, INC.
Field: Measurement (Instruments)
Classification: CPC G | IPC G

Claim 8:
9. A system comprising one or more processors, a memory, and one or more programs stored in the memory, the one or more programs comprising instructions configured to cause the one or more processors to:
receive one or more key patterns for testing a design of a hardware intellectual property (IP), wherein (a) the design comprises one or more invisible scan chains and (b) each invisible scan chain comprises a plurality of flip-flops connected on-demand upon verification of the one or more key patterns;
determine a mode for the design based at least in part on the one or more key patterns and using a scan enable finite state machine (SEFSM);
responsive to determining a test mode for the design:
load a set of scan input data into the one or more invisible scan chains of the design over a first configurable number of clock cycles;
cause the design to perform a normal operation for a second configurable number of clock cycles; and
obtain a set of scan output data from the one or more invisible scan chains of the design over the first configurable number of clock cycles; and

perform one or more automated actions based at least in part on whether the set of scan output data is in accordance with an expected set of scan output data.