Patent ID: 11881254
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 4:
5. The enable control circuit according to claim 4, wherein the control circuit further comprises a 2-input OR gate, wherein
the selection circuit is further configured to generate a target achievement signal, wherein the target achievement signal indicates that the clock cycle count value reaches the target clock cycle count value; and
the 2-input OR gate is configured to perform an OR operation on the target achievement signal and a second config signal to obtain the first set signal, wherein the second config signal is generated according to a setting of a mode register (MR), and the second config signal is configured to: indicate that an ODT function of a chip is disabled when the second config signal is at a fifth level; and indicate that the ODT function of the chip is enabled when the second config signal is at a sixth level.