Patent ID: 11961891
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A method, comprising:
forming a gate dielectric layer;
forming a first work function metal layer over the gate dielectric layer;
forming a fill-metal layer over the first work function metal layer;
forming a second work function metal layer over the fill-metal layer;
performing an etch-back process on the first work function metal layer, the fill-metal layer, and the second work function metal layer, wherein after the etch-back process has been performed, a first portion of the fill-metal layer protrude vertically over the first work function metal layer and the second work function metal layer;
forming, after the performing of the etch-back process, a dielectric material over the first work function metal layer, the fill-metal layer, and the second work function metal layer, wherein the dielectric material wraps around the first portion of the fill-metal layer;
etching the dielectric material, thereby forming an opening that exposes at least side surfaces of the first portion of the fill-metal layer; and
filling the opening with a conductive gate contact, wherein the first portion of the fill-metal layer is at least partially wrapped around by the conductive gate contact.