Patent ID: 11908554
Assignee: nan
Field: Medical technology (Instruments)
Classification: CPC G  H  Y | IPC G  H

Claim 3:
4. A method comprising:
providing at least a DC-DC converter as part of an electronic circuit;
providing a low frequency oscillator for generating a low frequency clock signal;
providing a phase locked loop (PLL) which receives the low frequency clock signal and generates a high frequency PLL clock signal;
establishing a sleep signal relating to powering down an electronic circuit into a sleep mode where the sleep signal;
turning off the DC-DC converter in dependence upon the establishment of the sleep signal where the turning off of the DC-DC converter is synchronised to an edge of the low frequency clock signal;
establishing a synthesized clock counter to count the number of synthesized clock cycles between the moment the sleep signal is raised and the moment the DC-DC converter is turned off where the synthesized clock cycles are of the high frequency PLL clock signal;
retaining the value of this synthesized clock counter during the sleep mode within a sleep counter circuit forming part of the electronic circuit; and
subtracting with the sleep counter circuit a time value established in dependence upon this retained synthesized clock counter value from a predetermined delay relating to when to turn on the DC-DC converter.