Patent ID: 11955978
Assignee: BLUE CHEETAH ANALOG DESIGN, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 19:
20. A method for a circuit of a voltage comparator comprising:
receiving a first input voltage at a first gate terminal of a first transistor;
receiving a second input voltage at a second gate terminal of a second transistor;
adjusting a first common mode voltage at the first gate terminal of the first transistor comprising utilizing one or more capacitors connected between the first gate terminal of the first transistor and a second source terminal of the second transistor;
adjusting a second common mode voltage at the second gate terminal of the second transistor comprising utilizing one or more capacitors connected to the second gate terminal of the second transistor and a first source terminal of the first transistor;
amplifying with positive feedback gain the first input voltage comprising utilizing the one or more capacitors connected between the first gate terminal of the first transistor and the second source terminal of the second transistor; and
amplifying with positive feedback gain the second input voltage comprising utilizing the one or more capacitors connected to the second gate terminal of the second transistor and the first source terminal of the first transistor, wherein:
the one or more capacitors connected between the first gate terminal of the first transistor and the second source terminal of the second transistor comprises a first capacitor and a second capacitor, wherein adjusting the first common mode voltage comprises decoupling the first capacitor from between the first gate terminal of the first transistor and the second source terminal of the second transistor, and wherein amplifying with positive feedback gain the first input voltage comprises coupling the first capacitor between the first gate terminal of the first transistor and the second source terminal of the second transistor, and
the one or more capacitors connected to the second gate terminal of the second transistor and the first source terminal of first transistor comprises a third capacitor and a fourth capacitor, wherein adjusting the second common mode voltage comprises decoupling the third capacitor from between the second gate terminal of the second transistor and the first source terminal of the first transistor, and wherein amplifying with positive feedback gain the second input voltage comprises coupling the third capacitor between the second gate terminal of the second transistor and the first source terminal of the first transistor.