Patent ID: 11876063
Assignee: NANYA TECHNOLOGY CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A semiconductor package structure, comprising:
a first semiconductor wafer including a first bonding pad;
a second semiconductor wafer including a second bonding pad and a third bonding pad exposed at a first side of the second semiconductor wafer, wherein the second bonding pad and the third bonding pad are bonded to the first bonding pad of the first semiconductor wafer;
a first via extending from the first side of the second semiconductor wafer to a second side of the second semiconductor wafer, wherein the first via is in direct contact with the first bonding pad, the second bonding pad and the third bonding pad;
a first conductive line disposed in the second semiconductor wafer and away from the first side of the second semiconductor wafer; and
a second via disposed in the second semiconductor wafer and extending from the second side of the second semiconductor wafer to the first conductive line, wherein a width of the first via is greater than a width of the second via.