Patent ID: 11940470
Assignee: ALLEGRO MICROSYSTEMS, LLC
Field: Electrical machinery, apparatus, energy (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 8:
9. A substrate, comprising:
one or more first conductive layers;
one or more second conductive layers that are electrically coupled to the first conductive layers, the first conductive layers and the second conductive layers being arranged to form a conductor, the first conductive layers being arranged to define a first rift in the conductor; and
a dielectric material that is arranged to encapsulate, at least in part, the first conductive layers and the second conductive layers,
wherein the conductor includes: a first portion having the first rift formed therein, a second portion having a second rift formed therein, and a cutout that is formed between the first portion and the second portion.