Patent ID: 11956972
Assignee: WINBOND ELECTRONICS CORP.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor memory device, comprising:
a substrate comprising a memory area and a logic circuit area;
a first interlayer dielectric layer on the substrate;
a second interlayer dielectric layer on the substrate; and
an embedded memory cell structure disposed within the memory area between the first interlayer dielectric layer and the second interlayer dielectric layer, wherein the embedded memory cell structure comprises a plurality of storage elements embedded in a dielectric stack, wherein the dielectric stack comprises a lower dielectric layer, a cap layer, and an upper oxide layer, wherein the second interlayer dielectric layer comprises a first portion covering the embedded memory cell structure within the memory area, and a second portion covering the logic circuit area, wherein a top surface of the first portion is coplanar with a top surface of the second portion, wherein the first portion covers a top surface of the embedded memory cell structure, and wherein a top surface of the first portion is higher than the top surface of the embedded memory cell structure, wherein the lower dielectric layer does not extend into the logic circuit area, and the lower dielectric layer is in direct contact with the second interlayer dielectric layer.