Patent ID: 11934798
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A system comprising:
at least one memory device;
at least one memory array of a memory device;
a plurality of memory cells of the at least one memory array, the plurality of memory cells accessible via a plurality of bit lines and a plurality of word lines, wherein at least one multiplicand is stored in the memory array and at least one multiplier is stored in the memory device;
the at least one memory device being configured to:
generate a sum of the at least one multiplicand based on a plurality of popcount operations performed on the at least one multiplicand, wherein each of the plurality of popcount operations is configured to determine a total number of high bits present in a single word line of the plurality of word lines; and
generate a multiplication result based on the sum and by sequencing through bits of the multiplier.