Patent ID: 11923440
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 0:
1. A semiconductor device, comprising:
a substrate;
a dielectric isolation structure disposed on the substrate and having a horizontal upper surface;
semiconductor fins disposed on the substrate, the semiconductor fins having semiconductor fin sidewalls;
a dummy fin having dummy fin sidewalls and disposed between the dielectric isolation structure and the semiconductor fins disposed on the substrate; and
a conducting gate disposed over the semiconductor fins and the dummy fin, the conducting gate contacting the dielectric isolation structure;
wherein an angle between the horizontal upper surface of the dielectric isolation structure and an adjacent of the semiconductor fin sidewalls of the fins disposed on the substrate is greater than 90 degrees, and an angle between the horizontal upper surface of the dielectric isolation structure and an adjacent of the dummy fin sidewalls is less than 90 degrees,
wherein the dummy fin includes a first dummy fin sublayer, a second dummy fin sublayer, and a third dummy fin sublayer.