Patent ID: 11868220
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. A method, comprising:
storing, at a first latch, a first address bit associated with a memory component identified as unreliable;
storing, at a second latch, an enable bit that indicates the first latch is storing the first address bit;
performing, at a logic component coupled with the second latch and an input of a second logic component coupled with an output of the first latch, a logic operation on signals representing the enable bit and a second address bit that is associated with a memory component selected for a memory access operation; and
outputting, by the logic component, a signal representing the second address bit to the second logic component coupled with the output of the first latch based at least in part on the logic operation.