Patent ID: 11894236
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. The method for manufacturing the semiconductor structure of claim 1, wherein, the base comprises an isolation layer and a third mask layer which are stacked, in which the third mask layer has a multi-layer structure, comprising a third lower mask layer, a third middle mask layer and a third upper mask layer which are stacked; and
forming the capacitor holes comprises:
etching parts of the third upper mask layer and parts of the third middle mask layer to form a patterned third upper mask layer and a patterned third middle mask layer with the sidewall layers and the repair layers as a mask; and etching parts of the third lower mask layer with the patterned third upper mask layer and the patterned third middle mask layer as a mask to form a patterned third lower mask layer; and
etching the isolation layer with the patterned third lower mask layer as a mask to form the capacitor holes.