Patent ID: 11948877
Assignee: QUALCOMM INCORPORATED
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A method of forming a package, comprising:
forming a second metallization structure comprising:
at least one second dielectric layer; and
a second plurality of interconnects;

forming a first metallization structure such that the first metallization structure is coupled to the second metallization structure, wherein the first metallization structure comprises:
at least one first dielectric layer; and
a first plurality of interconnects;

forming a first substrate structure such that the first substrate structure is coupled to the second metallization structure,
wherein the first substrate structure is at least partially coplanar with the first substrate structure on a horizontal plane, wherein the second metallization structure touches the first metallization structure and the first substrate structure, and
wherein the first substrate structure comprises:
at least one substrate dielectric layer; and
a plurality of substrate interconnects;

forming a plurality of metal interconnects that are coupled to and touching the first metallization structure;
forming a first mold that is coupled to the first substrate structure and the first metallization structure such that the first mold is located at least between the first substrate structure and the first metallization structure; and
forming a portion that is coupled to and touching the plurality of metal interconnects, wherein the portion comprises:
at least one portion dielectric layer; and
a plurality of portion interconnects;

coupling a die to the second metallization structure,
wherein the die is configured to be electrically coupled to the first metallization structure and the first substrate structure through the second metallization structure,
wherein a first electrical path between the die and the portion includes (i) at least one interconnect from the second plurality of interconnects, (ii) at least one substrate interconnect from the plurality of substrate interconnects and (iii) at least one portion interconnect from the plurality of portion interconnects, and
wherein at least part of the first electrical path between the die and the portion extends through a first side of the first substrate structure and through a second side of the first substrate structure.