Patent ID: 11887653
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 14:
15. The memory device of claim 13,
wherein the first non-selection circuit includes a third NMOS transistor connected between the first word line and a low voltage terminal that is configured to receive the non-selection voltage, the third NMOS transistor being configured to operate in response to the first word line non-selection signal,
wherein the second non-selection circuit includes a fourth NMOS transistor connected between the second word line and the low voltage terminal, and configured to operate in response to the second word line non-selection signal,
wherein the third non-selection circuit includes a fifth NMOS transistor connected between the first word line and the low voltage terminal, and configured to operate in response to the first word line non-selection signal, and
wherein the fourth non-selection circuit includes a sixth NMOS transistor connected between the second word line and the low voltage terminal, and configured to operate in response to the second word line non-selection signal.