Patent ID: 11901183
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of forming a semiconductor device, the method comprising:
forming source/drain regions on opposing sides of a gate structure, wherein the gate structure is over a fin and surrounded by a first dielectric layer;
forming openings in the first dielectric layer to expose the source/drain regions;
performing a plasma-enhanced chemical vapor deposition (PECVD) process to selectively form silicide regions in the openings on the source/drain regions, wherein an average energy of plasmas in the PECVD process is tuned to be above a first activation energy for forming the silicide regions on the source/drain regions and below a second activation energy for forming the silicide regions on the first dielectric layer, wherein the PECVD process forms the silicide regions at bottoms of the openings on the source/drain regions but does not form a material along sidewalls of the openings; and
filling the openings with an electrically conductive material.