Patent ID: 11914532
Assignee: APPLE INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 15:
16. An apparatus, comprising:
a computer system including:
one or more processor circuits;
a communication fabric;
a memory controller configured to receive memory requests from the one or more processor circuits via the communication fabric; and
a memory system coupled to the memory controller via an interface that includes a command bus and a data bus, wherein the memory system includes a plurality of memory devices that include multiple memory banks that are accessible using activate and read/write commands, wherein the plurality of memory devices have a minimum timing delay between an activation sequence and a corresponding read/write command when accessing a given memory bank; and

wherein the memory controller is configured, in response to receiving a request for a burst memory operation to a particular one of the plurality of memory devices, to schedule, on the command bus, a sequence of read/write commands to a set of memory banks within the particular memory device such that alternating ones of the read/write commands in the sequence are scheduled to be delayed by a multi-cycle window beyond the minimum timing delay, wherein remaining read/write commands in the sequence are scheduled to not be delayed beyond the minimum timing delay.