Patent ID: 11972811
Assignee: NEO SEMICONDUCTOR, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A method for reading a NAND flash memory comprising strings of cells connected to a plurality of bit lines, wherein the plurality of bit lines are connected to a plurality of bit line select gates and a plurality of load devices, respectively, and wherein the plurality of bit line select gates are connected to a page buffer, the method comprising:
applying a read voltage to a selected word line to generate cell current;
applying load current from the load devices to the bit lines, wherein bit line voltages are generated based on ratios of the cell current and the load current for each bit line; and
selectively enabling the bit line select gates so that the page buffer senses a bit line voltage for each bit line to determine data for that bit line.