Patent ID: 11907130
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 1:
2. An apparatus comprising:
a cache comprising a plurality of cache entries;
cache access circuitry responsive to a cache access request to perform, based on a target memory address associated with the cache access request, a cache lookup operation;
tracking circuitry to track pending requests to modify cache entries of the cache; and
prediction circuitry responsive to the cache access request to make a prediction of whether the pending requests tracked by the tracking circuitry include a pending request to modify a cache entry associated with the target memory address,
wherein:
the cache access circuitry is responsive to the cache access request to determine, based on the prediction, whether to perform an additional lookup of the tracking circuitry;
the tracking circuitry comprises a store buffer to track pending store operations to store data in the cache;
the prediction circuitry comprises prediction data storage circuitry to store prediction data for use in making the prediction; and
the prediction circuitry is responsive to misses being detected following lookups, based on a given memory address, in both the cache and the store buffer to update the prediction data to indicate that a store buffer lookup need not be performed, as the additional lookup, in response to a subsequent access request associated with the given memory address.