Patent ID: 11864383
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. A vertical-type memory device, comprising:
a peripheral circuit region comprising a lower substrate and circuit devices on the lower substrate; and
a cell region on the peripheral circuit region,
wherein the cell region comprises:
a plurality of gate electrodes stacked on a substrate;
a channel layer that penetrates the plurality of gate electrodes in a first direction, perpendicular to an upper surface of the substrate;
a liner comprising a semiconductor material that is in contact with an upper internal side wall of the channel layer and includes n-type impurities; and
a pad on the liner,

wherein a bottom surface of the liner is convexly rounded toward the upper surface of the substrate,
wherein the channel layer further extends downwardly than the bottom surface of the liner, and
wherein the bottom surface of the liner is at a level between a first level of a lower surface of an uppermost first gate electrode among the plurality of gate electrodes and a second level of an upper surface of a second gate electrode directly below the first gate electrode,
a bottom surface of the pad protrudes toward the upper surface of the substrate.