Patent ID: 11907134
Assignee: RADIAN MEMORY SYSTEMS, LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 4:
5. The memory controller of claim 1 wherein:
the circuitry to map is configured to perform address translation for at least a portion of each host-provided address by identifying a selected one of plural address translation tables according to one of the first portion and the second portion, by identifying a value of a remainder portion of the provided host-provided address, and by looking up a corresponding one of the physical addresses indexed by the selected one of the plural address translation table to the value of the remainder portion; and
the circuitry to service the write requests is configured to issue one or more read commands to the nonvolatile memory responsive to the one of the read requests in a manner that specifies the corresponding one of the physical addresses.