Patent ID: 11941078
Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A computing system that uses a sparse matrix library of a multi-core processing unit to perform a set operation using one or more matrix operations offered by the multi-core processing unit, the set operation being converted into the one or more matrix operations to enable performance of the set operation by the multi-core processing unit despite the multi-core processing unit not offering the set operation in its sparse matrix library, said computing system comprising:
one or more processors; and
one or more hardware storage devices that store instructions that are executable by the one or more processors to cause the computing system to:
represent an input set as a first matrix;
select a set operation;
identify an operand associated with the set operation;
represent the operand using a second matrix;
identify a sparse matrix operation that corresponds to the set operation;
generate an output matrix by using the multi-core processing unit to perform the sparse matrix operation on the first and second matrices; and
represent the output matrix as an output set that represents a result of performing the set operation on the input set.