Patent ID: 11942144
Assignee: ALMA MATER STUDIORUM—UNIVERSITA' DI BOLOGNA
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. The in-memory computation circuit of claim 1, wherein each row includes the first word line and a second word line connected to the memory cells of the row, and each column includes the first bit line and a second bit line connected to the memory cells of the column;
wherein each memory cell comprises:
a first sub-cell connected to the first bit line and the first word line; and
a second sub-cell connected to the second bit line and the second word line; and

wherein the first word line is asserted with the word line signal pulse if the input signal coefficient data value has a positive sign and the second word line is asserted with the word line signal pulse if the input signal coefficient data value has a negative sign.