Patent ID: 11887857
Assignee: ASM IP HOLDING B.V.
Field: Semiconductors (Electrical engineering)
Classification: CPC C  H  B | IPC C  H

Claim 16:
17. A gate-all-around pmos field effect transistor comprising a threshold voltage tuning layer, the threshold voltage tuning layer being formed according to a method for forming a layer on a substrate in a reactor chamber, the method comprising the application of a deposition process comprising:
providing a first precursor to the reactor chamber, the first precursor comprising vanadium;
providing a second precursor to the reactor chamber, the second precursor comprising an element selected from a list consisting of molybdenum, tantalum, niobium, aluminum, and silicon; and
providing a reactant to the reactor chamber, the reactant comprising nitrogen;, thus forming a layer on the substrate, the layer comprising the vanadium; the layer comprising the element selected from the list consisting of molybdenum, tantalum, niobium, aluminum, and silicon; and the layer comprising the nitrogen.