Patent ID: 11899593
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus comprising:
a computer-readable memory for storage of data, the computer-readable memory comprising a first memory buffer and a second memory buffer;
an attack discovery unit device comprising processing circuitry to perform operations, comprising:
receiving a direct memory access (DMA) request from a remote device via a Peripheral Component Interconnect Express (PCIe) link, the direct memory access (DMA) request comprising a host physical address and a header indicating that the target memory address has previously been translated to a host physical address (HPA);
searching a first memory table for an address translation verified bus device (ATVBDE) entry that matches a bus device pair associated with the PCIe link and a second memory table for an entry that matches a bus concatenation of a requester ID (RID) and a translated address included in an Address Translation Services (ATS) completion message; and
blocking a direct memory access in response to a determination of at least one of: that the remote device has not obtained a valid address translation from a translation agent; or that the remote device has not obtained a valid translation for the target memory address from the translation agent.