Patent ID: 11914488
Assignee: VISA INTERNATIONAL SERVICE ASSOCIATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 7:
8. A method comprising:
analyzing, with at least one active processor node, a network system and active processor data;
comparing and analyzing two blocks from at least one data storage device to detect, with at least one active processor node, at least one failure comprising at least one of the following: an occurring or anticipated system failure, an occurring or anticipated active processor node failure, an occurring or anticipated active data storage device failure, or any combination thereof;
in response to detecting the at least one failure, issuing, with at least one processor node, a command to cause at least one of the following: a system shut down, a switch-over from a failed or anticipated to fail active processor node to a standby processor that activates as a new active processor node, a switch-over from a failed or anticipated to fail active data storage device to a standby data storage device that activates as an active data storage device, or any combination thereof; and
in response to the command, at least one of the following: configuring a third processor of a plurality of processors as a standby processor node, configuring a third data storage device among a plurality of data storage devices as a standby data storage device, or any combination thereof.