Patent ID: 11881254
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 7:
8. The enable control circuit according to claim 7, wherein the counting circuit comprises an asynchronous binary counter, the asynchronous binary counter comprises a plurality of second flip-flops, and the plurality of second flip-flops are connected in sequence;
wherein each second flip-flop of the plurality of second flip-flops is a second DFF, an input terminal (D) of each second flip-flop is connected to a second output terminal (Q-NON) of the second flip-flop, and the second output terminal (Q-NON) of the second flip-flop is connected to a clock terminal (CK) of a next second flip-flop.