Patent ID: 11869572
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A method, comprising:
providing a core supply voltage to only one power gating transistor for operating a memory array, wherein the only one power gating transistor is coupled in series between the core supply voltage and the memory array, wherein the core supply voltage refers to a positive supply voltage;
providing an applied core voltage to the memory array and a biasing stage by activating the only one power gating transistor with the biasing stage by way of a plurality of transistors arranged and coupled together to receive the applied core voltage from the only one power gating transistor, wherein the applied core voltage refers to a positive applied core voltage;
power gating the core supply voltage with the biasing stage so as to provide the applied core voltage to the memory array with the only one power gating transistor, wherein the only one power gating transistor has only one gate; and
selectively activating the only one power gating transistor with a feedback signal applied by the biasing stage by way of the plurality of transistors to the only one gate of the only one power gating transistor based on sensing a changing voltage level of the applied core voltage,
wherein the biasing stage uses a leakage current drawn from a settled voltage level of the core supply voltage as a reference current to bias the biasing stage itself for regulating the applied core voltage without comparing the applied core voltage with an additional reference voltage.