Patent ID: 11876785
Assignee: MAY PATENTS LTD.
Field: Digital communication (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A method for use with a processor in a first enclosure and a location-addressable memory in a second enclosure having an address space, the memory is connectable to the processor via a bus of a first type, the method comprising:
receiving, from the processor by a first interface via a first connector that is coupled to a first bus, a first address word in the address space, the first address word consists of a sequence of bits where each of the bits is associated with a level of significance;
converting using a one-to-one mapping, by a scrambler coupled between the first interface and a second interface, the first address word to a second address word in the address space that is distinct from the first address word, wherein the second address word consists of a sequence of bits where each of the bits is associated with a level of significance;
transmitting, to the memory by the second interface via a second connector that is coupled to a second bus, the second address word; and
powering the scrambler only by a power signal carried over the first bus,
wherein the first and second connectors, the first and second interfaces, and the scrambler are housed in a single enclosure that is separate from, and external to, each of the first and second enclosures, and
wherein the first interface or the second interface comprises a transmitter that uses a differential signaling, an emphasis shaping, and a self-clocking line-code, and a receiver coupled to the respective connector for respectively transmitting to, and receiving from, the respective bus.