Patent ID: 11901221
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. A method for forming an integrated chip, the method comprising:
depositing a first metal layer over a substrate;
depositing a hard mask layer over the first metal layer;
patterning the hard mask layer and the first metal layer to form a first metal line over the substrate, a pair of first openings on opposite sides of the first metal line, and a hard mask segment over the first metal line;
depositing a first dielectric layer in the pair of openings, over the first metal line, and over the hard mask segment to form a pair of dielectric structures in the pair of first openings;
forming a blocking layer on the hard mask segment and directly over a top surface of the first metal line;
depositing a second dielectric layer, different from the first dielectric layer, on top surfaces of the pair of dielectric structures with the blocking layer in place to form a pair of protective etch-stop structures on the top surfaces of the pair of dielectric structures;
removing the blocking layer and the hard mask segment from directly over the top surface of the first metal line;
depositing an interlayer dielectric (ILD) layer directly over the pair of protective etch-stop structures and directly over the first metal line;
patterning the ILD layer to form a second opening in the ILD layer directly over the first metal line, wherein patterning the ILD layer comprises etching the ILD layer and the pair of protective etch-stop structures, wherein the etching removes the ILD layer at a faster rate than the pair of protective etch-stop structures; and
depositing a second metal layer in the second opening to form a metal via in the second opening, directly over the first metal line, and over the pair of protective etch-stop structures, wherein the metal via is separated from a first dielectric structure of the pair of dielectric structures by a first protective etch-stop structure of the pair of protective etch-stop structures, and wherein the metal via extends along a sidewall of the first protective etch-stop structure from a top surface of the first protective etch-stop structure to the top surface of the first metal line.