Patent ID: 11889688
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 17:
18. A semiconductor device, comprising:
a substrate including a cell array region and a key region;
a stack structure on the cell array region, wherein the stack structure includes a first stack structure on the substrate and a second stack structure on the first stack structure, each of the first and second stack structures including a vertically stacked and spaced apart electrodes;
a dummy structure on the key region, wherein the dummy structure includes a first dummy structure on the substrate and a second dummy structure on the first dummy structure;
a vertical channel structure penetrating the stack structure to connect the substrate;
a dummy pillar penetrating the first dummy structure;
an interlayer dielectric layer on the stack structure and the dummy structure, wherein an upper portion of the interlayer dielectric layer on the dummy structure includes a key pattern that vertically overlaps the dummy pillar;
a capping layer on the key region and covering the key pattern; and
an upper dummy structure on a peripheral region of the substrate, wherein the peripheral region is disposed between the cell array region and the key region, and the upper dummy structure is at a same level as the second stack structure and the second dummy structure.