Patent ID: 11954582
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 18:
19. A neural network accelerator, comprising:
a first bit operator configured to generate first product bits of a multiplication of first feature bits of first input feature data and first weight bits of first weight data;
a second bit operator configured to generate second product bits of a multiplication of first feature bits of second input feature data and first weight bits of second weight data;
a third bit operator configured to generate third product bits of a multiplication of second feature bits of the first input feature data and the first weight bits of the first weight data, a multiplication of the first feature bits of the first input feature data and second weight bits of the first weight data, or a multiplication of the second feature bits of the first input feature data and the second weight bits of the first weight data;
a fourth bit operator configured to generate fourth product bits of a multiplication of second feature bits of the second input feature data and the first weight bits of the second weight data, a multiplication of the first feature bits of the second input feature data and second weight bits of the second weight data, or a multiplication of the second feature bits of the second input feature data and the second weight bits of second weight data;
a first adder configured to generate first sum bits, including a summation of the first product bits and the second product bits;
a second adder configured to generate second sum bits, including a summation of the third product bits and the fourth product bits;
a first shifter configured to generate a first bit-shifted value by first bit-shifting the first sum bits by a first bit shift extent; and
an accumulator configured to generate output feature data based on the first bit-shifted value and dependent on the second sum bits,
wherein the first bit shift extent is determined based on a first bit position of the first feature bits in the first feature data and a second bit position of the first weight bits in the first weight data.