Patent ID: 11907154
Assignee: QUALCOMM INCORPORATED
Field: Digital communication (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 24:
25. The data communication apparatus of claim 19, further comprising:
means for counting synchronization pulses, including a second counter clocked by the signal received from the one-wire bus, the means for counting synchronization pulses being configured to drive a second control input of the clock gating circuit,
wherein the second counter is held in a reset state when the one-wire bus is idle and until a sequence start condition (SSC) is detected in the signal received from the one-wire bus,
wherein the means for counting synchronization pulses is configured to halt the second counter when an expected number of synchronization pulses have been counted in the signal received from the one-wire bus, and
wherein the clock gating circuit is disabled until the second counter halts counting.