Patent ID: 11862633
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 0:
1. An integrated chip, comprising:
a first plurality of channel structures disposed over a substrate and extending in parallel between a first source/drain region and a second source/drain region, wherein the first plurality of channel structures are vertically separated from one another;
a first gate electrode layer continuously surrounding and arranged directly between the first plurality of channel structures;
a second plurality of channel structures disposed over the substrate and extending in parallel between a third source/drain region and a fourth source/drain region, wherein the second plurality of channel structures are vertically separated from one another;
a second gate electrode layer continuously surrounding and arranged directly between the second plurality of channel structures;
a third plurality of channel structures disposed over the substrate and extending in parallel between a fifth source/drain region and a sixth source/drain region, wherein the third plurality of channel structures are vertically separated from one another; and
a third gate electrode layer continuously surrounding and arranged directly between the third plurality of channel structures, wherein the third gate electrode layer laterally overlaps both the first gate electrode layer and the second gate electrode layer.