Patent ID: 11901305
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A method of fabricating a semiconductor structure, comprising:
forming a conductive feature over a substrate, wherein:
the substrate defines a product region and an alignment region, and
the conductive feature is disposed in the product region;

forming a dielectric layer in the alignment region and over the conductive feature in the product region;
forming an alignment mark layer in the alignment region;
patterning the alignment mark layer to define a first alignment mark feature in the alignment region; and
forming a bottom conductive layer, wherein:
the dielectric layer is between the bottom conductive layer and the substrate in the product region, and
the first alignment mark feature is between the bottom conductive layer and the substrate in the alignment region.