Patent ID: 11902062
Assignee: INTEL CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. An apparatus for decoding a data signal comprising a plurality of pulses of variable pulse length at predetermined positions, the apparatus comprising:
an input interface configured to receive the data signal; and
a demodulation circuit configured to:
if a respective pulse length of each of the plurality of pulses at the predetermined positions are not longer than a maximum payload data symbol pulse length defined in a communication protocol, determine that a bit value of a bit is a first value; and
if the respective pulse length of one of the plurality of pulses at the predetermined positions is longer than a maximum payload data symbol pulse length defined in the communication protocol,
determine that the bit value of the bit is a second value;

determine a position m of the pulse with the pulse length being longer than the maximum payload data symbol pulse length defined in the communication protocol among the plurality of pulses; and
determine that a symbol value of an i-th payload data symbol of a plurality of payload data symbols is ([m−i] mod z), wherein z is the number of possible symbol values of the payload data symbols defined in the communication protocol, and wherein 1≤i≤z.