Patent ID: 11880710
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus comprising:
an interface to receive an identification of a function to be executed; and
a scheduling engine comprising circuitry, the scheduling engine to select a candidate compute element from a plurality of candidate compute elements based on a combined burden, the combined burden based on an estimated burden to execute the function by the candidate compute element and an estimated burden of data movement over at least one interconnect identified for the candidate compute element;
wherein a first interconnect of the at least one interconnect identified for the candidate compute element comprises an interconnect coupled between the candidate compute element and a memory element storing input data for the function and a second interconnect of the at least one interconnect identified for the candidate compute element comprises an interconnect located within the candidate compute element.