Patent ID: 11942860
Assignee: MURATA MANUFACTURING CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A gate control circuit for a power FET in a power converter circuit, including:
(a) a level shifter including an input configured to receive a control signal and output a voltage-shifted version of the control signal to control the power FET;
(b) a gate driver circuit including:
(1) a current source coupled between a first voltage source and a node;
(2) a voltage regulator coupled to the node and configured to provide a voltage at the node;
(3) a voltage control circuit including a first selectable configuration electrically disconnected from the node, and a second selectable configuration electrically coupled to the node which lowers the voltage at the node; and
(4) a voltage supply circuit element coupled to the node and configured to provide an output voltage in response to the voltage at the node; and

(c) a buffer circuit coupled to the output of the level shifter and to the output voltage from the voltage supply circuit element, the buffer circuit configured to be coupled to a gate of the power FET, wherein the buffer circuit provides a drive voltage to the gate of the power FET having a first voltage when the voltage control circuit is in the first selectable configuration and a second, lower voltage when the voltage control circuit is in the second selectable configuration.