Patent ID: 11935925
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for manufacturing a semiconductor structure, comprising:
successively forming a first conductive layer, a second conductive layer and a passivation layer on a semiconductor substrate;
patterning the passivation layer and the second conductive layer to form a primary gate pattern, wherein a portion of the first conductive layer that is not covered by the primary gate pattern is exposed;
subjecting the primary gate pattern with plasma treatment to form a first protective layer on a side wall of the second conductive layer;
forming a dielectric layer on a side wall of the primary gate pattern and a side surface of the first protective layer;
removing the exposed portion of the first conductive layer to retain a portion of the first conductive layer covered by the primary gate pattern; and
forming a second protective layer on a side wall of the exposed portion of the first conductive layer, wherein the second protective layer and the dielectric layer serve as an isolation layer of the gate structure.