Patent ID: 11947453
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A system, comprising:
a plurality of bank groups, wherein each bank group comprises a plurality of memory banks;
a plurality of row buffers communicatively coupled to the plurality of bank groups;
a cache comprising a plurality of cache lines, wherein a size of each cache line of the plurality of cache lines is equal to a size of a row buffer of the plurality of row buffers;
a content-addressable memory (CAM) circuit to translate a specified memory address to one of: an identifier of a particular row of a particular memory bank of the plurality of memory banks or an identifier of a particular line of the cache;
a processing logic communicatively coupled to the plurality of bank groups and the plurality of row buffers, the processing logic to perform operations comprising:
receiving a read command specifying a memory address comprising a cache selector bit at a specified position within the memory address, wherein a first value of the cache selector bit indicates that the memory address references a memory location and a second value of the cache selector bit indicates that the memory address references a cache location;
translating, by the CAM circuit, based on the cache selector bit, the memory address to an identifier of a cache line of the plurality of cache lines; and
reading data from the cache line.