Patent ID: 11941394
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 18:
19. A processor comprising:
a decode unit to decode an instruction, the instruction to have at least one field to specify a source packed data register that is to have a plurality of source data elements, to have at least one field to specify a register that is to store a source packed indices operand that is to have a plurality of indices, and to have a single destination packed data register, wherein each of the indices is to correspond to a different one of the source data elements in a same relative position, wherein each of the indices is to be represented in a lowest order subset of bits of a least significant byte of an associated data element; and
an execution unit coupled with the decode unit, the execution unit to perform the instruction to store a result packed data operand in the single destination packed data register, the result packed data operand to include a plurality of result data elements, each result data element to have a value of one of the source data elements whose corresponding index indicates a data element position of the result data element in the result packed data operand, wherein the execution unit is only to store result data elements in the single destination packed data register.