Patent ID: 11886365
Assignee: APPLE INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus, comprising:
configuration storage configured to store programming information for a plurality of direct memory access (DMA) channels, wherein a transfer over a given DMA channel is between a sample buffer in a memory and a corresponding one of a plurality of peripherals via an intermediate storage buffer, and wherein the programming information for the given DMA channel includes quality of service (QoS) information for that channel that is indicative of a tolerable latency for transferring a given amount of data; and
a control circuit configured to:
control timing of data transfers between sample buffers in the memory and the intermediate storage buffer, including by generating, based on data levels of the intermediate storage buffer and the QoS information, a priority value that indicates a priority of the apparatus for accesses to the memory;
send the priority value to the memory; and
control data transfers between the intermediate storage buffer and interfaces to corresponding peripherals.