Patent ID: 11960856
Assignee: FLEX LOGIX TECHNOLOGIES, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 13:
14. An integrated circuit comprising:
a multiplier-accumulator execution pipeline to receive (i) input data and (ii) filter weights, wherein the multiplier-accumulator execution pipeline includes a plurality of multiplier-accumulator circuits to process the input data, using associated filter weights, via a plurality of multiply operations and a plurality of accumulate operations;
first memory to store the filter weights having a first data format and a first bit length;
first data format conversion circuitry, coupled to outputs of the first memory, (i) to receive the filter weights having the first data format and the first bit length, and, in operation, (ii) to convert the filter weights from the first data format and the first bit length to a Gaussian floating point data format having a second bit length;
second memory, coupled to outputs of the first data format conversion circuitry, to receive and store the filter weights having the Gaussian floating point data format and the second bit length;
second data format conversion circuitry, coupled to inputs of the multiplier-accumulator execution pipeline, including:
inputs to receive filter weights of a plurality of sets of filter weights, wherein each set of filter weights includes a plurality of associated filter weights wherein each associated filter weight includes the Gaussian floating point data format and the second bit length,
Gaussian floating point format conversion circuit, coupled to the inputs of the second data format conversion circuitry, to convert the plurality of associated filter weights of each set of filter weights from the Gaussian floating point data format and the second bit length to a data format and a bit length that are different from the Gaussian floating point data format and the second bit length, respectively, and
outputs, coupled to the inputs of the multiplier-accumulator execution pipeline, to output each filter weight having the data format and the bit length that are different from the Gaussian floating point data format and the second bit length, respectively; and

wherein, in operation, the multiplier-accumulator circuits of the multiplier-accumulator execution pipeline are configured to perform the plurality of multiply operations using (a) the input data and (b) the plurality of associated filter weights of each set of filter weights having the data format and the bit length that are different from the Gaussian floating point data format and the second bit length, respectively.