Patent ID: 11935602
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G  H

Claim 16:
17. A memory device, comprising:
an array of memory cells;
a node for connection to a signal line;
a plurality of registers, wherein one register of the plurality of registers is configured to store an expected peak current magnitude of the memory device, and wherein remaining registers of the plurality of registers are each configured to store a respective expected peak current magnitude of a respective different memory device of a grouping of memory devices containing the memory device; and
a controller for access of the array of memory cells, wherein the controller is configured to cause the memory device to:
determine whether the memory device is expecting to initiate a next phase of an access operation on the array of memory cells;
in response to determining that the memory device is expecting to initiate the next phase of the access operation:
determine whether there is sufficient first current demand budget for the grouping of memory devices to initiate the next phase of the access operation in a selected operating mode in response to at least:
the respective expected peak current magnitudes of the remaining registers of the plurality of registers; and
an expected peak current magnitude for the next phase of the access operation in the selected operating mode; and

determine whether there is sufficient second current demand budget for a subset of the memory devices, of the grouping of memory devices, containing the memory device to initiate the next phase of the access operation in the selected operating mode in response to at least:
the respective expected peak current magnitudes of the registers of the plurality of registers for memory devices of the subset of memory devices other than the memory device; and
the expected peak current magnitude for the next phase of the access operation in the selected operating mode; and

in response to determining that there is sufficient first current demand budget and sufficient second current demand budget to initiate the next phase of the access operation in the selected operating mode, output the expected peak current magnitude for the next phase of the access operation in the selected operating mode to the node and store the expected peak current magnitude for the next phase of the access operation in the selected operating mode to the one register of the plurality of registers.