Patent ID: 11928361
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory system comprising:
a controller;
a plurality of channels connected to the controller;
a non-volatile memory including a first memory area and a second memory area, each of the first memory area and the second memory area arranged to be accessed by the controller via the plurality of channels,
wherein the controller is configured to:
write data of a plurality of clusters into the first memory area via the plurality of channels based on a write command regarding sequential data from a host,
specify an order in which the data of the plurality of clusters is written based on log information,
generate order information correlating cluster identification information and writing order information based on the specified order,
read the data of the plurality of clusters from the first memory area based on a read instruction regarding an internal process,
rearrange the read data based on the order information, and
write the rearranged data into the second memory area via the plurality of channels based on a write instruction regarding the internal process.