Patent ID: 11901283
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method, comprising:
depositing a first electrode material over a first electrode routing on a semiconductor substrate;
patterning the first electrode material to form a lower metal plate having a first through hole therein;
filling a first dielectric material into the first through hole of the lower metal plate;
after filling the first dielectric material, depositing a second dielectric material over the lower metal plate;
depositing a second electrode material over the second dielectric material;
patterning the second electrode material to form a middle metal plate having a second through hole therein and having opposite straight edges, wherein the middle metal plate has a larger width than the lower metal plate, and the second through hole non-overlaps the first through hole;
filling a third dielectric material into the second through hole of the middle metal plate;
performing an etching process to form a first via hole extending through the lower metal plate and a second via hole extending through the middle metal plate and having a distance to a first one of the straight edges of the middle metal plate in a range from about 0.1 to 1 times a maximum dimension of the second via hole in a plan view, wherein the middle metal plate is spaced from the first via hole by the third dielectric material, and the lower metal plate is spaced from the second via hole by the first dielectric material; and
filling a conductive material into the first and second via holes.