Patent ID: 11968837
Assignee: SUNRISE MEMORY CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A memory structure comprising a plurality of NOR memory strings form above a planar surface of a substrate, wherein each NOR memory string comprises a plurality of memory cells sharing a common bit line and a common source line, wherein (i) each memory cell is associated with a gate electrode, (ii) the common bit line extends lengthwise along a first direction substantially parallel the planar surface, (iii) a first group of the memory cells are formed along a first side of the common bit line and (iv) a second group of the memory cells are formed along a second side of the common bit line opposite the first side, and (v) the gate electrodes of the memory cells on the first side and the gate electrodes of the memory cells on the second side are provided in a staggered configuration.