Patent ID: 11886931
Assignee: SAMBANOVA SYSTEMS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 4:
5. A data processing system, comprising:
a first reconfigurable processor operatively coupled to a first host processor running on a first processing node, the first processing node operatively coupled to a first Network Interface Controller (NIC);
a second reconfigurable processor operatively coupled to a second host processor running on a second processing node, the second processing node operatively coupled to a second NIC;
an address generator of the first reconfigurable processor configured to stream configuration data and application data for execution of configuration files that define applications from the first reconfigurable processor to the second reconfigurable processor using memory addresses that map to a first plurality of buffers; and
an address generator of the second reconfigurable processor configured to stream the configuration data and the application data from the second reconfigurable processor to the first reconfigurable processor using memory addresses that map to a second plurality of buffers;
wherein the second reconfigurable processor is configured to push output data for applications to buffers in the second plurality of buffers;
wherein the first host processor is configured to cause the first NIC to stream the output data to the first reconfigurable processor from the buffers in the first plurality of buffers; and
wherein the first host processor uses one or more Remote Direct Memory Access (RDMA) commands to update tail pointers of the buffers in the first plurality of buffers after the output data is streamed to the buffers in the first plurality of buffers.