Patent ID: 11892503
Assignee: TOSHIBA TEC KABUSHIKI KAISHA
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 15:
16. A packaged semiconductor device, comprising:
a wiring substrate;
a first semiconductor chip on the wiring substrate;
a second semiconductor chip on the wiring substrate;
a first pad on the first semiconductor chip and electrically connected to a node between a power supply pad and a ground pad on the first semiconductor chip;
a second pad on the second semiconductor chip;
a third pad on the second semiconductor chip;
an internal wiring connecting the first pad to the second pad;
a power supply circuit on the second semiconductor chip configured to supply a current to the second pad;
a switch on the second semiconductor chip between the second pad and the power supply circuit to connect or disconnect the second pad from the power supply circuit;
a control circuit on the second semiconductor chip configured to output:
a first control signal for controlling ON and OFF states of the switch in response to a test signal supplied to the third pad, and
a second control signal to the power supply circuit to cause the power supply circuit to output current; and

a sealing resin covering the first and second semiconductor chips, the internal wiring, and a first surface of the wiring substrate.