Patent ID: 11887900
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC H

Claim 14:
15. A semiconductor package comprising:
a base;
a first semiconductor chip on the base and including a first front side bonding structure, a first internal circuit structure on the first front side bonding structure, a first semiconductor substrate on the first internal circuit structure and a first back side bonding structure on the first semiconductor substrate, wherein the first semiconductor substrate is between the first back side bonding structure and the first internal circuit structure; and
a second semiconductor chip on the first semiconductor chip and including a second front side bonding structure, a second internal circuit structure on the second front side bonding structure, a second semiconductor substrate on the second internal circuit structure and a second back side bonding structure on the second semiconductor substrate,
wherein the first front side bonding structure includes a first front side insulating layer and a first front side pad,
wherein the first back side bonding structure includes a first back side insulating layer, a first back side pad and a first back side test pad,
wherein the second front side bonding structure includes a second front side insulating layer bonded to the first back side insulating layer and a second front side pad bonded to the first back side pad along planar surfaces of the first back side pad and the second front side pad that face each other,
wherein the second back side bonding structure includes a second back side insulating layer, a second back side pad and a second back side test pad,
wherein a width of the first back side test pad is greater than a width of the first back side pad,
wherein a width of the second back side test pad is greater than a width of the second back side pad,
wherein the first back side test pad does not overlap the second front side pad and
wherein the second front side bonding structure and the second internal circuit structure are between the second semiconductor substrate and the first back side bonding structure,
wherein a center of an upper surface of the first back side test pad contacts a lower surface of the second front side insulating layer.