Patent ID: 11947828
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device, comprising:
a memory array, wherein at least one first faulty cell and at least one second faulty cell that are in the memory array are configured to store data corresponding to, respectively, first and second fields of a floating-point number;
a selection circuit configured to identify the at least one first faulty cell and the at least one second faulty cell based on a priority of a cell replacement operation which indicates that a priority of the at least one first faulty cell is higher than that of the at least one second faulty cell, and further configured to determine that an address of the at least one first faulty cell matches one of a plurality of addresses of a group of memory cells to output the address of the at least one first faulty cell as a fault address, wherein the group of memory cells store data corresponding to an exponent field of the floating-point number,
wherein the selection circuit is further configured to output the fault address to a redundancy analyzer circuit that is configured to perform a replacing operation of replacing the at least one first faulty cell; and
a clipping circuit configured to output the floating-point number read out from the memory array as a read data when the floating-point number is between a first threshold value and a second threshold value smaller than the first threshold value.