Patent ID: 11948658
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. The PIM device of claim 6,
wherein the second operational logic circuit comprises:
a second multiplication circuit configured to perform a multiplication operation on the second set of the first input data and the second set of the second input data to output second multiplication data;
a second addition circuit configured to add the second multiplication data to output second addition data; and
a second accumulator configured to perform a second accumulation operation on the second addition data, and
wherein the second accumulator comprises:
a second accumulating adder configured to add the second addition data and second latch data to output second accumulation data;
a selector configured to receive the first operation result data and the second accumulation data and output one of the first operation result data and the second accumulation data as selection data; and
a second latch circuit configured to latch the selection data output from the selector to transmit latched selection data into the second accumulating adder as the second latch data.