Patent ID: 11916072
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 0:
1. A semiconductor device, comprising:
a semiconductor base portion sandwiched between a first isolation feature portion and a second isolation feature portion along a direction;
a plurality of nanostructures stacked one over another over the semiconductor base portion;
a gate structure wrapping around each of the plurality of nanostructures;
a dielectric fin disposed over the first isolation feature portion;
an isolation structure disposed over the second isolation feature portion; and
a metal layer spanning over the dielectric fin and the gate structure,
wherein the metal layer terminates at a sidewall of the isolation structure,
wherein the dielectric fin comprises a liner and a filler,
wherein the liner extends along a sidewall of the gate structure and a top surface of the first isolation feature portion and the filler is spaced apart from the gate structure and the first isolation feature portion by the liner.