Patent ID: 11972788
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus comprising:
a memory array comprising a plurality of word lines each associated with a respective row address;
a controller;
a refresh control circuit comprising a sample timing circuit configured to provide a sampling signal at an active level based on timing logic of the sample timing circuit, wherein the refresh control circuit is separate from the controller, wherein the sample timing circuit is further configured to provide the sampling signal at the active level responsive to a sampling command signal received from a different sample timing circuit included in the controller, wherein the sampling signal causes detection of a row address when the sampling signal is at the active level, and
wherein the refresh control circuit further comprises an aggressor detector circuit configured to identify an aggressor address based, in part, on the row address when the sampling signal is at the active level; and
an aggressor address storage structure configured to store first aggressor addresses identified by the aggressor detector circuit and further configured to store second aggressor addresses received from the controller, wherein the second aggressor addresses are identified as aggressor addresses by the controller.