Patent ID: 11909421
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G  Y | IPC G  H

Claim 17:
18. The MAC operator of claim 15, wherein the normalizer includes:
a floating-point moving circuit configured to receive the 22-bit first intermediate mantissa multiplication data to output the 22-bit second intermediate mantissa multiplication data obtained by moving a binary point by 1 bit toward the MSB of the first intermediate mantissa multiplication data; and
a multiplexer configured to receive the first intermediate mantissa multiplication data and the second intermediate mantissa multiplication data, and when the MSB of the first intermediate mantissa multiplication data is ‘0’ and ‘1’, output the first intermediate mantissa multiplication data and the second intermediate mantissa multiplication data, respectively, as the 22-bit mantissa of the multiplication result data of the floating-point format.