Patent ID: 11921390
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Optics (Instruments)
Classification: CPC G | IPC G

Claim 0:
1. An array substrate, comprising: a display area and a peripheral area surrounding the display area; the display area is provided with a plurality of gate lines and a plurality of data lines, the gate lines and the data lines are crossed to define a plurality of sub-pixel regions distributed in an array; the array substrate further comprises:
a first electrode, the first electrode comprising a first portion located in the display area and a second portion located in the peripheral area;
an electrode connection line, the electrode connection line is located in the peripheral area and electrically connected to the second portion, and is configured to provide a first signal for the first electrode; and
a plurality of compensation signal lines, at least part of the compensation signal lines are located in the display area, and the compensation signal lines are electrically connected to the first portion;
wherein the plurality of sub-pixel regions are divided into multiple rows of sub-pixel regions, and the compensation signal lines correspond to at least one row of sub-pixel regions in a one-to-one manner;
at least part of the compensation signal lines are located in a corresponding row of sub-pixel regions, and in the corresponding row of sub-pixel regions, the compensation signal lines are electrically connected to the first portion through at least one first via structure;
wherein, the first via structure comprises: a first via, a second via, and a first conductive pattern;
the first conductive pattern is located between the compensation signal lines and the first portion, the compensation signal lines are electrically connected to the first conductive pattern through the first via, and the first conductive pattern is electrically connected to the first portion through the second via.