Patent ID: 11923409
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 11:
12. A device, comprising:
a stack of semiconductor channels over a substrate;
a gate structure on the stack of semiconductor channels and having gate portions wrapping around each of the semiconductor channels, each of the gate portions having a same thickness;
a source/drain feature adjacent to the stack of semiconductor channels and directly contacting sidewalls of each of the semiconductor channels; and
inner spacers vertically between each of the semiconductor channels and horizontally between the gate structure and the source/drain feature, wherein the source/drain feature has concave sidewalls that form air gaps between the inner spacers and the source/drain feature,
wherein a first concave sidewall exposed in a bottommost air gap includes an apex at a mid-height of the bottommost air gap, a second concave sidewall exposed in a middle air gap above the bottommost air gap includes an apex at a mid-height of the middle air gap, and a third concave sidewall exposed in a topmost air gap above the middle air gap includes an apex at a mid-height of the topmost air gap,
wherein the third concave sidewall has a greater curvature than the second concave sidewall, and the second concave sidewall has a greater curvature than the first concave sidewall,
wherein each of the air gaps have a height less than a thickness of each of the gate portions, and the source/drain feature directly contacts a portion of the inner spacers.