Patent ID: 11862621
Assignee: TSMC NANJING COMPANY, LIMITED
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 17:
18. An integrated circuit (IC) device, comprising:
a first active region of a first semiconductor type and extending along a first axis;
a second active region of a second semiconductor type different from the first semiconductor type, and extending along the first axis; and
a plurality of gate electrodes extending along a second axis transverse to the first axis, and across the first and second active regions,
wherein
the plurality of gate electrodes and the first active region are configured as a plurality of transistors of a first type,
the plurality of gate electrodes and the second active region are configured as a plurality of transistors of a second type different from the first type,
the plurality of transistors of the first type and the plurality of transistors of the second type are electrically coupled into at least one delay circuit configured to delay an input signal at an input to generate a delayed signal at an output,
the IC device further comprises, in or over the first active region, a structure configured to change a stress on the first active region to increase a threshold voltage of the plurality of transistors of the first type and increase a time delay of the at least one delay circuit.