Patent ID: 11910732
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 15:
16. A method of forming a memory device, comprising:
forming vertical stacks of a respective lower bit line, a respective inter-bit-line dielectric rail, and a respective upper bit line;
forming a layer stack of a resistive memory material layer and a selector material layer over sidewall of the vertical stacks; and
forming word lines that laterally extend along a horizontal direction that is perpendicular to a lengthwise direction of the vertical stacks, wherein each of the word lines includes a respective horizontally-extending portion that overlie each of the vertical stacks and a respective row of downward-protruding portions that protrude downward from the respective horizontally-extending portion between neighboring pairs of the vertical stacks,, wherein:
at least one set selected from a set of the word lines, a set of the lower bit lines, and a set of the upper bit lines comprises a carbon-based conductive material containing hybridized carbon atoms in a hexagonal arrangement;
the lower bit lines comprise a first material selected from the carbon-based conductive material and a conductive material other than the carbon-based conductive material; and
the upper bit lines comprise a second material that is different from the first material and selected from the carbon-based conductive material and the conductive material other than the carbon-based conductive material.