Patent ID: 11894089
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A memory, comprising banks, each of the banks comprising a U half bank and a V half bank;
a first error checking and correcting unit connected with U half banks and V half banks and configured to check and correct errors of output data of the U half banks and the V half banks; and
a second error checking and correcting unit connected with the U half banks and the V half banks and configured to check and correct errors of output data of the U half banks and the V half banks;
wherein each of the V half banks comprises an even number of block data buses, and the block data buses are sequentially numbered from zero according to natural numbers;
wherein odd-numbered block data buses are connected with the first error checking and correcting unit, and even-numbered block data buses are connected with the second error checking and correcting unit; or the odd-numbered block data buses are connected with the second error checking and correcting unit, and the even-numbered block data buses are connected with the first error checking and correcting unit.