Patent ID: 11894084
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. A semiconductor apparatus comprising:
one or more substrates; and
logic coupled to the one or more substrates, wherein the logic is implemented in one or more of configurable logic or fixed-functionality logic hardware, the logic coupled to the one or more substrates to:
execute a margin test of a first memory storage based on a subset of first signals associated with the first memory storage;
determine, based on the margin test, first margin data to indicate whether the first memory storage complies with one or more electrical constraints; and
determine, based on the first margin data, whether to execute a signal training process to retrain a plurality of signals associated with a plurality of memory storages, wherein the plurality of memory storages includes the first memory storage.