Patent ID: 11862626
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A method of forming an electrostatic discharge (ESD) protection device comprising:
forming a field effect transistor transistor on a semiconductor substrate in a front-end-of-line (FEOL) layer during an FEOL process;
forming a metal interconnect layer on top of the FEOL layer during a back-end-of-line (BEOL) process,
wherein the metal interconnect layer is configured to interconnect the FET to a plurality of components formed on the semiconductor substrate;
forming a power delivery network (PDN) under the semiconductor substrate in a backside layer during a backside back-end-of-line (B-BEOL) process; and
forming a through substrate resistive component between the FEOL layer and a B-BEOL layer,
wherein a first contact of the through substrate resistive component is connected to a drain terminal of the FET and a second contact of the through substrate resistive component is connected, through the PDN, to a power supply rail.