Patent ID: 11888487
Assignee: REALTEK SEMICONDUCTOR CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A device, comprising:
a digital controller circuit; and
a phase interpolator electrically coupled to the digital controller circuit and including:
a plurality of circuit branches electrically coupled to an output node and controlled by the digital controller circuit to generate an n-th phase clock of N phase clocks between a first input clock and a second input clock, wherein the n-th phase clock serves as an output clock, N is an integer greater than 1, and n is an integer from 1 to N;

wherein each of the plurality of circuit branches includes a first current source and a second current source electrically coupled in series between a supply voltage and a ground voltage, the output node is electrically coupled between the first current source and the second current source, and the phase interpolator further includes a capacitive circuit electrically coupled between the output node and the ground voltage;
wherein a quantity of the plurality of circuit branches is greater than or equal to N×M, M is an integer greater than or equal to 1, and when the digital controller circuit controls the circuit branches to generate the n-th phase clock, the digital controller circuit controls, in response to appearances of rising edges of the first input clock, the plurality of circuit branches to charge the capacitive circuit with (N−n+1)×M ones of the first current source, and the digital controller circuit controls, in response to appearances of rising edges of the second input clock, the plurality of circuit branches to charge the capacitive circuit with N×M ones of the first current source.