Patent ID: 11923329
Assignee: nan
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A semiconductor die assembly, comprising:
a first semiconductor die having a major surface with non-overlapping first and second regions;
a second semiconductor die spaced apart from the first semiconductor die;
an array of first pillars extending from the first region of the major surface of the first semiconductor die to the second semiconductor die and electrically coupling the first and second semiconductor dies; and
an array of second pillars extending from the second region of the major surface of the first semiconductor die toward the second semiconductor die, wherein the second pillars are electrically insulated from one or both of the first and second semiconductor dies,
wherein—
a minimum lateral spacing between the first pillars is different than a minimum lateral spacing between the second pillars by at least 5%, or
an average width of the first pillars is different than an average width of the second pillars by at least 2%.