Patent ID: 11942956
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 14:
15. A calibrator included in a digital phase-locked loop circuit, the calibrator configured to calibrate a loop filter input signal of a time-to-digital converter outputting the loop filter input signal based on an analog to digital conversion, the calibrator comprising,
an offset lookup table generation circuit configured to receive the loop filter input signal and generate a plurality of offset lookup tables that offset an error between an ideal digital code value and a nonlinear digital code value over time of the loop filter input signal;
a gain-corrected analog-to-digital conversion output generator circuit configured to generate a gain-corrected analog-to-digital conversion output that offsets a difference between a first gain having the ideal digital code value and a second gain with the nonlinear digital code value; and
a first adder configured to generate a calibrated analog-to-digital conversion output by calibrating an analog-to-digital conversion output by adding the offset lookup table and the gain-corrected analog-to-digital conversion output,

wherein the calibrator is configured to output the calibrated analog-to-digital conversion output to the time-to-digital converter for calibrating the loop filter input signal using the calibrated analog-to-digital conversion output.