Patent ID: 11909421
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G  Y | IPC G  H

Claim 6:
7. The MAC operator of claim 6, wherein the first bit supplier is configured to:
transmit a 5-bit exponent and a 10-bit mantissa of the 16-bit input data to the first input terminal of the first 4:1 demultiplexer and the first input terminal of the second 4:1 demultiplexer, respectively, in response to a first mode register setting signal indicating the first data type;
transmit a 6-bit exponent and a 9-bit mantissa of the 16-bit input data to the second input terminal of the first 4:1 demultiplexer and the second input terminal of the second 4:1 demultiplexer, respectively, in response to a second mode register setting signal indicating the second data type;
transmit a 7-bit exponent and an 8-bit mantissa of the 16-bit input data to the third input terminal of the first 4:1 demultiplexer and the third input terminal of the second 4:1 demultiplexer, respectively, in response to a third mode register setting signal indicating the third data type; and
transmit an 8-bit exponent and a 7-bit mantissa of the 16-bit input data to the fourth input terminal of the first 4:1 demultiplexer and the fourth input terminal of the second 4:1 demultiplexer, respectively, in response to a fourth mode register setting signal indicating the fourth data type.