Patent ID: 11934964
Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 18:
19. In an integrated circuit having a regular expression engine, a method, comprising:
receiving a DFA NRA graph, the received graph including a plurality of nodes connected by directional arcs, wherein:
each arc representing transitions between nodes based on criteria specified for the respective arc,
the plurality of nodes including nodes, including a skip node and a root node, representing states in the regular expression operation, and
the directional arcs include an arc from the skip node to the root node;

selecting a stream of data units;
beginning at the root node in the plurality of nodes of the received DFA car NFA graph, stepping a regular expression engine through one or more nodes of the graph until the regular expression engine arrives at the skip node;
if the skip node is configured to consume on match, consuming, at the skip node, a predefined number of data units from the selected stream of data units before traversing the arc from the skip node to the root node, wherein the predefined number of data units is provided by a counter used to detect an end of a payload; and
if the skip node is configured to not consume on match, traversing the arc from the skip node to the root node.