Patent ID: 11968817
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A method, comprising:
forming a first gate structure, a second gate structure, a source/drain and dielectric materials disposed over the source/drain and between the first gate structure and the second gate structure;
forming a patterned mask layer over the first gate structure, the second gate structure, the source/drain, and the dielectric materials, the patterned mask layer defining an opening;
extending the opening vertically downwards through the dielectric materials, wherein portions of the source/drain and the first gate structure are exposed by the opening;
depositing a protection layer in the opening, wherein portions of the protection layer are deposited on the exposed portions of the source/drain and the first gate structure;
removing the patterned mask layer, wherein the protection layer protects portions of the source/drain and the first gate structure from being damaged during the removing of the patterned mask layer;
removing the protection layer, thereby exposing the portions of the source/drain and the first gate structure; and
filling the opening with a conductive material.