Patent ID: 11875844
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A static random access memory (SRAM) device comprising:
a memory cell array including a plurality of memory cells arranged in rows and columns, wherein each of the plurality of memory cells is connected with one of a plurality of word lines and one of a plurality of bit lines; and
control logic including a clock generator configured to generate a first internal clock, a first tracking circuit configured to track a number of the rows and a number of the columns based on the first internal clock and to generate a first signal, and a second tracking circuit configured to track the number of the rows and the number of the columns based on the first internal clock and to generate a second signal,
wherein the first tracking circuit includes:
a first wire including a first capacitor corresponding to a length of the memory cells in a column direction;
a second wire including a first resistor corresponding to the length of the memory cells in the column direction; and
a third wire including a second capacitor and a second resistor each corresponding to a length of the memory cells in a row direction,
wherein the first wire and the second wire are identical to a wire through which a power supply voltage is supplied to the plurality of memory cells, and
wherein the control logic is configured to
generate a pulse for controlling a write operation of the SRAM device based on the first signal, and
generate a pulse for controlling a read operation of the SRAM device based on the second signal.