Patent ID: 11929412
Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A semiconductor device comprising:
a substrate;
a first insulating layer over the substrate;
a second insulating layer over the first insulating layer;
a semiconductor layer over the second insulating layer;
a third insulating layer over the semiconductor layer;
a first gate electrode over the third insulating layer;
a fourth insulating layer over the first gate electrode;
a first conductive layer functioning as one of a source and a drain of a transistor and being electrically connected to the semiconductor layer; and
a second conductive layer functioning as the other of the source and the drain of the transistor and being electrically connected to the semiconductor layer,
wherein, in a cross-sectional view in a channel width direction, an entire top surface of the second insulating layer is covered by a bottom surface of the fourth insulating layer, a bottom surface of the semiconductor layer, and a bottom surface of the third insulating layer.