Patent ID: 11899607
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A method comprising:
performing an operation that requires a coordination agent to send, as a response to a single input request received from a requesting agent coupled to an interconnect, a request to each of a plurality of target agents selected for the operation from agents coupled to the interconnect, and receive a response from each of the plurality of target agents, the operation being unable to complete until the response has been received from each of the plurality of target agents, and the interconnect providing communication paths between the agents coupled to the interconnect;
storing, for each agent that the coordination agent may communicate with via the interconnect, a latency indication for communication between that agent and the coordination agent; and
prior to performing the operation, determining a sending order in which to send the request to each of the plurality of target agents, the sending order being determined in dependence on the latency indication for each of the plurality of target agents;
wherein:
the operation comprises a maintenance operation, and the request comprises a request to perform a maintenance action in respect of a respective microarchitectural structure for each of the target agents; and
the maintenance operation comprises a cache maintenance operation, the respective microarchitectural structure for each of the target agents comprises a target cache, and the maintenance action comprises one of:
invalidating at least one entry in the respective target cache for each of the target agents; and
updating data stored in the at least one entry.