Patent ID: 11925015
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A vertical memory device comprising:
a plurality of first cell gate lines spaced apart from one another in a vertical direction on a substrate;
a plurality of second cell gate lines spaced apart from one another in the vertical direction on the substrate, the plurality of second cell gate lines being laterally spaced apart from the plurality of first cell gate lines;
a contact plug interposed between the plurality of first cell gate lines and the plurality of second cell gate lines, the contact plug comprising an inner sidewall delimiting a recessed region;
a buried film pattern in a portion of the recessed region, the buried film pattern being formed of a Si-containing material;
a contact overlying the buried film pattern, the contact comprising an inner contact portion disposed in the recessed region; and
a separation film pattern having a first insulating portion interposed between the plurality of first cell gate lines and the contact plug, and a second insulating portion interposed between the plurality of second cell gate lines and the contact plug,
wherein the inner contact portion of the contact has a sidewall in contact with the inner sidewall of the contact plug, and
wherein a bottom surface of the inner contact portion is in contact with a top surface of the buried film pattern within the recessed region.