Patent ID: 11875040
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. A semiconductor system comprising:
a controller configured to:
generate a command and an address for performing a row hammering tracking operation; and
generate the command and the address for performing a tracking write operation on a bank on which the tracking write operation of the row hammering tracking operation has not been performed based on a logic level of a flag signal when a row address that is included in the address does not have the same logic level combination or for performing a precharge operation on the bank on which the tracking write operation has been performed; and

a semiconductor device including the bank and a row hammering storage circuit, the semiconductor device configured to:
store, in the row hammering circuit, an active number of the bank that is counted by performing the tracking write operation of the row hammering tracking operation; and
perform the precharge operation on the bank based on the command.