Patent ID: 11954347
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A memory system comprising:
a plurality of memory devices; and
a first core unit configured to manage a first superblock comprising memory blocks included in each of the plurality of memory devices,
wherein the first core unit:
searches for a first unstable memory region of the first superblock, by performing a first search operation on a first memory block in a first memory device of the plurality of memory devices; and
performs a recovery operation on a first candidate unstable memory region of the first superblock included in a second memory device, wherein the first search operation is not performed on the second memory device, and wherein the first candidate unstable memory region is expected to be unstable based on the first unstable memory region, and
wherein the first unstable memory region is a memory region on which a last write operation is performed in the first memory block before an abnormal event occurs.