Patent ID: 11921623
Assignee: SECURED-IC SAS
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A device for testing a bit sequence generated by a Random Number Generator, wherein the device is configured to apply one or more statistical tests to the bit sequence, in response the detection of N bits generated by the Random number generator, each statistical test being configured to test randomness in said N bits generated by the Random number generator, each statistical test providing at least one sum value derived from the bits of said sequence, a statistical test comprising several runs, a run having a length k, wherein the testing device comprises:
a comparator for comparing at least one test parameter related to each statistical test to a threshold;
a validation unit configured to determine if said bit sequence is valid depending on the comparison made by the comparator for said each statistical test;
wherein said at least one test parameter is a parameter related to the statistical test and determined from N and from a target error probability, and
wherein the test parameter is the integer part of the length of a run.