Patent ID: 11869867
Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 2:
3. A semiconductor device according comprising:
a single die pad having a first surface and a second surface that is an opposite side of the first surface, the die pad being made of a metal or a metal alloy;
a signal lead that is arranged next to the die pad in plan view;
a plurality of leads that are arranged around the die pad in plan view;
a semiconductor chip that is mounted on the second surface;
a plurality of bonding wires connecting a signal pad of the semiconductor chip and the signal lead and connecting the semiconductor chip and at least one of the plurality of leads; and
a mold resin covering the die pad, the signal lead, the plurality of leads, the semiconductor chip, and the plurality of bonding wires;
wherein an interval between the signal lead and the die pad is narrower than an interval between the plurality of leads and the die pad.