Patent ID: 11875153
Assignee: NEXT SILICON LTD
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. The system of claim 1, wherein the dataflow graph comprises a plurality of nodes and a plurality of edges;
wherein the at least one identified operation is represented in the dataflow graph by at least one identified node of the plurality of nodes;
wherein the at least one hardware processor is further configured for identifying in the dataflow graph a sub-graph (residual sub-graph) such that the residual sub-graph consists of a subset of nodes of the plurality of nodes and a subset of edges of the plurality of edges, where no path exists in the dataflow graph between any two of the at least one identified node, where for each node of the subset of nodes no path exists in the dataflow graph between the at least one identified node and the node, and where for each edge of the subset of edges no path exists in the dataflow graph between the at least one identified node and the edge; and
wherein the at least one runtime context value is at least one edge value of at least one of the subset of edges.