Patent ID: 11966310
Assignee: MELLANOX TECHNOLOGIES, LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An Integrated Circuit (IC), comprising:
one or more functional hardware circuits;
one or more processor cores, to handle events occurring in the one or more functional hardware circuits;
a cause-tree circuit to deliver the events from the one or more functional hardware circuits to the one or more processor cores for handling, the cause-tree circuit comprising leaf nodes, middle nodes and a root node, the leaf nodes comprising storage elements to collect the events from the one or more functional hardware circuits, and the middle nodes comprising coalescing circuits to coalesce the collected events and to deliver the events to the root node;
a memory buffer coupled to the root node of the cause-tree circuit, the memory buffer to buffer a plurality of the events delivered to the root node, so as to trigger the processor cores to handle the buffered events; and
a buffer analysis circuit, to analyze a performance of the cause-tree circuit based on the events buffered in the memory buffer.