Patent ID: 11960408
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. The semiconductor memory device of claim 17, wherein:
the first upper sub-latch blocks and the first lower sub-latch blocks intersect a first bit line set,
the second upper sub-latch blocks and the second lower sub-latch blocks intersect a second bit line set,
each of the first and second bit line sets includes eight bit lines extending in the column direction,
even bit lines of the bit lines are electrically connected to the common column decoder block of the first page buffer pair and the common column decoder block of the third page buffer pair, and
odd bit lines of the bit lines are electrically connected to the common column decoder block of the second page buffer pair and the common column decoder block of the fourth page buffer pair.