Patent ID: 11955511
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for manufacturing a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises an array area and a peripheral area adjacent to each other, and the array area comprises a buffer area connected to the peripheral area;
forming a first dielectric layer, a first supporting layer, a second dielectric layer, a second supporting layer and a third dielectric layer, which are successively stacked onto one another, on the substrate, wherein the first supporting layer is arranged at least in the peripheral area, the first dielectric layer is arranged between the first supporting layer and the substrate, the second dielectric layer covers the first supporting layer and the substrate, and each of the second supporting layer and the third dielectric layer is arranged in the array area and the peripheral area;
forming a groove-type lower electrode, which at least penetrates through the third dielectric layer and the second supporting layer, in the buffer area, wherein a bottom surface of the groove-type lower electrode is located in the first dielectric layer or in the second dielectric layer;
removing the third dielectric layer through a wet etching process; and
etching the second supporting layer in the peripheral area after removing the third dielectric layer.