Patent ID: 11916125
Assignee: nan
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 15:
16. A method, comprising:
receiving a workpiece comprising:
a substrate,
a sacrificial layer over the substrate, and
a stack over the sacrificial layer, the stack comprising a plurality of first semiconductor layers interleaved by a plurality of second semiconductor layers;

patterning the stack, the sacrificial layer and a portion of the substrate into a fin-shaped structure having a drain region, a source region, and a channel region disposed between the drain region and the source region;
forming a dummy gate stack over the channel region;
etching the drain region and the source region to form a drain trench and a source trench, respectively;
after the etching of the drain region and the source region, selectively extending the source trench through the sacrificial layer to form an extended source trench;
protecting end surfaces of the plurality of second semiconductor layers with a plurality of inner spacer features;
replacing the sacrificial layer with a bottom dielectric layer;
forming a source feature in the extended source trench and a drain feature in the drain trench;
replacing the dummy gate stack with a metal gate structure;
removing the substrate to expose the source feature; and
forming a backside metal feature to electrically couple to the source feature.