Patent ID: 11953966
Assignee: META PLATFORMS TECHNOLOGIES, LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A system, comprising:
a systolic array including a plurality of processing elements arranged in at least two dimensions, a first dimension corresponding to rows, and a second dimension corresponding to columns, wherein inputs to the systolic array include a separate input stream of input values at each column; and
a clock distribution network through which a root clock signal is distributed to the plurality of processing elements, wherein the clock distribution network includes a clock gate controller, and wherein the clock gate controller is configured to:
pass the root clock signal as a gated clock signal from which local clock signals are derived for processing elements in a first column of the systolic array,
at each clock cycle, check whether a most recent value input to the first column from a corresponding input stream is zero, and
disable the gated clock signal based on detecting that the most recent value input to the first column is zero.