Patent ID: 11868221
Assignee: ADVANCED MICRO DEVICES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 18:
19. A system, including:
a plurality of counters;
a cache memory configured to store a plurality of test sets and a plurality of non-test sets; and
a cache controller configured to:
store performance events for the plurality of test sets in the plurality of counters, wherein the performance events comprise misses in the plurality of test sets, the performance events including a miss count for each test set, the storing including decrementing all miss counts in response to at least one miss count arriving at a maximum value;
detect a replacement policy change trigger event associated with a test set of the plurality of test sets, wherein detecting the replacement policy trigger event comprises detecting that a count associated with misses for a test set of the plurality of test sets is lower than counts associated with misses for each other test set of the plurality of test sets, wherein the count is stored in the plurality of counters; and
in response to the replacement policy change trigger event, operate the plurality of non-test sets according to a replacement policy associated with the test set, wherein the replacement policy is selected based on the miss counts for each test set.