Patent ID: 11948638
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. The method of claim 11, further comprising:
applying, to a first subset of bit lines of a plurality of bit lines that are coupled with the first tier of memory cells by the plurality of pillars, a first sequence of voltages during the first duration, the second duration, the third duration, or a combination thereof, wherein the at least one memory cell of the first subset of the first tier of memory cells thresholds and is written to the first logic state based at least in part on applying the first sequence of voltages; and
applying, to a second subset of bit lines of the plurality of bit lines, a second sequence of voltages during the first duration, the second duration, the third duration, or a combination thereof, wherein the at least one memory cell of the second subset of the first tier of memory cells thresholds and is written to the second logic state based at least in part on applying the second sequence of voltages.