Patent ID: 11972802
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A semiconductor memory system comprising:
a plurality of semiconductor memory chips including:
a first semiconductor memory chip having a first data input/output terminal, a first control signal input/output terminal and a first clock signal generator, and
a second semiconductor memory chip having a second data input/output terminal, a second control signal input/output terminal and a second clock signal generator;

a first common signal line connected to the first data input/output terminal of the first semiconductor memory chip and the second data input/output terminal of the second semiconductor memory chip; and
a second common signal line connected to the first control signal input/output terminal of the first semiconductor memory chip and the second control signal input/output terminal of the second semiconductor memory chip,
wherein the first semiconductor memory chip performs an operation specified by a command signal communicated through the first common signal line under timings specified by a clock signal communicated through the second common signal line.