Patent ID: 11907716
Assignee: INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A method for vector reading-writing, applied to a predetermined vector-register system, comprising:
by a vector-register controller, obtaining a vector-operation instruction sent by a processor, wherein the vector-operation instruction comprises a vector-writing instruction and/or a vector-reading instruction;
when the vector-operation instruction is the vector-writing instruction, by the vector-register controller, converting a to-be-written-vector address space in the vector-writing instruction into a to-be-written-vector-register-file bit address;
by a nonstandard-vector converting unit, obtaining a to-be-written standard vector of first preset length and width sent by a vector processing unit, and when a received first converting instruction sent by the vector-register controller indicates that a valid vector in the to-be-written vector is a nonstandard vector, converting the to-be-written standard vector into a to-be-written nonstandard vector; and
by a vector-register file, obtaining the to-be-written-vector-register-file bit address, and storing the to-be-written nonstandard vector into the to-be-written-vector-register-file bit address; and
when the vector-operation instruction is the vector-reading instruction, according to a to-be-read width and a to-be-read length that correspond to the vector-reading instruction, by the vector-register controller, converting a to-be-read-vector address space in the vector-reading instruction into a to-be-read-vector-register-file bit address, wherein the to-be-read width is a standard width or a nonstandard width, and the to-be-read length is a standard length or a nonstandard length; and
by the vector-register file, obtaining the to-be-read-vector-register-file bit address, and outputting a to-be-read vector corresponding to the to-be-read-vector-register-file bit address.