Patent ID: 11864393
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 19:
20. The method of claim 19, further comprising:
depositing an insulating layer over the stepwise structure;
forming a plurality of via structures in the insulating layer over the stepwise structure, the plurality of via structures having different heights and electrically coupled correspondingly to the plurality of electrode layers,
wherein in said forming the plurality of second transistors, a first source/drain of each of the plurality of second transistors is formed over and in electrical contact with an upper end of a corresponding via structure among the plurality of via structures;

forming a bit line over the plurality of second transistors, the bit line electrically coupled to second source/drains of the plurality of second transistors; and
forming a plurality of select bit lines over the plurality of second transistors, the plurality of select bit lines electrically coupled correspondingly to gates of the plurality of second transistors.