Patent ID: 11862221
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. An apparatus, comprising:
a memory array comprising a plurality of memory cells; and
circuitry coupled with the memory array and configured to cause the apparatus to:
determine to perform an imprint recovery procedure on at least a portion of the memory array;
bias a memory cell of the plurality, during a first duration of a voltage pulse, with a first voltage magnitude having a voltage polarity based at least in part on determining to perform the imprint recovery procedure;
reduce the biasing of the memory cell, during a second duration of the voltage pulse after the first duration, from the first voltage magnitude to a second voltage magnitude having the voltage polarity; and
hold the biasing of the memory cell, during a third duration of the voltage pulse after the second duration, at the second voltage magnitude having the voltage polarity.