Patent ID: 11880215
Assignee: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH
Field: Control (Instruments)
Classification: CPC G | IPC G

Claim 9:
10. A method of controlling a digital comparator that is coupled to a pair of pull-up resistors and a pair of pull-down resistors whereby both pairs of resistors are coupled to a gate terminal of an output stage, the method comprising:
detecting, using a single-edge detector stage, a first rising edge in a received first digital signal, and a first falling edge in a received second digital signal, whereby when the first rising edge is detected and when the first falling edge is not simultaneously detected, setting a detector node to a low voltage level, and when the first falling edge is detected, setting the detector node to a high voltage level;
detecting, using a consecutive two-edge detector stage coupled to the single-edge detector stage, a voltage level of the detector node, a consecutive second rising edge in the received first digital signal and a consecutive second falling edge in the received second digital signal,
whereby when the consecutive second rising edge is detected and when the voltage level of the detector node is simultaneously detected to be at the low voltage level, causing one of the pair of pull-up resistors to pull up a voltage at the gate terminal, and
when the consecutive second falling edge is detected and when the voltage level of the detector node is simultaneously detected to be at the high voltage level, causing one of the pair of pull-down resistors to pull down the voltage at the gate terminal;

detecting, a consecutive three-edge detector stage coupled to the single-edge and the consecutive two-edge detector stages, the voltage level of the detector node, a consecutive third rising edge in the received first digital signal and a consecutive third falling edge in the received second digital signal,
whereby when the consecutive third rising edge is detected and when the voltage level of the detector node is simultaneously detected to be at the low voltage level, causing the other one of the pair of pull-up resistors to pull up the voltage at the gate terminal, and
when the consecutive third falling edge is detected and when the voltage level of the detector node is simultaneously detected to be at the high voltage level, causing the other one of the pair of pull-down resistors to pull down the voltage at the gate terminal.