Patent ID: 11942178
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. The circuit of claim 9, further comprising:
a third device series coupled between the first and second data lines, wherein the third device series comprises a third NMOS capacitor coupled between fifth and sixth switching devices;
a fourth device series coupled between the first and second data lines, wherein the fourth device series comprises a fourth NMOS capacitor coupled between seventh and eighth switching devices;
a ninth switching device coupled between the second terminal of the first NMOS capacitor and a first terminal of the third NMOS capacitor; and
a tenth switching device coupled between the second terminal of the second NMOS capacitor and a first terminal of the fourth NMOS capacitor,
wherein
the first NMOS transistor is coupled between a second terminal of the third NMOS capacitor and the ground node,
the second NMOS transistor is coupled between a second terminal of the fourth NMOS capacitor and the ground node, and
the circuit is configured to close each of the fifth through tenth switching devices in the first part of the read operation and open each of the fifth through tenth switching devices in the second part of the read operation.