Patent ID: 11894043
Assignee: INTEGRATED SILICON SOLUTION INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A power management circuit in a low-power double data rate memory, which is configured to manage a plurality of power supplies of the low-power double data rate memory according to a reference voltage, the power management circuit in the low-power double data rate memory comprising:
a low dropout regulator having a first transmitting terminal and a second transmitting terminal, wherein the first transmitting terminal is configured to transmit a first voltage of the power supplies, the second transmitting terminal is configured to transmit a second voltage of the power supplies, and the low dropout regulator adjusts a voltage difference between the first voltage and the second voltage according to the reference voltage; and
a power network structure electrically connected to the low dropout regulator and comprising:
a first power network circuit having a first connecting point electrically connected to the first transmitting terminal, wherein the first power network circuit has a grid shape and a first unit network space; and
a second power network circuit having a second connecting point electrically connected to the second transmitting terminal, wherein the second power network circuit has another grid shape and a second unit network space, and the second connecting point is separated from the first connecting point by a distance;

wherein the distance is smaller than or equal to one of the first unit network space and the second unit network space.