Patent ID: 11935892
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. An integrated circuit structure, comprising:
a first gate structure surrounding a channel region of a first semiconductor nanowire;
a second gate structure surrounding a channel region of a second semiconductor nanowire;
a gate endcap isolation structure between the first and second semiconductor nanowires and laterally between and in contact with the first and second gate structures;
a first trench contact structure above the first semiconductor nanowire;
a second trench contact structure above the second semiconductor nanowire, the gate endcap isolation structure laterally between and in contact with the first trench contact structure and the second trench contact structure; and
a local gate-to-contact interconnect electrically connecting the first gate structure to the first trench contact structure.