Patent ID: 11935890
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 7:
8. A method comprising:
forming an epitaxial stack over a substrate, wherein the epitaxial stack comprises first epitaxial layers and second epitaxial layers alternately arranged;
forming a dummy gate over the epitaxial stack;
depositing source/drain regions over the epitaxial stack and on opposite sides of the dummy gate;
removing the dummy gate and portions of the first epitaxial layers directly under the dummy gate;
forming a gate structure to surround the second epitaxial layers;
forming an ILD layer over the gate structure and the source/drain regions; and
forming a transistor over the ILD layer, wherein a channel of the transistor comprises 2D materials, wherein forming the transistor comprises forming source/drain contacts over the 2D materials, forming a gate dielectric layer over the source/drain contacts, and forming a gate electrode over the gate dielectric layer.