Patent ID: 11967360
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 13:
14. A method comprising:
providing memory circuitry with an array of bitcells that store data;
providing address decoder circuitry that receives an address for accessing the data stored in the array of bitcells, wherein accessing the data includes read-write operations;
providing dynamic pipeline circuitry that enables a data access pipeline to perform the read-write operations so as to access the data stored in the memory based on the address, wherein the dynamic pipeline circuitry dynamically adjusts the data access pipeline during the read-write operations so as to output the data based on the address, and wherein the dynamic pipeline circuitry determines whether additional memory access operations are impending based on a chip-enable bit; and
manufacturing, or causing to be manufactured, an integrated circuit with the memory circuitry and the dynamic pipeline circuitry.