Patent ID: 11907547
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G  H

Claim 25:
26. The memory device of claim 23, wherein the lesser priority token is a first lesser priority token, and wherein the controller is further configured to cause the memory device to:
in response to determining that the memory device does not have the first lesser priority token:
determine whether there is sufficient available current budget to initiate the next phase of the access operation in a selected operating mode;
in response to determining that there is sufficient available current budget to initiate the next phase of the access operation in the selected operating mode, broadcast an expected peak current magnitude for the selected operating mode and a second lesser priority token to remaining memory devices of the plurality of memory devices; and
in response to determining that there is insufficient available current budget to initiate the next phase of the access operation in the selected operating mode, broadcast the expected peak current magnitude for an idle memory device and the second lesser priority token to the remaining memory devices of the plurality of memory devices.