Patent ID: 11929412
Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 6:
7. A semiconductor device comprising:
a substrate;
a first insulating layer over the substrate;
a second insulating layer over the first insulating layer;
an oxide semiconductor layer over the second insulating layer;
a third insulating layer over the oxide semiconductor layer;
a first gate electrode over the third insulating layer;
a fourth insulating layer over the first gate electrode;
a first conductive layer functioning as one of a source and a drain of a transistor and being electrically connected to the oxide semiconductor layer;
a second conductive layer functioning as the other of the source and the drain of the transistor and being electrically connected to the oxide semiconductor layer; and
a third conductive layer, functioning as a second gate electrode of the transistor, over the substrate,
wherein, in a top view, the first gate electrode, the one of the source and the drain of the transistor, and the second insulating layer overlap each other,
wherein the first insulating layer is in contact with a top surface of the third conductive layer,
wherein, in a cross-sectional view in a channel width direction, the fourth insulating layer is in contact with a top surface of the first insulating layer and a top surface of the second insulating layer,
wherein each of the second insulating layer and the third insulating layer comprises an oxide,
wherein the first insulating layer comprises a metal oxide, and
wherein the fourth insulating layer comprises a metal nitride.