Patent ID: 11948650
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A testing circuit, comprising:
a first sampling module, configured to receive a to-be-tested pulse signal, and generate a first sampled signal according to the to-be-tested pulse signal; and
a second sampling module, configured to receive the to-be-tested pulse signal, and generate a second sampled signal according to the to-be-tested pulse signal,
wherein the second sampled signal and the first sampled signal have a phase difference, the phase difference being equal to a pulse width of the to-be-tested pulse signal,
wherein the first sampling module comprises:
a first temporary storage unit, configured to sample a first to-be-sampled signal in response to the to-be-tested pulse signal so as to generate a first temporary storage signal, wherein a triggering type of the first temporary storage unit is edge triggering, and an edge of the first temporary storage signal corresponds to a first edge of the to-be-tested pulse signal and corresponds to an edge of the first sampled signal; and
wherein the second sampling module comprises a transmission gate and a second temporary storage unit.