Patent ID: 11869571
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. A controller for controlling a memory device, the controller comprising:
a clock generator configured to generate a clock signal and to output the clock signal to the memory device;
a command address generator configured to generate a command and address signal to operate the memory device;
a command address transmitter configured to transmit the command and address signal in response to the clock signal; and
a processing-in-memory (PIM) mode generator configured to generate a mode change command for selecting one of a first operation mode and a second operation mode,
wherein one bank among a plurality of banks of the memory device is activated in response to the mode change command indicating the first operation mode, and
at least two banks among the plurality of banks of the memory device are activated in response to the mode change command indicating the second operation mode.