Patent ID: 11895890
Assignee: HEFEI BOE JOINT TECHNOLOGY CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. The display substrate according to claim 9, further comprising a plurality of first gate lines, a plurality of first voltage lines and a plurality of second voltage lines, the plurality of first gate lines all extending along the first direction, and the plurality of first voltage lines and the plurality of second voltage lines all extending along the second direction, wherein
a pixel driver circuit in each of the first sub-area, the second sub-area and the third sub-area includes a first transistor, a driving transistor and a storage capacitor; and the storage capacitor includes a first storage electrode and a second storage electrode;
a gate of the first transistor is connected to a first gate line corresponding to the pixel driver circuit; a second electrode of the first transistor is connected to a gate of the driving transistor; a first electrode of a first transistor located in the first sub-area is connected to the first data line, a first electrode of a first transistor located in the second sub-area is connected to the second data line, and a first electrode of a first transistor located in the third sub-area is connected to the third data line;
a first electrode of the driving transistor is connected to a first voltage line corresponding to the pixel driver circuit, and a second electrode of the driving transistor is connected to the first storage electrode; a first storage electrode of the storage capacitor in the first sub-area is connected to the third anode through the third via hole, a first storage electrode of the storage capacitor in the second sub-area is connected to the first anode through the first via hole, and a first storage electrode of the storage capacitor in the third sub-area is connected to the second anode through the second via hole; the first cathode, the second cathode and the third cathode are connected to a second voltage line through at least one fourth via hole;
the second storage electrode is connected to the gate of the driving transistor; and
the orthographic projections of the first via hole, the second via hole and the third via hole on the first base overlap with orthographic projections of corresponding storage capacitors on the first base, respectively.