Patent ID: 11948616
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 11:
12. The manufacturing method of a semiconductor structure according to claim 10, wherein the forming a first magnetic memory structure, a second magnetic memory structure, a first bit line, and a second bit line comprises:
forming a first dielectric layer, wherein the first dielectric layer covers the transistor;
forming a first interconnecting hole in the first dielectric layer, wherein the first interconnecting hole exposes the first terminal of the transistor;
forming a first interconnecting structure in the first interconnecting hole, and forming a first conductor layer on an upper surface of the first dielectric layer, wherein the first conductor layer is electrically connected to the first terminal of the transistor through the first interconnecting structure;
forming a second dielectric layer on the first dielectric layer, and forming a second interconnecting hole in the second dielectric layer, wherein the second interconnecting hole exposes the first conductor layer;
forming a second interconnecting structure in the second interconnecting hole;
forming a third dielectric layer, a first magnetic memory structure, a second magnetic memory structure, and a fourth dielectric layer on the second dielectric layer, wherein the bottom electrode of the first magnetic memory structure is connected to the first conductor layer through the second interconnecting structure;
forming a fifth dielectric layer on the fourth dielectric layer, forming a third interconnecting hole in the fifth dielectric layer, and forming a fourth interconnecting hole in the fifth dielectric layer and the fourth dielectric layer, wherein the third interconnecting hole exposes the top electrode of the first magnetic memory structure, and the fourth interconnecting hole exposes the bottom electrode of the second magnetic memory structure; and
forming a third interconnecting structure in the third interconnecting hole, forming a fourth interconnecting structure in the fourth interconnecting hole, and forming the first bit line and the second bit line on the fifth dielectric layer, wherein the first bit line is electrically connected to the top electrode of the first magnetic memory structure through the third interconnecting structure, and the second bit line is electrically connected to the bottom electrode of the second magnetic memory structure through the fourth interconnecting structure.