Patent ID: 11908794
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An integrated chip comprising:
a substrate;
a first interconnect dielectric layer disposed over the substrate;
an interconnect wire disposed in the first interconnect dielectric layer, the interconnect wire having a base portion with a base width and an upper portion with an upper width, wherein the upper width is less than the base width such that the interconnect wire has tapered outer sidewalls;
a protection liner arranged along the tapered outer sidewalls of the interconnect wire and on a top surface of the upper portion of the interconnect wire;
a first etch stop layer arranged on an upper surface of the first interconnect dielectric layer and having a sidewall substantially aligned with an edge of an upper portion of the protection liner over the interconnect wire; and
an interconnect via arranged over and coupled to the interconnect wire, the interconnect via having a lower portion that contacts an upper surface of the protection liner, extends along the sidewall of the first etch stop layer, and contacts an upper surface of the first etch stop layer.