Patent ID: 11921579
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. A memory system comprising:
a memory controller; and
a memory device comprising a plurality of bank arrays provided in a memory cell array, and an error correction circuit,
wherein the memory device is configured to perform a memory operation based on a first command received from the memory controller,
wherein the error correction circuit is configured to perform a scrubbing operation which comprises detecting an error of data read from the memory cell array, correcting the detected error to generate error correction data, and writing back the error correction data to the memory cell array,
wherein the memory controller is configured to provide the memory device with a second command to block the scrubbing operation based on the error detected by the error correction circuit being a multi-bit error, and
wherein the memory device is configured to control the error correction circuit to receive the second command from the memory controller based on the detected error being the multi-bit error and to block the error correction circuit from writing back the error correction data to the memory cell array based on the second command.