Patent ID: 11972818
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. The controller as set forth in claim 9, wherein the controller is further configured to, in the verify level trimming process:
instruct the memory apparatus to program the memory cells connected to a sample group of the plurality of word lines in at least one sample block with a predetermined test data pattern;
instruct the memory apparatus to apply the predetermined refresh read voltage to the selected ones of the plurality of word lines in the at least one sample block for the predetermined period of time at the predetermined intervals of time to maintain the memory cells in the second read condition during the refresh read operation;
instruct the memory apparatus to read an obtained data test pattern from the memory cells of the at least one sample block after the predetermined sample test time; and
instruct the memory apparatus to count the quantities of the memory cells having threshold voltages crossing over between the plurality of data states in the plurality of crossovers and the total failure bit count based on a comparison of the obtained data test pattern read from the memory cells of the at least one sample block to the predetermined test data pattern.