Patent ID: 11881253
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus, comprising:
a memory having a plurality of memory cells coupled to a common node driver, wherein a group of the memory cells are coupled to an access line and each respective memory cell of the group is coupled to a different respective sense line;
sense circuitry coupled to the different respective sense lines and to the group of memory cells via the different respective sense lines; and
circuitry configured to apply an average reference voltage from the common node driver to the sense circuitry during a sense operation being performed on the group of memory cells coupled to the access line and whose data states are being sensed by the sense operation, wherein the average reference voltage is an average of magnitudes of voltage signals provided from the group of memory cells via the different respective sense lines.