Patent ID: 11868874
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A method of operating a neuromorphic processor including a two-dimensional (2D) array having synapse circuits disposed at intersections of n first direction lines, respectively extending from n axon circuits in a first direction, and m second direction lines intersecting the first direction lines, and neuron circuits connected to the first direction lines or the second direction lines, the method comprising:
receiving a first input corresponding to a respectively different bit from among bits of an n-bit activation, by each of the axon circuits;
obtaining an operation value of a corresponding first input of the first inputs and a second input corresponding to a respectively different bit among bits of an m-bit weight, by each of the synapse circuits; and
for each of the neuron circuits:
receiving respective operation values output from at least one of the synapse circuits, based on corresponding time information assigned individually to the synapse circuits; and
performing an arithmetic operation based on the received respective operation values,

wherein n and m are natural numbers, and at least one of n or m is greater than 1,
wherein the neuron circuits collectively generate a multiplication result between the n-bit activation and the m-bit weight,
wherein at least some of the neuron circuits respectively include a different single adder,
wherein the performing of the arithmetic operations comprise calculating, by each of the single adders, one of a plurality of bits of the multiplication result by performing an addition operation, and
wherein the method further comprises:
assigning respective synapse circuits provided on a same line among the first direction lines with same time information; and
assigning respective synapse circuits provided on different lines among the first direction lines with different time information.