Patent ID: 11962234
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Electrical machinery, apparatus, energy (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A circuit, comprising:
a first gate driver having a first gate driver input, wherein the first gate driver is adapted to be coupled to a control terminal of a first transistor, and the first gate driver is configured to turn on the first transistor in response to a first active gate signal received at the first gate driver input;
a second gate driver having a second gate driver input, wherein the second gate driver is adapted to be coupled to the control terminal of a second transistor, and the second gate driver is configured to turn on the second transistor in response to a second active gate signal received at the second gate driver input;
a third gate driver having a third gate driver input, wherein the third gate driver is adapted to be coupled to the control terminal of a third transistor, and the third gate driver is configured to turn on the third transistor in response to a third active gate signal received at the third gate driver input;
a fourth gate driver having a fourth gate driver input, wherein the fourth gate driver is adapted to be coupled to the control terminal of a fourth transistor, and the fourth gate driver is configured to turn on the fourth transistor in response to a fourth active gate signal received at the fourth gate driver input; and
a pulse width modulation (PWM) controller having first, second, third, and fourth outputs coupled to respective first, second, third, and fourth gate driver inputs, wherein the PWM controller is configured to generate first, second, third, and fourth gate signals for the first, second, third, and fourth gate drivers, respectively, to implement a repeating pattern, the repeating pattern including:
a first pattern portion in which the second and third gate signals are asserted and the first and fourth gate signals are deasserted;
a second pattern portion in which the first and second gate signals are asserted and the third and fourth gate signals are deasserted;
a third pattern portion in which the first and fourth gate signals are asserted and the second and third gate signals are deasserted; and
a fourth pattern portion in which the third and fourth gate signals are asserted and the first and second gate signals are deasserted.