Patent ID: 11907574
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device comprising:
an array of memory cells; and
a controller configured to access the array of memory cells,
wherein the controller is further configured to:
receive a command to perform a program operation;
in response to the command to perform the program operation, begin execution of the program operation;
in response to executing the program operation, pull down a ready/busy control signal to indicate the memory device is busy executing the program operation;
while executing the program operation, receive a command to perform a read operation with the ready/busy control signal pulled down;
in response to the command to perform the read operation, suspend the execution of the program operation while keeping the ready/busy control signal pulled down; and
with the execution of the program operation suspended and with the ready/busy control signal pulled down, execute the read operation while keeping the ready/busy control signal pulled down.