Patent ID: 11899067
Assignee: SHANGHAI JIAO TONG UNIVERSITY
Field: Electrical machinery, apparatus, energy (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 10:
11. A current control method for a cascaded converter SM testing system, wherein the current control method is used to suppress an interference of a pulse voltage output of a tested SM caused by a nearest level control (NLC) modulation on a current output waveform; wherein by compensating a feedforward voltage in a current controller, the interference of the pulse voltage of the tested SM caused by the NLC modulation is eliminated; wherein: the feedforward voltage used for compensation is generated by any of the following methods:
a first method: calculating a difference between an inserted number of tested SMs in an inverting mode and the tested SMs in a rectifying mode, and generating the feedforward voltage in combination with a capacitor voltage of a single SM;
a second method: sampling a terminal pulse voltage signal of the tested SM through a voltage sampler; performing a low-pass filtering on the sampled voltage signal to remove a sampling error caused by a switching dead zone; using a filtered voltage signal as the feedforward voltage;
the feedforward voltage changing synchronously with the pulse voltage at a terminal of the tested SM is compensated to an output of a proportional integral and resonant (PIR) regulator in the current controller to eliminate the interference caused by the pulse voltage at the terminal of the tested SM and remove a current distortion caused by the interference of the pulse voltage.