Patent ID: 11868280
Assignee: MICRON TECHNOLOGY, INC.
Field: nan (nan)
Classification: CPC nan | IPC G

Claim 14:
15. A system, comprising:
a first sequencer configured to provide a first plurality of sequenced output signals;
a second sequencer configured to provide a second plurality of sequenced output signals; and
a third sequencer configured to provide a third plurality of sequenced output signals;
wherein the first, second, and third sequencers are coupled, via chaining circuitry, in a feed-forward and a feed-backward manner such that:
responsive to assertion of a primary enable signal provided to the chaining circuitry, sequencer enable signals provided to the respective first, second, and third sequencers are asserted in the feed-forward manner; and
responsive to a subsequent deassertion of the primary enable signal, the sequencer enable signals provided to the respective first, second, and third sequencers are deasserted in the feed-backward manner; and

wherein the chaining circuitry comprises:
a last logic gate configured to, responsive to the deassertion of the primary enable signal, stop receiving the primary enable signal as a first input and stop outputting a second sequencer enable signal to the third sequencer of the plurality of sequencers; and
a first logic gate configured to, responsive to the deassertion of the primary enable signal, stop receiving the primary enable signal as a first input, stop receiving an output of the second sequencer as a second input, and stop outputting a first sequencer enable signal to the first sequencer of the plurality of sequencers.