Patent ID: 11864020
Assignee: CISCO TECHNOLOGY, INC.
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A system comprising:
at least one processor; and
at least one memory storing instructions, which when executed by the at least one processor, cause the at least one processor to perform operations comprising:
determine a data amount in a first buffer;
calculate an estimated throughput needed to satisfy the data amount in the first buffer;
determine whether the estimated throughput is sufficient to service the data stored at the first buffer;
determine, in response to the throughput being determined to be insufficient to service the data, whether a counter value for a counter is less than a threshold value;
empty, in response to the counter value being above the threshold, a second buffer;
in response to the counter value being less than the threshold value:
pad the second buffer with a padding amount;
incrementing the counter value; and
iteratively repeating the operations by returning to the calculating with the incremented counter value.