Patent ID: 11887690
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 24:
25. The apparatus of claim 22, wherein the circuitry is operable to cause the apparatus to:
isolate a second conductor of the memory die from the voltage source based at least in part on deactivating a third transistor that is associated with the first level of the memory die;
generate a fifth voltage at the second conductor of the memory die based at least in part on coupling a storage element of a second memory cell with a second digit line and coupling the second digit line with the second conductor;
shift the second conductor from the fifth voltage to a sixth voltage based at least in part on shifting a bias applied to a gate of a fourth transistor that is associated with the second level of the memory die from a seventh voltage to an eighth voltage, the fourth transistor having a channel portion coupled between a first portion of the second conductor and a second portion of the second conductor; and
determine the logic state based at least in part on shifting the second conductor from the fifth voltage to the sixth voltage.