Patent ID: 11962326
Assignee: ACCELERCOMM LIMITED
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 18:
19. The method for LDPC decoding of claim 12, further comprising:
determining, by each activated CN sub-processor, two or more minimum values and two or more next minimum values from the two or more soft bit values provided as inputs on each of its I-O ports in each of the sub-steps during the first set of sub-steps of the LDPC decoding operations and wherein the CN processor supports at least the following two modes of operation:
using, by each activated CN sub-processor in the first mode of operation, its two or more minimum values and two or more next minimum values to determine the two or more soft bit values to output on an I-O port in each of the sub-steps during the second set;
using, by each activated CN sub-processor in the second mode of operation, its two or more minimum values and two or more next minimum values provided by at least one other activated CN sub-processor to determine the two or more soft bit values to output on each of I-O port in each of the sub-steps during the second set.