Patent ID: 11960764
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 8:
9. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to:
select a primary ready/busy pin (R/B #) among a plurality of R/B # pins that are associated with respective memory dice among a plurality of memory dice of a memory device;
set the primary R/B # pin to low status;
receive, by at least one memory die among the plurality of memory dice, signaling indicative of performance of memory access for the primary R/B # pin;
receive, by the at least one memory die among the plurality of memory dice, signaling indicative of performance of the memory access involving a first memory die among the plurality of memory dice;
receive, by the at least one memory die among the plurality of memory dice, signaling indicative of performance of the memory access involving a second memory die among the plurality of memory dice;
initiate a first internal clocking signal subsequent to receipt of signaling indicative of completion of the performance of the memory access of the first memory die among the plurality of memory dice; and
initiate a second internal clocking signal subsequent to receipt of signaling indicative of completion of the performance of the memory access of the second memory die among the plurality of memory dice.