Patent ID: 11966348
Assignee: NVIDIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 10:
11. The method of claim 6 wherein the two three-level symbols comprise a first three-level symbol and a second three-level symbol, and further comprising:
the sequences of seven bits comprising a first sequence of seven bits for communication on the serial data bus, and a second sequence of seven bits for communication on the serial data bus after the communication of the first sequence of seven bits on the serial data bus; and
a voltage level of the second three-level symbol of the first sequence of seven bits being either (a) at most two voltage steps below a voltage level of a second one of the two four-level symbols of the first sequence of seven bits, or (b) at most two voltage steps above the second one of the two four-level symbols of the first sequence of seven bits.