Patent ID: 11936375
Assignee: CHIPONE TECHNOLOGY (BEIJING) CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 1:
2. The apparatus according to claim 1, wherein the buffer module comprises a third PMOS, a fourth PMOS, a fifth PMOS, a fifth NMOS, a sixth NMOS, a seventh NMOS, and an inverter, wherein,
a source of the third PMOS is electrically connected to a source of the fifth PMOS to input a supply voltage,
a gate of the third PMOS is electrically connected to a gate of the fourth PMOS, a gate of the fifth NMOS, and a gate of the sixth NMOS to receive the input signal,
a drain of the third PMOS is electrically connected to a drain of the fifth PMOS and a source of the fourth PMOS, a drain of the fourth PMOS is electrically connected to an input of the inverter and a drain of the fifth NMOS, a source of the fifth NMOS is electrically connected to a drain of the sixth NMOS and a drain of the seventh NMOS, and a source of the sixth NMOS and a source of the seventh NMOS are grounded, and
an output of the inverter is electrically connected to a gate of the fifth PMOS and a gate of the seventh NMOS to output the buffered signal.