Patent ID: 11869932
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 19:
20. A capacitor, comprising:
a semiconductor base, wherein a first mask layer is formed on the semiconductor base, and a plurality of first round hole patterns distributed uniformly are formed on the first mask layer; first openings distributed uniformly are formed on the semiconductor base by etching based on the first round hole patterns; a second mask layer is formed on one side, away from the semiconductor base, of the first openings, and a plurality of second round hole patterns are formed on the second mask layer; and second openings distributed uniformly are formed on the semiconductor base by etching based on the second round hole patterns, and meanwhile the first openings are etched continuously, so that the first openings and the second openings are same in depth;
capacitive holes, which are arranged in the semiconductor base, and arranged in an array mode;
wherein each of the capacitive holes is formed by three of the first openings and one of the second openings, a projection of each of the first openings on the semiconductor base is a first round projection, a projection of each of the second openings on the semiconductor base is a second round projection, a contour line of the second round projection respectively intersects with contours lines of the three first round projections corresponding to the three of the first openings, and a continuous outer contour of the first round projection and the second round projection forms a projection contour of one of the capacitive holes in the semiconductor base; and
a lower electrode layer, a dielectric layer and an upper electrode layer, which are deposited in the capacitive holes in sequence.