Patent ID: 11955551
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC B  H

Claim 0:
1. A method of manufacturing a semiconductor device, comprising:
forming a multi-layer structure of first semiconductor layers and second semiconductor layers alternately stacked in a vertical direction over a substrate;
patterning the multi-layer structure into a fin structure including the first semiconductor layers and the second semiconductor layers alternately stacked over a bottom fin structure;
forming a sacrificial gate structure over the fin structure, the sacrificial gate structure covering a first part of the fin structure and leaving a second part of the fin structure exposed, the first part of the fin structure including a channel region and the second part of the fin structure including source/drain region;
forming a source/drain epitaxial layer in the source/drain region;
removing the sacrificial gate structure to expose the channel region;
removing the second semiconductor layers in the channel region thereby exposing the first semiconductor layers in the channel region; and
forming a gate dielectric layer and a gate electrode layer around the first semiconductor layers in the channel region, wherein:
the first semiconductor layers are made of Si1-xGex, where 0.9≤x≤1.0, and
the bottom fin structure is made of Si1-y1Gey1, where y<x and 0.3≤y1≤0.7.