Patent ID: 11902410
Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A Phase Locked Loop, PLL, circuit for generating multiphase output signals comprising:
a digitally controlled oscillator for generating the multiphase output signals;
a sample circuit configured to sample the multiphase output signals from the digital controlled oscillator;
an analog to digital converter for converting the sampled multiphase output signals to digital samples;
a digital processing unit comprising:
a phase estimator configured to estimate a phase of the multiphase output signals from the digital samples;
a differentiator configured to calculate a phase difference between a current phase and a previous phase; and
an accumulator configured to accumulate the phase differences generated by the differentiator;
the PLL circuit further comprises:
a loop filter configured to receive an output from the accumulator and generate a control signal to the digitally controlled oscillator to adjust frequency of the digitally controlled oscillator generating the multiphase output signals.