Patent ID: 11948886
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. A method of fabricating a semiconductor device, the method comprising:
providing a semiconductor substrate having a first active region and a second active region that correspondingly extend in a first direction;
configuring the first active region to have a first conductivity;
configuring the second active region to have a second conductivity;
a front side being defined over the semiconductor substrate and a back side being defined beneath the semiconductor substrate;
forming a first front side conductive line at the front side;
configuring the first front side conductive line to receive an input signal or provide an output signal;
forming a first front side power rail in a first front side metal layer at the front side;
configuring the first front side power rail to receive a first reference power voltage;
forming a first back side power rail, a second back side power rail, a third back side power rail and a fourth back side power rail in a first back side metal layer at the back side of the semiconductor substrate and each extending in the first direction, the forming including:
within a span of a first cell that is defined relative to the first direction,
locating the second back side power rail between the third and fourth back side power rails relative to the first direction; and
locating, relative to a second direction that is substantially perpendicular to the first direction, the third back side power rail and the fourth back side power rail to at least partially overlap the first front side power rail;

configuring the first back side power rail to receive a second reference power voltage;
configuring the second back side power rail to receive a third reference power voltage;
configuring each of the third and fourth back side power rails to receive the first reference power voltage,
the first reference power voltage, the second reference power voltage, and the third reference power voltage being different from each other;

forming a first gate electrode at the front side, the first gate electrode extending in the second direction;
arranging the first gate electrode to define a first drain/source region and a second drain/source region in the first active region and a third drain/source region and a fourth drain/source region in the second active region;
connecting the first gate electrode to the first front side conductive line;
connecting the first drain/source region or the second drain/source region to the first front side power rail; and
connecting the third drain/source region or the fourth drain/source region to the first back side power rail.