Patent ID: 11876076
Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A stacked memory device, comprising:
at least one first stack layer; and
at least one second stack layer;
wherein each of the at least one first stack layer and the at least one second stack layer comprises a stack of layers stacked in a vertical direction and further comprises:
a NAND block comprising a plurality of oxide layers, the plurality of oxide layers forming a staircase structure at a first edge of the NAND block;
a first plurality of vias disposed on the staircase structure of the NAND block;
a second plurality of vias disposed at the first edge of the NAND block;
a plurality of first bonding interconnects electrically connected to the second plurality of vias;
a plurality of bitlines extending across the NAND block; and
a plurality of second bonding interconnects electrically connected to the bitlines, wherein the bitlines are disposed between the second bonding interconnects and the stack of layers in the vertical direction.