Patent ID: 11947993
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. A system comprising:
a memory having computer readable instructions; and
one or more processors for executing the computer readable instructions, the computer readable instructions controlling the one or more processors to perform operations comprising:
creating a first file control block in a primary runtime environment with a first addressing mode and a second file control block in a secondary runtime environment with a second addressing mode, wherein both the first file control block and the second file control block describe a status of a first file of a caller program in the primary runtime environment;
passing parameters of the first file of the caller program in the primary runtime environment to a target callee program in the secondary runtime environment;
adding an anchor in the first file control block as a link to the second the second file control block;
synchronizing the first file control block and the second file control block with updates to the first file in the primary runtime environment and the passed parameters of the first file of the first file in the secondary runtime environment;

determining that the first addressing mode is greater than the second addressing mode;
creating the second file block in the secondary runtime environment;
locking the first file control block in the primary runtime environment;
anchoring the first file control block to the second file control block; and
releasing, in respond to anchoring the first file control block to the second file control block, the first file control block.