Patent ID: 11922984
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 5:
6. A method of manufacturing a memory device, the method comprising:
forming a first gate structure embedded in a substrate, a first active region including a first channel region adjacent to the first gate structure, and a capacitor connected to the first active region and extended in a direction perpendicular to a top surface of the substrate, such that a first memory cell having volatility is formed in the first active region;
forming an interlayer insulating layer to cover the capacitor;
forming a second gate structure on the interlayer insulating layer;
forming a ferroelectric layer to cover the second gate structure; and
forming a second channel region, including an indium-gallium-zinc oxide, and a second active region, connected to the second channel region, on the ferroelectric layer, such that a second memory cell having non-volatility is formed in the second active region, the second memory cell having a height smaller than a height of the first memory cell in a direction perpendicular to a top surface of the substrate;
forming a transfer switch between the first and second memory cells; and
forming a controller configured to turn on the transfer switch, read data of the first memory cell, and store the data in the second memory cell.