Patent ID: 11915735
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus, comprising:
a first switching component configured to couple a first digit line of a first memory cell, in a first tier of memory cells, with an input of a sense component;
a second switching component configured to couple a second digit line of a second memory cell, in the first tier of memory cells, with the input of the sense component, the second memory cell coupled with a different word line than the first memory cell and coupled with a different plate line than the first memory cell;
the sense component configured to sense the first memory cell and the second memory cell at different times;
a third switching component, in a second tier of memory cells, configured to couple a third digit line of a third memory cell with a second input of a second sense component; and
a fourth switching component, in the second tier of memory cells, configured to couple a fourth digit line of a fourth memory cell with the second input of the second sense component.