Patent ID: 11956947
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 16:
17. A method of fabricating one-time programmable (OTP) memory cells, comprising:
fabricating a first antifuse transistor, wherein a first terminal of the first antifuse transistor is a vacancy terminal;
fabricating a first selection transistor;
fabricating a second antifuse transistor, wherein a first terminal of the second antifuse transistor is a floating terminal including a contact structure;
fabricating a second selection transistor;
connecting a second terminal of the first antifuse transistor to the first selection transistor;
connecting a second terminal of the second antifuse transistor to the second selection transistor;
connecting a gate terminal of the first antifuse transistor to a first word line configured to receive a first signal, wherein the first antifuse transistor is selectable between a first state and a second state in response to the first signal;
connecting a gate terminal of the first selection transistor to a second word line configured to receive a second signal, wherein the first selection transistor is configured to provide access to the first antifuse transistor in response to the second signal;
connecting a gate terminal of the second antifuse transistor to a third word line configured to receive a third signal, wherein the second antifuse transistor is selectable between the first state and the second state in response to the third signal;
connecting a gate terminal of the second selection transistor to a fourth word line configured to receive a fourth signal, wherein the second selection transistor is configured to provide access to the antifuse transistor in response to the fourth signal; and
connecting the first selection transistor and the second selection transistor to a bit line.