Patent ID: 11908697
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of forming an interconnect structure, the method comprising:
forming a first conductive feature in a first dielectric layer, wherein the first conductive feature comprises a first void;
forming a second dielectric layer over the first dielectric layer;
forming a third dielectric layer over the second dielectric layer;
forming a trench in the second dielectric layer and the third dielectric layer, wherein the trench extends into the first dielectric layer, wherein the trench exposes the first void in the first conductive feature;
forming a carbon-containing barrier layer along surfaces of the trench, wherein the carbon-containing barrier layer lines the first void in the first conductive feature, wherein the carbon-containing barrier layer lines the first void to form a second void; and
forming a conductive layer over the carbon-containing barrier layer in the trench.