Patent ID: 11955170
Assignee: UNTETHER AI CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A static random-access memory comprising:
a word line circuit for generating a word line signal on a word line;
a plurality of six-transistor memory cells arranged between a first bitline, a second bitline and the word line for simultaneously selecting one of either all or a portion of the plurality of six-transistor memory cells for data reading or writing, and wherein each memory cell comprises:
a first inverter;
a second inverter, the first inverter and the second inverter configured to operate at a power supply voltage (Vdd);
a first n-channel transistor having a gate for receiving the word line signal on the word line and in response connecting a first output of the first inverter to the first bitline;
a second n-channel transistor having a gate for receiving the word line signal on the word line and in response connecting a second output of the second inverter to the second bitline; and
a bitline precharge circuit for precharging the first bitline and second bitline to a voltage of Vdd/2 prior to the first and second n-channel transistors receiving the word line signal, wherein the word line circuit selects a portion of the plurality of six transistor memory cells along a selected word-line for simultaneous data reading or writing, and comprises a first PMOS transistor, a second PMOS transistor and an NMOS transistor,
wherein the first PMOS transistor has a drain connected to the word line, a source connected to a first power supply voltage Vdd1 less than Vdd and greater than Vdd/2 when reading and writing to said memory cell, and a gate for receiving a first control signal (A),
wherein the second PMOS transistor has a drain connected to the word line, a source connected to one of either Vdd when reading said memory cell or a boosted voltage Vdd_boost when writing to said memory cell, and a gate for receiving one of either a second control signal (B) or third control signal (B′), and
wherein the NMOS transistor has a drain connected to the word line, a source connected to a low power supply voltage reference (Vss), and a gate connected to a third control input (WL_clear), such that the word line signal is provided in two steps including: a first step where in response to receiving the first control signal (A) the amplitude is at the first power supply voltage (Vdd1) when reading and writing to said memory cell; and a second step, following the first step, where in response to receiving the second control signal (B) the amplitude is at the power supply voltage (Vdd) when reading said memory cell or where in response to receiving the third control signal (B′) the amplitude is at the boosted voltage Vdd_boost when writing to said memory cell.