Patent ID: 11942527
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 13:
14. An integrated chip comprising:
a first source/drain region;
a second source/drain region spaced apart from the first source/drain region;
a channel structure extending between the first source/drain region and the second source/drain region;
a gate electrode arranged over the channel structure;
an upper interconnect contact having tapered sidewalls, the upper interconnect contact being arranged over and coupled to the first source/drain region and the upper interconnect contact being the only contact directly contacting the first source/drain region; and
a backside contact arranged below and coupled to the second source/drain region wherein the backside contact being the only contact directly contacting the second source/drain region.