Patent ID: 11915775
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A method comprising:
entering a memory into a bad row mode to disable a selected row of the memory and test a repair logic configured to detect defective rows of the memory;
disabling the selected row of the memory, wherein disabling the selected row includes causing the selected row to temporarily appear to be a defective row by causing failure of an access operation on the selected row, and wherein the access operation is caused to fail by changing a value of at least one data bit in the selected row;
detecting, using the repair logic configured to detect the defective rows of the memory, the selected row as the defective row responsive to the failure of the access operation on the selected row;
performing a post-package repair (PPR) operation on the selected row;
testing an address associated with the selected row; and
exiting the memory from the bad row mode, wherein the selected row is disabled only while the memory is in the bad row mode.