Patent ID: 11927632
Assignee: INVENTEC (PUDONG) TECHNOLOGY CORPORATION
Field: Measurement (Instruments)
Classification: CPC G | IPC G

Claim 1:
2. The DIMM slot test system without series connection of test board through JTAG according to claim 1, wherein the third test signal generated by the CPU based on the second test signal with JTAG signal format is a power test signal or a ground test signal, the CPU transmits the power test signal to the specified one of the at least one CPLD chip through the control pins, the specified one of the at least one CPLD chip tests the power pins to read and record the values of the power pin as a power test result, or the CPU transmits the ground test signal to the specified one of the at least one CPLD chip through the control pins, the specified one of the at least one CPLD chip tests the ground pins to read and record the values of the ground pins as a ground test result.