Patent ID: 11916703
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. An equalizer circuit, comprising:
a decision feedback equalizer (DFE) circuit having a first output and a second output;
a sign-sign least mean squares (SS-LMS) adaptation circuit having a weight value output coupled to the DFE circuit; and
an error sampler circuit coupled to the DFE circuit and the SS-LMS adaptation circuit, the error sampler circuit comprising a master latch circuit, and the master latch circuit including a slicer circuit configured to:
generate a first difference signal as a difference of the first output and a first reference signal;
generate a second difference signal as a difference of the second output and a second reference signal;, a reference voltage source wherein the reference voltage source comprises:
a digital-to-analog converter (DAC) coupled to the SS-LMS adaptation circuit, and configured to generate a reference voltage based on an output of the SS-LMS adaptation circuit;
a common-mode feedback loop coupled to the DAC, the DFE circuit, and the error sampler circuit, and configured to adjust a first common-mode voltage of the reference voltage based on a second common-mode voltage of the input voltage.