Patent ID: 11876732
Assignee: STMICROELECTRONICS (ROUSSET) SAS
Field: Digital communication (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 7:
8. A system on a chip, comprising:
a plurality of master pieces of equipment on the system on a chip;
a plurality of slave resources, on the system on a chip, including a first particular slave resource coupled to at least one element of the system on a chip intended to cooperate with the first particular slave resource during an operation of the system on a chip;
an interconnection circuit, on the system on a chip, coupled between the master pieces of equipment, the slave resources and the at least one element, the interconnection circuit configured to rout transactions between the master pieces of equipment, the slave resources and the at least one element; and
a processing circuit, on the system on a chip, configured to allow a user of the system on a chip to implement within the system on a chip at least one configuration diagram of the system as defined by a set of configuration pieces of information assigned to the master pieces of equipment, to the slave resources, and to the at least one element;
wherein the set of configuration pieces of information are configured to be used to define an assignment of at least one master piece of equipment to at least some of the slave resources; wherein the configuration pieces of information assigned to the at least one element are identical to the configuration pieces of information assigned to the first particular slave resource;
wherein the set of configuration pieces of information comprises at least one identification piece of information assigned to each master piece of equipment; and
wherein the set of configuration pieces of information of the configuration diagram further comprises, for at least one slave resource, an inaccessibility piece of information intended to indicate that the slave resource is inaccessible by any master piece of equipment.