Patent ID: 11869622
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 31:
32. An apparatus, comprising:
a memory device;
a first organic substrate comprising a first conductive line with a first pitch, the first organic substrate comprising a plane for powering one or more components of the memory device;
a second organic substrate coupled with the first organic substrate and comprising a second conductive line with a second pitch smaller than the first pitch, the second conductive line routed through the second organic substrate couples the memory device with a host device, the memory device is coupled with the second organic substrate; and
a controller associated with the memory device and configured to cause the apparatus to:
perform a synchronization procedure to synchronize a first clock of the host device associated with a command/address (CA) channel with a second clock of the memory device associated with the CA channel;
receive, over the CA channel based at least in part on performing the synchronization procedure, a command during a frame associated with a frame boundary of the CA channel; and
perform, by the memory device, an operation associated with the command based at least in part on receiving the command.