Patent ID: 11972292
Assignee: XCONN TECHNOLOGIES HOLDINGS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A switch, comprising:
a plurality of ports through which packets ingress and egress the switch, each of the packets being divisible into a plurality of packet segments;
a memory including a plurality of banks; and
a scheduler coupled with the plurality of ports and the memory, the scheduler configured to allocate memory to store the plurality of packet segments in the plurality of banks such that a beginning packet segment of a packet is stored in a selected bank of the plurality of banks and each subsequent packet segment in the packet is stored in order in a next adjacent bank of the plurality of banks, wherein the allocating of the memory comprises to:
store the beginning packet segment to the selected bank;
lock the next adjacent bank for the next packet segment, wherein the locking of the next adjacent bank includes preventing a beginning segment for a new packet from being stored in the same cycle at the next adjacent bank; and
store the next packet segment in the next adjacent bank.