Patent ID: 11876078
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A method for fabricating a TSV interconnection structure, comprising:
providing a plurality of upper substrate structures, and sequentially bonding the plurality of upper substrate structures, wherein the plurality of upper substrate structures is displaced from adjacent upper substrate structures;
forming a plurality of TSVs in the bonded plurality of upper substrate structures, wherein the plurality of TSVs penetrates through at least one of the bonded plurality of upper substrate structures;
forming connecting wires in the plurality of TSVs to connect corresponding circuits on the plurality of upper substrate structures;
providing a bottom substrate structure;
disposing the plurality of upper substrate structures on the bottom substrate structure; and
connecting the plurality of upper substrate structures with a circuit on the bottom substrate structure;
forming at least one displacement mark on each of the upper substrate structures and the bottom substrate structure, and bonding the plurality of upper substrate structures and the bottom substrate structure according to the at least one displacement mark.