Patent ID: 11860803
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 15:
16. A memory device comprising:
a buffer die comprising:
a command and address buffering circuit configured to receive first and second broadcast commands and a processing command from an external device, and transmit the first and second broadcast commands, and the processing command through a first through silicon via (TSV); and
a data input/output buffer circuit configured to receive external data from the external device and transmit the external data through a second TSV;

a plurality of core dice stacked on the buffer die and connected to the buffer die through a plurality of TSVs including the first TSV and the second TSV, wherein the plurality of core dice comprise:
a first core die comprising a first processing circuit, a first memory cell array, a first command decoder configured to decode the first broadcast command transmitted through the first TSV, and a first data input/output circuit configured to output first data of the first memory cell array to a common data input/output bus under control of the first command decoder; and
a second core die comprising a second processing circuit, a second memory cell array, a second command decoder configured to decode the second broadcast command transmitted through the second TSV, and a second data input/output circuit configured to receive the first data of the first memory cell array from the common data input/output bus under control of the second command decoder,

wherein the second processing circuit is configured to decode the processing command and generate second data by performing a processing operation on the first data and the external data.