Patent ID: 11870459
Assignee: MASSACHUSETTS INSTITUTE OF TECHNOLOGY
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 2:
3. A universal decoder comprising:
a syndrome calculator for checking membership of received data in a codebook, and an error generator, coupled to the syndrome calculator, wherein in response to the syndrome calculator detecting an error, the syndrome calculator provides the error to the error generator and the error generator calculates rank-ordered binary symmetric channel noise patterns and checks for membership in the codebook, wherein the error generator comprises:
an error logic which generates (D1, D2) distance pairs to indicate distances between active bits having a first logic value in a guessed noise sequence (E);
a pattern generator coupled to the error logic; and
an error shifter coupled to the error logic and the pattern generator wherein the error logic which generates (D1, D2) distance pairs to indicate the distances between active bits having the first logic value in a guessed noise sequence (E) and the pattern generator constructs a bit sequence defined by (D1, D2), which is then used as indices of one or more input-seed values having the first logic value for the error shifter and the error shifter creates in parallel variations of a sequence of input-seed values through cyclical shifts for the primary and secondary error generators such that the error generator creates ordered error sequences in parallel.