Patent ID: 11947887
Assignee: CADENCE DESIGN SYSTEMS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. A method for allocating test-point flops into scan-chains of a circuit design, the method comprising:
receiving, at a circuit design tool executing on a computing platform, a circuit netlist comprising functional logic, test-point nodes interconnecting portions of the functional logic, and test-point flops associated with scan-chains;
generating a compatibility matrix based on the circuit netlist via a test-point flop allocation module executing on the computing platform, the compatibility matrix defining the compatibility of the test-point nodes in the circuit netlist based on shared nodes of the functional logic associated with a given pair of test-point nodes;
implementing a graph coloring algorithm based on the compatibility matrix to identify a quantity of compatible test-point nodes for each of the test-point nodes via the test-point flop allocation module, wherein the graph coloring algorithm is configured to order the test-point nodes from minimum to maximum compatible test-point nodes and to assign an identifier to each the test-point nodes in the order based on relative compatibility of the test-point nodes, the identifier defining a given one of a plurality of test-point sharing groups;
allocating each of the test-point flops to one of the test-point sharing groups via the test-point flop allocation module, each of the test-point sharing groups comprising a plurality of compatible test-point nodes; and
generating a circuit layout associated with the circuit design, the circuit layout comprising the functional logic and scan-chains comprising the test-point flops allocated to the test-point sharing groups in response to the circuit netlist via a circuit layout module executing on the computing platform.