Patent ID: 11941339
Assignee: SYNOPSYS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to perform operations comprising:
receiving information describing a set of pin-pairs of an integrated circuit (IC) design;
determining an initial routing of the IC design including (i) defining connected wires between each pin-pair in the set of pin-pairs, and (ii) evaluating a target resistance for the pin-pair over the connected wires, wherein each connected wire is routed compactly with other connected wires and wire resistances are evaluated sequentially;
determining after initial routing, a resistance adjustment to be applied to adjust wire resistance, further comprising:
determining whether the wire resistance is below the target resistance, and whenever the wire resistance is below the target resistance:
determining a square routing;

otherwise determining whether the wire resistance is above the target resistance, and whenever the wire resistance is above the target resistance:
determining a multi-layer stacking; and

providing the routing in compact patterns as generated by the initial routing and as adjusted by the resistance adjustment.