Patent ID: 11935617
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A method, comprising:
receiving, at a memory device, signaling that indicates a first data pattern and one or more addresses of memory cells within the memory device;
latching a second data pattern associated with the one or more addresses by one or more sense amplifiers based at least in part on receiving the signaling;
writing, by the memory device, the first data pattern to the one or more sense amplifiers after latching the second data pattern by the one or more sense amplifiers; and
outputting, by the memory device, an indication of whether the first data pattern matches the second data pattern based at least in part on writing the first data pattern to the one or more sense amplifiers, wherein the indication of whether the first data pattern matches the second data pattern is based at least in part on whether a current associated with writing the first data pattern to the one or more sense amplifiers satisfies a threshold.