Patent ID: 11881280
Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. An integrated circuit, comprising:
a charge pump configured to receive a supply voltage and to provide an output voltage higher than the supply voltage; and
a charge pump regulator coupled to the charge pump and including:
a sense current generator coupled to the charge pump and configured to generate a sense current indicative of a slew rate of the output voltage, wherein the sense current generator includes:
a first transistor having a source terminal coupled to ground, a gate terminal, and a drain terminal coupled to the gate terminal;
a plurality of sense capacitors each having a first terminal coupled to an output terminal of the charge pump and a second terminal; and
a plurality of switches each coupled between to the second terminal of a respective sense capacitor and the drain terminal of the first transistor and configured to enable the corresponding sense capacitor to participate in generating the sense current;
a second transistor having a source terminal coupled to ground, a drain terminal, and a gate terminal coupled to the gate terminal of the first transistor;

a reference current generator coupled between a high supply voltage and a drain of the second transistor and configured to generate a reference current;
a clock generator configured to generate a clock signal with a frequency based on a difference current corresponding to a difference between the reference current and the sense current and to provide the clock signal to the charge pump, the clock generator including:
a current controlled oscillator having an input directly coupled to the drain terminal of the second transistor and that receives, from the drain terminal of the second transistor, wherein the current controlled oscillator generates an oscillating signal with a frequency based on the difference current; and
a level shifter configured to shift a level of the oscillating signal.