Patent ID: 11940940
Assignee: GRAPHCORE LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 0:
1. A data processing device comprising:
a plurality of processors, each of the processors comprising an instruction memory storing a local program that is associated with the respective processor, the local programs of the processors together providing at least part of a computer program;
a plurality of interfaces enabling ingress data packets received from external devices to be provided to the plurality of processors;
a switching fabric comprising a plurality of buses, wherein each of at least some of the buses is associated with a respective one of the interfaces and is configured to transport ones of the ingress data packets received on the respective one of the interfaces; and
for each of the plurality of processors, switching circuitry associated with the respective processor,
wherein each of at least some of the local programs comprises a schedule defining, for different phases of execution of the computer program, which of the interfaces its associated one of the processors is scheduled to connect to,
wherein at least one of the plurality of processors is configured to, in dependence upon the schedule in its associated local program:
control its associated switching circuitry to, during a first of the phases of execution of the computer program, connect to a first of the at least some of the buses so as to enable reception of a first set of the ingress data packets from a first of the interfaces that is associated with the first of the at least some of the buses; and
control its associated switching circuitry to, during a second of the phases of execution of the computer program, connect to a second of the at least some of the buses so as to enable reception of a second set of the ingress data packets from a second of the interfaces that is associated with the second of the at least some of the buses,
wherein the second of the interfaces is configured to receive a third set of ingress data packets during the first of the phases of execution of the computer program,
wherein a further at least one of the processors is configured to:
control its associated switching circuitry to, during the first of the phases of execution of the computer program, connect to the second of the at least some of the buses so as to enable reception of the third set of the ingress data packets from the second of the interfaces.