Patent ID: 11861189
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A memory system, comprising:
a memory device including a plurality of memory blocks, each memory block including memory cells capable of storing multi-bit data; and
a controller configured to:
allocate the plurality of memory blocks for plural zoned namespaces input from an external device,
access a memory block allocated for one of the plural zoned namespaces in response to a data input/output request input from the external device,
adjust, in response to a first request, a number of bits of data stored in a memory cell included in a memory block, which is allocated for at least one zoned namespace among the plural zoned namespaces, and
deactivate at least one zoned namespace other than the at least one zoned namespace among the plural zoned namespaces to maintain the storage capacity of the at least one zoned namespace corresponding to the first request.