Patent ID: 11894075
Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device, comprising:
memory cells arranged in rows and columns, each memory cell configured to store n-bit of data, wherein n is a whole number larger than 1; and
a periphery circuit coupled to the memory cells and configured to program a selected row of memory cells according to n logic pages of current programming data, wherein:
the periphery circuit comprises page buffers, each page buffer comprising n data latches and coupled to a column of memory cells through a bit line; and
the periphery circuit is further configured to:
store the n logic pages of the current programming data in the n data latches for programming the selected row of memory cells;
release one or more of the n data latches, by discarding one or more of the n logic pages of the current programming data correspondingly, before the programming the selected row of memory cells according to the n logic pages of the current programming data is completed;
store one or more of n logic pages of new programming data in the released data latches before the programming the selected row of memory cells according to the n logic pages of the current programming data is completed; and
recover the discarded one or more of the n logic pages of the current programing data when there is a programming failure, based on remaining logic pages of the current programming data, logic states of the selected row of memory cells that have passed programming verification and a mapping scheme between a set of n-bit binary codes and 2n logic states of each memory cell.