Patent ID: 11907567
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 4:
5. The memory system of claim 1, wherein the controller is configured to:
control ON/OFF of the data erase processing function,
when an erase request from the host is received and the data erase processing function is turned on, confirm a number of pieces of the first data logically erased in the predetermined partition from a previous data erase processing to the present by a method consistent with the file system specified by the data erase processing function,
when the number of pieces of the first data exceeds a preset upper limit value, control the data erase processing function from on to off, and physically erase the first data according to the erase request from the host,
when the number of pieces of the first data does not exceed the preset upper limit value, physically erase the first data by the data erase processing function at a time of a next data erasing process without following any type of erase request from the host.