Patent ID: 11960735
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. A system, comprising:
a first memory controller coupled to a first memory device, wherein a first memory address range, reserved for a first portion of a first data type, is allocated to the first memory device;
a second memory controller coupled to a second memory device, wherein:
a second memory address range, reserved for a first portion of a second data type, is allocated among the first memory device and the second memory device, and
a third memory address range, reserved for a second portion of the first data type, is allocated to the second memory device; and

a memory manager configured to:
determine a memory address range associated with a first access request;
determine a memory address range associated with a second access request;
utilize the first memory controller and the second memory controller to execute the first access request responsive to a determination that the first access request is associated with the second memory address range;
utilize the first memory controller to execute the first access request responsive to a determination that the first access request is associated with the first memory address range; and
utilize the second memory controller to execute the second access request in parallel with an execution of the first access request utilizing the first memory controller, responsive to a determination that the first access request is associated with the first memory address range and a determination that the second access request is associated with the third memory address range.