Patent ID: 11955384
Assignee: NATIONAL TAIWAN UNIVERSITY
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 0:
1. A method comprising:
forming a fin structure over a substrate, wherein the fin structure comprises a first channel layer, a sacrificial layer over the first channel layer, and a second channel layer over the sacrificial layer;
forming a dummy gate structure across the fin structure;
recessing the fin structure by using the dummy gate structure as an etch mask;
after recessing the fin structure, epitaxially growing first source/drain epitaxial structures on opposite sides of the first channel layer;
epitaxially growing epitaxial isolation structures on and in contact with the first source/drain epitaxial structures, respectively, wherein epitaxially growing the epitaxial isolation structures comprises:
epitaxially growing a first epitaxial layer on and in contact with one of the first source/drain epitaxial structures;
epitaxially growing a second epitaxial layer on and in contact with the first epitaxial layer;
epitaxially growing a third epitaxial layer on and in contact with the second epitaxial layer; and
epitaxially growing a fourth epitaxial layer on and in contact with the third epitaxial layer, wherein the first and third epitaxial layers are of a first conductivity type, and the second and fourth epitaxial layers are of a second conductivity type different from the first conductivity type;
epitaxially growing second source/drain epitaxial structures on opposite sides of the second channel layer, wherein the second source/drain epitaxial structures are on and in contact with the epitaxial isolation structures, respectively;
removing the dummy gate structure and the sacrificial layer to form a gate trench between the first source/drain epitaxial structures and between the second source/drain epitaxial structures; and
forming a metal gate structure in the gate trench.