Patent ID: 11914886
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A method comprising:
receiving, by a memory die, a plurality of logical pages of data to be stored in a page of Multi-Level Cell (MLC) memory;
calculating, by circuits of the memory die, parity data for the plurality of logical pages of data;
programming the plurality of logical pages of data in the page of MLC memory in a foggy program operation such that memory cells of the page of MLC memory are programmed to first distributions;
reading the page of MLC memory while the memory cells are programmed to the first distributions in a foggy read operation to obtain, in data latches of the memory die, an initial copy of the plurality of logical pages of data;
performing, by logic circuits of the memory die, a plurality of AND operations on the initial copy of the plurality of logical pages of data and the parity data, wherein the plurality of AND operations are applied between bits obtained from reading an individual memory cell in the MLC memory and a corresponding parity data bit;
flipping selected bits of the initial copy of the plurality of logical pages of data while each selected bit remains in a respective data latch of the data latches according to results of the plurality of AND operations to obtain, in the data latches, a recovered copy of the plurality of logical pages of data; and
further programming the page of MLC memory from the first distributions to second distributions in a fine programming operation, the second distributions representing the recovered copy of the plurality of logical pages of data obtained according to the results of the plurality of AND operations.