Patent ID: 11892502
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 10:
11. The integrated circuit of claim 10, wherein each of the first transmission gate and the second transmission gate comprises a first control terminal, a second control terminal, an input and an output, and the third inverter comprises a first terminal and a second terminal,
the first control terminal of the first transmission gate is coupled to an output of the decoder, the second control terminal of the first transmission gate is coupled to the second terminal of the third inverter, the input of the first transmission gate is configured to receive a signal intended to be input to the operational TSV, the output of the first transmission gate is coupled to an input of the operational TSV,
the first terminal of the third inverter is coupled to the output of the decoder, the second terminal of the third inverter is coupled to the first control terminal of the second transmission gate,
the second control terminal of the second transmission gate is coupled to the output of the decoder, the input of the second transmission gate is configured to receive the signal intended to be input to the operational TSV, the output of the second transmission gate is coupled to the input of the spare TSV.