Patent ID: 11950517
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 7:
8. A three-dimensional semiconductor memory device, comprising:
a first conductive line extending in a first direction;
a second conductive line extending in a second direction crossing the first direction;
a cell stack at an intersection of the first conductive line and the second conductive line,
the cell stack including a first electrode, a second electrode, and a third electrode, which are sequentially stacked, a switching pattern between the first electrode and the second electrode, and a variable resistance pattern between the second electrode and the third electrode;
a gapfill insulating pattern covering a side surface of the cell stack, a top surface of the gapfill insulating pattern being located between a top surface of the third electrode and a bottom surface of the third electrode; and
a barrier metal pattern between the second conductive line and the third electrode, wherein
the barrier metal pattern extends in the second direction, and
a lower width of the barrier metal pattern is larger than an upper width of the barrier metal pattern.