Patent ID: 11954358
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 20:
21. An apparatus, comprising:
a ferroelectric random access memory (FeRAM);
a dynamic random access memory (DRAM) comprising a plurality of banks; and
an interface controller coupled with the FeRAM and the DRAM, the interface controller comprising, for each bank of the plurality of banks of the DRAM, a respective first static random access memory (SRAM) buffer of a plurality of first SRAM buffers of the interface controller and a respective second SRAM buffer of a plurality of second SRAM buffers of the interface controller, the respective first SRAM buffer and the respective second SRAM buffer both assigned to the each bank of the DRAM, both configured for data transfers involving the each bank of the DRAM, and both having a storage capacity that is equal to a page size of the DRAM, the interface controller operable to:
receive a command from a system-on-a chip (SoC) to access a memory address of the FeRAM, the memory address of the FeRAM associated with a set of memory cells in a bank of the plurality of banks of the DRAM;
store first data associated with the command, based at least in part on the command, in the respective first SRAM buffer of the interface controller that is assigned to the bank of the DRAM;
transfer, based at least in part on determining that the set of memory cells in the bank of the DRAM stores second data, the second data from the set of memory cells in the bank of the DRAM to the respective second SRAM buffer of the interface controller that is assigned to the bank of the DRAM; and
transfer, based at least in part on the command and after transferring the second data from the bank of the DRAM to the respective second SRAM buffer and, the first data from the respective first SRAM buffer.