Patent ID: 11862261
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. A nonvolatile memory device comprising:
a memory cell array including a plurality of memory cells; and
processing circuitry configured to,
receive a write command, a write address and write data to be programmed,
receive offset information representing a verification level, the receiving the offset information including,
checking an input/output (I/O) pattern of the write data and determining whether the write data corresponds to a distribution deterioration pattern based on results of the checking the I/O pattern of the write data,
in response to the write data not corresponding to the distribution deterioration pattern, not receiving the offset information, and
in response to the offset information not being received, programming the write data such that all of a plurality of states are maintained, the plurality of states corresponding to a distribution of threshold voltages of memory cells, and

program the write data based on the offset information in response to the offset information being received such that at least one state among the plurality of states included in the distribution of threshold voltages of memory cells in which the write data is stored is changed.