Patent ID: 11929288
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 14:
15. A method comprising:
forming a first semiconductor layer over a first area and a second area of a substrate;
removing the first semiconductor layer from over the first area of the substrate;
forming a spacer feature on the substrate between the first and second areas of the substrate;
forming a first stack of semiconductor layers over the first area of the substrate and a second stack of semiconductor layers over the first semiconductor layer disposed over the second area of the substrate, wherein the first stack of the semiconductor layer and the second stack of semiconductor layers interface with the spacer feature after the forming of the first stack of semiconductor layers over the first area of the substrate and the second stack of semiconductor layers over the first semiconductor layer disposed over the second area of the substrate;
removing the spacer feature;
patterning the first stack of semiconductor layers; and
patterning the second stack of semiconductor layers.