Patent ID: 11929109
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory system comprising:
a first group of memory cells;
a second group of memory cells;
a first sub-word line driver abutted to the first group of memory cells, wherein the first sub-word line driver is configured to apply a first control signal to the first group of memory cells; and
a second sub-word line driver abutted to the second group of memory cells, wherein the second sub-word line driver is configured to apply a second control signal to the second group of memory cells;
wherein the first group of memory cells, the first sub-word line driver, the second sub-word line driver, and the second group of memory cells are disposed next to one another in such a sequence along a lateral direction.