Patent ID: 11886721
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A method for adjusting a memory, wherein the memory comprises a transistor, a gate of the transistor is electrically connected with a Word Line (WL) of the memory, one of a source and a drain of the transistor is electrically connected with a Bit Line (BL) of the memory, and another one of the source and the drain of the transistor is electrically connected with a storage capacitor of the memory, the method comprising:
acquiring a mapping relationship between a temperature of the transistor, a gate voltage of the transistor, and an actual time at which data is written into the memory;
acquiring a current temperature of the transistor; and
adjusting the gate voltage, based on the current temperature and the mapping relationship, so that the actual time at which the data is written into the memory corresponding to the adjusted gate voltage is within a preset writing time.