Patent ID: 11881520
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An integrated circuit structure, comprising:
a first plurality of semiconductor fins having a longest dimension along a first direction, wherein adjacent individual semiconductor fins of the first plurality of semiconductor fins are spaced apart from one another by a curved surface and by a first amount in a second direction orthogonal to the first direction;
a second plurality of semiconductor fins having a longest dimension along the first direction, wherein adjacent individual semiconductor fins of the second plurality of semiconductor fins are spaced apart from one another by a curved surface and by the first amount in the second direction, and wherein closest semiconductor fins of the first plurality of semiconductor fins and the second plurality of semiconductor fins are spaced apart from one another by a second amount in the second direction, the second amount greater than the first amount but less than twice the first amount;
a gate structure over the first plurality of semiconductor fins, over the second plurality of semiconductor fins, and continuous between the first plurality of semiconductor fins and the second plurality of semiconductor fins from a first end of the gate structure to a second end of the gate structure;
a first dielectric plug, on a first trench isolation structure, at the first end of the gate structure, the first dielectric plug having a bottommost surface below a bottommost surface of the gate structure; and
a second dielectric plug, on a second trench isolation structure, at the second end of the gate structure, the second dielectric plug having a bottommost surface below the bottommost surface of the gate structure.