Patent ID: 11929316
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A method of fabricating a semiconductor package, the method comprising:
forming a redistribution substrate that includes a dielectric pattern and a redistribution pattern buried in the dielectric pattern;
forming a seed layer on the redistribution substrate;
forming a mask pattern on the seed layer, the mask pattern having first openings and second openings;
performing a plating process in which the seed layer is used as a seed to form first substrate pads that fill the first openings and second substrate pads that fill the second openings, a height of the second substrate pads being formed higher than a height of the first substrate pads;
removing the mask pattern and an exposed portion of the seed layer;
providing a plurality of connection members on corresponding chip pads of a semiconductor chip;
placing the semiconductor chip on the redistribution substrate to allow the connection members to rest on the first substrate pads and the second substrate pads; and
performing on the connection members a reflow process to form first connection terminals that connect the first substrate pads to first chip pads of the semiconductor chip and second connection terminals that connect the second substrate pads to second the chip pads of the semiconductor chip,
wherein each of the first and second chip pads has a quadrilateral shape when viewed in cross-section,
wherein a maximum width of the first substrate pads is substantially the same as widths of the first and second chip pads, and
wherein a maximum width of the second substrate pads is less than the widths of the first and second chip pads.