Patent ID: 11874787
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. A method implemented on a platform including a plurality of central processing units (CPUs), a firmware storage device in which platform firmware is stored, and one or more controller hubs coupled to a platform control entity, each controller hub including a plurality of Input-Output (TO) interfaces, a plurality of IO pins coupled to a set of handshake wires, and coupled to a respective CPU, the plurality of CPUs including a CPU with bootable logic that is coupled to the firmware storage device and coupled to a first controller hub the method comprising:
configuring each of the plurality of controller hubs including the first controller hub to operate as an IO-expander under which the controller hub is used to expand the IO interfaces available to the CPU to which the controller hub is coupled;
booting the platform by accessing the platform firmware stored in the firmware storage device via the CPU with bootable logic;
booting the first controller hub;
coordinating booting of each of the IO-expanders other than the first controller hub via handshake signals sent between the first controller hub and the platform control entity and handshake signals sent between the platform control entity and each of those IO-expanders;
sending a platform reset handshake signal from a first IO pin of the first controller hub to the platform control entity;
for each controller hub other than the first controller hub,
receiving a wake handshake signal from the platform control entity at a second IO pin;
booting or waking the controller hub; and
when the controller hub has successfully booted or has awaken, sending a wake acknowledgement (ACK) signal from a third IO pin on the controller hub to the platform control entity;

verifying, via the platform control entity, that a wake ACK signal has been received from each controller hub other than the first controller hub; and
triggering a reset for each of the plurality of CPUs.