Patent ID: 11908554
Assignee: nan
Field: Medical technology (Instruments)
Classification: CPC G  H  Y | IPC G  H

Claim 5:
6. A method comprising:
establishing a synthesized clock counter to count the number of synthesized clock cycles between the moment a sleep signal is raised and the moment a DC-DC converter is turned off where the synthesized clock cycles are of a high frequency phase locked loop (PLL) clock signal generated by a PLL which receives a low frequency clock signal and generates the high frequency PLL clock signal and the sleep signal relates to powering down into a sleep mode an electronic circuit coupled to the DC-DC converter;
retaining the value of this synthesized clock counter during the sleep mode within a sleep counter circuit forming part of the electronic circuit; and
subtracting with the sleep counter circuit a time value established in dependence upon this retained synthesized clock counter value from a predetermined delay relating to when to turn back on the DC-DC converter; wherein
the synthesized clock cycles are of the high frequency PLL clock signal.