Patent ID: 11922132
Assignee: SHANGHAI CAMBRICON INFORMATION TECHNOLOGY CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 9:
10. A computation circuit, comprising a communication circuit and an operation circuit, wherein
the communication circuit is configured to obtain a frame image to be processed, wherein the frame image has a first painting style;
the operation circuit is configured to obtain and call an operation instruction to perform painting style conversion on the frame image to obtain a target image, wherein
the target image has a second painting style, the second style is different from the first style, and the operation instruction is a preset instruction for painting style conversion of an image,
wherein the operation circuit includes a primary operation module and a plurality of secondary operation modules, wherein the primary operation module is interconnected with the plurality of secondary operation modules by an interconnection module, and when the operation instruction is a convolution operation instruction,
the secondary operation modules are configured to implement a convolution operation of input data and a convolution kernel in a convolutional neural network algorithm, wherein the input data is the frame image and the convolutional neural network algorithm corresponds to the convolution operation instruction,
the interconnection module is configured to implement data transfer between the primary operation module and the secondary operation modules, before a forward operation of a neural network fully connected layer starts, the primary operation module sends the input data to each secondary operation module through the interconnection module, and after the computation of the secondary operation modules is completed, the interconnection module splices output scalars of the respective secondary operation modules stage by stage into an intermediate vector and sends the intermediate vector back to the primary operation module, and
the primary operation module is configured to splice intermediate vectors corresponding to all input data into an intermediate result, and perform subsequent operations on the intermediate result, wherein
the primary operation module is configured to add bias data to the intermediate result, and then perform an activation operation.