Patent ID: 11915752
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. Write circuitry for a memory device, comprising:
a comparator having a first input terminal configured to receive a reference voltage signal, a second input terminal, and an output terminal;
a reference transistor having a gate terminal connected to the output terminal of the comparator, a first S/D terminal connected to a power terminal, and a second S/D terminal connected to an indicator node, the indicator node connected to a current source and configured to generate a reference current; and
a drive transistor having a gate terminal connected to the output terminal of the comparator, a first S/D terminal connected to the power terminal, and a second S/D terminal connected to the second input terminal of the comparator and configured to output a programming signal to a bit line of a memory cell of a first memory array;
wherein the indicator node is configured to output an indicator signal based on a comparison of a current of the memory cell and the reference current.