Patent ID: 11960769
Assignee: MACRONIX INTERNATIONAL CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. A method for performing a high performance secure read of information from a memory array of a memory chip, including:
detecting by the memory chip that a command received from a host includes a command code field and a payload, wherein the command code field includes an op code indicating a continuous secure memory read command, in which information read from the memory array is encrypted by a security engine prior to output, and wherein the payload includes: an address pointing to at least one address of a plurality of addresses indicating a security region within the memory array from which information is to be read; and a configurable dummy cycle in which a specific context is to be output; and triggering performing, substantially contemporaneously:
(i) outputting a first set of information read from the memory array and encrypted by an on-chip security engine, along with the specific context used to encrypt the first set of information;
(ii) performing encryption upon a second set of information read from the memory array through the on-chip security engine; and
(iii) reading a third set of information from the memory array into a buffer to be encrypted by the on-chip security engine; and
repeating activities (i)-(iii) until a specified end of a secure area of addresses in the memory array is reached; thereby providing a continuous output of encrypted information along with the specific context.