Patent ID: 11862638
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A method comprising:
forming a fin and protruding above an isolation region;
forming a dummy gate on a first sidewall of the fin, a second sidewall of the fin, and a top surface of the isolation region;
forming a gate spacer adjacent the dummy gate, a sidewall of the gate spacer forming a first angle with the first sidewall of the fin in a top-down view, the sidewall of the gate spacer forming a second angle with the second sidewall of the fin in the top-down view;
recessing the dummy gate to expose the sidewall of the gate spacer;
treating the gate spacer to decrease the first angle and the second angle by inwardly bowing the sidewall of the gate spacer towards the dummy gate in the top-down view;
after treating the gate spacer, removing remaining portions of the dummy gate to expose the fin; and
forming a gate structure on the first sidewall of the fin, the second sidewall of the fin, and the top surface of the isolation region.