Patent ID: 11881830
Assignee: REALTEK SEMICONDUCTOR CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 4:
5. A filter circuit, comprising:
a plurality of registers, each being configured to store an input;
a switch circuit, configured to adjust arrangement of a series of coefficients according to a count value to generate a series of rearranged coefficients, wherein the count value is accumulated in response to reception of a new input of the filter circuit;
a plurality of multipliers, coupled to the switch circuit and the registers and configured to receive the inputs from the registers and receive the series of rearranged coefficients from the switch circuit, wherein each multiplier is configured to generate a multiplication result according to the received input and the received coefficient; and
a summation circuit, coupled to the multipliers and configured to sum up the multiplication results to generate an output;
wherein when the filter circuit receives the new input, the new input is written in one of the registers to replace the oldest input among the inputs currently being stored in the registers.