Patent ID: 11921392
Assignee: JAPAN DISPLAY INC.
Field: Optics (Instruments)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A semiconductor device comprising:
an insulating substrate;
a thin-film transistor formed on the insulating substrate including a semiconductor layer and a gate electrode;
a first metal layer between the insulating substrate and the semiconductor layer;
a first insulating layer between the first metal layer and the semiconductor layer;
a second insulating layer on the semiconductor layer;
a second metal layer on the second insulating layer that at least partly overlaps the semiconductor layer; and
a third metal layer that connects the first metal layer and the second metal layer via one contact hole penetrating the first insulating film and the second insulating film; wherein
an area of the first metal layer is larger than an area where the semiconductor layer and the second metal layer overlap each other, in plan view,
the third metal layer directly contacts a top surface and a side surface of the second metal layer and a top surface of the first metal layer.