Patent ID: 11923367
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 0:
1. An integrated circuit (IC) device, comprising:
a semiconductor substrate having an n-type transistor region and a p-type transistor region;
a first plurality of stacked semiconductor layers in the p-type transistor region and a second plurality of stacked semiconductor layers in the n-type transistor region;
a gate dielectric layer that wraps around each of the first and second plurality of stacked semiconductor layers;
a first metal gate in the p-type transistor region, the first metal gate having a work function metal layer and a first fill metal layer, wherein the work function metal layer wraps around and is in direct contact with the gate dielectric layer and the first fill metal layer wraps around and is in direct contact with the work function metal layer;
a second metal gate in the n-type transistor region, the second metal gate having a second fill metal layer that wraps around and is in direct contact with the gate dielectric layer, wherein the second fill metal layer applies a tensile stress over the second plurality of stacked semiconductor layers and includes a conductive material with a work function about equal to or lower than 4.3 eV;
a first gate contact feature over and directly contacting the first fill metal layer of the first metal gate;
a second gate contact feature over and directly contacting the second fill metal layer of the second metal gate; and
an interlayer dielectric layer on sidewalls of the first and the second gate contacts.