Patent ID: 11886733
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A circuit for testing a memory, comprising:
a switch control circuit, configured to input a trigger signal for triggering potential of a Word Line (WL) signal end in a to-be-tested circuit to meet a preset potential suspension range,
wherein the switch control circuit is connected between a discharge end and a negative bias signal end of a Sub Wordline Drive (SWD), and the to-be-tested circuit is a corresponding circuit in a single memory;
wherein the switch control circuit comprises: a signal input circuit and a transistor;
wherein a first end of the transistor is connected with the discharge end, a second end of the transistor is connected with the negative bias signal end, and a control end of the transistor is connected with an output end of the signal input circuit;
wherein the signal input circuit is a NAND gate element, an output end of the NAND gate element is connected with the control end of the transistor, a first input end of the NAND gate element is configured to input an Address Signal (RA), and a second input end of the NAND gate element is configured to input the trigger signal.