Patent ID: 11956376
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 13:
14. The memory device according to claim 13, wherein
the first bit line sense amplifier and each of the second bit line sense amplifiers includes a pair of PMOS transistors and a pair of NMOS transistors; and
the memory device further comprises processing circuitry configured to
drive the pair of PMOS transistors and the pair of NMOS transistors of the first bit line sense amplifier in a first order in a presensing period, the presensing period being a period in which voltages of the plurality of bit lines and voltages of a plurality of complementary bit lines corresponding to the plurality of bit lines are presensed, and
drive the pair of PMOS transistors and the pair of NMOS transistors of each of the second bit line sense amplifiers in a second order in the presensing period, the first order being different from the second order.