Patent ID: 11942985
Assignee: nan
Field: Telecommunications (Electrical engineering)
Classification: CPC H | IPC H

Claim 1:
2. The 10G rate OLT terminal transceiver integrated chip based on XGSPON and DFB laser according to claim 1, wherein the burst mode receiver RX comprises a pre-amplifier Pre_Amplifier, a level detector LEVEL DETECTOR, a 10G burst-mode limiting amplifier BurstLA_10G, a current mode logic output buffer CML BUFFER, a signal detection output buffer BUFFER and a fast recovery module,
a non-inverting input and an inverting input of the pre-amplifier Pre_Amplifier are arranged to receive a burst data packet (the electrical signal) from the burst transimpedance amplifier TIA;
the fast recovery module is arranged to provide a fast recovery circuit to ensure a timing sequence is correct, so that physical collision of two adjacently time sequenced burst data packets is avoided;
an output terminal of the pre-amplifier Pre_Amplifier is simultaneously connected to an input terminal of the 10G burst-mode limiting amplifier BurstLA_10G and an input terminal of the level detector LEVEL DETECTOR;
an output terminal of the 10G burst-mode limiting amplifier BurstLA_10G is connected to an input terminal of the current mode logic output buffer CML BUFFER;
an output terminal of the level detector LEVEL DETECTOR is simultaneously connected to an input terminal of the signal detection output buffer BUFFER and an on/off control terminal of the current mode logic output buffer CML BUFFER;
two output terminals of the current mode logic output buffer CML BUFFER are connected to output pins RX_OUTP and RX_OUTN of the burst mode receiver RX respectively;
an output terminal of the signal detection output buffer BUFFER is connected to a chip pin RX_SD, and the burst mode receiver RX sends an amplitude detection result to the host through the chip pin RX_SD;
wherein in response to a reset signal sent by a chip pin LA_RESET from the host, the chip sends a feedback signal to the host through the pin RX_SD.