Patent ID: 11967504
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 16:
17. A method comprising:
removing a first dummy gate structure to form a first recess and removing a second dummy gate structure to form a second recess;
depositing a sacrificial layer in the first recess and the second recess with a flowable chemical vapor deposition (CVD) process;
patterning the sacrificial layer to remove the sacrificial layer from the first recess while leaving a remaining portion of the sacrificial layer in the second recess, the remaining portion of the sacrificial layer being disposed between a first nanostructure and a second nanostructure;
depositing a first work function metal in the first recess and the second recess, wherein the sacrificial layer blocks the deposition of the first work function metal between the first nanostructure and the second nanostructure;
patterning the first work function metal to remove the first work function metal from the second recess while leaving the first work function metal in the first recess;
removing the remaining portion of the sacrificial layer;
depositing a second work function metal in the second recess; and
depositing a fill metal over the first work function metal in the first recess and over the second work function metal in the second recess.