Patent ID: 11900112
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A processor comprising:
an instruction fetch unit configured to receive a vector reverse instruction and a second instruction, wherein the vector reverse instruction specifies whether the processor is to perform the vector reverse instruction and the second instruction in parallel and further specifies that the vector reverse instruction is a single vector reverse operation;
a register file that includes a source register configured to store a first vector that includes a set of elements stored in a first order and a destination register;
a functional unit coupled to the register file and configured to, based on the vector reverse instruction:
receive the first vector from the source register;
reverse an order of the set of elements of the first vector to produce a second vector that includes all elements of the set of elements; and
cause all elements of the second vector to be stored in the destination register in a second order that is reverse of the first order,

wherein the vector reverse instruction is completed in a single operation.