Patent ID: 11955463
Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An apparatus comprising:
a substrate; and
a die stack disposed on the substrate, the die stack comprising:
a plurality of directly bonded dies comprising a first die having a first hybrid bonding surface and a second die having a second hybrid bonding surface, wherein the first bonding surface of the first die is hybrid bonded to the second bonding surface of the second die without an adhesive;
a top die on the plurality of directly bonded dies; and
a non-die layer disposed between the top die and the plurality of directly bonded dies, wherein the non-die layer comprises at least one compliant layer;

a first lateral die support layer disposed along at least a portion of a sidewall of the first die, an entirety of the first lateral die support layer disposed laterally outside a footprint of the first die; and
a second lateral die support layer disposed laterally adjacent the top die and at least a portion of the first lateral die support layer, an entirety of the second lateral die support layer disposed laterally outside the die stack.