Patent ID: 11956947
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 0:
1. A one-time programmable (OTP) memory cell system, comprising:
a first antifuse transistor, wherein a gate terminal of the first antifuse transistor is connected to a first word line configured to receive a first signal, and the first antifuse transistor is selectable between a first state and a second state in response to the first signal;
a first selection transistor connected between the first antifuse transistor and a bit line, wherein a gate terminal of the first selection transistor is connected to a second word line configured to receive a second signal, and the first selection transistor is configured to provide access to the first antifuse transistor in response to the second signal;
a second antifuse transistor, wherein a gate terminal of the second antifuse transistor is connected to a third word line configured to receive a third signal, and the second antifuse transistor is selectable between the first state and the second state in response to the third signal; and
a second selection transistor connected between the second antifuse transistor and the bit line, wherein a gate terminal of the second selection transistor is connected to a forth word line configured to receive a third signal, and the second selection transistor is configured to provide access to the second antifuse transistor in response to the fourth signal;
wherein:
a first terminal of the first antifuse transistor is a vacancy terminal, and a second terminal of the first antifuse transistor is connected to the first selection transistor, and
a first terminal of the second antifuse transistor is a floating terminal including a contact structure, and a second terminal of the second antifuse transistor is connected to the second selection transistor.