Patent ID: 11861230
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 8:
9. A controller that controls a memory device, comprising:
a plurality of operation modules including a processor and a memory; and
a clock generator suitable for providing the plurality of operation modules with clock signals,
wherein, when the processor detects a change in actual performance of the controller and the memory device or a change in a host request pattern, the processor initializes a clock frequency set corresponding to the clock signals provided to the plurality of operation modules, determines a target performance on the basis of the actual performance after the clock frequency set is initialized, determines an optimal clock frequency set such that the actual performance is maintained greater than or equal to the target performance, and provides the plurality of operation modules with clock signals according to the optimal clock frequency set,
wherein the processor determines the optimal clock frequency set by repeatedly performing an operation of changing at least one clock frequency included in the clock frequency set and an operation of monitoring the actual performance after the clock frequency is changed, and
wherein the optimal clock frequency set is a clock frequency set such that power consumption of the controller and the memory device is minimized, among clock frequency sets so that the actual performance is maintained greater than or equal to the target performance.