Patent ID: 11928021
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. A memory device, comprising:
an error correction code (ECC) system configured to detect one or more bit errors in data stored by a memory bank; and
an address fault detection system configured to:
intercept a read address denoting a location to read data from the memory bank;
encode the read address to generate an encoded read address;
read a stored code by using the read address, wherein the stored code is generated based on a write address when the data is written to the memory bank;
decode the stored code based on the encoded read address;
detect an address fault by using the decoded stored code during reading the data from the read address; and
raise an address fault indication flag if the address fault is detected, which is indicated by a corruption of the data, wherein the address fault detection system or a portion of the address fault detection system is included in the ECC system.