Patent ID: 11903219
Assignee: KEPLER COMPUTING INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 16:
17. An apparatus comprising:
a first transistor having a first gate terminal coupled to a word-line, a first source terminal couple to a bit-line, and a first drain terminal coupled to a storage node;
a second transistor coupled to the first transistor, wherein the second transistor includes a second gate terminal coupled to the storage node, a second source terminal couple to a sense line, and a second drain terminal coupled to a bias;
a stack of vertical vias which is coupled to the storage node;
a plurality of metal layers coupled to the stack of vertical vias; and
a plurality of capacitors having a first terminal coupled to the plurality of metal layers, wherein the plurality of capacitors includes capacitors on either side of the stack of vertical vias, wherein a second terminal of an individual capacitor of the plurality of capacitors is coupled to an individual plate-line, and wherein the plurality of capacitors are planar capacitors.