Patent ID: 11929127
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A system comprising:
a memory device comprising a plurality of memory cells, wherein a first subset of the plurality of memory cells store a first logic state and a second subset of the plurality of memory cells store a second logic state; and
a processing device operatively coupled to the memory device the processing device to perform operations comprising:
determining to perform a rewrite operation on at least a portion of the plurality of memory cells;
incrementing a counter of a number of rewrite operations performed at the second subset of memory cells by a first value in response to determining to perform the rewrite on at least the portion of the plurality of memory cells;
determining that the number of rewrite operations performed at the second subset of the plurality of memory cells fail to satisfy a threshold criterion based on comparing the number of rewrite operations performed to the threshold criterion;
causing a rewrite of data stored at the second subset of the plurality of memory cells in response to determining the number of rewrite operations performed at the second subset of the plurality of memory cells fail to satisfy the threshold criterion; and
causing the counter of the number of rewrite operations performed at the second subset of memory cells to decrement by a second value based at least in part on rewriting the data stored at the first subset of the plurality of memory cells.