Patent ID: 11894853
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 16:
17. The semiconductor memory of claim 16, wherein the controllable storage circuit comprises:
a first controllable storage circuit, a first end of the first controllable storage circuit being connected with the second end of the phase calibration circuit, a second end of the first controllable storage circuit being connected with a third end of the second logical circuit, a third end of the first controllable storage circuit being connected with the first end of the second detection circuit, wherein the first controllable storage circuit is configured to generate a first storage control signal according to a period of the second signal, and receive and store, according to the first storage control signal, the first phase difference pulse signal or release the stored first phase difference pulse signal; and
a second controllable storage circuit, a first end of the second controllable storage circuit being connected with the first end of the phase calibration circuit, a second end of the second controllable storage circuit being connected with a third end of the third logical circuit, a third end of the second controllable storage circuit being connected with the first end of the second detection circuit, wherein the second controllable storage circuit is configured to generate a second storage control signal according to a period of the first signal, receive the second phase difference pulse signal, and perform at least one of storage or release of the second phase difference pulse signal according to the second storage control signal.