Patent ID: 11889768
Assignee: FERDINAND-BRAUN-INSTITUT GGMBH, LEIBNIZ-INSTITUT FÜR HÖCHSTFREQUENZTECHNIK
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A method for producing a gate structure according to the generic term of claim 9, characterized in that before developing a gate contact element (240) disposed within the recess (222), the following further steps are comprised:
c′) applying an intermediate layer (230) with a third stress within the recess (222), wherein the intermediate layer (230) is developed between the contact element (240) and the passivation layer (220);
c″) producing a second recess (232) in the intermediate layer (230), wherein the second recess (232) extends through the entire intermediate layer (230) in the direction of the active layer (212);
f) wherein the development of at least one layer (120, 220, 150, 250) disposed above the active layer (112, 212) is conducted in a tensile stressed or compressively stressed manner in the area around the contact element (140, 240) with a normal tension of |σ|>200 MPa, wherein via the individual stresses in the area around the contact element (140, 240), a resulting force on the boundary area between the passivation layer (120, 220) and the active layer (112, 212) is set, which influences via the piezoelectric effect the electron density in the active layer (112, 212) in the area below the contact element (140, 240), wherein the normal tensions of stressed layers lie in the range between ±4 GPa.