Patent ID: 11901035
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 6:
7. The system of claim 3, wherein:
the first set of one or more of the memory cells is contained within a first collection of one or more of the core dies;
the second set of one or more of the memory cells is contained within a second collection of one or more of the core dies;
in terms of membership, the first and second collections are non-overlapping of each other; and
the DDVFS device is further configured to perform the following:
adjusting the first clock or the first PS voltage of the first collection resulting in a first core-die-wide adjustment of temperatures amongst the memory cells of the core dies of the first collection; and
adjusting the second clock or the second PS voltage of the second collection resulting in a second core-die-wide adjustment of temperatures amongst the memory cells of the core dies of the second collection.