Patent ID: 11900065
Assignee: APPIAN CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. At least one non-transitory computer-readable storage device storing instructions that, when executed by one or more processors, cause the one or more processors to perform operations comprising:
identifying a baseline expression specifying a first element and a second element that are each to be evaluated on a primary thread of the one or more processors;
determining that evaluation of the second element within the baseline expression involves accessing at least one external resource;
based on determining that evaluation of the second element within the baseline expression involves accessing the at least one external resource, grouping the first element and the second element into a parse tree representation, the parse tree representation comprising a hierarchal structure of nodes reflecting a manner in which the first element and the second element are evaluated in multiple threads associated with the one or more processors;
generating a transformed expression corresponding to the baseline expression based on the hierarchal structure of nodes specified by the parse tree representation,
wherein the transformed expression comprises instructions that, when the transformed expression is evaluated by one or more processors, cause the one or more processors to:
(i) evaluate the first element in the primary thread, and
(ii) evaluate the second element in a secondary thread that runs in parallel with the primary thread; and

providing the transformed expression for output.