Patent ID: 11907040
Assignee: NXP USA, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G  H

Claim 11:
12. A processor system comprising a processor coupled to a memory comprising a plurality of memory banks, the memory further comprising a region configurable as a heap region, wherein the processor is operable to execute instructions comprising one or more cryptographic operations; and wherein the processor system is configured to:
allocate at least one memory bank to the heap region dependent on a predetermined memory size required for execution of at least one cryptographic operation;
allocate at least one further memory bank to the heap region; and
further configured to switch from a first operating mode to a second operating mode by:
setting the at least one memory bank to an active state;
setting the at least one further memory bank to an active state; and

to switch from the second operating mode to the first operating mode by:
setting the at least one memory bank to a retention state;
setting the at least one further memory bank to a power-down state.