Patent ID: 11863222
Assignee: CISCO TECHNOLOGY, INC.
Field: Telecommunications (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. An apparatus comprising:
a plurality of sub-rate receiver lanes each of which is configured to receive an analog receive signal from an analog front-end and produce digital sub-rate receiver data, wherein each of the plurality of sub-rate receiver lanes includes an equalizer having a number of taps;
one or more first digital-to-analog converters (DACs) shared across the plurality of sub-rate receiver lanes;
one or more second DACs for each sub-rate receiver lane of the plurality of sub-rate receiver lanes, wherein the one or more second DACs of a respective sub-rate receiver lane are configured to provide output to be combined with an output of a corresponding one of the one or more first DACs during processing of the analog receive signal in the respective sub-rate receiver lane to account for a sub-rate receiver lane specific offset with respect to a corresponding one of the one or more first DACs; and
a logic circuit configured to generate an average tap weight DAC control for each of the one or more first DACs and a mismatch tap cancellation DAC control for each second DAC in each of the plurality of sub-rate receiver lanes.