Patent ID: 11862700
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 13:
14. A method for forming a semiconductor device structure, comprising:
forming first and second fin structures from a substrate, wherein each of first and second fin structures comprises first plurality of semiconductor layers and second plurality of semiconductor layers vertically stacked;
forming an insulation region around a portion of exposed surfaces of the first and second fin structures;
fondling a first dielectric wall over the insulation region between the first fin structures and the second fin structures;
forming a second dielectric wall and a third dielectric wall so that the second dielectric wall is separated from an end of the first semiconductor layer by a first distance;
removing the second plurality of semiconductor layers from the first and second fin structures, wherein at least the two adjacent first semiconductor layers of the first fin structure define a second distance greater than the first distance;
depositing an interfacial layer (IL) over exposed surfaces of the first plurality of semiconductor layers of the first and second fin structures;
depositing a high-K (HK) dielectric layer on the IL and exposed surfaces of the first, second, and third dielectric walls;
forming a dummy material over the first dielectric wall, the second dielectric wall, the third dielectric wall, and the first plurality of semiconductor layers so that the dummy material over the second and third dielectric walls and the dummy material over the first plurality of semiconductor layers are merged, and the dummy material partially fills regions between adjacent first semiconductor layers of the first fin structure;
removing a portion of the dummy material over the first plurality of semiconductor layers of the second fin structure; and
surrounding at least three surfaces of each of the first plurality of semiconductor layers with a first gate electrode layer, and the first gate electrode layer partially fills regions between adjacent first semiconductor layers of the first plurality of semiconductor layers of each first and second fin structure.