Patent ID: 11955481
Assignee: STMICROELECTRONICS (CROLLES 2) SAS
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A microelectronic device that includes a PNP transistor and an NPN transistor, comprising:
a semiconductor substrate that is P-type doped;
an N+ doped isolating well for the PNP transistor in the semiconductor substrate;
a first epitaxial semiconductor layer extending on the N+ doped isolating well, and on the semiconductor substrate;
a P+ doped region including a first portion in the N+ doped isolating well and a second portion in the first epitaxial semiconductor layer;
an N+ doped well of the NPN transistor at an upper surface of the first epitaxial semiconductor layer, wherein at least part of said N+ doped well extends from the upper surface and through the first epitaxial semiconductor layer to contact the semiconductor substrate;
a second epitaxial semiconductor layer extending on an upper surface of the N+ doped well and on the upper surface of the first epitaxial semiconductor layer;
a P doped region including a third portion in the second epitaxial semiconductor layer and a fourth portion in the first epitaxial semiconductor layer, wherein the P doped region forms a collector of the PNP transistor, and wherein said P doped region extends through the second epitaxial semiconductor layer and in the first epitaxial semiconductor layer to contact the P+ doped region;
a base region of the PNP transistor in contact with the P doped region;
an N doped region in the second epitaxial semiconductor layer that forms a collector of the NPN transistor, wherein at least a portion of the N doped region extends to contact the N+ doped well; and
a base region of the NPN transistor in contact with the N doped region.