Patent ID: 11894462
Assignee: ADEIA SEMICONDUCTOR SOLUTIONS LLC
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method comprising:
providing a substrate having thereon a layer of epitaxial channel material;
patterning a hardmask above the layer of epitaxial channel material;
performing a first etch to a first depth, using the hardmask as a mask, to form an upper portion of a fin, wherein the first depth extends beyond a bottom surface of the layer of epitaxial channel material;
forming a liner over exposed surfaces of the upper portion of the fin;
performing a second etch to a second depth, using the liner as a mask, to form a lower portion of the fin;
removing the liner; and
forming a gate dielectric on exposed surfaces of the upper portion of the fin, wherein the gate dielectric extends beyond the bottom surface of the layer of epitaxial channel material.