Patent ID: 11862218
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 9:
10. A memory device, comprising:
an MTJ memory cell configured to switch between a first data state and a second data state, the first data state having a first resistance and the second data state having a second resistance greater than the first resistance, wherein the MTJ memory cell comprises 3 terminals;
a reference cell coupled in parallel with the MTJ memory cell;
a read bias circuit connected to the MTJ memory cell and the reference cell and configured to provide a reading bias respectively for the MTJ memory cell and the reference cell; and
a first non-linear resistance device connected in series and between the MTJ memory cell and the read bias circuit, wherein the first non-linear resistance device is configured to provide a first resistance when conducting a first current and a second resistance greater than the first resistance when conducting a second current smaller than the first current.