Patent ID: 11880319
Assignee: NETLIST, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A method of operation in a host system having a system memory controller, comprising:
at a memory subsystem coupled to the system memory controller, the memory subsystem including a printed circuit board, a memory subsystem controller on the printed circuit board, and dynamic random access memory elements on the printed circuit board, the memory subsystem controller having an open drain output, wherein the memory subsystem is configured to provide a first signaling interface via the open drain output during normal operations and a second signaling interface via the open drain output during an initialization operation including initialization operation sequences, wherein the second signaling interface is distinct from the first signaling interface and the initialization operation is distinct from any of the normal operations,
performing the normal memory read or write operations, including receiving address and command signals associated with the memory read or write operations, controlling the dynamic random access memory elements in accordance with the address and command signals, and outputting via the open drain output a parity error signal in response to a parity error having occurred during the normal memory read or write operations; and
performing the initialization operation, including outputting via the open drain output a signal related to one or more parts of the initialization operation sequences.