Patent ID: 11956943
Assignee: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A method for manufacturing a memory, comprising steps of:
forming a memory cell comprising a transistor on one side of a substrate, the forming comprises:
preparing a secondary gate, a second dielectric layer, a semiconductor layer, a first dielectric layer, a primary gate, a word line connected to the primary gate, and a first insulating layer sequentially on one side of a substrate, the semiconductor layer comprising a source contact region, a channel region and a drain contact region connected sequentially;
etching the first insulating layer and the first dielectric layer sequentially to obtain a first through hole exposing at least part of the source contact region of the semiconductor layer;
etching the first insulating layer, the first dielectric layer and the second dielectric layer sequentially to obtain a second through hole exposing at least part of the drain contact region of the semiconductor layer and part of the secondary gate;
manufacturing conducting materials in the first through hole and the second through hole, respectively, so that a first via hole connected to the source contact region of the semiconductor layer is formed in the first through hole and a second via hole connected to the secondary gate and the drain contact region of the semiconductor layer is formed in the second through hole; and
manufacturing a bit line on the first via hole so that the bit line is electrically connected to the source contact region;
wherein the memory cell further comprises a storage structure comprising the secondary gate,
wherein a node capacitors between the secondary gate and the drain being used as a storage capacitor of the memory cell, so that data “1” or “0” is stored in the storage capacitor in a writing state, and whether “1” or “0” being stored is determined according to ON or OFF of the transistor in a reading state,
wherein the storage structure further comprises a first electrode, the storage capacitor being formed between the secondary gate and the first electrode, and
wherein the primary gate is located between the substrate and the semiconductor layer, the secondary gate is located on one side of the semiconductor layer away from the substrate, and the first electrode is located on one side of the secondary gate away from the substrate.