Patent ID: 11973105
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An integrated circuit structure, comprising:
a non-planar transistor comprising: a plurality of metal gates above a substrate and formed in a first dielectric layer, wherein the plurality of metal gates include a first set of one or more metal gates, a second set of one or more metal gates, and a third set of one or more metal gates, the third set of one or more metal gates located between the first set of one or more metal gates and the second set of one or more metal gates, ones of the plurality of metal gates comprising a workfunction layer and a gate oxide layer along sidewalls of the first dielectric layer, and respective source/drains, the respective source/drains formed between the first set of one or more metal gates and the third set of one or more metal gates, and between the third set of one or more metal gates and the second set of one or more metal gates;
a field effect (FE) inter-dielectric layer (ILD) formed over the first dielectric layer of the plurality of metal gates, the FE ILD comprising at least a bottom dielectric layer formed over and in contact with the first dielectric layer of the plurality of metal gates, and a top dielectric layer formed over the bottom dielectric layer;
a resistor comprising a thin-film metallic material over and on the bottom dielectric layer and extending over ones of the third set of one or more metal gates; and
a hardmask material over and on the resistor within the top dielectric layer.