Patent ID: 11948981
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method comprising:
forming a dummy gate stack over a semiconductor region;
forming epitaxial source/drain regions on opposite sides of the dummy gate stack;
removing the dummy gate stack to form a trench;
depositing a gate dielectric layer extending into the trench;
depositing a work-function layer over the gate dielectric layer, wherein the work-function layer comprises a seam therein;
depositing a silicon-containing layer to fill the seam, wherein at a time the depositing the silicon-containing layer is started, some portions of the seam are sealed by the work-function layer, and in a top view of the work-function layer, the seam is separated as discrete portions; and
performing a planarization process to remove excess portions of the silicon-containing layer, the work-function layer, and the gate dielectric layer, with remaining portions of the silicon-containing layer, the work-function layer, and the gate dielectric layer forming a gate stack.