Patent ID: 11948942
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 17:
18. An integrated circuit device, comprising:
a fin-type active area along a first horizontal direction on a substrate, the fin-type active area including a fin top and a recess, and a level of a lowermost surface of the recess being less than a level of the fin top in a vertical direction;
a pair of nanosheet stacks on the fin-type active area, each of the pair of nanosheet stacks including at least one nanosheet on the fin top, and the at least one nanosheet being spaced apart from the fin top in the vertical direction;
a device isolation layer on opposite sidewalls of the fin-type active area;
a pair of gate structures extending along a second horizontal direction crossing the first horizontal direction on the substrate, each of the pair of gate structures surrounding the at least one nanosheet in each of the pair of nanosheet stacks on the fin-type active area; and
a source/drain area on the recess, the source/drain area being in contact with the at least one nanosheet in each of the pair of nanosheet stacks,
wherein the source/drain area includes:
an outer blocking layer contacting the fin-type active area and the pair of nanosheet stacks, the outer blocking layer having a first Si1-xGex layer, where 0<x<0.15,
an inner blocking layer on the outer blocking layer, the inner blocking layer including a Si layer, and at least a portion of the inner blocking layer having a width greater than a width of the outer blocking layer in the first horizontal direction, and
a main body layer on the inner blocking layer, the main body layer including a second Si1-xGex layer, where 0.15≤x<0.7, and
wherein a first level of a lowermost surface of the outer blocking layer is lower than the level of the fin top in the vertical direction.