Patent ID: 11948909
Assignee: QUALCOMM INCORPORATED
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 22:
23. A method for fabricating a package, comprising:
providing a second integrated device comprising a second plurality of interconnects and a plurality of solder interconnects coupled to the second plurality of interconnects;
providing an underfill at least partially surrounding the plurality of solder interconnects;
providing a polymer layer and a plurality of spacer balls over the second integrated device; and
coupling a first integrated device comprising a first plurality of interconnects, to the second integrated device such that the second integrated device is coupled to the first integrated device through the second plurality of interconnects, the plurality of solder interconnects and the first plurality of interconnects,
wherein the first integrated device is coupled to the second integrated device such that the polymer layer and the plurality of spacer balls are located between the first integrated device and the second integrated device;
wherein a portion of the polymer layer at least partially surrounds the plurality of spacer balls and is laterally adjacent to the underfill and in direct contact with the underfill.