Patent ID: 11961556
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 14:
15. A memory device, comprising:
an array of memory cells, wherein the memory device is configured to receive an access command for a memory cell of the array of memory cells, the memory cell coupled with a first access line and a second access line; and
one or more drivers configured to route a current through the memory cell, the first access line, a first socket coupled with the first access line, the second access line, and a second socket coupled with the second access line,
wherein:
the first socket is included in a first row of sockets that is non-orthogonal to the first access line;
the second socket is included in a second row of sockets that is parallel to the first row and non-orthogonal to the second access line; and
the memory device is configured to read or write the memory cell based at least in part on the current.