Patent ID: 11937434
Assignee: MICROCHIP TECHNOLOGY INCORPORATED
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of forming an integrated circuit structure including a ferroelectric random access memory capacitor, the method comprising:
forming a tub opening and a via opening in a dielectric region, wherein the via opening is laterally spaced apart from the tub opening;
concurrently forming a cup-shaped bottom electrode contact in the tub opening and a via in the via opening;
forming a cup-shaped bottom electrode in an interior opening defined by the cup-shaped bottom electrode contact;
forming a cup-shaped ferroelectric element in an interior opening defined by the cup-shaped bottom electrode;
forming a top electrode in an interior opening defined by the cup-shaped ferroelectric layer; and
forming an upper metal layer over the dielectric region, the upper metal layer including a capacitor contact in conductive contact with the top electrode;
wherein the cup-shaped bottom electrode, cup-shaped ferroelectric element, and top electrode define the ferroelectric random access memory capacitor.