Patent ID: 11903183
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 13:
14. A method for forming arrays of vertically stacked memory cells, having multiple multi-direction conductive lines, comprising:
forming a number of layers, in repeating iterations vertically to form a vertical stack, the layers comprising: a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer having a conductive line formed in a horizontal plane therein;
the second dielectric material layer having multiple multi-direction horizontal conductive lines has a first portion extending in a first horizontal direction and a second portion extending in a second horizontal direction at an angle to the first horizontal direction and wherein the second portions are laterally spaced with respect to each other to allow for vertical interconnections to be attached to the second portions;
performing a removal process in repeating vertical iterations at an area that includes at least a section of the second portion of the conductive line to form a staircase contact structure, comprising:
selectively removing a first portion of each layer of a first group of layers of the number of layers by removing the first portion of each layer of the first group of layers between a reference line and a first lateral distance from the reference line;
selectively removing a portion of each layer of a second group of layers of the number of layers by removing the portion of each layer of the second group of layers between the reference line and a second distance back from the reference line; and
selectively removing a second portion of each layer of the first group of layers of the number of layers by removing the second portion of each layer of the first group of layers between the reference line and a third distance back from the reference line and wherein the third distance is greater than the second distance.