Patent ID: 11915124
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. A system comprising:
a block of memory comprising:
a first memory array configured to store:
a number of incoming connections of a number of destination neurons, each of the number of incoming connections include a delay value and an incoming neuron identification, wherein each of the number of incoming connections are grouped together based on the delay value and wherein each of the delay values corresponds to a time interval in a series of time intervals of a spiking neural network (SNN); and
a second memory array configured to store:
a number of pre-synaptic spike events from respective source neurons, wherein each pre-synaptic spike event includes an incoming neuron identification, and the number of pre-synaptic spike events are grouped together by the time interval in a series of time intervals of the SNN; and
a filter configured to determine a match between an incoming neuron identification of a pre-synaptic spike event corresponding to a first time interval and an incoming neuron identification of an incoming connection corresponding to the first time interval.