Patent ID: 11869929
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for manufacturing a laminated capacitor, comprising:
providing a substrate;
forming a first isolation insulation spacer and a plurality of discrete bottom bonding pads arranged in the first isolation insulation spacer on the substrate;
forming a first sub-capacitor structure on the first isolation insulation spacer and the bottom bonding pads, which comprises a plurality of discrete bottom electrodes, a plurality of discrete top electrodes, and a dielectric medium located between the bottom electrodes and the top electrodes, wherein the plurality of bottom bonding pads are respectively electrically connected with the plurality of bottom electrodes in one-to-one correspondence; and
performing an operation of sequentially forming a nth connection structure and a nth sub-capacitor structure on the first sub-capacitor structure from n=1 to n=N, wherein N is an integer greater than or equal to 1,
wherein the laminated capacitor finally has N connection structures and N+1 sub-capacitor structures which are alternately arranged along a direction perpendicular to the substrate.