Patent ID: 11935586
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device, comprising:
a memory array comprising a plurality of memory cells arranged in a plurality of columns and a plurality of rows, wherein the memory cells in each of the plurality of columns comprise first memory cells and second memory cells alternately arranged along a column direction of the plurality of columns;
a first computation circuit coupled to the first memory cells in each of the plurality of columns, and configured to generate first output data corresponding to a first computation performed on first weight data stored in the first memory cells; and
a second computation circuit coupled to the second memory cells in each of the plurality of columns, and configured to generate second output data corresponding to a second computation performed on second weight data stored in the second memory cells,
wherein in each of the plurality of columns, at least one of the first memory cells is arranged between two of the second memory cells.