Patent ID: 11963368
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 0:
1. A memory device, comprising:
a dielectric fin formed over a substrate;
a memory cell disposed along and directly contacting a flat surface of a first sidewall of the dielectric fin, the memory cell comprising: a first conductor layer, a selector layer, a resistive material layer, and a second-conductor layer, wherein each of the first conductor layer, the selector layer, the resistive material layer, and the second conductor layer directly contact the first sidewall, wherein lower and upper boundaries of the selector layer are each tilted away from the flat surface by an angle, wherein the angle is less than 90 degrees; and
a capping layer disposed along and directly contacting each of the first conductor layer, the selector layer, the resistive material layer, and the second conductor layer such that the memory cell is disposed directly between the capping layer and the dielectric fin.