Patent ID: 11963351
Assignee: SK HYNIX INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A method of manufacturing a semiconductor memory device, the method comprising:
stacking first material layers and second material layers alternately on a support substrate including a chip region and a scribe region;
forming a dummy groove passing through the first material layers and the second material layers to expose the support substrate in the scribe region;
forming a dummy pattern in the dummy groove to define a gap in a central area of the dummy groove;
forming a circuit structure including a semiconductor substrate;
overlapping the support substrate with the semiconductor substrate so that the dummy pattern is disposed between the semiconductor substrate and the support substrate;
removing the support substrate;
forming a cavity inside the semiconductor substrate, wherein the cavity overlaps the gap in the dummy pattern spaced apart from the cavity; and
propagating cracks from the cavity to the gap in the dummy pattern thereby separating the first material layers and the second material layers into chip patterns.