Patent ID: 11916077
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method, comprising:
routing a reference metal line to couple to a first source/drain terminal of a transistor with a gate terminal, the first source/drain terminal, and a second source/drain terminal;
routing, at a same interconnect level as the reference metal line, a local interconnect structure to couple to the gate terminal of the transistor and to an other gate terminal of an other transistor;
routing, above an interconnect level of the local interconnect structure, a first interconnect structure to couple to the second source/drain terminal; and
routing, above the interconnect level of the local interconnect structure and at a same interconnect level as the first interconnect structure, a second interconnect structure.