Patent ID: 11972145
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. An apparatus, comprising:
a non-volatile memory;
a volatile memory configured to operate as cache for the non-volatile memory; and
an interface controller coupled with the non-volatile memory and the volatile memory, the interface controller operable to cause the apparatus to:
receive a write command for data from a row of a bank in the volatile memory;
write, based at least in part on the write command, the data from the row of the bank to a buffer coupled with the volatile memory and the non-volatile memory;
communicate the data from the buffer to the non-volatile memory based at least in part on the write command and before a pre-charge command for the row of the bank is received from a host device; and
write the data to the non-volatile memory after communicating the data to the non-volatile memory and based at least in part on the write command.