Patent ID: 11962311
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A sub-sampling phase locked loop (PLL) comprising:
a slope generating and sampling circuit configured to generate a sampling voltage based on a reference clock signal and an output clock signal;
a first transconductance circuit configured to generate a first output control voltage based on the sampling voltage, a reference voltage, and a control current;
a second transconductance circuit configured to generate a second output control voltage based on the sampling voltage, the reference voltage, and the control current;
a constant transconductance bias circuit including a switched capacitor resistor (SCR), the constant transconductance bias circuit configured to generate the control current;
a loop filter connected to an output terminal of the first transconductance circuit and an output terminal of the second transconductance circuit; and
a voltage controlled oscillator (VCO) configured to generate the output clock signal based on the first output control voltage and the second output control voltage,
wherein the constant transconductance bias circuit further includes
a first circuit connected between a power supply voltage and a ground voltage, and
a second circuit connected to the power supply voltage and the first circuit, and configured to output the control current, and

wherein the switched capacitor resistor is connected between the first circuit and the ground voltage and the switched capacitor resistor is configured to operate based on a first phase signal and a second phase signal.