Patent ID: 11877454
Assignee: SK HYNIX INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for fabricating a vertical memory device, the method comprising:
forming a plurality of dielectric layers and a plurality of sacrificial layers interleaved over a substrate in a cell array region and a contact region;
forming a stepwise structure where the sacrificial layers are exposed by patterning the dielectric layers and the sacrificial layers in the contact region;
forming a plurality of multi-layer sacrificial structures including a sacrificial material over the exposed sacrificial layers of the stepwise structure;
forming a capping layer over the sacrificial structures, wherein the capping layer includes a plurality of air gaps respectively interconnecting multiple layers of multi-layer sacrificial structures of the plurality of multi-layer sacrificial structures;
replacing the sacrificial layers in the cell array region with a plurality of gate electrodes;
replacing the sacrificial layers, the air gaps, and the multi-layer sacrificial structures in the contact region with a plurality of multi-layered pad portions; and
forming a plurality of contact plugs, wherein contact plugs of the plurality of contact plugs are respectively coupled to multi-layered pad portions of the multi-layered pad portions.