Patent ID: 11869843
Assignee: KEPLER COMPUTING INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 17:
18. A method of fabricating a device structure, the method comprising:
forming a first conductive interconnect in a first dielectric in a memory region and a second conductive interconnect in the first dielectric in a logic region;
depositing an etch stop layer on the first dielectric and on the first conductive interconnect and on the second conductive interconnect;
forming an electrode structure on the first conductive interconnect by a first process comprising:
etching a first opening in the etch stop layer;
depositing a first conductive hydrogen barrier layer in the first opening; and
depositing a first conductive material on the first conductive hydrogen barrier layer;

forming a memory device by depositing a material layer stack comprising a ferroelectric material or a paraelectric material on the electrode structure and etching the material layer stack;
depositing a second dielectric comprising an amorphous greater than 90% film density hydrogen barrier material on the memory device and on the etch stop layer;
etching and removing the second dielectric from the logic region and depositing a third dielectric comprising a less than 90% film density material;
performing a planarization of the third dielectric, wherein the planarization forms a first portion of the third dielectric directly laterally adjacent to the second dielectric and a second portion of the third dielectric above the second dielectric;
etching the third dielectric to form a first hanging trench above the second conductive interconnect;
forming a first mask within a portion of the first hanging trench;
etching the third dielectric through an opening in the first mask to form a first via opening;
depositing a liner layer in the first via opening, in the first hanging trench and on an uppermost surface of the third dielectric;
depositing a second conductive material on the liner layer in the first via opening, and in the first hanging trench;
planarizing to remove the second conductive material and the liner layer from above the third dielectric and forming a via structure in the first via opening and a metal line in the first hanging trench;
etching the third dielectric and forming a second hanging trench in the third dielectric and exposing the second dielectric;
forming a second mask within a portion of the second hanging trench;
etching the second dielectric through an opening in the second mask to form a second via opening;
depositing a second conductive hydrogen barrier layer on at least a portion of an uppermost surface of the memory device in the second via opening and in the second hanging trench;
depositing one or more layers of conductive material on the second conductive hydrogen barrier layer; and
planarizing to form a via electrode in the second via opening and a contact electrode in the second hanging trench, on the via electrode.