Patent ID: 11901026
Assignee: NEUROBLADE LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory chip comprising:
a plurality of memory banks;
a data storage configured to store access information indicative of access operations for one or more segments of the plurality of memory banks,
a refresh controller configured to perform a refresh operation of the one or more segments based, at least in part, on the stored access information, and
a sense amplifier configured to access the one or more segments,
wherein the data storage comprises at least one bit register associated with the one or more segments, wherein a state of the at least one bit register is configured to be changed in response to the one or more segments being accessed,
wherein the refresh controller is configured to skip a refresh of the one or more segments based on the state of the at least one bit register,
wherein the sense amplifier is configured to communicate with the refresh controller configured to update the state of the at least one bit register.