Patent ID: 11955486
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. A method, comprising:
providing a substrate having a first, second, third and fourth circuit regions;
forming a patterned sacrificial layer over the substrate, the patterned sacrificial layer extending lengthwise along a first direction, wherein a longitudinal axis of the patterned sacrificial layer in the first circuit region is offset in a second direction relative to a longitudinal axis of the patterned sacrificial layer in the second circuit region, the second direction being generally perpendicular to the first direction;
forming spacers on sidewalls of the patterned sacrificial layer;
removing the patterned sacrificial layer, wherein the spacers remain over the first, second, third and fourth circuit regions of the substrate after the removing of the patterned sacrificial layer;
removing selective portions of the spacers disposed over the second, third and fourth circuit regions to form a patterned spacer layer; and
etching the substrate using the patterned spacer layer as an etch mask to form a plurality of fin lines in the first circuit region, a first single fin line in the second circuit region, a second single fin line in the third circuit region, and a third single fin line in the fourth circuit region, wherein a projection of a longitudinal axis of the first single fin line along the first direction lies in a space separating adjacent ones of the plurality of fin lines.