Patent ID: 11967372
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. An apparatus, comprising:
a pillar extending through a plurality of levels of a memory array, wherein, at each level of the plurality of levels, one or more memory cells of the memory array are coupled with the pillar and a respective word line;
a bit line;
a first transistor and a second transistor in a series configuration with the first transistor, the first transistor and the second transistor configured to selectively couple the bit line with the pillar;
a first gate line coupled with the first transistor;
a second gate line coupled with the second transistor;
a circuit coupled with the first gate line and the second gate line, the circuit comprising:
a signal node coupled with the first gate line;
a first inverter coupled with the signal node and the second gate line; and
a second inverter coupled with the first inverter and the second gate line; and

a decoder coupled with the circuit and configured to drive a signal to the signal node.