Patent ID: 11922037
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. A controller controlling a plurality of nonvolatile memories, each including multi-level cell memory blocks each including a plurality of pages, comprising:
a buffer memory configured to buffer data received along with write commands from a host; and
a processor configured to determine a size of continuous data based on a logical address and a chunk size of the buffered data, configured to determine a striping number indicating a number of nonvolatile memory for distributing and storing the buffered data in sub-page units corresponding memory cell level in one page based on the size of continuous data, and configured to provide the buffered data to at least one nonvolatile memory selected from among the plurality of nonvolatile memories based on the determined striping number to be programmed the buffered data in sub-pages included in one page in one-time operation.