Patent ID: 11862604
Assignee: ADEIA SEMICONDUCTOR INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A chip comprising:
an individual chip having a first surface and a second surface and a plurality of side surfaces wherein the first surface comprises a plurality of interconnects;
a plurality of chiplets bonded to the first surface of the individual chip, each of the plurality of chiplets having a first chiplet surface and a second chiplet surface and a plurality of side chiplet surfaces; and
a plurality of plated posts, wherein at least some of the plated posts are disposed on the first surface of the individual chip and at least some of the plated posts are disposed on the first chiplet surface of one or more of the plurality of chiplets, the plurality of plated posts terminating in a single level across an upper portion of the individual chip,
wherein one or more of the plurality of plated posts disposed on the first chiplet surface of a corresponding one of the one or more of the plurality of chiplets are configured to provide direct electrical access to the individual chip vertically through the plurality of chiplets.