Patent ID: 11861230
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. An operating method of a controller that controls a memory device, comprising:
initializing a clock frequency set corresponding to clock signals provided to a plurality of operation modules included in the controller when a change in actual performance of the controller and the memory device or a change in a host request pattern is detected;
determining target performance on the basis of the actual performance after the clock frequency set is initialized;
determining an optimal clock frequency set such that the actual performance is maintained greater than or equal to the target performance, by repeatedly performing an operation of changing at least one clock frequency included in the clock frequency set and an operation of monitoring the actual performance after the clock frequency is changed; and
providing the plurality of operation modules with clock signals according to the optimal clock frequency set,
wherein the optimal clock frequency set is a clock frequency set such that power consumption of the controller and the memory device is minimized, among clock frequency sets such that the actual performance is maintained greater than or equal to the target performance.