Patent ID: 11894080
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 0:
1. An apparatus, comprising:
a plurality of memory cells;
a control circuit coupled to the plurality of memory cells and configured to:
acquire a first set of read levels on a wordline of a first block of pages of a first set of memory cells of the plurality of memory cells;
perform, using the first set of read levels, a first read operation on a page of a second block of pages of a second set of memory cells of the plurality of memory cells;
determine whether a fail bit count of the page after the first read operation is above a threshold amount;
in response to determining that the fail bit count of the page after the first read operation is above the threshold amount, acquire a second set of read levels on a first wordline of the second block;
perform, using the second set of read levels, a second read operation on the page;
determine whether a fail bit count of the page after the second read operation is above the threshold amount;
in response to determining that the fail bit count of the page after the second read operation is above the threshold amount, acquire a third set of read levels on a second wordline of the second block; and
perform, using the third set of read levels, a third read operation on the page.