Patent ID: 11894305
Assignee: nan
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A memory device, comprising:
a stack structure comprising tiers each comprising alpha phase tungsten material and insulative material vertically neighboring the alpha phase tungsten material;
strings of memory cells vertically extending through the tiers of the stack structure;
a staircase structure horizontally offset from an array of the strings of memory cells and having steps comprising edges of at least some of the tiers of the stack structure;
beta phase tungsten pad structures directly physically contacting the steps of the staircase structure, each of the beta phase tungsten pad structures having a horizontal center spaced apart from a horizontal center of one of the steps directly vertically thereunder; and
conductive contacts directly physically contacting the beta phase tungsten pad structures;
access lines coupled to the conductive contacts;
data lines vertically offset from the stack structure and coupled to the strings of memory cells;
a source structure offset from the stack structure and the data lines and coupled to the strings of memory cells; and
complementary metal-oxide-semiconductor (CMOS) circuitry within a horizontal area of the array of the strings of memory cells and vertically offset from the stack structure, the data lines, and the source structure.