Patent ID: 11916139
Assignee: WINBOND ELECTRONICS CORP.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor device, comprising:
a substrate;
a semiconductor channel layer disposed on the substrate;
a semiconductor barrier layer disposed on the semiconductor channel layer, wherein a surface of the semiconductor barrier layer comprises at least one recess;
a first interlayer dielectric layer disposed on the semiconductor barrier layer, wherein the first interlayer dielectric layer has a single layer structure;
a gate electrode disposed on the first interlayer dielectric layer, wherein the gate electrode comprises a body portion and at least one vertical extension portion respectively extending into the first interlayer dielectric layer, wherein the at least one vertical extension portion overlaps the at least one recess, and a portion of the first interlayer dielectric layer is between a bottom surface of the at least one vertical extension portion and a bottom surface of the at least one recess in a vertical direction with respect to a top surface of the semiconductor barrier layer;
a gate capping layer disposed between the semiconductor barrier layer and the body portion of the gate electrode; and
a second interlayer dielectric layer disposed on the first interlayer dielectric layer and directly covering the gate electrode and the first interlayer dielectric layer, wherein a top surface of the first interlayer dielectric layer between the body portion and the at least one vertical extension portion is flush with another top surface of the first interlayer dielectric layer that is in direct contact with the second interlayer dielectric layer,
wherein the at least one recess comprises a plurality of recesses separated from each other, portions of the recesses are disposed at one side of the body portion of the gate electrode, and other portions of the recesses are disposed at another side of the body portion of the gate electrode.