Patent ID: 11947468
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. A memory device, comprising:
a memory means including a first sub-bank and a second sub-bank;
a first data interface means for coupling to a memory controller via a first data bus; and
a second data interface means for coupling to the memory controller via a second data bus;
wherein the memory device is configured to receive a first refresh command to refresh the first sub-bank and a first calibration command from the memory controller, and while the first sub-bank is being refreshed responsive to the first refresh command and a first calibration operation is performed on the first data interface means responsive to the first calibration command, data is transferred, via the second data interface means, between the memory controller and the second sub-bank that is not being refreshed.