Patent ID: 11950427
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 14:
15. An integrated chip device, comprising:
a plurality of conductive lines disposed over a substrate, wherein the plurality of conductive lines are stacked onto one another and are separated from one another by dielectric layers interleaved between adjacent ones of the plurality of conductive lines;
a ferroelectric layer extending along sidewalls of the plurality of conductive lines and the dielectric layers;
an oxide semiconductor layer covering a sidewall of the ferroelectric layer, wherein the ferroelectric layer separates the oxide semiconductor layer from the plurality of conductive lines;
a plurality of conductive pillars separated by a dielectric and arranged on a sidewall of the oxide semiconductor layer facing away from the ferroelectric layer; and
a species disposed within the ferroelectric layer and having a valence of 5, valence of 7, or a combination thereof, wherein the species has a concentration that decreases from the conductive pillars towards the conductive lines.