Patent ID: 11902297
Assignee: INTEL CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC H  B  G | IPC B  G  H

Claim 4:
5. The computing apparatus of claim 3, the instructions when executed by the processor configure the apparatus to:
issue at least one secondary controlled message errors on the communication bus against the low priority message to force the low priority message to be retransmitted to cause an overlap between transmission of the low priority message and a third message the plurality of messages, the third message another higher priority message than the low priority message;
determine whether the low priority message lost an arbitration, responsive to the overlap, with the other higher priority message; and
determine that the low priority message and the other higher priority message did not originate from the first ECU based on a determination that the low priority message did lose an arbitration, responsive to the overlap, with the other higher priority message.