Patent ID: 11935618
Assignee: QUICKLOGIC CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 6:
7. The configuration memory latch of claim 1, wherein:
the first pull up network further comprises a fifth pMOS transistor, wherein the fifth pMOS transistor source is coupled to the third pMOS transistor drain and to the fourth pMOS transistors drain and, wherein fifth pMOS transistor drain is coupled to the first node;
the first pull-down network further comprises a fifth nMOS transistor, wherein the fifth nMOS transistor drain is coupled to the second nMOS transistor source and the fifth nMOS transistor source is coupled to the first nMOS transistor drain; and
a scan mode input, wherein the scan mode input is active low, and wherein the scan mode input is coupled to the fifth pMOS transistor gate and to the fifth nMOS transistor gate, wherein the scan mode input is asserted to place the configuration memory latch in test mode.