Patent ID: 11961566
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device comprising:
a memory array comprising:
a first data line;
a first pillar coupled with the first data line;
a second data line;
a second pillar coupled with the second data line; and
a plurality of wordlines coupled with the first pillar and the second pillar; and

control logic operatively coupled with the memory array, the control logic to perform operations comprising:
causing the plurality of wordlines to be discharged after a program pulse is applied to program one or more memory cells coupled with a selected wordline of the plurality of wordlines;
causing a supply voltage to be applied to the second data line to cause a voltage of the second pillar to float;
causing a ground voltage to be applied to the first data line to inhibit soft erase via the first pillar;
causing unselected wordlines of the plurality of wordlines to be charged to boost channel voltages in memory cells coupled with the second pillar; and
causing one of the ground voltage or a negative voltage to be applied to the selected wordline to increase a soft erase voltage between a channel of a memory cell coupled with the second pillar and the selected wordline, causing a threshold voltage stored in the memory cell to be partially erased.