Patent ID: 11941407
Assignee: GSI TECHNOLOGY INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A method for accumulating a plurality N of multiplied M bit values, the method comprising:
pipelining multiplicands A and B to a multiply-accumulator such that, at each cycle, a new set of multiplicands is received;
at each cycle, bit-wise multiplying bits of a current multiplicand A with bits of a current multiplicand B in bit multipliers and providing sum and carry values, output from said bit-wise multiplying, to other bit multipliers ; and
at each cycle, bit-wise accumulating output of said bit-wise multipliers thereby to accumulate said multiplicands during the pipelining process,
wherein said bit-wise multiplying and said bit-wise accumulating are implemented in bit-line processors.