Patent ID: 11973125
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. A semiconductor device, comprising:
a fin;
a bottom source/drain structure around the fin; and
a multi-layer bottom spacer on the bottom source/drain structure, around the fin, having three adjacently positioned layers, with a first layer being closest to the fin, a third layer being farthest from the fin, and a second laver being between the first layer and the second layer, the third layer having a portion with a stepped profile, including a top portion and a bottom portion, the top portion having a smaller horizontal width than a horizontal width of the bottom portion,
wherein each layer of the multi-layer bottom spacer has a respective vertical height above the bottom source/drain structure, and
wherein a layer of the multi-layer bottom spacer that is farthest from the fin has a greater vertical height than a layer of the multi-layer bottom spacer that is closest to the fin, to address parasitic capacitance from the bottom source/drain structure.