Patent ID: 11942334
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A method of manufacturing a microelectronic assembly, comprising:
depositing and patterning a first photoresist layer on a substrate to form one or more openings;
forming a first conductive layer in the one or more openings to form a first conductive trace having a first thickness and a first width, wherein the first conductive trace is rectilinear having a straight top, bottom, and side surfaces, wherein the side surfaces are at a 90 degree angle to the top and bottom surfaces;
electrically coupling the first conductive trace to a power plane;
depositing and patterning a second photoresist layer on the first photoresist layer to cover one or more of the one or more openings;
forming a second conductive layer in the one or more openings not covered by the second photoresist layer to form a second conductive trace having a second thickness and a second width, wherein the second conductive trace is rectilinear having a straight top, bottom, and side surfaces, wherein the side surfaces are at a 90 degree angle to the top and bottom surfaces, wherein the first thickness is greater than the second thickness and the first width is greater than the second width, and wherein the first thickness is between 4 microns (um) and 70 um and the second thickness is between 1 um and 35 um; and
electrically coupling the second conductive trace to a data signal or a data transmission line.