Patent ID: 11942143
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. A semiconductor memory device, comprising:
a memory cell array including memory blocks, wherein each of the memory blocks includes memory cells; and
a row driver connected with the memory cell array through word lines,
wherein the row driver includes
a decoder configured to adjust voltages of selection lines based on a row address,
pass switches respectively corresponding to the memory blocks and connected with the memory blocks through the word lines,
a driver connected in common with the pass switches through transmission lines, the driver configured to adjust voltages of the transmission lines based on an enable signal and the voltages of the selection lines,
a block decoder configured to activate one pass switch of the pass switches and to deactivate a remainder of the pass switches, based on the row address, and
a detection circuit connected with the selection lines, the detection circuit configured to activate a detection signal in response to the voltages of the selection lines being identical at a specific timing,

wherein each of the pass switches is connected with a corresponding memory block of the memory blocks through some corresponding word lines of the word lines, and
wherein the activated one pass switch of the pass switches is configured to transfer the voltages of the transmission lines to some word lines corresponding to the activated one pass switch from among the word lines.