Patent ID: 11961795
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of manufacturing a semiconductor package, the method comprising:
attaching a semiconductor chip and a plurality of lower conductive solders onto a support wiring structure;
forming a preliminary filling member surrounding the semiconductor chip and the plurality of lower conductive solders on the support wiring structure, the preliminary filling member including a plurality of fillers;
forming a lower filling unit and a plurality of lower connection units by removing an upper portion of the preliminary filling member and upper portions of the plurality of lower conductive solders until upper surfaces of the lower filling unit and the plurality of lower connection units are positioned at a reference level;
attaching a plurality of upper conductive solders under a cover wiring structure;
arranging the cover wiring structure on the support wiring structure so that the plurality of lower connection units and the plurality of upper conductive solders correspond to each other;
forming a plurality of connection structures that are one body by soldering the plurality of lower connection units and the plurality of upper conductive solders corresponding to each other by performing a reflow process, each of the plurality of connection structures including the lower connection unit and an upper connection unit; and
forming a filling member including the lower filling unit and an upper filling unit, the upper filling unit is formed by filling a gap between the lower filling unit and the cover wiring structure;
wherein a partial portion of the plurality of fillers includes cutting fillers having a flat surface that extends along the reference level.