Patent ID: 11942406
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A method of manufacturing an integrated circuit assembly, comprising:
providing a semiconductor package, comprising:
a semiconductor package first side;
a semiconductor package second side;
a bridge interconnect embedded in a build-up material, the bridge interconnect comprising a bridge interconnect first side comprising a conductive pad, and a bridge interconnect second side opposite the bridge interconnect first side, wherein a distance between the bridge interconnect first side and the semiconductor package first side is less than a distance between the bridge interconnect second side and the semiconductor package first side;
a first via extending through a portion of the build-up material, the first via comprising a first end that is narrower than a second end of the first via, wherein a distance between the first end of the first via and the semiconductor package first side is less than a distance between the second end of the first via and the semiconductor package first side;

attaching, prior to forming a second via, a flattening device to the semiconductor package to hold the semiconductor package first side flat, wherein attaching the flattening device comprises attaching a temporary carrier to the semiconductor package second side;
providing additional build-up material at the bridge interconnect first side;
forming the second via extending through the additional build-up material, the second via comprising a first end that is narrower than a second end of the second via, wherein a distance between the second end of the second via and the semiconductor package first side is less than a distance between the first end of the second via and the semiconductor package first side; and
attaching a die to the semiconductor package first side while the flattening device is holding the semiconductor package first side flat.