Patent ID: 11936353
Assignee: CADENCE DESIGN SYSTEMS, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. A transmitter for amplifying a differential input signal to a differential output signal across a first output node and a second output node, the transmitter comprising:
an H-bridge current driver connected between a first supply terminal and a second supply terminal, the H-bridge current driver having:
a first transistor having a first current-handling terminal connected to the first supply terminal, a control terminal, and a second current-handling terminal connected to the first output node;
a second transistor having a first current-handling terminal connected to the first supply terminal, a control terminal, and a second current-handling terminal connected to the second output node;
a third transistor having a first current-handling terminal connected to the second supply terminal, a control terminal, and a second current-handling terminal connected to the first output node;
a fourth transistor having a first current-handling terminal connected to the second supply terminal, a control terminal, and a second current-handling terminal connected to the second output node;
a differential amplifier having:
a differential-amplifier load; a current source;
a fifth transistor having a first current-handling terminal coupled the differential amplifier load and the control terminal of the first transistor, a differential amplifier control terminal to receive a first half of the differential input signal, and a second current-handling terminal coupled to the current source;
a sixth transistor having a first current-handling terminal coupled to the differential-amplifier load and the control terminal of the second transistor, a differential amplifier control terminal to receive a second half of the differential input signal, and a second current-handling terminal coupled to the current source;
a seventh transistor having a first current-handling terminal coupled the differential amplifier load and the control terminal of the first transistor, a differential amplifier control terminal to receive a first half of a second differential input signal, and a second current-handling terminal coupled to the current source; and
an eighth transistor having a first current-handling terminal coupled to the differential amplifier load and the control terminal of the second transistor, a differential amplifier control terminal to receive a second half of the second differential input signal, and a second current handling terminal coupled to the current source.