Patent ID: 11862241
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 17:
18. A memory system comprising:
a controller configured to output a control command; and
a variable resistive memory device including a control circuit and a plurality of mats, the control circuit configured to receive the control command from the controller to generate control signals, each of the mats including a plurality of memory cells configured to perform a memory operation and a discharge operation by using a forward current or a reverse current in response to the control signals,
wherein the memory cells are positioned at intersection points of a plurality of bit lines and a plurality of word lines,
wherein each of the plurality of bit lines is selectively connected to a first hierarchical bit line structure configured to receive a first voltage and a second hierarchical bit line structure configured to receive a second voltage that is lower than the first voltage,
wherein each of the plurality of word lines is selectively connected to a first hierarchical word line structure configured to receive the second voltage and a second hierarchical word line structure configured to receive the first voltage, and
wherein the control circuit is configured to generate control signals for selecting the mat and the memory cell in the selected mat, control signals for transmitting the forward current, control signals for transmitting the reverse current, and a discharge control signal for discharging a selected bit line and a selected word line during the discharge operation, and
wherein a current for the discharge operation flows in an opposite direction compared to a current direction for the memory operation.