Patent ID: 11908789
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. An integrated circuit structure comprising:
a first etch stop layer over an inter-layer dielectric;
a first metal line over the first etch stop layer, the first metal line having a first sidewall and a second sidewall opposite the first sidewall, wherein the first sidewall is linear from an upper surface of the first metal line to a bottom surface of the first metal line;
a second metal line over the first etch stop layer and adjacent the first metal line, the second metal line having a third sidewall and a fourth sidewall opposite the third sidewall, wherein the third sidewall is linear from an upper surface of the second metal line to a bottom surface of the second metal line, wherein the first sidewall faces the third sidewall, wherein a bottom portion of the first sidewall is separated from a bottom portion of the third sidewall by a first positive distance, wherein a top portion of the first sidewall is separated from a top portion of the third sidewall by a second positive distance, and wherein the second positive distance is greater than the first positive distance; and
a dielectric layer surrounding the first metal line and the second metal line, wherein a portion of the dielectric layer is between the first sidewall and the second sidewall of the first metal line.