Patent ID: 11892909
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. A non-transitory computer-readable medium storing instructions, which when executed by a processing device, cause the processing device to perform operations comprising:
detecting a plurality of failures of a set of memory devices, wherein a first failure affects stored data on a first memory device and a second failure affects stored data on a second device;
notifying a host system of a change in a capacity of the set of memory devices after each of the plurality of failures;
receiving from the host system an indication to continue at a reduced capacity after each of the plurality of failures;
updating the set of memory devices to change the capacity to the reduced capacity after each of the plurality of failures, wherein the updating comprises reducing a quantity of bits stored per memory cell of one or more memory devices of the set of memory devices;
notifying the host system that the set of memory devices comprise data in excess of the reduced capacity;
receiving, from the host system, a storage location for storing the data in excess of the reduced capacity;
storing the data in excess of the reduced capacity at the storage location; and
recovering the stored data using recovery data in the set of memory devices.