Patent ID: 11955560
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 17:
18. A method of fabricating a transistor structure, the method comprising:
patterning an electrode material layer to form a gate electrode above a substrate;
depositing a gate dielectric layer on the gate electrode;
forming a material layer stack on the gate dielectric layer, the forming comprising:
depositing a channel layer on the gate dielectric layer;
depositing a barrier layer on the channel layer;
depositing an etch stop layer on the barrier layer;
depositing a sealant layer on the etch stop layer;
patterning the material layer stack into a block;
depositing a dielectric on the block;
patterning a plurality of openings in the block; and
forming metallization structures in the plurality of openings.