Patent ID: 11940492
Assignee: STMICROELECTRONICS S.R.L.
Field: Measurement (Instruments)
Classification: CPC G | IPC G

Claim 0:
1. A circuit comprising:
a set of test stimulus generators, each of the set of test stimulus generators activatable to produce test stimulus signals for at least one circuit under test as a function of test stimulus information loaded in a test stimulus register in the test stimulus generator;
a set of controllers, each of the set of controllers configured to control loading of test stimulus information in the test stimulus register in a respective generator in the set of test stimulus generators as a function of test control information loaded in a respective control register in a set of control registers;
a test programming interface configured to load test programming information in the control registers in the set of control registers, wherein the test stimulus generators in the set of test stimulus generators are activatable as a function of test programming information loaded in the control registers in the set of control registers via the test programming interface;
a set of input signature registers, configured to store therein signature reference signals indicative of signature reference values received from the test programming interface; and
signature control circuitry comprising a set of signature control modules coupled to respective ones of the set of input signature registers, the signature control circuitry being separate from the set of controllers, the signature control circuitry configured to
receive test outcome signals from the at least one circuit under test in response to the test stimulus signals being applied thereto,
produce signature comparison signals from the test outcome signals received from the at least one circuit under test,
compare in the set of signature control modules the signature comparison signals produced from the test outcome signals received from the at least one circuit under test with respective signature reference signals in the set of input signature registers, and
produce error signals in response to the signature comparison signals produced from the test outcome signals received from the at least one circuit under test failing to match with respective signature reference signals in the set of input signature registers, wherein the signature control circuitry further comprises compressor circuitry configured to receive plural sets of test outcome signals from the at least one circuit under test in response to the test stimulus signals being applied thereto, the compressor circuitry comprising:
two gated via AND gates under control of respective enabling signals produced by one or more funnel configuration registers, wherein each of the one or more funnel configuration registers is configured via software in the test programming interface to associate a respective set of data to a single input signature register; and
an XOR gate coupled to respective outputs of the two gated via AND gates.