Patent ID: 11876732
Assignee: STMICROELECTRONICS (GRAND OUEST) SAS
Field: Digital communication (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 9:
10. The system on a chip according to claim 8, wherein:
each slave resource belongs to a first group formed at least by a peripheral, a feature of the peripheral, a first memory internal to the system on a chip, and a memory interface internal to the system on a chip and intended to be coupled to a second memory external to the system on a chip;
at least one master piece of equipment is controllable by a microprocessor and includes an output port configured to emit first transactions as well as an input port configured to receive second transactions, the input port being considered as a slave resource and the output port as a master piece of equipment; and
the first particular slave resource belongs to a second group formed by the peripheral, the feature of the peripheral, and the input port of the master piece of equipment controllable by the microprocessor; and
the at least one element is selected from a generator of at least one clock signal, a generator of at least one reset signal, a power block, or at least one configurable input/output pin of the system on a chip.