Patent ID: 11871277
Assignee: QUALCOMM INCORPORATED
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An apparatus for wireless communications, comprising:
one or more processors;
one or more memories coupled with the one or more processors; and
one or more processor-readable instructions stored in the one or more memories and executable by the one or more processors to cause the apparatus to:
measure a respective interference level for each symbol duration of a plurality of symbol durations, each symbol duration associated with a respective symbol index of a plurality of symbol indexes of a physical resource block structure;
determine, based at least in part on the respective interference level measurements of the plurality of symbol durations, a rate matching pattern comprising a pattern of resources associated with a downlink transmission, the rate matching pattern comprising a first rate matching pattern for a first subset of the plurality of symbol indexes of the physical resource block structure and a second rate matching pattern for a second subset of the plurality of symbol indexes of the physical resource block structure;
transmit, to a network device, an indication of the rate matching pattern comprising the first rate matching pattern and the second rate matching pattern; and
receive the downlink transmission from the network device based at least in part on transmitting the indication of the rate matching pattern.