Patent ID: 11948941
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 12:
13. A semiconductor device, comprising:
a gate layer, disposed over a substrate;
a channel material layer, disposed over the gate layer, wherein a material of the channel material layer comprises a first low dimensional material;
a first dielectric layer, sandwiched between the gate layer and the channel material layer;
source/drain terminals, in contact with the channel material layer, wherein the channel material layer is at least partially sandwiched between the source/drain terminals and over the gate layer, and the gate layer is disposed between the substrate and the source/drain terminals; and
a second dielectric layer, disposed over the gate layer, wherein the source/drain terminals penetrate through the second dielectric layer, and an outermost surface of the second dielectric layer is lower than outermost surfaces of the source/drain terminals.