Patent ID: 11954041
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. A memory system comprising:
a memory device including memory blocks, each storing physical addresses; and
a controller configured to communicate with the memory device using a physical address among the physical addresses and communicate with a host using a logical address corresponding to the physical address, the controller including a map cache,
wherein the controller is configured to store a descriptor in a linear structure of the map cache and transmit the descriptor from the linear structure to a binary tree structure after a calculation of the descriptor for the binary tree structure is finished, and
wherein the controller searches for the descriptor corresponding to the logical address in at least one the linear structure, the binary tree structure, and both the linear structure and the binary tree structure according to status information of the map cache when receiving a read request for the logical address from the host.