Patent ID: 11916559
Assignee: SAMBANOVA SYSTEMS, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A delay-locked loop (DLL) with a DLL signal input, comprising:
a delay line including a series of delay stages, with a signal input coupled with the DLL signal input, a speed control input, a first phase output, and a second phase output;
a gater with a first gater input coupled with the first phase output and a second gater input coupled with the second phase output, a gater clock input coupled with the DLL signal input, a first gater output and a second gater output;
a phase-frequency detector (PFD) with a first PFD input coupled with the first gater output and a second PFD input coupled with the second gater output, and a first PFD output and a second PFD output;
a retimer with a first retimer input coupled with the first PFD output, a second retimer input coupled with the second PFD output, a retimer clock input coupled with the DLL signal input, a first retimer output, and a second retimer output; and
a loop filter with a first input coupled with the first retimer output and a second input coupled with the second retimer output, and a speed control output coupled with the speed control input.