Patent ID: 11900875
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. The display substrate according to claim 1, further comprising a third power line, a fourth power line, a first scanning clock signal line, a second scanning clock signal line, and a scanning initial signal line that extend in the column direction; wherein
the scanning drive circuit comprises: multiple cascaded first shift registers that are sequentially arranged in the column direction, and each first shift resister comprises: a first scan transistor to an eighth scan transistor, a first scanning capacitor, a second scanning capacitor, a scanning signal input terminal, a scanning signal output terminal, a first scanning clock signal terminal, a second scanning clock signal terminal, a first scanning power terminal, and a second scanning power terminal;
a control electrode of the first scan transistor is electrically connected to the first scanning clock signal terminal, a first electrode of the first scan transistor is electrically connected to the scanning signal input terminal, and a second electrode of the first scan transistor is electrically connected to a first scan node; a control electrode of the second scan transistor is electrically connected to the first scan node, a first electrode of the second scan transistor is electrically connected to the first scanning clock signal terminal, and a second electrode of the second scan transistor is electrically connected to a second scan node; a control electrode of the third scan transistor is electrically connected to the first scanning clock signal terminal, a first electrode of the third scan transistor is electrically connected to the second scanning power terminal, and a second electrode of the third scan transistor is electrically connected to the second scan node; a control electrode of the fourth scan transistor is electrically connected to the second scan node, a first electrode of the fourth scan transistor is electrically connected to the first scanning power terminal, and a second electrode of the fourth scan transistor is electrically connected to the scanning signal output terminal; a control electrode of the fifth scan transistor is electrically connected to a third scan node, a first electrode of the fifth scan transistor is electrically connected to the scanning signal output terminal, and a second electrode of the fifth scan transistor is electrically connected to the second scanning clock signal terminal; a control electrode of the sixth scan transistor is electrically connected to the second scan node, a first electrode of the sixth scan transistor is electrically connected to the first scanning power terminal, and a second electrode of the sixth scan transistor is electrically connected to a first electrode of the seventh scan transistor; a control electrode of the seventh scan transistor is electrically connected to the second scanning clock signal terminal, and a second electrode of the seventh scan transistor is electrically connected to the first scan node; a control electrode of the eighth scan transistor is electrically connected to the second scanning power terminal, a first electrode of the eighth scan transistor is electrically connected to the first scan node, and a second electrode of the eighth scan transistor is electrically connected to the third scan node; a first plate of the first scanning capacitor is electrically connected to the first scanning power terminal, and a second plate of the first scanning capacitor is electrically connected to the second scan node; and a first plate of the second scanning capacitor is electrically connected to the scanning signal output terminal, and a second plate of the second scanning capacitor is electrically connected to the third scan node; and
a scanning signal input terminal of a first-stage first shift register is electrically connected to the scanning initial signal line, a scanning signal output terminal of an (i−1)th-stage first shift register is electrically connected to a scanning signal input terminal of an ith-stage first shift register, first scanning power terminals of all the first shift registers are electrically connected to the third power line, second scanning power terminals of the first shift registers are electrically connected to the fourth power line, a first scanning clock signal terminal of an odd-stage first shift register is electrically connected to the first scanning clock signal line, a second scanning clock signal terminal of the odd-stage first shift register is electrically connected to the second scanning clock signal line, a first scanning clock signal terminal of an even-stage first shift register is electrically connected to the second scanning clock signal line, a second scanning clock signal terminal of the even-stage first shift register is electrically connected to the first scanning clock signal line, a scanning signal output terminal of a first shift register is electrically connected to a scanning signal line, where i is a positive integer greater than or equal to 2.