Patent ID: 11973042
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor package having a top and a bottom, comprising:
a semiconductor chip disposed within the semiconductor package between the top of the semiconductor package and the bottom of the semiconductor package, wherein the semiconductor chip includes at least one connection pad disposed on a top surface thereof;
a plurality of wiring layers disposed adjacently to the semiconductor chip, and stacked vertically between the top of the semiconductor package and the bottom of the semiconductor package;
a first conductive bump disposed on the at least one connection pad of the semiconductor chip;
a second conductive bump disposed on an uppermost wiring layer among the plurality of wiring layers;
an insulating post disposed between the semiconductor chip and the plurality of wiring layers, and extending towards the top of the semiconductor package and the bottom of the semiconductor package;
an encapsulant disposed on side surfaces of the first and second conductive bumps, the insulating post, and the semiconductor chip; and
a redistribution structure including an insulating layer disposed on the encapsulant, and a redistribution layer disposed on the insulating layer and electrically connected to the first and second conductive bumps,
wherein the insulating post has a side surface spaced apart from the plurality of wiring layers and in contact with the encapsulant, and a top surface in contact with the insulating layer of the redistribution structure.