Patent ID: 11955977
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A method of adjusting a data clock signal provided to a memory device, the method comprising:
issuing, from a controller, a first mode register write command to a memory device to cause a first value to be written to a mode register to initiate testing of a plurality of adjustments on a duty cycle of the data clock signal;
issuing, from the controller, a mode register read command to read a result signal stored in the mode register;
issuing from the controller, a second mode register write command to cause a second value to be written to the mode register to select one of a plurality of lookahead duty codes stored in the mode register, based, at least in part, on the result signal; and
issuing, from the controller, a third mode register write command to the memory device to terminate the testing.