Patent ID: 11955090
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 7:
8. The buffer circuit of claim 7, wherein
the boosting transistor is included in the push compensation current circuit and the pull compensation current circuit,
the offset blocking circuit includes
a P-channel field effect transistor (PFET) having a first gate connected to the push connection node, a first end of the first gate connected to a gate of the boosting transistor included in the push compensation current circuit, and a power supply voltage applied from a second end of the first gate; and
an N-channel field effect transistor (NFET) having a second gate connected to the pull connection node, a first end of the second gate connected to the gate of the boosting transistor included in the pull compensation current circuit, and a second end of the second gate to which a ground voltage is applied.