Patent ID: 11950514
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A confined memory cell structure, comprising:
a pinned region;
a dielectric material formed over the pinned region, wherein the dielectric material comprises a via formed within the dielectric material and over the pinned region;
a barrier region formed within the via and comprising barrier materials conformally deposited to fill a portion of a volume of the via, the barrier region having a first horizontal portion, a second horizontal portion, and vertical portions, wherein the first horizontal portion is formed directly on and in contact with the pinned region, wherein the second horizontal portion is formed directly on top of and in contact with the dielectric material, and wherein the vertical portions are formed along vertical sidewalls of the via;
a free region formed within the via directly on and in contact with the horizontal portion and the vertical portions of the barrier region such that the barrier region surrounds each vertical periphery of the free region and such that the free region fills an entire remaining volume of the via; and
a conductive contact formed directly on a top surface of the free region and the barrier region and in contact with the free region and the barrier region, wherein the lateral edges of the conductive contact are vertically aligned with the lateral edges of the pinned region.