Patent ID: 11960946
Assignee: SNAP INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A message-based processor system, comprising a first plurality of message based processor system cores, each core comprising:
a second plurality of processor elements, having a respective second addressable storage entry with a processor element address storing a respective processor element state;
respective third pluralities of addressable storage entries specifying pattern information of a respective target pattern, the pattern information comprising, for respective pattern elements of the respective target pattern, a magnitude value and a control value selected from a fourth plurality of optional control values; and
a processor element controller configured to;
receive as an input message an event message comprising a first indication of a subset of the second plurality of processor elements and a second indication of a target pattern, and
update a state value of respective processor elements in the subset in accordance with one or more magnitude values of respective succeeding pattern elements of the target pattern,
wherein the processor element controller is configurable in an address computation mode selected from a cyclic set of address computation modes, and configured to maintain a current address computation mode or assume a next address computation mode selected from the cyclic set dependent on whether the control value of a currently applied pattern element is a first optional control value or a second optional control value respectively,
wherein the processor element controller is configured to assume an initial address computation mode selected from the cyclic set upon receipt of the input message,
wherein the processor element controller computes a processor element address of a succeeding processor element by addition of an address step to a processor element address of a processor element preceding the succeeding processor element, and
wherein respective address computation modes correspond to respective mutually different address steps.