Patent ID: 11968826
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 2:
3. A three-dimensional memory device, comprising:
an alternating stack of insulating layers and electrically conductive layers;
memory openings extending through the alternating stack; and
memory opening fill structures located in the memory openings and comprising a respective vertical semiconductor channel and a respective memory film,
wherein each of the electrically conductive layers comprises:
a tubular metallic liner in contact with a respective outer sidewall segment of a respective one of the memory opening fill structures;
an electrically conductive barrier layer contacting the respective tubular metallic liner and two of the insulating layers; and
a metallic fill material layer contacting the electrically conductive barrier layer, and not contacting the tubular metallic liner or any of the insulating layers;

wherein the tubular metallic liners comprise:
a cylindrical outer sidewall having a closed upper edge and a closed lower edge; and
an inner sidewall including a straight inner sidewall segment, an upper tilted convex surface segment connecting an upper edge of the straight inner sidewall segment to the closed upper edge of the cylindrical outer sidewall, and a lower tilted convex surface segment connecting a lower edge of the straight inner sidewall segment to the closed lower edge of the cylindrical outer sidewalk;

wherein the tubular metallic liner has a greater vertical extent than the metallic fill material layer; and
wherein:
each of the memory films comprises a respective aluminum oxide blocking dielectric layer and a respective memory material layer; and
the respective aluminum oxide blocking dielectric layer and the respective memory material layer have a lesser maximum lateral extent at a level of one of the electrically conductive layers than at a level of an insulating layer contacting a top surface of the one of the electrically conductive layers and than at a level of another insulating layer contacting a bottom surface of the one of the electrically conductive layers.