Patent ID: 11934281
Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 4:
5. The memory device of claim 4, wherein
for 1≤p<P,
an output of each main write MUX in the pth write sub-array is coupled to a first input of a corresponding main write MUX in a (p+1)th write sub-array; and
an output of the redundant write MUX in the pth write sub-array is coupled to a qth redundant input of a corresponding redundant write MUX in each (p+q)th write sub-array with 1≤q≤P−p, where q is a positive integer; and

for p=P,
outputs of the N main write MUXs and the redundant write MUX in the pth write sub-array are coupled to the N main banks and the redundant bank, respectively.