Patent ID: 11907772
Assignee: GRAPHCORE LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 18:
19. A method for tracing synchronisation activity for a processor of a processing unit, the method comprising:
exchanging a plurality of sync messages between a sync controller hardware unit and the processor so as to co-ordinate a plurality of barrier synchronisations, each of the barrier synchronisations separating a compute phase of the processor from an exchange phase for the processor;
receiving at sync trace circuitry, a first sync message of the plurality of sync messages; and
in response to the first sync message, providing sync trace information for output from a device comprising the sync trace circuitry, the sync trace information comprising timing information associated with the first sync message,
wherein a plurality of dedicated wires are used for transmitting different types of sync message between the processing unit and the sync controller hardware unit,
wherein exchanging the plurality of sync messages comprises at least one of:
asserting signals on at least one of the dedicated wires; and
detecting assertion of signals by circuitry of the sync controller hardware unit on a further at least one of the dedicated wires,

wherein the sync trace circuitry comprises a plurality of connections to different ones of the dedicated wires, and
wherein the method further comprises:
for each of the plurality of sync messages, providing the respective sync trace information in dependence upon which of the dedicated wires an assertion of a signal corresponding to the respective sync message was detected.