Patent ID: 11907574
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 23:
24. A memory device comprising:
an array of memory cells; and
a controller configured to access the array of memory cells,
wherein the controller is further configured to:
receive a command to perform an erase operation;
in response to the command to perform the erase operation, begin execution of the erase operation;
receive a command to suspend the execution of the erase operation;
in response to the command to suspend the execution of the erase operation, suspend the execution of the erase operation;
with the execution of the erase operation suspended, receive a command to perform a read operation;
in response to the command to perform the read operation, execute the read operation;
in response to executing the read operation, pull down a ready/busy control signal to indicate the memory device is busy executing the read operation; and
in response to the execution of the read operation completing and with the ready/busy control signal pulled down, resume the execution of the erase operation while keeping the ready/busy control signal pulled down.