Patent ID: 11895840
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 1:
2. The memory device of claim 1, wherein the lower structure comprises a second stacked structure including a plurality of second gate layers stacked on the peripheral circuit in the vertical direction, a plurality of second channel structures each passing through the second stacked structure in the vertical direction, a second bit line disposed on the second stacked structure and connected to the plurality of second channel structures, and a second through via passing through the second stacked structure and connecting the upper bonding pad of the lower structure to the peripheral circuit,
the second bit line of the lower structure comprises a first portion extending in the horizontal direction, a second portion extending in the horizontal direction, and a gap separating the first portion of the second bit line of the lower structure from the second portion of the second bit line in the horizontal direction, and
in a plan view, the second through via of the lower structure overlaps the gap of the second bit line of the lower structure.