Patent ID: 11950411
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 17:
18. A method for fabricating a memory device, comprising:
forming a plurality of first nanostructures and a plurality of second nanostructures separated by a dielectric fin structure, wherein each of the plurality of first nanostructures, each of the plurality of second nanostructures, and the dielectric fin structure extend along a first lateral direction;
forming a first gate structure wrapping around each of the first nanostructures except for a sidewall that is in contact with the dielectric fin structure;
forming a second gate structure wrapping around each of the second nanostructures except for a sidewall that is in contact with the dielectric fin structure, wherein the first and second gate structures extend along a second lateral direction perpendicular to the first lateral direction;
forming a first metal structure above the first and second gate structures, wherein the first metal structure is electrically coupled to first nanostructures; and
forming a second metal structure above the first and second gate structures, wherein the second metal structure is electrically coupled to second nanostructures.