Patent ID: 11968085
Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
Field: Digital communication (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. An apparatus comprising:
a processor; and
a memory on which is stored machine readable instructions that cause the processor to:
instruct a host device to:
pre-spawn a number of first host processes configured to provide a first version of a service in one or more computing nodes; and
pre-spawn a number of second host processes configured to provide a second version of the service in the one or more computing nodes, wherein the number of first host processes and the number of second host processes are defined in a first scaling constraint and are each greater than or equal to one, wherein the host device pre-spawns the second host processes in each of the one or more computing nodes through:
identification of a host process of the first host processes that is unbound from a client session;
termination of the identified host process; and
pre-spawning of a second host process that provides the second version of the service based on termination of the identified host process; and

in response to receipt of an indication that each of the second host processes in the one or more computing nodes is operating properly, instruct the host device to decrease the number of first host processes and to increase the number of second host processes in the one or more computing nodes as defined in a second scaling constraint.