Patent ID: 11895832
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A memory integrated circuit, comprising:
a first memory array and a second memory array, laterally spaced apart from each other, and respectively comprising:
memory cells, each comprising an access transistor and a storage capacitor coupled to the access transistor;
bit lines, respectively coupled to a row of the memory cells; and
word lines, respectively coupled to a column of the memory cells; and

a driving circuit, disposed below the first and second memory arrays, and comprising sense amplifiers, wherein each of the bit lines in the first memory array and one of the bit lines in the second memory array are routed to input lines of one of the sense amplifiers,
wherein the first and second memory arrays are disposed at the same height with a spacing in between, and the bit lines coupled to the memory cells of the first and second memory arrays are connected to the input lines of the sense amplifiers through the spacing.