Patent ID: 11861758
Assignee: NVIDIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. A system comprising:
a Parallel Processing Unit (“PPU”) executing a process;
a PPU memory associated with the PPU;
a network interface to receive a set of packets and store packet data transmitted by the set of packets in the PPU memory;
one or more processors; and
one or more memories to store instructions executable by the one or more processors and when executed by the one or more processors cause the one or more processors to at least:
detect receipt of the set of packets by the network interface;
cause at least a portion of the PPU memory to be flushed after the packet data is stored in the PPU memory by the network interface; and
after the portion of the PPU memory has been flushed, write, to a shared memory portion of the PPU memory that is shared between the one or more processors and the PPU, an indication indicating that packet data transmitted by the set of packets is available for processing, the process being executed by the PPU before the indication is written to the shared memory portion, the process processing the packet data to obtain processed packet data after the PPU detects the indication.