Patent ID: 11860671
Assignee: WINBOND ELECTRONICS CORP.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory-control logic, disposed in a memory circuit, wherein the memory circuit comprises a memory-cell array that is divided into a plurality of regions, and the regions comprise at least one damaged region, and the memory circuit receives an address signal, the memory-control logic comprising:
a one-time-programmable (OTP) memory array;
an array-control circuit, programming an available memory-size ratio of the memory-cell array, programming a region-failure flag corresponding to each region in the memory-cell array, and programming a redirecting mapping table corresponding to each region into a first array, a second array, and a third array of the OTP memory array;
wherein the array-control circuit performs a programming operation on the redirecting mapping table corresponding to each region stored in the OTP memory array according to the available memory-size ratio to direct the redirecting mapping table corresponding to each damaged region to non-repetitive good regions among the regions; and
an address-redirecting circuit, converting the address signal into a first redirected address signal according to the redirecting mapping table corresponding to each region stored in the OTP memory array, converting the first redirected address signal into a second redirected address signal according to the available memory-size ratio, and inputting the second redirected address signal into the memory-cell array,
wherein:
the region-failure flag indicates whether the corresponding region is the damaged region, and
the address-redirecting circuit masks one or more of the highest bits in the first redirected address signal according to the available memory-size ratio of the memory-cell array,
wherein:
the first array is a binary array,
when the binary array is a first value, the logic circuit sets a first highest bit of the second redirected address signal to a first highest bit of the first redirected address signal,
when the binary array is a second value, the logic circuit sets the first highest bit of the second redirected address signal to 0,
when the binary array is the third value, the logic circuit sets the first highest bit and a second highest bit of the second redirected address signal to 0,
when the binary array is the fourth value, the logic circuit sets the first highest bit, the second highest bit, and a third highest bit of the second redirected address signal to 0.