Patent ID: 11881265
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A memory system, comprising:
a memory chip including a plurality of memory cells for storing multi-bit data according to a plurality of threshold voltage levels;
a memory controller configured to apply a plurality of read voltages to each of a plurality of subsets of the plurality of memory cells, the plurality of read voltages corresponding to the plurality of threshold voltage levels, wherein
the memory controller is configured to store:
a default value table indicating a first initial value for each reading voltage level corresponding to the plurality of threshold voltage levels,
a read success flag table that identifies for each subset of the plurality of memory cells whether a previous reading using the first initial values for each reading voltage level was successful or not, and
a first shift table including shift information indicating a second initial value for each reading voltage level corresponding to the plurality of threshold voltage levels to be used on each subset for which the previous reading using the first initial values was not successful.