Patent ID: 11973041
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 27:
28. A multi-die electronic package, comprising:
a first die comprising interconnections, the first die having a top surface, a bottom surface, a first side and a second side, the second side opposite the first side, and the first die having a plurality of through substrate vias;
a first mold layer laterally adjacent to the first die, the first mold layer in direct contact with the first side and the second side of the first die;
a first plurality of vias in and in direct contact with the first mold layer, the first plurality of vias laterally adjacent to a first side of the first die, each of the first plurality of vias extending from a top surface of the first mold layer to a bottom surface of the first mold layer;
a second plurality of vias in and in direct contact with the first mold layer, the second plurality of vias laterally adjacent to a second side of the first die, each of the second plurality of vias extending from the top surface of the first mold layer to the bottom surface of the first mold layer;
a second die electrically coupled to the first die, and the second die electrically coupled to the first plurality of vias;
a third die electrically coupled to the first die, the third die electrically coupled to the second die by the interconnections of the first die; and
a second mold layer between and in contact with the second die and the third die, the second mold layer vertically between the second die and the first mold layer, the second mold layer vertically between the third die and the first mold layer, and the second mold layer distinct from the first mold layer.