Patent ID: 11928329
Assignee: NXP B.V.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. The IC of claim 13, wherein the logic circuit of the second set of logic circuits further comprises:
a third logic gate that is coupled to the address decoder, and configured to receive the third control bit and the second mask bit, and output a fourth select bit based on the third control bit and the second mask bit, wherein the fourth select bit has the first logic state when the second mask bit and the third control bit have the first logic state, and the fourth select bit has the second logic state when at least one of a group consisting of the second mask bit and the third control bit has the second logic state; and
a fourth logic gate that is coupled to the address decoder, the third logic gate, and the third multiplexer, and configured to (i) receive the first control bit and the fourth select bit, (ii) output the third select bit based on the first control bit and the fourth select bit, and (iii) provide the third select bit to the third multiplexer, wherein the third select bit has the second logic state when the first control bit and the fourth select bit have the second logic state, and the third select bit has the first logic state when at least one of a group consisting of the first control bit and the fourth select bit has the first logic state.