Patent ID: 11881430
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. A semiconductor device, comprising:
a substrate including a field region and an active region;
a transistor including a gate electrode, source/drain regions, and a nanosheet on the active region;
a first interlayer insulating film on the transistor;
a first connecting wire in the first interlayer insulating film;
a lower etching stopper film on the first interlayer insulating film;
a resistance pattern on the lower etching stopper film;
a first etching stopper film on the lower etching stopper film, the first etching stopper film extending in parallel with a top surface of the first interlayer insulating film;
a second etching stopper film spaced apart from the resistance pattern, the second etching stopper film extending in parallel with a top surface of the resistance pattern;
an upper etching stopper film between the resistance pattern and the second etching stopper film;
a second interlayer insulating film on the first etching stopper film and the second etching stopper film;
a first wire via in the second interlayer insulating film, the first wire via being connected to the first connecting wire and passing through the lower etching stopper film and the first etching stopper film;
a first resistance via in the second interlayer insulating film, the resistance via being connected to the resistance pattern and passing through the second etching stopper film and the upper etching stopper film; and
a second connecting wire on the first wire via and the resistance via, the second connecting wire being connected to at least one of the first wire via and the resistance via,
wherein the resistance pattern is on the first interlayer insulating film and vertically overlaps the field region of the substrate.