Patent ID: 11881509
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 17:
18. A semiconductor device, comprising:
a substrate including a PMOSFET region and an NMOSFET region, which are adjacent to each other in a first direction;
a first active pattern and a second active pattern on the PMOSFET and NMOSFET regions, respectively;
a first source/drain pattern on the first active pattern and a second source/drain pattern on the second active pattern;
a first channel pattern connected to the first source/drain pattern and a second channel pattern connected to the second source/drain pattern, each of the first and second channel patterns including a first semiconductor pattern, a second semiconductor pattern, and a third semiconductor pattern, which are sequentially stacked to be spaced apart from each other;
a first fence insulating layer extended from a side surface of the first active pattern to a lower side surface of the first source/drain pattern;
a second fence insulating layer extended from a side surface of the second active pattern to a lower side surface of the second source/drain pattern;
a pair of middle insulating patterns at both sides of a bottom surface of the second source/drain pattern and between the second active pattern and the second source/drain pattern in contact with an inner side surface of the second fence insulating layer;
a first gate electrode and a second gate electrode crossing the first and second active patterns, respectively, and extending in the first direction, each of the first and second gate electrodes including a first portion between the substrate and the first semiconductor pattern, a second portion between the first semiconductor pattern and the second semiconductor pattern, a third portion between the second semiconductor pattern and the third semiconductor pattern, and a fourth portion on the third semiconductor pattern;
inner spacers respectively between the first to third portions of the second gate electrode and the second source/drain pattern;
a first gate insulating layer and a second gate insulating layer respectively between the first channel pattern and the first gate electrode and between the second channel pattern and the second gate electrode;
a first gate spacer and a second gate spacer on side surfaces of the first and second gate electrodes, respectively;
a first gate capping pattern and a second gate capping pattern on top surfaces of the first and second gate electrodes, respectively;
a first interlayer insulating layer on the first and second gate capping patterns;
active contacts penetrating the first interlayer insulating layer and coupled to the first and second source/drain patterns, respectively;
gate contacts penetrating the first interlayer insulating layer and coupled to the first and second gate electrodes, respectively;
a second interlayer insulating layer on the first interlayer insulating layer;
a first metal layer in the second interlayer insulating layer, the first metal layer including first interconnection lines, which are electrically connected to the active contacts and the gate contacts, respectively;
a third interlayer insulating layer on the second interlayer insulating layer; and
a second metal layer in the third interlayer insulating layer, the second metal layer including second interconnection lines, which are electrically connected to the first interconnection lines, respectively.