Patent ID: 11875847
Assignee: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 21:
22. The memory circuit of claim 21, wherein the current mirror circuit comprises:
an input transistor to which the current based upon the input voltage is applied;
a first output transistor in a current mirror arrangement with the input transistor;
a first diode-coupled transistor coupled between the first output transistor and the full read voltage, wherein the regulated voltage is produced at a gate of the first diode-coupled transistor;
a second output transistor in a current mirror arrangement with the input transistor; and
a second diode-coupled transistor coupled between the second output transistor and the fractional read voltage, wherein the regulated fractional voltage is produced at a gate of the second diode-coupled transistor.