Patent ID: 11864393
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A memory device, comprising:
at least one bit line;
at least one word line;
at least one memory cell comprising:
a first transistor comprising a gate electrically coupled to the word line, a first source/drain, and a second source/drain;
a plurality of data storage elements; and
a plurality of second transistors corresponding to the plurality of data storage elements;

a plurality of select bit lines each electrically coupled to a gate of a corresponding second transistor among the plurality of second transistors; and
a controller electrically coupled to the at least one memory cell via the at least one word line, the at least one bit line, and the plurality of select bit lines,
wherein each data storage element among the plurality of data storage elements and the corresponding second transistor are electrically coupled in series between the first source/drain of the first transistor and the bit line, and
wherein the controller is configured to
turn ON the first transistor and a selected second transistor among the plurality of second transistors, correspondingly through the at least one word line and the select bit line coupled to the selected second transistor, and
while the first transistor and the selected second transistor are turned ON, apply different voltages to the at least one bit line, the different voltages corresponding to different operations to be performed on the data storage element coupled to the selected second transistor.