Patent ID: 11917826
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 11:
12. A semiconductor memory device, comprising:
a semiconductor substrate extending in a first direction, a second direction, and a third direction, the first, second, and third directions crossing one another;
a circuitry formed on the semiconductor substrate;
a source line extending in the first direction and the second direction ;
a plurality of word lines, each word line extending in the first direction and the second direction, the word lines being laminated in the third direction;
a plurality of first memory pillars, each first memory pillar penetrating the word lines in the third directions to reach the source line, each first memory pillar having a first diameter, the first memory pillars being arranged in the second direction at first intervals;
a plurality of second memory pillars, each second memory pillar penetrating the word lines in the third directions to reach the source line, each second memory pillar having the first diameter, the second memory pillars being arranged in the second direction at the first intervals, each second memory pillar partially overlapping with at least one of the first memory pillars when viewed in the first direction;
a plurality of third memory pillars, each third memory pillar penetrating the word lines in the third directions to reach the source line, each third memory pillar having the first diameter, the third memory pillars being arranged in the second direction at the first intervals, each third memory pillar partially overlapping with at least one of the second memory pillars when viewed in the first direction;
a plurality of first contacts connected to ends of the first memory pillars, respectively, each first contact extending in the third direction, each first contact having a second diameter different from the first diameter;
a plurality of second contacts connected to ends of the second memory pillars, respectively, each second contact extending in the third direction, each second contact having the second diameter;
a plurality of third contacts connected to ends of the third memory pillars, respectively, each third contact extending in the third direction, each third contact having the second diameter;
a plurality of first bit lines, each first bit line extending in the first direction, the first bit lines being arranged in the second direction, each first bit line being connected to a corresponding one of the first contacts;
a plurality of second bit lines, each second bit line extending in the first direction, each second bit line being arranged next to a corresponding one of the first bit lines in the second direction, each second bit line being connected to a corresponding one of the second contacts; and
a plurality of third bit lines, each third bit line extending in the first direction, each third bit line being arranged next to a corresponding one of the second bit lines in the second direction, each third bit line being connected to a corresponding one of the second contacts,
wherein
a distance between adjacent two of the first contacts is smaller than the first diameter and the second diameter, when viewed in the third direction,
a distance between adjacent two of the second contacts is smaller than the first diameter and the second diameter, when viewed in the third direction, and
a distance between adjacent two of the third contacts is smaller than the first diameter and the second diameter, when viewed in the third direction.