Patent ID: 11971741
Assignee: QUALCOMM INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 17:
18. A system, comprising:
a latching circuit having a signal input, a clock input, a set input, a reset input, and an output, wherein the latching circuit is configured to latch a logic value at the signal input on an edge of a clock signal input to the clock input when the set input and the reset input are de-asserted, and output the latched logic value at the output of the latching circuit;
a signal path having an input and an output, wherein the input of the signal path is coupled to the output of the latching circuit; and
a controller coupled to the set input and the reset input of the latching circuit, wherein the controller has an indicator input, and the controller is configured to:
receive a mode indicator signal at the indicator input;
if the mode indicator signal has a first logic value, de-assert the set input and the reset input; and
if the mode indicator signal has a second logic value, alternately assert the set input and the reset input over multiple consecutive idle periods.