Patent ID: 11942454
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A manufacturing method of a package, comprising:
providing a wafer substrate having a first interconnection structure, first bonding vias, and a first bonding layer disposed over the first interconnection structure, wherein a first capacitor is formed in the first interconnection structure, and the first bonding vias electrically connect the first bonding layer and the first capacitor;
providing a die having a second interconnection structure, second bonding vias, and a second bonding layer disposed over the second interconnection structure, wherein a second capacitor is formed in the second interconnection structure, and the second bonding vias electrically connect the second bonding layer and the second capacitor;
bonding the first bonding layer of the wafer substrate to the second bonding layer of the die such that the first capacitor is electrically connected to the second capacitor; and
laterally encapsulating the die by an encapsulant.