Patent ID: 11908503
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. A nonvolatile memory device, comprising:
an array of magnetic memory cells having a plurality of memory cell groups therein;
a control logic circuit comprising a voltage generator, which is configured to generate a gate voltage;
a row decoder having a word line driver therein, which is driven by the gate voltage and connected to the memory cell array through word lines;
a column decoder connected to the memory cell array through bit lines and source lines; and
a write driver having a write voltage generating circuit therein, which is configured to output: (i) a write voltage proportional to a reference voltage generated using a replica magnetic memory cell based on the reference voltage, and (ii) a compensation voltage generated using a compensation circuit operating as a source follower including a PMOS transistor, and transmit the write voltage to a bit line selected by the column decoder when performing a write operation.