Patent ID: 11971740
Assignee: NXP B.V.
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 16:
17. A circuit comprising
a data-path being arranged between an output of a first set of flop-flops and an input of a second set of flip-flops, and
a timing error detection and correction circuit comprising:
a clock unit configured to receive a reference clock and to provide a delayed reference clock;
a plurality of transition detectors,
wherein each of the plurality of transition detectors are coupled to a a set of nodes on the data-path and configured to detect a data value transition;
an error detection circuit coupled to the transition detector and the clock unit and configured to detect an error in response to a data value transition being detected by one or more of the plurality of transition detectors during a time period between a transition of the reference clock and a corresponding transition of the delayed reference clock;
a timing correction circuit coupled to the error detection circuit and configured
to output a system clock derived from the delayed reference clock and
to provide the system clock to the first set of flip-flops and the second set of flip-flops and

wherein the timing correction circuit is further configured to adapt the system clock in response to an error being detected.