Patent ID: 11869617
Assignee: META PLATFORMS TECHNOLOGIES, LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A system, comprising:
a static random access memory (SRAM) device comprising:
a bit cell array comprising a plurality of bit cells, the plurality of bit cells arranged in a plurality of rows and a plurality of columns, each column of the plurality of columns operatively coupled to a pair of bit lines, wherein the plurality of columns is arranged as a plurality of column groups each comprising a plurality of local columns,
a row decoder that is configured to operatively couple a word line to a row of the plurality of rows of bit cells based at least in part on a row address provided to the row decoder, and
a plurality of column decoders, each associated with a column group of the plurality of column groups, wherein each column decoder is configured to operatively couple a data line to a local column of the plurality of local columns corresponding to a column group of the plurality of column groups associated with said column decoder; and

a controller configured to, for a column group of the plurality of column groups, read the local columns of the plurality of local columns included in the column group by, for a given local column, sensing a voltage difference on a corresponding pair of bit lines, in a rearranged sequential order that is different from a physical sequential order of the plurality of local columns in the column group, and wherein the rearranged sequential order is based at least in part on speed information associated with the local columns of the plurality of local columns such that a first local column is selected before a second local column, the first local columns being associated with a faster bit line than the second local column.