Patent ID: 11869589
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. An apparatus, comprising:
a controller;
a main content addressable memory coupled to the controller; and
a buffer content addressable memory coupled to the controller;
wherein the controller is configured to:
manage a data structure comprising an entry that comprises a mapping between a location of data stored in the main content addressable memory for comparison to input data and a location of corresponding data stored in the buffer content addressable memory; and
write, in the entry, a timestamp indicative of the validity of the data stored in the main content addressable memory; wherein the timestamp corresponds to a time at which the data stored at the location in the main content addressable memory and the data stored at the location in the buffer content addressable memory were concurrently written.