Patent ID: 11908061
Assignee: HUAWEI TECHNOLOGIES CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. A multiprocessor apparatus comprising:
a plurality of processing clusters, each of the plurality of processing clusters configured to execute a grouping of related threads in parallel, each of the plurality of processing clusters comprising:
a general purpose register (GPR);
a plurality of processing cores, each processing core of the plurality of processing cores comprising a temporary register, wherein each processing core of the plurality of processing cores is configured to utilize a respective dedicated portion of the GPR when processing instructions;
a shared memory for the plurality of processing cores; and
a memory read/write hub coupled to the GPR and the shared memory, the memory read/write hub comprising a crossbar switch,
wherein the multiprocessor apparatus is configured to execute instructions of an instruction set architecture, the instructions of the instruction set architecture comprising a move data instruction comprising operands that reference a source temporary register and a destination portion of the GPR; and
in response to execution of the move data instruction:
a processing core of the plurality of processing cores is configure to retrieve data from the source temporary register; and
the memory read/write hub is configured to write, via the crossbar switch, the retrieved data to the destination portion of the GPR, the writing of the retrieved data occurring without first writing the retrieved data to the shared memory.