Patent ID: 11967044
Assignee: SILICON WORKS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 3:
4. The device of claim 2, further comprising:
a second residual block, which is connected to the first dimension reduction layer in series, sequentially performs a group convolution operation using a third-type convolution filter having a square size and a point-wise convolution operation using the second-type convolution filter on the first dimension reduction feature map and performs the residual operation on the basis of results of the operations to generate a second residual feature map; and
a second dimension reduction layer configured to concatenate the input feature map, the first residual feature map, and the second residual feature map and reduce a dimension of a result of the concatenation to the same dimension as the input feature map to generate the output feature map.