Patent ID: 11908802
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 18:
19. A method comprising:
forming a substrate on a peelable carrier, the substrate comprising:
a plurality of dielectric layers;
a plurality of first conductive contacts having a first pitch spacing on a top surface of the substrate;
a plurality of second conductive contacts having a second pitch spacing on the top surface of the substrate;
a plurality of first conductive interconnects disposed within the substrate to couple the plurality of first conductive contacts on the top surface of the substrate with a plurality of conductive contacts having a third pitch spacing on a bottom surface of the substrate; and
a plurality of second conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site; attaching integrated circuit dies to the die sites on the substrate;
forming bumps over the conductive contacts on the bottom surface of the substrate; and

peeling multi-chip packages from the carrier.