Patent ID: 11863183
Assignee: KEPLER COMPUTING INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 18:
19. A system comprising:
a memory;
a processor coupled to the memory; and
a communication interface coupled to the processor, wherein the processor includes a multiplier which comprises:
a 5-input threshold gate having a non-linear polar material, wherein the 5-input threshold gate comprises a first set of capacitors of different sizes;
an inversion circuitry coupled to an output of the 5-input threshold gate; and
a 7-input threshold gate having the non-linear polar material, wherein the 7-input threshold gate comprises a second set of capacitors of different sizes, wherein an output of the inversion circuitry is coupled to two inputs of the 7-input threshold gate, wherein the non-linear polar material includes one of: a ferroelectric material, a paraelectric material, or a non-linear dielectric, and wherein the 5-input threshold gate includes:
a first input coupled to a first capacitor of a first size;
a second input coupled to a second capacitor of the first size;
a third input coupled to a third capacitor of a second size;
a fourth input coupled to a fourth capacitor of the second size; and
a fifth input coupled to a fifth capacitor of the first size, wherein the first capacitor, the second capacitor, the third capacitor, the fourth capacitor, and the fifth capacitor are part of the first set of capacitors.