Patent ID: 11909403
Assignee: INTEL CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. An apparatus comprising:
a duty cycle correction (DCC) circuit to receive a first clock having a first frequency to generate an output which is corrected for duty cycle error; and
a multiplier circuitry coupled to the output of the DCC circuit, wherein the multiplier circuitry is to generate a second clock having a second frequency higher than the first frequency, wherein the multiplier circuitry is independent of a phase locked loop, and wherein the multiplier circuitry includes:
a first delay line to delay the output of the DCC circuit and generate a substantially 90 degree phase shifted signal,
an XOR gate to compare the output of the DCC circuit and the substantially 90 degree phase shifted signal,
a second delay line to delay the substantially 90 degree phase shifted signal and generate a substantially 180 degree phase shifted signal,
an inverter to invert the substantially 180 degree phase shifted signal; and
a phase frequency detector to receive an output of the inverter, and the output of the DCC circuit.