Patent ID: 11961909
Assignee: RENESAS ELECTRONICS CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. A method of manufacturing a semiconductor device including a MISFET, comprising the steps of:
(a) preparing a semiconductor substrate having a main surface, an element isolation region embedded in a trench of the main surface, and an active region surrounded by the element isolation region;
(b) forming a well region of a first conductivity type in the active region of the semiconductor substrate;
(c) after the (b), forming a gate electrode of the MISFET on the well region of the semiconductor substrate via a gate dielectric film, the gate electrode extending in a first direction;
(d) after the (c), by a first ion implantation, forming a first semiconductor region and a second semiconductor region each having a second conductivity type opposite the first conductivity type in the well region, the first semiconductor region and the second semiconductor region being spaced from each other via a region directly below the gate electrode in a second direction perpendicular to the first direction;
(e) after the (c), by a second ion implantation, forming a first region of the first conductivity type and a second region of the first conductivity type spaced from each other in the second direction in the well region, each of the first region and the second region having an impurity concentration higher than that of the well region;
(f) after the (d) and after the (e), forming a sidewall spacer on each of both sidewalls of the gate electrode; and
(g) after the (f), by a third ion implantation, forming a first high concentration region of the second conductivity type in the well region, the first high concentration region having an impurity concentration higher than that of the first semiconductor region, and forming a second high concentration region of the second conductivity type in the well region, the second high concentration region having an impurity concentration higher than that of the second semiconductor region,
wherein a source region of the MISFET is formed by the first semiconductor region and the first high concentration region,
wherein a drain region of the MISFET is formed by the second semiconductor region and the second high concentration region,
wherein the first region is adjacent to the first semiconductor region, the second region is adjacent to the second semiconductor region, and at least a portion of the first region and at least a portion of the second region are located under the gate electrode, and
wherein the first region and the second region are formed at a vicinity of both end portions of the active region in the first direction, while the first region and the second region are not formed at a center portion of the active region in the first direction.