Patent ID: 11915748
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 1:
2. A semiconductor memory device comprising:
a memory cell array including a first memory cell capable of holding at least n-bit data, with n being an integer that is at least 4;
a conversion circuit configured to recover the n-bit data based on m-bit data generated by converting the n-bit data and data written in the first memory cell, with m being an integer that is smaller than n; and
at least one pad connectable with an outside of the semiconductor memory device,
wherein:
an operation of writing the n-bit data in the first memory cell includes a first write operation and a second write operation,
the first write operation is executed based on the n-bit data that is received from the outside, and
the second write operation is executed based on the n-bit data that is recovered by the conversion circuit.