Patent ID: 11935785
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 5:
6. The method of manufacturing a semiconductor structure according to claim 1, wherein said forming the second opening comprises:
forming a third mask layer filling the first opening and covering a top surface of the target layer, and forming a first stop layer and a fourth mask layer sequentially on the third mask layer, wherein the fourth mask layer in the array region and the second circuit region is provided with fourth openings through the fourth mask layer, and a second sidewall layer is formed on an inner wall of the fourth opening in the array region;
forming a fifth mask layer filling the fourth opening and located on a top surface of the fourth mask layer, wherein a top surface of the fifth mask layer in the first circuit region is higher than a top surface of the fifth mask layer in the array region and the second circuit region;
etching back the fifth mask layer to expose the second sidewall layer on top of the fourth mask layer in the array region; and
removing the second sidewall layer, etching the third mask layer and the target layer by use of the fifth mask layer and the fourth mask layer as a mask to form the second opening.