Patent ID: 11963298
Assignee: IBIDEN CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC H  Y | IPC H

Claim 10:
11. A method for manufacturing a printed wiring board, comprising:
forming, on a base insulating layer, a conductor layer including a first conductor pad and a second conductor pad;
forming a solder resist layer on the base insulating layer such that the solder resist layer covers the conductor layer;
forming a first opening in the solder resist layer such that the first opening exposes the first conductor pad of the conductor layer;
forming a second opening in the solder resist layer such that the second opening exposes the second conductor pad of the conductor layer;
forming a first recess on a surface of the first conductor pad exposed by the first opening of the solder resist layer;
forming a second recess on a surface of the second conductor pad exposed by the second opening of the solder resist layer such that a depth of the first recess is larger than a depth of the second recess;
forming, on the first conductor pad, a first bump comprising a first base plating layer in the first opening of the solder resist layer and a first top plating layer on the first base plating layer; and
forming, on the second conductor pad, a second bump comprising a second base plating layer in the second opening of the solder resist layer and a second top plating layer on the second base plating layer,
wherein the forming of the second opening includes forming the second opening in the solder resist layer such that the second opening has a diameter smaller than a diameter of the first opening, the forming of the first bump includes forming the first base plating layer in the first opening, forming the first top plating layer on the first base plating layer, and reflowing the first top plating layer, and the forming of the second bump includes forming the second base plating layer in the second opening, forming the second top plating layer on the second base plating layer, reflowing the second top plating layer, and forming the second bump on the second conductor pad such that the second bump has a diameter smaller than a diameter of the first bump.