Patent ID: 11927632
Assignee: INVENTEC CORPORATION
Field: Measurement (Instruments)
Classification: CPC G | IPC G

Claim 7:
8. The DIMM slot test method without series connection of test board through JTAG according to claim 6, wherein the test board further comprises an analog-to-digital converter (ADC), the ADC is electrically connected to the specified CPLD chip, and the DIMM connector interface, the third test signal generated by the CPU based on the second test signal with JTAG signal format is a power test signal, the CPU transmits the power test signal to the specified one of the at least one CPLD chip through the control pins, the specified one of the at least one CPLD chip tests the power pins through the ADC, the ADC reads the values of the power pins, the specified one of the at least one CPLD chip reads the values of the power pins from the ADC and records the values as the power test result.