Patent ID: 11948937
Assignee: FUJI ELECTRIC CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 1:
2. The semiconductor integrated circuit of claim 1, wherein the edge structure includes:
an enhancement-mode transistor including a first main terminal region of the first conductivity-type having a same potential of the second well and configured to supply the third potential, a second main terminal region of the first conductivity-type to which the first potential is applied, and a first control electrode configured to control a current flowing between the first main terminal region and the second main terminal region;
a Zener diode including a third main terminal region of the second conductivity-type to which the second potential is applied, and a fourth main terminal region of the first conductivity-type connected to the first control electrode; and
a depletion-mode transistor including a fifth main terminal region of the first conductivity-type connected to the fourth main terminal region, a sixth main terminal region of the first conductivity-type to which the first potential is applied, and a second control electrode connected to the first control electrode and configured to control a current flowing between the fifth main terminal region and the sixth main terminal region.