Patent ID: 11869623
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A device, comprising:
a first inverter and a second inverter that are cross coupled between a first node and a second node;
a first transistor configured to couple a first terminal, proving a first supply voltage, to the first inverter and the second inverter in response to a first control signal;
a second transistor configured to couple a second terminal, providing a second supply voltage, to the first inverter and the second inverter in response to a second control signal;
a third transistor coupled to the first node and a fourth transistor coupled to the second node, wherein gates of the third transistor and the fourth transistor receive a third control signal different from the first and second control signals,
wherein a voltage level of the third control signal falls after a voltage level of the first control signal falls, and the first and second control signals having different logic values;
wherein when the third control signal has a first logic value, the third transistor is configured to output a first output signal to the first node and the fourth transistor is configured to output a second output signal to the second node;
wherein when the third control signal has a second logic value, the first transistor is configured to transmit the first supply voltage to the first node and the second transistor is configured to transmit the second supply voltage to the second node;
a third inverter configured to generate, in response to a first input signal, a second input signal for outputting the first output signal;
a fourth inverter configured to generate, in response to the second input signal, a third input signal for outputting the second output signal; and
a fifth inverter configured to generate the second input signal in response to the first input signal,
wherein the device further comprises:
fifth to eighth transistors coupled in series between the first and second terminals, wherein gates of the fifth and eighth transistors are coupled to the second node to receive the second output signal, a gate of the sixth transistor is configured to receive the first control signal, and a gate of the seventh transistor is configured to receive the second control signal, wherein the fifth to eighth transistors are configured to generate a third output signal.