Patent ID: 11915787
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. A method, comprising:
in a memory cell having a plurality of memory strings coupled in parallel between a bit line and a source line, wherein each of the plurality of memory strings comprises n memory elements coupled in series between the bit line and the source line and correspondingly coupled to n word lines, where n is an integer greater than 1, and wherein each memory element of the n memory elements of each of the memory strings is programmable to have different resistances, a programming operation of a selected memory element of the memory cell comprising
applying a turn-ON voltage to, among the n word lines, a word line coupled to the selected memory element for turning ON the selected memory element, and
applying a programming voltage across the selected memory element to individually program the selected memory element to have one of the different resistances.