Patent ID: 11943931
Assignee: STMICROELECTRONICS (ROUSSET) SAS
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 12:
13. A method for manufacturing a non-volatile memory device, the method comprising:
forming a semiconductor well isolated from a carrier substrate by an embedded layer and lateral wells having a conductivity type opposite to a conductivity type of the semiconductor well;
forming trenches in the semiconductor well, the trenches extending into the semiconductor well to the embedded layer;
forming source regions around a bottom portion of the trenches;
depositing a gate dielectric layer on sidewalls of the trenches;
partially filling the trenches with a first conductive material to form select gates in lower portions of the trenches;
forming a gate isolation area over the first conductive material partially filling the trenches;
forming dielectric areas along sidewalls of upper portions of the trenches;
forming a second conductive material over the partially filled trenches; and
planarizing the second conductive material to form control gates.