Patent ID: 11942548
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A multi-gate semiconductor device, comprising:
a fin element extending from a substrate;
a shallow trench isolation (STI) feature on each of two opposing sides of the fin element;
a plurality of nanowire channel layers including a first nanowire channel layer disposed a first distance over the fin element and a second nanowire channel layer disposed a second distance over the first nanowire channel layer;
a gate dielectric material extending from a top surface of the STI feature to over a top surface of the second nanowire channel layer, wherein the gate dielectric material fills the first distance and the second distance;
spacer elements abutting the gate dielectric material between the first nanowire channel layer and the second nanowire channel layer, the spacer elements extending into a source/drain region of the multi-gate semiconductor device; and
a gate electrode disposed over the plurality of nanowire channel layers.