Patent ID: 11922863
Assignee: AUO CORPORATION
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. The pixel circuit according to claim 1, wherein the driving current generator comprises:
a first transistor comprising a first end for receiving a first operation voltage, wherein a control end of the first transistor receives the pulse width modulation enable signal;
a second transistor comprising a first end coupled to a second end of the first transistor, wherein a second end of the second transistor receives second write-in display data, and a control end of the second transistor receives the data write-in signal;
a third transistor coupled in series between the first transistor and the current enabler;
a fourth transistor comprising a first end coupled to a first end of the third transistor, wherein a second end of the fourth transistor is coupled to a control end of the third transistor, and a control end of the fourth transistor is coupled to the control end of the second transistor;
a fifth transistor comprising a first end coupled to the second end of the fourth transistor, wherein a control end and a second end of the fifth transistor jointly receive a reset signal;
a sixth transistor comprising a first end coupled to the second end of the first transistor, wherein a control end of the sixth transistor receives the pulse width modulation enable signal;
a seventh transistor comprising a first end coupled to a second end of the sixth transistor, wherein a second end of the seventh transistor receives a second operation voltage, and a control end of the seventh transistor receives the data write-in signal;
an eighth transistor coupled in parallel with the seventh transistor, wherein a control end of the eighth transistor receives the reset signal; and
a capacitor, coupled between the second end of the sixth transistor and the control end of the third transistor.