Patent ID: 11923869
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 16:
17. The apparatus of claim 16, wherein the support circuitry further includes a plurality of memory buffers, and
wherein the means for dynamically mapping the plurality of LDPC engines to the plurality of memory dies further includes:
means for dynamically allocating the memory operations that are stored in the priority queue to the plurality of LDPC engines,
means for performing parity checking and error correction on the memory operations that have been dynamically allocated to the plurality of LDPC engines,
means for storing the memory operations that have been parity checked and error corrected in the plurality of memory buffers, each memory buffer corresponding to one of the plurality of FCs,
means for retrieving a memory operation that is stored in one of the plurality of memory buffers, and
means for performing the memory operation at the corresponding one of the plurality of memory dies.