Patent ID: 11869968
Assignee: ATOMERA INCORPORATED
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A semiconductor device comprising:
a substrate;
spaced apart doped source and drain regions in the substrate having a first conductivity type, the drain region being larger than the source region to define an asymmetric channel therebetween;
a superlattice extending between the source and drain regions to constrain dopant therein;
the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions;
a well implant constrained within the substrate by the superlattice adjacent the source region and having a second conductivity type different than the first conductivity type; and
a gate overlying the asymmetric channel so that the drain region extends laterally beneath the gate beyond a center thereof.