Patent ID: 11950428
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A memory device, comprising:
a plurality of first stacking structures, disposed on a substrate and comprising first insulating layers and first gate layers alternately stacked on the substrate in a first direction;
a plurality of second stacking structures, disposed on the substrate and comprising second insulating layers and second gate layers alternately stacked on the substrate in the first direction, wherein the plurality of first stacking structures and the plurality of second stacking structures are alternately arranged on the substrate and separated from one another by one of a plurality of trenches along a second direction perpendicular to the first direction;
a plurality of first isolation structures, disposed in the plurality of trenches, wherein a plurality of cell regions are respectively confined between two adjacent first isolation structures of the plurality of first isolation structures in each of the plurality of trenches, and each of the plurality of first isolation structures comprise a first main layer and a first liner surrounding the first main layer;
gate dielectric layers, disposed in the plurality of cell regions and lining sidewalls of the plurality of cell regions, wherein the gate dielectric layers cover portions of the substrate overlapped with the plurality of cell regions;
channel layers, disposed in the plurality of cell regions and each lining a sidewall of a respective one of the gate dielectric layers;
conductive pillars, disposed in the plurality of cell regions and extending in the first direction, wherein every two conductive pillars are placed into a respective one cell region and in contact with one of the channel layers disposed in the respective one cell region; and
a plurality of second isolation structures, disposed in the plurality of cell regions and extending in the first direction, wherein the every two conductive pillars are separated from one another by a respective one of the plurality of second isolation structures, and each of the plurality of second isolation structures comprises a second main layer and a second liner surrounding the second main layer.