Patent ID: 11960437
Assignee: T-HEAD (SHANGHAI) SEMICONDUCTOR CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. A system comprising:
a plurality of parallel processing units (PPUs) included in a first chip, each of the PPUs including:
a plurality of processing cores;
a plurality of memories, wherein a first set of the memories couple to a first set of the plurality of processing cores; and

a plurality of interconnects in an inter-chip network (ICN) configured to communicatively couple the plurality of PPUs,
wherein each of the PPUs is configured to communicate over the ICN in accordance with respective routing tables that are stored and reside in registers included in the respective PPUs,
wherein the respective routing tables comprise information of multiple paths to any given other PPU, and
wherein communications are processed in accordance with the routing scheme that provides balanced workloads, guaranteed dependency, and guaranteed access orders.