Patent ID: 11899958
Assignee: KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A storage device comprising:
at least one non-volatile memory device including a memory cell array with a plurality of memory blocks including a plurality of cell strings that includes at least one string selection transistor each connected between a bitline and a common source line and, a plurality of memory cells corresponding to the respective wordlines, and at least one ground selection transistor, a row decoder configured to, in response to an address, select a memory block from among the plurality of memory blocks and select a wordline from among the wordlines, a page buffer circuitry including a plurality of page buffers connected to bitlines and connected to a memory cell connected to each of the wordlines, a voltage generator configured to generate wordline voltages applied to the wordlines, and a control logic configured to control the row decoder, the page buffer circuitry, and the voltage generator; and
a controller configured to control the at least one non-volatile memory device, to receive a personal information destruction request from an external host device, and to generate a personal information destruction command in response to the personal information destruction request,
wherein the controller identifies at least one memory block including an invalid page in which personal information is stored from among the plurality of memory blocks,
the control logic deletes the personal information by applying at least one deletion duty pulse (DDP) to a wordline corresponding to the invalid page in response to the personal information destruction command, and
a number of the at least one DDP is determined to exceed an error correction level of an error correction code (ECC).