Patent ID: 11943806
Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. The integrated circuit according to claim 1,
wherein the control circuitry, in operation, performs a common buffer status reporting procedure for all data transmission usage scenarios of the communication apparatus,
wherein the control circuitry, when performing the common buffer status reporting procedure, generates a second common buffer status report that separately indicates a buffer status of the logical channel(s) associated with each data transmission usage scenario,
wherein the integrated circuit comprises transmitting circuitry which, in operation, transmits the generated second common buffer status report to the radio base station, and
wherein each data transmission usage scenario encompasses at least one numerology scheme, wherein each data transmission usage scenario is one of massive machine-type communication (mMTC), enhanced mobile broadband (eMBB), or ultra-reliable low-latency communications (URLLC).