Patent ID: 11880306
Assignee: AMPERE COMPUTING LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. A non-transitory computer-readable medium having stored thereon computer-executable instructions which, when executed by a processor, cause the processor to dynamically configure a combined private and shared cache structure to select a private cache portion and a shared cache portion;
wherein:
the combined private and shared cache structure comprises a plurality of ways; and
the computer-executable instructions cause the processor to dynamically configure the combined private and shared cache structure to select the private cache portion and the shared cache portion by causing the processor to:
store a value in a configuration register (CR) that indicates a count of the plurality of ways assigned as the shared cache portion; and
allocate the shared cache portion and the private cache portion to include at least a respective shared portion and a respective private portion of the plurality of ways.