Patent ID: 11916042
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A semiconductor package, comprising:
a substrate;
a first semiconductor chip on the substrate, and having a first region and a second region in a plan view;
a second semiconductor chip on a top surface of the second region of the first semiconductor chip and exposing a top surface of the first region of the first semiconductor chip;
a first signal bonding wire on the top surface of the first region of the first semiconductor chip, and coupled to the first semiconductor chip and the substrate;
a second signal bonding wire on the top surface of the first region of the first semiconductor chip, and coupled to the first semiconductor chip and the second semiconductor chip;
a first ground bonding wire on the top surface the second region of the first semiconductor chip, and coupled to the substrate and the first semiconductor chip; and
a second ground bonding wire on a top surface of the second semiconductor chip and coupled to the substrate,
wherein the second ground bonding wire is spaced apart from the first semiconductor chip and electrically isolated from the first semiconductor chip.