Patent ID: 11934252
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. An apparatus comprising:
a memory array;
a controller coupled with the memory array, the controller configurable to cause the apparatus to:
transition from a first power state having a first current to a second power state having a second current lower than the first current, wherein the first power state is associated with executing received commands and the second power state is associated with deactivating one or more components associated with the memory array;
initiate a timer based at least in part on transitioning from the first power state to the second power state;
determine the timer satisfies a threshold based at least in part on initiating the timer, wherein the threshold is configurable based at least in part on a power performance target of the apparatus or a link target of the apparatus; and
transition, based at least in part on determining the timer satisfies the threshold, from the second power state to a third power state having a third current lower than the second current;
initiate a second timer based at least in part on transitioning from the second power state to the third power state;
determine the second timer satisfies a second threshold based at least in part on initiating the second timer;
transition from the third power state to a fourth power state having a fourth current lower than the third current based at least in part on determining the second timer satisfies the second threshold, wherein the fourth power state is entered while a host system associated with the apparatus is in an idle state;
receive a command associated with synchronizing a cache after transitioning from the third power state to the fourth power state;
transition from the fourth power state to the first power state based at least in part on receiving the command;
execute the command based at least in part on transitioning from the fourth power state to the first power state; and
transition from the first power state to a fifth power state having a fifth current equal to or less than the fourth current based at least in part on executing the command, wherein the fifth power state is associated with decoupling a voltage supply of components of the memory array or the controller.