Patent ID: 11972789
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 1:
2. The circuit according to claim 1,
wherein the comparison circuit comprises a comparison sub-circuit and a first latch sub-circuit, wherein
the comparison sub-circuit has a first input terminal connected to the decoding circuit and a second input terminal connected to an output terminal of the first latch sub-circuit, and the comparison sub-circuit is configured to compare the decoding information with the historical maximum decoding information outputted by the first latch sub-circuit and output an enable signal based on a comparison result; and
the first latch sub-circuit has an input terminal connected to the decoding circuit and an enable terminal connected to an output terminal of the comparison sub-circuit, and the first latch sub-circuit is configured to latch the current maximum decoding information and output the current maximum decoding information in response to the enable signal.