Patent ID: 11948877
Assignee: QUALCOMM INCORPORATED
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A package comprising:
a first substrate structure comprising:
at least one substrate dielectric layer; and
a plurality of substrate interconnects;

a first metallization structure at least partially coplanar with the first substrate structure, wherein the first metallization structure comprises:
at least one first dielectric layer; and
a first plurality of interconnects;

a plurality of metal interconnects coupled to and touching the first plurality of interconnects of the first metallization structure;
a first mold coupled to the first substrate structure and the first metallization structure,
wherein the first mold is located at least between the first substrate structure and the first metallization structure, and
wherein the first mold at least partially encapsulates the first substrate structure and the plurality of metal interconnects;

a portion coupled to and touching the plurality of metal interconnects and the plurality of substrate interconnects, wherein the portion comprises:
at least one portion dielectric layer; and
a plurality of portion interconnects;

a second metallization structure coupled to the first metallization structure and the first substrate structure such that the second metallization structure touches the first metallization structure and the first substrate structure, wherein the second metallization structure comprises:
at least one second dielectric layer; and
a second plurality of interconnects coupled to (i) the first plurality of interconnects of the first metallization structure and (ii) the plurality of substrate interconnects; and

a die coupled to the second metallization structure,
wherein the die is configured to be electrically coupled to the first metallization structure, the first substrate structure and the portion, through the second metallization structure, and
wherein a first electrical path between the die and the portion includes (i) at least one interconnect from the second plurality of interconnects, (ii) at least one substrate interconnect from the plurality of substrate interconnects and (iii) at least one portion interconnect from the plurality of portion interconnects.