Patent ID: 11966480
Assignee: NVIDIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 15:
16. An accelerator circuit comprising:
a copy engine (CE) comprising Advanced Encryption Standard Galois Counter Mode (AES-GCM) hardware configured to perform both encryption and authentication for a plurality of applications, wherein the CE comprises secure memory to store a first context comprising a first encryption key, a first initialization vector (IV), a first hash key, and a first block counter associated with a first application of the plurality of applications, and a second context comprising a second encryption key, a second IV, a second hash key, and a second block counter associated with a second application of the plurality of applications;
an engine scheduler coupled to the CE, wherein:
the engine scheduler is to:
receive an encryption or decryption operation descriptor of a first data transfer of a specified size for the first application; and
split the first data transfer into a set of partial transfers, each partial transfer having a fixed size less than or equal to the specified size and be required to be completed before a context switch to another application;

the copy engine (CE) is to:
sequentially execute the set of partial transfers using the first context until a timeslice timeout for the first application; and
in response to the timeslice timeout for the first application, store a current value for the first hash key and a current value for the first block counter in the secure memory computed from a last partial transfer completed before the timeslice timeout.