Patent ID: 11948639
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 9:
10. The method of claim 1 wherein,
the channel-material strings in a vertical region project laterally outward compared to a portion of the channel-material strings that is immediately-above the vertical region and compared to a portion of the channel-material strings that is immediately-below the vertical region; and
at least a majority of all of the first tiers in a finished construction of the memory array comprise conductive tiers comprising conductive gate lines that are individually operatively laterally proximate the channel-material strings in individual of the conductive tiers, the conductive gate lines comprising part of some of the memory cells in that individual conductive tier, one of the conductive gate lines that is in the vertical region being in the first tier having the larger vertical thickness in the individual memory-block regions and being vertically thicker than another of the conductive gate lines that is immediately-above the vertical region and another of the conductive gate lines that is immediately-below the vertical region.