Patent ID: 11901441
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A method, comprising:
forming a trench over a channel region of a semiconductor layer, the trench having an upper portion over a lower portion;
forming a first glue layer in the trench, the first glue layer having a first portion formed in the upper portion of the trench and a second portion formed in the lower portion of the trench;
forming a second glue layer over the first glue layer, an entirety of the second glue layer being formed in the upper portion of the trench; and
performing an etching process to remove the second glue layer and the first portion of the first glue layer, thereby exposing the second portion of the first glue layer.