Patent ID: 11860730
Assignee: WAYMO LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A device comprising:
an integrated circuit; and
a serial peripheral interface (SPI) communicatively coupled to the integrated circuit,
wherein the SPI comprises a Master In Slave Out (MISO) channel and a Master Out Slave In (MOSI) channel,
wherein the MOSI channel is configured to:
receive a write address within the integrated circuit to be written to;
receive payload data to be written; and
receive a forward error-checking code usable to identify data corruption within the write address or the payload data, and

wherein the integrated circuit is configured to:
calculate a reverse error-checking code based on the received write address and payload data, wherein the reverse error-checking code is usable to identify data corruption within the write address or the payload data;
provide, to the MISO channel, the calculated reverse error-checking code;
compare the forward error-checking code to the reverse error-checking code; and
write, to the write address when the forward error-checking code matches the reverse error-checking code, the payload data.