Patent ID: 11901413
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC B  H

Claim 14:
15. An integrated chip, comprising:
a gate structure overlying a semiconductor substrate;
a source/drain layer disposed on the semiconductor substrate and adjacent a side of the gate structure, wherein the source/drain layer comprises a first dopant; and
a diffusion barrier layer between the source/drain layer and the semiconductor substrate, wherein the diffusion barrier layer comprises a second dopant different from the first dopant, wherein a doping concentration of the second dopant within the diffusion barrier layer is less than a doping concentration of the first dopant within the source/drain layer, and wherein a thickness of the diffusion barrier layer is less than a thickness of the source/drain layer, wherein a region of the semiconductor substrate directly contacting a bottom surface of the diffusion barrier layer has a doping type opposite the first dopant.