Patent ID: 11943933
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 15:
16. A method of manufacturing a memory device, comprising:
forming first metal interconnect structures embedded within at least one lower-level dielectric material layer over a substrate;
forming a thin film transistor over the lower-level dielectric material layer;
forming a ferroelectric memory cell over the at least one lower-level dielectric material layer prior to, or after, formation of the thin film transistor, wherein the ferroelectric memory cell is formed underneath, above, or at a same level as, a level of the thin film transistor; and
forming second metal interconnect structures over the thin film transistor or the ferroelectric memory cell, wherein a subset of the second metal interconnect structures electrically connects a first node of the ferroelectric memory cell to a node of the thin film transistor,
wherein forming the thin film transistor comprises:
forming a thin film transistor gate electrode over the at least one lower-level dielectric material layer;
forming a thin film transistor gate dielectric layer over the thin film transistor gate electrode; and
depositing and patterning a semiconducting metal oxide material layer over the thin film transistor gate dielectric layer.