Patent ID: 11942961
Assignee: STMICROELECTRONICS S.R.L.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 15:
16. A non-transitory computer-readable medium having stored instructions thereon that, when executed by one or more processors, cause the one or more processors to perform a method for testing a circuit including first and second channels, the first channel including a first digital to analog converter having an output coupled to a first input of a first sign comparator, the first channel configured to receive a first analog signal, the second channel including a second digital to analog converter, the second channel configured to receive a second analog signal, the method comprising:
selectively coupling by a switch network, upon reception of a self-test mode signal signaling a test phase, an output of the second digital to analog converter to a second input of the first sign comparator, the first input of the first sign comparator being maintained coupled to the output of the first digital to analog converter;
generating, by a ramp generation circuit, and sending to inputs of the first digital to analog converter and the second digital to analog converter two identical ramps of digital codes, which are shifted by a programmable offset with respect to the other; and
issuing, by a checking circuit coupled to an output of the first sign comparator, a test status signal based on the output of the first sign comparator.