Patent ID: 11955159
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 5:
6. The semiconductor memory device of claim 5, wherein the first command corresponds to a read command including an auto precharge or a write command including an auto precharge,
wherein the row hammer management circuit is configured to perform the internal read-update-write operation in response to:
a chip selection signal having a logic high level, and
a tenth command/address signal from among first through fourteenth command/address signals of the read command including an auto precharge or the write command including an auto precharge,
wherein the tenth command/address signal has a logic low level or a logic high level, and
wherein the tenth command/address signal includes at least one of a command signal and an address signal.