Patent ID: 11880706
Assignee: NANJING QINHENG MICROELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 12:
13. The interrupt control system based on RISC-V according to claim 11, wherein the control and status register set further comprises a programmable fast interrupt control register, and the programmable fast interrupt control register comprises a hardware memory area enhanced control bit HS_ENHANCE;
when HS_ENHANCE=1, the a first-type memory area is not full and the a second-type memory area is full, during an interrupt response, the content of the Caller-save type general-purpose register is protected by software, and the content of the control and status register set is stored in the first-type memory area; and when exiting the an interrupt, the content of the Caller-save type general-purpose register is restored by software, and the content is loaded back from the first-type memory area into the control and status register set; and
when HS_ENHANCE=0, neither the first-type memory area nor the second-type memory area is full, during an interrupt response, the content of the Caller-save type general-purpose register is stored in the second-type memory area, and the content of the control and status register set is stored in the first-type memory area; and when exiting the interrupt, the content is loaded back from the second-type memory area into the Caller-save type general-purpose register, and the content is loaded back from the first-type memory area into the control and status register set; and when the second-type memory area is full, the interrupt is masked.