Patent ID: 11929761
Assignee: SEAGATE TECHNOLOGY LLC
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 3:
4. The apparatus of claim 3 further comprising:
the edge combiner further configured to generate the plurality of output message vectors to provide an output message vector to each check node vector of the check node processor, including:
for the combined output message vector:
XOR a sign bit of v2c message vectors sharing the same target check node to generate the sign information of the combined output message vector;
set the min1 value and min1 value based on magnitudes of the v2c message vectors sharing the same target check node;

for a first output vector message generated for a target check node vector of a single v2c message vector:
set the sign information and the min1 value based on the sign bit and magnitude of the single v2c message vector;
set the min1 value to a maximum magnitude value;

for a second output vector message generated for a target check node of no v2c message vector from the plurality of v2c message vectors:
set the sign information to a ‘0’ value; and
set the min1 value and min1 value to the maximum magnitude value.