Patent ID: 11894089
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. The memory of claim 7, wherein a number of the block data buses is 2*4*(16*N), a number of the local data buses is 2*4*M*(16*N); a number of the odd-numbered block data buses is 4*(16*N), a number of the even-numbered block data buses is 4*(16*N); a number of the local data buses O is 4*M*(16*N), a number of the local data buses E is 4*M*(16*N); one block data bus O corresponds to M local data buses O, one block data bus E corresponds to M local data buses E; and the local data buses are divided into M*(16*N) groups of local data buses O and M*(16*N) groups of local data buses E by taking 4 adjacent local data buses as one group.