Patent ID: 11910590
Assignee: SK HYNIX INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor memory device, comprising:
a substrate;
an active layer spaced apart from the substrate, extending in a direction parallel to the substrate, and including a thin-body channel;
a bit line extending in a direction vertical to the substrate and connected to one side of the active layer;
a capacitor connected to another side of the active layer;
a first word line and a second word line extending in a direction crossing the thin-body channel with the thin-body channel interposed therebetween,
a bit line contact node disposed between one side of the active layer and the bit line;
a bit line side-ohmic contact disposed between the bit line contact node and the bit line;
a storage contact node disposed between another side of the active layer and the capacitor; and
a storage node side-ohmic contact disposed between the storage contact node and the capacitor,
wherein a thickness of the thin-body channel is smaller than thicknesses of the first word line and the second word line.