Patent ID: 11907535
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A device comprising:
a processor;
a memory array comprising:
a plurality of memory devices;
wherein the plurality of memory devices is configurable into one or more namespaces; and

a proof of space optimization logic configured to:
monitor a device status to determine whether one or more proof of space blockchain activities has been detected;
determine that at least a portion of the memory devices are being utilized for one or more proof of space blockchain activities;
in response to proof of space blockchain activity not being detected, continuing to monitor one or more subsequent status or receive commands;
suspend one or more background operations for the portion of memory devices being utilized for the one or more proof of space blockchain activities; and
reinstate, upon a determination that the proof of space blockchain activities have ended, the one or more background operations for the portion of memory devices utilized.