Patent ID: 11961565
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device comprising:
an array of memory cells configured as single-level cell memory; and
control logic operatively coupled with the array of memory cells, the control logic to perform operations comprising:
causing first data to be programmed to a plurality of memory cells of the array of memory cells, the first data comprising a first erase distribution programmed below an erase threshold voltage (Vt) level and a first voltage distribution programmed relative to a first Vt level; and
causing, without erasing the plurality of memory cells, second data to be programmed to the plurality of memory cells, the second data comprising a second erase distribution programmed relative to a second Vt level and a second voltage distribution programmed relative to a third Vt level, wherein the second Vt level is higher than the first Vt level and the third Vt level is higher than the second Vt level.