Patent ID: 11935923
Assignee: GLOBALFOUNDRIES U.S. INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A method comprising:
forming an extrinsic base region vertically over a semiconductor substrate and comprising asymmetrical sidewall spacers on opposing sidewalls of the extrinsic base region;
forming a collector region on the semiconductor substrate and separated from the extrinsic base by at least a first spacer of the asymmetrical sidewall spacers; and
forming an emitter region on the semiconductor substrate and separated from the extrinsic base region by a second spacer of the asymmetrical sidewall spacers;
forming a gate structure adjacent to the collector region; and
a sidewall spacer on the gate structure, wherein the sidewall spacer separates the gate structure from the collector region and the first spacer separates the gate structure from the extrinsic base region.