Patent ID: 11899532
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. The apparatus of claim 9, wherein the one or more controllers is further configured to cause the apparatus to:
select, based at least in part on the timeout duration, the set of memory cells based at least in part on the set of memory cells being associated with a read latency that is less than a latency threshold, an error rate that is less than an error threshold, a quantity of data levels that is less than a data level threshold, or any combination thereof; and
select, based at least in part on the second timeout duration, the second set of memory cells based at least in part on the second set of memory cells being associated with a second read latency that is greater than or equal to the latency threshold, a second error rate that is greater than or equal to the error threshold, a second quantity of data levels that is greater than or equal to the data level threshold, or any combination thereof, wherein the second information for the boot sequence is stored in the second set of memory cells based at least in part on the second set of memory cells being selected.