Patent ID: 11942950
Assignee: ELITE SEMICONDUCTOR MICROELECTRONICS TECHNOLOGY INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A clock signal buffering method, comprising:
(a) filtering a DC component of a differential input signal;
(b) forming a first pair of signal paths for the differential input signal by input terminals of a first amplifier after filtering the DC component;
(c) generating a first output signal by the first amplifier;
(d) forming a second pair of signal paths for the differential input signal by input terminals of a second amplifier;
(e) generating a second output signal by the second amplifier;
(f) generating a frequency detection signal according to a frequency of the differential input signal; and
(g) selectively coupling an output of the first amplifier and an output of the second amplifier according to the frequency detection signal.