Patent ID: 11868204
Assignee: AMAZON TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A system of error detection in an integrated circuit, the system comprising:
a cache memory including a plurality of cache memory lines;
error detection logic coupled to the cache memory, the error detection logic including a plurality of outputs, wherein each of the plurality of outputs has a one-to-one correspondence with the plurality of cache memory lines such that one of the plurality of outputs is configured to be activated when an error is detected on a corresponding cache memory line;
a cache line vector coupled to the plurality of outputs of the error detection logic, the cache line vector including a plurality of memory elements for storing activation data indicating which of the plurality of outputs from the error detection logic has been activated, wherein each of the plurality of memory elements of the cache line vector has a one-to-one correspondence with the plurality of cache memory lines; and
a counter coupled to the cache line vector for counting how many of the plurality of memory elements in the cache line vector are storing activation data.