Patent ID: 11962676
Assignee: SYNOPSYS, INC.
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A clock and data recovery (CDR) system comprising:
compensation circuitry that generates a first compensation signal based on a first compensation value received from via an input node of the compensation circuitry, the compensation circuitry comprises:
a first delay element that delays the first compensation value; and
a summation element that generates a non-linearity signal from the first compensation value and the delayed first compensation value, wherein the first delay element is coupled between the input node and a first input of the summation element, and wherein a second input of the summation element is coupled to the input node; and

phase accumulation circuitry that:
receives the first compensation signal and a phase accumulator input update signal, and
combines the first compensation signal with the phase accumulator input update signal to compensate for a first non-linearity within phase mixer (PMIX) circuitry.