Patent ID: 11916122
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 11:
12. A method, comprising:
forming a plurality of semiconductor nanosheets corresponding to channel regions of a gate all around transistor;
forming, with a first deposition process, a plurality of sheet inner spacers each between a respective pair of semiconductor nanosheets;
forming, with a second deposition process, a cladding inner spacer in contact with each of the nanosheets and the sheet inner spacers, wherein the cladding inner spacer and the sheet inner spacers are different dielectric materials;
forming a source region of the transistor in contact with the semiconductor nanosheets, the sheet inner spacers, and the cladding inner spacer;
depositing a gate dielectric of the transistor on the semiconductor nanosheets and on the sheet inner spacers; and
depositing a gate metal of the transistor on the gate dielectric and between the semiconductor nanosheets.