Patent ID: 11960355
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory system comprising:
a first memory;
an interface circuit configured to receive a first command from an external device, device and receive a second command from the external device after receiving the first command, the first command including information including of a time limit of an error correction to be executed in the memory system, the second command specifying to read data from the first memory; and
a processor circuitry configured to:
select a mode among a first plurality of modes of error correction based on the time limit included in the received first command, the first plurality of modes of error correction being a plurality of kinds of error correction which the memory system is capable of performing;
read the data from the first memory after receiving the second command;
perform, on the read data, an error correction corresponding to the selected mode; and
send a response including unrecovered error to the external device based on a failure of the error correction on the read data.