Patent ID: 11900111
Assignee: QUALCOMM INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 20:
21. A non-transitory computer-readable medium storing instructions that, when executed by a processor, cause the processor to:
access a permutation instruction that includes multiple parameters, wherein one or two of the multiple parameters are register selection order parameters that characterize a register selection order, wherein each of the register selection order parameters is a scalar value, and wherein one of the register selection order parameters is a periodicity parameter indicating a count of vector registers of a plurality of vector registers that contain source data for the permutation instruction, wherein the register selection order indicates a repeated pattern of register selection, wherein the periodicity parameter indicates a length of the repeated pattern, and wherein a particular source vector register is included once during each iteration of the repeated pattern; and
execute the permutation instruction to, for each particular element of multiple elements of a first permutation result register of the plurality of vector registers:
select, based on the register selection order, a vector register of the plurality of vector registers; and
populate the particular element based on a value in a corresponding element of the selected vector register.