Patent ID: 11892950
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. An apparatus comprising:
one or more processors including one or more graphics processing units (GPUs);
one or more caches to provide storage for the one or more processors, the one or more caches including an instruction cache to receive instructions for execution; and
a hardware prefetcher;
wherein the apparatus to provide prefetching for the instruction cache including:
receiving a command to load block instructions in instruction code,
commencing execution of a current kernel for an application, a driver for the application being aware of a next kernel for the application to follow the current kernel, and
upon commencing execution of the current kernel, issuing a prefetch for the next kernel for execution, the prefetch for the next kernel being made directly into the instruction cache.