Patent ID: 11925011
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A memory structure comprising:
an n-well disposed between a first p-well and a second p-well along a first direction, wherein the n-well, the first p-well, and the second p-well extend along a second direction that is different than the first direction and the n-well, the first p-well, and the second p-well span a first region and a second region along the second direction;
in the first region, a pass-gate FinFET and a pull-down FinFET disposed over the second p-well, wherein:
the pass-gate FinFET and the pull-down FinFET include and share a first p-type semiconductor fin extending from the second p-well, wherein the first p-type semiconductor fin extends lengthwise along the second direction and the first p-type semiconductor fin has a first width along the first direction, and
the pass-gate FinFET and the pull-down FinFET include n-type epitaxial source/drains disposed on the first p-type semiconductor fin; and

in the second region, a dummy FinFET is disposed over the second p-well, wherein:
the dummy FinFET includes a second p-type semiconductor fin extending from the second p-well, wherein the second p-type semiconductor fin extends lengthwise along the second direction and the second p-type semiconductor fin has a second width along the first direction,
the dummy FinFET includes p-type epitaxial source/drains disposed on the second p-type semiconductor fin, and
the second width is greater than the first width.