Patent ID: 11908739
Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. The apparatus of claim 1, wherein:
the first bonding surface comprise a first flat conductive metal feature having a width of at least 5 microns on the first substrate, wherein a dishing concavity across the width of the first flat conductive metal feature has a maximum dishing depth of less than 10 nanometers for each micron (nm/μ) of depth of the first flat conductive metal feature; and
the second bonding surface comprise a second flat conductive metal feature having a width of at least 5 microns on the second substrate, wherein a dishing concavity across the width of the second flat conductive metal feature has a maximum dishing depth of less than 10 nanometers for each micron (nm/μ) of depth of the second flat conductive metal feature.