Patent ID: 11893251
Assignee: APPLE INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. An apparatus, comprising:
a system memory circuit;
a cache memory circuit; and
a processing circuit configured to:
allocate a portion of the system memory circuit to a buffer having a plurality of storage locations; and
issue a plurality of memory transactions in a particular order, different from a linear order, to allocate respective storage locations of the plurality of storage locations into the cache memory circuit; and

wherein the cache memory circuit is configured to:
in response to receiving, in the particular order, content from respective ones of the plurality of memory transactions, cache at least a subset of the plurality of storage locations of the buffer in the cache memory circuit;
track a cache miss rate in the cache memory circuit for memory transactions that include accesses to the plurality of storage locations; and
in response to a determination that the tracked cache miss rate satisfies a threshold rate, modify the particular order.