Patent ID: 11928176
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A computer-based method for multiplying matrices, comprising:
a matrix multiply accelerator (MMA) having an array of processing engines (PEs) multiplying, based on a bitmap or index, a compressed first matrix and a second matrix to generate an output matrix over a number of calculation cycles, the bitmap or index relating elements of the compressed first matrix to corresponding elements of a first matrix from which the compressed first matrix is derived, said multiplying including:
for each element i,j of the output matrix, calculating a dot product of an ith row of the compressed first matrix and selected elements of a jth column of the second matrix based on the bitmap or index; or

the matrix multiply accelerator (MMA) multiplying, based on the bitmap or index, selected elements of the second matrix and the compressed first matrix to generate the output matrix over a number of calculation cycles, said multiplying including:
for each element i,j of the output matrix, calculating a dot product of selected elements of an ith row of the second matrix and a jth column of the compressed first matrix based on the bitmap or index,

 where calculating a dot product in a PE of the array of PEs includes:
storing a row or column of the compressed first matrix in a first vector register as a first compressed vector;
storing a column or row of the second matrix in a second vector register as a second vector;
for each calculation cycle:
selecting, by a multiplexer circuit of the PE, an element of a second vector from the second vector register based on the bitmap or index;
multiplying, by a multiplier circuit of the PE, an element of the first compressed vector and the selected element of the second vector to produce an intermediate product; and
accumulating, by an accumulator circuit of the PE, the intermediate product to update a dot product of the first compressed vector and selected elements of the second vector; and

storing the dot product in an output register as element i,j of the output matrix, where each calculation cycle consumes one element of the first compressed vector.