Patent ID: 11909421
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G  Y | IPC G  H

Claim 19:
20. The MAC operator of claim 19, wherein the normalizer includes:
a floating-point moving circuit configured to receive the 16-bit second intermediate mantissa multiplication data to output 16-bit third intermediate mantissa multiplication data obtained by moving a binary point by 1 bit toward the MSB of the second intermediate mantissa multiplication data;
a multiplexer configured to receive the second intermediate mantissa multiplication data and the third intermediate mantissa multiplication data, and when the MSB of the second intermediate mantissa multiplication data is ‘0’ and ‘1’, output the second intermediate mantissa multiplication data and the third intermediate mantissa multiplication data, respectively, as fourth intermediate mantissa multiplication data; and
a round processing circuit configured to remove bits with an implicit bit for the fourth intermediate mantissa multiplication data output from the multiplexer and perform round processing to output an 11-bit mantissa of the multiplication result data of the floating-point format.