Patent ID: 11942935
Assignee: STMICROELECTRONICS (ROUSSET) SAS
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. A method, comprising:
receiving a plurality of input signals at a logic cell of a programmable logic array;
generating, with the logic cell, a direct output signal based on the plurality of input signals;
generating, with the logic cell, a synchronized output signal by passing the direct output signal through a flip-flop of the logic cell;
generating a first clock signal, including:
receiving a global clock signal at a first input terminal or an AND gate;
receiving a selected input signal input from the plurality of input signals at a second input terminal of the AND gate; and
outputting the first clock signal from an output terminal of the AND gate; and

passing, to a clock-input terminal of the flip-flop, the first clock signal.