Patent ID: 11929084
Assignee: FRAUNHOFER GESELLSCHAFT ZUR FÖRDERUNG DER ANGEWANDTEN FORSCHUNG E.V.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. An audio decoder for decoding an encoded audio signal comprising a first encoded audio signal portion and a second encoded audio signal portion to obtain a decoded audio signal, comprising:
a first decoding processor configured for decoding the first encoded audio signal portion in a frequency domain to obtain a decoded time domain first audio signal portion;
a second decoding processor configured for decoding the second encoded audio signal portion in the time domain to acquire a decoded time domain second audio signal portion having a low band and a high band; and
a combiner configured for combining the decoded time domain first audio signal portion and the decoded time domain second audio signal portion to acquire the decoded audio signal
wherein the audio decoder further comprises a cross-processor configured for calculating, from the decoded spectral representation of the first encoded audio signal portion, initialization data of the second decoding processor, so that the second decoding processor is initialized to decode the encoded second audio signal portion following in time the first audio signal portion in the encoded audio signal, wherein the cross-processor comprises:
a frequency-time converter configured for converting the decoded spectral representation to obtain a further decoded first signal portion in the time domain;
a pre-emphasis filter configured for filtering the further decoded first signal portion to obtain a filtered version; and
a delay stage f configured or delaying the filtered version to obtain a delay stage output and for feeding the delay stage output into a prediction synthesis filter of the second decoding processor for for initialization, or
a frequency-time converter configured for converting the decoded spectral representation to obtain a further decoded first signal portion in the time domain; and a switch configured for feeding the further decoded first signal portion or a delayed further decoded first signal portion into an analysis stage of a resampler of the second decoding processor for an initialization.