Patent ID: 11955200
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. A dynamic random access memory (DRAM) device, comprising:
command/address (C/A) circuitry including a first (C/A) interface for coupling to a first memory channel and a second C/A interface for coupling to a second memory channel independent from the first memory channel;
wherein the C/A interface circuitry is configurable to operate in one of at least two modes including
a first operating mode to receive a first read command for first read data via the first C/A interface and a second read command for second read data via the second C/A interface, the first and second C/A interfaces to receive the first and second read commands in accordance with a first read delay and at a first serialization ratio; and
a second operating mode to receive the first read command for the first read data via the first C/A interface and the second read command for the second read data via the second C/A interface, the first and second C/A interfaces to receive the first and second read commands in accordance with a second read delay and at a second serialization ratio, wherein the second read delay is different than the first read delay.