Patent ID: 11868210
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. A method, comprising:
performing, via control circuitry, a parity operation on a first set of data of a plurality of memory cells coupled to access lines of an array resulting in a first set of parity data corresponding to each of the access lines resulting in access line parity data;
performing, via a host, an additional parity operation on a second set of data of a plurality of memory cells coupled to sense lines of the array resulting in a second set of parity data corresponding to each of the sense lines resulting in sense line parity data;
sending the access line parity data and the sense line parity data to the host;
generating crossed matrix parity values, via the host, using the access line parity data and the sense line parity data and using the crossed matrix parity values to generate instructions;
receiving, at the control circuitry and from the host, the instructions to perform an error correction operation on at least a portion of the plurality of memory cells based on the crossed matrix parity values; and
performing the error correction operation on the at least a portion of the plurality of memory cells.