Patent ID: 11947483
Assignee: XCONN TECHNOLOGIES HOLDINGS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. A Compute Express Link Internet Protocol (CXL IP) switch, comprising:
a plurality of ports through which transactions ingress and egress the CXL IP switch;
a plurality of port logic modules coupled with the plurality of ports, each port logic module having core clock domain logic for a core clock domain specific to a corresponding port of the plurality of ports, each port logic module including a clock domain crossing (CDC) first-in-first-out (FIFO) buffer, the CDC FIFO buffer being configured for managing a transition between the core clock domain and a system clock domain, each port control logic module being configured to combine a first number of port streams from the corresponding port to a second number of system streams and to separate the second number of system streams into the first number of port streams, each port control logic module controlling flow through the port for a host via credit granting, the port control logic module configured to decrement a pending credit count for the host based on a write request for a pending credit buffer and increment the pending credit count for a read request for the pending credit buffer, each port logic module further including routing logic, the routing logic configured to allow a response transaction to bypass a request transaction and to prevent the request transaction from bypassing the response transaction, wherein the second number of system streams includes a with data stream and a no data stream, the with data stream corresponding to transactions including a data payload, the no data stream corresponding to transactions free of a data payload, and wherein the port streams include cache streams and memory streams, the cache streams including a request stream, a plurality of response streams, and a data stream, the data stream being merged with a first memory stream having data payload into the with data stream, the request stream, the plurality of response streams, and a second memory stream not having the data payload being merged into the no data stream;
a memory including a plurality of banks; and
a switch fabric, wherein the memory and the switch fabric have the system clock domain, the core clock domain for each of the plurality of port logic modules being different from the system clock domain.