Patent ID: 11901230
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A manufacturing method of a semiconductor package, comprising:
ablating material from a first surface of a substrate to form a through hole in the substrate, the through hole opening at the first surface of the substrate and at a second surface opposite to the first surface;
plugging an end of the through hole at the second surface of the substrate;
sputtering a first barrier material on the substrate, from the side of the first surface, whereby the first barrier material is deposited on sidewalls and at the plugged end of the through hole;
sputtering a first seed material on the first barrier material;
plating a first conductive material on the first seed material while the through hole is still plugged;
unplugging the through hole to reveal at least a portion of the first barrier material at the end of the through hole;
etching the portion of the first barrier material at the end of the through hole; and
plating a second conductive material on an opposite side of the first seed material with respect to the first conductive material.