Patent ID: 11916770
Assignee: CISCO TECHNOLOGY, INC.
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. A system comprising:
one or more processors; and
one or more non-transitory computer-readable media storing computer-executable instructions that, when executed by the one or more processors, cause the one or more processors to perform operations including:
receiving, at a first device, one or more packets of a flow, the one or more packets having a Real-time Transport Protocol (RTP) header including a source time stamp that indicates a time at which the one or more packets were generated the first device being at a first location;
determining, using the source time stamp and a first local time at the first device, a first latency associated with the one or more packets of the flow passing through the first device;
receiving, at a second device, the one or more packets of the flow;
determining, using the source time stamp and a second local time at the second device, a second latency associated with the one or more packets of the flow passing through the second device, the second device being at a second location;
determining that latency was increased in the flow between the first location and the second location based at least in part on the second latency being greater than the first latency;
identifying an intermediate device located at a third location along a network path between the first location and the second location;
determining that the intermediate device caused the increased latency based at least in part on the latency increasing in the flow between the first and second locations and the intermediate device being at the third location between the first and second locations; and
providing a message to an administrator associated with the network path indicating that the intermediate device is causing jitter in the network path.