Patent ID: 11887968
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. The method of claim 1, wherein the plurality of second semiconductor chips further includes a second through-electrode electrically connected to the second connection pad, and
the method further comprises:
after stacking the plurality of second semiconductor chips, grinding the plurality of second semiconductor chips to form a ground surface in each of the plurality of second semiconductor chips, the second through-electrode having a tip protruding above the ground surface of each of the plurality of second semiconductor chips;
forming a third upper insulating layer on the plurality of second semiconductor chip to cover the protruding tip of the second through-electrode;
grinding the third upper insulating layer to expose an upper surface of the second through-electrode;
forming a fourth upper insulation layer on the third upper insulation layer and a second bonding pad connected to the second through-electrode, an upper surface of the fourth upper insulating layer being substantially coplanar with an upper surface of the second bonding pad; and
stacking a plurality of third semiconductor chips on the plurality of second semiconductor chips, respectively, each of the plurality of third semiconductor chips having a third connection pad directly bonded to the second bonding pad, and a third lower insulation layer directly bonded to the second upper insulation layer.