Patent ID: 11881820
Assignee: SMARTER MICROELECTRONICS (GUANG ZHOU) CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A power control circuit, comprising:
a radio frequency signal path; and
a negative feedback loop;
wherein
the radio frequency signal path comprises: a first NMOS transistor and a second NMOS transistor;
a gate of the first NMOS transistor is configured as a radio frequency signal input end, a drain of the first NMOS transistor is connected with a source of the second NMOS transistor, and a source of the first NMOS transistor is connected with a ground terminal; a drain of the second NMOS transistor is configured as a radio frequency signal output end and is connected with a first voltage source;
the negative feedback loop comprises: a third NMOS transistor, a fourth NMOS transistor and a differential amplifier;
a gate of the third NMOS transistor is connected with an output end of the differential amplifier, a source of the third NMOS transistor is connected with the ground terminal, and a drain of the third NMOS transistor is connected with a source of the fourth NMOS transistor; a gate of the fourth NMOS transistor is connected with a reverse input end of the differential amplifier and is connected with a second voltage source, and a drain of the fourth NMOS transistor is connected with a forward input end of the differential amplifier and is connected with a first bias current source;
the gate of the first NMOS transistor is connected with the output end of the differential amplifier; a gate of the second NMOS transistor is connected with the second voltage source;
each of the second NMOS transistor and the fourth NMOS transistor operates in a saturation region, so that power control of the first NMOS transistor is performed;
the power control circuit further comprising:
a first resistor; wherein the gate of the first NMOS transistor is connected with the output end of the differential amplifier via the first resistor;
a second resistor; wherein the gate of the second NMOS transistor is connected with the second voltage source via the second resistor; and
an inductor; wherein the drain of the second NMOS transistor is connected with the first voltage source via the inductor.