Patent ID: 11860793
Assignee: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. A computing system comprising:
a controller configured to create a page table comprising page table entries comprising mapping information for translating a virtual address to a physical address, and store a part of the page table entries; and
a main memory comprising a physical memory, and configured to store the page table in the physical memory,
wherein each of the page table entries comprises a virtual page number, a physical frame number, valid information, and size information,
wherein the virtual address comprises the virtual page number,
wherein the physical address comprises the physical frame number,
wherein the valid information comprises a first predetermined number of bits,
wherein the size information comprises a second predetermined number of bits,
wherein the first predetermined number of bits of the valid information represents an address translation range in a page table entry or a number of page table entries to be grouped,
wherein the size information represents a size indicated by each bit of the first predetermined number of bits of the valid information,
wherein the controller is configured to create the page table entry of the page table entries by mapping the virtual page number to the physical frame number, set a selected bit of the first predetermined number of bits of the valid information to a first state, and set the second predetermined number of bits of the size information to an initial state, and
wherein the controller is configured to combine the valid information in the created page table entry with valid information in at least one previously created page table entry.