Patent ID: 11875053
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. The read operation circuit according to claim 1, wherein the data buffer module comprises a plurality of PMOS transistors, a gate of each of the plurality of PMOS transistors being connected to the memory bank, a drain of each of the plurality of PMOS transistors being connected to the global bus; and wherein the precharge module comprises a plurality of NMOS transistors and a plurality of hold circuits, a gate of each of the plurality of NMOS transistors being connected to the precharge signal line, a drain of each of the plurality of NMOS transistors being connected to the global bus, and an input terminal and an output terminal of each of the plurality of hold circuits being connected to the global bus.