Patent ID: 11886365
Assignee: APPLE INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A system, comprising:
a processing circuit including one or more processing cores;
a memory;
an intermediate storage buffer;
a plurality of peripherals, including at least one audio peripheral;
a communication fabric; and
a direct memory access (DMA) control circuit coupled to the memory via the communication fabric and to the plurality of peripherals via a peripheral interface, wherein the DMA control circuit is configured to:
receive, from the processing circuit, quality of service (QoS) information for a plurality of DMA channels corresponding to different ones of the plurality of peripherals;
receive transfer descriptor information indicating locations and sizes of sample buffers in the memory for different ones of the plurality of DMA channels;
control timing of data transfers from different ones of the sample buffers to the intermediate storage buffer, including by outputting a priority value indicative of a priority of the DMA control circuit for accesses to the memory, wherein the priority value for a particular DMA channel is generated based on current channel conditions and QoS information for that channel;
control data transfers between the intermediate storage buffer and interfaces to different ones of the plurality of peripherals; and
store, for respective data transfers, timestamp information that is accessible by the one or more processing cores, wherein the timestamp information includes timing information indicative of when portions of the respective data transfers are completed.