Patent ID: 11915775
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. An apparatus comprising:
a memory array comprising a plurality of word lines, each associated with one of a plurality of row addresses;
a repair circuit configured to remap a plurality of repaired addresses to a respective one of a plurality of redundant word lines, and
a disable control circuit configured to receive a row address, compare the received row address to a selected row address, and provide a kill signal at an active level,
wherein responsive to the kill signal at the active level, access operations to a selected word line of the plurality of word lines associated with the selected address are caused to fail to cause the selected row to temporarily appear to be a defective row by changing a value of at least one data bit in the selected word line,
wherein, when the apparatus is entered into a bad row mode to disable the selected word line and test a repair logic configured to detect defective rows of the memory array, the selected word line is detected as the defective row responsive to a failure of an access operation on the selected row, the disable control circuit disables the selected word line, and the repair circuit performs a post-package repair (PPR) operation on the selected word line, and
wherein, when the apparatus is exited from the bad row mode, the selected word line is not disabled.