Patent ID: 11960429
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. A method implemented by a Peripheral Component Interconnect Express (PCIe) switch chip including a first plurality of PCIe ports coupled to a plurality of host nodes having memory via a first plurality of PCIe links and a second plurality of PCIe ports coupled to respective PCIe Input/Output (I/O) devices via a second plurality of PCIe links, the method comprising:
receiving packets from the plurality of PCIe I/O devices relating to PCIe transactions initiated by the PCIe I/O devices;
for at least a portion of the packets that are received,
inspect the packet to determine its destination memory address, the destination memory address comprising a memory address in an application address space for one of the plurality of host nodes; and
forward the packet to a host node having an application address space including the destination memory address.