Patent ID: 11973061
Assignee: YIBU SEMICONDUCTOR CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A chip package, comprising:
a redistribution layer; and
a stack of chip layers, each respective chip layer in the stack of chip layers including at least one chip having chip contacts on a front side and the front side facing the redistribution layer, the stack of chip layers including first chip layers and a second chip layer assembled on the first chip layers, the first chip layers including a bottom chip layer adjacent the redistribution layer and at least one middle chip layer between the bottom chip layer and the second chip layer, the first chip layers further including chip couplers, wherein each chip coupler in a particular chip layer of the first chip layers is disposed next to at least one chip in the particular chip layer and stacked immediately above or below a chip coupler in another chip layer, wherein the each chip coupler has a top surface facing away from the redistribution layer, a bottom surface facing the redistribution layer, top coupler contacts formed on the top surface, bottom coupler contacts formed on the bottom surface, and through vias between the top surface and the bottom surface, each respective through via of the through vias extending through the each chip coupler to couple a respective top coupler contact to a respective bottom coupler contact, wherein at least a subset of the top coupler contacts of each chip coupler in the bottom chip layer are respectively coupled to corresponding bottom coupler contacts of a chip coupler in a middle chip layer immediately above the bottom chip layer, and wherein at least a subset of the bottom coupler contacts of each chip coupler in the at least one middle chip layer are respectively coupled to corresponding top coupler contacts of a chip coupler in a chip layer immediately below the each chip coupler in the at least one middle chip layer;
wherein the redistribution layer is formed on a side of the bottom chip layer facing away from the at least one middle chip layer.