Patent ID: 11876127
Assignee: RENESAS ELECTRONICS CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 18:
19. The method of manufacturing the semiconductor device according to claim 16 further comprising:
a step of forming a third implantation layer for forming a second germanium implantation layer in a portion closer to the second main surface than the first germanium implantation layer by an ion implantation method of doping with germanium to the second main surface of the silicon substrate,
wherein, in the step of forming the second implantation layer, the first germanium implantation layer, the number of which is one or plural, is formed,
in the step of forming the third implantation layer, the second germanium implantation layer, the number of which is one or plural, is formed in a region where the first germanium implantation layer, the number of which is one or plural, is not formed in a planar view, and
the second dislocation suppressing layer, the number of which is one or plural, is formed by the annealing step activating the second germanium implantation layer, the number of which is one or plural.