Patent ID: 11908841
Assignee: ELUX, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 39:
40. A method for fabricating a back emission backplane, the method comprising:
providing a transparent substrate with a top surface;
depositing a first dielectric layer having a bottom surface overlying the substrate top surface;
forming a power interface layer from the first dielectric layer, including a first plurality of first electrical contacts, a first plurality of second electrical contacts, and a first plurality of apertures formed between the top surface and the bottom surface;
depositing a second dielectric layer having a bottom surface overlying the power interface layer top surface;
forming an emission layer from the second dielectric layer including a first plurality of sub-pixel regions, forming each sub-pixel as follows:
patterning the emission layer to form a well overlying a corresponding aperture, a first via overlying a corresponding first electrical contact, and a second via overlying a corresponding second electrical contact;
depositing an electrically conductive metal in the emission layer first and second vias;

positioning back emission micro-light emitting diodes (microLEDs) with an emissive bottom surface interfacing a corresponding aperture;
wherein patterning the emission layer includes patterning the second via in a ring shape surrounding the well; and,
wherein depositing metal in the emission layer vias includes filling the second via ring with an optically reflective metal.