Patent ID: 11921641
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. An apparatus, comprising:
means for mapping a plurality of superblocks of a nonvolatile memory to a plurality of zones, each of the plurality of zones being of a type requiring sequential write of host data therein, an erase block being a minimum erasable unit of the plurality of superblocks;
means for performing logical-to-physical (L2P) address translation using a compacted L2P table having an erase-block granularity; and
means for obtaining a corresponding physical address for a logical address of a zone of the plurality of zones, the means for obtaining including:
means for retrieving a physical address of a corresponding erase block from the compacted L2P table;
means for calculating a corresponding word-line number, a corresponding string-line number, a corresponding page-type identifier, and a corresponding page offset based on the logical address; and
means for combining the physical address that is retrieved with the corresponding word-line number, the corresponding string-line number, the corresponding page-type identifier, and the corresponding page offset.