Patent ID: 11894092
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 17:
18. A memory system comprising:
a nonvolatile memory device; and
a memory controller configured to control the nonvolatile memory device,
wherein the nonvolatile memory device comprises:
a memory cell region comprising a first metal pad;
a peripheral region comprising a second metal pad, the peripheral region being connected to the memory cell region through the first metal pad and the second metal pad;
a memory cell array comprising a plurality of memory cells forming a plurality of strings in a direction substantially perpendicular to a substrate, the memory cell array being included in the memory cell region;
wherein the peripheral region further comprises:
a row decoder comprising a pass transistor configured to switch a plurality of word lines connected to the plurality of memory cells, configured to select, through the plurality of word lines, a memory block that is included in the memory cell array;
a voltage generator included in the peripheral region and configured to generate a plurality of voltages provided to the memory cell array and the pass transistor; and
a control logic included in the peripheral region and configured to decrease, based on a first erase command, a gate-source potential difference of the pass transistor to detect a leakage current of a word line in the memory block,
wherein the memory controller is configured to count the number of erases of the memory block, issue the first erase command when the number of erases reaches a reference value, and detect the leakage current.