Patent ID: 11908538
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 12:
13. A method of fabricating an integrated circuit, the method comprising:
forming a first conductor layer over the integrated circuit, wherein the first conductor layer includes a conductor stripe that is divided into multiple conductor segments and a first power stripe that is configured to provide a first voltage signal;
forming a contact layer overlying the first conductor layer;
forming a second conductor layer overlying the contact layer and comprising a second power stripe and one or more conductor pillars, wherein the second power stripe is configured to provide a second voltage signal, wherein a contact in the contact layer electrically connects a first conductor segment in the multiple conductor segments to the second power stripe to provide the second voltage signal to the first conductor layer, and wherein each conductor pillar is electrically connected to the first power stripe,
forming a third conductor layer disposed between the first and second conductor layers, the third conductor layer providing one or more contacts between the first and the second conductor layers.