Patent ID: 11942444
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A method for manufacturing a semiconductor device assembly, comprising:
aligning a first interconnect structure on a first surface of a first semiconductor device with a second interconnect structure on a second surface of a second semiconductor device, the second interconnect structure being configured to receive the first interconnect structure; and
bonding the first semiconductor device to the second semiconductor device by:
forming, in a first plane, metal-metal bonds between a first conductive element in the first interconnect structure and a second conductive element in the second interconnect structure, and
forming, in a second plane, a first oxide-oxide bond between a first surface of a first perimeter structure in the first interconnect structure and a corresponding second surface of a second perimeter structure of the second interconnect structure, wherein the second plane is vertically offset from the first plane.