Patent ID: 11894306
Assignee: PING-JUNG YANG
Field: Semiconductors (Electrical engineering)
Classification: CPC H  C  Y | IPC H

Claim 9:
10. A chip package comprising:
a solid layer having a first surface and a second surface opposite to said first surface, wherein said solid layer comprises a compound of silicon and oxygen, wherein said solid layer has a thickness between 100 and 300 micrometers, wherein said solid layer comprises a first region and a second region between said first region and a first edge of said solid layer;
a plurality of copper posts in a plurality of through holes in said second region respectively, wherein said first region has a width in a direction greater than a shortest distance between a sidewall of one of said plurality of through holes and said first edge in said direction and greater than a pitch between two neighboring copper posts of said plurality of copper posts;
a first interconnection scheme over said first surface, wherein said first interconnection scheme comprises a first metal interconnect over said first surface, and a polymer layer over said first metal interconnect, wherein said first metal interconnect is connected to one of said plurality of copper posts, wherein said first metal interconnect comprises a first metal layer and a first copper layer over said first metal layer;
a first metal bump over said first interconnection scheme, wherein said first metal bump comprises a first tin-containing layer;
a second metal bump over said first interconnection scheme;
a first semiconductor chip over said first interconnection scheme and between said first and second metal bumps, wherein said first semiconductor chip has a height between a backside surface of said first semiconductor chip and a top surface of said polymer layer is smaller than a thickness of said first metal bump, wherein said first semiconductor chip comprises a third metal bump on a first metal pad of said first semiconductor chip, wherein said third metal bump comprises a second tin-containing layer; and
a second semiconductor chip over said first interconnection scheme, wherein said second semiconductor chip comprises a fourth metal bump on a second metal pad of said second semiconductor chip, wherein said fourth metal bump comprises a third tin-containing layer.