Patent ID: 11934480
Assignee: MACRONIX INTERNATIONAL CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 21:
22. The circuit of claim 17, wherein, for each tile, blocks in the plurality of NAND blocks each include B*S NAND strings including B columns and S rows of NAND strings, and L levels of memory cells, wherein B, S and L are integers, the NAND strings including L memory cells in series in respective levels of the L levels;
a set of (S) NAND strings in respective columns in the B columns coupled to corresponding bit lines in a set of B bit lines;
string select switches in a set of (B) NAND strings in respective rows in the S rows coupled to a corresponding string select line in a set of S string select lines;
a set of (B*S) memory cells in respective levels in the L levels operatively coupled to a corresponding word line or word lines in the L levels; and
a source line operatively coupled to the B*S NAND strings in the block.