Patent ID: 11886354
Assignee: APPLE INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A method, comprising:
executing, by a computing system, program instructions that cause access to a first cache circuitry at a first level in a cache hierarchy and a second cache circuitry at a second, different level in the cache hierarchy;
inserting, by the computing system, data into the first cache circuitry according to a first cache insertion policy over a first set of processor cycles;
evaluating, by the computing system, respective values of a performance metric for the first cache circuitry and for the second cache circuitry; and
in response to detecting that the value of the performance metric for the first cache circuitry does not meet a first threshold and that the value of the performance metric for the second cache circuitry meets a second threshold, the computing system determining to replace the first cache insertion policy with a second cache insertion policy over a second set of processor cycles, wherein the second threshold is greater than the first threshold.