Patent ID: 11869826
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. The memory module of claim 7 wherein:
the surface is a first surface;
the substrate includes a second surface opposite the first surface having a central portion, a first array area on one side of the central portion and a second array area on an opposite side of the central portion, wherein the first array area on the second surface is cooler than the second array area on the second surface during operation; and
the memory module further comprises a third semiconductor die attached to the substrate in the first array area on the second surface, wherein:
the third semiconductor die has a third degree of susceptibility to temperature, wherein the third degree of susceptibility to temperature is based on a change in the operating parameter at different temperatures, and wherein the third degree is greater than the second degree such that the third semiconductor die operates less effectively than the second semiconductor die at the temperature of the second array area during operation, and
the third semiconductor die is mounted in the first array area on the second surface of the substrate in a distal-most position relative to the central portion.