Patent ID: 11934675
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. A storage device, comprising:
a controller configured to direct the storage device to:
utilize a mixed mode programming method to store data within a plurality of data blocks within the storage device;
detect one or more errors during data transfer; and
wherein the storage device is directed to operate a plurality of data blocks in a plurality of mixed modes, wherein each mixed mode is associated with a different level of performance;
wherein the plurality of mixed modes includes a single-level cell (SLC) mode and one of: a double-level cell (MLC) mode, a triple-level cell (TLC) mode, or a quad-level cell (QLC) mode;
wherein the SLC mode is used for storing intermediate data;
wherein each block has a first counter to track SLC mode program/erase cycles and a second counter to track multiple bit per cell mode program/erase cycles; and
wherein values of the first and second counters remain balanced until a maximum threshold number of program/erase cycles of the SLC mode is reached; and
wherein after the maximum threshold number of program/erase cycles of the SLC mode is reached, the block is retired from use in SLC mode and only operates in multiple bit per cell mode thereafter.