Patent ID: 11861223
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory controller, comprising:
a command storage including a first read command queue and a second read command queue, the first read command queue configured to store read commands and physical addresses corresponding to the read commands based on index number, wherein the read commands instruct a memory device to read data stored in a memory device including a plurality of memory blocks, and wherein each of the physical addresses correspond to a plane number, a block number, and a page number;
a command generation controller coupled to the command storage and configured to generate a first read command in response to a read request, translate a logical address to a first physical address, and store the first read command and the first physical address in the first read command queue; and
a command schedule controller coupled to the command storage and configured to search for a first physical address group in response to a scheduling event signal from the command generation controller, the first physical address group including at least one second physical address including a page number that corresponds to a physical address stored in the first read command queue and the first physical address,
wherein the command schedule controller is configured to sequentially schedule a second physical address group and the first physical address group in consecutive index numbers of the second read command queue, the second physical address group including at least one physical address with a plane number different from the plane number of the first physical address group stored in the first read command queue.