Patent ID: 11875057
Assignee: NVIDIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 18:
19. A system, comprising:
a processor comprising a first set of logic circuits and a second set of logic circuits; and
a memory included in the processor;
wherein the processor:
receives, via the first set of logic circuits, a first set of one or more signals;
generates, via the first set of logic circuits, a first input based on the first set of one or more signals;
determines, via the first set of logic circuits, based on the first input and a current state, that a first state transition condition is satisfied, wherein the first state transition condition is stored in a first data entry in the memory;
in response to determining that the first state transition condition is satisfied, transmits, via the first set of logic circuits, a trigger signal to the second set of logic circuits; and
in response to the trigger signal, causes a second set of one or more signals to be stored in the memory via the second set of logic circuits, wherein to cause the second set of one or more signals to be stored in the memory, the processor causes the first data entry in the memory to be overwritten with a second data entry that includes the second set of one or more signals.