Patent ID: 11900873
Assignee: HEFEI BOE JOINT TECHNOLOGY CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. The display device according to claim 18, wherein
the first reset circuit comprises a fifth transistor, wherein a first terminal of the fifth transistor is the first terminal of the first reset circuit, a second terminal of the fifth transistor is the second terminal of the first reset circuit, and a control terminal of the fifth transistor is a control terminal of the first reset circuit;
the first compensation circuit comprises a sixth transistor, wherein a first terminal of the sixth transistor is the first terminal of the first compensation circuit, a second terminal of the sixth transistor is the second terminal of the first compensation circuit, and a control terminal of the sixth transistor is a control terminal of the first compensation circuit;
the first data writing circuit comprises a seventh transistor, wherein a first terminal of the seventh transistor is the first terminal of the first data writing circuit, a second terminal of the seventh transistor is the second terminal of the first data writing circuit, and a control terminal of the seventh transistor is a control terminal of the first data writing circuit;
the first drive circuit comprises an eighth transistor, wherein a first terminal of the eighth transistor is the first terminal of the first drive circuit, a second terminal of the eighth transistor is a second terminal of the first drive circuit, and a control terminal of the eighth transistor is the control terminal of the first drive circuit;
the first storage circuit comprises a first capacitor, wherein a first terminal of the first capacitor is the first terminal of the first storage circuit, and a second terminal of the first capacitor is the second terminal of the first storage circuit;
the second reset circuit comprises a ninth transistor, wherein a first terminal of the ninth transistor is the first terminal of the second reset circuit, a second terminal of the ninth transistor is the second terminal of the second reset circuit, and a control terminal of the ninth transistor is a control terminal of the second reset circuit;
the second compensation circuit comprises a tenth transistor, wherein a first terminal of the tenth transistor is the first terminal of the second compensation circuit, a second terminal of the tenth transistor is the second terminal of the second compensation circuit, and a control terminal of the tenth transistor is a control terminal of the second compensation circuit;
the second data writing circuit comprises an eleventh transistor, wherein a first terminal of the eleventh transistor is the first terminal of the second data writing circuit, a second terminal of the eleventh transistor is the second terminal of the second data writing circuit, and a control terminal of the eleventh transistor is a control terminal of the second data writing circuit;
the second drive circuit comprises a twelfth transistor, wherein a first terminal of the twelfth transistor is the first terminal of the second drive circuit, a second terminal of the twelfth transistor is a second terminal of the second drive circuit, and a control terminal of the twelfth transistor is the control terminal of the second drive circuit; and
the second storage circuit comprises a second capacitor, wherein a first terminal of the second capacitor is the first terminal of the second storage circuit, and a second terminal of the second capacitor is the second terminal of the second storage circuit.