Patent ID: 11941246
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A memory system comprising:
a memory device configured to store data; and
a controller configured to:
provide a host with a memory map segment, which includes a plurality of map pieces, each of the plurality of map pieces including a mapping relationship between a logical address and a physical address, as a host map segment,
store, in a map cache, one or more changed map pieces among the plurality of map pieces,
cause the host to update the host map segment by inserting the changed map pieces in a response to a first command of the host and providing the host with the response, the host map segment being updated on the basis of the changed map pieces provided through the response, and
access, when a read command from the host includes a logical address and a physical address, a memory device by selectively using a physical address included in the read command according to whether the logical address included in the read command is stored in the map cache,
wherein the controller is further configured to:
store identification of a slot that is included in the host and queues the first command, and
detect completion of the updating of the host map segment by receiving a doorbell signal indicating the slot, and
wherein the doorbell signal is provided from the host when the first command is removed from the slot after the updating of the host map segment and a second command is queued in the slot.