Patent ID: 11876052
Assignee: SK HYNIX INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A semiconductor die bonding structure, comprising:
a lower die including a lower top bonding dielectric layer and a lower connection structure; and
an upper die stacked over the lower die and including an upper bottom bonding dielectric layer and an upper connection structure,
wherein the lower connection structure comprises:
a lower through-via structure including a lower through-via plug, a lower through-via barrier layer surrounding a side surface of the lower through-via plug, and a lower through-via liner layer surrounding a side surface of the lower through-via barrier layer, wherein the lower through-via structure penetrates the lower substrate in a vertical direction; and
a lower top bonding pad structure including a lower top bonding pad base, a lower top bonding pad barrier layer over the lower top bonding pad base, and a lower top bonding pad body over the lower top bonding pad barrier layer,
wherein:
the lower top bonding dielectric layer and the upper bottom bonding dielectric layer are directly bonded to each other,
the lower top bonding pad structure and the upper connection structure are bonded to each other,
an upper surface of the lower connection structure has a first width in a first horizontal direction and a second width in a second horizontal direction,
a lower surface of the upper connection structure has a third width in the first horizontal direction and a fourth width in the second horizontal direction,
the first horizontal direction, the second horizontal direction, and the vertical direction being substantially perpendicular to one another, and
the second width is at least twice as large as the first width and the fourth width.