Patent ID: 11869775
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor package comprising:
a package substrate;
an interposer substrate on the package substrate;
a wafer level package on the interposer substrate; and
a memory stack structure on the interposer substrate and mounted side by side with the wafer level package,
wherein the wafer level package comprises a semiconductor chip and an external connection member between the semiconductor chip and the interposer substrate,
wherein the semiconductor chip includes a substrate, a front-end-of-line structure on the substrate, and a back-end-of-line structure on the front-end-of-line structure,
wherein the back-end-of-line structure includes:
a plurality of metal layers stacked on the front-end-of-line structure, an uppermost metal layer of the metal layers including a pad therein;
a redistribution line on the pad, the redistribution line being configured to electrically connect the pad and the external connection member; and
a first dielectric layer between the uppermost metal layer and the redistribution line,

wherein the first dielectric layer includes a first region and a second region beside the first region, the first region vertically overlapping the redistribution line,
wherein the redistribution line includes a first sidewall at an end thereof,
wherein the second region includes a first recess in an upper portion thereof, an inner wall of the first recess including a second sidewall connected to the first sidewall, and
wherein a slope of the first sidewall is different from a slope of the second sidewall.