Patent ID: 11862723
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 3:
4. The manufacturing method of claim 2, wherein the step of forming the active pillar of the vertical storage transistor and the gate dielectric layer surrounding the active pillar in the through hole comprises the steps of:
forming an annular gate dielectric layer on a sidewall of the through hole; and
forming the active pillar in the through hole with a first doped region being formed in a lower end portion of the active pillar and connected to the bit line, a second doped region being formed on an upper end portion of the active pillar and being configured to connect a storage element, and a third doped region being formed between the lower end portion and the upper end portion of the active pillar,
wherein the first doped region, the second doped region and the third doped region are respectively constructed to a drain region, a source region and a channel region of the vertical storage transistor.