Patent ID: 11869852
Assignee: ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITY
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 6:
7. A method of generating a secure key comprising:
(a) providing an array comprising
a plurality of copper lines; and
a plurality of lines comprising W, Ni, Pt, TiN, TaN, TiW, or polycrystalline silicon, the plurality of lines positioned perpendicular to the plurality of copper lines;
wherein a plurality of PUF devices is formed at a plurality of intersections of the plurality of copper lines and the plurality of lines,
wherein each of the plurality of PUF devices comprise
a first copper electrode,
a second electrode, and
a layer of silicon oxide positioned directly between the first copper electrode and the second electrode,

(b) subsequently placing each of the plurality of PUF devices into an off state;
(c) subsequently applying a positive voltage to one of the plurality of copper lines and a negative voltage or a ground voltage to one of the plurality of lines, with all other lines floating;
(d) subsequently measuring a parameter of the PUF device at the intersection of the lines in step (c); and
(e) repeating the sequence defined by steps (b) through (d) for a different pair of intersecting lines in step (c).