Patent ID: 11928176
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A computer-based method for multiplying matrices, comprising:
generating a bitmap based on a first matrix having a plurality of elements; and
compressing the first matrix into a compressed first matrix having fewer elements than the first matrix;
a matrix multiply accelerator (MMA) having an array of processing engines (PEs) each having a single multiplier circuit multiplying, based on the bitmap, the compressed first matrix and a second matrix to generate an output matrix over a number of calculation cycles based upon a sparsity ratio of the first matrix before compression, from which the compressed first matrix is derived, the bitmap including a plurality of bit positions, each bit position corresponding to a different element of the first matrix, said multiplying including:
for each element i,j of the output matrix, calculating a dot product of an ith row of the compressed first matrix and a jth column of the second matrix based on the bitmap; or

a matrix multiply accelerator (MMA) multiplying, based on the bitmap, the second matrix and the compressed first matrix to generate the output matrix over a number of calculation cycles based upon the sparsity ratio of the uncompressed first matrix from which the compressed first matrix is derived, said multiplying including:
for each element i,j of the output matrix, calculating a dot product of an ith row of the second matrix and a jth column of the compressed first matrix based on the bitmap, where said calculating the dot product is performed by a matrix multiply accelerator that includes a scalar register, a first vector register, a second vector register, an output vector register and an array of processing engines (PEs), and the computer-based method further comprises:

storing the bitmap in the scalar register;
storing the compressed first matrix in the first vector register;
storing the second matrix in the second vector register;
storing the output matrix in the output vector register; and
calculating, by each PE of the array of PEs, the dot product for a different element of the output matrix.