Patent ID: 11942478
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 4:
5. A method, comprising:
forming first, second and third fins;
depositing a first dielectric layer between the first and second fins and between the second and third fins;
depositing a second dielectric layer on the first dielectric layer between the first and second fins and between the second and third fins;
removing portions of the first and second dielectric layers between the first and second fins;
depositing a third dielectric layer between the first and second fins;
deposing a fourth dielectric layer on the third dielectric layer between the first and second fins;
forming a sacrificial gate stack on a first portion of each of the first fin, the second fin, the third fin, the first dielectric layer, the second dielectric layer, the third dielectric layer, and the fourth dielectric layer, wherein a second portion of each of the first fin, the second fin, the third fin, the first dielectric layer, the second dielectric layer, the third dielectric layer, and the fourth dielectric layer are exposed;
removing the exposed second portions of the first dielectric layer and the third dielectric layer, wherein a bottom surface of the second portion of the second dielectric layer and a bottom surface of the second portion of the fourth dielectric layer are exposed; and
forming a first dielectric spacer under the second portions of the second and fourth dielectric layers, wherein sidewalls of the second portions of the second and fourth dielectric layers are exposed, and the first dielectric spacer is in contact with the bottom surfaces of the second portions of the second and fourth dielectric layers.