Patent ID: 11910620
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 0:
1. A method for fabricating a semiconductor structure, comprising:
forming a bottom electrode;
forming a magnetic tunneling junction (MTJ) layer over the bottom electrode, wherein the MTJ layer comprises a first material;
forming a top electrode over the MTJ layer;
forming a first dielectric layer over the top electrode and the MTJ layer; and
patterning the MTJ layer to form an MTJ, thereby generating residue over an outer sidewall of the first dielectric layer, wherein the residue comprises the first material, and the residue is apart from the bottom electrode;
forming a second dielectric layer over the first dielectric layer to encapsulate the residue; and
forming an insulation layer surrounding the second dielectric layer.