Patent ID: 11917811
Assignee: WINBOND ELECTRONICS CORP.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 12:
13. The memory as claimed in claim 12, wherein forming the second insulating structure and forming the first connecting pad comprise:
forming a first material layer with non-uniform thickness on the bit line structure and the capacitor contact structure, wherein the first material layer comprises a first insulating material;
performing a first etching process to partially remove the first material layer and expose a top surface of the capacitor contact structure;
depositing a conductive material on the first material layer and the capacitor contact structure;
performing a planarization process so that a top surface of the first material layer is coplanar with a top surface of the conductive material, wherein after the planarization process the conductive material forms the first connecting pad;
performing a second etching process to remove a portion of the first material layer and form a recess adjacent to the first connecting pad; and
forming a second insulating material in the recess, wherein the second insulating material is different from the first insulating material,
wherein the top surface of the second insulating structure is level with the top surface of the first connecting pad.