Patent ID: 11906332
Assignee: STMICROELECTRONICS (ROUSSET) SAS
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 21:
22. A system, comprising:
an integrated circuit, including:
a first substrate; and

a first MOS transistor having a first polysilicon region electrically isolated from the first substrate and including a gate region, a second polysilicon region electrically isolated from the first polysilicon region and from the first substrate, said second polysilicon region including a source region, a substrate region and a drain region of said first MOS transistor, wherein the first polysilicon region is located between an area of the first substrate and the second polysilicon region;
wherein the integrated circuit further comprises:
a dielectric layer disposed between the first polysilicon region and the first substrate; and
a second MOS transistor including, in the first substrate, a source region, a drain region and a substrate region between the source and drain regions and covered by said dielectric layer, the first polysilicon region including a gate region common to the first MOS transistor and to the second MOS transistor.