Patent ID: 11902927
Assignee: SK TELECOM CO., LTD.
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 4:
5. The apparatus of claim 4, wherein the delay processor further includes:
a frequency divider, when the delay buffer delays an inputted test signal and outputs the delayed signal in the initialization mode, lowering a frequency of the signal outputted by the delay buffer by an integer multiple and outputting the frequency-lowered signal; and
a phase frequency detector measuring a frequency and period of the system clock and a frequency and period of the output signal of the frequency divider,
wherein the control code generator generates the initialization control code allowing the frequency and period of the output signal of the frequency divider to coincide with the frequency and period of the system clock, and
wherein the control code processor inputs the generated initialization control code to the delay buffer.