Patent ID: 11915982
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. A method of forming an integrated circuit device, the method comprising:
forming a preliminary vertical field-effect transistor (VFET) on a substrate, wherein the preliminary VFET comprises a bottom source/drain region in the substrate, a channel region and a mask layer that are sequentially stacked on the substrate in a vertical direction, and a preliminary gate structure on a side surface of the channel region;
sequentially forming a preliminary gate liner, a preliminary sacrificial layer, and a preliminary transistor isolation layer on the preliminary VFET;
performing a planarization process until the mask layer is exposed, thereby forming a gate liner, a sacrificial layer, and a transistor isolation layer, wherein the sacrificial layer comprises a horizontal portion extending parallel to an upper surface of the substrate, and a vertical portion protruding from the horizontal portion and extending on a side surface of the preliminary VFET;
forming a recess on the vertical portion of the sacrificial layer by removing a portion of the vertical portion of the sacrificial layer;
forming a gap capping layer in the recess;
forming a top sourceldrain opening on the channel region by removing the mask layer and a portion of the preliminary gate structure of the preliminary VFET;
forming a top source/drain region in the top source/drain opening;
forming a top capping layer on the top source/drain region;
forming an opening extending through the top capping layer and the transistor isolation layer and exposing the horizontal portion of the sacrificial layer;
forming a cavity by removing the sacrificial layer through the opening; and then forming an isolation plug in the opening,
wherein the method further comprises:
before forming the cavity, forming a contact isolation layer on the top capping layer;
forming a top source/drain contact in the contact isolation laver, wherein the top source/drain contact contacts the top source/drain region; and
after forming the top source/drain contact, forming the opening that extends through the contact isolation layer the top capping layer, and the transistor isolation layer.