Patent ID: 11915752
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. A memory write method, comprising:
providing a first RRAM cell array for storing bits;
providing a second RRAM cell array for storing redundancy bits for the first RRAM cell array;
coupling one or more write drivers to the first RRAM cell array and the second RRAM cell array for performing two-cells per one-bit redundancy;
performing a first set operation on a memory cell of one of the first RRAM cell array and the second RRAM cell array;
determining whether a current threshold of the memory cell is exceeded during the first set operation; and
in response to determining the current threshold of the memory cell is exceeded during the first set operation, disabling a second set operation at another of the first RRAM cell array and the second RRAM cell array.