Patent ID: 11888052
Assignee: SUZHOU INSTITUTE OF NANO-TECH AND NANO-BIONICS (SINANO) , CHINESE ACADEMY OF SCIENCES
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 3:
4. A manufacturing method of a semiconductor device, comprising:
manufacturing and forming a semiconductor material layer comprising a heterojunction, wherein a two-dimensional electron gas is formed in the heterojunction, and the heterojunction comprises a first semiconductor layer and a second semiconductor layer, wherein the manufacturing and forming comprises growing a third semiconductor layer and a fourth semiconductor layer on the first semiconductor layer in sequence so as to form the second semiconductor layer, and setting an etching transition layer between the third semiconductor layer and the fourth semiconductor layer;
etching a part of the fourth semiconductor material layer located in a selected region corresponding to the gate until the etching is stopped after reaching or entering the etching transition layer, then subjecting a part of the etching transition layer located in the region corresponding to the gate to thermal decomposition through thermal treatment so that the part of the etching transition layer located in the region corresponding to the gate is completely removed, and realizing termination of the thermal decomposition on the third semiconductor layer, thereby forming a trench structure matched with the gate in the second semiconductor layer;
after the trench structure matched with the gate is formed, directly conducting secondary epitaxial growth on the semiconductor material layer to form a fifth semiconductor layer such that the fifth semiconductor layer is grown in the trench structure matched with the gate;
filling partially the fifth semiconductor layer into the trench structure matched with the gate;
removing the rest parts of the fifth semiconductor layer, and retaining the partial fifth semiconductor layer located in the region matched with the gate;
cladding a continuous passivation layer on the semiconductor material layer;
providing windows for allowing a source, a drain and the gate to pass on the passivation layer;
etching the semiconductor material layer from the windows until the etching is stopped after reaching or entering the etching transition layer, and then subjecting parts of the etching transition layer located in selected regions corresponding to the source and the drain to thermal decomposition through thermal treatment so that the parts of the etching transition layer located in the regions corresponding to the source and the drain are completely removed, and realizing termination of the thermal decomposition on the third semiconductor layer, thereby forming trench structures matched with the source and the drain in the second semiconductor layer; and
manufacturing the source, the drain and the gate, wherein the source, the drain, and the gate are matched with the semiconductor material layer, wherein the gate is manufactured such that the fifth semiconductor layer is spaced between the gate and the third semiconductor layer, and wherein the fifth semiconductor layer is capable of exhausting the two-dimensional electron gas inside the heterojunction located in a region under the gate.