Patent ID: 11900994
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 15:
16. The SRAM chip of claim 11, wherein:
each first edge cell of the plurality of first edge cells comprises a pair of PMOS transistors whose gates are coupled to each other and coupled to a word line of the first edge cell;
sources of the pair of PMOS transistors are coupled to a positive power supply voltage of the first edge cell;
drains of the pair of PMOS transistors are coupled to a power header supply voltage of the first edge cell;
each second edge cell of the plurality of second edge cells comprises a pair of NMOS transistors whose gates are coupled to each other and coupled to a word line of the second edge cell;
sources of the pair of NMOS transistors are coupled to a power footer supply voltage of the second edge cell; and
drains of the pair of NMOS transistors are coupled to a negative power supply voltage of the second edge cell.