Patent ID: 11868872
Assignee: AMAZON TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. The apparatus of claim 15, wherein the hardware processor is configured to, based on executing a first set of instructions associated with the first computation operation:
control the DMA engine to fetch the second DMA descriptor from the second DMA descriptor queue, and to execute the second DMA descriptor to fetch the first address mapping; and
program the address translation table based on the first address mapping;
wherein the hardware processor is configured to, after the first computation operation completes and based on executing a second set of instructions associated with the second computation operation:
control the DMA engine to fetch the third DMA descriptor from the second DMA descriptor queue, and to execute the third DMA descriptor to fetch the second address mapping; and
program the address translation table based on the second address mapping.