Patent ID: 11889441
Assignee: CISCO TECHNOLOGY, INC.
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 5:
6. A system comprising:
a memory storage; and
a processing unit coupled to the memory storage, wherein the processing unit is operative to:
perform a reverse time synchronization procedure between a sending device and a target receiving device;
determine a Time Error (TE) between the sending device and the target receiving device based on the reverse time synchronization procedure wherein the processing unit being operative to determine the TE based on the reverse time synchronization comprises the processing unit being operative to perform other reverse time synchronizations between the sending device and other non-target receiving devices in addition to the reverse time synchronization and determine the TE based on the other reverse time synchronizations and the reverse time synchronization; and
schedule a gate time on the target receiving device based on the determined TE.