Patent ID: 11961914
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of manufacturing an integrated circuit device, the method comprising:
alternately forming a plurality of channel semiconductor layers and a plurality of sacrificial layers on a substrate to form a sacrificial layer pattern that extends in a first direction parallel to an upper surface of the substrate;
forming a dummy gate structure that extends in a second direction that is perpendicular to the first direction on the sacrificial layer pattern;
forming a spacer structure on a sidewall of the dummy gate structure;
forming a recess by removing a portion of the sacrificial layer pattern adjacent to an outer sidewall of the spacer structure, wherein each of the plurality of channel semiconductor layers has a dumbbell shaped horizontal cross-sectional surface after forming the recess;
forming a source/drain region in the recess; and
replacing the plurality of sacrificial layers with a gate electrode, the gate electrode comprising a main gate portion that extends on an uppermost channel semiconductor layer in the second direction and a sub-gate portion that is between adjacent ones of the plurality of channel semiconductor layers,
wherein the sub-gate portion comprises:
a sub-gate center portion; and
sub-gate edge portions that comprise opposing end portions of the sub-gate portion, respectively, in the second direction,

wherein the source/drain region comprises a protrusion portion protruding toward a respective one of the sub-gate edge portions, and
wherein forming the spacer structure comprises:
sequentially forming a first spacer layer and a second spacer layer on an upper surface of the dummy gate structure and on the sidewall of the dummy gate structure;
forming a cover spacer layer on the second spacer layer; and
forming the spacer structure comprising a first spacer and a second spacer by performing an anisotropic etching process on the first spacer layer, the second spacer layer, and the cover spacer layer.