Patent ID: 11907149
Assignee: QUALCOMM INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 18:
19. A computing system comprising:
a communication bus including a two-wire bus and a high-speed bus operative at a high speed greater than a low speed associated with the two-wire bus;
a first integrated circuit (IC), comprising:
a first two-wire interface coupled to the two-wire bus;
a high-speed interface coupled to the high-speed bus; and
a first control circuit coupled to the first two-wire interface and configured to:
using an initial protocol_transmitting messages, negotiate a transition to a second protocol for communications with a secondary IC over the first two-wire interface;
transition to using the second protocol;
operate using the second protocol; and
subsequently change back to using the initial protocol; and

the secondary IC comprising:
a secondary two-wire interface coupled to the two-wire bus; and
a secondary control circuit coupled to the secondary two-wire interface and configured to:
responsive to negotiations from the first control circuit, transition to using the second protocol; and
operate using the second protocol.