Patent ID: 11954040
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. A method comprising:
fabricating only one or more processing cores and cache control logic in a first tier without cache memory being physically disposed in the first tier;
fabricating only a first system-level cache in a second tier without the cache control logic being physically disposed in the second tier, wherein the first system-level cache is coupled to the one or more processing cores via the cache control logic to operate as a computing architecture, and wherein the second tier is separate from the first tier; and
fabricating one or more additional system-level caches in one or more additional tiers, wherein the one or more additional system-level caches are coupled to the first system-level cache in the second tier, and the one or more additional system-level caches in the one or more additional tiers are coupled to the one or more processing cores via the cache control logic that is disposed in the first tier,
wherein the first tier, the second tier, and the one or more additional system-level caches are integrated together with the computing architecture to operate as a stackable cache memory architecture.