Patent ID: 11881267
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 15:
16. A semiconductor memory device comprising:
a memory string that extends in a first direction and includes a select transistor, a dummy cell, and a plurality of memory cells;
a select gate electrode connected to the select transistor;
a dummy gate electrode connected to the dummy cell;
a plurality of gate electrodes connected to the plurality of memory cells;
a conductive layer connected to one end portion of the memory string; and
a control circuit connected to the select gate electrode, the plurality of gate electrodes, the dummy gate electrode, and the conductive layer, the control circuit configured to execute an erase operation of the plurality of memory cells, wherein
the erase operation includes:
a first operation that applies a first voltage to the plurality of gate electrodes and applies a second voltage larger than the first voltage to the dummy gate electrode;
a second operation performed after the first operation, the second operation applying a third voltage larger than the first voltage to the plurality of gate electrodes and applying a fourth voltage larger than the third voltage to the dummy gate electrode; and
a third operation performed after the second operation, the third operation applying a fifth voltage smaller than the second voltage to the plurality of first gate electrodes and applying a sixth voltage larger than the fifth voltage and smaller than the second voltage to the dummy gate electrode.