Patent ID: 11907627
Assignee: BATTELLE MEMORIAL INSTITUTE
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An integrated circuit (IC) assessment device for assessing an IC-under-test, the IC assessment device comprising:
an electronic processor; and
a non-transitory storage medium storing:
a library of as-fabricated standard cell layout renderings constructed using at least one reference layout image acquired of a reference IC;
instructions readable and executable by the electronic processor to perform an IC assessment method including identifying instantiated standard cells and their placements in the layout image of the IC-under-test by matching the instantiated standard cells with corresponding as-fabricated standard cell layout renderings retrieved from the library of as-fabricated standard cell layout renderings; and
instructions readable and executable by the electronic processor to perform a method of constructing the library of as-fabricated standard cell layout renderings, the method including:
training an artificial intelligence (AI) component comprising at least one artificial neural network (ANN) to transform layout rendering tiles of a layout rendering of a reference IC into corresponding reference layout image tiles extracted from at least one layout image of the reference IC; and
using the trained AI component, transforming standard cell layout renderings of a library of standard cell layout renderings into the as-fabricated standard cell layout renderings forming the library of as-fabricated standard cell layout renderings.