Patent ID: 11907725
Assignee: GRAPHCORE LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 15:
16. A computer implemented method of generating multiple programs, each of which is suitable for execution by a processor of one of a plurality of chips, the method comprising:
compiling a single set of executable instructions;
determining a first index value for a first one of the chips and a second index value for a second one of the chips; and
generating, for the first one of the chips, a first local program comprising the single set of executable instructions and the first index value, and generating, for the second one of the chips, a second local program comprising the single set of executable instructions and the second index value,
wherein the single set of executable instructions, when allocated to the first one of the chips is scheduled to execute on a first processor of the first one of the chips to cause:
in dependence upon the first index value, selecting a further one of the chips as a destination and providing an address of the further one of the chips in a data packet; and
dispatching the data packet via routing hardware to the further one of the chips.