Patent ID: 11950423
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 6:
7. The semiconductor device of claim 1, wherein:
the peripheral circuit area comprises a low-voltage transistor area including the plurality of planar channel transistors, and a high-voltage transistor area laterally adjacent the low-voltage transistor area and including the at least one recess channel transistor, the at least one recess channel transistor having an operation voltage greater than respective operation voltages of the plurality of planar channel transistors; and
the first and second recess channel transistors are in the high-voltage transistor area, the first recess channel transistor having a first operation voltage and comprising the first source/drain region including a first impurity region and a second impurity region, the first impurity region extending to the first depth and having a first dopant concentration and the second impurity region having a second dopant concentration greater than the first dopant concentration, the second recess channel transistor having a second operation voltage greater than the first operation voltage and comprising the second source/drain region including a third impurity region and a fourth impurity region, the third impurity region extending to the second depth and having a third dopant concentration and the fourth impurity region having a fourth dopant concentration greater than the third dopant concentration.