Patent ID: 11887657
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. The amplifier circuit according to claim 1, further comprising: a preprocessing circuit, coupled to the readout node and the complementary readout node, wherein
at a charging stage, the preprocessing circuit is coupled to at least one of the readout node or the complementary readout node, and configured to precharge the bit line, the complementary bit line, the readout node, and the complementary readout node to a preset voltage based on a precharge signal; and
at an equilibrium stage, the preprocessing circuit is coupled to both the readout node and the complementary readout node, and configured to synchronize a node voltage of the readout node and a node voltage of the complementary readout node based on an equilibrium signal.