Patent ID: 11895221
Assignee: INTEL CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An apparatus implementing an Advanced Encryption Standard (AES) substitutions box (S-box) encryption, comprising:
an S-box logic function, wherein the S-box logic function takes as input a state and is an 8-bit to 8-bit logic function, and wherein the S-box logic function is minimized such that an S-box round comprises nine not-and (NAND) levels and duplications of a logical product of the minimized S-box logic function are eliminated; and
a MixColumns multiplication operation, wherein the MixColumns multiplication operation comprises a plurality of factors that are exclusive ORed (XOR) with an output of the S-box round to obtain a scaled 16-byte output.