Patent ID: 11949414
Assignee: INTEL CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An apparatus to improve in-memory multiply and accumulate operations, the apparatus comprising:
a first multiplexer in a subarray of memory, the first multiplexer including first select terminals, first input terminals, and first output terminals, the first input terminals to receive first values representative of a column of a lookup table (LUT) including entries to represent products of four-bit numbers, the first multiplexer to return second values from an intersection of a row and the column of the LUT based on a first element of a first operand received at the first select terminals;
shift and adder logic in the subarray, the shift and adder logic including second input terminals and second output terminals, the second input terminals in circuit with the first output terminals, the shift and adder logic to shift the second values based on at least one of the first element of the first operand or a first element of a second operand; and
accumulation storage in the subarray, the accumulation storage including third input terminals in circuit with the second output terminals, the accumulation storage to store at least the shifted second values.