Patent ID: 11901031
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. A memory device comprising:
a bank fail test circuit configured to generate a first fail bank flag indicating whether a failure was detected in a first memory bank, on the basis of first internal data outputted from a column line of the first memory bank, and control the first fail bank flag to indicate that a failure was detected in the first memory bank, on the basis of a first fail control signal, when performing a test;
an active row region information output circuit configured to output first bank active row region information as active row region information for repairing the column line, on the basis of the first fail bank flag, the first bank active row region information being generated when an active operation is performed in the first memory bank, and
wherein the bank fall test circuit configured to generate the first fall bank flag when the test is performed basis of a test mode signal generated from a command address.