Patent ID: 11899584
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 7:
8. The method of claim 7, wherein the cache hit ratio for the cache memory is determined based on at least one of: (1) a ratio of a size of data in the cache memory that is accessed during a preset time period to a total size of data in the random access memory or the cache memory that is accessed during the preset time period; (2) a ratio of a number of data accesses to the cache memory during the preset time period to a total number of data accesses to the random access memory or the cache memory during the preset time period, or (3) a ratio of the number of data accesses to the cache memory during the preset time period to a total number of data retrieves from the cache memory during the preset time period.