Patent ID: 11869772
Assignee: STMICROELECTRONICS (CROLLES 2) SAS
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A semiconductor device comprising:
a first polycrystalline silicon gate disposed over a semiconductor body in a first region of the semiconductor body;
a first silicide region disposed proximate the first polycrystalline silicon gate in the first region;
a first sidewall spacer disposed on sidewalls of the first polycrystalline silicon gate, the first sidewall spacer disposed between the first silicide region and the first polycrystalline silicon gate;
a second silicide region disposed on the first polycrystalline silicon gate;
a second polycrystalline silicon gate disposed over the semiconductor body in a second region of the semiconductor body, the second region contacting the first region;
a second sidewall spacer disposed on sidewalls of the second polycrystalline silicon gate; and
an oxide layer disposed over the second polycrystalline silicon gate and the second sidewall spacer, the oxide layer physically contacting a major surface of the second polycrystalline silicon gate, the oxide layer extending to an edge between the first region and the second region; and
a silicon nitride region disposed, at the edge, over a portion of the oxide layer, wherein the silicon nitride region occupies a surface area of less than 50% of a total surface area of the semiconductor body.