Patent ID: 11862621
Assignee: TSMC NANJING COMPANY, LIMITED
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. An integrated circuit (IC) device, comprising:
at least one delay circuit comprising:
an input and an output, and
a plurality of transistors electrically coupled with each other between the input and the output, the plurality of transistors configured to delay an input signal received at the input to generate a delayed signal at the output; and

an output connector electrically coupled to the output,
wherein
the output is in a first metal layer, and
the output connector comprises
a first conductive pattern in the first metal layer, and
a second conductive pattern in a second metal layer different from the first metal layer, the second conductive pattern electrically coupling the output to the first conductive pattern.