Patent ID: 11887660
Assignee: MEDIATEK INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A pseudo dual-port memory, comprising:
a single-port memory;
a multiplexer, configured to receive a first address and a second address, and output one of the first address and the second address to the single-port memory;
a timing control circuit, configured to generate a multiplexer control signal to control the multiplexer to sequentially output the first address and the second address to the single-port memory; and
an output circuit, configured to receive output data from the single-port memory to generate a first reading result corresponding to the first address and a second reading result corresponding to the second address; and the output circuit comprises:
a first sense amplifier, configured to receive the output data from the single-port memory to generate first data to a first latch according to a first control signal, wherein the first data stored in the first latch serves as the first reading result; and
a second sense amplifier, configured to receive the output data from the single-port memory to generate second data to a second latch according to a second control signal, wherein the second data stored in the second latch serves as the second reading result;

wherein the timing control circuit generates the multiplexer control signal to control the multiplexer to sequentially output the first address and the second address to the single-port memory within a clock cycle, and the timing control circuit further generates the first control signal and the second control signal to sequentially enable the first sense amplifier and the second sense amplifier.