Patent ID: 11908934
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 4:
5. A method of fabricating a semiconductor structure, the method comprising:
forming a gate electrode over a single crystalline silicon substrate, the gate electrode defining a channel region in the single crystalline silicon substrate;
forming a gate dielectric between the gate electrode and the channel region, the gate dielectric having a bottom surface;
forming an epitaxial semiconductor source region laterally adjacent a first end of the channel region at a first side of the gate electrode and extending above an uppermost surface of the channel region, the epitaxial semiconductor source region in contact with a first portion of the bottom surface of the gate dielectric, and the epitaxial semiconductor source region comprising a first inflection point at a lowermost horizontal surface of the epitaxial semiconductor source region and a second inflection point above the first inflection point, wherein a single facet is between the first and second inflection points of the epitaxial semiconductor source region, wherein the first inflection point of the epitaxial semiconductor source region is not vertically beneath the gate electrode, and wherein the second inflection point of the epitaxial semiconductor source region is vertically beneath the gate electrode;
forming an epitaxial semiconductor drain region laterally adjacent a second end of the channel region at a second side of the gate electrode opposite the first side of the gate electrode and extending above an uppermost surface of the channel region, the epitaxial semiconductor drain region in contact with a second portion of the bottom surface of the gate dielectric, and the epitaxial semiconductor drain region comprising a first inflection point at a lowermost horizontal surface of the epitaxial semiconductor drain region and a second inflection point above the first inflection point, wherein a single facet is between the first and second inflection points of the epitaxial semiconductor drain region, wherein the first inflection point of the epitaxial semiconductor drain region is not vertically beneath the gate electrode, and wherein the second inflection point of the epitaxial semiconductor drain region is vertically beneath the gate electrode;
forming a first dielectric spacer adjacent the first side of the gate electrode and over a portion of the epitaxial semiconductor source region, wherein the first inflection point of the epitaxial semiconductor source region is not vertically beneath the first dielectric spacer; and
forming a second dielectric spacer adjacent the second side of the gate electrode and over a portion of the epitaxial semiconductor drain region, wherein the first inflection point of the epitaxial semiconductor drain region is not vertically beneath the second dielectric spacer.