Patent ID: 11875045
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. The semiconductor memory of claim 13, wherein the address processing circuit comprises:
a row address processing circuit, configured to output a row address of the target bank, wherein an output terminal of the row address processing circuit is connected to an input terminal of the region selection signal generation circuit and the target bank;
a column address processing circuit, configured to output a column address of the target bank, wherein an output terminal of the column address processing circuit is connected to the target bank; and
a bank address processing circuit, configured to output a bank address of the target bank, wherein an output terminal of the bank address processing circuit is connected to the target bank;
wherein the region selection signal generation circuit is configured to perform logic processing on the target code and a row address of the storage region to be trimmed corresponding to the target code to obtain a target level, and take the target level as the region selection signal.