Patent ID: 11894326
Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. A method comprising:
providing a substrate having a recess or opening extending from a first surface of the substrate, at least a portion of the first surface of the substrate having a planarized topography;
disposing a first conductive material having a first coefficient of thermal expansion (CTE) within the recess or opening and forming a first portion of an interconnect structure, the first portion of the interconnect structure extending normal to a plane of the substrate;
disposing a second conductive material having a second CTE different from the first CTE within the recess or opening, the second conductive material forming a second portion of the interconnect structure, the second portion of the interconnect structure comprising a plurality of conductive portions extending normal to the plane of the substrate, the first conductive material at least partially surrounding the second conductive material; and
disposing a barrier layer between the substrate and the first conductive material.