Patent ID: 11882038
Assignee: SERIALTEK, LLC
Field: Digital communication (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 6:
7. The apparatus of claim 1, comprising:
a first analog splitter circuit configured to couple onto the one or more first directional lanes of the communication link between the one or more endpoint devices and the host and provide replicas of the one or more first directional lanes to the first circuit;
a second analog splitter circuit configured to couple onto the one or more second directional lanes of the communication link between the one or more endpoint devices and the host and provide replicas of the one or more second directional lanes to the second circuit;
the first circuit comprising a first field programmable gate array (FPGA) coupled to the replicas of the one or more first directional lanes and having a first interface configured to couple to the second circuit over an intermediate link, wherein the intermediate link carries at least the information determined for the first packets; and
the second circuit comprising a second FPGA coupled to the replicas of the one or more second directional lanes and having a second interface configured to couple to the first circuit over the intermediate link.