Patent ID: 11901961
Assignee: SILICON MOTION, INC.
Field: Telecommunications (Electrical engineering)
Classification: CPC H  G  Y | IPC H

Claim 6:
7. A memory controller, coupled to a memory device for controlling access operations of the memory device, comprising:
an interface circuit, coupled to a host device and configured to communicate with the host device, wherein the interface circuit comprises:
a first signal processing device, disposed on a receiving signal processing path and configured to process a received signal;
a second signal processing device, disposed on a transmitting signal processing path and configured to process a transmitting signal; and
a calibration device, coupled to the first signal processing device and the second signal processing device and configured to calibrate a characteristic value of the first signal processing device and a characteristic value of the second signal processing device in a calibration procedure,
wherein the first signal processing device is coupled to an external signal receiving path and an internal signal receiving path and is configured to sequentially process the received signal received from the external signal receiving path and the received signal received from the internal signal receiving path in the calibration procedure, and
wherein the second signal processing device is coupled to the first signal processing device via the internal signal receiving path and is configured to provide the transmitting signal to the first signal processing device in the calibration procedure.