Patent ID: 11915769
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A non-volatile memory device, comprising:
a control circuit configured to connect to a bit line that is connected to one or more non-volatile memory cells, the control circuit comprising:
a first plurality of data latches connected to a first local data bus, the first plurality of data latches configured to store first program-verify pass/fail bits for first non-volatile memory cells connected to the bit line;
a second plurality of data latches connected to a second local data bus, the second plurality of data latches configured to store second program-verify pass/fail bits for second non-volatile memory cells connected to the bit line;
a shared isolation latch; and
one or more interface circuits connected to the first local data bus and the second local data bus, the one or more interface circuits configured to selectively block the first program-verify pass/fail bits from the first plurality of latches and the second program-verify pass/fail bits from the second plurality of latches according to an indicator bit stored in the shared isolation latch.