Patent ID: 11954048
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus comprising:
memory management circuitry to control access to a memory system based on access control information defined in table entries of a table structure comprising a plurality of levels of access control table; and
table accessing circuitry to access the table structure to obtain the access control information corresponding to a target address; in which:
for a given access control table at a given level of the table structure other than a starting level:
the table accessing circuitry is configured to select a selected table entry of the given access control table corresponding to the target address, based on an offset portion of the target address, the selected table entry providing either a pointer to an access control table at a next lowest level of the table structure or the access control information corresponding to the target address; and
the table accessing circuitry is configured to determine a size of the offset portion of the target address based on a variable nesting control parameter specified in a table entry of a higher-level access control table at a higher level of the table structure than the given access control table.