Patent ID: 11875856
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A semiconductor memory device comprising:
a first memory cell;
a second memory cell;
a first word line coupled to the first memory cell;
a second word line coupled to the second memory cell;
a semiconductor layer interposed between the first memory cell and the second memory cell; and
a first bit line capable of being electrically coupled to both the first memory cell and the second memory cell,
wherein the semiconductor memory device is configured to execute a first operation, a second operation, and a third operation, wherein
in the first operation, a first voltage is applied to a word line corresponding to a non-selected memory cell,
in the second operation, after the first operation, a second voltage higher than the first voltage is applied to the word line corresponding to the non-selected memory cell,
in the third operation, after the second operation, a third voltage higher than the second voltage is applied to the word line corresponding to the non-selected memory cell, and a fourth voltage lower than both the third voltage and the second voltage is applied to a word line corresponding to a selected memory cell,

the semiconductor memory device is further configured to:
execute the first operation, the second operation, and the third operation when receiving a write command for the first memory cell; and
execute the third operation when receiving a write command for the second memory cell,
wherein
data writing into the second memory cell is executed after data writing into the first memory cell is executed.