Patent ID: 11935244
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 5:
6. An apparatus for improving sensitivity of wafer detection, comprising:
memory for storing instructions;
a transceiver; and
a processor, wherein the processor is configured to execute the instructions stored in the memory to:
acquire a gray-scale image of a peripheral circuit region of a wafer;
divide the gray-scale image into at least one pixel region;
determine a repeated image region in each of the at least one pixel region, wherein the repeated image region is a region with N*M pixels, where M pixels on a same column in the repeated image region have a same gray-scale value, and N and M are integers greater than 0;
perform Fourier analysis on all repeated image regions in the gray-scale image to determine position information where interference superposition occurs in the peripheral circuit region of the wafer according to all the repeated image regions in the gray-scale image; and
process the interference superposition according to the position information to obtain a wafer defect.