Patent ID: 11957065
Assignee: 1372934 B.C. LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. The method of claim 13 wherein determining a set of dimensions for each of a number of verniers to be formed in the superconducting integrated circuit based at least in part on the determined target resolution of interlayer misalignment to be electrically detectable in the superconducting integrated circuit via a measurement of resistance of portions of the superconducting integrated circuit includes: determining a length, a width and a thickness of a first mark in a first wiring layer, determining a length, a width and a thickness of a second mark in a second wiring layer, determining a length, a width and a thickness of a stud via that electrically couples the first and the second marks, and determining a length and a width a first resistive overlap region defined by an orthogonal projection of the second mark on the stud via, such that the first resistance overlap region has a resistance that is larger than a cumulative resistance of the first mark, the second mark and the stud via at least at temperatures above a critical temperature.