Patent ID: 11955986
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 17:
18. A comparator circuit comprising:
an input circuit configured to generate a positive amplified input signal through a positive sampling node and generate a negative amplified input signal through a negative sampling node by alternately selecting a positive input voltage and a negative input voltage during an equalizing period and a sampling period;
a first positive coupling capacitor connected between the positive sampling node and a first positive node;
a first negative coupling capacitor connected between the negative sampling node and a first negative node, and
a first positive inverter connected between the first positive node and a second positive node;
a first negative inverter connected between the first negative node and a second negative node;
a first positive equalization switch configured to electrically connect the first positive node and the second positive node based on an equalization signal having an activation period corresponding to the equalizing period;
a first negative equalization switch configured to electrically connect the first negative node and the second negative node based on the equalization signal;
a second positive coupling capacitor connected between the second positive node and a third positive node;
a second negative coupling capacitor connected between the second negative node and a third negative node;
a second positive inverter connected between the third positive node and a fourth positive node;
a second negative inverter connected between the third negative node and a fourth negative node;
a second positive equalization switch configured to electrically connect the third positive node and a fourth positive node based on the equalization signal;
a second negative equalization switch configured to electrically connect the third negative node and a fourth negative node based on the equalization signal;
a first latching switch configured to electrically connect the fourth positive node and the third negative node based on a latch signal that is activated during the sampling period;
a second latching switch configured to electrically connect the fourth negative node and the third positive node based on the latch signal;
a positive feedback switch configured to electrically connect the fourth positive node and the first positive node based on the latch signal; and
a negative feedback switch configured to electrically connect the fourth negative node and the first negative node based on the latch signal.