Patent ID: 11901011
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 5:
6. The semiconductor storage device according to claim 1,
wherein
each of the first to fourth memory pillars is sandwiched by the third word line and the fourth word line, and includes a third memory cell and a fourth memory cell, the third memory cell facing to the third word line and sharing the memory pillar with the first memory cell, the fourth memory cell facing to the fourth word line and sharing the memory pillar with the second memory cell,
the control circuit is
configured to perform in order of a first write operation and a second write operation in each of the first memory cell, the second memory cell, the third memory cell, and the fourth memory cell,
configured to perform the first write operation to the third memory cell and the fourth memory cell after performing the first write operation to the first memory cell and the second memory cell, and
configured to perform the second write operation to the first memory cell and the second memory cell after performing the first write operation to the third memory cell and the fourth memory cell.