Patent ID: 11886972
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 8:
9. A method for performing multiply-and-accumulate (MAC) operations for an artificial neural network (ANN) accelerator, comprising:
receiving digital input data at a non-volatile memory (NVM) crossbar module including a plurality of digital-to-analog converters (DACs), an NVM crossbar and a plurality of analog-to-digital converters (ADCs);
converting, by the DACs, the digital input data into a plurality of analog voltage signals;
converting, by the NVM crossbar, the analog voltage signals into a plurality of MAC signals using a plurality of MAC cells, each MAC cell including one or more NVM elements programmed to a conductance level representing one of a plurality of unipolar weights of an ANN;
converting, by the NVM crossbar, the analog voltage signals into a correction signal using a plurality of correction cells, each correction cell including one or more NVM elements programmed to a predetermined conductance level; and
correcting each MAC signal based on the correction signal.