Patent ID: 11953963
Assignee: ZETAGIG INC.
Field: Control (Instruments)
Classification: CPC G | IPC G

Claim 0:
1. An array of devices, comprising:
each device within the array of devices being specified by a location (i,j) within the array of devices, wherein i is a row index ranging from 1 to N, and j is a column index ranging from 1 to M, wherein M is a positive integer greater than or equal to 2 and N is a positive integer;
each device including a Vdd terminal and a Vss terminal, wherein the Vdd terminal has a higher potential than the Vss terminal;
at least a first plurality of the devices in the array of devices, where each device in the first plurality of the devices further including at least one input terminal and at least one output terminal and Zmax number of V_Terz terminals, where z is an index ranging from 1 to Zmax, where Zmax is a positive integer;
wherein when N is greater than or equal to 2, then for at least a first majority of the devices in the array of devices, the Vss terminal of the device at location (i,j), for i=2:N, j=1:M, is connected to the Vdd terminal of the device at location (i−1,j), resulting in a potential difference between the Vdd terminal and the Vss terminal of at least the first majority of the devices in the array of devices to be a substantially same voltage VDD;
wherein for at least a second majority of the devices in the array of devices, the potential of the Vss terminal of each device at any location (i,j+1) of the array of devices is generated to be higher than the potential of the Vss terminal for another device at location (i,j) by a voltage Xj, for i=1:N, j=1:(M−1), wherein at least one of a V_Terz terminal of a first device in the first plurality of the devices is connected to one of a Vss terminal or a Vdd terminal of a second device in the first plurality of the devices, and at least one of a V_Terz terminal of the second device is connected to a Vss terminal or a Vdd terminal of at least one of the first device or a different device in the array of devices; and
wherein VDD is substantially same as a potential difference between the Vdd terminal and the Vss terminal of the first device, and a sum of all Xj voltages for j=1: (M−1) is greater than or substantially same as VDD/2.