Patent ID: 11942556
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 13:
14. A method comprising:
forming a fin structure over a substrate, wherein the fin structure comprises a first sacrificial layer, a first channel layer, a second sacrificial layer, and a second channel layer sequentially over the substrate;
forming a dummy gate structure over the fin structure to define a channel portion in the fin structure and under the dummy gate structure and two source/drain portions in the fin structure and on opposite sides of the channel portion;
forming gate spacers respectively on opposite sides of the dummy gate structure;
removing the source/drain portions of the fin structure;
epitaxially growing source/drain epitaxial structures on opposite sides of the channel portion of the fin structure;
removing the dummy gate structure, the first sacrificial layer, and the second sacrificial layer to form a gate trench surrounded by the gate spacers;
after removing the dummy gate structure, the first sacrificial layer, and the second sacrificial layer, forming a first recess in the first channel layer and in the gate trench, wherein after forming the first recess, the first recess exposes an inner surface of the first channel layer;
forming a gate structure in the gate trench and the first recess; and
forming a second recess in the second channel layer and in the gate trench, wherein after forming the second recess, the second recess exposes an inner surface of the second channel layer, and the second recess is deeper than the first recess.