Patent ID: 11887675
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 18:
19. A memory device comprising:
a floating gate memory array comprising a plurality of memory cells configured to store respective data values;
an address decoder configured to direct access to a memory cell of the plurality of memory cells for a read operation or a verify operation in response to address information corresponding to the memory cell;
regulating circuitry configured to provide a time varying wordline signal to a wordline of the memory cell during a discharge period of the read operation of the memory cell or the discharge period of the verify operation of the memory cell, wherein the time varying wordline signal comprises a plurality of pulses, wherein each pulse of the plurality of pulses changes a voltage of the time varying wordline signal from a first voltage state to a second voltage state and returns the voltage to the first voltage state; and
sense circuitry configured to integrate a current response of a bitline of the memory cell during the discharge period and determine a data value of the memory cell based on integration of the current response.