Patent ID: 11868740
Assignee: POSTECH RESEARCH AND BUSINESS DEVELOPMENT FOUNDATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 3:
4. The circuit of claim 3, further comprising:
a ninth BFA configured to receive a sum output signal of the third full adder, an inverting signal for a sum output signal of the seventh BFA, and a drain voltage;
a tenth BFA configured to receive a sum output signal of the second half adder, an inverting signal for a sum output signal of the fifth BHA, and a carry output signal of the ninth BFA;
an eleventh BFA configured to receive a sum output signal of the third half adder, an inverting signal for a sum output signal of the sixth BHA, and a carry output signal of the tenth BFA; and
a twelfth BFA configured to receive a carry output signal of the third half adder, an inverting signal for a carry output signal of the sixth BHA, and a carry output signal of the eleventh BFA.