Patent ID: 11936893
Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
Field: Audio-visual technology (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An encoder comprising:
memory; and
circuitry coupled to the memory and configured to:
encode a slice into one or more data access regions in a variable length encoding process; and
encode one or more offsets into a slice header, based on a flag written into a sequence header and a total number of the one or more data access regions, the one or more offsets each specifying a head position of a corresponding one of the one or more data access regions in a bitstream, wherein

when the flag indicates that the one or more offsets are to be encoded and the total number is at least two, the one or more offsets are encoded, and
the flag switches between encoding and not encoding the one or more offsets regardless of whether the total number is at least two.