Patent ID: 11955160
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 16:
17. A circuit comprising:
a delay chain, disposed on a memory chip, comprising at least two delay elements, wherein the delay chain is configured to generate a particular time delay for a reference signal transmitted from a command decoder to the delay chain; and
a status circuit configured to:
receive a first status value from a first delay element of the delay chain disposed on the memory chip, wherein the first status value is associated with a first time delay generated for the reference signal by the first delay element;
receive a second status value from a last delay element of the delay chain disposed on the memory chip, and wherein the second status value is associated with a second time delay generated for the reference signal by the last delay element; and
generate a status signal based on the first status value and the second status value.