Patent ID: 11934834
Assignee: AMPERE COMPUTING LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A processor, comprising:
a means for storing scheduling entries comprising a plurality of scheduling entries, each scheduling entry among the plurality of scheduling entries configured to store first operation source parent information;
a means for receiving the first operation source parent information from the means for storing the scheduling entries; and
a means for performing a dependency comparison with a first source parent of a plurality of source parents based on the first operation source parent information;
wherein:
each of the plurality of source parents is associated with an execution pipeline of a plurality of execution pipelines; and
the means for performing the dependency comparison comprises:
a means for selecting, using the first operation source parent information, an associated execution pipeline from among the plurality of execution pipelines on which to perform the dependency comparison;
a means for selecting, using the first operation source parent information, information from the associated execution pipeline; and
a means for performing the dependency comparison only against the information from the associated execution pipeline.