Patent ID: 11868277
Assignee: RENESAS ELECTRONICS CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A data processing apparatus comprising:
N (N is an integer) number of first registers each of which stores setting information for memory protection;
a second register storing a border information which defines an M-th (M is an integer) register of the first registers; and
a determination circuit which determines whether an access request is permitted based on the first registers and the second register,
wherein each of the (first to (M−1)-th) first registers stores setting information for memory protection set by a virtual machine and each of the (M-th to N-th) first registers stores setting information for memory protection set by a virtual machine monitor, and
wherein the determination circuit determines that an access request from the virtual machine is permitted when both one of the (first to (M−1)-th) first registers and one of the (M-th to N-th) first registers include an address as the setting information for memory protection corresponding to an address destination of the access request from the virtual machine.