Patent ID: 11916570
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 21:
22. A method of manufacturing an integrated circuit, the method comprising:
forming a memory system on or over a semiconductor substrate, the memory system comprising memory; and
forming a controller circuit on or over the semiconductor substrate, the controller circuit comprising one or more logic circuits, the controller circuit being communicatively coupled to the memory system, the controller circuit being configured to:
receive from the memory system a codeword read from the memory, the codeword having a format including first bit positions corresponding to multi-bit data, second bit positions corresponding to a bitwise inversion of the multi-bit data, a third bit position corresponding to a first parity value of the multi-bit data, and a fourth bit position corresponding to a second parity value of the multi-bit data, wherein the first parity value is one of an even parity value or an odd parity value, and the second parity value is the other of the even parity value or the odd parity value;
determine a number of counted bit errors in the codeword, a counted bit error including a bit value of a bit position of the first bit positions and a bit value of a corresponding bit position of the second bit positions having an equal value and including a bit value of the third bit position and a bit value of the fourth bit position having an equal value;
determine a third parity value of bit values of the first bit positions, the third parity value being a same parity type as the first parity value;
determine a fourth parity value of bit values of the second bit positions;
transmit the bit values of the first bit positions as the multi-bit data read from the memory on the condition that (i) the number of counted bit errors is equal to or less than one and (ii) the third parity value is equal to a bit value of the third bit position; and
transmit a bitwise inversion of the bit values of the second bit positions as the multi-bit data read from the memory on the condition that (i) the number of counted bit errors is equal to or less than one, (ii) the third parity value is not equal to the bit value of the third bit position, and (iii) the fourth parity value is equal to a bit value of the fourth bit position.