Patent ID: 11948940
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor device, comprising:
a first transistor comprising:
a first source/drain feature and a second source/drain feature,
a first plurality of channel members sandwiched between the first source/drain feature and the second source/drain feature along a first direction, and
a first gate structure wrapping around each of the first plurality of channel members; and

a second transistor comprising:
a third source/drain feature and a fourth source/drain feature,
a second plurality of channel members sandwiched between the third source/drain feature and the fourth source/drain feature along the first direction, and
a second gate structure wrapping around each of the second plurality of channel members,

wherein a height of the first source/drain feature is greater than a height of the second source/drain feature,
wherein the first source/drain feature and the second source/drain feature comprise a first width along the first direction,
wherein the third source/drain feature and the fourth source/drain feature comprises a second width along the first direction,
wherein the second width is greater than the first width.