Patent ID: 11908704
Assignee: KEPLER COMPUTING INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of fabricating a material layer stack for a memory device, the method comprising:
depositing a first electrode layer above a substrate, wherein the first electrode layer comprises a first conductive nonlinear polar material, the first conductive nonlinear polar material comprising a first grain length;
depositing a dielectric layer comprising a perovskite material on the first electrode layer, the perovskite material comprising a second grain length;
depositing a second electrode layer on the dielectric layer, wherein the second electrode layer comprises a second conductive nonlinear polar material, the second conductive nonlinear polar material comprising a third grain length that is substantially equal to the first grain length; and
annealing the material layer stack for a duration of less than 60 seconds at temperatures below 1300 degrees Celsius, wherein the annealing modifies the first conductive nonlinear polar material to have a first new grain length which is a factor of 3 larger than the first grain length, wherein the annealing modifies the perovskite material to have a second new grain length which is a factor of 3 larger than the second grain length, and wherein the annealing modifies the second conductive nonlinear polar material to have a third new grain length which is a factor of 3 larger than the third grain length.