Patent ID: 11881254
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 16:
17. A semiconductor memory, comprising:
an enable control circuit, comprising:
a counting circuit, configured to: count past clock cycles, and determine a clock cycle count value;
a selection circuit, configured to determine a target clock cycle count value according to a first config signal; and
a control circuit, connected to the counting circuit and the selection circuit, and configured to: control an On Die Termination (ODT) path to be in an enabled state responsive to a level state of an ODT pin signal being inverted, and start the counting circuit; and control the ODT path to switch from the enabled state to a disabled state when the clock cycle count value reaches the target clock cycle count value;
wherein the control circuit comprises a first control subcircuit and a second control subcircuit, wherein
the first control subcircuit is configured to generate a first intermediate signal according to the ODT pin signal, wherein the first intermediate signal comprises: before the level state of the ODT pin signal is inverted, the first intermediate signal is at a first level; after the level state of the ODT pin signal is inverted, the first intermediate signal is switched from the first level to a second level and maintains at the second level for a preset time period; and after the preset time period, the first intermediate signal is switched from the second level to the first level; and
the second control subcircuit is configured to perform a logical operation on the first intermediate signal to generate an ODT enable signal, wherein the ODT enable signal is configured to: control the ODT path to be in the enabled state when the ODT enable signal is at a third level; and control the ODT path to be in the disabled state when the ODT enable signal is at a fourth level;

wherein the first control subcircuit comprises a delay circuit and an XOR gate circuit, wherein
the delay circuit is configured to delay the ODT pin signal by the preset time period to obtain a delayed ODT signal; and
the XOR gate circuit is configured to perform an XOR operation on the ODT pin signal and the delayed ODT signal to obtain the first intermediate signal.