Patent ID: 11894846
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 9:
10. A memory device, comprising:
clock distortion calibration circuitry including update control circuitry and detection circuitry operably connected to the control circuitry,
wherein the detection circuitry is configured to:
in response to determining that a duty cycle calibration (DCC) condition is met, set a DCC enable signal to a first state, wherein the DCC condition comprises the memory device performing a data write operation and refraining from performing a data read operation based on receiving a command; and
in response to determining that the DCC condition is not met, set the DCC enable signal to a second state different from the first state, and
wherein the update control circuitry is configured to:
in response to determining that the DCC enable signal is in the first state, enable the clock distortion calibration circuitry to execute a DCC operation to adjust a trim value associated with a duty cycle of a voltage signal; and
in response to determining that the DCC enable signal is in the second state while the clock distortion calibration circuitry is executing the DCC operation, disable the clock distortion calibration circuitry before execution of the DCC operation is completed such that the clock distortion calibration circuitry is disabled (i) from adjusting the trim value during the execution of the DCC operation or (ii) from using an adjusted trim value, generated during the execution of the DCC operation, to calibrate the duty cycle of the voltage signal.