Patent ID: 11928045
Assignee: CADENCE DESIGN SYSTEMS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A computer-implemented method for use with an electronic design comprising:
simulating a processor model representative of a processor and a hardware model representative of a hardware element, wherein each of the processor model and the hardware model are executed with a corresponding simulator thread on a simulation platform;
simulating embedded software using the processor model, wherein the simulating the embedded software includes updating a given register of the processor model that stores a value that changes in response to switching between one or more processes within the embedded software;
setting a simulator breakpoint, wherein a change of state in the given register is captured at the simulator breakpoint;
setting a software breakpoint at a function that switches between the one or more processes within the embedded software; and
enabling debugging of both non-virtual and virtual addresses at the software breakpoint without leaving the software breakpoint, wherein the non-virtual addresses are associated with a register transfer level model written in a first hardware description language and the virtual addresses are associated with a transaction level model written in a system level modeling language.