Patent ID: 11922998
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A memory device, comprising:
a memory array including a first memory bank having a first memory cell connected to a first local bit line and a first word line;
a first local I/O including a first local data latch connected to the first local bit line, the first local data latch having an enable terminal configured to receive a first local clock signal;
a global controller configured to receive a memory address, the global controller having a global address latch configured to latch an address signal and having an enable terminal configured to receive a global clock signal, and including an address decoder circuit configured to decode the memory address and provide a first bank select signal; and
a first local controller connected to the first memory bank and to the global controller, the first local controller having a first bank select latch configured to latch the first bank select signal received from the address decoder circuit of the global controller, the first bank select latch having an enable terminal configured to receive a second local clock signal,
wherein the first local controller includes:
a first AND gate having a first input configured to receive the second local clock signal, a second input configured to receive the first bank select signal, and an output connected to an enable terminal of a word line latch, and
a second AND gate having a first input coupled to the output of the first AND gate and a second input connected to the global address latch.