Patent ID: 11972834
Assignee: QUALCOMM INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. The level-shifting pulse latch of claim 9, further comprising:
a NAND gate configured to NAND the memory select signal with a scan-in signal to form a latch input signal;
a second inverter formed by a first NMOS transistor in series with a first PMOS transistor and configured to invert the latch input signal to form the inverted latch input signal;
a second NMOS transistor having a source connected to ground and a drain connected to a drain for the first NMOS transistor, wherein a gate for the second NMOS transistor is configured to be controlled by the first internal clock signal; and
a second PMOS transistor having a source connected to a power supply node for the system power supply voltage and having a drain connected to a source for the first PMOS transistor, wherein a gate for the first PMOS transistor is configured to controlled by the second internal clock signal.