Patent ID: 11869886
Assignee: SEIKO EPSON CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. The ESD protection circuit according to claim 1, further comprising:
a first diode which is disposed between a P-channel open drain terminal provided to the protection target circuit and a fifth line configured to supply a fifth potential as a potential lower than the first potential, and an anode and a cathode of which are coupled respectively to the fifth line and the P-channel open drain terminal;
a second diode which is disposed between the P-channel open drain terminal and the first line, and an anode and a cathode of which are coupled respectively to the P-channel open drain terminal and the first line; and
a third diode which is disposed between the fifth line and the third line, and an anode and a cathode of which are coupled respectively to the fifth line and the third line.