Patent ID: 11889697
Assignee: SK HYNIX INC.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor device, comprising:
a source structure formed over a base;
an etch prevention layer formed over the source structure;
bit lines;
a stack structure located between the etch prevention layer and the bit lines and including conductive layers and insulating layers that are alternately stacked on each other;
a channel structure extending in a vertical direction in the stack structure and the etch prevention layer;
a slit extending in the vertical direction in the stack structure and the etch prevention layer;
a spacer formed along an inner wall of the slit; and
a source contact structure formed along an inner wall of the spacer,
wherein a lower portion of the channel structure is located in the source structure and a sidewall of the lower portion of the channel structure is in direct contact with the source structure,
the source contact structure and the etch prevention layer are physically separated from each other by the spacer, and
the conductive layers correspond to at least one source select line and a plurality of word lines.