Patent ID: 11862271
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A method, comprising:
identifying memory for error correction, wherein the memory has an array of bitcells arranged in columns and rows;
analyzing column related data in the columns with error accumulation to detect a number of column errors including multiple column errors in the columns;
repairing the column related data in the columns with column redundancy including repairing the multiple column errors in each column with column redundancy;
analyzing row related data in the rows with error accumulation to detect a number of row errors including multiple row errors in the rows; and
repairing the row related data in the rows with row redundancy including repairing the multiple row errors in each row with row redundancy,
wherein repairing the column related data includes writing multiple data sequences to each column, reading the multiple data sequences from each column, comparing the written data sequences to the read data sequences, and repairing the column errors in each column with column redundancy, and
wherein repairing the row related data includes writing multiple data sequences to each row, reading the multiple data sequences from each row, comparing the written data sequences to the read data sequences, and repairing the row errors in each row with row redundancy.