Patent ID: 11893251
Assignee: APPLE INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A method, comprising:
allocating, by a processing circuit, a plurality of locations in a system memory to a buffer;
issuing, by the processing circuit, a plurality of memory transactions in a particular order, different from a linear order, for allocating respective locations of the plurality of locations into a cache memory circuit;
in response to receiving, in the particular order, content from respective ones of the plurality of memory transactions, attempting to cache, by the cache memory circuit, the plurality of locations of the buffer;
tracking a cache miss rate associated with use of the particular order to cache the plurality of locations; and
in response to determining that the tracked cache miss rate satisfies a threshold rate, adjusting the particular order for a subsequent use.