Patent ID: 11948649
Assignee: NANJING QINHENG MICROELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 0:
1. An anti-fuse memory cell, comprising a base, wherein the base is provided with an N-well and a non-N-well region; the non-N-well region is provided with a first NMOS transistor; a gate of the first NMOS transistor is used for inputting a first selection signal; the N-well is provided with a PMOS transistor and a varactor; a gate of the PMOS transistor and a gate of the varactor are both connected to a drain of the first NMOS transistor; and the N-well, a drain, a source and a substrate of the PMOS transistor and a drain a source, and a substrate of the varactor are all connected to a controllable power supply; the source of the PMOS transistor is adjacent to the source of the varactor; the drain of the PMOS transistor is adjacent to the drain of the varactor; an active region of the PMOS transistor is adjacent to an active region of the varactor; the gate of the PMOS transistor is adjacent to the gate of the varactor or the PMOS transistor and the varactor share one gate, and at least one of the drain and the source of the varactor is N-type implanted and reused as a N-well tap of the PMOS transistor; and the PMOS transistor has no dedicated N-well tap.