Patent ID: 11971837
Assignee: PHYTIUM TECHNOLOGY CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 4:
5. The interface circuit according to claim 4, wherein:
the second address is an x-bit address, wherein x is a positive integer;
the address conversion circuit is further configured to prepend z bits to the second address based on the. portion of the data stored in the register and corresponding to the kith sub-interface circuit, and to make values of the added z data bits all have a same pre-determined value to generate a first intermediate address, wherein z is a positive integer;
the address conversion circuit is further configured to generate a second intermediate address based on the portion of the data stored in the register and corresponding to the kth sub-interface circuit, wherein values of the lowest x data bits of the second intermediate address all have a same pre-determined value, and a number of the data bits of the second intermediate address is equal to a number of the data bits of the first intermediate address;
the address conversion circuit further includes a plurality of logic operators;
a first terminal and a second terminal of the plurality of logic operators are configured to receive the first intermediate address and the second intermediate address, respectively; and
the plurality of logic operators is configured to perform logic operations on data of data bits corresponding to the first intermediate address and the second intermediate address to generate the third address and output the third address through the plurality of logic operators.