Patent ID: 11862535
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. An integrated chip, comprising:
a plurality of interconnects disposed within an inter-level dielectric (ILD) structure arranged along a first side of a substrate;
an etch stop layer arranged along the first side of the substrate;
a through-substrate-via (TSV) extending through the substrate and the etch stop layer;
a dielectric liner separating the TSV from the substrate, wherein the dielectric liner is along sidewalls of the substrate and the etch stop layer and wherein the dielectric liner comprises a first sidewall and a second sidewall facing opposing sides of the TSV and a horizontally extending ledge protruding outward from the first sidewall and towards the second sidewall; and
wherein the TSV comprises a horizontally extending surface disposed on the horizontally extending ledge of the dielectric liner and a protrusion extending outward from the horizontally extending surface to one of the plurality of interconnects.