Patent ID: 11942475
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A structure, comprising:
a first transistor formed on a first region of a semiconductor substrate, wherein the first transistor comprises:
a first source/drain region having a lightly doped region;
a silicon oxide gate dielectric disposed above the semiconductor substrate, wherein an edge of the silicon oxide gate dielectric coincides with an edge of the lightly doped region;
a polysilicon gate electrode disposed on the silicon oxide gate dielectric, wherein the polysilicon gate electrode has a length shorter than that of the silicon oxide gate dielectric; and
a first spacer structure with inner sidewalls abutting sidewall edges of the polysilicon gate electrode; and

a second transistor formed on a second region of the semiconductor substrate, wherein the second transistor has a smaller surface area than that of the first transistor and comprises:
a high-k gate dielectric;
a metal gate electrode disposed on the high-k gate dielectric;
a second spacer structure abutting sidewall edges of the metal gate electrode and the high-k gate dielectric; and
a second source/drain region substantially co-planar with the first source/drain region and in physical contact with a bottom surface of the second spacer structure.