Patent ID: 11936392
Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A phase locked loop comprising:
a multi-phase clock generation circuit configured to generate a plurality of feedback clocks signals having different phases;
a feedback side frequency divider configured to divide frequencies of the plurality of feedback clock signals and to output the plurality of feedback clock signals as frequency-divided clock signals;
a reference clock latch circuit configured to:
hold the frequency divided clock signals in synchronization with a predetermined reference clock signal and to output a held value, and
output the held value as a fractional part code representing a fractional part of a phase difference between the reference clock signal and any of the plurality of feedback clock signals; and

a control circuit configured to control the frequencies of the plurality of feedback clock signals based on the held value, wherein the control circuit includes:
a feedback side accumulator configured to integrate a predetermined value in synchronization with any of the frequency-divided clock signals and to output an integrated value,
a retiming circuit configured to hold the reference clock signal in synchronization with any of the plurality of feedback clock signals and to output the reference clock signal as a retiming clock signal,
an integrated value latch circuit configured to hold the integrated value in synchronization with the retiming clock signal and to output the held value as an integral part code representing an integral part of the phase difference,
a correction circuit configured to obtain a correction value for the phase difference representing the integral part code and the fractional part code, and
a phase comparator configured to correct the phase difference according to the correction value and to output phase difference information representing the corrected phase difference.