Patent ID: 11899584
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. A system comprising:
a random access memory structured to include memory cells to store data;
a cache memory configured to cache at least part of the data; and
a processor in communication with the random access memory and the cache memory to access at least part of the data in the random access memory or the cache memory,
wherein the processor is configured to: determine a cache hit ratio for the cache memory;
and set an operating frequency of the random access memory based on the cache hit ratio for the cache memory,
wherein the system determines a size of data in the random access memory that is accessed by the processor based on a size of data in the random access memory and the cache memory that is accessed by the processor and the cache hit ratio for the cache memory, and sets the operating frequency of the random access memory based on the size of the data in the random access memory that is accessed by the processor.