Patent ID: 11941501
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. The electronic apparatus as claimed in claim 6, wherein the shuffler comprises:
a plurality of buffer sets comprising circuitry; and
a first in first out (FIFO) memory comprising circuitry and which receives at least two processing elements from among the plurality of processing elements, output from corresponding register files from among the plurality of register files, and outputs the plurality of operation results to the plurality of buffer sets,
wherein the plurality of buffer sets store each of the plurality of operation results in a buffer corresponding to each of the plurality of buffer sets, and
wherein, based on the plurality of operation results being stored in all buffers included in the plurality of buffer sets, outputs the plurality of processing elements stored in one of the plurality of buffer sets to the line memory in a pre-set order.