Patent ID: 11953936
Assignee: SILICON LABORATORIES INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. An apparatus comprising:
an oscillator to output a clock signal on a first line;
a switch coupled to the first line, the switch configured to pass the clock signal when closed;
a voltage divider coupled to the switch, a first pin and a second pin, the first pin and the second pin external to a semiconductor die of the apparatus; and
a control circuit coupled to the switch, the control circuit configured to cause the switch to output the clock signal through the voltage divider via the first line to the first pin in a non-reset mode and prevent the clock signal from being provided to the first pin in a reset mode, the non-reset mode following the reset mode in which a reset flow of the apparatus occurs.