Patent ID: 11935894
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 14:
15. An integrated circuit device, comprising:
a plurality of cells at respective cell locations, each cell comprising:
a device layer having device features spaced in accordance with a predetermined device pitch;
a first interconnection layer disposed above the device layer and coupled to the device layer; and
a second interconnection layer disposed above the first interconnection layer and coupled to the first interconnection layer through a first via layer,
wherein the second interconnection layer has connection lines spaced in accordance with a predetermined line pitch, and
wherein a ratio of the predetermined line pitch to predetermined device pitch is less than 1,
wherein the each cell includes at least one cell connection pin in the first metal interconnection layer and at least one cell connection pin in the second metal interconnection layer, and
wherein each cell conforms with the equation M0_Enc≤(Max_M0_Length−Max_M1_Pitch_Length−VIA0_Width)/2, where:
Max_M0_Length represents a maximum possible length of a line in the first interconnection layer in the cell;
Max_M1_Pitch_Length represents a maximum possible pitch between two lines in the second interconnection layer in the cell;
VIA0_Width represents a width of a via that connects a line in the first interconnection layer with a line in the second interconnection layer; and
M0_Enc represents a distance from an outermost edge of the line in the first interconnection layer to an edge of a nearest possible via connecting the line in the first interconnection layer to the line in the second interconnection layer.