Patent ID: 11862515
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of forming an integrated chip structure, comprising:
receiving a first semiconductor substrate;
forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of the first semiconductor substrate;
performing an first edge trimming process to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate, wherein the first edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an outer sidewall disposed directly over the first semiconductor substrate;
forming a metal residue layer after the first edge trimming process, the metal residue layer extending over the plurality of interconnect layers; and
forming a first dielectric capping structure along a sidewall of the metal residue layer, over an upper surface of the metal residue layer, and along a sidewall of the first interconnect structure.