Patent ID: 11955480
Assignee: STMICROELECTRONICS (TOURS) SAS
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 5:
6. A method, comprising:
forming a first region of a first surface of a substrate having a first thickness with respect to a second surface of the substrate opposite to the first surface and a second region of the substrate having a second thickness smaller than the first thickness with respect to the second surface;
forming a trench in the first region of the substrate;
forming a stack of layers on a surface of the first region and in the trench, the stack of layers including a first conductive layer, a second conductive layer, and a first dielectric layer stacked between the first conductive layer and the second conductive layer; and
forming a first contact structure over the second region, the first contact structure in contact with the first conductive layer and separated from the second conductive layer;
forming a first interconnect structure that extends through the second region of the substrate and in contact with the first contact structure.