Patent ID: 11875847
Assignee: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A sense circuit for use with an array of memory cells, the sense circuit comprising:
a regulation circuit configured to receive as input an input voltage, a full read voltage from reading of a selected cell of the array of memory cells, and a fractional read voltage applied to unselected cells of the array of memory cells, the regulation circuit configured to generate a regulated voltage and a regulated fractional voltage based upon the input, wherein the regulated voltage and the regulated fractional voltage are used in reading of the selected cell of the array of memory cells;
a capacitor circuit configured to generate a reference voltage through charge sharing between an input capacitor and a reference capacitor; and
a comparator circuit configured to generate a data output signal based upon a comparison between the reference voltage and the input voltage.