Patent ID: 11948987
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 8:
9. A semiconductor device, comprising:
a source feature and a drain feature;
a plurality of semiconductor nanostructures extending between the source feature and the drain feature along a first direction;
a first dielectric fin and a second dielectric fin sandwiching the source feature and the drain feature along a second direction perpendicular to the first direction;
a first isolation feature disposed on the first dielectric fin;
a second isolation feature disposed on the second dielectric fin;
a gate structure wrapping around each of the plurality of semiconductor nanostructures;
a bottom dielectric layer disposed over the gate structure and the drain feature and sandwiched directly between the first dielectric fin and the second dielectric fin along the second direction; and
a backside power rail disposed over the bottom dielectric layer,
wherein the backside power rail is isolated from the drain feature by the bottom dielectric layer,
wherein the backside power rail is electrically coupled to the source feature,
wherein each of the first dielectric fin and the second dielectric fin comprises an inner dielectric layer, an outer dielectric layer wrapping over the inner dielectric layer, and a dielectric capping layer underlying and in direct contact with the inner dielectric layer and the outer dielectric layer.