Patent ID: 11929927
Assignee: INTEL CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A system comprising:
a central processing unit (CPU) interconnect; and
a network interface device comprising:
a first interface;
a second interface;
direct memory access (DMA) circuitry; and
circuitry to:
based on receipt of a packet:
copy a portion of the received packet via the first interface to the CPU interconnect to forward to a first memory buffer accessible by a CPU connected to the CPU interconnect and

based on receipt of a second packet:
copy, by the DMA circuitry, a portion of the second received packet via the second interface to an accelerator fabric to forward to a second memory buffer accessible by an accelerator device connected to the accelerator fabric, wherein
the accelerator device comprises a field programmable gate array (FPGA) and an application specific integrated circuit (ASIC) and
the network interface device comprises second circuitry to: based on a request to transmit a third packet that comprises data generated by the accelerator device, copy the data via the second interface and the accelerator fabric and cause transmission of the third packet.