Patent ID: 11929772
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Telecommunications (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. An electronic circuit comprising:
a plurality of sub electronic circuits configured to convert a receive signal being analog into reception data being digital,
wherein each of the plurality of sub electronic circuits includes:
a delay circuit configured to receive a first receive signal and to output a reference signal, the reference signal being generated by delaying the first receive signal as much as one or a plurality of different timing delays respectively set to a plurality of loops;
a sub analog-to-digital converter (sub-ADC) configured to receive a second receive signal and to sample the second receive signal based on the reference signal in each of the plurality of loops;
an estimation circuit configured to output a compensation signal for compensating for a timing skew by extracting a statistical characteristic of sample data sampled through the sub-ADC and estimating the timing skew based on the statistical characteristic; and
a loop filter configured to filter specific frequency components of the compensation signal.