Patent ID: 11925024
Assignee: KIOXIA CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. The semiconductor memory device according to claim 8, wherein
the substrate has an eighth region, and the eighth region is arranged with the second region in the first direction and arranged with the seventh region in the second direction,
each of the plurality of first word line layers includes an eighth word line part provided over the eight region,
each of the plurality of first interlayer insulating layers includes an eleventh interlayer insulating part provided over the eighth region,
all eleventh interlayer insulating parts of the plurality of first interlayer insulating layers are laminated in the third direction alternately with all eighth word line parts of the plurality of first word line layers,
the semiconductor memory device comprises a fifth contact extending in the third direction, the fifth contact being connected to one of the eighth word line parts of the plurality of first word line layers at the one end in the third direction,
the one of the eighth word line parts of the plurality of first word line layers electrically connected to the fourth contact is the fifth contact.