Patent ID: 11935598
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. A semiconductor storage device comprising:
a first memory transistor;
a bit line electrically coupled to the first memory transistor;
a third transistor electrically coupled to the first memory transistor via the bit line; and
a third signal supply line coupled to a gate electrode of the third transistor,
wherein the third transistor includes:
a first semiconductor layer facing a semiconductor substrate; and
a first insulating layer provided between the semiconductor substrate and the first semiconductor layer, and wherein the first semiconductor layer includes: a third region connected to a first electrode and containing impurities of a first conductive type; a fourth region connected to a second electrode and containing the impurities of the first conductive type; and a fifth region provided between the third region and the fourth region, and containing impurities of a second conductive type different from the first conductive type, and the semiconductor substrate includes an impurity region that faces the fifth region and is connected to the third signal supply line.