Patent ID: 11942454
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A package, comprising:
a first die, comprising:
a first interconnection structure; and
first bonding vias at least partially embedded in the first interconnection structure;

a second die stacked on the first die, comprising:
a second interconnection structure; and
second bonding vias at least partially embedded in the second interconnection structure;
a passive device, comprising a first portion and a second portion electrically connected to the first portion, wherein the first portion is embedded in the first interconnection structure, the second portion is embedded in the second interconnection structure, the first portion comprises a bottom metal layer, an insulating layer, and a top metal layer stacked in sequential order, one of the first bonding vias is directly in contact with the top metal layer, and another one of the first bonding vias is directly in contact with the bottom metal layer; and
an encapsulant laterally encapsulating the second die.