Patent ID: 11934317
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 15:
16. A method comprising:
receiving, by a memory controller of a memory system comprising a memory array and a memory cache, a pre-fetch buffer, or both, a memory access request targeting a memory page of the memory array via a memory bus;
determining, by the memory controller, whether a data block of the memory page is stored in the memory cache, the pre-fetch buffer, or both;
enabling, by the memory controller, a cache bypassing associated with the memory cache, the pre-fetch buffer, or both when the memory page is deactivated and a statistical likelihood that a subsequent memory access request will target the memory page is higher than a first threshold in response to determining that the data block of the memory page is not stored in the memory cache, the pre-fetch buffer, or both, wherein the cache bypassing is determined based on one or more previously determined counter values each indicating a number of consecutive memory access requests previously targeting the memory page; and
instructing, by the memory controller, the memory array to output the data block of the memory page directly to a processor-side via a memory bus in response to determining that the cache bypassing is enabled.