Patent ID: 11908890
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor device, comprising:
a first vertical transistor comprising a first lower source/drain region and a first upper source/drain region disposed on a semiconductor substrate;
a second vertical transistor comprising a second lower source/drain region and a second upper source/drain region stacked on the first vertical transistor;
an isolation layer disposed between the first upper source/drain region of the first vertical transistor and the second lower source/drain region of the second vertical transistor;
at least one dielectric layer distinct from the isolation layer, wherein the at least one dielectric layer is disposed on lateral sides of the isolation layer and disposed on the first vertical transistor and the second vertical transistor;
wherein the isolation layer has a greater lateral width than a lateral width of the first upper source/drain region and a lateral width of the second lower source/drain region;
wherein an entirety of respective ones of lateral sides of the first upper source/drain region and of the second lower source/drain region are recessed with respect to the lateral sides of the isolation layer; and
wherein the isolation layer comprises a rare earth oxide.