Patent ID: 11879939
Assignee: NXP B.V.
Field: Measurement (Instruments)
Classification: CPC G  H | IPC G  H

Claim 3:
4. The IC of claim 3, wherein the testing system further comprises:
a first flip-flop configured to generate a second pipeline enable signal based on (i) a scan enable signal, (ii) the first pipeline enable signal, and (iii) a fourth clock signal that is generated based on the first clock signal, the first clock enable signal, and the first pipeline enable signal; and
a first inverter that is coupled to the first flip-flop, and configured to generate the first pipeline enable signal as an inverted version of the second pipeline enable signal, wherein a transition of the scan enable signal from the asserted state to a de-asserted state is indicative of the activation of the capture phase, wherein based on the activation of the capture phase, the second pipeline enable signal is de-asserted and the first pipeline enable signal is asserted, and wherein during the capture phase, based on a transition of the fourth clock signal, the second pipeline enable signal is asserted and the first pipeline enable signal is de-asserted.