Patent ID: 11909401
Assignee: UNIVERSITY OF WASHINGTON
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A self-clocked dynamic comparator, comprising:
a latch configured to receive an input voltage (VIN), a reference voltage (VREF) and a clocking (CLKsf) signal, and configured to output a first rail-to-rail output (OUT+) signal and a second rail-to-rail output (OUT−) signal;
a first pre-amplifier (PRE-AMP) configured to output a first enable (TRI) signal based on a comparison between the VIN and VREF-Δv; and
a first AND gate configured to receive the first TRI signal and one of the OUT− signal, and configured to output the CLKsf signal;
a second PRE-AMP configured to output a second TRI signal based on a comparison between the VIN and VREF+Δv; and
a second AND gate configured to receive the second TRI signal and the OUT+ signal, and configured to output the CLKsf signal;
wherein cycles of the CLKsf signal cause the latch to dissipate energy.