Patent ID: 11879942
Assignee: MICRON TECHNOLOGY, INC.
Field: Measurement (Instruments)
Classification: CPC G | IPC G

Claim 10:
11. A system, comprising:
a plurality of integrated circuits, wherein each integrated circuit, included in the plurality of integrated circuits, includes:
a plurality of lower-level input scan flip-flops arranged in a plurality of lower-level input scan flip-flop stages that includes at least a first lower-level input scan flip-flop stage and a second lower-level input scan flip-flop stage,
wherein inputs to a first plurality of lower-level input scan flip-flops included in the first lower-level input scan flip-flop stage are connected to inputs of a corresponding integrated circuit, of the plurality of integrated circuits, that includes the plurality of lower-level input scan flip-flops, and
wherein inputs to a second plurality of lower-level input scan flip-flops included in the second lower-level input scan flip-flop stage are connected to outputs of a logic component that is connected to outputs of the first plurality of lower-level input scan flip-flops;

a plurality of lower-level output scan flip-flops arranged in a plurality of lower-level output scan flip-flop stages that includes at least a first lower-level output scan flip-flop stage and a second lower-level output scan flip-flop stage,
wherein outputs from a first plurality of lower-level output scan flip-flops included in the first lower-level output scan flip-flop stage are connected to outputs of the corresponding integrated circuit, and
wherein outputs from a second plurality of lower-level output scan flip-flops included in the second lower-level output scan flip-flop stage are connected to inputs of a logic component that is connected to inputs of the first plurality of lower-level output scan flip-flops; and

a plurality of lower-level core scan flip-flops,
wherein a first stage of lower-level core scan flip-flops, included in the plurality of lower-level core scan flip-flops, are connected to a final lower-level input scan flip-flop stage of the plurality of lower-level input scan flip-flop stages, and
wherein a second stage of lower-level core scan flip-flops, included in the plurality of lower-level core scan flip-flops, are connected to an initial lower-level output scan flip-flop stage of the plurality of lower-level output scan flip-flop stages.