Patent ID: 11886293
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. A memory controller comprising:
a processor configured to control a memory operation for a memory device and to designate one or more cells of a memory cell array of the memory device as a monitoring unit;
an error correcting code (ECC) circuit configured to perform an error correction operation on data read from the memory device, to generate first strong error information based on hard decision information collected using a normal read level and soft decision information collected using one or more offset read levels for the monitoring unit of the memory device, and to generate second strong error information based on the hard decision information and the soft decision information collected again for the monitoring unit in response to a read request from a host; and
a volatile memory configured to store the first strong error information or the second strong error information, wherein:
the normal read level and the offset read levels have different values, and
the ECC circuit corrects an error of data requested to be read from the host by using the first strong error information and the second strong error information.