Patent ID: 11894049
Assignee: SYNOPSYS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 7:
8. A method for reading a memory cell, the memory cell comprising,
a pair of cross-coupled inverters as a storage element, a first inverter in the pair of cross-coupled inverters having a first output at a first node, a second inverter in the pair of cross-coupled inverters having a second output at a second node;
a first complementary transmission gate including a first nMOS pass gate and a first pMOS pass gate, connected between the first node and a first bit line;
a second complementary transmission gate including a second nMOS pass gate and a second pMOS pass gate, connected between the second node and a second bit line;
a first word line connected to gate conductors of the first and second nMOS pass gates in the first and second complementary transmission gates; and
a second word line connected to gate conductors of the first and second pMOS pass gates in the first and second complementary transmission gates,
the method comprising:
first triggering a signal drop on the second word line to generate a first voltage drop on the first bit line;
after the first triggering, waiting until a bump voltage at the first node drops; and
triggering a signal rise on the first word line after the bump voltage at the first node drops, to generate a second voltage drop on the first bit line.