Patent ID: 11961561
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. A method of operating a memory device comprising a read and write circuit including a plurality of page buffers respectively connected to memory cells included in a memory block through a plurality of bit lines, a current sensing circuit configured to perform a verify operation of comparing sensing voltages received from the plurality of page buffers with a reference voltage corresponding to an error correctable bit number, and a control logic configured to group the plurality of page buffers into a plurality of page buffer groups, and control the current sensing circuit to perform the verify operation for each of the plurality of page buffer groups, the method comprising:
determining a logical group number of page buffers having consecutive column addresses to be the same among the plurality of page buffers;
determining a physical group number of page buffers whose column addresses increase by a number of physical groups sequentially to be the same among the plurality of page buffers;
performing a first verify operation on the sensing voltages of each of the page buffer groups having a same logical group number;
performing a second verify operation on the sensing voltages of each of the page buffer groups having a same physical group number; and
outputting a verify pass signal in response to both results of the first verify operation and the second verify operation satisfying a pass criterion.