Patent ID: 11967632
Assignee: nan
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. A memory array comprising strings of memory cells, comprising:
a conductor tier comprising conductor material;
laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above the conductor tier, conducting material of a lowest of the conductive tiers being directly against the conductor material of the conductor tier, channel-material strings of memory cells extending through the insulative tiers and the conductive tiers;
intervening material laterally-between and longitudinally-along immediately-laterally-adjacent of memory blocks, the intervening material comprising insulating material that is directly against the conductor material of the conductor tier;
the conducting material in the lowest conductive tier being directly electrically coupled to the channel material of individual of the channel-material strings; and
the insulating material of the intervening material projecting laterally in a direction towards the channel-material strings to be directly under a lowest of the insulative tiers.