Patent ID: 11959938
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Measurement (Instruments)
Classification: CPC G | IPC G

Claim 4:
5. The package substrate of claim 4, wherein the surface of the package substrate is further disposed with the chip to be tested, and the chip to be tested comprises a plurality of pin arrays, each of the plurality of pin arrays at least comprising power supply pins,
wherein power supply pins belonging to the same power supply type in the plurality of pin arrays are divided into a test pin and a power supply pin set, and
wherein each of power supply pins in the power supply pin set is electrically connected to a respective one of the power supply pads in the power supply pad set, and the test pin is electrically connected to the test pad, so that the test pad is capable of performing, through the test pin, the noise teasing of the internal power supply corresponding to the same power supply type in the chip to be tested.