Patent ID: 11935853
Assignee: nan
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. A method for manufacturing a memory die, the method comprising:
forming a through-silicon via (TSV) in a substrate of the memory die, the substrate comprising a frontside and a backside opposite the frontside;
forming control circuitry on the frontside of the substrate of the memory die;
forming a memory array on the memory die, the memory array over the control circuitry and the TSV on the memory die, wherein the memory array is electrically coupled to the control circuitry; and
forming a bond pad on the backside of the substrate of the memory die, wherein the bond pad is (1) electrically coupled to the control circuitry via the TSV and (2) configured for coupling the memory array to one or more external components.