Patent ID: 11862280
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 8:
9. An apparatus, comprising:
a first memory array at a first deck of a plurality of decks of the apparatus, the first memory array comprising a first plurality of electrodes and a first plurality of memory cells;
a first plurality of transistors configured to select electrodes from the first plurality of electrodes;
a second memory array at a second deck of the plurality of decks of the apparatus, the second memory array comprising a second plurality of electrodes and a second plurality of memory cells;
a second plurality of transistors configured to select electrodes from the second plurality of electrodes; and
decoder circuitry configured to select one or more decks from among the plurality of decks of the apparatus, the decoder circuitry positioned between the first deck and the second deck.