Patent ID: 11886622
Assignee: UNIVERSITY OF CINCINNATI
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 15:
16. A method of operating a THx2 threshold gate cell comprising:
accessing the THx2 threshold gate cell comprising a mode-independent PMOS configuration and an NMOS configuration configured to operate in one of a TH12 mode and a TH22 mode;
setting x to a threshold of 1 to operate in the TH12 mode; and
setting x to a threshold of 2 to operate in the TH22 mode, wherein:
the THx2 threshold gate cell is one of a mask programmable gate array (MPGA) and a field programmable gate array (FPGA), the MPGA comprising an MPGA base cell and an output network, the FPGA comprising a memory cell configured to transmit a signal M and a logical inverse signal Mb, an FPGA base cell configured to receive the signal M and the logical inverse signal Mb, and a modified output network comprise one NMOS transistor and three PMOS transistors;
setting x in THx2 to a threshold of 1 to operate in the TH12 mode comprises
(1) connecting a pair of NMOS transistors in parallel in the NMOS configuration to eliminate an NMOS transistor of the NMOS configuration in the TH12 mode for the MPGA, and
(2) programming the memory cell for the FPGA such that a pair of NMOS transistors in the FPGA base cell are configured to receive respective inputs and be connected in parallel and a value of 1 on the signal M and a value of 0 on the logical inverse signal Mb from the memory cell is configured to operate the FPGA base cell in the TH12 mode; and

setting x in THx2 to a threshold of 2 to operate in the TH22 mode comprises
(1) connecting the pair of NMOS transistors in in series in the NMOS configuration for the MPGA, and
(2) programming the memory cell for the FPGA such that the pair of NMOS transistors in the FPGA base cell configured to receive respective inputs are configured to be connected in series and a value of 0 on the signal M and a value of 1 on the logical inverse signal Mb from the memory cell is configured to operate the FPGA base cell in the TH22 mode for the FPGA.