Patent ID: 11910723
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 16:
17. A method, comprising:
providing a memory cell array having a plurality of memory cells arranged in a plurality of rows and a plurality of columns, each row of memory cells being associated with a word line, each column of memory cells being associated with a bit line and a source line, wherein each memory cell comprises:
a storage device coupled to the bit line, the storage device being selectable between a first resistance state and a second resistance state in response to a bit line signal at the bit line; and
a selection device connected in series with the storage device and coupled to the source line, the selection device being configured to provide access to the storage device in response to a word line signal at the word line;

coupling a word-line driver to the word line to generate the word line signal;
coupling a bit-line driver the bit line to generate the bit line signal; and
electrically connecting corresponding source lines for the each column of memory cells in parallel through one or more metal contacts that extend perpendicular to the source lines.