Patent ID: 11960856
Assignee: FLEX LOGIX TECHNOLOGIES, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. An integrated circuit comprising:
a multiplier-accumulator execution pipeline to receive (i) input data and (ii) filter weights, wherein the multiplier-accumulator execution pipeline includes a plurality of multiplier-accumulator circuits to process the input data, using associated filter weights, via a plurality of multiply operations and a plurality of accumulate operations;
first memory to store filter weights having a Gaussian floating point data format and a first bit length;
data format conversion circuitry, (i) having inputs connected to outputs of the first memory, to receive the filter weights having the Gaussian floating point data format and the first bit length, and (ii) coupled to inputs of the multiplier-accumulator execution pipeline, wherein the data format conversion circuitry further includes:
a data format conversion circuit, coupled to the inputs of the data format conversion circuitry, to receive the filter weights having the Gaussian floating point data format and the first bit length, to convert the filter weights from the Gaussian floating point data format and the first bit length to filter weights having a data format and a bit length that are different from the Gaussian floating point data format and the first bit length, and
outputs, coupled to the inputs of the multiplier-accumulator execution pipeline, to output the filter weights having the data format and the bit length that are different from the Gaussian floating point data format and the first bit length, respectively; and

wherein, in operation, the multiplier-accumulator circuits of the multiplier-accumulator execution pipeline are configured to perform the plurality of multiply operations using (a) the input data and (b) the filter weights having the data format and the bit length that are different from the Gaussian floating point data format and the first bit length, respectively.