Patent ID: 11928475
Assignee: CEREMORPHIC, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. An apparatus comprising: a primary processor comprising a primary processor pipeline, wherein the primary processor pipeline comprises, operably connected in sequence, a fetch stage, a decode stage, an execute stage, a load/store stage, and a writeback stage;
a secondary processor comprising a secondary processor pipeline, wherein the secondary processor pipeline comprises, operably connected in sequence, a fetch stage, a decode stage, an execute stage, a load/store stage, and a writeback stage,
wherein the primary processor pipeline fetch stage and the secondary processor pipeline fetch stage are operably coupled to a program store common to the primary processor and the secondary processor;
a store data comparator having a first input operably coupled with an output of the primary processor pipeline execute stage to receive delayed primary processor pipeline signals through a primary processor store data comparison delay module comprising a three-stage buffer delay, a second input operably coupled with the secondary processor pipeline execute stage to receive delayed secondary processor pipeline signals through a secondary processor store data comparison delay module comprising a one-stage buffer delay, and an output, wherein the store data comparator is configured to indicate at the output a result of comparing the delayed primary processor pipeline signals with the delayed secondary processor pipeline signals, and wherein the delayed primary processor pipeline signals and the delayed secondary processor pipeline signals compared by the store data comparator further comprise handshake signals and data between a data cache and a core, and handshake signals between a data memory and the core;
a primary processor pipeline store data control gate having a first input, a second input, and an output, wherein the first input is operably coupled with an output of the primary processor pipeline execute stage to receive delayed primary processor pipeline signals through a primary processor store data path delay module comprising a three-stage triple module redundancy buffer delay wherein each stage is configured to pass only majority data, wherein the second input is operably coupled with the store data comparator output, and the primary processor pipeline store data control gate is configured to output the delayed primary processor pipeline store data path signals to the primary processor pipeline load/store stage only if the store data comparator output indicates agreement between the delayed primary processor pipeline signals and the delayed secondary processor pipeline signals compared by the store data comparator, and wherein the primary processor pipeline is configured to forward data from the primary processor pipeline store data path delay module to the writeback stage if a load data address matches the address of data in the primary processor pipeline store data path delay module buffer stages;
a secondary processor pipeline store data control gate having a first input, a second input, and an output, wherein the first input is operably coupled with an output of the secondary processor pipeline execute stage to receive delayed secondary processor pipeline signals through a secondary processor store data path delay module comprising a one-stage buffer delay, wherein the second input is operably coupled with the store data comparator output, and the secondary processor pipeline store data control gate is configured to output the delayed secondary processor pipeline store data path signals to the secondary processor pipeline load/store stage only if the store data comparator output indicates agreement between the delayed primary processor pipeline signals and the delayed secondary processor pipeline signals compared by the store data comparator, and wherein the secondary processor pipeline is configured to forward data from the secondary processor pipeline store data path delay module to the writeback stage if a load data address matches the address of data in the secondary processor pipeline store data path delay module;
a writeback comparator having a first input operably coupled with an output of the primary processor pipeline load/store stage to receive delayed primary processor pipeline signals through a primary processor writeback comparison delay module comprising a three-stage buffer delay, a second input operably coupled with the secondary processor pipeline load/store stage to receive delayed secondary processor pipeline signals through a secondary processor writeback comparison delay module comprising a one-stage buffer delay, and an output, and wherein the writeback comparator is configured to indicate at the output the result of comparing the delayed primary processor pipeline signals with the delayed secondary processor pipeline signals, and wherein the delayed primary processor pipeline signals and the delayed secondary processor pipeline signals compared by the writeback comparator further comprise handshake signals and data between a register file, a data cache, a data memory, and a core;
a primary processor pipeline writeback control gate having a first input, a second input, and an output, wherein the first input is operably coupled with an output of the primary processor pipeline load/store stage to receive delayed primary processor pipeline signals through a primary processor writeback path delay module comprising a three-stage triple module redundancy buffer delay wherein each stage is configured to pass only majority data, and wherein the second input is operably coupled with the writeback comparator output, and the primary processor pipeline writeback control gate is configured to output the delayed primary processor pipeline writeback signals to the primary processor pipeline writeback stage only if the writeback comparator output indicates agreement between the delayed primary processor pipeline signals and the delayed secondary processor pipeline signals compared by the writeback comparator; and
a secondary processor pipeline writeback control gate having a first input, a second input, and an output, wherein the first input is operably coupled with an output of the secondary processor pipeline load/store stage to receive delayed secondary processor pipeline signals through a secondary processor writeback path delay module comprising a one-stage buffer delay, and wherein the second input is operably coupled with the writeback comparator output, and the secondary processor pipeline writeback control gate is configured to output the delayed secondary processor pipeline writeback signals to the secondary processor pipeline writeback stage only if the writeback comparator output indicates agreement between the delayed primary processor pipeline signals and the delayed secondary processor pipeline signals compared by the writeback comparator.