Patent ID: 11869886
Assignee: SEIKO EPSON CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An ESD protection circuit which is disposed between a first line configured to supply a first potential and a second line configured to supply a second potential different from the first potential, and protects a protection target circuit from a surge voltage, the ESD protection circuit comprising:
a power MOS transistor disposed between the first line and the second line;
a clamp circuit disposed between the first line and a first node to which a gate of the power MOS transistor is coupled;
a first resistor disposed between the first node and the second line;
a MOS transistor disposed between the first node and the second line;
a third line supplied with a third potential generated by a constant-voltage circuit of the protection target circuit; and
a second resistor and a first capacitor coupled in series between a second node coupled to the third line and the second line, wherein
when defining a junction between the second resistor and the first capacitor as a third node, a gate of the MOS transistor is coupled to the third node, and
the third potential is a potential between the first potential and the second potential.