Patent ID: 11908507
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 14:
15. The semiconductor memory device according to claim 14, wherein each of the plurality of conjunction blocks comprises:
a plurality of selection signal drivers configured to drive the plurality of selection signals in response to the random pick signal and the fourth row address so as to generate a plurality of sub word line selection signals,
wherein each of the even sub word line driver blocks comprises:
a plurality of even sub word line drivers configured to select even-numbered sub word lines among the plurality of sub word lines of each of the sub memory cell array blocks in both sides, the selecting the even-numbered sub word lines based on each of the plurality of main word line selection signals and even-numbered sub word line selection signals among the plurality of sub word line selection signals, and
wherein each of the odd sub word line driver blocks comprises:
a plurality of odd sub word line drivers configured to select odd-numbered sub word lines among the plurality of sub word lines of each of the sub memory cell array blocks in both sides, the selecting the odd-numbered sub word lines based on each of the plurality of main word line selection signals and odd-numbered sub word line selection signals among the plurality of sub word line selection signals.