Patent ID: 11972823
Assignee: APPLE INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A controller comprising:
an interface for communicating with a plurality of memory cells arranged in multiple address locations, the memory cells comprising (i) respective storage nodes for holding storage values, and (ii) respective select transistors for selecting and accessing the respective storage nodes, the select transistors being powered by an adjustable supply voltage; and
control circuitry, configured to:
read data units protected by an Error Correction Code (ECC) from the memory cells, and decode the ECC of the data units;
upon detecting, using the ECC, that a given data unit read from a given address location contains one or more errors, log an error event specifying at least a time of occurrence associated with the error event and the given address location;
identify that the select transistors, which are used for selecting and accessing the storage nodes of the memory cells, experience physical degradation due to aging, based on the times of occurrence and address locations logged in the error events; and
adjust the supply voltage provided to the select transistors to compensate for the physical degradation of the select transistors.