Patent ID: 11972145
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus, comprising:
a non-volatile memory;
a volatile memory configured to operate as cache for the non-volatile memory; and
an interface controller coupled with the non-volatile memory and the volatile memory, the interface controller operable to cause the apparatus to:
receive, from a host device, a write command associated with a row of a bank in the volatile memory;
write data associated with the write command to a buffer that is associated with the bank and that is coupled with the volatile memory;
communicate, by the interface controller, the data from the buffer to the volatile memory based at least in part on the write command and before a pre-charge command associated with the data is received, by the interface controller from the host device, for the row of the bank; and
write the data to the row of the bank in the volatile memory after communicating the data to the volatile memory and based at least in part on the write command.