Patent ID: 11972675
Assignee: RENESAS ELECTRONICS AMERICA INC.
Field: Control (Instruments)
Classification: CPC G | IPC G

Claim 19:
20. The apparatus of claim 19, wherein:
the fault test process comprises a first fault test process;
the test current comprises a first test current; and
the at least one processing device is further configured to:
configure the detection system for performance of a second fault test process by:
setting the first switch to closed;
setting the second switch to closed;
setting the third switch to open;
setting the fourth switch to closed; and
configuring the current generator of the detection system to generate a second test current;

perform the second fault test process by:
activating the current generator to generate the second test current;
deactivating the current generator after a second predetermined amount of time;
initiating a second analog-to-digital conversion to generate second count values; and
storing the second count values from the second analog-to-digital conversion in a memory;

compare the stored second count values to factory second count values corresponding to a prior performance of the second fault test process; and
determine, based at least in part on the comparison of the stored second count values to the factory second count values, that the fault condition has occurred.