Patent ID: 11949011
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A semiconductor structure comprising:
a bottom source drain region arranged on a substrate;
a semiconductor channel region extending vertically upwards from a top surface of the bottom source drain region;
a metal gate disposed around the semiconductor channel region;
a top source drain region above the semiconductor channel region;
an amorphous silicon layer directly on top of the metal gate; and
an oxidation layer directly on top of the amorphous silicon layer, wherein the amorphous silicon layer and the oxidation layer together completely separate the metal gate from a surrounding interlevel dielectric layer,
wherein an uppermost surface of the metal gate, an uppermost surface of the amorphous silicon layer, and an upper surface of the oxidation layer are substantially flush with one another, and another upper surface of the oxidation layer is substantially flush with an uppermost surface of the top source drain region.