Patent ID: 11961561
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device comprising:
a memory block including memory cells;
a read and write circuit including a plurality of page buffers respectively connected to the memory cells through a plurality of bit lines;
a current sensing circuit configured to perform a verify operation of comparing sensing voltages received from the plurality of page buffers with a reference voltage corresponding to an error correctable bit number; and
a control logic configured to group the plurality of page buffers into a plurality of page buffer groups, and control the current sensing circuit to perform the verify operation for each of the plurality of page buffer groups,
wherein the control logic is further configured to determine a logical group number and a physical group number of each of the plurality of page buffers based on a column address of each of the plurality of page buffers, and configured to control the current sensing circuit to perform a first verify operation on the sensing voltages of each of page buffer groups having a same logical group number, and perform a second verify operation on the sensing voltages of each of page buffer groups having a same physical group number,
wherein column addresses of the page buffers having the same logical group number are consecutive,
wherein column addresses of the page buffers having the same physical group number increase by a number of physical groups sequentially, and
wherein the current sensing circuit is further configured to output a verify pass signal in response to both results of the first verify operation and the second verify operation satisfying a pass criterion.