Patent ID: 11888494
Assignee: NUVOTON TECHNOLOGY CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. A semiconductor circuit including a data converter that outputs a digital output signal corresponding to a measured signal, the semiconductor circuit comprising:
an analog circuit that quantizes the measured signal inputted; and
a digital circuit that outputs the digital output signal,
wherein the analog circuit includes:
a correction element group including one or more correction elements each for correcting nonlinearity that occurs during a process of converting the measured signal into the digital output signal in the analog circuit; and
a test element group including one or more test elements for testing the one or more correction elements,

the digital circuit tests the correction element group using the test element group,
the digital circuit includes:
a self-diagnostic code generation circuit that generates a self-diagnostic code for (i) enabling or disabling each of the one or more correction elements included in the correction element group and (ii) enabling or disabling each of the one or more test elements included in the test element group;
an error detection circuit that detects, as an error signal, a difference between a quantizer output signal of the analog circuit and a predetermined threshold value, the quantizer output signal being outputted in response to the self-diagnostic code; and
a self-diagnostic circuit that generates a self-diagnostic signal indicating a diagnostic result of the correction element group, based on the error signal,

the digital circuit causes the self-diagnostic circuit to self-diagnose each of the one or more correction elements included in the correction element group,
the self-diagnostic code generation circuit has:
an optimum correction code output mode for outputting an optimum correction code in response to the error signal so that a quantization error of the quantizer becomes minimum; and
a logic inversion code output mode for outputting a logic inversion code obtained by logically inverting a first bit signal for controlling a single correction element selected as a test target from the correction element group, the first bit signal being included in the optimum correction code, and

at time of testing, the digital circuit:
enters the optimum correction code output mode, supplies the optimum correction code to the analog circuit, and generates a first error signal, based on the error signal from the error detection circuit;
enters the logic inversion code output mode, supplies the logic inversion code to the analog circuit, and generates a second error signal, based on the error signal from the error detection circuit; and
compares magnitudes of the first error signal and the second error signal, and performs a fault diagnosis on the single correction element selected as the test target.