Patent ID: 11947471
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. A memory controller, comprising:
a first interface to communicate a first write operation to a first memory device, the first interface to communicate a second write operation to the first memory device, the first memory device to perform a first verify operation after the first write operation is attempted, the first memory device to store a first entry in a first internal write retry buffer in response to the first verify operation determining the first write operation failed in a manner that causes loss of data;
a second interface to receive an indicator that at least one of the first internal write retry buffer meets a threshold criteria associated with a number of unused entries left in the first internal write retry buffer; and
a scheduler to, in response to the indicator, schedule a first command to be sent to the first memory device, the first command to cause the first memory device to retry the first write operation.