Patent ID: 11968908
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 6:
7. A device comprising:
a first memory cell comprising:
a first bottom electrode;
a first magnetic tunnel junction stack on the first bottom electrode; and
a first top electrode on the first magnetic tunnel junction stack, the first top electrode comprising first conductive layers and a first dielectric layer between the first conductive layers, the first dielectric layer having a first thickness;

a second memory cell comprising:
a second bottom electrode;
a second magnetic tunnel junction stack on the second bottom electrode; and
a second top electrode on the second magnetic tunnel junction stack, the second top electrode comprising second conductive layers and a second dielectric layer between the second conductive layers, the second dielectric layer having a second thickness, the second thickness less than the first thickness.