Patent ID: 11930665
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 7:
8. The display substrate according to claim 7, wherein
the planarization layer between the entire at least one conductive line layer and the pixel driving circuit in each second sub-pixel includes at least one first planarization layer; wherein
the first planarization layer includes one first planarization layer, the plurality of first blocking layers include a first first blocking layer arranged in a same layer as the first planarization layer, the plurality of second blocking layers include a first second blocking layer arranged in the same layer as the first planarization layer, and the at least one connection layer includes a first connection layer; and the first connection layer connects the first first blocking layer and the first second blocking layer; or
the first planarization layer includes two first planarization layers, the plurality of first blocking layers include a first first blocking layer arranged in a same layer as one first planarization layer of the two first planarization layers and a second first blocking layer arranged in another same layer as another first planarization layer of the two first planarization layers, the plurality of second blocking layers include a first second blocking layer arranged in the same layer as the one first planarization layer and a second second blocking layer arranged in the another same layer as the another first planarization layer, and the at least one connection layer includes a first connection layer and a second connection layer; and the first connection layer connects the first first blocking layer and the first second blocking layer, and the second connection layer connects the second first blocking layer and the second second blocking layer.