Patent ID: 11943925
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 14:
15. A semiconductor memory device comprising:
a plurality of first bit lines extending lengthwise in a first direction parallel to a top surface of a substrate and stacked in a second direction perpendicular to the top surface of the substrate;
a plurality of second bit lines extending lengthwise in the first direction and stacked in the second direction, the plurality of second bit lines spaced apart from the plurality of first bit lines in a third direction parallel to the top surface of the substrate and intersecting the first and second directions;
a plurality of source lines extending lengthwise in the second direction between the plurality of first bit lines and the plurality of second bit lines and spaced apart from each other in the first direction;
a plurality of first memory cells, each being provided at a corresponding one of a plurality of intersection points of the plurality of first bit lines and the plurality of source lines, wherein each of the plurality of first memory cells comprises a first semiconductor pattern including a first source region having a first conductivity type, a first drain region having a second conductivity type different from the first conductivity type, and a first channel region between the first source region and the first drain region;
a plurality of second memory cells, each being provided at a corresponding one of a plurality of intersection points of the plurality of second bit lines and the plurality of source lines, wherein each of the plurality of second memory cells comprises a second semiconductor pattern including a second source region having the first conductivity type, a second drain region having the second conductivity type, and a second channel region between the second source region and the second drain region;
a pair of first and second word lines surrounding each of a plurality of first channel regions of a plurality of first semiconductor patterns of the plurality of first memory cells and extending in the first direction and the second direction;
a plurality of first charge storage patterns, each surrounding a first channel region of a corresponding first semiconductor pattern of the plurality of first semiconductor patterns, and being disposed between the corresponding first semiconductor pattern and each of the pair of the first and second word lines;
a pair of third and fourth word lines surrounding each of a plurality of second channel regions of a plurality of second semiconductor patterns of the plurality of second memory cells and extending in the first direction and the second direction; and
a plurality of second charge storage patterns, each surrounding a second channel region of a corresponding second semiconductor pattern of the plurality of second semiconductor patterns, and being disposed between the corresponding second semiconductor pattern and each of the pair of the third and fourth word lines.