Patent ID: 11894067
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 1:
2. The memory apparatus as set forth in claim 1, wherein the control means further includes a read counter configured to count a block read quantity of the plurality of read operations of each of the plurality of blocks of the memory cells, the control means is further configured to:
initialize the block read quantity associated with the one of the plurality of blocks as zero,
receive a read request associated with one of the plurality of read operations,
read data in the one of the plurality of blocks and communicate the data,
increment the block read quantity by one,
determine whether the block read quantity is greater than a block read quantity threshold, and
conclude the memory apparatus is ready for a next read and return to receive the read request associated with one of the plurality of read operations in response to the block read quantity not being greater than the block read quantity threshold.