Patent ID: 11916782
Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Field: Digital communication (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A switch, comprising:
an output port;
an output buffer coupled to the output port that buffers packets of packet flows to be transmitted via the output port, wherein a respective packet flow includes packets with one or more common header fields and is identified by a flow identifier that is unique within an input port via which the packet flow is received;
an output buffer control logic block that allocates bandwidth of the output port based on a predetermined configuration among the packet flows, wherein the packet flows share the bandwidth of the output port with fairness based on the predetermined configuration;
an arbitration logic block that:
arbitrates among the number of packet flows based on the bandwidth allocated to a respective packet flow, and
selects a packet flow based on the arbitration for forwarding a packet from the output buffer; and

an input queue logic block that:
maintains state information for the respective packet flow by monitoring acknowledgment packets for packets of the respective packet flow transmitted via the output port, and
deallocates the flow identifier from the respective packet flow in response to receiving an acknowledgement packet for a last transmitted packet of the respective packet flow.