Patent ID: 11955559
Assignee: SAKAI DISPLAY PRODUCTS CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 8:
9. A method for manufacturing a thin film transistor, comprising:
forming a gate electrode on a substrate;
forming a gate insulating film to cover the gate electrode;
forming an amorphous silicon film on the gate insulating film;
forming a polysilicon layer in a first portion of the amorphous silicon film, while forming a first amorphous silicon layer in a second portion of the amorphous silicon film other than the first portion in the same layer as the polysilicon layer, by irradiating the first portion of the amorphous silicon film with energy beams, the first portion of the amorphous silicon film being located within a range defined by an outer edge of the gate electrode in a plan view;
forming an insulating film on the polysilicon layer and the first amorphous silicon layer, the insulating film serving as an etch stop layer;
forming the etch stop layer by removing a portion of the insulating film so that the polysilicon layer includes a first region and a second region each not covered with the etch stop layer; and
forming a source electrode and a drain electrode with a space therebetween so that a part of one of the source electrode and the drain electrode is located over the first region and a part of another one of the source electrode and the drain electrode is located over the second region.