Patent ID: 11948627
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 7:
8. A device, comprising:
an array of memory cells that comprises:
a lower portion with first memory cells having first bitlines; and
an upper portion with second memory cells having second bitlines longer than the first bitlines;

a write driver circuit configured to provide a reference voltage to the first and second memory cells via the first and second bitlines; and
a voltage generator circuit, comprising:
a first capacitive element;
a second capacitive element; and
a logic circuit configured to:
receive first row address information and second row address information associated with the first memory cells and the second memory cells, respectively; and
control a reference voltage provided to the first bitlines and the second bitlines,
wherein based on the first row address information, the logic circuit is configured to couple, via the first capacitive element, the reference voltage to a first negative voltage applied to the first bitlines of the first memory cells in the lower portion of the array of memory cells,
wherein based on the second row address information, the logic circuit is configured to couple, via the first and second capacitive elements, the reference voltage to a second negative voltage lower than the first negative voltage, and
wherein the second negative voltage is applied to the second bitlines of the second memory cells in the upper portion of the array of memory cells.