Patent ID: 11955979
Assignee: nan
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. Phase-locked loop circuitry comprising:
a phase frequency detector having a first input configured to receive a reference clock signal, a second input, and an output;
charge pump and loop filter circuitry having an input coupled to the output of the phase frequency detector and having an output;
a voltage-controlled oscillator having an input coupled to the output of the charge pump and loop filter circuitry and having an output;
a frequency divider having an input coupled to the output of the voltage-controlled oscillator and having an output coupled to the second input of the phase frequency detector;
a first order sigma delta modulator having an output, wherein the first order sigma delta modulator is non-dithered; and
a finite impulse response filter having an input coupled to the output of the first order sigma delta modulator and having an output coupled to the frequency divider.