Patent ID: 11916127
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A method for forming a memory device, comprising:
forming a multi-layer bottom electrode over a substrate, wherein the multi-layer bottom electrode comprises a first bottom electrode layer and a second bottom electrode layer over the first bottom electrode layer;
forming a ferroelectric switching layer on the multi-layer bottom electrode;
forming a multi-layer top electrode on the ferroelectric switching layer, wherein the multi-layer top electrode comprises a first top electrode layer and a second top electrode layer disposed between the first top electrode layer and the ferroelectric switching layer, wherein the first bottom electrode layer and the first top electrode layer comprise a first conductive material, and wherein the second bottom electrode layer and the second top electrode layer comprise a second conductive material different from the first conductive material; and
performing a baking process, wherein the second top electrode layer is configured to prevent oxidation of the first top electrode layer during the baking process.