Patent ID: 11875045
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. The method of claim 2, wherein the target bank comprises at least two logic storage regions, and each of the at least two logic storage regions comprises at least two consecutive physical storage regions; wherein the storage region to be trimmed in the target bank comprises at least two consecutive physical storage regions to be trimmed; and
wherein in response to determining that the density configuration parameter of the target bank comprises the physical storage regions to be trimmed in the target bank,
determining, based on the density configuration parameter of the target bank, the target code from the set of codes of the target bank comprises:
determining, based on the at least two consecutive physical storage regions to be trimmed in the target bank, a logic storage region to be trimmed from the at least two logic storage regions in the target bank; and
determining, based on the logic storage region to be trimmed, the target code from the set of codes of the target bank.