Patent ID: 11936384
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 11:
12. The multi-bit flip-flop of claim 1, wherein the second latch comprises:
a first inverter configured to receive the fifth data bit and output the sixth data bit;
a second inverter configured to receive the sixth data bit; and
a first transmission gate configured to transfer an output of the second inverter to an input of the first inverter in synchronization with the clock signal and the inverse clock signal, and
the fourth latch comprises
a third inverter configured to receive the tenth data bit and output the eleventh data bit;
a fourth inverter configured to receive the eleventh data bit; and
a second transmission gate configured to transfer an output of the fourth inverter to an input of the third inverter in synchronization with the clock signal and the inverse clock signal.