Patent ID: 11935612
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. The memory of claim 7, wherein the second sub-output circuit comprises:
a fifteenth transistor configured to enable a source to be electrically connected to the first voltage, a drain to be electrically connected to the second data line, and a gate to be electrically connected to the first voltage node;
a sixteenth transistor configured to enable a drain to be electrically connected to the drain of the fifteenth transistor, and a gate to be electrically connected to each of the first voltage node and the gate of the fifteenth transistor;
a seventeenth transistor configured to enable a drain to be electrically connected to a source of the sixteenth transistor, and a gate to be electrically connected to the second complementary data line;
an eighteenth transistor configured to enable a source to be grounded, a drain to be electrically connected to a source of the seventeenth transistor, and a gate to be electrically connected to a reset signal;
a nineteenth transistor configured to enable a source to be electrically connected to the first voltage, a drain to be electrically connected to the second data line, and a gate to be electrically connected to each of the second complementary data line and the gate of the seventeenth transistor; and
a twentieth transistor configured to enable a source to be electrically connected to the first voltage, a drain to be electrically connected to the second data line, and a gate to be electrically connected to each of the reset signal and the gate of the eighteenth transistor.