Patent ID: 11862287
Assignee: MACRONIX INTERNATIONAL CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device comprising:
a memory cell array comprising a plurality of memory cells;
a plurality of memory cell lines connecting respective lines of memory cells in the memory cell array; and
a page buffer circuit comprising a plurality of page buffers coupled to the plurality of memory cell lines, each page buffer comprising:
a sensing latch circuit comprising a sensing transistor coupled to a sensing node and at least one sensing latch unit having a first node coupled to the sensing node and a second node coupled to the sensing transistor, and
a storage latch circuit comprising at least one storage latch unit having third and fourth nodes coupled to the sensing node,
wherein the sensing transistor comprises a first terminal coupled to the second node of the at least one sensing latch unit, a gate terminal coupled to the sensing node and the third and fourth nodes of the at least one storage latch unit, and a second terminal coupled to a ground, and
wherein the sensing latch circuit comprises one or more sensing transistors that each are substantially same as the sensing transistor, wherein the sensing latch circuit comprises a plurality of sensing latch units, and wherein a number of the one or more sensing transistors is smaller than a number of the plurality of sensing latch units.