Patent ID: 11972814
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A memory device, comprising:
a plurality of memory cells, the plurality of memory cells including a first set of memory cells in a first set of planes or a first physical block and a second set of memory cells in a second set of planes or a second physical block;
a controller in communication with the memory cells and configured to, in a first programming pass and then a second programming pass, program the memory cells of the first and second sets to respective final threshold voltages associated with a plurality of programmed data states, the controller being further configured to:
in the first programming pass,
verify a first set of checkpoint data states of the first set of memory cells, wherein the first set of checkpoint data states is a first subset of the plurality of programmed data states, and skip verification of remaining programmed data states of the first set of memory cells, and
verify a second set of checkpoint data states of the second set of memory cells, wherein the second set of checkpoint data states is a second subset of the plurality of programmed data states that is different than the first set of checkpoint data states, and skip verification of remaining programmed data states of the second set of memory cells.