Patent ID: 11940940
Assignee: GRAPHCORE LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 2:
3. The data processing device of claim 1, wherein the first of the interfaces is associated with a first set of the processors for the first of the phases of execution, wherein each of the first set of the processors is configured to:
in dependence upon the schedule in its associated one of the local programs, control its associated switching circuitry to, during the first of the phases of execution of the computer program, connect to the first of the at least some of the buses so as to enable reception of the first set of the ingress data packets from the first of the interfaces; and
for each of the first set of the ingress data packets:
check a destination identifier in the respective data packet;
if the destination identifier indicates that the respective data packet is for delivery to that respective one of the first set of the processors, accept the respective data packet; and
if the destination identifier indicates that the respective data packet is not for delivery to that respective one of the first set of the processors, do not accept the respective data packet.