Patent ID: 11908509
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A system, comprising:
a controller coupled to a memory array, the controller configured to:
send a clock signal to the memory array;

the memory array operably coupled to at least one processor and configured to:
count a first number of input transitions of the clock signal for a set time period;
store in one or more sets of latches a count value of the first number of input transitions;
adjust an input bias level for a communication buffer after counting the first number of input transitions;
count a second number of input transitions of the clock signal for the set time period using the adjusted input bias level;
generate a comparison result based on the second number of input transitions and the first number of input transitions; and
send the comparison result to the controller.