Patent ID: 11915787
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. A method, comprising:
patterning a multilayer structure comprising at least one memory array layer, to obtain
an opening between a first portion and a second portion of the multilayer structure, and
a plurality of channels extending across the opening from the first portion to the second portion, the plurality of channels belonging to at least one active region layer in the at least one memory array layer;

depositing a memory film
over first and second walls of the opening correspondingly on the first and second portions of the multilayer structure, and
around each of the plurality of channels;

depositing a conductive material in the opening;
patterning the deposited conductive material to obtain a plurality of gate electrodes each individually around at least one corresponding channel among the plurality of channels; and
depositing an insulating material between adjacent gate electrodes among the plurality of gate electrodes.