Patent ID: 11899491
Assignee: BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 15:
16. A system for timing synchronization between two or more nodes in network architecture, the system comprising:
timestamp hardware to generate timestamps in data;
a physical hardware clock (PHC clock), wherein cycle counts of the PHC clock are transmitted between the PHC clock and the timestamp hardware;
a trigger pulse generator coupled to the PHC clock, wherein cycle counts of the PHC clock are transmitted between the PHC clock and the trigger pulse generator;
a physical layer driver (PHY driver) to process data packets and cycle counts;
an application coupled with the PHY driver to process timestamps and sync with the PHC clock;
a PHC synchronizer to synchronize the PHC clock with system time; and
a microprocessor coupled to the trigger pulse generator, wherein a pulse generated from the trigger pulse generator is transmitted from the trigger pulse generator to the microprocessor;
wherein the pulse transmitted from the trigger pulse generator to the microprocessor is based on a trigger interrupt at a trigger generator interrupt time.