Patent ID: 11907546
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G

Claim 8:
9. A method, comprising:
receiving, at a first memory device via a first interface, a first set of signals comprising data from a second memory device, the first set of signals modulated according to a first modulation scheme using a first quantity of voltage levels, wherein the first interface comprises a set of buffers for storing the data, wherein the first memory device is configured for access operations with a first array of memory cells and the second memory device is configured for access operations with a second array of memory cells;
storing the data at the first memory device based at least in part on receiving the first set of signals; and
transmitting, to a host device via a second interface, a second set of signals comprising the data based at least in part on receiving the data, the second set of signals modulated according to a second modulation scheme using a second quantity of voltage levels that is different than the first quantity of voltage levels, wherein the set of buffers is configured to support concurrent data management between the first memory device and the second memory device.