Patent ID: 11967504
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 8:
9. A method comprising:
removing a first dummy gate structure to form a recess around a first nanostructure and a second nanostructure;
depositing a sacrificial layer in the recess with a flowable chemical vapor deposition (CVD);
patterning the sacrificial layer to leave a portion of the sacrificial layer between the first nanostructure and the second nanostructure;
depositing a first work function metal in the recess;
removing the first work function metal and the portion of the sacrificial layer from the recess;
depositing a second work function metal in the recess, wherein the second work function metal is of an opposite type than the first work function metal; and
depositing a fill metal over the second work function metal in the recess.