Patent ID: 11960764
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. A method, comprising:
selecting a primary ready/busy pin (R/B #) among a plurality of R/B # pins that are associated with respective memory dice among a plurality of memory dice of a memory device;
setting the primary R/B # pin to low status;
receiving, by at least one memory die among the plurality of memory dice, signaling indicative of performance of a memory access for the primary R/B # pin;
receiving, by the at least one memory die among the plurality of memory dice, signaling indicative of performance of the memory access involving a first memory die among the plurality of memory dice;
receiving, by the at least one memory die among the plurality of memory dice, signaling indicative of performance of the memory access involving a second memory die among the plurality of memory dice;
initiating a first internal clocking signal subsequent to receipt of signaling indicative of completion of the performance of the memory access of the first memory die among the plurality of memory dice; and
initiating a second internal clocking signal subsequent to receipt of signaling indicative of completion of the performance of the memory access of the second memory die among the plurality of memory dice, wherein the first internal clocking signal and the second internal clocking signal are associated with timing of operations performed by the plurality of memory dice.