Patent ID: 11908856
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 9:
10. An integrated circuit structure, comprising:
a first vertical arrangement of horizontal nanowires above a first fin;
a first gate stack over the first vertical arrangement of horizontal nanowires;
a first pair of epitaxial source or drain structures at first and second ends of the first vertical arrangement of horizontal nanowires, one of the first pair of epitaxial source or drain structures directly electrically coupled to the first fin, and the other of the first pair of epitaxial source or drain structures electrically isolated from the first fin;
a second vertical arrangement of horizontal nanowires above a second fin;
a second gate stack over the second vertical arrangement of horizontal nanowires; and
a second pair of epitaxial source or drain structures at first and second ends of the second vertical arrangement of horizontal nanowires, both of the second pair of epitaxial source or drain structures electrically isolated from the second fin, wherein the second pair of epitaxial source or drain structures has a bottommost surface vertically between a bottommost nanowire of the second vertical arrangement of horizontal nanowires and an uppermost surface of the second fin.