Patent ID: 11860685
Assignee: ADVANCED MICRO DEVICES, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. An apparatus comprising:
a first clock divider circuit configured to:
receive a first input clock signal; and
generate a first output clock signal based on the first input clock signal; and

a second clock divider circuit configured to:
receive a second input clock signal, wherein the first input clock signal and the second input clock signal have an initial phase difference between them;
receive a first intermediate clock signal based on the first output clock signal;
receive a reset signal that is asserted asynchronously, in a given clock cycle of the second input clock signal, with respect to the second input clock signal; and
in response to assertion of the reset signal, generate, in the given clock cycle, a second output clock signal such that the first output clock signal and the second output clock signal have the initial phase difference between them.