Patent ID: 11868241
Assignee: CADENCE DESIGN SYSTEMS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A non-transitory computer readable storage medium for optimizing a verification regression session for testing a DUT in a corresponding verification environment, having stored thereon instructions that when executed by a processor will cause the processor to:
extract from data of previously executed runs of at least one verification regression session values of one or a plurality of control knobs selected from the group consisting of: selection or deselection of a specific test for inclusion in a regression, selection or deselection of specific units of the DUT for testing in a specific test and a controllable entity of the DUT or a testing environment of the DUT to be subjected to control conditions and values of one or a plurality of verification metrics that were recorded during the execution for each of the previously executed runs of said at least one verification regression session;
find correlation between said one or a plurality of the control knobs and each said one or a plurality of verification metrics, and generating a set of one or a plurality of control conditions based on the found correlation; and
apply the generated set of one or a plurality of control conditions on the verification environment or on the DUT, or on both, to obtain a new verification regression session,
wherein the set of one or a plurality of control conditions is selected so that when applied on the verification environment or on the DUT, or on both causes the new verification regression session to achieve one or a plurality of predetermined verification targets.