Patent ID: 11860812
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 10:
11. A system comprising:
an upstream port;
a downstream port coupled to the upstream port by one or more links compliant with a Peripheral Component Interconnect Express (PCIe) protocol, the downstream port comprising a transmission/reception settings register;
a nonvolatile memory;
the downstream port comprising downstream port logic to:
determine equalization parameter values for the one or more links interconnecting the upstream port with the downstream port for a plurality of data rates including a first data rate and a second data rate;
store the equalization parameter values in the nonvolatile memory;
operate the one or more links at the first data rate;
determine that the one or more links are to change from the first data rate to the second data rate;
determine that the upstream port and the downstream port support equalization bypass from information in a training set;
write equalization parameter values for the second data rate from the nonvolatile memory to the transmission/reception settings register of the downstream port; and
use the equalization parameter values to operate the one or more links.