Patent ID: 11908735
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A device comprising:
two gate structures disposed over a substrate, wherein one of the two gate structures is disposed between a first source/drain feature and a second source/drain feature;
a cobalt-containing contact disposed directly on the first source/drain feature, wherein the cobalt-containing contact includes a cobalt-containing bulk layer and the cobalt-containing contact is disposed in a first interlayer dielectric layer and a second interlayer dielectric layer;
a tungsten-containing via disposed directly on the cobalt-containing contact, wherein the tungsten-containing via is disposed in a third interlayer dielectric layer and the tungsten-containing via includes a tungsten-containing bulk layer;
a titanium-containing barrier layer that directly contacts the tungsten-containing bulk layer and the cobalt-containing contact; and
a copper-containing trace disposed directly on the tungsten-containing via, wherein the copper-containing trace is disposed in a fourth interlayer dielectric layer.