Patent ID: 11862236
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. A method of operation within an integrated-circuit memory component, the method comprising:
receiving a configuration value;
receiving a first command/address value that specifies a memory read access;
if the configuration value specifies a first operating mode:
decoding a first column address constituted by N bits of the first command/address value to retrieve a first quantity of data from a first one of 2N independently accessible columns of a page buffer; and
outputting the first quantity of data via a fixed-width data interface of the integrated-circuit memory component over Q successive data output intervals; and

if the configuration value specifies a second operating mode:
decoding a second column address constituted by M bits of the first command/address value to access a second quantity of data from a first one of 2M independently accessible columns of the page buffer, M being smaller than N and the second quantity of data exceeding the first quantity of data; and
outputting the second quantity of data via the fixed-width data interface over R successive data output intervals, R being greater than Q.