Patent ID: 11971741
Assignee: QUALCOMM INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 40:
41. A system, comprising:
a multiplexer having a first input, a second input, a select input, and an output;
a signal path having an input and an output, wherein the input of the signal path is coupled to the output of the multiplexer;
a latching circuit having a signal input, a clock input, and an output, wherein the signal input is coupled to the output of the signal path, the clock input of the latching circuit is configured to receive a clock signal, and the latching circuit is configured to latch a logic value at the signal input on an edge of the clock signal, and output the latched logic value at the output of the latching circuit; and
a controller coupled to the second input of the multiplexer and the select input of the multiplexer, wherein the controller has an indicator input, and the controller is configured to:
receive a mode indicator signal at the indicator input;
if the mode indicator signal has a first logic value, instruct the multiplexer to select the first input of the multiplexer; and
if the mode indicator signal has a second logic value, instruct the multiplexer to select the second input of the multiplexer, output a control signal to the second input of the multiplexer, set the control signal high for k of N consecutive idle periods, and set the control signal low for N−k of the N consecutive idle periods, wherein k is an integer equal to or greater than one, and N is an integer greater than k.