Patent ID: 11894477
Assignee: RAYTHEON COMPANY
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. The electrical device according to claim 4,
the electrical device further comprising a bonding layer including SiOx overlying at least a part of the substrate, the bonding layer having a CTE in a range from 0.6×10−6/K to 3.5×10−6/K;
wherein the fragile material is a photoconductor including Hg1-xCdxTe having a CTE in a range from 5.0×10−6/K to 5.6×10−6/K; and
wherein the stress buffer layer is configured to counteract forces imparted by a CTE mismatch between the bonding layer and the fragile material to thereby minimize strain in the fragile material or at an interface of the fragile material.