Patent ID: 11955165
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 9:
10. A memory module comprising:
a module substrate having a first module data port, a second module data port, and a third module data port;
first and second memory components each having a first memory-component data port and a second memory-component data port;
a first memory-component substrate having a first signal trace extending from the first module data port through the first memory-component substrate, a second signal trace extending between the second module data port and the first memory-component data port of the first memory component, and a third signal trace extending between the third module data port and the second memory-component data port of the first memory component; and
a second memory-component substrate having a fourth signal trace extending between the first signal trace of the first memory-component substrate and the first memory-component data port of the second memory component, and a fifth signal trace extending between the third signal trace of the first memory-component substrate and the second memory-component data port of the second memory component;
wherein the module substrate includes a first module-substrate side bearing the first, second, and third module data ports and a second module-substrate side bearing a fourth module data port, a fifth module data port, and a sixth module data port;
third and fourth memory components each having a first memory-component data port and a second memory-component data port;
a third memory-component substrate having a first signal trace extending from the fourth module data port through the third memory-component substrate, a second signal trace extending between the fifth module data port and the first memory-component data port of the third memory component, and a third signal trace extending between the sixth module data port and the second memory-component data port of the third memory component; and
a fourth memory-component substrate having a fourth signal trace extending between the first signal trace of the third memory-component substrate and the first memory-component data port of the fourth memory component, and a fifth signal trace extending between the third signal trace of the third memory-component substrate and the second memory-component data port of the fourth memory component.