Patent ID: 11934337
Assignee: ANHUI CAMBRICON INFORMATION TECHNOLOGY CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. A multi-chip system comprising a plurality of chips, each chip comprising a data bus, and a memory, a data receiver, a computing and processing unit, and a data transmitter connected to the data bus,
wherein the data receiver is configured to receive first data and header information from outside, write the first data to a corresponding area of the memory through the data bus, and configure a corresponding computing and processing unit and/or data transmitter according to the header information;
the computing and processing unit is configured to receive first task information, perform an operation processing according to the first task information, and perform a configuration operation on the data transmitter; and
the data transmitter is configured to obtain second task information and second data, and output third data to outside based on at least part of the second data,
wherein the data receiver includes
a first serial interface,
a data buffer configured to cache the first data from the first serial interface,
a decoder configured to parse a format and storage address of the first data according to the header information, segment the first data according to the format, and configure corresponding bits of the computing and processing unit and the data transmitter according to the header information, and
a DMA unit configured to receive the first data and the storage address from the decoder to write the first data into a corresponding area of the memory through the data bus.