Patent ID: 11915740
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 0:
1. An apparatus, comprising:
a plurality of pillars arranged in a two-dimensional array of a first quantity of pillars along a first direction and a second quantity of pillars along a second direction, each pillar of the plurality of pillars coupled with a respective plurality of memory cells;
a plurality of activation lines each operable to activate a respective set, having the second quantity of pillars, of the plurality of pillars along the second direction;
a plurality of first word lines each coupled with a respective memory cell of each pillar of a first subset of the plurality of pillars, the first subset arranged in a two-dimensional array of the first quantity of pillars along the first direction and a third quantity of pillars along the second direction and less than the second quantity of pillars;
a first word line driver operable to bias one of the plurality of first word lines;
a plurality of second word lines each coupled with a respective memory cell of each pillar of a second subset of the plurality of pillars, the second subset arranged in a two-dimensional array of the first quantity of pillars along the first direction and the third quantity of pillars along the second direction; and
a second word line driver operable to bias one of the plurality of second word lines.