Patent ID: 11860814
Assignee: KONDA TECHNOLOGIES INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A method for deterministic communication in a scalable distributed computing system comprising:
wherein said scalable distributed computing system further comprising an α×b processing elements arranged in a two dimensional grid with one side of said two dimensional grid having the size of α processing elements and the other side of said two dimensional grid having the size of b processing elements where α>2, b>2, and both α and b are non-negative numbers; and
Wherein said α×b processing elements are numbered with a representation in binary format having n bits, where 2n−1<α×b≤2n and where n is a positive number; and
Wherein said α×b processing elements are arranged in said two dimensional grid so that a first processing element of said α×b processing elements is placed 2k hops away either vertically or horizontally from a second processing element of said α×b processing elements when said all n bits of said representation in binary format of said first processing element and said representation in binary format of said second processing element are the same in each bit excepting in one of either (2×k+1)th least significant bit or (2×k+2)th least significant bit differ where k is a non-negative number; and
Wherein each processing element of said α×b processing elements arranged in said two dimensional grid connected to an interconnect comprising one or more 2k hop length horizontal buses and one or more 2k hop length vertical buses where k is a non-negative number; and
Wherein each horizontal bus of said one or more 2k hop length horizontal buses comprises one or more wires and each vertical bus of said one or more 2k hop length vertical buses comprises one or more wires; and
Wherein a switch of said one or more switches of a first processing element of said α×b processing elements is connected, by a 2k hop length horizontal bus of said one or more 2k hop length horizontal buses or a 2k hop length vertical bus of said one or more 2k hop length vertical buses, to a switch of said one or more switches of a second processing element of said α×b processing elements when said all n bits of said representation in binary format of said first processing element and said representation in binary format of said second processing element are the same in each bit excepting in one of either (2×k+1)th least significant bit or (2×k+2)th least significant bit differ where k is a non-negative number and also said switch of said one or more switches of said first processing element of said α×b processing elements is connected, by a 2k hop length horizontal bus of said one or more 2k hop length horizontal buses or a 2k hop length vertical bus of said one or more 2k hop length vertical buses, from said switch of said one or more switches of said second processing element of said α×b processing elements when if said all n bits of said representation in binary format of said first processing element and said representation in binary format of said second processing element are the same in each bit excepting in one of either (2×k+1)th least significant bit or (2×k+2)th least significant bit differ where k is a non-negative number so that said interconnect of each processing element of said α×b processing elements comprising said one or more 2k hop length horizontal buses connecting to said interconnect of one or more processing elements of said α×b processing elements and said interconnect of each processing element of said α×b processing elements comprising said one or more 2k hop length vertical buses connecting to said interconnect of one or more processing elements of said α×b processing elements; and
each processing element of said α×b processing elements further comprising one or more packets wherein each packet of said one or more packets comprises a data token and a length; and
said interconnect of each processing element of said α×b processing elements is capable of concurrently transmitting, in a clock speed of operation, one or more packets of said one or more packets through one or more horizontal buses of said one or more 2k hop length horizontal buses connected from said interconnect of each processing element of said α×b processing elements (source processing element) to a processing element of said α×b processing elements (target processing element) and also through one or more vertical buses of said one or more 2k hop length vertical buses connected from said interconnect of each processing element of said α×b processing elements (source processing element) to a processing element of said α×b processing elements (target processing element); and
said method for deterministic communication further comprising:
performing concurrent broadcast of each packet of said one or more packets from each source processing element of said α×b processing elements to target processing elements of all the rest of said α×b processing elements in a plurality of deterministic number of time steps through said one or more 2k hop length horizontal buses or said one or more 2k hop length vertical buses; and
wherein said each packet of said one or more packets traverses through one or more processing element of said α×b processing elements (intermediate processing element) when said source processing element of said α×b processing elements and said target processing element of said α×b processing elements are not directly connected by one of either said one or more 2k hop length horizontal buses or said one or more 2k hop length vertical buses; and
wherein duration of each time step of said plurality of deterministic number of time steps is determined by the length of said of said one or more packets, the hop length of said one or more 2k hop length horizontal buses, the hop length of said one or more 2k hop length vertical buses, the number of wires in each bus of said one or more 2k hop length horizontal buses, the number of wires in each bus of said one or more 2k hop length vertical buses, a implemented non-transitory medium of said one or more 2k hop length horizontal buses or said one or more 2k hop length vertical buses, and said clock speed of operation; and
wherein said concurrent broadcast of each packet of said one or more packets of each processing element of said α×b processing elements is performed in a non-blocking, collision-free or without requiring to queue at the one or more intermediate processing elements of said α×b processing elements.