Patent ID: 11916032
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 14:
15. A memory device, comprising:
a first die comprising:
a memory array region comprising vertical stacks of memory cells;
a stack structure comprising alternating conductive structures and insulative structures intersecting the vertical stacks of memory cells, horizontal edges of the alternating conductive structures and insulative structures defining steps of a staircase structure;
conductive pillar structures vertically extending through access devices of the memory array region; and
global digit lines vertically underlying the vertical stacks of memory cells and extending from a conductive contact exit region at a first horizontal end of the memory array region to an additional conductive contact exit region at a second horizontal end of the memory array region opposite the first horizontal end of the memory array region;

a second die bonded to the first die, the second die comprising:
a sub word line driver vertically overlying the staircase structure of the first die, the staircase structure of the first die within a horizontal area of the sub word line driver; and
sense amplifier regions comprising one or more sense amplifiers vertically overlying the conductive contact exit region and the additional conductive contact exit region; and

conductive contacts vertically extending between the sense amplifier regions and each of the conductive contact exit region and the additional conductive contact exit region.