Patent ID: 11963362
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A semiconductor device comprising:
a peripheral circuit structure comprising a first substrate and circuit elements on the first substrate;
a memory cell structure comprising a second substrate on the first substrate, a first horizontal conductive layer extending on the second substrate, a horizontal insulating layer extending in parallel with the first horizontal conductive layer, a second horizontal conductive layer on the first horizontal conductive layer, gate electrodes spaced apart from each other and stacked on the second horizontal conductive layer in a first direction, wherein the first and second horizontal conductive layers are distinct from the gate electrodes, channel structures extending through the gate electrodes in the first direction and each comprising a channel layer, and separation regions penetrating the gate electrodes, extending in a second direction different than the first direction, and spaced apart from each other in a third direction different from the first and second directions; and
a through-wiring region between first separation regions among the separation regions, the through-wiring region comprising a through-contact plug extending in the first direction and electrically connecting one or more elements of the memory cell structure and one or more of the circuit elements of the peripheral circuit structure,
wherein the first separation regions are adjacent to the through-contact plug in the third direction,
wherein the first separation regions extend through the second horizontal conductive layer and are spaced apart from the first horizontal conductive layer,
wherein the second horizontal conductive layer conformally extends on respective top surfaces and end portions of the horizontal insulating layer at opposing sides of the first separation regions, and contacts the second substrate between the respective end portions of the horizontal insulating layer to define respective support regions, and
wherein the support regions are free of the first horizontal conductive layer and the horizontal insulating layer.