Patent ID: 11963345
Assignee: NANYA TECHNOLOGY CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor structure, comprising:
a substrate defined with an active region;
a first gate structure disposed in the active region;
a second gate structure disposed in the active region adjacent to the first gate structure; and
a fin structure having a first top surface arranged to alternate with the first gate structure and the second gate structure,
wherein the first gate structure and the second gate structure each comprises a filled dielectric material to define a second top surface of the first gate structure and a third top surface of the second gate structure respectively;
wherein the second top surface and the third top surface are lower than the first top surface,
wherein a width of the first gate structure is smaller than a width of the second gate structure,
wherein the third top surface is lower than the second top surface, wherein at least one of the second top surface or the third top surface is a non-flat surface.