Patent ID: 11894103
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 10:
11. The apparatus of claim 1, further comprising:
a plurality of first rows of pillars each comprising two or more first pillars and two or more second pillars; and
a plurality of second rows of pillars each comprising two or more first pillars and two or more second pillars, each second row of pillars interposed between a corresponding set of two first rows of pillars, wherein the plurality of first rows of pillars comprises a first logical page and the plurality of second rows of pillars comprises a second logical page, the first logical page for accessing a first subset of the plurality of first memory cells and a first subset of the plurality of second memory cells, and the second logical page for accessing a second subset of the plurality of first memory cells and a second subset of the plurality of second memory cells.