Patent ID: 11881853
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A true complement dynamic circuit for combining, in particular comparing, binary data on dynamic first and second input signals to third and fourth input signals, comprising:
at least a 1-bit compare circuit, wherein a first input signal and a second input signal are dynamic signals, the dynamic first and second input signals are complementary signals during an evaluation phase, at least the first input signal and the second input signal are restored to ‘1’ signals or restored to ‘0’ signals, respectively, during a precharge phase, and the dynamic first and second input signals are complementary signals during an evaluation phase;
wherein a logical behavior is determined by a third input signal and a fourth input signal, the third and fourth input signals being static signals or dynamic signals.