Patent ID: 11960728
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. A method of interfacing a plurality of memory dies, comprising:
receiving at least one of a first address and a first chip selection signal;
selecting, based on the at least one of the first address and the first chip selection signal, a first register of a plurality of registers corresponding to the plurality of memory dies, respectively;
providing, based on first information stored in the first register, a first data operation control signal to a first memory die corresponding to the first register;
receiving a second data operation control signal, at least one of a second address and a second chip selection signal;
selecting, based on the at least one of the second address and the second chip selection signal, a second register of the plurality of registers; and
storing, based on the second data operation control signal, second information in the second register,
wherein the selecting the second register comprises providing, based on the at least one of the second address and the second chip selection signal, a second control signal to a demultiplexer connected to the plurality of registers.