Patent ID: 11863178
Assignee: INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC G  H

Claim 0:
1. A method for detecting properness of a Power-Good pin (PG pin) power-on timing sequence, comprising:
obtaining a pull-up level of a PG pin of a Voltage Regulator chip (VR chip);
determining a value of a pull-up resistor of the PG pin, as a first resistance, when a current injected into the VR chip by using the pull-up level is equal to a maximum withstand current of the VR chip;
obtaining an equivalent resistance to ground when the PG pin is at a low level, and calculating, based on the equivalent resistance to ground, a value of the pull-up resistor of the PG pin, as a second resistance, when an output voltage of the PG pin is equal to a preset interference voltage limit value; and
outputting, when it is determined that an actual resistance of the pull-up resistor is lower than the first resistance or the second resistance, first prompt information for indicating that a resistance of the pull-up resistor is improper and that the PG pin power-on timing sequence has a hidden danger.