Patent ID: 11916559
Assignee: SAMBANOVA SYSTEMS, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. A method to lock a phase output signal to a phase input signal, comprising:
in a delay line with a delay line signal input and a speed control input, receiving the phase input signal at the delay line signal input and delaying the phase input signal to obtain a first delayed signal, a second delayed signal, and the phase output signal;
in a gater, copying the first delayed signal apart from a first pulse to output a first gater output signal, and copying the second delayed signal to output a second gater output signal;
in a phase-frequency detector (PFD), asserting a first PFD output signal when the PFD receives a first gater output signal, asserting a second PFD output signal when the PFD receives a second gater output signal, and deasserting the first PFD output signal and the second PFD output signal when both the first gater output signal and the second gater output signal are asserted;
in a loop filter, generating a speed control signal from the first PFD output signal and the second PFD output signal, wherein either (i) the speed control signal increases when the loop filter receives a first PFD output signal and decreases when the loop filter receives a second PFD output signal; or (ii) the speed control signal decreases when the loop filter receives a first PFD output signal and increases when the loop filter receives a second PFD output signal; and
in the delay line, changing the delay speed based on the speed control signal, wherein either the delay speed increases when the second delayed signal lags the first delayed signal and decreases when the second delayed signal leads the first delayed signal.