Patent ID: 11861370
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus, comprising:
a non-volatile memory device;
a volatile memory device; and
a controller coupled with the non-volatile memory device and the volatile memory device and configured to cause the apparatus to:
record a first phase of a first boot-up procedure and a second phase of the first boot-up procedure;
detect that the first phase of a second boot-up procedure is occurring, wherein the second boot-up procedure occurs after the first boot-up procedure;
transfer, from a first logical block address of the non-volatile memory device to the volatile memory device, first information for the first phase of the second boot-up procedure based at least in part on the recording of the first phase of the first boot-up procedure and in response to detecting that the first phase of the second boot-up procedure is occurring;
receive a first command to transmit the first information to a host system as part of the first phase of the second boot-up procedure after transferring the first information from the non-volatile memory device to the volatile memory device;
detect that the second phase of the second boot-up procedure is occurring;
transfer, from a second logical block address of the non-volatile memory device to the volatile memory device, second information for the second phase of the second boot-up procedure based at least in part on the recording of the second phase of the first boot-up procedure and in response to detecting that the second phase of the second boot-up procedure is occurring; and
receive a second command to transmit the second information to the host system as part of the second phase of the second boot-up procedure after transferring the second information from the non-volatile memory device to the volatile memory device.