Patent ID: 11934654
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. A method of operation in a memory device, the method comprising:
storing data in an array of storage cells organized into multiple banks;
configuring the memory device to generate hidden refresh commands on-die during a hidden refresh mode of operation;
receiving commands from a host memory controller to start a memory access operation with at least one selected bank from the multiple banks, the memory access operation occurring during a memory access interval;
performing a hidden refresh operation to at least one idle bank of the multiple banks during a designated hidden refresh interval that at least partially overlaps the memory access interval;
notifying the host memory controller of any corrective action following the performing of the hidden refresh operation;
for a non-hidden refresh mode, a first timing interval between an Activate command and a corresponding memory access command is of a first duration;
for the hidden refresh mode, a second timing interval between the Activate command and the corresponding memory access command is of a second duration longer than the first duration; and
wherein the designated hidden refresh interval is based on the second timing interval.