Patent ID: 11935586
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. The memory device of claim 7, further comprising a plurality of word lines, wherein
the plurality of rows in the memory array comprises first rows of the first memory cells, second rows of the second memory cells, third rows of the third memory cells, and fourth rows of the fourth memory cells,
the first through fourth rows are alternately arranged along the column direction, and
the plurality of word lines comprises:
at least one first word line coupled to the first memory cells in one of the first rows and the second memory cells in an adjacent one of the second rows, and
at least one second word line coupled to the third memory cells in one of the third rows and the fourth memory cells in an adjacent one of the fourth rows.