Patent ID: 11907549
Assignee: QUALCOMM INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. A system for allocating data structures to a plurality of processing nodes, each processing node having a respective local memory, the system comprising: a first processor; and a first memory in electrical communication with the first processor, the first memory comprising instructions which, when executed by a processing unit comprising at least one of the first processor and a second processor, and in electronic communication with a memory module comprising at least one of the first memory and a second memory, program the processing unit to: select as a first data structure of a set of data structures, a data structure having a read-write ratio greater than a read-write threshold; compute a respective value of a memory access parameter for each data structure of the set of data structures; compute a first duplication factor for the first data structure by optimizing a function of a value of a memory access parameter corresponding to the first data structure, subject to a memory capacity constraint based on a number N of processing nodes, N being greater than one; and generate a first statement allocating different portions of the first data structure duplicated by the first duplication factor, across the plurality of processing nodes, wherein the first value of the memory access parameter, corresponding to the first data structure, comprises a first correction factor based on an association between the first data structure and a first processing node of the plurality of processing nodes.