Patent ID: 11889413
Assignee: NEW YORK UNIVERSITY
Field: Telecommunications (Electrical engineering)
Classification: CPC H  Y | IPC H

Claim 12:
13. An apparatus according to claim 12, wherein:
the first duration is a first determined first duration and the second duration is a first determined second duration,
the instance of the switched architecture reception process is a first instance of the switched architecture reception process,
the processor is further configured to perform a timing synchronized second instance of the switched architecture reception process, and a timing synchronized third instance of the switched architecture reception process, each using said first duration that is based on the first determined first duration value, and using said second duration that is based on the first determined second duration value, wherein:
the timing synchronized second instance of the switched architecture reception process temporally aligns, based at least in part on the determined periodicity, the first duration with one or more of the control slots, or one or more of the synchronization slots, or both, of an (n+2)th subframe immediately succeeding the (n+1)th subframe and the second duration with data slots of the (n+2)th subframe, and
the timing synchronized third instance of the switched architecture reception process temporally aligns, based at least in part on the determined periodicity, the first duration with one or more of the control slots, or one or more of the synchronization slots, or both, of an (n+3)th subframe immediately succeeding the (n+2)th subframe and the second duration with data slots of the (n+3)th subframe, wherein n is an integer.