Patent ID: 11925022
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 7:
8. A semiconductor device, comprising:
a tiered material structure comprising an insulative material interleaved with a conductive material;
a vertical structure extending through the tiered material structure, the vertical structure comprising:
a charge-blocking material along a sidewall of the tiered material structure;
a charge storage material along a sidewall of the charge-blocking material;
a tunneling structure along a sidewall of the charge storage material, the tunneling structure comprising:
a first portion comprising a high-κ material; and
a second portion above the first portion, the second portion consisting essentially of an oxide material and being substantially free of the high-κ material,
an entirety of the high-κ material of the first portion being elevationally below the second portion; and

a channel structure along a sidewall of the tunneling structure, the channel structure comprising:
a first channel portion along a sidewall of the first portion of the tunneling structure; and
a second channel portion along a sidewall of the second portion of the tunneling structure,
a channel material of the first channel portion differing in at least one of thickness, horizontal outer dimension, and composition from a channel material of the second channel portion.