Patent ID: 11901035
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 5:
6. The system of claim 3, wherein:
each of the core dies of the HBM is arranged in channels;
the first set of one or more of the memory cells is contained within at least a first bundle of one or more of the channels;
the second set of one or more of the memory cells is contained within at least a second bundle of one or more of the channels;
in terms of membership, the first and second bundles are non-overlapping of each other; and
the DDVFS device is further configured to perform the following:
adjusting the first clock or the first PS voltage of the first bundle resulting in a first channel-wide adjustment of temperatures amongst the memory cells of the channels of the first bundle; and
adjusting the second clock or the second PS voltage of the second bundle resulting in a second channel-wide adjustment of temperatures amongst the memory cells of the channels of the second bundle.