Patent ID: 11901364
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 7:
8. A semiconductor device structure, comprising:
a first plurality of semiconductor layers disposed at a first location of the semiconductor device structure;
a second plurality of semiconductor layers disposed at a second location of the semiconductor device structure, wherein the semiconductor layers of the second plurality of semiconductor layers are disposed at same levels as corresponding semiconductor layers of the first plurality of semiconductor layers;
a third plurality of semiconductor layers disposed at a third location of the semiconductor device structure, wherein the semiconductor layers of the third plurality of semiconductor layers are disposed at same levels as corresponding semiconductor layers of the second plurality of semiconductor layers;
a first source/drain epitaxial feature in contact with a first number of semiconductor layers of the first plurality of semiconductor layers, wherein the first source/drain epitaxial feature has a first height;
a first dielectric material disposed over the first source/drain epitaxial feature, wherein the first dielectric material is disposed adjacent a second number of semiconductor layers of the first plurality of semiconductor layers;
a second source/drain epitaxial feature disposed over the first dielectric material, wherein the second source/drain epitaxial feature is in contact with a third number of semiconductor layers of the first plurality of semiconductor layers;
a third source/drain epitaxial feature in contact with a fourth number of semiconductor layers of the second plurality of semiconductor layers, wherein the third source/drain epitaxial feature has a second height different from the first height;
a second dielectric material disposed over the third source/drain epitaxial feature, wherein the second dielectric material is disposed adjacent a fifth number of semiconductor layers of the second plurality of semiconductor layers; and
a fourth source/drain epitaxial feature disposed over the second dielectric material, wherein the fourth source/drain epitaxial feature is in contact with a sixth number of semiconductor layers of the second plurality of semiconductor layers.