Patent ID: 11954356
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. A system comprising:
a memory to store memory pages;
one or more processor to access the memory pages stored in the memory by issuing access requests to the memory;
a cache to track recent accesses made by the one or more processors to the memory pages, wherein a page index bitmap is to maintain a list of all accesses made by the one or more processors to the memory pages in a given time frame, the page index bitmap to receive from cache updates, responsive to one or more criteria being met, based on the tracked recent accesses, wherein the list of all accesses is usable to identify infrequently accessed memory pages;
a secondary storage unit to store the infrequently accessed memory pages removed from the memory;
wherein the memory comprises a plurality of memory modules, each of the plurality of memory modules storing a portion of the page index bitmap, and wherein the apparatus further comprises storage to store one or more interleave rules, the one or more interleave rules usable for determining which of the plurality of memory modules stores the portion of the page index bitmap that is to store the tracked recent accesses.