Patent ID: 11922566
Assignee: IMAGINATION TECHNOLOGIES LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. Coarse depth test hardware configured to perform coarse depth testing in a graphics processing system in which a rendering space is subdivided into a plurality of tiles, the coarse depth test hardware comprising:
hidden depth test logic configured to:
receive a set of one or more primitives related to one of the plurality of tiles,
obtain a depth range for the tile, the depth range for the tile identifying a depth range based on primitives previously processed for the tile,
for at least one primitive in the set of one or more primitives:
determine, based on the depth range for the tile, whether all of the primitive is hidden in the tile,
in response to determining that all of the primitive is hidden in the tile, discard the primitive, and
in response to determining that all of the primitive is not hidden in the tile, output the primitive; and

front depth test logic configured to:
receive one or more primitive fragments generated from the primitives output by the hidden depth test logic,
for at least one received primitive fragment:
determine, based on the depth range for the tile, whether the primitive fragment has better depth than the primitives previously processed for the tile according to a depth compare mode, and
in response to determining that the primitive fragment has better depth than the primitives previously processed for the tile, identify the primitive fragment as not requiring a read of a depth buffer to perform full resolution depth testing.