Patent ID: 11962326
Assignee: ACCELERCOMM LIMITED
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A method for LDPC decoding in an electronic device comprising two or more check node, CN, sub-processors, the method comprising:
deriving a parity check matrix, PCM, from a basegraph selected from a set comprising at least one basegraph having a plurality of rows;
performing a series of low density parity check, LDPC, decoding operations for the PCM;
activating a subset of one or more input/output, I-O, ports of the two or more CN sub-processors based on a current LDPC decoding sub-step of the LDPC decoding operations and the at least one basegraph;
independently controlling an activation and a rotation of each rotator of two or more rotators by a controller;

supporting a connection of I-O ports of the CN sub-processors to incomplete subsets of the two or more rotators;
rotating an order of two or more soft bit values when activated in an LDPC decoding sub-step;
grouping sub-steps in each LDPC decoding operation into a first set and a second set, and wherein:
activating a subset of the two or more rotators, in each sub-step, corresponding to a subset of the two or more columns that have a binary value of ‘1’ in the row(s) of the at least one basegraph; and

activating connections within the interconnection network to connect the activated rotators to corresponding I-O ports of the CN sub-processors;
configuring the two or more CN sub-processors in a first mode of operation in a single LDPC decoding operation to perform LDPC decoding computations for different orthogonal rows of the plurality of rows in the at least one basegraph, wherein each CN sub-processor performs LDPC decoding computations for two rows of the PCM that are derived from the respective different orthogonal row of the plurality of rows in the at least one basegraph; and
configuring the two or more CN sub-processors in a second mode of operation in a single LDPC decoding operation to co-operate to perform LDPC decoding computations for a single row in the at least one basegraph, wherein the two or more CN sub-processors co-operate to perform the LDPC decoding computations for two rows of the PCM that are derived from the single row in the at least one basegraph.