Patent ID: 11894236
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. The method for manufacturing the semiconductor structure of claim 1, wherein, forming the first mask layers and the sidewall layers comprises:
forming a second mask layer on the base, wherein the second mask layer is provided with multiple discrete third vias;
forming first sidewall layers on side walls of the third vias, wherein the first sidewall layers define the second vias;
after forming the first sidewall layers, removing the second mask layer;
after removing the second mask layer, forming the first mask layers filling the second vias; and
after forming the first mask layers, forming second sidewall layers on the side walls, away from the first mask layers, of the first sidewall layers, wherein each second sidewall layer is connected to closest second sidewall layers, and the side walls, away from the first mask layers, of the multiple connected second sidewall layers define the initial first vias; and the first sidewall layers and the second sidewall layers constitute the sidewall layers.