Patent ID: 11880300
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 3:
4. The memory controller of claim 3, wherein the operations further comprise:
maintaining a plane vector for each of the planes including a value for each of the lanes to a plane indicating whether the plane is valid for each of the lanes;
maintaining a super plane vector including a value for each of the lanes comprising an OR of the values for the planes for each of the lanes indicating which lanes have at least one valid plane,
wherein the determining the valid planes for each lane comprises:
determining whether the super plane vector indicates there is at least one valid plane for the lane; and
processing the plane vectors to determine the valid planes for the lane in response to determining that the super plane vector indicates there is at least one valid plane for the lane, wherein a multi-plane read is directed to the page to read to each valid plane indicated in the plane vectors for a lane indicated in the super plane vector as having a valid plane on that lane.