Patent ID: 11915741
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A system, comprising:
a logic component; and
a plurality of memory components coupled with the logic component;
wherein each of the plurality of memory components comprise a respective plurality of partitioned banks, each bank comprising:
an array of memory cells;
sensing circuitry coupled to the array and configured to perform operations on the respective bank; and
timing circuitry coupled to the array and the sensing circuitry and is responsible for conflict free access to the respective array of memory cells;

wherein the logic component comprises:
a first control logic coupled to a first plurality of timing circuitries, sequencers, and sensing circuitry respectively of a first group of partitioned banks of the plurality of memory components that form a first processing in memory (PIM) device, wherein at least two partitioned banks of the first group are on different memory components; and
a second control logic coupled to a second plurality of timing circuitries, sequencers, and sensing circuitry respectively of a second group of partitioned banks of the plurality of memory components that form a second PIM device.