Patent ID: 11870441
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: nan (nan)
Classification: CPC nan | IPC G  H

Claim 5:
6. The clock gating circuit of claim 1, the cross-coupled pair of transistors comprises:
a second transistor of the first type, the second transistor including a second gate terminal, a second drain terminal and a second source terminal, the second gate terminal being configured to receive the clock output signal, and the second source terminal being coupled to the reference voltage supply; and
a third transistor of the first type, the third transistor being configured to adjust the clock output signal responsive to the second control signal, the third transistor including a third gate terminal, a third drain terminal and a third source terminal, the third gate terminal being configured to receive the second control signal, the third source terminal being coupled to the reference voltage supply,
wherein each of the second gate terminal, the third drain terminal, the first drain terminal and the output node are coupled together, and
each of the third gate terminal, the second drain terminal, the transmission gate and the second node are coupled together.