Patent ID: 11955986
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 18:
19. A comparator circuit comprising:
an input circuit configured to generate an amplified input signal through a sampling node by alternately selecting a positive input voltage and a negative input voltage during an equalizing period and a sampling period;
a first inverting amplification circuit configured to generate an intermediate amplified signal by performing an inversion and amplification operation based on the amplified input signal during the sampling period;
a second inverting amplification circuit configured to generate a comparison result signal by performing an inversion and amplification operation based on the intermediate amplified signal during the sampling period;
a first coupling circuit connected between the input circuit and an input node of the first inverting amplification circuit;
a second coupling circuit connected between an output node of the first inverting amplification circuit and an input node of the second inverting amplification circuit; and
a feedback circuit configured to amplify the input node of the first inverting amplification circuit with a rail-to-rail voltage corresponding to a power supply voltage or a ground voltage based on the comparison result signal during the sampling period,
wherein the comparator circuit has a differential structure to generate a complementary pair of a positive comparison result signal and a negative comparison result signal,
wherein the first inverting amplification circuit includes:
a first positive inverter connected between a first positive node corresponding to a first input node of the first inverting amplification circuit and a second positive node corresponding to a first output node of the first inverting amplification circuit; and
a first negative inverter connected between a first negative node corresponding to a second input node of the first inverting amplification circuit and a second negative node corresponding to a second output node of the first inverting amplification circuit, wherein the second inverting amplification circuit includes:
a second positive inverter connected between a third positive node corresponding a first input node of the second inverting amplification circuit and a fourth positive node corresponding to a first output node of the second inverting amplification circuit, the fourth positive node generating the positive comparison result signal; and
a second negative inverter connected between a third negative node corresponding to a second input node of the second inverting amplification circuit and a fourth negative node corresponding to a second output node of the second inverting amplification circuit, the fourth negative node generating the negative comparison result signal, and wherein the second inverting amplification circuit includes:
a first latching switch configured to electrically connect the fourth positive node and the third negative node based on a latch signal that is activated during the sampling period; and
a second latching switch configured to electrically connect the fourth negative node and the third positive node based on the latch signal.