Patent ID: 11973025
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A three-dimensional semiconductor memory device, comprising:
a peripheral circuit structure; and
a cell array structure on the peripheral circuit structure,
wherein the peripheral circuit structure includes
a first lower wiring on a substrate,
a second lower wiring on the substrate, the second lower wiring isolated from direct contact with the first lower wiring in a horizontal direction, the second lower wiring adjacent to the first lower wiring in the horizontal direction,
a stopping insulating layer on both the first lower wiring and the second lower wiring, the stopping insulating layer on an upper surface of the first lower wiring and an upper surface of the second lower wiring, the stopping insulating layer exposing the second lower wiring,
a first support via on the stopping insulating layer, such that a bottom surface of the first support via is on an upper surface of the stopping insulating layer and at least partially overlapping the first lower wiring in a vertical direction that is perpendicular to the horizontal direction, the first support via not contacting the first lower wiring,
a contact via on the second lower wiring and at least partially overlapping the second lower wiring in the vertical direction, the contact via contacting the second lower wiring through a via hole in the stopping insulating layer, and
an upper wiring on the contact via, the upper wiring contacting the contact via.