Patent ID: 11934263
Assignee: AMPERE COMPUTING LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory control circuit configured to:
receive a codeword comprising:
a first block comprising:
a first data portion;
metadata bits comprising codeword information; and
parity bits; and

a second block comprising:
a second data portion;
a first error correction code (ECC) symbol; and
a second ECC symbol,

wherein the first block and the second block comprise a same number of bits;

determine whether the second block comprises one or more bit error(s) based on the first ECC symbol and the second ECC symbol; and
in response to determining the second block comprises the one or more bit error(s), correct the bit error(s);
determine whether the first block comprises one or more parity error(s) based on the parity bits; and
in response to determining the first block comprises the one or more parity error(s), generate a request for a corrective action.