Patent ID: 11948619
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 7:
8. A controller device to control a dynamic random access memory (DRAM) device, the controller device comprising:
a transmitter to provide a clock signal to the DRAM device;
an interface to transmit commands to a command interface of the DRAM device, the commands including:
a first command to specify storage, in a first mode register, of first parameter information associated with operation of the command interface at a first clock frequency of the clock signal; and
a second command to specify storage, in a second mode register, of second parameter information associated with operation of the command interface at a second clock frequency of the clock signal; and
the interface to issue, to the command interface of the DRAM device, a third command that indicates changing a frequency of the clock signal from the first clock frequency to the second clock frequency, wherein, in association with the third command, a power mode of the DRAM device is changed, and wherein the command interface is to issue a fourth command using the clock signal at the second clock frequency after the power mode of the DRAM device is changed.