Patent ID: 11930696
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A method comprising:
forming an isolation layer over and contacting a semiconductor substrate;
forming an etch stop layer over the isolation layer;
forming a dielectric layer over the etch stop layer;
forming a plurality of carbon nanotubes over and contacting a first portion and a second portion of the dielectric layer;
forming a dummy gate stack over the dielectric layer and the plurality of carbon nanotubes;
removing the dummy gate stack through etching to reveal the plurality of carbon nanotubes, wherein the etching stops on the etch stop layer;
forming a gate stack extending into a space left by the dummy gate stack that has been removed, wherein the gate stack further extends between the first portion and the second portion of the dielectric layer, wherein the gate stack comprises:
a gate dielectric encircling portions of the plurality of carbon nanotubes, wherein the portions of the plurality of carbon nanotubes are between the first portion and the second portion of the dielectric layer; and
a gate electrode surrounding a combined region of the plurality of carbon nanotubes and the gate dielectric, wherein the gate electrode comprises an upper portion overlapping the combined region, and a lower portion overlapped by the combined region.