Patent ID: 11909565
Assignee: CADENCE DESIGN SYSTEMS, INC.
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A method of calibrating a decision feedback equalization (DFE) coefficient of a receiver, comprising:
(a) finding a first sample timing of a slicer that corresponds to a first eye center;
(b) providing a first data pattern and a second data pattern to an input of the receiver;
(c) iteratively varying a reference voltage of the slicer and sweeping a value of the DFE coefficient to measure a plurality of first eye boundaries and a plurality of second eye boundaries corresponding to a plurality of reference voltage values;
(d) based on the plurality of first eye boundaries and the plurality of second eye boundaries, determining a reference voltage value that maximizes a difference between a corresponding first eye boundary and second eye boundary;
(e) while the receiver is using the reference voltage value that maximizes the difference between the corresponding first eye boundary and second eye boundary, finding a second sample timing of the slicer that corresponds to a second eye center; and
(f) repeating steps (b) through (e) for a number of iterations.