Patent ID: 11862575
Assignee: SK HYNIX INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 18:
19. The semiconductor device of claim 16,
wherein the first seal-ring includes:
a first doped region formed inside an upper substrate; and
a multilayer of first wiring patterns and a plurality of first via patterns formed inside an upper interlayer insulating layer on the upper substrate,
wherein the first doped region and the first wiring patterns extend parallel to each other in a horizontal direction,
wherein the second seal-ring includes:
a second doped region formed inside the upper substrate; and
a multilayer of second wiring patterns and a plurality of second via patterns formed inside the upper interlayer insulating layer,
wherein the second doped region and the second wiring patterns extend parallel to each other in a horizontal direction, and
wherein the crack detection ring includes:
a crack detection doped region formed inside the upper substrate; and
a multilayer of crack detection pad patterns and a plurality of crack detection via patterns formed inside the upper interlayer insulating layer,
wherein the plurality of controllers and the plurality of operators are formed on a lower substrate.