Patent ID: 11955159
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 16:
17. A memory system comprising:
a semiconductor memory device including a memory cell array that includes a plurality of memory cell rows, each including a plurality of memory cells; and
a memory controller configured to control the semiconductor memory device,
wherein the memory controller is configured to apply an active command and a subsequent command to the semiconductor memory device such that the semiconductor memory device is configured to:
count a number of times of access associated with each of the plurality of memory cell rows in response to the active command to store the counted values in each of the plurality of memory cell rows,
manage a row hammer event of each of the plurality of memory cell rows based on the counted values, and
update the counted values of each of the plurality of memory cell rows in response to the subsequent command,
wherein the subsequent command corresponds to one of:
an active count update command which the memory controller applies after the active command and a read command designating a read operation on a target memory cell row or a write command designating a write operation on the target memory cell row, and before a precharge command,
a precharge command designating a precharge operation on the target memory cell row, and including a ninth command/address signal or a tenth command/address signal each having a logic low level or a logic high level from among the first through fourteenth command/address signals of the precharge command, and
a read command including an auto precharge or a write command including an auto precharge on the target memory cell row, and each including a tenth command/address signal having a logic low level or a logic high level from among the first through fourteenth command/address signals,
wherein the ninth command/address signal or the tenth command/address signal of the precharge command includes at least one of a command signal and an address signal, and
wherein the tenth command/address signal of the read command or the write command includes at least one of a command signal and an address signal.