Patent ID: 11900038
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 3:
4. The method of claim 1, wherein said determining the minimum voltage of the power input node of each circuit module in the circuit corresponding to the power wire topology network comprises:
performing a first simulation based a preset power voltage according to the power wire topology network, so as to obtain a current of each circuit module in the circuit corresponding to the power wire topology network;
performing a circuit simulation according to the parasitic element between the power child nodes and the current of each circuit module, so as to obtain a voltage waveform of the power input node of each circuit module; and
determining a minimum voltage of the power input node of each circuit module according to the voltage waveform of the power input node of each circuit module.