Patent ID: 11961007
Assignee: QUALCOMM INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A system for accelerating machine learning, comprising:
a first inference accelerator and a second inference accelerator to host a neural network, the neural network split between the first inference accelerator and the second inference accelerator;
a host processor to receive inference data and a final inference request result, the final inference request result being generated from intermediate inference request results, the host processor including:
a first request queue associated with the first inference accelerator, the first request queue receiving a pointer to the inference data, the inference data being transmitted from the host processor, via a virtual channel, to the first inference accelerator for processing in response to the first request queue receiving the pointer, and
a completion queue for receiving a final inference request result, via a first direct memory access (DMA) transfer, in response to transmitting the inference data;

means for routing the intermediate inference request results directly between the first inference accelerator and the second inference accelerator, the routing of the intermediate interface request results being performed independently of the host processor; and
means for transmitting, the final inference request result to the host processor, via the first DMA transfer, the transmission being initiated by a global synchronization manager (GSM) included in the first inference accelerator or the second inference accelerator in accordance with satisfying a pre-synchronization condition.