Patent ID: 11941338
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 14:
15. An integrated circuit (IC), comprising:
at least one first macro comprising a first macro boundary and a first main pattern surrounded by the first macro boundary, wherein the first macro boundary is formed by a plurality of first dummy boundary cells;
at least one second macro comprising a second macro boundary and a second main pattern surrounded by the second macro boundary, wherein the second macro boundary is formed by a plurality of second dummy boundary cells; and
a top channel between the first and second macros, wherein the top channel is filled with the first dummy boundary cells,
wherein a first gate length of dummy patterns within the first dummy boundary cells is greater than a second gate length of dummy patterns within the second dummy boundary cells.