Patent ID: 11901463
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. A method comprising:
implanting a first dopant into a substrate to form a plurality of source/drain (S/D) regions in the substrate;
implanting a second dopant into the substrate to define a channel region, wherein the channel region is between adjacent S/D regions of the plurality of S/D regions, wherein the second dopant and the first dopant are p-type, and a concentration of the second dopant in the channel region is less than a concentration of the first dopant in each of the plurality of S/D regions;
implanting a third dopant into the substrate to define a lightly doped drain (LDD) region extending continuously under each of the plurality of S/D regions and under the channel region; and
forming a gate stack over the channel region.