Patent ID: 11868647
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A memory controller comprising:
a processor;
control pins configured to provide control signals to at least one nonvolatile memory device including a first memory area connected to a first word line;
an error correction circuit configured to correct data read from the at least one nonvolatile memory device based on the control signals; and
a buffer memory configured to store a plurality of tables for compensating for a reading level of a reading operation of the at least one nonvolatile memory device,
wherein the processor is configured to input a first read command for performing a first reading operation on the first memory area using at least one variation table stored in the at least one nonvolatile memory device,
wherein the plurality of tables includes a history reading level table, and the processor is further configured to update the history reading level table when error correction of data read by the first reading operation is successful,
wherein the at least one nonvolatile memory device further includes a second memory area connected to a second word line; and the processor is further configured to input a second read command for performing a second reading operation on the second memory area to the at least one nonvolatile memory device, based on the history reading level table,
wherein the processor is further configured to input a variation flag together with the second read command to the at least one nonvolatile memory device, and
wherein the variation flag includes a signal allowing the at least one nonvolatile memory device to perform the second reading operation by reflecting variation information of threshold voltages of memory cells connected to the second word line, wherein the at least one variation table includes the variation information.