Patent ID: 11899961
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus, comprising:
a memory die comprising a plurality of planes arranged in a plurality of tiles, of the plurality of planes comprising content-addressable memory cells; and
logic coupled with the memory die and configured to:
perform a computational operation on first data that is stored in a first plane of the plurality of planes, wherein the computational operation is based at least in part on a capability of the content-addressable memory cells, and wherein the first data is representative of a set of contiguous bits of a vector;
perform, concurrent with performing the computational operation on the first data, the computational operation on second data that is stored in a second plane of the plurality of planes, wherein the second data is representative of the set of contiguous bits of the vector; and
read, from the first plane and write to the second plane, third data representative of a result of the computational operation on the first data.