Patent ID: 11973040
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A method for forming an integrated circuit (IC) chip package structure, comprising:
providing a substrate for an interposer having a front surface and a back surface;
forming a conductive interconnect structure in and on the substrate for connecting a group of selected IC dies facing the front surface of the interposer;
forming warpage-reducing trenches in non-routing regions of the interposer, wherein the warpage-reducing trenches are sized and positioned based on a warpage characteristic to reduce the warpage of the chip package structure, and the warpage-reducing trenches do not extend to the back surface of the interposer;
depositing a warpage-relief material in the warpage-reducing trenches according to the warpage characteristic to reduce the warpage of the chip package structure; and
bonding the group of selected IC dies to the front surface of the interposer to form a chip package structure.