Patent ID: 11941294
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory controller for controlling a memory device, comprising:
a host interface configured to receive a request from a host;
a processor configured to generate a command corresponding to the request;
a command queue configured to store the generated command; and
a memory interface configured to provide the memory device with the command stored in the command queue or a suspend command, generated by the processor,
wherein, when a read request is input through the host interface while the memory device is performing an operation, the processor is further configured to:
determine a delay amount of time for output of the suspend command that instructs suspension of the operation, based on a number of read commands stored in the command queue, and
output, after the delay amount of time has elapsed, the suspend command, and
wherein a length of the delay amount of time depends on the number of read commands.