Patent ID: 11966591
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A memory controller, comprising:
at least one processor;
embedded memory coupled to the processor and storing instructions for execution by the at least one processor, the instructions comprising—
controlling operations of a memory array to program a first deck before a second deck of a memory block of the memory array;
determining a deck separation delay according to a duration between programming the first and second decks;
identifying an offset level based on the deck separation delay, wherein the offset level represents an imbalance in charges stored at the first and second decks due to the deck separation delay; and
dynamically computing a deck-specific read level based on a base read level, the offset level, or a combination thereof to account for the imbalance in the stored charges.