Patent ID: 11917830
Assignee: XIANGTAN UNIVERSITY
Field: nan (nan)
Classification: CPC H | IPC H

Claim 0:
1. A method for preparing a NAND ferroelectric memory cell with a three-dimensional structure, comprising:
alternately depositing a plurality of insulating layers (2) and gates (3) on a substrate (1);
depositing a protective layer on the alternately deposited insulating layers (2) and gates (3) to complete a stacked gate;
etching a through hole of a predetermined size on the stacked gate directly to the substrate (1);
successively depositing, on the inner wall of the through hole, a gate buffer layer (6), a ferroelectric layer (8), a channel buffer layer (9), a channel layer (10), and an oxide insulating layer (11); or a gate buffer layer (6), a ferroelectric layer (8), a channel layer (10), and an oxide insulating layer (11); or a ferroelectric layer (8), a channel buffer layer (9), a channel layer (10), and an oxide insulating layer (11), wherein an etching protection layer (7) is respectively deposited after depositing the gate buffer layer (6), the ferroelectric layer (8) and the channel buffer layer (9).