Patent ID: 11862708
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A device comprising:
a replacement gate stack;
a laminate low-k dielectric liner directly on a sidewall of the replacement gate stack, wherein the laminate low-k dielectric liner comprises a first sub layer and a second sub layer, with the first sub layer and the second sub layer comprising different materials;
a dielectric spacer comprising a first sidewall contacting a second sidewall of the laminate low-k dielectric liner to form a vertical interface;
a source/drain region on a side of the replacement gate stack;
a source/drain silicide region over and contacting the source/drain region;
a source/drain contact plug over and contacting the source/drain silicide region; and
a high-k dielectric contact spacer encircling the source/drain contact plug, wherein the high-k dielectric contact spacer extends lower than a top surface of the source/drain silicide region.