Patent ID: 11869934
Assignee: SILANNA ASIA PTE LTD
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A semiconductor device, comprising:
an active region;
a LOCOS region formed within the active region and extending vertically above a top surface of the active region;
a gate region formed above the top surface of the active region; and
a polysilicon resistor having a bottom surface that is offset vertically and physically isolated from a top surface of the LOCOS region;
wherein:
the active region comprises a source region laterally disposed from the gate region, a drain region laterally disposed from the gate region, and a drift region laterally disposed between the gate region and the drain region, the polysilicon resistor being formed above the drift region, the active region further comprising a first charge balance region formed in the active region below the drift region and the first charge balance region is separated from the LOCOS region by the drift region;
a lateral extent of the first charge balance region is less than a lateral extent of the drift region;
a lateral extent of the polysilicon resistor is less than the lateral extent of the first charge balance region; and
the polysilicon resistor is substantially laterally aligned with the first charge balance region and the drift region.