Patent ID: 11961890
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 1:
2. A semiconductor device comprising:
a semiconductor layer having an upper surface;
a drift region disposed in the semiconductor layer and having a first conductivity type;
a well region disposed in the semiconductor layer and having a second conductivity type opposite the first conductivity type;
a dielectric film disposed in the drift region; and
a gate structure disposed on the semiconductor layer and including:
a multi-stepped gate dielectric including a first gate dielectric portion and a second gate dielectric portion connected to the first gate dielectric portion, the first gate dielectric portion having a flat upper surface, the second gate dielectric portion having a stepped upper surface that includes a flat upper surface portion connected to and flush with the flat upper surface of the first gate dielectric portion, and
a gate electrode disposed on the multi-stepped gate dielectric,

wherein a projection of the dielectric film on the upper surface of the semiconductor layer is non-overlapping with a projection of the second gate dielectric portion on the upper surface of the semiconductor layer, and
wherein the multi-stepped gate dielectric includes a first gate dielectric segment disposed on the dielectric film and the drift region, a second gate dielectric segment disposed on the drift region and connected to the first gate dielectric segment, and a third gate dielectric segment disposed on the drift region and the well region and connected to the second gate dielectric segment, the first gate dielectric segment having a first thickness, the second gate dielectric segment having a second thickness that is less than the first thickness, the third gate dielectric segment having a third thickness that is less than the second thickness.