Patent ID: 11907158
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. An apparatus, comprising:
a plurality of vector registers configured to store a plurality of vectors of data elements respectively;
a register configured to store an index;
a plurality of processing units configured to operate in parallel; and
a circuit controlled by the register and coupled between the plurality of vector registers and the plurality of processing units, the circuit configured to provide a plurality of input vectors to the plurality of processing units respectively, wherein the circuit is configured to generate each respective input vector in the plurality of input vectors using:
a first portion selected according to the index from a first lane and a second lane of a first vector register in the plurality of vector registers; and
a second portion selected according to the index from a third lane and a fourth lane of a second vector register in the plurality of vector registers,
wherein the circuit comprises:
a first multiplexor configured to receive first data from the first lane of the first vector register and second data from the second lane of the first vector register and output a first lane input to a first processing unit of the plurality of processing units;
a second multiplexor configured to receive third data from the first lane of the first vector register and fourth data from the second lane of the first vector register and output a second lane input to a second processing unit of the plurality of processing units;
a third lane input to the first processing unit from a third multiplexor associated with the third lane of the second vector register, wherein the third multiplexor further outputs the third lane input to a third processing unit of the plurality of processing units; and
a fourth lane input to the second processing unit from a fourth multiplexor associated with the fourth lane of the second vector register.