Patent ID: 11916055
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A semiconductor structure, comprising:
a cell array, comprising:
a plurality of first logic cells arranged in odd-numbered rows of the cell array, each of the plurality of first logic cells having a first cell height; and
a plurality of second logic cells arranged in even-numbered rows of the cell array, each of the plurality of second logic cells having a second cell height that is different than the first cell height, wherein one of the plurality of second logic cells is immediately adjacent to one of the plurality of first logic cells,
a plurality of first metal lines formed in a metal layer and inside the plurality of first logic cells of the odd-numbered rows of the cell array;
a plurality of second metal lines formed in the metal layer and inside the plurality of second logic cells of the even-numbered rows of the cell array; and
a plurality of third metal lines formed in the metal layer and covering the plurality of first and second logic cells,
wherein the plurality of first metal lines, the plurality of second metal lines and the plurality of third metal lines are parallel to each other,
wherein each of the plurality of third metal lines is disposed between at least one of the plurality of first metal lines and at least one of the plurality of second metal lines,
wherein the plurality of first metal lines of the odd-numbered rows of the cell array have a uniform first width, the plurality of second metal lines of the even-numbered rows of the cell array have a uniform second width, and the first width is greater than the second width, and
wherein the odd-numbered rows of the cell array are free of the plurality of second logic cells and the plurality of second metal lines, and the even-numbered rows of the cell array are free of the plurality of first logic cells and the plurality of first metal lines.