Patent ID: 11916554
Assignee: INTEL CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 14:
15. A system comprising:
a memory device; and
a memory controller to include:
input/output interface circuitry arranged to couple with the memory device;
a target clock to generate a target clock signal used to derive a duty cycle;
a sample clock to measure the duty cycle by periodic sampling of the target clock signal based on a greater than 1 prime number ratio of a reference clock cycle time, wherein the reference clock cycle time is used to set a measurement cycle time over which the target clock signal is to be sampled; and
duty cycle correction logic to determine a duty cycle error as compared to a programmable target duty cycle based on a measured duty cycle during the measurement cycle time and adjust the duty cycle derived by the target clock signal based, at least in part, on the duty cycle error.