Patent ID: 11868283
Assignee: THE REGENTS OF THE UNIVERSITY OF MICHIGAN
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 8:
9. A computer system for analyzing a graph, comprising:
a plurality of computer processor nodes interconnected together and integrated onto a single integrated circuit; wherein each computer processor node in the plurality of computer processor nodes includes a core processor, a cache memory, a scratchpad memory, and an atomic operations compute unit; and
one or more off-chip memory modules physically separated from the integrated circuit and accessible to the plurality of computer processor nodes, wherein each of the one or more off-chip memory modules includes an atomic compute unit, a memory controller, and a memory;
wherein data related to high-degree vertices of a graph are stored in the scratchpad memory and data related to low-degree vertices of the graph are stored in the memory of the one or more off-chip memory modules, such that vertices in the graph are ordered in descending order from vertices with most number of edges to vertices with least number of edges and a subset of the vertices having the most number of edges are the high-degree vertices and the remainder of the vertices in the graph are low-degree vertices,
wherein atomic operations pertaining to the high-degree vertices are performed by an atomic compute unit of a respective computer processor node where the data related to the high-degree vertices is stored.