Patent ID: 11869604
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device, comprising:
an array of memory cells comprising:
a plurality of memory blocks; and
a plurality of dummy rows configured to store a respective particular pattern corresponding to each respective memory block of the plurality, wherein each dummy row is:
associated with an address space that is outside an address space of the respective memory block; and
configured to store parameters of a recently completed erasing operation in the respective memory block; and

a controller coupled to the array of memory cells and configured to, for each respective memory block of the plurality:
determine, responsive to a power-up of the array of memory cells, whether the corresponding particular pattern is written to the corresponding dummy row, wherein a determination that the corresponding particular pattern is not written to the corresponding dummy row is indicative of an incomplete erase of the memory block;
responsive to a determination that the corresponding particular pattern is not written to the corresponding dummy row, execute an erase phase on the corresponding memory block; and
responsive to a completion of the execution of the erase phase on the corresponding memory block, store, in the corresponding dummy row, new parameters of the completed erase phase as parameters of the recently completed erasing operation in the corresponding memory block.