Patent ID: 11935792
Assignee: SK HYNIX INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor device, comprising:
a gate dielectric layer conformally covering a trench of a substrate;
a first barrier layer formed over the gate dielectric layer;
a lower gate formed over the first barrier layer and partially filling a lower portion of the trench;
an upper gate formed over the lower gate;
a vertical gate formed over the first barrier layer and formed between the upper gate and the gate dielectric layer;
a capping layer formed over the upper gate;
a spacer formed over the vertical gate and formed between the gate dielectric layer and the capping layer;
a second barrier layer formed between the first barrier layer and the vertical gate; and
wherein the second barrier layer includes material that nitriding a surface of the first barrier layer.