Patent ID: 11901030
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A memory device, comprising:
a memory array, comprising a memory cell;
a voltage tracking circuit, configured to generate a first reference voltage based on a threshold voltage of a select transistor of the memory cell;
a temperature tracking circuit, configured to generate a second reference voltage based on a temperature of the memory array;
a bit line voltage adjustment circuit, coupled to the voltage tracking circuit and the temperature tracking circuit, configured to generate a bit line voltage according to at least one of the first reference voltage or the second reference voltage, wherein the memory cell is driven by the bit line voltage,
wherein the voltage tracking circuit comprises:
a resistor, coupled between a gate terminal and a source terminal of the select transistor of the memory cell, configured to sense the threshold voltage of the select transistor through a current flowing through the resistor.