Patent ID: 11915778
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. The semiconductor memory device according to claim 2, wherein
the first plane includes a first circuit configured to read the first data from the first memory cell group via a first number of first bit lines and generate the third data based on the read first data,
the second plane includes a second circuit configured to read the second data from the second memory cell group via the first number of second bit lines and generate the fourth data based on the read second data,
the number of bits of the first data is the first number,
the number of bits of the second data is the first number,
the number of bits of the third data is equal to or less than half of the first number, and
the number of bits of the fourth data is equal to or less than half of the first number.