Patent ID: 11940922
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 18:
19. An HBM system comprising:
an HBM comprising:
a DRAM die comprising a DRAM; and
a logic die comprising a controller, an Arithmetic Logic Unit (ALU), and a SRAM, wherein the SRAM is configured as a scratchpad;

a memory controller separate from the HBM, and configured to send an instruction to the controller;
wherein the controller is configured to receive the instruction from an HBM memory controller of a processor, and to forward the instruction to the DRAM on the DRAM die in response to the instruction being a regular instruction and to coordinate execution of an atomic operation of the instruction in response to the instruction being a Function-in-HBM (FIM) instruction, wherein the FIM instruction comprises the atomic operation and a FIM designator that identifies the FIM instruction as FIM, the atomic operation being generated by the processor by merging a first instruction of a first type and a second instruction of a second type into an atomic instruction; and
wherein the execution of the instruction is performed using the controller and at least one of the DRAM, the ALU or the SRAM.