Patent ID: 11973090
Assignee: DEPUY SYNTHES PRODUCTS, INC.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC H  A | IPC A  H

Claim 10:
11. A method of accessing data comprising:
electronically connecting a pixel array to supporting circuits of an imaging sensor;
wherein the pixel array comprises a plurality of pixels formed into a plurality of pixel columns, wherein the plurality of pixel columns are divided into a plurality of pixel sub-columns;
wherein the imaging sensor comprises a plurality of pixel sub-column buses that correspond with the plurality of pixel sub-columns, such that at least one of the plurality of pixel sub-column buses is associated with one of the plurality of pixel sub-columns such that each of the plurality of pixel sub-columns are configured to be read independently;
wherein the imaging sensor comprises a plurality of supporting circuits configured to process data received from the plurality of pixels, wherein the plurality of supporting circuits are formed into a plurality of supporting circuit columns, and wherein the plurality of supporting circuit columns are divided into a plurality of supporting circuit sub-columns;
wherein the imaging sensor comprises a plurality of supporting circuit sub-column buses that correspond with the plurality of supporting circuit sub-columns, such that at least one of the plurality of supporting circuit sub-column buses is associated with one of the plurality of supporting circuit sub-columns;
reading data out from the plurality of pixel sub-columns starting with a first pixel in each of the plurality of sub-columns and sequentially reading out data from each of the pixels in the pixel sub-column until the last pixel in the sub-column is read;
transmitting the data from each of the plurality of pixel sub-column buses through at least one interconnect to a corresponding supporting circuit sub-column bus;
processing the data into a visual frame for display;
wherein at least a portion of the plurality of supporting circuit sub-column buses and at least a portion of the plurality of pixel sub-columns buses are superimposed;
wherein the at least one interconnect is positioned anywhere along an intercept of the plurality of pixel sub-column buses and the plurality of circuit sub-column buses, wherein the intercept is defined by the superimposition of the at least a portion of the plurality of pixel sub-column buses directly with the at least a portion of the plurality of the circuit sub-column buses.