Patent ID: 11960946
Assignee: SNAP INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. A method of operating a message-based processor system, comprising a first plurality of message-based processor system cores, the method comprising:
providing a second plurality of storage locations for maintaining respective processor element states, each of the second plurality of storage locations having a respective processor element address;
providing respective pluralities of third addressable storage entries and storing therein pattern information of respective target patterns, the pattern information comprising, for respective pattern elements of a respective target pattern, both a magnitude indicator with a magnitude value and a control indicator with a control value;
receiving as an input message an event message comprising a target pattern indication with a target pattern indication value and a target processor element subset indication with a target processor element subset indication value;
selecting an initial address computation mode from a cyclic set of address computation modes;
determining a processor element address in accordance with the target processor element subset indication value;
designating one of the third addressable storage entries of a pattern element in accordance with the target pattern indication;
retrieving, from the designated one of the third addressable storage entries, the magnitude value and the control value;
updating a state of the processor element specified by the processor element address in accordance with the magnitude value;
selectively selecting, in accordance with the control value, a next address computation mode in the cyclic set of address computation modes;
computing a subsequent processor element address in accordance with a current address computation mode as determined by the selectively selecting the next address computation mode;
determining a subsequent third addressable storage entry; and
repeating the retrieving from the third addressable storage entry and succeeding updating, selectively selecting, computing and determining operations until a stop condition is valid.