Patent ID: 11961824
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor package comprising:
a package substrate including an upper surface;
bonding pads arranged on the upper surface of the package substrate;
a lower semiconductor chip disposed on the upper surface of the package substrate, wherein an upper surface of the lower semiconductor chip includes a connect edge region and an open edge region;
connection pads arranged on the upper surface of the lower semiconductor chip in the connect edge region;
bonding wires respectively connecting the bonding pads and the connection pads;
a dam structure including dummy bumps disposed in the open edge region and dummy wires extending between adjacent ones of the dummy bumps;
an upper semiconductor chip disposed on the upper surface of the lower semiconductor chip;
an inter-chip bonding layer between the lower semiconductor chip and the upper semiconductor chip; and
a molding portion on the package substrate and substantially surrounding the lower semiconductor chip and the upper semiconductor chip.