Patent ID: 11946970
Assignee: TEKTRONIX, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 13:
14. A method for electrical margin testing of a device under test (DUT), the method comprising:
establishing, by a test device that includes a controller coupled to at least one interface, a multi-lane high speed input/output (I/O) link of the DUT in which, for one or more lanes of the multi-lane high speed I/O link, the controller implements physical and logical link layers of the test device that communicatively connect margin test circuitry with the DUT via the at least one interface, the margin test circuitry including a margin test transmitter of the test device and/or a margin test receiver of the test device; and
assessing, by the controller of the test device controlling the margin test transmitter and/or the margin test receiver, an electrical margin of the one or more lanes of the multi-lane high speed I/O link, in either or both transmit (Tx) and receive (Rx) directions, wherein in the Tx direction the controller causes the margin test transmitter to transmit data generated by the margin test circuitry to the DUT, and in the Rx direction the margin test receiver receives data from the DUT.