Patent ID: 11935925
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 1:
2. The method for manufacturing the semiconductor structure of claim 1, wherein said patterning the passivation layer and the second conductive layer to form the primary gate pattern further comprises:
forming a mask layer and a photoresist layer on the passivation layer;
patterning the photoresist layer, wherein the photoresist layer at a region where the primary gate pattern needs to be formed is retained;
transferring the pattern of the photoresist layer to the mask layer to form a patterned mask layer;
removing the passivation layer and the second conductive layer by taking the mask layer as a mask; and
removing the mask layer and the photoresist layer to form the primary gate pattern.