Patent ID: 11902059
Assignee: APPLE INC.
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A system comprising:
a receiver circuit configured to receive, from a transmitter, an incoming signal having a stream of data symbols, wherein the receiver circuit includes:
a continuous time linear equalizer (CTLE) circuit configured to generate a filtered signal based on the incoming signal;
a summing circuit configured to generate an equalized signal by combining the filtered signal with a feedback signal;
a sample recovery circuit configured to recover a plurality of symbols from the equalized signal;
a decision feedback equalization (DFE) circuit configured to generate the feedback signal based on the plurality of recovered symbols; and
a finite state machine configured to cause adjustments to one or more filters in the CTLE circuit based on the plurality of recovered symbols, wherein the one or more filters include one or more resistances and one or more capacitances, and wherein the finite state machine is configured to generate control signals to cause adjustments of the one or more filters by adjusting the one or more resistances and the one or more capacitances.