Patent ID: 11949595
Assignee: INTEL CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An apparatus comprising:
a first set of processing element nodes arranged in at least two columns and at least two rows, the first set of processing element nodes defining a first hierarchy of processing element nodes, the first set of processing element nodes comprising:
a source node,
a source look-up table (LUT),
a first router, the first router to comprise a first forwarder node, and
a first reflection LUT; and

a second set of processing element nodes arranged in at least two columns and at least two rows, the second set of processing element nodes defining a second hierarchy of processing element nodes, the second set of processing element nodes comprising:
a second router, the second router to comprise a second forwarder node,
a target node;

wherein the first reflection LUT is to comprise an address of the second forwarder node in the second hierarchy,
wherein, for a packet from the source node to the target node, (i) the source node is to route the packet to the first forwarder node with use of dimension order routing (DOR) within the first set of processing element nodes, (ii) the first forwarder node is to route the packet to the second forwarder node with use of DOR within a plurality of forwarder nodes, the plurality of forwarder nodes comprising the first forwarder node and the second forwarder node, wherein each of the forwarder nodes of the plurality of forwarder nodes resides in its own hierarchy, and (iii) the second forwarder node is to route the packet to the target node with use of DOR within the second set of processing element nodes.