Patent ID: 11915748
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. A method for controlling a semiconductor memory device, the semiconductor memory device including (i) a memory cell array including a first memory cell capable of holding at least n-bit data, with n being an integer that is at least 4, (ii) a conversion circuit configured to recover the n-bit data based on m-bit data generated by converting the n-bit data and data written in the first memory cell, with m being an integer that is smaller than n, and (iii) at least one pad connectable with an outside of the semiconductor memory device, and the method comprising:
receiving the n-bit data from the outside;
performing a first write operation to the first memory cell based on the n-bit data that is received from the outside;
recovering the n-bit data using the conversion circuit; and
performing a second write operation to the first memory cell based on the n-bit data that is recovered by the conversion circuit, thereby writing the n-bit data in the first memory cell.