Patent ID: 11961881
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for forming a semiconductor structure, comprising:
providing a semiconductor substrate, which at least comprises discrete conducting layers in the semiconductor substrate;
forming a bottom conducting layer on the semiconductor substrate, the bottom conducting layer being electrically connected with the conducting layers;
forming discretely arranged supporting structures on the bottom conducting layer, capacitor openings being comprised between the supporting structures;
forming lower electrodes on sidewalls of the supporting structures, the lower electrodes being electrically connected with the bottom conducting layer;
etching away the bottom conducting layer exposed from the bottom of the capacitance openings, the bottom conducting layer located only between the semiconductor substrate and the supporting structure;
forming a capacitor dielectric layer covering tops of the supporting structures, sidewalls of the lower electrodes, and bottoms of the capacitor openings; and
forming an upper electrode covering the capacitor dielectric layer, to form capacitor structures.