Patent ID: 11908757
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A chip package structure, comprising:
at least one semiconductor die attached to a redistribution structure;
a first underfill material portion located between the redistribution structure and the at least one semiconductor die and laterally surrounding a portion of the at least one semiconductor die;
a molding compound laterally surrounding at least one semiconductor die; and
a second underfill material portion contacting sidewalls of the redistribution structure and sidewalls of the molding compound and comprising at least one cut region, wherein the second underfill material portion comprises a vertically-extending portion having a uniform lateral width and a horizontally-extending portion having a uniform vertical thickness and adjoined to a bottom end of the vertically-extending portion within each of the at least one cut region, wherein:
the molding compound has a rectangular outer periphery in a plan view; and
the at least one cut region comprises four cut regions located outside, and in proximity to, four corners of the rectangular outer periphery.