Patent ID: 11894374
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A semiconductor structure, comprising a substrate, and an NMOS transistor and a PMOS transistor that are located on the substrate, wherein
the NMOS transistor comprises:
a first dielectric layer, located on the substrate;
a first work function layer, located on the first dielectric layer; and
a first conductive layer, located on the first work function layer; and

the PMOS transistor comprises:
a second dielectric layer, located on the substrate;
a second work function layer, located on the second dielectric layer; and
a second conductive layer, located on the second work function layer;

at least one of:
the first work function layer is provided with a first sidewall isolation layer on a side facing the second work function layer, or
the second work function layer is provided with a second sidewall isolation layer on a side facing the first work function layer,

an isolation structure is formed in the substrate, so as to separate a first active region and a second active region in the substrate for the NMOS transistor and the PMOS transistor respectively, and
at least one of the NMOS transistor or the PMOS transistor covers a part of the isolation structure.