Patent ID: 11893438
Assignee: EXCELIO TECHNOLOGY (SHENZHEN) CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. The positive feedback latch amplitude limiting control method according to claim 8, wherein when the field strength changes from weak to strong, the step S2 includes following states:
a: when 0<S1<the turn-on voltage of the first inverting sub-module and the second inverting sub-module, both the logic signal S2 and the logic signal S2′ are the high level “1”, and both the first discharge path and the second discharge path maintain the turned-off state;
b: when the turn-on voltage of the first inverting sub-module and the second inverting sub-module≤S1<the sum of the threshold voltage and the turn-on voltage of the third inverting sub-module and the fourth inverting sub-module, the logic signal S2 is the low level “0”, the logic signal S2′ is the high level “1”, the first discharge path is in the turned-on state to maintain discharging, and the second discharge path maintains the turned-off state; and
c: when the sum of the threshold voltage and the turn-on voltage of the third inverting sub-module and the fourth inverting sub-module≤S1, both the logic signal S2 and the logic signal S2′ are the low level “0”, and both the first discharge path and the second discharge path are in the turned-on state to maintain discharging; or
when the field strength changes from strong to weak, the step S2 includes following states:
a′: when the sum of the threshold voltage and the turn-on voltage of the third inverting sub-module and the fourth inverting sub-module≤S1, both the logic signal S2 and the logic signal S2′ are the low level “0”, and both the first discharge path and the second discharge path are in the turned-on state to maintain discharging;
b′: when the turn-on voltage of the first inverting sub-module and the second inverting sub-module≤S1<the sum of the threshold voltage and the turn-on voltage of the third inverting sub-module and the fourth inverting sub-module, the logic signal S2 is the low level “0”, the logic signal S2′ is the high level “1”, the first discharge path is in the turned-on state to maintain discharging, and the second discharge path maintains the turned-off state; and
c′: when 0<S1<the turn-on voltage of the first inverting sub-module and the second inverting sub-module, both the logic signal S2 and the logic signal S2′ are the high level “1”, and both the first discharge path and the second discharge path maintain the turned-off state.