Patent ID: 11907680
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 24:
25. The MAC operator of claim 24, wherein the second normalizer includes:
an MSB “1” searching circuit that searches for a position of MSB “1” in the mantissa data of the MAC data output from the second buffer and outputs a shift bit based on the search result;
a shifting circuit that performs shift on the mantissa data of the MAC data output from the second buffer by a value of the shift bit to output the mantissa data of the standard format;
an exponent lower data extracting circuit that outputs a binary stream corresponding to the value of the shift bit as the exponent lower data; and
a sign data extracting circuit that outputs the most significant bit (MSB) of the mantissa data of the MAC data output from the second buffer as the sign data.