Patent ID: 11954059
Assignee: SONY INTERACTIVE ENTERTAINMENT LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. A signal processing chip including a plurality of signal processing blocks connected to each other by a signal line,
the signal processing chip being connected to another signal processing chip including a plurality of signal processing blocks connected to each other by a signal line,
the signal processing chip comprising:
reception means for receiving, from the another signal processing chip, a data frame indicating a signal on the signal line between the signal processing blocks in the another signal processing chip, the signal having been sampled in the another signal processing chip; and
inverse sampling means for outputting a signal to the signal line of the signal processing chip on a basis of the data frame received; wherein
the sampling is performed with a predetermined scheme irrespective of on-chip interconnect protocols of the signal processing chip and on-chip interconnect protocols of the another signal processing chip; and
the predetermined scheme optimizes voltage amplitude.