Patent ID: 11922133
Assignee: STMICROELECTRONICS (GRENOBLE 2) SAS
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 0:
1. A method of operating an arithmetic and logic unit of a central processing unit (CPU), the method comprising:
receiving, by an arithmetic-to-logic circuit of an input masking circuit, first arithmetic-masked input data and first input masks;
generating, by a complementary circuit of the arithmetic-to-logic circuit, masked complementary data from the first arithmetic-masked input data;
generating, by a first carry circuit of the arithmetic-to-logic circuit, arithmetic carry digits from the first arithmetic-masked input data and the first input masks;
generating, by a first exclusive-OR circuit of the arithmetic-to-logic circuit, first logic-masked input data from the masked complementary data and the arithmetic carry digits;
generating, by a second carry circuit of a logic-to-arithmetic circuit, logic carry digits from second logic-masked input data and second input masks;
generating, by a second exclusive-OR circuit of the logic-to-arithmetic circuit, second arithmetic-masked input data from the second logic-masked input data and the logic carry digits;
applying, by an arithmetic circuit, arithmetic operations to the first arithmetic-masked input data, the first input masks, the second arithmetic-masked input data, and the second input masks to generate intermediate arithmetic-masked result data and first intermediate result masks;
applying, by a logic circuit, logic operations to the first logic-masked input data, the first input masks, the second logic-masked input data, and the second input masks to generate intermediate logic-masked result data and second intermediate result masks;
generating, by an output masking circuit, final masked result data and final result masks from the intermediate arithmetic-masked result data, the first intermediate result masks, the intermediate logic-masked result data, and the second intermediate result masks; and
keeping, by the arithmetic and logic unit, the first arithmetic-masked input data, the first logic-masked input data, the second arithmetic-masked input data, the second logic-masked input data, the masked complementary data, the intermediate arithmetic-masked result data, the intermediate logic-masked result data, and the final masked result data masked throughout processing of the first arithmetic-masked input data, the first logic-masked input data, the second arithmetic-masked input data, the second logic-masked input data, the masked complementary data, the intermediate arithmetic-masked result data, the intermediate logic-masked result data, and the final masked result data in the arithmetic and logic unit.