Patent ID: 11915000
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 18:
19. A system comprising:
a memory;
a decoder to decode an instruction into a decoded instruction;
an execution circuit to execute the decoded instruction to produce a resultant;
a first level data cache;
a store buffer;
a retirement circuit to retire the instruction when a store request for the resultant is queued into the store buffer for storage into the memory but is not yet completed to the memory; and
a performance monitoring circuit to:
monitor post-retirement performance information of the retired instruction between the store request being accepted into the first level data cache and being completed to the memory, wherein the post-retirement performance information comprises a first value to indicate the store request missed in the first level data cache and a second value to indicate the store request missed in a translation lookaside buffer, and
store the post-retirement performance information in storage of the performance monitoring circuit.