Patent ID: 11869951
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 1:
2. The method according to claim 1, wherein the patterning comprises:
etching back the gate layer until a top surface of the gate layer is below top surfaces respectively of the first and second control-gate stacks, wherein the gate layer has a U-shaped profile between the first and second control-gate stacks at completion of the etching back;
after the etching back, depositing a hard mask layer over the first and second control-gate stacks and the gate layer, wherein a thickness of the hard mask layer is substantially uniform from the first control-gate stack to the second control-gate stack;
patterning the hard mask layer with a word-line pattern; and
performing an etch into the gate layer with the hard mask layer in place to transfer the word-line pattern from the hard mask layer to the gate layer to form the word line.