Patent ID: 11907680
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. The MAC operator of claim 14, wherein the first normalizer includes:
a shift discriminating circuit that discriminates whether a bit having a value of “1” is located at least upper 8 bits or higher from a binary decimal point in the accumulative mantissa data and generates and outputs a first selection signal and a second selection signal based on a discrimination result;
a demultiplexer that outputs the accumulative mantissa data as the first normalized accumulative mantissa data through a first output terminal in response to the first selection signal of a first logic level and outputs the accumulative mantissa data through a second output terminal in response to the first selection signal of a second logic level;
a shifting circuit that, when the accumulative mantissa data is transmitted from the second output terminal of the demultiplexer, performs shifting on the accumulative mantissa data and outputs the result as the first normalized accumulative mantissa data;
a “+1” adder that adds “+1” to the second maximum exponent upper data and outputs an addition result as added second maximum exponent upper data; and
a multiplexer that outputs the added second maximum exponent upper data transmitted to a first input terminal as the accumulative exponent upper data in response to the second selection signal of a second logic level and outputs the second maximum exponent upper data transmitted to a second input as the accumulative exponent upper data terminal in response to the second selection signal of the first logic level.