Patent ID: 11929300
Assignee: QORVO US, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for packaging an integrated circuit (IC), the method comprising:
providing an IC die having an active side and a backside opposite the active side; and
forming a backside polymer redistribution layer (RDL) underneath the backside of the IC die, wherein:
the backside polymer RDL includes a plurality of signal lines, a polymer dielectric layer, and a heat spreader;
the plurality of signal lines is configured to laterally redistribute connections from backside contacts on the backside of the IC die to an opposite surface of the backside polymer RDL;
the polymer dielectric layer encapsulates and isolates the plurality of signal lines from one another; and
the heat spreader is embedded in the polymer dielectric layer and connected to the backside of the IC die, wherein the heat spreader spans a thickness of the polymer dielectric layer, and the heat spreader has a width greater than the thickness of the polymer dielectric layer.