Patent ID: 11929748
Assignee: STMICROELECTRONICS (GRENOBLE 2) SAS
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 9:
10. The device of claim 7, wherein,
the delay elements of the chain, when enabled, add a same delay time period to a received digital signal; and
the control circuitry, in operation, generates a regulation control value H according to:

H=(M−Rf)*K, where:
Rf represents a number of rising edges of the reference clock signal during a sampling time period C;
M represents a number of rising edges of the wobulated signal counted by the counter during the sampling time period C; and
K is a constant depending on the sampling time period C and a duration S of the delay time period of a delay element of the chain of delay elements.