Patent ID: 11928057
Assignee: CYPRESS SEMICONDUCTOR CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A system, comprising:
a processor;
an application image memory storing a first application image, a second application image, a first offset between a base starting address of the first application image and a physical starting address of the first application image in the application image memory, a second offset between a base starting address of the second application image and a physical starting address of the second application image in the application image memory, and an active image identifier indicating one of the first application image or the second application image as being an active application image; and
a virtual memory controller configured to receive a first address for accessing the application image memory from the processor, modify the first address based on an active image offset to generate a second address, and access the application image memory based on the second address, wherein:
the active image offset comprises the first offset responsive to the first application image being the active application image, and
the active image offset comprises the second offset responsive to the second application image being the active application image.