Patent ID: 11967574
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A memory device, comprising:
a first structure; and
a second structure on the first structure, wherein:
the first structure includes:
a first substrate;
a peripheral circuit on the first substrate;
a first insulating layer covering the first substrate and the peripheral circuit; and
a first bonding pad on the first insulating layer,

the second structure includes:
a second substrate;
a memory cell array on a first surface of the second substrate;
a second insulating layer directly contacting and covering the first surface of the second substrate and the memory cell array;
a conductive pattern at least partially recessed from a second surface of the second substrate; and
a second bonding pad on the second insulating layer,

the first bonding pad is in contact with the second bonding pad, and
the conductive pattern is spaced apart from the second insulating layer.