Patent ID: 11894891
Assignee: INTEL CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A device of an initiator device, the device comprising storage and processing circuitry coupled to storage, the processing circuitry configured to:
generate a block acknowledgment schedule information field associated with one or more destination devices, wherein the block acknowledgment schedule information field comprises:
a block acknowledgment transmission time (BATT) start offset subfield indicative of the beginning of a time slot for the destination device to transmit its block acknowledgment, and
a next physical layer convergence protocol data unit (PPDU) start offset subfield which indicates the moment indicates the offset from the end of the transmitted PPDU to when the initiator device is expected to start transmitting its next PPDU;
cause to send a multi-user multiple-input multiple-output (MU-MIMO) frame to the one or more destination devices, wherein the MU-MIMO frame comprises the block acknowledgment schedule information field, wherein a field of the MU-MIMO frame associated with the block acknowledgment schedule information field starts at bit zero of the block acknowledgment schedule information field; and
identify a first acknowledgment frame received from a first destination device of the one or more destination devices, wherein the first acknowledgment frame is received based on the BATT start offset subfield.