Patent ID: 11860794
Assignee: VENTANA MICRO SYSTEMS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. A method, comprising:
in a microprocessor comprising:
a physically-indexed physically-tagged second-level set-associative cache, wherein each entry in the second-level cache is uniquely identified by a set index and a way of the second-level cache; and
wherein each entry of the second-level cache holds a generational identifier (GENID);

by the second-level cache:
detecting a miss of a physical memory line address in the second-level cache, wherein a set index that selects a set of the second-level cache is obtained from the physical memory line address;
picking a way of the selected set for replacement;
incrementing the GENID held in the entry in the picked way of the selected set;
forming a physical address proxy (PAP) for the physical memory line address with the obtained set index and the picked way, wherein the PAP uniquely identifies the entry in the second-level cache picked for replacement; and
forming a generational PAP (GPAP) for the physical memory line address with the PAP and the incremented GENID held in the entry in the picked way of the selected set; and

making available the GPAP as a proxy of the physical memory line address for comparisons with GPAPs of other physical memory line addresses, rather than making comparisons of the physical memory line address itself with the other physical memory line addresses, to determine whether the physical memory line address matches the other physical memory line addresses.