Patent ID: 11967368
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. The memory system according to claim 1, further comprising: a volatile first storage configured to store the data corresponding to the first to fourth bits; and a volatile second storage configured to store data corresponding to a bit, which is input redundantly during the k-th write process and the the (2n+k)-th write process, among the first to fourth bits, wherein the memory controller discards or invalidates the data corresponding to the first to fourth bits after the k-th write process is started, and the memory controller stores the data corresponding to the bit, which is input redundantly during the k-th write process and the (2n+k)-th write process, among the first to fourth bits before the k-th write process is started, and discarding or invalidating the data after the (2n+k)-th write process is started.