Patent ID: 11860775
Assignee: SILICON MOTION, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. The method of claim 3, wherein the accelerator comprises:
a second SRAM, arranged operably for the processing unit to store the operation settings, the mid-end parameter set, the back-end parameter set and a programming table of the first data-programming transaction; and
a second controller, coupled to the second SRAM and the activation queue,
the method comprising:
driving, by the second controller, the RAID engine to obtain the second data from the second designated address of the RAM through the shared bus architecture, and encrypt the second data or generate the parity-page data in terms of the multiple pages of the second data according to the mid-end parameter set when receiving the activation message for the first data-programming transaction from the activation queue and determining that the mid-end processing stage needs to be activated for the first data-programming transaction according to the operation settings; and
driving, by the second controller, the data access engine to obtain the third data from the third designated address of the RAM through the shared bus architecture and program the third data into the designated address of the flash module when determining that the mid-end processing stage does not need to be activated for the first data-programming transaction according to the operation settings or the mid-end processing stage has been completed, and the back-end processing stage needs to be activated for the first data-programming transaction according to the operation settings.