Patent ID: 11947471
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A module, comprising:
a first memory device disposed on the module and including a first write retry buffer, the first memory device to, based on a first verify operation performed by the first memory device determining a first attempted write failed in a manner that causes loss of data, store a first entry in the first write retry buffer, the first memory device to also output a first indicator that indicates whether the first write retry buffer meets a threshold criteria associated with an amount of unused entries in the first write retry buffer;
a second memory device disposed on the module and including a second write retry buffer, the second memory device to, based on a second verify operation performed by the second memory device determining a second attempted write failed in a manner that causes loss of data, store a second entry in the second write retry buffer; and
a first interface to receive a command from a memory controller, the first memory device to, in response to the command, retry the first attempted write using the first entry, the second memory device to, in response to the command, retry the second attempted write using the second entry.