Patent ID: 11940907
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G

Claim 8:
9. An apparatus comprising:
at least one memory;
instructions; and
at least one processor to execute the instructions to:
generate a sparsity map corresponding to a tensor, the sparsity map to indicate whether a data point of the tensor is zero;
divide the tensor into one or more storage elements;
reallocate an amount of memory for the tensor based on the one or more storage elements exceeding a threshold sparsity;
perform a first compression of the one or more storage elements to generate one or more first compressed storage elements, the first compression to remove data points of the one or more storage elements based on the sparsity map;
perform a second compression of the one or more first compressed storage elements, the second compression to store the one or more first compressed storage elements contiguously in memory of a first compute unit;
rotate the one or more storage elements to a target orientation based on a dimensionality of the tensor and a scaling factor including a number of bits in the data point;
determine a data point of a workload of the one or more second compressed storage elements to transmit;
determine a border region of the workload to transmit based on whether a data point of the workload is located within a border width and border height of the one or more second compressed storage elements; and
replicate the border region to a memory of a second compute unit.