Patent ID: 11887674
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory apparatus, comprising:
memory cells each connected to one of a plurality of word lines and disposed in strings coupled to one of a plurality of bit lines and configured to retain a threshold voltage corresponding to one of a plurality of data states; and
a control means coupled to the plurality of word lines and the plurality of bit lines and configured to:
read each of the memory cells in a read operation, and
for each one of the memory cells, offset at least one of a bit line settling time and a kick voltage applied to the one of the plurality of bit lines coupled to the one of the memory cells during the read operation based on a probability of at least one neighboring one of the plurality of bit lines being coupled to the memory cells retaining the threshold voltage corresponding to a different one of the plurality of data states than the one of the memory cells.