Patent ID: 11901375
Assignee: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. An array substrate having a display area and a bonding area located on a side of the display area; the array substrate comprising:
a base;
a plurality of first transistors disposed on a side of the base and located in the display area, and a first transistor including a first gate, a first source, and a first drain;
a plurality of conductive pins disposed on the side of the base and located in the bonding area, and the plurality of conductive pins being disposed in a same layer as the first gate; and
a plurality of conductive electrodes each disposed on a respective one of surfaces of the plurality of conductive pins away from the base.