Patent ID: 11902132
Assignee: INTEL CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 5:
6. The circuit system of claim 5, wherein the variable latency circuit further comprises:
a second subtractor circuit that subtracts a fourth latency of a second data path from a fifth latency of a third data path to generate the measured latency of the first data path, wherein the third data path comprises the digital-to-analog converter circuit, a loopback connection, and the analog-to-digital converter circuit, and wherein the second data path comprises the analog-to-digital converter circuit; and
a measurement circuit that measures the fourth latency of the second data path based on a timing difference between a reference timing signal and a second timing signal that incurs a same latency as data propagating through the second data path.