Patent ID: 11863190
Assignee: nan
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. The compound sequential circuit of claim 14,
wherein the first sequence detector configured to activate a first differential sub-circuit of the latch in response to:
(1) the first output of the latch being at a second level,
(2) the input signal being at a first level, and
(3) a main clock signal being at the first level;
wherein the first differential sub-circuit of the latch is deactivated when the main clock signal is at the second level;
wherein the second sequence detector configured to activate a second differential sub-circuit of the latch in response to:
(1) the first output of the latch being at a first level,
(2) the input signal being at a second level, and
(3) a main clock signal being at the first level;
wherein the second differential sub-circuit of the latch is deactivated when the main clock signal is at the second level;
wherein the first differential sub-circuit of the latch and second differential sub-circuit of the latch are electrically coupled to the third shared clock node; and
wherein the inputs of the first keeper sub-circuit have the same logic polarities compared to the inputs of the first sequence detector, and wherein the inputs of the second keeper sub-circuit have the same logic polarities compared to the inputs of the second sequence detector.