Patent ID: 11971847
Assignee: XDL TECHNOLOGIES INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 8:
9. A method, comprising:
executing a first instruction at a reconfigurable processing element (PE) in a plurality of columns a number of times according to a first configuration, the reconfigurable PE being configured to be part of a first physical data path during the first configuration;
delivering an execution result from the reconfigurable PE to a temporary data storage to temporality store the execution result after each execution of the first instruction; and
feeding the execution result stored in the temporary data storage to a second physical data path;
wherein the reconfigurable PE is one PE of a plurality of processing elements (PEs) arranged in a plurality of columns with each column including at least one PE, each of the plurality of PEs including a plurality of arithmetic logic units (ALUs) configured to execute a same instruction in parallel threads, wherein the plurality of columns are coupled for data to flow from a preceding column to a succeeding column in a direction from a first column to a last column of the plurality of columns, and the temporary data storage is configured to store data received from the last column and to provide the data stored to the first column;
wherein a sequencer is coupled to the plurality of PEs and configured to distribute decoded instructions packaged as configurations to the plurality of PEs;
wherein the processor further comprises a plurality of switch boxes (SBs) arranged in the plurality of columns with each SB associated with one of the plurality of PEs for the plurality of switch boxes to collectively provide data switching for the plurality of PEs.