Patent ID: 11881136
Assignee: NOVATEK MICROELECTRONICS CORP.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A display driver for driving a display panel, comprising:
at least one first latch configured to receive input data;
at least one second latch with an input terminal thereof coupled to an output terminal of the at least one first latch;
an output buffer, comprising at least one variable current source, coupled to the at least one second latch; and
a comparator coupled to the at least one first latch, the at least one second latch, and the at least one variable current source and configured to generate at least one control signal of the at least one variable current source;
wherein the comparator includes:
a first logic circuit coupled to the at least one first latch and the at least one second latch;
a register coupled to the first logic circuit; and
a second logic circuit coupled to the register and the at least one variable current source;
wherein the first logic circuit includes:
a first inverter and a second inverter coupled to the at least one first latch;
a third inverter and a fourth inverter coupled to the at least one second latch;
a first NAND gate coupled to the first inverter, the third inverter, and the fourth inverter;
a second NAND gate coupled to the first inverter, the second inverter, and the third inverter;
a third NAND gate coupled to the first inverter, the second inverter, and the third inverter;
a fourth NAND gate coupled to the first inverter, the third inverter, and the fourth inverter;
a fifth NAND gate coupled to the first NAND gate, the second NAND gate, the third NAND gate, the fourth NAND gate, and the register;
a first XOR gate coupled to the at least one first latch and the at least one second latch;
a second XOR gate coupled to the at least one first latch and the at least one second latch;
a first NOR gate coupled to the first XOR gate and the second XOR gate; and
a second NOR gate coupled to the first NOR gate, the fifth NAND gate, and the register.