Patent ID: 11908948
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 5:
6. A memory device, comprising:
a stack structure including tiers each comprising conductive material and insulative material vertically neighboring the conductive material, the stack structure having a memory array region and a staircase region horizontally neighboring the memory array region;
strings of memory cells within a horizontal area of the memory array region and vertically extending through the stack structure;
a staircase structure within a horizontal area of the staircase region and having steps comprising horizontal ends of at least some of the tiers of the stack structure;
conductive contact structures in contact with the conductive material of the at least some of the tiers of the stack structure at the steps of the staircase structure; and
vertical transistors vertically overlying the stack structure and within the horizontal area of the staircase region, at least one of vertical transistors comprising:
indium-containing material having:
a bottom section coupled to one of the conductive contact structures;
a top section vertically overlying the bottom section; and
a middle section vertically extending from and between the bottom section and the top section, the middle section having a lower atomic concentration of indium than each of the bottom section and the top section and comprising:
a lower surface in physical contract with and substantially confined within a horizontal area of an upper surface of the lower section of the indium-containing material, the lower surface of the middle section of the indium-containing material having a smaller horizontal area than the horizontal area of the upper surface of the lower section of the indium-containing material;
outer side surfaces in physical contract with dielectric material, the outer side surfaces comprising:
 a lowermost vertical boundary substantially coplanar with a lowermost vertical boundary of the dielectric material; and
 an uppermost vertical boundary substantially coplanar with an uppermost vertical boundary of the dielectric material; and
inner side surfaces opposing the outer side surfaces and in physical contact with dielectric fill material having an upper surface vertically underlying the uppermost vertical boundary of the dielectric material, the inner side surfaces comprising:
 a lowermost vertical boundary vertically overlying the lowermost vertical boundary of the dielectric material; and
 an uppermost vertical boundary substantially coplanar with the uppermost vertical boundary of the dielectric material;

conductive gate material horizontally neighboring and within vertical boundaries of the middle section of the indium-containing material; and
the dielectric material, the dielectric material horizontally extending from and between the middle section of the indium-containing material and the conductive gate material.