Patent ID: 11973082
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 18:
19. An integrated circuit device comprising:
a semiconductor on insulator (SOI) substrate layer comprising a base substrate layer, an insulating substrate layer, and a cover substrate layer in a first region;
a semiconductor substrate layer in a second region different from the first region;
a first impurity region in a portion of the SOI substrate layer comprising a first impurity type;
a second impurity region in a portion of the semiconductor substrate layer comprising a second impurity type;
a plurality of first fin-type active areas and a plurality of second fin-type active areas defined by a plurality of trenches and extending in a first horizontal direction, on the SOI substrate layer and the semiconductor substrate layer, respectively;
a plurality of nanosheet stacked structures each comprising a plurality of nanosheets extending in parallel with each other and spaced apart from upper surfaces of the plurality of first fin-type active areas and the plurality of second fin-type active areas;
a plurality of first source/drain regions connected to ends of the plurality of nanosheets adjacent to each other on the plurality of first fin-type active areas, the plurality of first source/drain regions extending through the cover substrate layer and into the insulating substrate layer, and comprising lower surfaces that are at a first vertical level;
a plurality of second source/drain regions extending into the semiconductor substrate layer and contacting the second impurity region on the plurality of second fin-type active areas, the plurality of second source/drain regions comprising lower surfaces that are at a second vertical level that is higher than the first vertical level;
a plurality of gate electrodes extending in a second horizontal direction that crosses the first horizontal direction, the plurality of gate electrodes extending on the plurality of first fin-type active areas and the plurality of second fin-type active areas, each of the plurality of gate electrodes comprising a main gate unit above a respective one of the plurality of nanosheet stacked structures, and a plurality of sub-gate units each underneath a respective nanosheet of the plurality of nanosheets of the respective one of the plurality of nanosheet stacked structures;
a gate dielectric layer arranged between the plurality of gate electrodes and the plurality of nanosheets; and
a plurality of insulating spacers in the first region between the plurality of first fin-type active areas and the plurality of nanosheets, the plurality of insulating spacers covering first and second ends of each of the plurality of sub-gate units with the gate dielectric layer therebetween.