Patent ID: 11943728
Assignee: BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC.
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A method for clock synchronization for use in high speed asynchronous serial interfaces, comprising:
receiving, on a first device, an ingress traffic from a second device;
decoding, on the first device, the ingress traffic using 8B10B;
splitting, via a traffic splitter on the first device, the ingress traffic into an ingress regular traffic and a calibration feedback traffic;
processing, on the first device, the calibration feedback traffic via a calibration message receiver;
tuning, on the first device, a clock frequency based on the calibration feedback traffic;
encoding, on the first device, a signal comprising at least one active message and an idle traffic using 8B10B to form a stream of K28.5 characters;
transmitting to the second device, via the first device, a signal comprising the encoded at least one active message and the idle traffic with an adjusted frequency;
receiving, on the second device, the signal comprising the at least one active message and the encoded idle traffic from the first device;
decoding, on the second device, the signal using 8B10B;
splitting, via a traffic splitter on the second device, the signal into an ingress regular traffic and an ingress idle traffic;
monitoring, on the second device, the ingress idle traffic to determine an amount of K28.5 characters;
starting, on the second device, an error check if the amount of K28.5 characters is above a threshold value;
generating, on the second device, a count-up or count-down signal via an up/down counter;
generating, on the second device, a calibration message comprising a calibration feedback traffic from the up/down counter;
merging, on the second device, the calibration message with the at least one active message to form a feedback message;
encoding, on the second device, the feedback message using 8B10B;
transmitting, via the second device, the feedback message to the first device; and
repeating preceding steps for a plurality of sample intervals, thereby reducing a probability of data sampling failure for high speed asynchronous serial interfaces.