Patent ID: 11916561
Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 12:
13. The clock generator of claim 12, wherein the state is one of a first state, a second state, a third state, or a fourth state,
wherein in the first state, the first phase-detector output and second phase-detector output are both logic low, and the phase interpolator shift is left,
wherein in the second state, the first phase-detector output and second phase-detector output are both logic high, and the phase interpolator shift is right,
wherein in the third state, the first phase-detector output is logic high and the second phase-detector output is logic low, and the phase interpolator shift is left,
wherein in the fourth state, the first phase-detector output is logic low and the second phase-detector output is logic high, and the phase interpolator shift is left.