Patent ID: 11915739
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. An apparatus, comprising:
a power bus supplying power to a component of a memory device and having a first rail and a second rail;
a noise source circuit generating a plurality of noise source signals that simulate a real-world noise;
a multiplexer circuit configured to select and output a noise source signal from the plurality of noise source signals;
a pulse generator circuit connected to the multiplexer circuit to receive the noise source signal and output at least one noise profile signal based on the noise source signal; and
a bus shorting circuit connected to the pulse generator circuit to receive the at least one noise profile signal, the bus shorting circuit having at least one transistor connected between the first rail and the second rail of the power bus,
wherein the bus shorting circuit is configured, based on the at least one noise profile signal, to intermittently connect the at least one transistor between the first rail to the second rail to induce noise on the power bus,
wherein the at least one transistor is a plurality of transistors connected in parallel between the first rail and the second rail,
wherein the at least one noise profile signal is a plurality of noise profile signals, each noise profile signal corresponding to a transistor of the plurality of transistors and controlling the operation of the respective transistor, and
wherein the apparatus further comprises:
a noise profile circuit connected to the pulse generator circuit and configured to at least one of enable one or more first noise profile signals of the plurality of noise profile signals or set a pulse width of a noise profile signal.