Patent ID: 11894250
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 6:
7. A method, comprising:
performing a plasma assisted semiconductor process on a semiconductor wafer in a semiconductor process chamber including a top electrode and the semiconductor wafer positioned on a bottom electrode, wherein the plasma assisted process generates an anode glow region adjacent to the top electrode, a cathode glow region adjacent to the bottom electrode and a plasma region between the anode glow region and the cathode glow region;
capturing, with a plurality of groups of cameras positioned around the semiconductor process chamber from different angles and positions, a plurality of images of the semiconductor process chamber, each group including an infrared camera, a visible light camera and an ultraviolet camera;
generating a 3D model of the plasma within the semiconductor process chamber based on the images; detecting, during the plasma assisted semiconductor process with a control system communicatively coupled to the one or more cameras, arcing between the top electrode and the wafer through the anode glow region, the plasma region and the cathode glow region within the semiconductor process chamber based on the 3D model;
determining a location of the arcing on the semiconductor wafer within the semiconductor processing chamber based on the images and angles and positions of the cameras; and
adjusting the semiconductor process within the semiconductor process chamber during the plasma assisted semiconductor process responsive to detecting arcing within the semiconductor process chamber.