Patent ID: 11887897
Assignee: TOKYO ELECTRON LIMITED
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 1:
2. The method of claim 1, wherein forming a first vertical channel structure includes:
forming a first type channel material on the semiconductor layer of the substrate within the first opening until covering the vertical sidewall of the first metal layer of the metal layers of the multilayer stack to form the first source region of the first vertical channel structure;
forming a first gate material on the first source region until covering the vertical sidewall of the second metal layer of the metal layers of the multilayer stack above the first metal layer to form the first gate material of the first vertical channel structure; and
forming the first type channel material on the first source region and the first gate region until covering the vertical sidewall of the third metal layer of the metal layers of the multilayer stack above the second metal layer to form the first drain region of the first vertical channel structure.