Patent ID: 11881278
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. The method of claim 2, further comprising: before acquiring the number of assignable local redundant circuits and the number of assignable global redundant circuits in the preset subdomain,
dividing a memory cell array bank of memory into a plurality of global regions;
dividing any one of the global regions into a plurality of segments;
dividing any one of the segments into a plurality of subdomains,
wherein the assignable global redundant circuits in any segment are not crossed with the assignable global redundant circuits in other segments in a same global region; and the assignable local redundant circuits in any subdomain are not crossed with the assignable local redundant circuits in other subdomains in a same segment.