Patent ID: 11888620
Assignee: INTEL CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 2:
3. The apparatus of claim 1 wherein the PPDU is a first PPDU, the MMPDU is a first MMPDU, the sequence number is a first sequence number, the frame body is a first frame body, and wherein the processing circuitry is further configured to:
receive a second MMPDU, the second MMPDU comprising a second sequence number, a second frame body, and an address 2 field, the address 2 field indicating an address of a third STA affiliated with a third MLD;
determine whether a receiver cache of the first MLD indicates that a third MMPDU has been received from the third STA of the third MLD, the third MMPDU having the second sequence number, wherein the receiver cache is indexed by a MLD MAC address of the third MLD and the second sequence number; and
in response to a determination that the third MMPDU has been received, discard the second MMPDU.