Patent ID: 11929286
Assignee: TESSERA LLC
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor structure fabrication method comprising:
forming a first fin and a second fin from a substrate material, the first and second fins being separated by a bottom well surface and each fin having (i) a first sidewall upper portion, (ii) a first sidewall lower portion, (iii) a second sidewall upper portion, (iv) a second sidewall lower portion, and (v) a top surface;
forming a well plug on exposed surfaces of the substrate material, the exposed surfaces comprising the bottom well surface, the first sidewall lower portion, and the second sidewall lower portion,
forming a 2D material upon (i) the top surface of the first fin, (ii) the first sidewall upper portion of the first fin, (iii) the second sidewall upper portion of the first fin, (iv) the top surface of the second fin, (v) the first sidewall upper portion of the second fin, and (vi) the second sidewall upper portion of the second fin; and
forming a single transistor having a first discrete channel formed from the 2D material on the first fin and a second discrete channel formed from the 2D material on the second fin, wherein the 2D material is not disposed upon (i) the first sidewall lower portion of the first fin, (ii) the second sidewall lower portion of the first fin, (iii) the first sidewall lower portion of the second fin, (iv) the second sidewall lower portion of the second fin, (v) the bottom well surface and (vi) a central portion of an upper surface of the well plug.