Patent ID: 11935616
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 11:
12. The comparison system of claim 11, wherein the M decoding units each comprises:
a decoder, configured to receive the X first operation codes and output N first decoded signals, each of the N first decoded signals corresponding to a respective one bit of the N data;
a first AND gate unit, configured to receive at least two selected operation codes and perform a logical AND operation, the at least two selected operation codes being second operation codes obtained by performing the fourth encoding operation on a subset of the Y second check codes corresponding to the respective one of the M bytes;
an NOR gate unit, configured to receive at least two unselected operation codes and perform a logical NOR operation, the at least two unselected operation codes being second operation codes other than the at least two selected operation codes corresponding to the respective one of the M bytes; and
N second AND gate units, each having an input terminal connected to an output terminal of the first AND gate unit, an output terminal of the NOR gate unit and one of the N first decoded signals, wherein a position of erroneous data is acquired based on outputs of the N second AND gate units.