Patent ID: 11936384
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 8:
9. The multi-bit flip-flop of claim 1, wherein the second latch comprises:
a first inverter configured to receive the fifth data bit;
a first NOR gate configured to receive an output of the first inverter as a first input and a reset signal as a second input, and output the sixth data bit; and
a first transmission gate configured to transfer the sixth data bit to an input of the first inverter in synchronization with the clock signal and the inverse clock signal, and
the fourth latch comprises
a second inverter configured to receive the tenth data bit;
a second NOR gate configured to receive an output of the second inverter as a first input and the reset signal as a second input, and output the eleventh data bit; and
a second transmission gate configured to transfer the eleventh data bit to an input of the second inverter in synchronization with the clock signal and the inverse clock signal.