Patent ID: 11861220
Assignee: IMAGINATION TECHNOLOGIES LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 4:
5. A processing system implemented in hardware, comprising:
a plurality of logical memories; and
at least one processor, implementing:
a first group counter,
a task creation circuit configured to create tasks, each of the tasks comprising a plurality of separate instances, each instance operating on a different data item,
a scheduler configured to group instances of one of the tasks into at least two groups, and
an address generation circuit configured, for each group of the at least two groups, to map registers referenced by the group to a same one of the plurality of logical memories based on a pre-defined allocation scheme and adjusted by a first group counter value, wherein the pre-defined allocation scheme traverses the logical memories in a pre-defined sequence;, and wherein either the task creation circuit or the scheduler is further configured to adjust the first group counter value for each of the tasks.