Patent ID: 11967389
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A semiconductor apparatus comprising:
a first storage circuit located outside a plurality of memory banks and connected to the plurality of memory banks;
an error correction circuit configured to correct an error bit of data output from the plurality of memory banks;
a read path including a plurality of sub-read paths, one side terminals of the plurality of sub-read paths are connected to the plurality of memory banks and the first storage circuit in common and other side terminals of the plurality of sub-read paths are connected to the error correction circuit; and
a control circuit configured to control the data output from the plurality of memory banks to be simultaneously stored in the first storage circuit by deactivating the read path during a first sub-test section, and to control the data stored in the first storage circuit to be sequentially transmitted to the error correction circuit by sequentially activating the plurality of sub-read paths during a second sub-test section.