Patent ID: 11881262
Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. The resistive random access memory device according to claim 6, wherein the read circuit further comprises: a third isolation transistor and a fourth isolation transistor cross-connected, the control logic block being further configured to produce a drive signal of the respective gates of said third and fourth isolation transistors and wherein:
when said other value is a second value corresponding to a selection of a first logic operation, in particular of the OR type or of the AND type, the control logic block is configured so as to produce a first drive signal, a second drive signal different from the first drive signal, so as to render conducting the first isolation transistor while rendering OFF the second isolation transistor,
when said other value is a third value corresponding to a selection of a second logic operation, in particular of the AND type or of the OR type: transmit a first drive signal and a second drive signal so as to render OFF the first isolation transistor while rendering conducting the second isolation transistor,
when the digital selection signal has a fourth value corresponding to a selection of a third logic operation, in particular of the XOR type, said logic selection block is configured so as to transmit a first drive signal to the gate of the first isolation transistor and a second drive signal to the gate of the second isolation transistor identical to the first drive signal, the third drive signal being in a state different from that of the first drive signal and from the second drive signal.