Patent ID: 11869972
Assignee: INVENTION AND COLLABORATION LABORATORY PTE. LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A transistor structure comprising:
a gate structure based on a semiconductor substrate, wherein the semiconductor substrate comprises a semiconductor surface and is made of a first semiconductor material;
a channel region under the semiconductor surface, the channel region including a first terminal and a second terminal;
a drain region independent from the semiconductor substrate, the drain region including a first predetermined physical boundary directly connected to the first terminal of the channel region;
a source region independent from the semiconductor substrate, the source region including a second predetermined physical boundary directly connected to the second terminal of the channel region;
a first isolator; and
a first etched concave having a first side barrier to reveal a first seed portion of the first semiconductor material and having a second side barrier opposite to the first side barrier, wherein the first isolator is positioned above a bottom of the first etched concave and the drain region is above the first isolator;
wherein between the gate structure and another gate structure next to the transistor structure, the drain region is continuously extended from the first side barrier to the second side barrier without blocked by the first isolator, there is no isolation layer exists in the drain region, and the first side barrier is adjacent to a spacer of the transistor structure and the second side barrier is adjacent to a spacer of the neighbor transistor structure;
wherein the first isolator is limited within the first etched concave and no other isolator is extended underneath the gate structure.