Patent ID: 11894372
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method, comprising:
forming a semiconductor substrate;
forming a first semiconductor layer above the semiconductor substrate;
forming a second semiconductor layer above the first semiconductor layer;
patterning a first fin from portions of the semiconductor substrate, the first semiconductor layer and the second semiconductor layer;
forming a dummy gate material around the fin;
performing a selective etch that removes remaining portions of the first semiconductor layer to form an upper fin and a lower fin from the first fin;
forming a conformal dielectric layer on the upper and lower fin, between the upper and lower fin, and on the dummy gate material;
removing portions of the upper fin and the lower fin that are located on a first and a second side of the dummy gate that extend beyond the dummy gate; and
forming a dielectric isolation structure and gate spacers by removing portions of the conformal dielectric layer.