Patent ID: 11914508
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 20:
21. A controller for wear leveling a nonvolatile memory having a plurality of erase units, each erase unit including nonvolatile access units specified by respective nonvolatile-access-unit addresses, the controller comprising:
means for writing data the nonvolatile access units, the data including eldest data in the nonvolatile memory and next data to be written to the nonvolatile memory;
a head register to store, as a head nonvolatile address, the nonvolatile-access-unit address of a next one of the nonvolatile access units to receive the next data;
a tail register to store, as a tail nonvolatile address, the nonvolatile-access-unit address of one of the nonvolatile access units in the one of the erase units storing the eldest data, the head nonvolatile address and the tail nonvolatile address defining between them a group of the erase units with valid data and invalid data, the group including the one of the erase units storing the eldest data; and
means for comparing the head nonvolatile address with the tail nonvolatile address to initiate a garbage-collection process that erases the eldest data.