Patent ID: 11956960
Assignee: SK HYNIX INC.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 8:
9. A semiconductor device, comprising:
a gate stack with conductive layers and insulating layers that are stacked alternately with each other;
a first channel pattern passing through the gate stack, wherein the first channel pattern has a first width;
a second channel pattern coupled to the first channel pattern, the second channel pattern protruding above a top surface of the gate stack, wherein the second channel pattern has a second width smaller than the first width;
an insulating core formed in the first channel pattern, the insulating core extending into the second channel pattern;
a gate liner having a first portion and a second portion, wherein the first portion covers the top surface of the gate stack except a portion surrounded by the first channel pattern, and the second portion surrounds a portion of a sidewall of the second channel pattern; and
a barrier pattern coupled to the gate liner, the barrier pattern surrounding a remaining portion of the sidewall of the second channel pattern,
wherein an inner diameter of the second portion is narrower than an inner diameter of an open area of the first portion surrounding the first and second channel patterns.