Patent ID: 11933846
Assignee: KIOXIA CORPORATION
Field: Measurement (Instruments)
Classification: CPC G | IPC G

Claim 0:
1. A memory tester comprising:
a first memory configured to store scan input data and expected value data, the scan input data including a don't care bit, the expected value data being obtained by converting the don't care bit of the scan input data into a first predetermined value;
a second memory configured to store scan output data and mask data, the scan output data being outputted from a scan test circuit, the mask data being obtained by converting a value of the scan input data other than the don't care bit into a second predetermined value;
an arithmetic circuit configured to perform an exclusive or operation between the expected value data and the scan output data; and
a determination circuit configured to determine whether the don't care bit of an arithmetic result from the arithmetic circuit is passed or failed by using the mask data,
wherein the scan input data are divided into groups of a predetermined number of bits, and are stored in the first memory in a state where a bit string of data obtained by division and having the predetermined number of bits is inverted.