Patent ID: 11886377
Assignee: CORNAMI, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G  H

Claim 50:
51. A reconfigurable arithmetic circuit comprising:
a plurality of input reordering queues configured to store a plurality of inputs, the plurality of input reordering queues further comprising:
input reordering logic circuitry configured to reorder a sequence of the plurality of inputs, and further configurable to adjust a sign bit for negate and absolute value functions, to de-interleave in-phase (“I”) and quadrature (“Q”) data inputs, and to de-interleave odd and even data inputs;

a multiplier shifter and combiner network coupled to the plurality of input reordering queues, the multiplier shifter and combiner network comprising:
a shifter circuit; and
a plurality of series-coupled adder circuits coupled to the shifter circuit;

an accumulator circuit; and
at least one control logic circuit coupled to the multiplier shifter and combiner network and to the accumulator circuit.