Patent ID: 11955395
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A semiconductor device, comprising:
a first passive device having a top side and a bottom side, and a first sidewall and a second sidewall between the top side and the bottom side, the second sidewall opposite the first sidewall, and the first passive device having a lateral width between the first sidewall and the second sidewall;
a material for encapsulating the first passive device, the material laterally adjacent to the first passive device, a first portion of the material in contact with the first sidewall of the first passive device, and a second portion of the material in contact with the second sidewall of the first passive device;
a second passive device laterally spaced apart from the first passive device, the second passive device in contact with the material for encapsulating the first passive device;
a plurality of successive dielectric layers and layers of electrical traces, the plurality of successive dielectric layers and layers of electrical traces on the top side of the first passive device, the plurality of successive dielectric layers and layers of electrical traces on the first portion of the material, the plurality of successive dielectric layers and layers of electrical traces on the second portion of the material, and the plurality of successive dielectric layers and layers of electrical traces including an electrical trace coupled to the top side of the first passive device, the electrical trace extending from a location vertically over the first passive device to a location laterally outside of the lateral width of the first passive device;
a conductive structure coupled to the electrical trace of the integrated routing layer, the conductive structure vertically above an uppermost one of the plurality of succesive dielectric layers of the integrated routing layer, wherein the conductive structure is not in contact with the uppermost one of the plurality of succesive dielectric layers of the integrated routing layer; and
a solder ball above and vertically overlapping with the second passive device.