Patent ID: 11861283
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A placement method of integrated circuit design for a computer system, wherein a placement region is divided into a plurality of grids, a plurality of cells form a plurality of nets, each of the nets connects at least two of the cells, and the placement method comprises:
taking the cells as a plurality of clusters, and merging the clusters in each of a plurality of levels from bottom to up;
performing an initial placement; and
disassembling the clusters in each of the levels from the up to the bottom and performing a first placement procedure comprising:
setting a bounding box for each of the nets, wherein the bounding box covers at least one first grid of the grids;
for each of the nets, calculating a routing congestion penalty according to an overlapping area between the bounding box and the at least one first grid and an overflow value of the at least one first grid; and
establishing a first objective function according to the routing congestion penalties of the nets to determine locations of the clusters so that the first objective function outputs a first optimal value.