Patent ID: 11906547
Assignee: INTEL CORPORATION
Field: Measurement (Instruments)
Classification: CPC G  C | IPC G

Claim 16:
17. A system comprising:
a test circuit configured to receive a device-under-test (DUT) and to run test programs on the DUT, the test circuit having a test circuit electric reference potential serving as a circuit ground for the test circuit;
a metallic thermal contact surface configured to contact the DUT connected to the test circuit and operable to regulate a temperature of the DUT when in contact with the DUT during testing;
a chassis electric reference potential for electrostatic discharge grounding of a tester chassis; and
an electrical insulation arrangement connected between the metallic thermal contact surface and the chassis electric reference potential to insulate the metallic thermal contact surface from the chassis electric reference potential,
wherein an electric potential difference exists between the chassis electric reference potential and the test circuit electric reference potential.