Patent ID: 11971821
Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 32:
33. The method as claimed in claim 30, further comprising:
through the memory ordering buffer of the first core and a channel between the first die and a second die, providing the write-back and invalidation request to a third in-core cache module of a third core of a second processor fabricated on the second die;
operating the third in-core cache module to provide the write-back and invalidation request to a second last-level cache within the second processor;
in response to the write-back and invalidation request, operating the second last-level cache to search itself to determine which cache lines within the second last-level cache match the designated key identification code, wherein: if a matched cache line has been modified and does not exist in any upper-level cache, the second last-level cache writes back the matched cache line to the system memory; and, whether modified or not, all matched cache lines within the second last-level cache are invalidated; and
after all matched cache lines within the second last-level cache are invalidated, operating the second last-level cache to return a third synchronization signal to the third in-core cache module, wherein, in response to the third synchronization signal, the third in-core cache module in the waiting state is awakened to search itself to determine which cache lines within the third in-core cache module match the designated key identification code, wherein: if a matched cache line has been modified, the third in-core cache module writes back the matched cache line to the system memory; and, whether modified or not, all matched cache lines within the third in-core cache module are invalidated.