Patent ID: 11968828
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 5:
6. A method, comprising:
forming an isolation feature in a semiconductor substrate, wherein a first region and a second region in a peripheral region of the semiconductor substrate are defined on two opposite sides of the isolation feature;
forming a first dielectric layer over the first region and the second region of the semiconductor substrate;
removing a first portion of the first dielectric layer over a first portion of the first region of the semiconductor substrate and a second portion of the first dielectric layer over the second region of the semiconductor substrate, such that a third portion and a fourth portion of the first dielectric layer remain on the first region, and the second region of the semiconductor substrate and a first portion of the isolation feature abutting the second region are exposed from the third and fourth portions of the first dielectric layer, wherein the fourth portion of the first dielectric layer is in contact with a second portion of the semiconductor substrate in the first region and a second portion of the isolation feature abutting the first region but spaced apart from a top surface of the first portion of the isolation feature abutting the second region;
after removing the first and second portions of the first dielectric layer, forming a second dielectric layer over the first region and the second region of the semiconductor substrate to cover the third and fourth portions of the first dielectric layer;
forming a dummy gate layer on a first portion of the second dielectric layer;
patterning the dummy gate layer, the second dielectric layer and the first dielectric layer to form a first gate stack over the first region and a second gate stack over the second region;
replacing the dummy gate layer with a conductive layer;
prior to forming the dummy gate layer, removing a second portion of the second dielectric layer over the second region;
after removing the second portion of the second dielectric layer, forming an interfacial layer over the second region; and
forming a third dielectric layer over the semiconductor substrate and in contact with the first portion of the second dielectric layer.