Patent ID: 11933815
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Measurement (Instruments)
Classification: CPC G | IPC G

Claim 8:
9. A test fixture, comprising:
a signal test board, wherein the signal test board comprises a first surface, and a second surface opposing the first surface, the first surface has at least one first pin, and at least one test point located around the first pin, and the second surface has at least one second pin;
at least one circuit routing located in the signal test board and configured to connect the at least one first pin and corresponding at least one second pin, wherein a portion of the circuit routing comprises an upper routing connected with one of the at least one first pin, a lower routing connected with one of the at least one second pin, and a via-hole routing connected with two ends of the upper routing and the lower routing, and wherein one end, connected with the via-hole routing, of the upper routing is located in a projection area of a corresponding test point; and
a branch routing located in the signal test board and configured to connect the at least one test point with a corresponding upper routing;, wherein
the test fixture further comprises a PCB main board, a packaged chip to be tested, and a padding board;
the packaged chip to be tested has at least one third pin, the PCB main board has a functional circuit, and at least one fourth pin connected with the functional circuit;
the padding board comprises a third surface and a fourth surface opposing each other;
the third surface has at least one fifth pin, the fourth surface has at least one sixth pin, and the padding board has at least one connecting line for connecting the at least one fifth pin with a corresponding at least one sixth pin;
the packaged chip to be tested is located on the first surface of the signal test board, the at least one third pin on the packaged chip to be tested is connected with a corresponding at least one first pin on the signal test board;
the padding board is located on the second surface of the signal test board, and the at least one fifth pin on the padding board is connected with a corresponding at least one second pin on the signal test board;
the PCB main board is located on the sixth surface of the padding board; and
the at least one fourth pin on the PCB main board is connected with a corresponding at least one sixth pin on the padding board.