Patent ID: 11876500
Assignee: FUJITSU SEMICONDUCTOR MEMORY SOLUTION LIMITED
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. An operation method of a receiver including a first matching circuit and a second matching circuit that receive antenna input power through a branch point in accordance with a radio signal received by an antenna, the antenna input power being input from the antenna, the first matching circuit inputting a portion of the received antenna input power to a first circuit as first input power, the second matching circuit inputting another portion of the received antenna input power to a second circuit as second input power, and at least either the first matching circuit or the second matching circuit including a delay element, the operation method comprising:
delaying, by the delay element, a phase of a first input signal or a phase of a second input signal so that an impedance of the first matching circuit decreases as the antenna input power increases and an impedance of the second matching circuit increases as the antenna input power increases, the first input power supplied to the first circuit and the second input power supplied to the second circuit being controlled by the impedance of the first matching circuit and the impedance of the second matching circuit,
wherein with the impedance of the first matching circuit being high relative to the impedance of the second matching circuit, more of the antenna input power is supplied to the second circuit than to the first circuit, and
wherein with the impedance of the second matching circuit being high relative to the impedance of the first matching circuit, more of the antenna input power is supplied to the first circuit than to the second circuit.