Patent ID: 11862634
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 6:
7. A semiconductor structure, comprising:
a first device region formed over a substrate, wherein the first device region comprises:
first silicon-containing layers stacked and spaced apart from each other in a first direction;
second silicon-containing layers stacked and spaced apart from each other in the first direction and spaced apart from the first silicon-containing layers in a second direction different from the first direction; and
a first gate structure wrapping around the first silicon-containing layers and the second silicon-containing layers, wherein the first gate structure has a first curved bottom surface between the first silicon-containing layers and the second silicon-containing layers; and

a second device region formed over the substrate, wherein the second device region comprises:
third silicon-containing layers stacked and spaced apart from each other in the first direction;
fourth silicon-containing layers stacked and spaced apart from each other in the first direction and spaced apart from the third silicon-containing layers in the second direction; and
a second gate structure wrapping around the third silicon-containing layers and the fourth silicon-containing layers, wherein the second gate structure has a second curved bottom surface between the third silicon-containing layers and the fourth silicon-containing layers,

wherein a lowest portion of the first curved bottom surface of the first gate structure is higher than a lowest portion of the second curved bottom surface of the second gate structure.