Patent ID: 11881480
Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 14:
15. The method according to claim 14, wherein a process of forming the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure includes:
forming a first initial gate structure in the first gate opening, in the first groove, and in the second groove, wherein the first initial gate structure spans the first nanostructure, the second nanostructure, and the first isolation structure;
forming a second initial gate structure in the second gate opening, in the third groove, and in the fourth groove, wherein the second initial gate structure spans the third nanostructure, the fourth nanostructure, and the second isolation structure; and
planarizing the first initial gate structure and the second initial gate structure until the top surface of the first isolation structure is exposed, forming the first gate structure and the second gate structure on the first region, and forming the third gate structure and the fourth gate structure on the second region.