Patent ID: 11962324
Assignee: UNIVERSITY OF NOTRE DAME DU LAC
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for lowering an error floor of a low-density parity-check (“LDPC”) decoder chip, thereby improving bit-error-rate and/or frame-error-rate performance of the LDPC decoder chip, the method comprising:
for each message passed from a check node to a variable node, computing a check node log-likelihood ratio within a check node processing unit of the LDPC decoder chip by iteratively passing quantized messages between processing units on a decoder chip, wherein a plurality of check nodes are connected to a respective variable node and wherein a plurality of variable nodes are connected to a respective check node, and wherein the connections are specified by a parity-check matrix of LDPC code, wherein computing further comprises:
comparing a minimum value of a set of variable node log-likelihood ratio magnitudes that are input into the check node processing unit with a threshold, wherein each of the input variable node log-likelihood ratio magnitudes are one of a plurality connected to a respective check node;

based on the results of the comparison, determining at the check node processing unit whether to apply a reduction to a check node log-likelihood ratio magnitude or not to apply a reduction to the check node log-likelihood ratio magnitude;
applying a reduction to the check node log-likelihood ratio magnitude in instances when the determining step determines that a reduction should be applied; and
not applying a reduction to the check node log-likelihood ratio magnitude in instances when the determining step determines that a reduction should not be applied.