Patent ID: 11915925
Assignee: DAICEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC C  H | IPC H

Claim 0:
1. A method of manufacturing a semiconductor device, the method comprising:
preparing a wafer laminate having a laminated structure, the laminate structure comprising at least a first wafer including an element forming surface having a wiring pattern, a second wafer with a thickness from 1 to 20 μm having a main surface and a back surface opposite from the main surface, and an adhesive layer which contains a polymerizable group-containing polyorganosilsesquioxane with a thickness from 0.5 to 4.5 μm interposed between the element forming surface of the first wafer and the back surface of the second wafer;
hole forming to form a hole extending inside the wafer laminate and reaching the wiring pattern of the first wafer by an etching treatment from the second wafer side via a mask pattern masking a portion of the main surface side of the second wafer in the wafer laminate; and
electrode forming to form a through electrode by filling the hole with a conductive material;
wherein the adhesive layer has an etching rate of 1 to 2 μm/min in dry etching performed using an etching gas comprising CF4, O2, and Ar at a volume ratio of 100:400:200 under conditions of an atmospheric pressure of 100 mTorr and a high frequency power supply power of 2000 W.