Patent ID: 11960744
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A device, comprising:
a memory partition;
a plurality of registers, wherein a first register of the plurality of registers when in operation stores a value associated with one of a first configuration setting of a memory device comprising the memory partition, a second configuration setting of a component of the memory device, a first status of the memory device, a second status of the component of the memory device, a first parameter of the memory device, or a second parameter of the component of the memory device, or a predetermined pattern; and
a memory controller that when in operation accesses a first location of the memory partition concurrently with accessing the first register, wherein concurrently accessing the first register comprises initiating access of the first register at a predetermined time during a latency period associated with the access of the first location of the memory partition, wherein the latency period comprises a period of time to access the first location of the memory partition, wherein the predetermined time is selected to allow for completion of the access of the first register during the latency period.