Patent ID: 11948797
Assignee: MITSUBISHI ELECTRIC CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A method for manufacturing a semiconductor device comprising:
applying a lower resist on a semiconductor substrate;
applying an upper resist on the lower resist;
forming a first opening in the upper resist by exposure and development and dissolving the lower resist with a developer upon the development to form a second opening having a width wider than that of the first opening below the first opening so that a resist pattern in a shape of an eave having an undercut is formed;
performing baking to thermally shrink the upper resist to bend an eave portion of the upper resist upward so that a taper angle is in a range from 30° to 90°;
after the baking, forming a metal film on the resist pattern and on the semiconductor substrate exposed at the second opening; and
removing the resist pattern and the metal film on the resist pattern and leaving the metal film on the semiconductor substrate as an electrode.