Patent ID: 11895835
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 16:
17. A finished construction of integrated circuitry comprising a memory array comprising strings of memory cells, comprising:
laterally-spaced memory blocks individually comprising a first vertical stack comprising alternating insulative tiers and conductive tiers, strings of memory cells comprising channel-material strings that extend through the insulative tiers and the conductive tiers, the conductive tiers individually comprising a horizontally-elongated conductive line; and
a second vertical stack aside the first vertical stack, the second vertical stack comprising an upper portion and a lower portion, the upper portion comprising vertically alternating first tiers and second insulating tiers that are of different composition relative one another, the lower portion comprising:
an upper polysilicon-comprising layer;
a lower polysilicon-comprising layer;
an intervening-material layer comprising polysilicon vertically between the upper and lower polysilicon-comprising layers;
an upper intermediate layer vertically between the upper polysilicon-comprising layer and the intervening-material layer;
a lower intermediate layer vertically between the lower polysilicon-comprising layer and the intervening-material layer;
the lower intermediate layer and the upper intermediate layer comprising at least one of (a), (b), and (c), where
(a): a hafnium oxide;
(b): a bilayer comprising silicon nitride and comprising silicon dioxide positioned vertically relative one another, the silicon nitride in the bilayer being closer to the intervening-material layer than is the silicon dioxide in the bilayer; and
(c): SiOxNy, where each of “x” and “y” is from 1 atomic percent to 90 atomic percent of the total of the Si, the O, and the N in the SiOxNy; and

the polysilicon of the intervening-material layer not being within the memory blocks in the finished construction.