Patent ID: 11961890
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor device comprising:
a semiconductor layer having an upper surface;
a dielectric film disposed in the semiconductor layer; and
a gate structure disposed on the semiconductor layer, and including:
a multi-stepped gate dielectric disposed on the semiconductor layer, and including a first gate dielectric portion and a second gate dielectric portion connected to the first gate dielectric portion, the first gate dielectric portion having a flat upper surface, the second gate dielectric portion having a stepped upper surface that includes a flat upper surface portion connected to and flush with the flat upper surface of the first gate dielectric portion, and
a gate electrode disposed on the multi-stepped gate dielectric,

wherein a projection of the dielectric film on the upper surface of the semiconductor layer is non-overlapping with a projection of the second gate dielectric portion on the upper surface of the semiconductor layer, and
wherein the projection of the dielectric film on the upper surface of the semiconductor layer is connected to the projection of the second gate dielectric portion on the upper surface of the semiconductor layer.