Patent ID: 11862250
Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device, comprising:
an array of memory cells arranged in a plurality of blocks; and
a peripheral circuit coupled to the array of memory cells and configured to, in response to a block of the plurality of blocks being an open block, perform a read operation on a memory cell of the array of memory cells in the block using a compensated read voltage, the compensated read voltage having an offset from a default read voltage of the block,
wherein the peripheral circuit comprises:
a register configured to store open block information of one or more blocks of the plurality of blocks, and
control logic coupled to the register and configured to determine that the block is an open block based on the open block information stored in the register.