Patent ID: 11916150
Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A semiconductor device comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor,
wherein one of a source and a drain of the first transistor is electrically connected to a first wiring for inputting a clock signal,
wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring for outputting an output signal,
wherein one of a source and a drain of the second transistor is electrically connected to the second wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to a first power supply line,
wherein one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to a first signal line,
wherein one of a source and a drain of the fourth transistor is electrically connected to the gate of the first transistor,
wherein the other of the source and the drain of the fourth transistor is electrically connected to a second signal line,
wherein one of a source and a drain of the fifth transistor is electrically connected to the gate of the first transistor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the first power supply line,
wherein a gate of the fifth transistor is electrically connected to a gate of the second transistor,
wherein one of a source and a drain of the sixth transistor is electrically connected to the gate of the second transistor,
wherein the other of the source and the drain of the sixth transistor is electrically connected to the first power supply line,
wherein one of a source and a drain of the seventh transistor is electrically connected to the gate of the second transistor,
wherein the other of the source and the drain of the seventh transistor is electrically connected to a second power supply line,
wherein a gate of the seventh transistor is electrically connected to one of a source and a drain of the eighth transistor and one of a source and a drain of the ninth transistor,
wherein one of a source and a drain of the tenth transistor is electrically connected to the gate of the second transistor,
wherein the other of the source and the drain of the tenth transistor is electrically connected to the first power supply line,
wherein a gate of the tenth transistor is electrically connected to the gate of the first transistor, and
wherein a potential of the first power supply line is lower than a potential of the second power supply line.