Patent ID: 11943979
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 2:
3. The array substrate according to claim 1, wherein:
the source/drain metal layer is provided on a side of the active layer that faces away from the base substrate, and the gate metal layer is provided between the active layer and the source/drain metal layer;
the array substrate further comprises a gate insulating layer provided between the active layer and the gate metal layer, and an interlayer insulating layer provided between the gate metal layer and the source/drain metal layer;
the bonding electrode and the source/drain metal layer are provided in a same layer and made of a same material, and a first via hole is provided in the gate insulating layer and the interlayer insulating layer; or, the bonding electrode and the gate metal layer are provided in a same layer and made of a same material, and a first via hole is provided in the gate insulating layer; and
the bonding electrode is electrically connected with the electrostatic barrier line through the first via hole.