Patent ID: 11876526
Assignee: REALTEK SEMICONDUCTOR CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An analog to digital conversion (ADC) apparatus having quick conversion mechanism, comprising:
a plurality of ADC circuits performing cyclic sampling according to sequential timing, configured to:
receive a previous higher-bit conversion result of a previous conversion result to perform prediction on a higher-bit section to generate a current higher-bit conversion result, wherein the previous conversion result is generated by a former ADC circuit of the ADC circuits that finishes performing conversion;
perform conversion on an input analog signal according to different phases of a sampling clock based on a successive-approximation mechanism to generate a current lower-bit conversion result, wherein the sampling clock has a frequency at least twice of the frequency of the input analog signal; and
combine the current higher-bit conversion result and current lower-bit conversion result to generate a current conversion result and output a remained signal amount as a residue; and

a noise-shaping circuit configured to, corresponding to each of the ADC circuits, perform calculation based on the residue from the former ADC circuit of the ADC circuits that finishes performing conversion to generate a noise-shaping reference signal,
wherein each of the ADC circuits combines the current conversion result and the noise-shaping reference signal to generate an output digital signal.