Patent ID: 11881283
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 18:
19. The memory system of claim 17, further comprising:
a first outer bitline of a plurality of bitlines, wherein the first outer bitline extends in the first direction over the first memory cell array and is a farthest one of the plurality of bitlines from the center line in the second direction; and
a second outer bitline of the plurality of bitlines, wherein the second outer bitline extends in the first direction over the first memory cell array and is farthest one of the plurality of bitlines from the first outer bitline in the second direction,
wherein the column selection transistors comprise a plurality of central column selection transistors that comprise respective portions of the central gate pattern, a first outer column selection transistor configured to control electric potential between the first outer bitline and the local sense amplifier, and a second outer column selection transistor configured to control electric potential between the second outer bitline and the local sense amplifier, and
wherein the first outer column selection transistor and the second outer column selection transistor are configured to provide electric potential to the local sense amplifier while the central column selection transistors are turned on and are providing electric potential to the local sense amplifier.