Patent ID: 11901005
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 15:
16. A method, comprising:
reading a data bit from a first memory cell that includes first and second dielectric capacitors configured to store first charges that represent complementary logical values;
latching the data bit at a sense amplifier;
writing the data bit from the sense amplifier back to the first memory cell, via a first bit line, to restore the charge that represents the data bit through the logical value; and
while maintaining the charge that represents the data bit through the logical value at the first memory cell, writing the data bit from the sense amplifier to a second memory cell, via the first bit line, that includes first and second ferroelectric capacitors configured to store second charges that represent complementary logical values.