Patent ID: 11887653
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 7:
8. A memory device comprising:
a row decoder configured to generate a first word line selection signal, a first word line non-selection signal, a second word line selection signal, and a second word line non-selection signal, based on a row address received from an external device;
a first sub-array including a plurality of first memory cells connected to a first word line and a plurality of second memory cells connected to a second word line;
a first sub-word line driver connected to the first word line, and configured to apply a selection voltage to the first word line in response to the first word line selection signal and to apply a non-selection voltage to the first word line in response to the first word line non-selection signal; and
a second sub-word line driver connected to the second word line, and configured to apply the selection voltage to the second word line in response to the second word line selection signal and to apply the non-selection voltage to the second word line in response to the second word line non-selection signal,
wherein the first sub-word line driver is connected to the second word line and is further configured to apply the non-selection voltage to the second word line in response to the second word line non-selection signal, and
wherein the second sub-word line driver is connected to the first word line and is further configured to apply the non-selection voltage to the first word line in response to the first word line non-selection signal.