Patent ID: 11972789
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. The circuit according to claim 13, wherein the first signal generator comprises at least one first generator, wherein
each of the at least one first generators comprises a second NOR gate and a second NOT gate, wherein the second NOR gate has an input terminal as an input terminal of the first generator and an output terminal connected to an input terminal of the second NOT gate, and an output terminal of the second NOT gate serves as an output terminal of the first generator;
input terminals of each of the at least one first generators are connected to some or all bits in the historical maximum decoding information and not lower than the corresponding bit of the comparator, and a combination result of all bits connected to the first generators comprises all the bits in the historical maximum decoding information and not lower than the corresponding bit of the comparator; and
each of the at least one first generators other than a first one is connected to an output terminal of the first generator of a previous stage, and the first generator of a last stage outputs the characteristic signal.