Patent ID: 11892508
Assignee: REALTEK SEMICONDUCTOR CORPORATION
Field: Measurement (Instruments)
Classification: CPC G | IPC G

Claim 0:
1. A joint test action group (JTAG) transmission system comprising:
a slave unit comprising:
a test access port (TAP) circuit comprising a data input terminal, a clock terminal, a mode selection terminal, a first controller, a counter, an address register set, a second controller, and a test data register set;
a memory;
a memory interface controller coupled to the test access port circuit and the memory, and configured to store data transmitted from the test access port circuit to the memory; and

a host unit coupled to the data input terminal, the clock terminal, and the mode selection terminal, and configured to transmit a download instruction set to the test access port circuit to have the test access port circuit select the test data register set, and have the test access port circuit enter a data shift status to receive a data package through the test data register set;
wherein:
the data package comprises an address and at least one piece of write data;
during a process of receiving the data package, the test access port circuit remains in the data shift status to continuously receive the address and the at least one piece of write data in the data package;
the first controller is configured to select the test data register set according to the download instruction set and have the test data register set capture data received from the data input terminal; and
the second controller is configure to:
enter an address receiving status and reset the counter when the first controller has the test data register set start to capture the data received from the data input terminal and has the test access port circuit enter the data shift status;

increment the counter when the clock terminal receives a clock signal in the address receiving status;
determine whether the address has been stored to the test data register set completely according to a value of the counter and an address width of the address; and
when the address has been stored to the test data register set completely, store a value stored in the test data register set to the address register set and complete the address receiving status.