Patent ID: 11870432
Assignee: KABUSHIKI KAISHA TOSHIBA
Field: Electrical machinery, apparatus, energy (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. The electronic circuitry according to claim 3, wherein
the delay circuit includes:
a first circuit including one of a first inverter and two or more cascaded first inverters to reverse or not reverse a bit of one of the first signal and the second signal and transmit the bit; and
a second circuit including one of a second inverter and two or more cascaded second inverters to reverse or not reverse the bit reversed by the one or more first inverters and transmit the bit revised by the one or more first inverters,

wherein the delay circuit, in response to the fourth signal, is configured to control an output response of at least one of the first circuit and the second circuit.