Patent ID: 11871584
Assignee: KEPLER COMPUTING INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 14:
15. A device comprising:
a first region comprising:
a first conductive interconnect within in a first level;
a second level above the first level, the second level comprising:
an electrode structure on at least a portion of the first conductive interconnect, the electrode structure comprising a first conductive hydrogen barrier layer and a first conductive fill material adjacent to the first conductive hydrogen barrier layer;
an insulator layer laterally surrounding the electrode structure;
a memory device on least a portion of the electrode structure, the memory device comprising a ferroelectric material or a paraelectric material;
a first dielectric spanning the first region, the first dielectric comprising an amorphous, greater than 90% film density hydrogen barrier material, wherein the memory device is directly adjacent to and embedded within the first dielectric; and
a via electrode on at least a portion of the memory device, the via electrode comprising:
a second conductive hydrogen barrier layer comprising a first lateral portion on the memory device and first substantially vertical portions directly adjacent to the first dielectric;
a second conductive fill material; and
a first liner layer directly between the second conductive hydrogen barrier layer and the second conductive fill material;

a third level above the second level, the third level comprising:
a second dielectric comprising a first less than 80% film density material on the first dielectric; and
a contact electrode structure comprising:
a second liner layer comprising a second lateral portion on the via electrode and second substantially vertical portions directly adjacent to the second dielectric; and
a third conductive fill material adjacent to the second liner layer; and

a second region adjacent to the first region, the second region comprising:
a third dielectric comprising a second less than 80% film density material directly adjacent to the first dielectric, the third dielectric on the insulator layer, and wherein the second dielectric extends laterally on the third dielectric;
a second conductive interconnect within the first level;
a third conductive interconnect within the third level; and
a via structure within the second level, the via structure coupled between the second conductive interconnect and the third conductive interconnect, wherein the via structure and the third conductive interconnect comprise:
a third liner layer adjacent to sidewalls of the third dielectric and the second dielectric, the third liner layer extending from an uppermost surface of the second conductive interconnect to an uppermost surface of the second dielectric; and
a fourth conductive fill material continuously filling the via structure and the third conductive interconnect.