Patent ID: 11942966
Assignee: MICRON TECHNOLOGY, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 11:
12. An apparatus, comprising:
error control circuitry operable to perform an error control operation on data received for storage at the apparatus, the error control circuitry further operable to:
generate a first plurality of syndromes associated with the error control operation based at least in part on the received data, each syndrome of the first plurality comprising error correction or error detection syndrome bits;
store the first plurality of syndromes based at least in part on the error control operation;
retrieve the data and the first plurality of syndromes based at least in part on storing the received data and storing the first plurality of syndromes;
generate a second plurality of syndromes associated with the error control operation based at least in part on retrieving the data, each syndrome of the second plurality comprising error correction or error detection syndrome bits;
determine whether the first plurality of syndromes matches the second plurality of syndromes based at least in part on comparing the first plurality of syndromes and the second plurality of syndromes; and
generate a signal indicative of whether the first plurality of syndromes matches the second plurality of syndromes; and

a register operable to receive the signal from the error control circuitry and store, at a location of the register, an indication of whether the first plurality of syndromes matches the second plurality of syndromes based at least in part on receiving the signal.