Patent ID: 11943207
Assignee: INTEL CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC H  G  Y | IPC G  H

Claim 11:
12. A secure data management system comprising:
a plurality of hardware components, including a processing circuitry, a direct memory access (DMA) engine, and a cryptographic engine; and
at least one memory device including instructions embodied thereon, wherein the instructions, which when executed by the processing circuitry, configure the hardware components to perform operations to:
perform a secure exchange with an edge computing device to negotiate a shared symmetric encryption key, based on a request for data received from the edge computing device;
generate an inline encryption command based on completion of the secure exchange, the inline encryption command including a first address associated with a storage location storing the data, a second address associated with a memory location in the at least one memory device, and the shared symmetric encryption key;
retrieve the data from the storage location using the first address of the inline encryption command;
encrypt the data using the cryptographic engine within the plurality of hardware components and based on the shared symmetric encryption key; and
store the encrypted data in the memory location using the second address.