Patent ID: 11869826
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for constructing an improved memory module having two or more semiconductor dies, comprising:
for each individual semiconductor die in the two or more semiconductor dies, determining a susceptibility to temperature of an operating parameter of the individual semiconductor die based on a change in a measurement of the operating parameter between a first temperature and a second temperature;
identifying at least one first semiconductor die that is more temperature-affected than at least one second semiconductor die based on the determined susceptibility to temperature for each of the two or more semiconductor dies; and
mounting the at least one first semiconductor die at a first array area of a memory module substrate and mounting the at least one second semiconductor die at a second array area of the memory module substrate, wherein the first array area is cooler than the second array area during operation.