Patent ID: 11954803
Assignee: IMAGINATION TECHNOLOGIES LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. The method according to claim 8, wherein forming a sub-polygon inside the tile by replacing vertices of the primitive outside the tile with the intersection points comprises:
forming an initial sub-polygon inside the tile by replacing vertices of the primitive outside the tile with the intersection points; and
if the initial sub-polygon has more than three vertices, dividing the initial sub-polygon into a plurality of smaller sub-polygons, each having only three vertices;
wherein a bounding box is generated at sample precision for each smaller sub-polygon and wherein testing each edge of the sub-polygon which is also part of an edge of the primitive against each sample point in the bounding box of the sub-polygon to determine if any sample point is inside the sub-polygon comprises:
for each smaller sub-polygon, testing each edge of the smaller sub-polygon which is also part of an edge of the primitive against each sample point in the bounding box of the smaller sub-polygon to determine if any sample point is inside the smaller sub-polygon.