Patent ID: 11914439
Assignee: ROHM CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 2:
3. The synchronous reset signal generation circuit according to claim 1, wherein
each flip-flop in the synchronous reset signal output circuit, the first error determination signal output circuit, and the second error determination signal output circuit has a data input terminal, a data output terminal, a clock input terminal, and an asynchronous reset input terminal, wherein the clock signal is input to the clock input terminal of each flip-flop, the asynchronous reset signal is input to the asynchronous reset input terminal of each flip-flop, and between two mutually adjacent flip-flops, an output signal from the data output terminal of a former-stage flip-flop is input to the data input terminal of a latter-stage flip-flop,
among the L flip-flops, a signal with a predetermined logic value is input to the data input terminal of an initial-stage flip-flop, and the synchronous reset signal is output from the data output terminal of the final-stage flip-flop,
among the M flip-flops, the signal with the predetermined logic value is input to the data input terminal of an initial-stage flip-flop, and the first error determination signal is output from the data output terminal of the final-stage flip-flop, and
among the N flip-flops, the first error determination signal is input to the data input terminal of the initial-stage flip-flop, and the second error determination signal is output from the data output terminal of the final-stage flip-flop.