Patent ID: 11950401
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G  B | IPC H

Claim 9:
10. A semiconductor structure, comprising:
a substrate; and
first and second two-port (TP) SRAM cells over the substrate, wherein each of the first and the second TP SRAM cells includes a write port and a read port,
wherein the write port of the first TP SRAM cell shares a cell boundary with the write port of the second TP SRAM cell, the write port of the first TP SRAM cell includes a first write pass gate (W_PG) transistor, the write port of the second TP SRAM cell includes a second W_PG transistor, the first and the second W_PG transistors share a common gate electrode that extend across the cell boundary, the write port of the second TP SRAM cell further includes a first write word line (W_WL) landing pad that is connected to the common gate electrode through a gate via.