Patent ID: 11956311
Assignee: MARVELL ASIA PTE LTD
Field: Digital communication (Electrical engineering)
Classification: CPC G  H | IPC H

Claim 15:
16. The computer device of claim 1, wherein the egress processor is configured to:
pre-map portions of the memory with the preconfigured descriptors, each preconfigured descriptor representing one of the portions of the memory;
fetch a data segment corresponding to one of the preconfigured descriptors from the memory;
wrap one of the data segments with the one of the preconfigured descriptors;
append the wrapped data segment to the aggregated data segments;
determine if the appending completes the aggregation of the data segments;
in response to determining that the appending completes the aggregation of the data segments, sending the aggregated data segments to the queue; and
in response to determining that the appending does not complete the aggregation, reusing the preconfigured descriptors to aggregate subsequent data segments.