Patent ID: 11868778
Assignee: ADVANCED MICRO DEVICES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 14:
15. A system for compacted addressing for transaction layer packets, comprising:
a compaction unit; and
a decompaction unit in communication with the compaction unit;
the compaction unit configured to:
receive, for a first epoch, a plurality of first transaction layer packets;
maintain, for each address bit in the plurality of first transaction layer packets, a corresponding counter, the corresponding counter indicating whether the address bit is a low entropy address bit;
remove, from one or more memory addresses of one or more second transaction layer packets associated with a second epoch after the first epoch, the one or more low entropy address bits; and
send the one or more second transaction layer packets to the decompaction unit.