Patent ID: 11862546
Assignee: APPLIED MATERIALS, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 18:
19. A method of forming a semiconductor device assembly, comprising:
forming at least one via in a core substrate comprising silicon, the at least one via extending from a first side of the core substrate to a second side of the core substrate and having a diameter less than about 100 μm, the core substrate having a thickness less than about 1000 μm;
forming a thermal oxide layer over and in direct contact with the first side and the second side the core substrate and a surface of the at least one via, the thermal oxide having a thickness between about 300 nm and about 2 μm;
disposing a dielectric material over and in direct contact with the thermal oxide layer on the first side and the second side the core substrate and the surface of the at least one via, the dielectric material having a thickness less than about 50 μm and comprising an epoxy resin having silica particles disposed therein;
forming an opening in the dielectric material disposed on the surface of the at least one via, the opening defined by a surface extending between an exposed first surface of the dielectric material on the first side of the core substrate and an exposed second surface of the dielectric material on the second side of the core substrate, the opening having a diameter less than about 50 μm;
depositing a molybdenum adhesion layer on the surface of the opening and a copper seed layer on a surface of the adhesion layer; and
depositing a copper conductive layer on the surface of the adhesion layer, the adhesion layer and the seed layer disposed between the conductive layer and the dielectric material.