Patent ID: 11868281
Assignee: META PLATFORMS TECHNOLOGIES, LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 8:
9. An integrated circuit comprising:
a plurality of shared memory banks including a first bank and a second bank, wherein at least one of the shared memory banks can operate in low power mode and wherein at least one of the shared memory banks cannot operate in low power mode;
a plurality of subsystems, including a first subsystem and a second subsystem, the first subsystem having access to each of the shared memory banks through a first port, the second subsystem having access to each of the shared memory banks through a second port, wherein latency to the first bank by the first port is lower than latency to the first bank by the second port, and wherein latency to the second bank by the second port is lower than latency to the second bank by the first port;
a network connecting the first port and the second port to each of the shared memory banks, wherein the network is configured within the integrated circuit to connect the first port to the first bank through a first switch, and connect the second port to the second bank through a second switch; and
logic for determining, based on power consumption attributes of each of the plurality of shared memory banks, which of the plurality of shared memory banks from which to allocate memory, wherein the power consumption attributes include whether each of the plurality of shared memory banks can operate in low power mode.