Patent ID: 11869574
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 19:
20. A semiconductor memory device comprising:
a mode register set configured to store a first control code set received from a memory controller and configured to set an operation mode of the semiconductor memory device; and
a clock correction circuit configured to:
generate first, second, third, and fourth divided clock signals, which have a phase difference of 90 degrees with respect to each other, based on a data clock signal received from the memory controller; and
sequentially perform a first duty cycle training to search a second control code set, a second duty cycle training to search a third control code set, and a third duty cycle training to search the first control code set, during a duty training interval based on a duty training command received from the memory controller,
wherein the second control code set is associated with the first divided clock signal and the third divided clock signal,
wherein the third control code set is associated with the second divided clock signal and the fourth divided clock signal, and
wherein the first control code set is associated with the first divided clock signal and the second divided clock signal,
wherein the clock correction circuit comprises:
a training scheduler configured to divide the duty training interval into a first interval, a second interval and a third interval, which are consecutive, and configured to generate training control signals during which a duty training signal based on the duty training command is activated;
a phase skew adjusting circuit configured to generate first, second, third, and fourth adjusted clock signals by adjusting skew of each of the first, second, third, and fourth divided clock signals during the duty training interval;
a multi pattern generator configured to generate first pattern data during the first interval, second pattern data during the second interval, and third pattern data during the third interval, based on a pattern generation control signal in the training control signals;
a clock multiplexer configured to provide the first adjusted clock signal and the third adjusted clock signal as a first selected clock signal and a second selected clock signal from among the first, second, third, and fourth adjusted clock signals based on the first pattern data during the first interval, configured to provide the second adjusted clock signal and the fourth adjusted clock signal as the first selected clock signal and the second selected clock signal from among the first, second, third, and fourth adjusted clock signals based on the second pattern data during the second interval, and configured to provide the first adjusted clock signal and the second adjusted clock signal as the first selected clock signal and the second selected clock signal from among the first, second, third, and fourth adjusted clock signals based on the third pattern data during the third interval;
a duty cycle monitor configured to monitor duty cycles of the first selected clock signal and the second selected clock signal in each of the first interval, the second interval, and the third interval, and configured to generate monitoring information based on a result of the monitoring;
a demultiplexer;
a register set; and
a flip-flop,
wherein the demultiplexer is configured to provide the monitoring information to the register set in the first interval, and is configured to provide the monitoring information to the memory controller through the flip-flop in the second interval, based on a first selection signal in the training control signals.