Patent ID: 11942131
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. A processing apparatus comprising:
a bit-cell array comprising at least one bit-cell line including a plurality of bit-cells electrically connected to each other in series,
wherein each of the plurality of bit-cells comprises:
a first magnetic resistor that is configured to store a first resistance value based on a movement of a location of a magnetic domain-wall;
a second magnetic resistor electrically connected to the first magnetic resistor in parallel, and configured to store a second resistance value that is equal to or less than the first resistance value;
a first switching element electrically connected to the first magnetic resistor in series, and configured to switch an electrical signal applied to the first magnetic resistor;
a second switching element electrically connected to the second magnetic resistor in series, and configured to switch an electrical signal applied to the second magnetic resistor; and
a third switching element connecting layers of the first magnetic resistor to each other, the layers having an identical magnetization direction to each other.