Patent ID: 11916003
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC B  H

Claim 21:
22. An electronic package, comprising:
a first substrate;
a second substrate; and
an array of interconnects electrically coupling the first substrate to the second substrate, wherein the array of interconnects comprises:
first interconnects, wherein the first interconnects have a first volume and a first material composition; and
second interconnects, wherein the second interconnects have a second volume and a second material composition, wherein the first volume is different than the second volume and/or the first material composition is different than the second material composition, and wherein second interconnects are located at a non-critical-to-function (NCTF) pin, a redundant power pin, a redundant ground pin, or a non-connect location of the electronic package.