Patent ID: 11871556
Assignee: SK HYNIX INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 7:
8. A memory device, comprising:
a plurality of cylindrical active layers including channel layers that are laterally spaced apart from a substrate in a first direction;
a word line extending in a second direction while surrounding the channel layers of the cylindrical active layers;
a bit line coupled to one side of the active layer and vertically oriented in a third direction from the substrate; and
a capacitor coupled to another side of the active layer,
wherein the word line includes:
an upper level portion positioned at a higher level than the channel layers;
a lower level portion positioned at a lower level than the channel layers; and
an intermediate level connection positioned between the upper level portion and the lower level portion while being positioned at the same level as the channel layers, and
wherein each of the cylindrical active layers includes:
an inner gap;
a gap-fill material filling the inner gap;
a first source/drain region surrounding an end of one side of the gap-fill material; and
a second source/drain region surrounding an end of another side of the gap-fill material,
wherein the channel layer includes a plurality of outer sides surrounding the gap-fill material.