Patent ID: 11961826
Assignee: nan
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. A bonded wafer structure, comprising:
a first semiconductor structure comprising a first substrate, first devices and a first interconnect structure;
a second semiconductor structure comprising a second substrate, second devices and a second interconnect structure, wherein the second interconnect structure comprises a top metal level comprising a plurality of metal features having a contact pad region and a second region contiguous with the contact pad region, wherein an upper surface of each of the contact pad regions is coplanar with an upper surface of each of the second regions, the contact pad regions have length and width dimensions in a range from 40 μm to 100 μm and the second regions have a length and/or width dimension that is less than 40 μm;
a bonding layer between the top metal level TM of the second interconnect structure and a first surface of the first substrate; and
an array of contact pads over a second surface of the first substrate, wherein the contact pad regions of the plurality of metal features form an array pattern that corresponds with an array pattern of the contact pads formed over the second surface of the first substrate.