Patent ID: 11967521
Assignee: INNOSCIENCE (SUZHOU) SEMICONDUCTOR CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 19:
20. An integrated semiconductor device, comprising:
a substrate;
a plurality of semiconductor circuit layers being disposed above the substrate;
a first insulating layer being disposed on the semiconductor circuit layers;
a second insulating layer being disposed on the first insulating layer; and
a plurality of circuit being embedded in the first and second insulating layers and electrically connected to the semiconductor circuit layers,
wherein the semiconductor circuit layers include a plurality of device portions and one or more isolating portions, and the isolating portions are disposed among the device portions, and the isolating portions provide electrical isolation between adjacent said device portions, and the first insulating layer or the second insulating layer has one or more isolating structures raised from top surfaces of the circuits on the device portions.