Patent ID: 11963363
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 9:
10. A memory device, comprising:
strip-shaped stacking structures each comprising conductive lines and dielectric patterns stacked alternately;
pillar-shaped structures penetrating through the conductive lines and the dielectric patterns of the strip-shaped stacking structures, and each of the pillar-shaped structures comprising:
a first conductive pillar;
a second conductive pillar;
an isolation structure disposed between the first conductive pillar and the second conductive pillar, wherein the isolation structure comprises a single material between the first conductive pillar and the second conductive pillar;
an oxide semiconductor layer and a charge storage dielectric layer, wherein the oxide semiconductor layer and the charge storage dielectric layer laterally surround the first conductive pillar, the second conductive pillar and the isolation structure, the charge storage dielectric layer is disposed between the oxide semiconductor layer and one of the strip-shaped stacking structures, and
wherein the perimeter of each of the first conductive pillar and the second conductive pillar is enclosed by the isolation structure and the oxide semiconductor layer; and

signal lines electrically connected to the first conductive pillar and the second conductive pillar.