Patent ID: 11967953
Assignee: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 8:
9. A logic cascading method based on a non-volatile Boolean logic circuit, comprising:
taking a previous logic operation result obtained by the operation method described in claim 7 as a new input logic value Q, the operation is performed again according to the operation method described in claim 7, thereby realizing a logic cascade,
wherein the non-volatile Boolean logic circuit comprising a controller, a memristor M1, a memristor M2 and a resistor,
wherein the controller is connected to a positive electrode of the memristor M1, a positive electrode of the memristor M2, and one end of the resistor, respectively, wherein negative electrodes of the memristor M1 and the memristor M2 are connected to a same word line, another end of the resistor is connected to the word line, wherein the memristor M1 and the memristor M2 have the same structure,
wherein the controller is used to set the memristor M2 to a high resistance state before performing logic operations, wherein when performing the logic operations, a voltage A is applied to the memristor M1, a voltage B is applied to the memristor M2, a voltage C is applied to the resistor, and a resistance state of the memristor M2 is read thereby obtaining a result of the logic operations;
wherein when the non-volatile Boolean logic circuit performs operations related to a logic value Q, the controller is further used to set the memristor M1 to a resistance state corresponding to the logic value Q before performing the logic operations, wherein the operations related to the logic value Q comprise performing logic operations on a logic value P and the logic value Q and performing a logic operation only on the logic value Q,
wherein values of the voltage A and the voltage C are determined based on the logic value P and a type of the logic operation, wherein a value of the voltage B is Vp, wherein the Vp satisfies Vset/2<Vp<Vse and Vp<2|Vreset|, wherein the Vset is a threshold value at which the memristor M1 or the memristor M2 changes from the high resistance state to a low resistance state, wherein the Vreset is a threshold value at which the memristor M1 or the memristor M2 changes from the low resistance state to the high resistance state.