Patent ID: 11876080
Assignee: KIOXIA CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A semiconductor memory device comprising:
a plurality of memory chips each extending in a first direction and a second direction and stacked to partially overlap one another in a third direction, the first, second, and third directions crossing one another, each memory chip including
a core circuit in which a plurality of memory cells are provided, the core circuit being arranged in a first rectangular region with a first side extending in the first direction and a second side extending in the second direction orthogonal to the first direction,
a first area adjacent to the first side and extending in the first direction,
a second area adjacent to the second side and extending in the second direction,
a third area adjacent to the first area in the first direction and adjacent to the second area in the second direction,
a first pad provided in the first area,
a second pad provided in the second area, and
a third pad provided in the third area;

a first bonding wire that connects the first and third pads of one of the memory chips;
a second bonding wire that connects the second pad of a first memory chip of the plurality of memory chips and the second pad of a second memory chip of the plurality of the memory chips,
wherein the second memory chip is stacked on the first memory chip such that the second memory chip overlaps the core circuit of the first memory chip and does not overlap the first, second, and third pads of the first memory chip in the third direction.