Patent ID: 11887987
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A circuit comprising:
a base silicon layer;
a base oxide layer formed over the base silicon layer;
a first top silicon layer formed over a first region of the base oxide layer, the first top silicon layer having a first thickness;
a second top silicon layer formed over a second region of the base oxide layer, the second top silicon layer having a second thickness that is less than the first thickness;
a first semiconductor device formed over the first top silicon layer;
a second semiconductor device formed over the second top silicon layer;
a first added oxide formed on the base oxide layer, the first top silicon layer contacting a top surface of the first added oxide and a bottom surface of the first semiconductor device; and
a second added oxide formed on the base oxide layer, the second top silicon layer contacting a top surface of the second added oxide and a bottom surface of the second semiconductor device;
wherein a third thickness of the first added oxide is less than a fourth thickness of the second added oxide;
wherein a sum of the first thickness of the first top silicon layer and the third thickness of the first added oxide is equal to a sum of the second thickness of the second top silicon layer and the fourth thickness of second added oxide; and
wherein a height of a bottom surface of the first added oxide is the same as a height of a bottom surface of the second added oxide.