Patent ID: 11894367
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 0:
1. A method, comprising:
forming a plurality of first semiconductor nanosheets corresponding to channel regions of a first gate all around transistor;
depositing a first interfacial dielectric layer on the first semiconductor nanosheets;
depositing a dipole-inducing layer on the first interfacial dielectric layer;
depositing a first high-K dielectric layer on the dipole-inducing layer after depositing the dipole-inducing layer such that the dipole inducing layer is positioned between the first interfacial dielectric layer and the first high-K dielectric layer; and
forming a dipole layer from the dipole-inducing layer and at least one of high-K dielectric layer and the interfacial dielectric layer on the first semiconductor nanosheets by performing a thermal anneal process.