Patent ID: 11895670
Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
Field: Digital communication (Electrical engineering)
Classification: CPC H  Y | IPC H

Claim 0:
1. An integrated circuit comprising:
reception circuitry which, in operation, controls receiving downlink control information (DCI) mapped to one or more Physical Resource Block (PRB) sets among a plurality of PRB sets;
processing circuitry which, in operation, controls mapping an ACK/NACK signal to a Physical Uplink Control Channel (PUCCH) resource, the ACK/NACK signal being generated based on a detection result of data indicated by the DCI; and
transmission circuitry which, in operation, controls transmitting the ACK/NACK signal, wherein
the plurality of PRB sets include a first PRB set having a first plurality of ECCEs and a second PRB set having a second plurality of ECCEs different from the first plurality of ECCEs,
for the first PRB set, an index to the PUCCH resource is determined based on a first ECCE index in which the DCI is mapped and which is offset by a higher layer signaling, and determined without adding a PRB value to the first ECCE index, and
for the second PRB set, an index to the PUCCH resource is determined based on a sum between (1) the PRB value and (2) a second ECCE index in which the DCI is mapped and which is offset by the higher layer signaling.