Patent ID: 11894418
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A semiconductor device, comprising a substrate, transistors, word lines, bit lines, and semiconductor structures, each of the semiconductor structures comprising:
the substrate, comprising an active area;
a first electrode layer, arranged on the substrate and electrically connected to the active area, the first electrode layer extending in a direction perpendicular to the substrate;
a dielectric layer, arranged on a surface of the first electrode layer; and
a second electrode layer, arranged on a surface of the dielectric layer,
wherein each of the surface of the first electrode layer and the surface of the dielectric layer is provided an uneven structure,
wherein the bit lines are arranged on the substrate, the word lines are arranged on the bit lines in a staggered manner, a gate of each of the transistors is connected with one of the word lines, a source and a drain of each of the transistors are formed in the active area of the substrate, the drain of each of the transistors is connected with one of the bit lines, and the source of each of the transistors is connected with the first electrode layer of one of the semiconductor structures.