Patent ID: 11972837
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 12:
13. A data transmitter circuit comprising:
first to fourth pattern detection circuits configured to activate first to fourth speed control signals by using first to fourth data corresponding to the first to fourth pattern detection circuits, respectively, each piece of the first to fourth data being multibit;
a first sampling circuit configured to sample the first data during an activation period of a first sampling clock and reduce an operating speed of the first sampling circuit when the first speed control signal is activated;
a second sampling circuit configured to sample the second data during an activation period of a second sampling clock and reduce an operating speed of the second sampling circuit when the second speed control signal is activated;
a third sampling circuit configured to sample the third data during an activation period of a third sampling clock and reduce an operating speed of the third sampling circuit when the third speed control signal is activated;
a fourth sampling circuit configured to sample the fourth data during an activation period of a fourth sampling clock and reduce an operating speed of the fourth sampling circuit when the fourth speed control signal is activated; and
a parallel-to-serial conversion circuit configured to perform parallel-to-serial conversion on the sampled data to output the converted data to an output node.