Patent ID: 11949395
Assignee: XILINX, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. A fractional resampling circuit, comprising:
a fixed coefficient filter comprising a plurality of filter phases; and
a delay line configured to provide a plurality of input samples to the plurality of filter phases such that the plurality of filter phases processes the plurality of input samples in parallel according to a resampling ratio, and generate a plurality of output samples in a same clock cycle;
at least one modulo counter configured to increment based on Q mod P where Q is a down sampling value (0) of the resampling ratio and P is the number of the plurality of filter phases; and
a filter phase enable circuit coupled to the output of the at least one modulo counter and configured to output phase enable signals to indicate which of the plurality of filter phases are used to process the plurality of input samples during the same clock cycle.