Patent ID: 11916109
Assignee: GLOBALFOUNDRIES U.S. INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. A method of forming bipolar transistor structure, the method comprising:
forming a first emitter/collector (E/C) layer on an insulator layer;
forming a base layer over the insulator layer;
forming a spacer between the first E/C layer and the base layer,
wherein the base layer includes:
a lower base region, wherein the spacer is adjacent to the lower base region and the first E/C layer, and
an upper base region on the lower base region and the spacer, wherein a horizontal width of the upper base region is larger than a horizontal width of the lower base region; and

a silicide layer on the upper base region, wherein the silicide layer contacts an upper surface, a lower surface, and sidewalls of the upper base region.