Patent ID: 11908942
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A method, comprising:
depositing, on a substrate, a stack comprising a plurality of silicon layers interleaved by a plurality of silicon germanium layers;
patterning the stack and the substrate into a first fin-shaped structure and a second fin-shaped structure extending lengthwise along a first direction;
forming a first dummy gate stack over a first channel region of the first fin-shaped structure and a second dummy gate stack over a second channel region of the second fin-shaped structure;
removing the first dummy gate stack and the second dummy gate stack;
selectively removing the silicon germanium layers in the first channel region and the second channel region to form first nanostructures in the first channel region and second nanostructures in the second channel region;
selectively trimming the first nanostructures in the first channel region while the second nanostructures are covered in a masking layer;
forming a first gate structure over the first nanostructures; and
forming a second gate structure over the second nanostructures,
wherein a width of the first fin-shaped structure along a second direction perpendicular to the first direction is greater than the second fin-shaped structure along the second direction.