Patent ID: 11948944
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A stacked FET device, comprising:
at least one bottom-level FET on a substrate;
lower contact vias and local interconnects present in an ILD disposed over the at least one bottom-level FET;
at least one top-level FET present over the lower contact vias;
top-level FET source/drain contacts that wrap-around source/drain regions of the at least one top-level FET,
wherein the lower contact vias connect the top-level FET source/drain contacts to source/drain regions of the at least one bottom-level FET, wherein each of the local interconnects connects a given one of the lower contact vias to a given one of the top-level FET source/drain contacts, and wherein each of the top-level FET source/drain contacts is in direct contact with either one of the local interconnects or one of the lower contact vias from a bottom of the at least one top-level FET.