Patent ID: 11954035
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 18:
19. memory device, comprising:
a memory array comprising a first set of memory cells;
a cache comprising a second set of memory cells; and
one or more processors coupled with the memory array and the cache, the one or more processors operable to cause the memory device to:
synchronize information of a first address of the memory array and a second address of the cache based at least in part on accessing the first address of the memory array;
perform a quantity of access operations on the memory array based at least in part on synchronizing the information; and
evict the information from the second address of the cache based at least in part on the quantity of access operations performed on the memory array after synchronizing the information exceeding a threshold quantity of access operations.