Patent ID: 11910658
Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 4:
5. A manufacturing method for manufacturing the display device according to claim 1, comprising:
forming the array substrate, forming the pixel units, wherein the auxiliary region is between the bending region and the main display region, the first trough holes are formed in each of the pixel units, and the second trough holes are formed between two adjacent pixel units, wherein the second trough holes are further disposed between one of the pixel units close to the main display region and the main display region, and disposed between one of the pixel units close to the bending region and the bending region; and
forming the anode electrode on the array substrate, and the first trough holes are disposed directly below the anode electrode,
wherein forming the array substrate comprises:
forming a base substrate extending from the display region to the non-display region;
forming a blocking layer on the base substrate in the display region and the non-display region;
forming a buffer layer on the blocking layer in the display region and the non-display region;
forming an active layer on the buffer layer in the display region;
forming a first gate insulating layer on the active layer and the buffer layer in the display region and the non-display region;
forming a first gate layer on the first gate insulating layer in the display region;
forming a second gate insulating layer on the first gate insulating layer and the first gate layer in the display region and the non-display region;
forming a second gate layer on the second gate insulating layer in the display region; and
forming a dielectric interleaver on the second gate insulating layer and the second gate layer in the display region;
wherein in each of the pixel units in the display region, two via holes are formed and extended from the dielectric interlayer to a surface of the active layer, and the first trough holes are simultaneously formed between the two via holes in the auxiliary region;
between two adjacent pixel units in the auxiliary region, the second trough holes are formed and extended from the dielectric interlayer to the blocking layer or extended from the dielectric interlayer to an inside of the buffer layer;
depositing a metal material in the via holes and forming a source electrode and a drain electrode in the dielectric interlayer; and
depositing an inorganic material in the first trough holes and the second trough holes and forming a planarization layer on surfaces of the dielectric interlayer, the source electrode, and the drain electrode.