Patent ID: 11948841
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A device comprising:
a semiconductor region;
a gate stack over the semiconductor region;
a gate spacer comprising an inner sidewall contacting the gate stack, and an outer sidewall opposing the inner sidewall, and wherein the gate spacer has a highest nitrogen atomic percentage at the inner sidewall, and a lowest nitrogen atomic percentage at the outer sidewall;
a contact etch stop layer comprising:
a horizontal portion over and contacting the semiconductor region; and
a vertical portion connecting to the horizontal portion, wherein the vertical portion contacts the outer sidewall of the gate spacer;

an inter-layer dielectric overlapping the horizontal portion of the contact etch stop layer; and
a source/drain region on a side of the gate spacer and underlying the contact etch stop layer.