Patent ID: 11942171
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus comprising:
a first memory region including a first memory cell mat including a first plurality of prime memory cells and a first plurality of redundant memory cells, a first sense amplifier coupled to each of the first plurality of prime memory cells and the first plurality of redundant memory cells;
a second memory region including a second memory cell mat including a second plurality of prime memory cells and a second plurality of redundant memory cells, a second sense amplifier coupled to each of the second plurality of prime memory cells and the second plurality of redundant memory cells;
a global row decoder coupled in common to the first and second memory regions, the global row decoder configured, in response to receipt of a first defective row address signal corresponds to a row of the first plurality of prime memory cells, to activate each of the first sense amplifier and the second sense amplifier; and
a row decoder configured, in response to receipt of the first defective row address signal, to provide a first prime section signal corresponding to the first plurality of prime memory cells to the global row decoder such that the first sense amplifier is activated, and to provide a second redundant section signal corresponding to the second plurality of redundant memory cells to the global row decoder such that the second sense amplifier is activated and a row of the second plurality of redundant memory cells is selected.