Patent ID: 11960421
Assignee: HUAWEI TECHNOLOGIES CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. An operation accelerator, comprising:
a first buffer, configured to store first input data;
a second buffer, configured to store weight data;
an operation circuit connected to the first buffer and the second buffer, configured to perform matrix multiplication on the first input data and the weight data, to obtain a computation result;
a compression module, configured to compress the computation result to obtain compressed data;
a third buffer, configured to store a control instruction, wherein the control instruction instructs whether to compress the computation result;
a controller connected to the third buffer and configured to obtain the control instruction from the third buffer, and when the control instruction comprises instructions to compress the computation result, control the compression module to compress the computation result to obtain the compressed data; and
a direct memory access controller (DMAC) connected to the compression module, configured to store the compressed data in a memory outside the operation accelerator.