Patent ID: 11916121
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 10:
11. A semiconductor memory device comprising a plurality of field effect transistors,
wherein each field effect transistor selected from the plurality of field effect transistors is located on an insulating matrix layer that extends along a first direction and a second direction that is perpendicular to the first direction;
wherein each field effect transistor in the plurality of field effect transistors comprises:
a metal oxide semiconductor channel layer having a thickness along a third direction between a first major surface and a second major surface,
a drain region and a backside gate dielectric layer that are embedded in the insulating matrix layer and contact the first major surface of the metal oxide semiconductor channel layer,
a backside gate electrode embedded in the insulating matrix layer,
a first gate dielectric layer contacting a first portion of the second major surface of the metal oxide semiconductor channel layer, and
a first gate electrode located on the first gate dielectric layer and contacting a second portion of the second major surface of the metal oxide semiconductor channel layer,
wherein the plurality of field effect transistors comprises at least one row of field effect transistors that are arranged along the second direction; and
wherein dielectric rails contact metal oxide semiconductor channel layers and first gate electrodes of a respective neighboring pair of field effect transistors within each row of field effect transistors and provide lateral electrical isolation thereamongst.