Patent ID: 11874772
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device, comprising:
an array of memory cells; and
a memory controller operable to perform operations comprising:
determining a write progress indicator indicating an actual amount of data requested by an external device to write to the memory cells during a tracking period relative to a target amount of data expected to be requested by the external device to write to the memory cells during the tracking period; and
adjusting an amount of memory space to be freed on a portion of the memory cells in response to the write progress indicator, including increasing the amount of memory space freed if the actual amount of data requested by an external device to write to the memory cells is less than the target amount of data expected to be requested by the external device to write to the memory cells by a specified margin, and withholding memory space freeing or decreasing the amount of memory space freed if the actual amount of data requested to write by the external device to the memory cells exceeds the target amount of data expected to be requested by the external device to write to the memory cells by a specified margin.