Patent ID: 11908543
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 11:
12. The transmission circuit according to claim 9, wherein the latch circuit includes a plurality of latch units, and
wherein at least one of the plurality of latch units comprises:
a cross-coupled latch configured to latch a level of a first differential input terminal, among the plurality of differential input terminals, in response to a transition of a first control clock signal, among the control clock signals, and configured to output latched data through a first output terminal; and
a switching section, connected between the first differential input terminal and the first output terminal, configured to output state information, which is input through the first differential input terminal, through the first output terminal in response to a state information read signal, regardless of the transition of the first control clock signal.