Patent ID: 11963358
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor memory device, comprising:
a stacked structure including a plurality of metallic lines stacked in a first direction on a substrate, the plurality of metallic lines including an uppermost metallic line;
a semiconductor conduction line on the uppermost metallic line of the plurality of metallic lines, the semiconductor conduction line including a semiconductor material;
a vertical structure including an upper vertical structure and a lower vertical structure, the upper vertical structure penetrating the semiconductor conduction line, the lower vertical structure penetrating the stacked structure, and a stacked structure of the upper vertical structure being different from a stacked structure of the lower vertical structure; and
a first cutting line through the plurality of metallic lines and the semiconductor conduction line, the first cutting line including:
a first upper cutting line through the semiconductor conduction line, and
a first lower cutting line through the plurality of metallic lines, a width of the first upper cutting line being greater than a width between two extension lines extending from sidewalls of the first lower cutting line on a lower surface of the semiconductor conduction line.