Patent ID: 11903333
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 14:
15. An apparatus, comprising:
a memory array comprising a plurality of memory cells, each memory cell of the plurality of memory cells comprising:
a first electrode;
a second electrode; and
a self-selecting storage element extending between the first electrode and the second electrode in a first direction parallel to a plane defined by a substrate, wherein the self-selecting storage element comprises a bulk region comprising a chalcogenide material having a first composition and a sidewall region comprising the chalcogenide material having a second composition that is different than the first composition, at least a portion of the sidewall region extending between the first electrode and the second electrode in the first direction, wherein a first concentration of one or more components in the first composition of the chalcogenide material is between two and twenty percent different than a second concentration of the one or more components in the second composition; and

a controller coupled with the memory array and configured to program a state of the plurality of memory cells by applying voltages across the plurality of memory cells.