Patent ID: 11960127
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 14:
15. A manufacturing method of a semiconductor package, comprising:
forming a device layer comprising a base layer; an optical device; a mode coupler located at an edge of the semiconductor package; and at least one waveguide configured to transmit the light from the mode coupler to the optical device from a front semiconductor layer, the front semiconductor layer being stacked on an insulator layer comprising a first dielectric material, wherein the mode coupler is configured to receive light of at least one wavelength;
forming an interconnection structure on the device layer, the interconnection structure having bonding pads formed at a top surface of the interconnection structure;
bonding a semiconductor die to the bonding pads of the interconnection structure;
forming a buffer layer at an opposite side of the insulator layer with respect to the device layer, wherein the buffer layer includes a second dielectric material;
removing portions of the buffer layer to form contact openings in the buffer layer; and
forming connective terminals in the contact openings, wherein the connective terminals reach the insulator layer through the buffer layer, wherein
before the device layer is formed from the front semiconductor layer, an etch stop layer is formed on a layer selected from a bulk semiconductor layer and the insulator layer, and the front semiconductor layer is stacked on the insulator layer and the bulk semiconductor layer when the device layer is formed, and
the manufacturing method further comprises removing first portions of the interconnection structure to form trenches at the top surface of the interconnection structure;
filling a first conductive material in the trenches to form the bonding pads; removing second portions of the interconnection structure to form via openings connected to the trenches; and
filling a second conductive material in the via openings to form bonding vias electrically connected to the bonding pads,
the bonding vias extends through the base layer of the device layer and the interconnection structure along a first direction, the bonding vias electrically connect the semiconductor die to the connective terminals, the bonding vias are spaced apart from the insulator layer by the connective terminals, and distal ends of the bonding vias with respect to the bonding pads are in contact with a portion of bottom surfaces of the connective terminals, and another portion of the bottom surfaces of the connective terminals are in contact with the etch stop layer, and the portion of bottom surfaces of the connective terminals is substantially coplanar with the another portion of the bottom surfaces of the connective terminals.