Patent ID: 11886715
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. An apparatus, comprising:
an array of memory cells, comprising:
a first portion of memory cells that are inaccessible by devices external to the apparatus and that are configured to store a first set of data and a set of instructions;
a second portion of memory cells that are accessible by the devices external to the apparatus and that are configured to store a second set of data;
a set of address registers, wherein the set of address registers indicate which portion of the array is the inaccessible first portion; and

a controller coupled to the array, the controller configured to:
read addresses in the set of address registers;
identify the first portion using the read addresses;
execute instructions stored in the first portion, and store a result of the executed instructions within memory cells of the first portion;
prevent data from being copied from the second portion to the first portion in response to execution of an instruction that is not stored in the first portion; and
allow data to be copied from the second portion to the first portion in response to execution of an instruction that is stored in the first portion.