Patent ID: 11869617
Assignee: META PLATFORMS TECHNOLOGIES, LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 18:
19. A system, comprising:
a static random access memory (SRAM) device, comprising:
a bit cell array comprising a plurality of bit cells, the plurality of bit cells arranged in a plurality of rows and a plurality of columns, each column of the plurality of columns operatively coupled to a pair of bit lines, wherein the plurality of columns is arranged as a plurality of column groups each comprising a plurality of local columns;
a row decoder that is configured to operatively couple a word line to a row of the plurality of rows of bit cells based at least in part on a row address provided to the row decoder; and
a plurality of column decoders, each associated with a column group of the plurality of column groups, wherein each column decoder is configured to operatively couple a data line to a local column of the plurality of local columns corresponding to a column group of the plurality of column groups associated with said column decoder; and

a controller configured to, for a column group of the plurality of column groups:
provide a row address to the row decoder that causes the word line corresponding to a row of the plurality of rows associated with the row address to be asserted;
responsive to determining that a sequential memory access operation of a series of memory access operations is to be performed on a slow bit line of the one or more bit lines having an access time that is longer than the access times associated with at least one other bit line of the one or more bit lines, causing a delay of at least a subset of memory access operations of the series of memory access operations; and
perform the at least the subset of memory access operations after a time period associated with the delay has elapsed.