Patent ID: 11948949
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A device, comprising:
a semiconductor substrate having an upper face and a lower face;
a shallow trench isolation (STI) region extending into the upper face of the semiconductor substrate and laterally surrounding an active area of the semiconductor substrate;
a first source/drain region disposed within the active area;
a second source/drain region disposed within the active area and spaced apart from the first source/drain region in a first direction;
a channel region disposed within the active area and arranged between the first source/drain region and the second source/drain region, wherein the channel region has an upper surface that is co-planar with an upper surface of the STI region;
a horizontal gate electrode structure extending over a frontside of the semiconductor substrate and over the channel region;
a first vertical gate electrode structure extending downward from the horizontal gate electrode structure and into the semiconductor substrate, the first vertical gate electrode structure extending in the first direction along a first side of the channel region; and
a second vertical gate electrode structure extending downward from the horizontal gate electrode structure and into the semiconductor substrate, the second vertical gate electrode structure spaced apart from the first vertical gate electrode structure and extending in the first direction along a second side of the channel region.