Patent ID: 11922061
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. A memory device comprising:
at least one memory array; and
control circuitry configured to:
access host-device refresh-timing information, the host-device refresh-timing information:
received in association with a first command from a host device; and
indicating at least a first amount of time that remains before the host device is scheduled to issue a second command to direct the memory device to perform a next refresh operation;

determine a self-refresh schedule for a memory cell of the at least one memory array based at least in part on the host-device refresh-timing information;
determine memory-device refresh-timing information based at least in part on the self-refresh schedule, the memory-device refresh-timing information indicating at least a second amount of time that remains before the memory device is scheduled to undergo a next self-refresh operation; and
transmit the memory-device refresh-timing information to the host device in response to a third command.