Patent ID: 11908523
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. A memory device comprising:
a memory array comprising a set of memory cells; and
control logic, operatively coupled with the memory array, to perform operations comprising:
initiating a first express programming operation to program the set of memory cells to a target programming level of a set of programming levels;
storing, in a cache register, a first set of data associated with the first express programming operation;
at one or more checkpoints during execution of the first express programming operation, executing a prediction operation to determine a prediction result corresponding to a programming status of the set of memory cells;
comparing the prediction result to a threshold level to determine whether a condition is satisfied;
causing a release of the first set of data associated with the first express programming operation from the cache register in response to the condition being satisfied; and
loading, into the cache register, a second set of data associated with a second express programming operation to be applied to the memory array.