Patent ID: 11881450
Assignee: ADVANCED MICRO DEVICES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An integrated circuit comprising:
a first metal layer;
a first dielectric layer adjacent to the first metal layer;
a second metal layer adjacent to the first dielectric layer;
a second dielectric layer adjacent to the second metal layer; and
a third metal layer adjacent to the second dielectric layer, wherein a metal-insulator-metal (MIM) capacitor is formed between the first metal layer and the third metal layer; and
wherein:
each of the first metal layer and the third metal layer is connected to a respective voltage reference level with one of the respective voltage reference levels being a first power supply voltage reference level that is different from a second power supply voltage level used in another region of the integrated circuit; and
the second metal layer is a floating net with no connection to a voltage reference level used by the integrated circuit.