Patent ID: 11881511
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. A semiconductor structure, comprising:
a substrate;
a superlattice structure that includes a plurality of heterojunction channels on the substrate;
a first gate that extends to one of the plurality of heterojunction channels;
a second gate that extends to a different one of the plurality of heterojunction channels;
a first source or drain structure immediately adjacent a first side of the first gate, the first source or drain structure extending through the superlattice structure;
a second source or drain structure immediately between a second side of the first gate and a first side of the second gate, the second source or drain structure extending through the superlattice structure, and the second source or drain structure having a bottommost surface at a same level as a bottommost surface of the first source or drain structure; and
a third source or drain structure immediately adjacent a second side of the second gate, the third source or drain structure extending through the superlattice structure, and the third source or drain structure having a bottommost surface at a same level as the bottommost surface of the second source or drain structure.