Patent ID: 11914510
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A method comprising:
receiving data to be stored at a 3-dimensional (3D) memory component of a memory sub-system in response to a write operation;
identifying a first layer within a first logical unit and a second layer within a second logical unit of the 3D memory component based on randomly selecting layers from a plurality of layers of the 3D memory component;
determining, by a processing device of the memory sub-system, a first location of the first layer of the 3D memory component at which to store a first portion of the data;
determining a second location of the second layer of the 3D memory component at which to store a second portion of the data; and
causing, by a processing device, the first portion of the data to be stored in first memory cells at the first location within the first layer and the second portion of the data to be stored in second memory cells at the second location within the second layer.