Patent ID: 11901281
Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A passive electronic component having a first surface and a second surface opposite the first surface, the passive electronic component comprising:
a nonconductive material;
a capacitor embedded within the nonconductive material, the capacitor having a first electrode, a second electrode, and a dielectric material disposed between the first and second electrodes, the first electrode comprising a first conductive layer and a plurality of elongate conductors extending vertically from and electrically connected to the first conductive layer, the plurality of elongate conductors comprising a different material from the first conductive layer, the plurality of elongate conductors each having a maximum horizontal dimension and a maximum vertical dimension greater than the maximum horizontal dimension, the maximum horizontal dimension being the maximum dimension of each elongate conductor in all horizontal directions;
a first conductive via extending through the passive electronic component vertically from the first surface to the second surface, the first conductive via electrically connected to the first electrode;
a first conductive contact at the first surface, the first conductive contact electrically connected to the second electrode;
a second conductive contact at the second surface, the second conductive contact electrically connected to the first electrode;
a second conductive via extending through the passive electronic component from the first surface to the second surface, the second conductive via electrically connected to the second electrode;
a first terminal formed with or electrically connected to the first conductive via and a second terminal formed with or electrically connected to the second conductive via, the first and second terminals exposed at or near the first surface of the passive electronic component;
a third terminal formed with or electrically connected to the first conductive via and a fourth terminal formed with or electrically connected to the second conductive via, the third and fourth terminals exposed at or near the second surface of the passive electronic component.