Patent ID: 11949012
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor device, comprising:
a first transistor which comprises a first gate stack on a substrate, wherein the first transistor includes a first nanosheet; and
a second transistor which comprises a second gate stack on the substrate, wherein the second transistor includes a second nanosheet,
wherein the first gate stack comprises an interfacial layer disposed on the substrate, a first ferroelectric material layer disposed on the interfacial layer, a high dielectric constant insulating layer and a conductive layer formed between the interfacial layer and the first ferroelectric material layer, a first work function layer disposed on the first ferroelectric material layer and a first upper gate electrode disposed on the first work function layer,
wherein a thickness of the first ferroelectric material layer is greater than a thickness of the first work function layer,
wherein the second gate stack comprises a second ferroelectric material layer disposed on the substrate, a second work function layer disposed on the second ferroelectric material layer and a second upper gate electrode disposed on the second work function layer,
wherein the first work function layer comprises the same material as the second work function layer,
wherein the semiconductor device further comprises a third transistor which comprises a third gate stack on the substrate, wherein the third transistor includes a third nanosheet,
wherein the third gate stack comprises a third ferroelectric material layer disposed on the substrate, a third work function layer contacting the third ferroelectric material layer and a third upper gate electrode disposed on the third work function layer, and
wherein a thickness of the third ferroelectric material layer is less than a thickness of the third work function layer.