Patent ID: 11894075
Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A method of cache programming for a memory device, wherein the memory device comprises memory cells arranged in rows and columns, the method comprising:
storing n logic pages of current programming data in page buffers, wherein:
n is a whole number greater than 1;
each page buffer comprises n data latches to store n-bit of data; and
each page buffer is coupled with a column of memory cells;

programming a selected row of memory cells according to the n logic pages of current programming data;
discarding one or more of the n logic pages of the current programming data before the programming the selected row of memory cells according to the n logic pages of the current programming data is completed;
storing one or more of n logic pages of new programming data before the programming the selected row of memory cells according to then logic pages of the current programming data is completed; and
recovering the discarded one or more of the n logic pages of the current programing data when there is a programming failure, based on remaining logic pages of the current programming data, logic states of the selected row of memory cells that have passed programming verification and a mapping scheme between a set of n-bit binary codes and 2n logic states of each memory cell.