Patent ID: 11961563
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. An apparatus comprising:
one or more control circuits configured to connect to a three-dimensional memory structure comprising a plurality of NAND strings having memory cells, each memory cell having a control gate, the three-dimensional memory structure comprising a plurality of word lines, each word line being connected to the control gates of memory cells on a group of the NAND strings, wherein the one or more control circuits are configured to:
program memory cells in a selected block in the three-dimensional memory structure; and
control a ramp rate of voltages applied to respective word lines in the selected block during respective verify phases of programming the memory cells in the selected block to balance programming speed against a peak current during the respective verify phases.