Patent ID: 11862726
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A manufacturing method of a transistor, comprising:
providing a dielectric layer;
forming an insulating layer to partially cover the dielectric layer;
forming a source region and a drain region on two opposite sidewalls of the insulating layer to be in physical contact with the two opposite sidewalls of the insulating layer, wherein a top surface of the source region, a top surface of the drain region, and a top surface of the insulating layer are substantially coplanar;
depositing a channel layer on the insulating layer, the source region, and the drain region;
forming a ferroelectric layer over the channel layer through a non-plasma deposition process such that an interfacial layer is formed between the channel layer and the ferroelectric layer;
forming a gate electrode on the ferroelectric layer; and
patterning the gate electrode, the ferroelectric layer, the interfacial layer, and the channel layer to expose at least a portion of the insulating layer, at least a portion of the source region and at least a portion of the drain region.