Patent ID: 11916550
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. The integrated circuit of claim 1, wherein the multiplexing latch circuit comprises:
a first tri-state inverter comprising an input terminal coupled to the first data line and a low enable terminal configured to receive the first latching clock signal;
a second tri-state inverter comprising an input terminal coupled to the second data line and a low enable terminal configured to receive the second latching clock signal;
a first inverter comprising an input terminal configured to receive the first latching clock signal and an output terminal coupled to a high enable terminal of the first tri-state inverter; and
a second inverter comprising an input terminal configured to receive the second latching clock signal and an output terminal coupled to a high enable terminal of the second tri-state inverter.