Patent ID: 11917874
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: nan (nan)
Classification: CPC nan | IPC G  H

Claim 16:
17. The display substrate according to claim 8, wherein the first pixel circuit and the second pixel circuit respectively comprise a thin film transistor and a storage capacitance, the thin film transistor comprises an active layer, a gate electrode, a first gate insulating layer, a second gate insulating layer, an interlayer insulating layer, and source and drain electrodes, and the storage capacitance comprises a first capacitance plate and a second capacitance plate;
the active layer is disposed on the base substrate, the first gate insulating layer is disposed on a side of the active layer away from the base substrate, and the gate electrode and the first capacitance plate are disposed in a same layer on a side of the first gate insulating layer away from the base substrate, and the second gate insulating layer is disposed on a side of the gate electrode away from the base substrate and a side of the first capacitance plate away from the base substrate,
the second capacitance plate is disposed on a side of the second gate insulating layer away from the base substrate, and the interlayer insulating layer is disposed on a side of the second capacitance plate away from the base substrate,
the source and drain electrodes are disposed on a side of the interlayer insulating layer away from the base substrate, and the source and drain electrodes are electrically connected to the active layer through via holes in the first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer,
the display substrate further comprises a first planarization layer disposed on a side of the source and drain electrodes away from the base substrate to provide a first planarization surface, the first planarization layer comprises first via holes,
wherein the second signal line is disposed in a same layer as the gate electrode and the first capacitance plate,
the first signal line and the third signal line are disposed in a same layer as the source and drain electrodes.