Patent ID: 11962314
Assignee: SOCIONEXT INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A phase locked loop circuit that receives a first reference clock and generates an output clock, the phase locked loop circuit comprising:
a delay circuit configured to delay the first reference clock to generate a second reference clock;
a feedback circuit configured to generate a control signal based on a phase difference between the second reference clock and a feedback clock;
an oscillator configured to oscillate at a frequency determined based on the control signal to generate the output clock; and
a divider configured to switch between an on state and an off state, and divide the output clock in the on state,
wherein the phase locked loop circuit is configured to switch between a first mode and a second mode, the feedback clock in the first mode is a signal obtained by retiming an output of the divider with the output clock, and the feedback clock in the second mode is a signal obtained by retiming the first reference clock with the output clock.