Patent ID: 11917809
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 15:
16. A method, comprising:
identifying a row of first memory cells of a set of first memory cells of a memory die for an access operation, the memory die comprising the set of first memory cells in a first level above a substrate of the memory die and a set of second memory cells of the memory die in the first level; and
coupling the row of first memory cells with circuitry of a second level based at least in part on the identifying, wherein coupling the row of first memory cells with the circuitry of the second level comprises:
coupling respective storage elements of the row of memory cells with a set of access lines above the substrate of the memory die based at least in part on activating a plurality of first transistors of the first level; and
coupling the set of access lines with the circuitry of the second level based at least in part on activating a plurality of second transistors of the first level.