Patent ID: 11862514
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A method of manufacturing an integrated circuit device, the method comprising:
forming lower wiring structures, on an upper surface of a substrate, the lower wiring structures spaced apart from each other in a first direction, extending in a second direction orthogonal to the first direction, and having a same height in a third direction perpendicular to the upper surface of the substrate;
forming an insulating barrier layer conformally covering the upper surface of the substrate and the lower wiring structures;
forming a sacrificial pattern having a different first or second width in the first direction between the lower wiring structures;
forming a capping layer covering an upper surface of the sacrificial pattern and having the first width or the second width with the same width as the corresponding sacrificial pattern;
forming an air gap by removing the sacrificial pattern;
forming an etch stop layer conformally covering an upper surface of each of the lower wiring structures, a side surface of the insulating barrier layer, an upper surface of the insulating barrier layer, and an upper surface of the capping layer;
forming an insulating layer covering the etch stop layer; and
forming an upper wiring structure penetrating the insulating layer and connected to an upper surface of the lower wiring structures that is not covered by the etch stop layer,
wherein the first width of the air gap is less than a thickness of the capping layer in the third direction.