Patent ID: 11966737
Assignee: NVIDIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A method performed by a multiprocessor to execute an operation on a communicatively coupled coprocessor, the multiprocessor is configured to receive instructions from, and in response to provide results to, a control processor, the method comprises:
establishing a connection to the coprocessor, wherein said establishing includes causing the coprocessor to reserve resources on the coprocessor for the operation;
after the connection is established, issuing a plurality of write instructions to write input data for the operation into coprocessor-accessible storage locations in the reserved resources;
issuing an operation instruction to cause the coprocessor to execute the operation using said input data;
issuing a plurality of read instructions to read result data of the operation from coprocessor-accessible storage locations to multiprocessor-accessible storage locations; and
closing the connection,
wherein the method further comprises issuing a macro initiation instruction configured to cause disabling of interrupts and execution of a predetermined number of instructions following the macro initiation instruction without intervening preemption, and wherein the predetermined number is determined based on an operand of the macro initiation instruction.