Patent ID: 11967354
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A semiconductor memory device, comprising:
a memory cell region including a plurality of normal cells and a plurality of row-hammer cells coupled to each of a plurality of rows, wherein the row-hammer cells of a selected row are suitable for storing first data and second data, the first data representing a number of accesses to the selected row and the second data denoting whether to refresh second adjacent rows of the selected row; and
a refresh control circuit suitable for:
when an active command associated with an input address is inputted and based on the number of accesses read from the first data of the row-hammer cells corresponding to the input address, selecting a sampling address corresponding to the input address,
determining, in response to a refresh command, whether to refresh first adjacent rows physically closest to a target row corresponding to the sampling address, and
determining, in response to the refresh command, whether to refresh second adjacent rows physically adjacent to the target row, other than the first adjacent rows, based on the second data read from the target row.