Patent ID: 11901405
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A semiconductor structure, comprising:
a substrate, wherein the substrate comprises an array region and a peripheral region adjacent to each other, and the array region comprises a buffer region connected with the peripheral region;
a first dielectric layer, a first supporting layer and a second supporting layer, wherein the first supporting layer is arranged in the peripheral region, the first supporting layer covers a top surface and a side wall of the first dielectric layer, the second supporting layer is arranged in the array region, and the second supporting layer is higher than the first supporting layer; and
a groove-type lower electrode, wherein the groove-type lower electrode is arranged in the buffer region and penetrates through the second supporting layer, and a bottom surface of the groove-type lower electrode is located in the first dielectric layer, or a bottom surface of the groove-type lower electrode is located on a side of the first supporting layer away from the first dielectric layer and is lower than the second supporting layer.