Patent ID: 11876650
Assignee: CADENCE DESIGN SYSTEMS, INC.
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A receiver comprising:
a node to communicate a series of input symbols;
a first equalizer coupled to the node to produce first equalized symbols responsive to the series of input symbols;
a delay element coupled to the first equalizer to delay each of the first equalized symbols to produce delayed versions of the first equalized symbols;
a second equalizer coupled to the node to produce second equalized symbols responsive to the series of input symbols;
a decision circuit coupled to the second equalizer to issue a high-confidence decision for each of some of the second equalized symbols and a low-confidence decision for each of others of the second equalized symbols;
a third equalizer to equalize the high-confidence decisions and the low-confidence decisions; and
an arithmetic operator to combine the delayed versions of the first equalized symbols with the equalized high-confidence decisions and the equalized low-confidence decisions to produce third equalized symbols.