Patent ID: 11961827
Assignee: MONOLITHIC 3D INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 7:
8. A semiconductor device, the device comprising:
a first substrate;
a first metal layer disposed over said first substrate;
a second metal layer disposed over said first metal layer;
a first level comprising a single crystal layer and a plurality of transistors, said first level disposed over said second metal layer,
wherein an average thickness of said single crystal layer is less than one micron;

a third metal layer disposed over said first level;
a fourth metal layer disposed over said third metal layer,
wherein said fourth metal layer is aligned to said first metal layer with a less than 200 nm alignment error; and

a via disposed through said first level, and
wherein processing of said single crystal layer to said thickness comprises use of at least one etch rate selectivity.