Patent ID: 11917821
Assignee: SUNRISE MEMORY CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. The process of claim 9, further comprising:
etching recesses into the dielectric layers from their exposed sidewalls facing the second trenches;
depositing conformally the same third semiconductor layer over the exposed sidewalls of the stacks in the second trenches;
depositing the same covering layer over the third semiconductor layer and filling the recesses;
etching back the covering layer to expose portions of the third semiconductor layer on the sidewalls of the stacks in the second trenches, while retaining, in each recess a portion of the covering layer, so as to prevent a corresponding portion of the third semiconductor layer from being exposed in the second trenches;
removing the exposed portions of the third semiconductor layer; and
filling the second trenches by the filler material.