Patent ID: 11876067
Assignee: NANYA TECHNOLOGY CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A method of manufacturing a semiconductor package, comprising:
providing a package substrate with a first connection pad and a second connection pad;
providing a semiconductor chip over the package substrate, the semiconductor chip comprising a first chip pad, a first bonding pad, and a first redistribution layer, wherein the first bonding pad is closer to a periphery of the semiconductor chip than the first chip pad, and the first redistribution layer is connected between the first chip pad and the first bonding pad, wherein the first chip pad is a power pad or a ground pad through which power is supplied to the semiconductor chip, wherein the semiconductor chip further comprises a second chip pad, a second bonding pad, and a second redistribution layer connected between the second chip pad and the second bonding pad, the second chip pad is a data signal pad or a command/address signal pad;
forming a plurality of first bonding wires connected in parallel between the first connection pad of the package substrate and the first bonding pad of the semiconductor chip; and
connecting the second bonding pad to the second connection pad of the package substrate with a second bonding wire, wherein the second bonding wire is the only conductive path between the second connection pad and the second bonding pad.