Patent ID: 11886911
Assignee: EMC IP HOLDING COMPANY LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. An apparatus comprising:
at least one processing device comprising a processor coupled to a memory;
said at least one processing device being configured:
to associate different classes of service with respective threads of one or more applications executing on at least one of a plurality of processing cores of a storage system;
to configure different sets of prioritized thread queues for respective ones of the different classes of service;
to enqueue particular ones of the threads associated with particular ones of the classes of service in corresponding ones of the prioritized thread queues; and
to implement different dequeuing policies for selecting particular ones of the enqueued threads from the different sets of prioritized thread queues based at least in part on the different classes of service;
wherein configuring different sets of prioritized thread queues for respective ones of the different classes of service comprises:
determining a number of priority classes;
establishing a set of prioritized thread queues for each of the priority classes; and
assigning weights to respective ones of the sets of prioritized thread queues of the respective priority classes;
wherein the prioritized thread queues within a given one of the sets each have a same priority for selection of threads enqueued therein; and
wherein different ones of the prioritized thread queues in different ones of the sets have different priorities for selection of threads enqueued therein.