Patent ID: 11967580
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A microelectronic assembly, comprising:
a first redistribution layer;
a first die above the redistribution layer, the first die having a top side and a bottom side, and a first sidewall and a second sidewall between the top side and the bottom side, the second sidewall laterally opposite the first sidewall, and the first die comprising a plurality of through substrate vias;
a first conductive pillar laterally spaced apart from the first sidewall of the first die, the first conductive pillar having a first side and a second side;
a second conductive pillar laterally spaced apart from the second sidewall of the first die, the second conductive pillar having a first side and a second side;
a mold material on the first redistribution layer, the mold material in contact with the first side of the first conductive pillar, the mold material between the second side of the first conductive pillar and the first sidewall of the first die, the mold material between the second sidewall of the first die and the first side of the second conductive pillar, and the mold material in contact with the second side of the second conductive pillar;
a second redistribution layer having a top surface and a bottom surface, the bottom surface on the first conductive pillar, on the second conductive pillar, on the mold material, and over the first die;
a second die coupled to the top surface of the second redistribution layer, the second die vertically over the first die; and
a third die coupled to the top surface of the second redistribution layer, the third die vertically over the first die, and the third die laterally spaced apart from the second die, wherein the first die electrically couples the second die to the third die.