Patent ID: 11894085
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A memory device, comprising:
one or more components configured to:
read a first set of bits stored in a test control mode register of the memory device;
identify a test mode, for performing a memory built-in self-test, based on the first set of bits;
read a second set of bits stored in a section identifier mode register of the memory device;
identify one or more memory sections of the memory device for which the memory built-in self-test is to be performed, based on the second set of bits,
wherein the one or more memory sections are a subset of a plurality of memory sections into which the memory device is divided;

perform the memory built-in self-test for the one or more memory sections of the memory device based on the test mode; and
write a value to a third set of bits of a test status mode register to indicate a test status based on performing the memory built-in self-test, wherein:
a first value of the third set of bits indicates that no failures were detected based on performing the memory built-in self-test for the one or more memory sections,
a second value of the third set of bits indicates that a repairable failure exists in the one or more memory sections,
a third value of the third set of bits indicates that an unrepairable failure remains in the one or more memory sections, and
a fourth value of the third set of bits indicates that the memory built-in self-test is unreliable.