Patent ID: 11955386
Assignee: SK SILTRON CO. LTD.
Field: Measurement (Instruments)
Classification: CPC H  G | IPC G  H

Claim 4:
5. A wafer defect region evaluation method comprising:
a step of preparing a sample wafer;
a step comprising a first temperature increase period of increasing temperature to a first target temperature and a first temperature maintenance period of maintaining the first target temperature, wherein a first oxide film is formed on the sample wafer using a dry oxidation process in the first temperature maintenance period;
a step comprising a second temperature increase period of increasing temperature from the first target temperature to a second target temperature and a second temperature maintenance period of maintaining the second target temperature, wherein a second oxide film is formed on the first oxide film using a dry oxidation process in the second temperature increase period and the second temperature maintenance period;
a step comprising a third temperature increase period of increasing temperature from the second target temperature to a third target temperature and a third temperature maintenance period of maintaining the third target temperature, wherein a third oxide film is formed on the second oxide film using a dry oxidation process in the third temperature increase period and the third temperature maintenance period;
a step comprising a fourth temperature increase period of increasing temperature from the third target temperature to a fourth target temperature and a fourth temperature maintenance period of maintaining the fourth target temperature, wherein a fourth oxide film is formed on the third oxide film using a wet oxidation process in the fourth temperature maintenance period;
a step of removing the first to fourth oxide films;
a step of etching the sample wafer, from which the first to fourth oxide films are removed, to form haze on a surface of the sample wafer; and
a step of evaluating a defect region of the sample wafer based on the haze.