Patent ID: 11910585
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 10:
11. A memory device, comprising:
a memory cell region;
a first well pick-up (WPU) region;
a second WPU region, wherein the first WPU region, the memory cell region, and the second WPU region are sequentially arranged along a first direction; and
an n-type well disposed on the first WPU region, the memory cell region, and the second WPU region,
wherein the n-type well has a first portion extending continuously from the first WPU region to the second WPU region along the first direction, a second portion disposed on the first WPU region and extending lengthwise along a second direction perpendicular to the first direction, and a third portion disposed on the second WPU region and extending lengthwise along the second direction, wherein the second portion and the third portion are disposed on two sides of the first portion, and wherein the first, second, and third portions are continuously connected.