Patent ID: 11948618
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. A method, comprising:
applying programming pulses on one of a first word line and a second word line to program a non-volatile analog resistive memory cell coupled to the first word line and the second word line, wherein the non-volatile analog resistive memory cell comprises a first select transistor comprising a first ferroelectric field-effect transistor (FeFET) device which is connected to the first word line, a second select transistor comprising a second FeFET device which is connected to the second word line, and a resistive memory device connected to the first and second FeFET devices;
wherein the application of the programming pulses on the first word line causes:
modulating a polarization state of the first FeFET device in response to the programming pulses applied to the first FeFET device from the first word line, wherein the modulation of the polarization state of the first FeFET device causes a modulation of a programming current for tuning a conductance of the resistive memory device; and
tuning the conductance of the resistive memory device by incrementally increasing the conductance of the resistive memory device by the modulated programming current which is generated upon an activation of the first FeFET device in response to each programming pulse applied to the first FeFET device, while the second FeFET device is maintained in an off state; and

wherein the application of the programming pulses on the second word line causes:
modulating a polarization state of the second FeFET device in response to the programming pulses applied to the second FeFET device from the second word line, wherein the modulation of the polarization state of the second FeFET device causes a modulation of the programming current for tuning the conductance of the resistive memory device; and
tuning the conductance of the resistive memory device by incrementally decreasing the conductance of the resistive memory device by the modulated programming current which is generated upon an activation of the second FeFET device in response to each programming pulse applied to the second FeFET device, while the first FeFET device is maintained in an off state.