Patent ID: 11956943
Assignee: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. The method for manufacturing a memory according to claim 11, wherein the step of preparing a secondary gate, a second dielectric layer, a semiconductor layer, a first dielectric layer, a primary gate, a word line connected to the primary gate, and a first insulating layer sequentially on one side of a substrate comprises:
preparing the secondary gate on the one side of the substrate;
preparing the second dielectric layer on the secondary gate and the exposed substrate;
preparing the semiconductor layer on the second dielectric layer, so that an orthographic projection of the channel region of the semiconductor layer on the substrate and an orthographic projection of the source contact region of the semiconductor layer on the substrate are partially overlapped with an orthographic projection of the secondary gate on the substrate, respectively; and
making the source contact region and the drain contact region of the semiconductor layer to be conductive.