Patent ID: 11915774
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G  H

Claim 0:
1. A memory device, comprising:
a stack of multiple memory die electrically connected with one another by through wafer interconnects extending through the stack of multiple memory die, the stack of multiple memory die comprising multiple partitions respectively including one or more arrays from each of two or more memory die of the stack of multiple memory die, the multiple partitions comprising multiple first partitions established according to a first memory map; and
control logic operably coupled to the stack of multiple memory die, the control logic operable to monitor portions of the stack of multiple memory die to collect error data indicating defective portions within one or more of the multiple partitions, and to remove a defective portion from one or more of the multiple partitions.