Patent ID: 11961761
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A method for forming a semiconductor structure associated with mitigating pattern collapse, comprising:
etching a first trench within a first dielectric layer, wherein the first trench is defined by a first sidewall of the first dielectric layer;
forming a first metal line barrier within the first trench;
forming a first metal line within the first trench after the forming a first metal line barrier, wherein the first metal line is spaced apart from the first dielectric layer by the first metal line barrier;
forming a second dielectric layer above the first metal line and the first dielectric layer;
etching a second trench within the second dielectric layer, wherein:
a portion of the first dielectric layer is exposed through the second trench, and
the second trench overlies the first sidewall of the first dielectric layer;

forming a second metal line barrier within the second trench;
etching the second metal line barrier to expose a portion of the first metal line and a portion of the first metal line barrier; and
forming a second metal line within the second trench after the etching the second metal line barrier.