Patent ID: 11862560
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. The package structure of claim 5, wherein the first redistribution circuit structure further comprises a third build-up layer comprising a third metallization layer, a third dielectric layer partially covering the third metallization layer, and a second inter-layer film laterally wrapping around the third metallization layer, wherein the second build-up layer is located between the first build-up layer and the third build-up layer, and the second inter-layer film is sandwiched between the second dielectric layer and the third dielectric layer,
wherein the package structure further comprises conductive elements disposed on and electrically coupled to the first redistribution circuit structure through the third metallization layer, and the first redistribution circuit structure is located between the semiconductor die and the conductive elements, and
wherein an interface of the second dielectric layer and the second inter-layer film is located at a sidewall of the second portion of the second metallization layer, and an interface of the second inter-layer film and the third dielectric layer is located at a sidewall of the third metallization layer.