Patent ID: 11862481
Assignee: APPLE INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A chip structure comprising:
a semiconductor substrate;
a first front-end-of-the-line (FEOL) die area of a first die patterned into the semiconductor substrate; and
a back-end-of-the-line (BEOL) build-up structure including:
a lower metallization layer, an upper metallization layer, and a first metallization layer spanning over the first FEOL die area, wherein the first metallization layer is between the lower metallization layer and the upper metallization layer;
a split metallic seal structure including an inner metallic seal and an outer metallic seal arranged with one of the inner metallic seal and the outer metallic seal being a lower metallic seal overlapping the lower metallization layer and another of the inner metallic seal and the outer metallic seal being an upper metallic seal overlapping the upper metallization layer;
wherein portions of the inner metallic seal and the outer metallic seal are both formed in the first metallization layer; and
a through seal interconnect extending from the first FEOL die area and into a scribe region laterally outside of the outer metallic seal; and
wherein the split metallic seal structure is coupled to a charge source to control potential of at least one of the inner metallic seal and the outer metallic seal.