Patent ID: 11961577
Assignee: NXP USA, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 12:
13. An integrated circuit including built-in self-test (BIST) circuitry which performs on-chip testing of analog-to-digital converters (ADCs), the ADCs including a first set of ADCs of a first ADC type and a second set of ADCs of a second ADC type, different from the first ADC type, the integrated circuit comprising:
on-chip memory;
an N-bit differential digital-to-analog converter (DAC) used in performing the on-chip testing of the ADCs;
calibration circuitry coupled to the N-bit differential DAC and configured to generate a pair of calibration codes corresponding to each possible N-bit DAC input code for the N-bit differential DAC;
a memory engine, coupled to the calibration circuitry and the on-chip memory, and configured to:
store each pair of calibration codes in a memory line of the on-chip memory addressed by upper significant bits of a corresponding N-bit DAC input code, wherein, after generating all pairs of calibration codes, each memory line includes multiple pairs of calibration codes; and
obtain a first pair of calibration codes from the on-chip memory for a received DAC input code by initiating a read to receive read data from an address line in the on-chip memory addressed by N−1 upper significant bits of the received DAC input code and using a least significant bit (LSB) of the received DAC input code to select the first pair of calibration codes from the received read data.