Patent ID: 11966631
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A controller for a data storage device, comprising:
one or more memory devices comprising computer-readable instructions;
a processor coupled to the one or more memory devices configured to execute the computer-readable instructions and cause the controller to perform a method for command queue order adjustment in a data storage device, the method comprising:
receive a first command having a first queue ID and a second command having a second queue ID at a completion order adjustment module comprising a search;
store the first queue ID and the second queue ID in an array;
generate a first processed command and a second processed command, wherein the first processed command and the second processed command are processed in an order of a fast read to a read look ahead (RLA);
determine if the first processed command and second processed command are sequential commands;
search the array for other commands of the sequential commands;
wait to transfer until each command of a LBA sequence of commands is found;
reorder the first queue ID and the second queue ID such that the first processed command comprising the first queue ID is to be sent to a host before the second processed command comprising the second queue ID is sent to the host;
transfer data for each command of the sequence of commands to the host;
generate a host transfer done interrupt service routine (ISR) and then check for any pending transfers; and
search a target queue ID when there are pending transfers, wherein the searching comprises using a search module to search a RLA location, a normal read location, and a fast read location, wherein the RLA location, the normal read location, and the fast read location are separate and distinct locations within the search module.