Patent ID: 11894326
Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. The method of claim 10, furthercomprising:
providing a recess or opening extending from a first surface of the second substrate of the microelectronic component, at least a portion of the first surface of the second substrate having a planarized topography;
disposing a third conductive material having a third melting point within the recess or opening of the second substrate, extending normal to a plane of the second substrate and forming a first portion of the second interconnect structure; and
disposing a fourth conductive material having a fourth melting point different from the third melting point within the recess or opening of the second substrate, extending normal to the plane of the second substrate and contacting the first portion of the second interconnect structure and forming a second portion of the second interconnect structure.