Patent ID: 11910618
Assignee: KEPLER COMPUTING INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 14:
15. An apparatus comprising:
a first transistor having a first gate terminal coupled to a word-line, a first source terminal coupled to a bit-line, and a first drain terminal coupled to a storage node;
a second transistor coupled to the first transistor, wherein the second transistor includes a second gate terminal coupled to the storage node, a second source terminal couple to a sense line, and a second drain terminal coupled to a bias;
a plurality of bottom electrodes extending vertically compared to lateral side of the first transistor, wherein the plurality of bottom electrodes is coupled to the storage node; and
a plurality of capacitors having a first terminal coupled to the plurality of bottom electrodes, wherein a second terminal of an individual capacitor of the plurality of capacitors is partially coupled to an individual plate-line, and wherein the plurality of capacitors are non-planar capacitors.