Patent ID: 11870615
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An equalizer comprising a summing circuit,
wherein the summing circuit comprises:
a reference signal generator configured to generate a first reference signal and a second reference signal, based on a coefficient code;
a first non-overlap clock buffer configured to generate a first switching signal and a second switching signal by using the first reference signal; and
a first current source configured to receive the first switching signal and the second switching signal generated by the first non-overlap clock buffer, generate a first output current by using a bias voltage, and output the first output current to an output line,

wherein the first switching signal comprises a switching signal and a complementary switching signal that is a complementary signal to the switching signal, and
wherein a logic low period of the second switching signal is comprised in a logic high period of the complementary switching signal of the first switching signal.