Patent ID: 11907126
Assignee: ADVANCED MICRO DEVICES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A method comprising:
in response to a first branch prediction at a processor:
selecting a first op cache pipeline of a plurality of op cache pipelines of the processor, wherein the op cache pipelines provide decoded instructions to op cache entries, wherein selecting the first op cache pipeline further comprises selecting the first op cache pipeline based on operation flow criteria associated with the plurality of op cache pipelines, wherein the operation flow criteria specify selecting the first op cache pipeline based on at least two quality of service levels, including at least one quality of service level of a thread being processed by at least one of the plurality of op cache pipelines; and
providing a first set of operations associated with the first branch prediction to a dispatch stage of the processor via the selected first op cache pipeline.