Patent ID: 11914863
Assignee: RAMBUS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. A memory module comprising:
a first set of memory devices including at least a first memory device comprising a first unidirectional input port and a first unidirectional output port; and
a first serial data buffer integrated circuit device comprising:
command scheduling logic to generate memory device commands for writing to and reading from the first memory device based on a set of host-side input packets from a memory controller, the memory device commands including activate commands, read commands, and write commands scheduled to meet timing specifications of the first memory device;
a unidirectional serial host side input port to receive the host-side input packets from the memory controller;
a unidirectional serial memory side output port to transmit the memory device commands to the first unidirectional input port of the first memory device;
a unidirectional serial memory side input port to receive read data from the first unidirectional output port of the first memory device in response to a read command; and
a unidirectional serial host side output port to transmit the read data to the memory controller;

first communication lines coupling the first unidirectional input port of the first memory device and the unidirectional serial memory side output port of the serial data buffer; and
second communication lines coupling the first unidirectional output port of the first memory device and the unidirectional serial memory side input port of the serial data buffer.