Patent ID: 11893336
Assignee: CADENCE DESIGN SYSTEMS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. The medium of claim 1, wherein the first set of multicycle faults and/or defects are a set of multicycle cell-aware delay faults and/or defects detectable by the plurality of two-cycle delay test patterns and the second set of multicycle faults and/or defects include a set of multicycle cell-aware delay faults and/or defects which are detectable by delay test patterns with three or more clock cycles, and wherein a given multicycle cell-aware delay fault and/or defect of the second set of multicycle faults and/or defects is detectable by a given two-cycle delay test pattern of the plurality of two-cycle delay test patterns with sim-shifting.