Patent ID: 11901348
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A method of manufacturing a semiconductor package, comprising:
forming first and second relay bonding pads on a dummy substrate;
stacking a first semiconductor chip on the dummy substrate such that first chip pads are on a first surface of the first semiconductor chip, and a second surface of the first semiconductor chip that is opposite to the first surface of the first semiconductor chip faces the dummy substrate;
forming first bonding wires to connect the first chip pads of the first semiconductor chip with the first relay bonding pads;
stacking a plurality of second semiconductor chips on the first semiconductor chip;
forming second bonding wires to connect second chip pads of the second semiconductor chips with the second relay bonding pads;
covering the first semiconductor chip and the second semiconductor chips on the dummy substrate with a molding member to form a mold substrate;
removing the dummy substrate from the mold substrate such that the first and second relay bonding pads are exposed from a first surface of the mold substrate; and
forming a redistribution wiring layer on the first surface of the mold substrate, the redistribution wiring layer including redistribution wirings electrically connected to the first and second relay bonding pads.