Patent ID: 11940835
Assignee: FMAD ENGINEERING (SNG) PTE. LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A computing device comprising:
an interface configured to receive signals from a reference clock, wherein the reference clock has a fixed clock period;
a hardware clock signal generator that ticks at a variable clock period;
memory configured to store a local time value, wherein the local time value is increased by a local time increment on ticks of the hardware clock signal generator;
an integrated circuit containing a state machine configured to: (i) detect a signal from the reference clock, and (ii) in response to detecting the signal, read the local time value and store it as a current time value;
one or more processors configured to execute program instructions that cause the computing device to:
determine a difference between the current time value and a previous time value that was stored in response to receiving a previous signal from the reference clock, wherein the previous time value is based on a previous reading of the local time value;
based on the difference, determine an adjustment to the local time increment so that the local time value increases at a rate that is closer to that of the reference clock; and
modify the local time increment by the adjustment.