Patent ID: 11961884
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor structure, comprising:
first and second fin structures on a substrate;
an isolation region on the substrate and between the first and second fin structures;
a first gate structure disposed on the first fin structure and the isolation region;
a second gate structure disposed on the second fin structure and the isolation region;
a gate spacer on sidewalls of the first and second gate structures;
a dielectric layer on the isolation region and surrounding the first and second gate structures, wherein the dielectric layer comprises a first dielectric material; and
a fill structure on the isolation region and between the first and second gate structures, wherein the fill structure comprises:
a dielectric structure between the first and second gate structures and in contact with the gate spacer, the dielectric layer, and the first and second gate structures, wherein the dielectric structure comprises a second dielectric material different from the first dielectric material; and
an air gap enclosed by the dielectric structure, wherein the air gap is below top surfaces of the first and second fin structures.