Patent ID: 11892956
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. A non-transitory computer-readable medium comprising instructions thereon that, when executed by at least one processor, causes the at least one processor to perform operations comprising:
communicating, by a memory system and to a host device, a first message describing background operations to be performed at the memory system, the memory system comprising a memory controller and a plurality of memory locations;
after communicating the first message, receiving, by the memory system, from the host device, a second message indicating permission to execute the background operations;
after receiving the second message, initiating execution of, by the memory system, at least one of the background operations;
reading, by the memory system, time data from a descriptor memory location, the time data describing a time period when the memory system is to execute the at least one of the background operations, the descriptor memory location being a memory location of the plurality of memory locations that is accessible to the host device;
determining, by the memory system and prior to completing the at least one of the background operations, that the time period when the memory system is to execute the at least one of the background operations has expired; and
stopping, by the memory system, the at least one of the background operations.