Patent ID: 11888654
Assignee: NANYANG TECHNOLOGICAL UNIVERSITY
Field: Digital communication (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. An offset detector circuit, comprising:
a digital signal register configured to store M unit digital signals received in latest M signal periods, where M is a natural number, among digital signals generated based on an externally received single-ended Pulse Amplitude Modulation (PAM)-N signal, where N is an odd number;
a comparator configured to output comparison signals of a positive signal and a negative signal included in differential signals generated from a differential signal generator based on the single-ended PAM-N signal;
a comparison result register configured to store M unit comparison signals corresponding to the latest M signal periods among the comparison signals;
a pattern detector configured to output a detection signal when the M unit digital signals match a predetermined signal pattern; and
an offset checker configured to check patterns of the M unit comparison signals in response to the detection signal, and output an offset detection signal when the patterns of the M unit comparison signals match a predetermined offset pattern.