Patent ID: 11930629
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 10:
11. A semiconductor memory device, comprising:
a plurality of memory cell transistors on a substrate;
a first line layer on the memory cell transistors; and
a second line layer on the first line layer,
wherein the first line layer includes a bit line, a power line, a first lower landing pad, and a second lower landing pad,
wherein the second line layer includes a ground line having a plurality of openings,
wherein the ground line includes a pair of first segments that extend in a first direction and a pair of second segments that extend in a second direction intersecting the first direction,
wherein each of the openings is defined by the pair of first segments and the pair of second segments,
wherein the second line layer further includes first vias provided below the ground line,
wherein the first vias are connected only to the second segments and not to the first segments,
wherein the power line included in the first line layer is under a corresponding one of the first segments of the ground line included in the second line layer, and the power line vertically overlaps the corresponding one of the first segments,
wherein both sidewalls of the power line vertically overlap the corresponding one of the first segments such that a width of the power line is less than or equal to a width of the corresponding one of the first segments, and wherein the ground line has electrical connection through the first vias and the first lower landing pad to a terminal of a first memory transistor of the memory cell transistors.