Patent ID: 11923408
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor structure, comprising:
one or more channel layers;
a gate structure engaging the one or more channel layers;
a first source/drain feature connected to a first side of the one or more channel layers and adjacent to the gate structure;
a first dielectric cap disposed over the first source/drain feature, wherein a bottom surface of the first dielectric cap is below a top surface of the gate structure;
a second source/drain feature connected to a second side of the one or more channel layers that is opposite to the first side of the one or more channel layers, wherein the gate structure is disposed between the first and the second source/drain features;
a contact plug disposed over and electrically connected to the second source/drain feature;
a second dielectric cap disposed over the contact plug;
a first via disposed under and electrically connected to the first source/drain feature; and
a power rail disposed under and electrically connected to the first via.