Patent ID: 11927632
Assignee: INVENTEC (PUDONG) TECHNOLOGY CORPORATION
Field: Measurement (Instruments)
Classification: CPC G | IPC G

Claim 0:
1. A dual in-line memory module (DIMM) slot test system without series connection of test board through joint test action group (JTAG), wherein the DIMM slot test system comprises
a circuit board under test, comprising a JTAG connection interface, a central processing unit and at least one DIMM slot, wherein each of the at least one DIMM slot comprises power pins, ground pins, differential pins and IO pins, some of the IO pins are selected as data transmission pins, some of the IO pins are selected as control pins, wherein the differential pin, at least some of the IO pins and the CPU are electrically connected to each other;
at least one test board, wherein each of the at least one test board comprises:
a DIMM connector interface, inserted into one of the at least one DIMM slot; and
at least one complex programmable logic device (CPLD) chip, electrically connected to the DIMM connector interface;

a test access port (TAP) controller, electrically connected to the circuit board under test through the JTAG connection interface; and
a test device, electrically connected to the TAP controller;
wherein the test device generates a test signal and provide the test signal to the TAP controller, the TAP controller converts the test signal into a second test signal with JTAG signal format and provides the second test signal to the CPU, the CPU generates test data or a third test signal based on the second test signal with JTAG signal format, the CPU transmits the test data to specified one of the at least one CPLD chip through the differential pins or the IO pins, the specified one of the at least one CPLD chip records the received data as a test result, the CPU transmits the third test signal to the specified one of the at least one CPLD chip through the control pins, the specified one of the at least one CPLD chip tests the power pins or the ground pins to read and record values of the power pins or the ground pins as the test result, the CPU generates a test result read signal and transmits the test result read signal to the specified one of the at least one CPLD chip through the control pins, to obtain the test result through the data transmission pin and send the test result to the test device.