Patent ID: 11967394
Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. The memory system of claim 1, further comprising:
a plurality of first word lines (WLs) each coupled a first memory row circuit of the plurality of first memory row circuits;
a plurality of second WLs each coupled to a second memory row circuit of the plurality of second memory row circuits; and
a memory driver circuit coupled to the plurality of first WLs and the plurality of second WLs;
the memory driver circuit configured to:
receive a memory access request comprising a memory address; and
in response to the memory access request, activate one of a first WL of the plurality of first WLs and a second WL of the plurality of second WLs, in response to the memory address corresponding to a respective one of:
the first memory row circuit of the plurality of first memory row circuits coupled to the activated first WL; and
the second memory row circuit of the plurality of second memory row circuits coupled to the activated second WL.