Patent ID: 11962676
Assignee: SYNOPSYS, INC.
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to:
provide compensation circuitry of clock and data recovery (CDR) circuitry, wherein the compensation circuitry comprises:
an input node that receives a first compensation value;
a first delay element that receives the first compensation value from the input node and delays the first compensation value; and
a summation element that subtracts a delayed version of the first compensation value from the first compensation value to generate a first non-linearity value, wherein the first delay element is coupled between the input node and a first input of the summation element, and wherein a second input of the summation element is coupled to the input node, wherein the compensation circuitry generates a first compensation signal based on the first non-linearity value; and

provide phase accumulation circuitry of the CDR circuitry, wherein the phase accumulation circuitry compensates for a first non-linearity within phase mixer (PMIX) circuitry based on the first compensation signal.