Patent ID: 11880333
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A method comprising:
reading memory region configuration definitions for memory regions, by a processor, wherein each memory region configuration definition identifies a size of a memory region, identifies a device where the memory region is located, and identifies another device allowed access to the memory region;
for each device allowed access to one of the memory regions, writing the size of the memory region, by the processor, in a base address register (BAR) of a function circuit of an interface circuit coupled to the device, wherein each device is coupled to a different interface circuit;
for each device having one of the memory regions, configuring a translation register of an output address translation unit (ATU) in the interface circuit coupled to the device by the processor with a local address; and
for each device allowed access to one of the memory regions, configuring a translation register of an input ATU in the function circuit of the interface circuit coupled to the device by the processor with the local address, wherein the translation register of the input ATU is associated with the BAR of the function circuit of the interface circuit.