Patent ID: 11881463
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A coreless semiconductor package comprising:
plurality of dielectric layers;
a magnetic inductor at least partly embedded within a first group of the plurality of layers;
an interconnect bridge adjacent the magnetic inductor, the interconnect bridge embedded within a second group of the plurality of layers;
a plurality of vias and interconnections in the plurality of layers, configured to connect a die of the interconnect bridge to other circuitry;
a first level interconnect (RI) on a first side of the package, the RI configured to connect to at least some of the plurality of vias and interconnections; and
a plurality of conductive BGA pads on a second side of the package opposite the first side of the package.