Patent ID: 11914473
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus, comprising: a controller associated with a memory device, wherein the controller is configured to cause the apparatus to:
receive, at a memory system, a write command indicating a range of logical addresses of a memory array of the memory system;
transmit a plurality of data requests each comprising an indicator of a respective subset of the range of logical addresses indicated in the write command;
receive a plurality of protocol units in response to the plurality of data requests, each of the plurality of protocol units corresponding to a data request and comprising data associated with the respective subset of the range of logical addresses of the corresponding data request;
process the plurality of protocol units to obtain at least one data storage unit corresponding to at least a subset of protocol units of the plurality of protocol units;
determine, based at least in part on processing the plurality of protocol units, an error associated with one or more protocol units of the plurality of protocol units;
retransmit one or more data requests corresponding to the one or more protocol units associated with the error;
receive retransmissions of the one or more protocol units associated with the error in response to the retransmission of the one or more data requests; and
reprocess the one or more protocol units to obtain the at least one data storage unit.