Patent ID: 11934330
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 9:
10. An apparatus comprising:
a multi-tile central processing unit (CPU) package comprising multiple tiles, a first interface, and a second interface, wherein:
the first interface is to provide communication among at least two of the multiple tiles
the second interface is to provide communication among at least one of the multiple tiles and a network interface,
at least one of the multiple tiles comprises at least one processor core,
at least one of the multiple tiles comprises an offload processor and a buffer,
the offload processor is to process data to be transmitted in a packet using the network interface and process second data received in a packet by the network interface, and
the offload processor comprises circuitry to determine whether to store the processed data in the buffer of the at least one of the multiple tiles that comprises the offload processor and the buffer or a system memory after processing by the offload processor and determine whether to store the processed second data in the buffer of the at least one of the multiple tiles that comprises the offload processor and the buffer or the system memory after processing by the offload processor.