Patent ID: 11935898
Assignee: JAPAN DISPLAY INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A semiconductor device comprising:
a first gate electrode;
a first gate insulating layer on the first gate electrode;
a first oxide semiconductor layer on the first gate insulating layer;
source and drain electrodes connected to the first oxide semiconductor layer;
a second gate insulating layer on the first oxide semiconductor layer;
a second oxide semiconductor layer on the second gate insulating layer;
a second gate electrode on the second oxide semiconductor layer, the second gate electrode being in contact with the second oxide semiconductor layer;
a first insulating layer on the second gate electrode, the first insulating layer having a part of a first aperture overlapping the second oxide semiconductor layer in a planar view; and
a first connecting electrode electrically connecting the first gate electrode and the second gate electrode via the first aperture.