Patent ID: 11942165
Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. A memory device, comprising:
a memory array comprising memory cells;
a page buffer comprising a first latch circuit, a second latch circuit, and a third latch circuit,
wherein the first latch circuit is configured to store verification data during a verification operation,
the second latch circuit is configured to store failure pattern data during the verification operation, and
the third latch circuit is configured to store program data; and

control logic configured to control access to the memory array in response to commands and generate status information for an external processor,
wherein the first latch circuit is further configured to store inverted inhibit information, and the inverted inhibit information is configured to indicate unverified states of the memory cells that include a first state and remaining states subsequent to the first state.