Patent ID: 11864386
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 7:
8. A memory structure, comprising:
vertically-alternating tiers of insulative levels and memory cell levels, the memory cell levels containing memory cells, individual of the memory cells comprising:
a transistor comprising first and second source/drain regions having a horizontally-oriented channel region there-between and comprising a gate operatively proximate the channel region;
a conductive pillar extending elevationally through multiple of the levels of memory cells, the gate of multiple of the memory cells comprised by the stack being directly electrically coupled to the conductive pillar;
a conductive line structure extending horizontally within each memory cell level; and
a horizontal longitudinally-elongated line that is above or below the stack and directly electrically coupled to the conductive pillar.