Patent ID: 11950412
Assignee: LONGITUDE FLASH MEMORY SOLUTIONS LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. The device of claim 1, further comprising:
a drain select transistor comprising:
a drain select gate electrode; and
a drain select charge trapping layer disposed between the base layer and the drain select gate electrode;

a third memory transistor comprising:
a third gate electrode; and
a third charge trapping layer disposed between the base layer and the third gate electrode;

wherein the third memory transistor and the drain select transistor are disposed in the NAND string;
wherein the drain select transistor is at an other end of the NAND string and the third memory transistor is adjacent to the drain select transistor;
wherein the third memory transistor and the drain select transistor are separated by a third distance, which defines a third region;
wherein there is no diffusion region in the third region defined by the third distance;
wherein a conductive path is formed in the third region between the third memory transistor and the drain select transistor due to gate fringing field effects associated with the third memory transistor and the drain select transistor; and
wherein the drain select transistor does not include a diffusion region for source and/or drain.