Patent ID: 11949595
Assignee: INTEL CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A method comprising:
receiving, at a first forwarder node from across a first virtual channel, a packet from a source node on a silicon substrate, the first forwarder node and the source node among a plurality of hardware elements within a first hierarchy of hardware elements, the first hierarchy of hardware elements arranged in at least two columns and at least two rows, wherein the packet is routed from the source node to the first forwarder node using dimension order routing (DOR) within the first hierarchy of hardware elements;
determining a second forwarder node based on a reflection look-up table (LUT) corresponding to the first forwarder node, the second forwarder node among a plurality of hardware elements within a second hierarchy of hardware elements, the second hierarchy of hardware elements arranged in at least two columns and at least two rows,; and
forwarding the packet to the second forwarder node across a second virtual channel, the second virtual channel different from the first virtual channel, wherein the packet is routed from the first forwarder node to the second forwarder node using DOR within a plurality of forwarder nodes, the plurality of forwarder nodes comprising the first forwarder node and the second forwarder node, wherein each of the forwarder nodes of the plurality of forwarder nodes resides in its own hierarchy.