Patent ID: 11934281
Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device, comprising:
an array of memory cells comprising P groups of banks, each group of banks comprising N main banks and a redundant bank such that P redundant banks in the P groups of banks, respectively, are included in and shared by the P groups of banks, where each of P and N is a positive integer with P>1;
an input/output (I/O) circuit coupled to the P groups of banks and configured to direct P×N pieces of data to or from P×N working banks, respectively; and
I/O control logic coupled to the I/O circuit and configured to:
determine the P×N working banks from the P groups of banks based on bank fail information indicative of K failed main banks from the P groups of banks, the P×N working banks comprising K redundant banks of the P redundant banks, where K is a positive integer not greater than P; and
control the I/O circuit to direct P×N pieces of data to or from the P×N working banks, respectively.