Patent ID: 11914253
Assignee: CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. An array substrate, comprising
a base;
a pixel electrode and a thin film transistor, disposed on the base;
a passivation layer, covering the thin film transistor and the pixel electrode, the passivation layer being provided with a transferring through hole exposing the pixel electrode and a drain electrode or a source electrode of the thin film transistor simultaneously;
a connection electrode, disposed on the passivation layer and at the transferring through hole,
wherein the connection electrode is connected with the pixel electrode, and the drain electrode or the source electrode through the transferring through hole,
wherein the array substrate further comprises a gate line and a data line, the thin film transistor comprises a gate electrode, an active layer, the source electrode and the drain electrode, the pixel electrode, the gate line and the gate electrode are disposed on the base, the pixel electrode, the gate line and the gate electrode are covered with a gate insulation layer, the active layer, the source electrode, the drain electrode and the data line are disposed on the gate insulation layer, and a conductive channel is formed between the source electrode and the drain electrode,
wherein a first compensation block is disposed at a side of the connection electrode close to the gate line, an orthographic projection of the first compensation block on the base includes at least a portion of an orthographic projection of an edge of the drain electrode or the source electrode at a side adjacent to the gate line on the base,
wherein the first compensation block extends from a mainbody of the connection electrode towards the gate line, and a size of the first compensation block is smaller than a size of the mainbody in a direction parallel to a direction of the gate line.