Patent ID: 11908896
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A method, comprising:
receiving a semiconductor substrate that includes an integrated circuit (IC) cell and a well tap cell surrounding the IC cell;
forming first active regions in the well tap cell and second active regions in the IC cell, wherein each of the first and second active regions is surrounded by an isolation feature;
forming a hard mask within the well tap cell, wherein the hard mask includes openings that define first source/drain (S/D) regions on the first active regions of the well tap cell;
forming gate stacks on the second active regions within the IC cell and absent from the well tap cell, wherein the gate stacks define second S/D regions on the second active regions;
epitaxially growing first S/D features in the first S/D regions using the hard mask to constrain the epitaxially growing; and
forming contacts landing on the first S/D features within the well tap cell and extending to a top surface of the isolation feature.