Patent ID: 11899586
Assignee: SYNOPSYS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. An integrated circuit (IC), comprising:
a first circuit to store a set of cache entries, wherein each cache entry includes one or more words of data, wherein each word of data corresponds to a memory address, and wherein the memory address is partitioned into a tag, an index, and an offset;
a first structure to store a first subset of tag bits corresponding to the set of cache entries;
a second structure to store a second subset of tag bits corresponding to the set of cache entries; and
a second circuit to:
use the index to select m entries in the first structure;
match a first portion of tag bits of the memory address with the m entries in the first structure;
in response to the first portion of tag bits of the memory address matching n entries in the first structure, where n is less than m, match a second portion of tag bits of the memory address with n entries in the second structure corresponding to the n entries in the first structure; and
wherein the matching the first portion of tag bits of the memory address with the m entries in the first structure and the matching the second portion of tag bits of the memory address with n entries in the second structure is performed in a single clock cycle.