Patent ID: 11862232
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. A circuit for data transmission, comprising:
a plurality of mode register decoding modules, configured to generate a mode register unselected enable signal, a mode register read enable signal, or a mode register write enable signal according to received mode register address information, a mode register read control signal, or a mode register write control signal;
a plurality of mode register read-write modules, disposed corresponding to the plurality of mode register decoding modules, electrically connected to a data line, a first cache module, and corresponding mode register decoding modules, configured to cache data on the data line according to the received mode register write enable signal in a write state, and further configured to output selected data and unselected data after setting the unselected data to zero according to the mode register read enable signal and the mode register unselected enable signal in a read state; and
a logic gate module, electrically connected to the first cache module and each mode register read-write module, and configured to calculate an OR value of the data outputted by the each mode register read-write module in the read state and to output a calculation result.