Patent ID: 11901821
Assignee: M3 TECHNOLOGY INC.
Field: Electrical machinery, apparatus, energy (Electrical engineering)
Classification: CPC H  Y | IPC H

Claim 11:
12. The apparatus of claim 1, wherein the ramp generator comprises:
a first diode and a first ramp capacitor connected in series, and wherein an anode of the first diode is configured to receive a gate drive signal of the high-side switch of the first phase of the power converter, and the first ramp capacitor is connected to a voltage ramp node;
a first ramp resistor connected between a common node of the first diode and the first ramp capacitor, and ground;
a second diode and a second ramp capacitor connected in series, and wherein an anode of the second diode is configured to receive a gate drive signal of the high-side switch of the second phase of the power converter, and the first ramp capacitor is connected to the voltage ramp node;
a second ramp resistor connected between a common node of the second diode and the second ramp capacitor, and ground;
a third ramp resistor and a third ramp capacitor connected in series between a switching node of the first phase of the power converter and the voltage ramp node;
a fourth ramp resistor and a fourth ramp capacitor connected in series between a switching node of the second phase of the power converter and the voltage ramp node;
a fifth ramp capacitor and a fifth ramp resistor connected in parallel between the voltage ramp node and ground;
a first transconductance amplifier having a non-inverting input connected to the voltage ramp node, and an inverting input connected to ground;
a second transconductance amplifier having a non-inverting input configured to receive a feedback signal of the power converter, and an inverting input configured to receive an error signal generated by an error amplifier of the power converter, and wherein an output of the first transconductance amplifier and an output of the second transconductance amplifier are connected together and further connected to ground through a resistor; and
a comparator having an inverting input connected to the output of the first transconductance amplifier and the output of the second transconductance amplifier, and a non-inverting input connected to ground, and wherein the comparator is configured to generate the set signal.