Patent ID: 11886740
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. An apparatus, comprising:
a controller configured to cause the apparatus to:
receive, by a host system and from one or more virtual machines associated with the host system, a plurality of commands to access a memory system common to the one or more virtual machines;
store, in a command queue of the host system associated with the memory system, the plurality of commands and a set of parameters associated with each command of the plurality of commands according to a first order;
arrange, by the host system, the plurality of commands within the command queue from the first order to a second order that is based at least in part on one or more identified patterns of accessing sequential addresses in the plurality of commands; and
transmit the plurality of commands from the host system to the memory system based at least in part on the second order.