Patent ID: 11886377
Assignee: CORNAMI, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G  H

Claim 18:
19. The plurality of reconfigurable arithmetic circuits arranged in an array of claim 18, wherein two adjacent linked reconfigurable arithmetic circuits having the pair configuration, of the plurality of reconfigurable arithmetic circuits, are configurable to perform at least two mathematical computation or functions selected from the group consisting of: a 32-bit integer for signed and unsigned 32-bit integer values (INT32) multiply per cycle; a 64-bit integer for signed and unsigned 64-bit integer values (INT64) multiply in a 4-cycle sequence using the accumulator circuit to add four 32×32 partial products; sum of a plurality of IEEE single precision or a plurality of 24-bit integer for signed and unsigned 24-bit integer values (INT24) multiplies per cycle; sum of a plurality of parallel IEEE half precision, 16-bit brain floating point (“BFLOAT”) (BFLOAT16) or 16-bit integer for signed and unsigned 16-bit integer values (INT16) multiplies per cycle; sum of a plurality of parallel IEEE quarter precision or 8-bit integer for signed and unsigned 8-bit integer values (INT8) multiplies per cycle; a half-precision or INT16 complex multiply per cycle; a plurality of multiplies and a plurality of adds; a fused add; an accumulation; and combinations thereof.