Patent ID: 11915743
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 18:
19. The circuit of claim 17, further comprising:
first and second data input terminals;
first and second NOR gates, the first NOR gate having a first input terminal coupled to the first data input terminal and a second input terminal coupled to the clock input terminal, the second NOR gate having a first input terminal coupled to the second data input terminal and a second input terminal coupled to the clock input terminal;
a first input transistor coupled between the second voltage terminal and the first bit line, and having a gate coupled to an output of the first NOR gate;
a second input transistor coupled between the second voltage terminal and the second bit line, and having a gate coupled to an output of the second NOR gate.