Patent ID: 11966595
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 15:
16. A memory system, comprising:
a first memory die in a set of memory dies; and
one or more controllers coupled with the first memory die, the one or more controllers operable to cause the memory system to:
generate, by a power management circuit on the first memory die, a first voltage for operating the set of memory dies;
provide, to a second memory die in the set of memory dies, the first voltage from the power management circuit on the first memory die; and
receive, at the first memory die, a second voltage from the second memory die that is a different level than the first voltage and that is based at least in part on the first voltage provided from the power management circuit on the first memory die.