Patent ID: 11935897
Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 2:
3. A display device comprising:
a first transistor;
a first circuit;
a second circuit;
a third circuit;
a first wiring;
a second wiring; and
a third wiring,
wherein each of the first circuit, the second circuit, and the third circuit includes a second transistor, a first capacitor, and a display element,
wherein the second circuit further includes a third transistor and a second capacitor,
wherein, in each of the first circuit, the second circuit, and the third circuit, one of a source and a drain of the second transistor is electrically connected to one electrode of the first capacitor,
wherein, in each of the first circuit, the second circuit, and the third circuit, the one electrode of the first capacitor is electrically connected to the display element,
wherein the first wiring is electrically connected to the other of the source and the drain of the second transistor in the second circuit,
wherein the second wiring is electrically connected to the other of the source and the drain of the second transistor in the third circuit,
wherein the third wiring is electrically connected to one of a source and a drain of the first transistor which is provided outside of the first circuit, the second circuit, and the third circuit,
wherein the other of the source and the drain of the first transistor is electrically connected to the other electrode of the first capacitor in each of the first circuit, the second circuit, and the third circuit,
wherein a gate of the second transistor in the second circuit is electrically connected to a fourth wiring,
wherein the one of the source and the drain of the second transistor in the second circuit is electrically connected to one of a source and a drain of the third transistor, the display element in the second circuit, and one electrode of the second capacitor, and
wherein the first transistor is not provided in a signal line driver circuit and a scan line driver circuit.