Patent ID: 11967293
Assignee: JAPAN DISPLAY INC.
Field: Optics (Instruments)
Classification: CPC G | IPC G

Claim 0:
1. An electronic device comprising:
a plurality of scanning lines extending along a first direction and aligned along a second direction intersecting the first direction;
a plurality of signal lines extending along the second direction and aligned the first direction;
a plurality of pixels disposed in a display area and provided at intersections of the plurality of scanning lines and the plurality of signal lines; and
an inspection circuit disposed in a non-display area different from the display area and including a plurality of first switch elements connected to the plurality of scanning lines;
a plurality of second switch elements disposed in the non-display region and connected to the plurality of signal lines, wherein
the plurality of first switch elements is oxide semiconductor transistors including an oxide semiconductor layer,
each of the plurality of first switch elements of the inspection circuit includes at least two transistors connected in series to one of the plurality of scanning lines,
the at least two transistors include a first transistor and a second transistor,
a gate of the first transistor and a gate of the second transistor are connected to a first wiring line,
one of a source and a drain of the first transistor is connected to the other of a source and a drain of the second transistor,
the other of a source and a drain of the first transistor is connected to a first scanning line of the plurality of scanning lines,
one of the source and the drain of the second transistor is connected to a second wiring line,
the second wiring is connected to one of the source and the drain of the second transistor of the first switch element connected to a second scanning line different from the first scanning line,
the plurality of second switch elements include third transistors, and
a gate electrode of each of the third transistors is connected to the first wiring line.