Patent ID: 11900038
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 1:
2. The method of claim 1, wherein said generating the power wire topology network according to the power layout comprises:
determining intersections of the first layer of metal wires and the second layer of metal wires as the power child nodes;
arranging the parasitic element between every two power child nodes, the parasitic element comprising a first parasitic resistance, a second parasitic resistance, and a parasitic capacitance, wherein a first end of the first parasitic resistance is connected to a first power child node, a second end of the first parasitic resistance is connected to a first end of the second parasitic resistance and a first end of the parasitic capacitance, a second end of the second parasitic resistance is connected to a second power child node, and a second end of the parasitic capacitance is connected to a grounding terminal; and
obtaining the power wire topology network according to the first layer of metal wires, the second layer of metal wires, the power child nodes, and the parasitic element.