Patent ID: 11875836
Assignee: KEPLER COMPUTING INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 18:
19. A system comprising:
a memory organized in a plurality of memory banks, wherein the plurality of memory banks comprises memory bit-cells, and wherein an individual memory bit-cell includes a capacitor comprising a non-linear polar material;
a processor circuitry coupled to the memory; a memory controller coupled to the memory and the processor circuitry, wherein the memory controller includes one or more circuitries which improve memory endurance of the memory via wear leveling, wherein the memory controller is to apply an outlier compensation scheme before or after the wear leveling, and wherein an array outside of a memory bank of the plurality of memory banks is queried; and
a communication interface to allow the processor circuitry to communicate with another device.