Patent ID: 11971740
Assignee: NXP B.V.
Field: Basic communication processes (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A timing error detection and correction circuit comprising:
a data-path including at least one logic gate and coupled between an output of a first flop-flop and an input of a second flip-flop,
a clock unit configured to receive a reference clock and to provide a delayed reference clock;
a transition detector coupled to a node on the data-path and configured to detect a data value transition on the node;
an error detection circuit coupled to the transition detector and the clock unit and configured to detect an error in response to the data value transition being detected during a time period between a transition of the reference clock and a corresponding transition of the delayed reference clock;
a timing correction circuit coupled to the error detection circuit and configured
to output a system clock derived from the delayed reference clock and
to provide the system clock to the first flip-flop and the second flip-flop and

wherein the timing correction circuit is further configured to adapt the system clock in response to an error being detected.