Patent ID: 11881860
Assignee: SK HYNIX INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 13:
14. The multi-phase clock signal alignment circuit of claim 9, wherein during the phase adjustment operation:
the clock selection circuit selects the first clock signal as the alpha clock signal and the third clock signal as the beta clock signal,
the first clock delay circuit provides the first selection clock signal by outputting the alpha clock signal delayed by a second interval corresponding to a quarter of the period of the first clock signal,
the second clock delay circuit provides the second selection clock signal by outputting the beta clock signal,
the phase detection circuit detects a phase difference between a rising edge of the first selection clock signal and the second selection clock signal, and
the phase control circuit controls a corresponding phase delay circuit so that a rising edge of the third clock signal is adjusted according to the phase difference.