Patent ID: 11966277
Assignee: DELL PRODUCTS L.P.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A storage error identification/reduction system, comprising:
a storage subsystem including a block;
a storage error identification/reduction subsystem that is coupled to the storage subsystem and that is configured to:
receive first data;
write the first data to a plurality of first storage locations in the block while writing storage error identification data to at least one second storage location in the block that is located adjacent at least one of the plurality of first storage locations, wherein the storage error identification data includes predetermined values that are written to predetermined locations included in the at least one second storage location in the block;
read the storage error identification data from the at least one second storage location;
identify, based on the predetermined values and predetermined locations of the storage error identification data, errors resulting from the reading of the storage error identification data;
determine, based on the errors, at least one error reduction operation that is configured to reduce errors associated with reading the first data; and
perform the at least one error reduction operation.