Patent ID: 11942138
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. The memory system of claim 1, wherein the semiconductor memory device includes:
a mode setting circuit suitable for storing the row-hammer data, and providing the stored row-hammer data to the memory controller through a data bus in response to a mode register read command;
a refresh control circuit suitable for generating a plurality of secondary sampling addresses by sampling the active address, sequentially outputting the plurality of secondary sampling addresses as a second row-hammer address according to a second target refresh command, and outputting a target address by selecting any of the first row-hammer address and the second row-hammer address; and
a row control circuit suitable for performing the target refresh operation on the one or more word lines corresponding to the target address according to the first target refresh command or the second target refresh command.