Patent ID: 11887648
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 16:
17. A semiconductor memory device, comprising:
a semiconductor substrate;
an etch stop layer arranged on the semiconductor substrate, the etch stop layer including an oxynitride;
a common source semiconductor layer doped with impurities of a first conductivity type and arranged on the semiconductor substrate;
a plurality of insulating layers and a plurality of word line structures alternately stacked on the common source semiconductor layer;
a memory cell dielectric layer comprising a gate insulating layer and a charge trap layer sequentially covering an internal sidewall of each of a plurality of channel holes, wherein the plurality of channel holes penetrate the plurality of insulating layers, the plurality of word line structures, and the etch stop layer in a vertical direction, and extend into the semiconductor substrate;
a plurality of memory cell structures each comprising:
a filling semiconductor layer arranged on a barrier insulating layer, the filling semiconductor layer located apart from the memory cell dielectric layer and filling some of a lower portion of each of the plurality of channel holes;
a channel layer arranged on the memory cell dielectric layer, being apart from the filling semiconductor layer with the common source semiconductor layer arranged therebetween, filling a first region of an upper portion of each of the plurality of channel holes, and comprising a material identical to that of the filling semiconductor layer; and
a drain layer covering an upper surface of the channel layer, filling a second region of the upper portion of each of the plurality of channel holes, and doped with impurities of a second conductivity type different from the first conductivity type; and

a plurality of bit lines each electrically connected to the drain layer of each of the plurality of memory cell structures, respectively, extending on the plurality of memory cell structures in a first horizontal direction, and having a certain distance from each other in a second horizontal direction orthogonal to the first horizontal direction.