Patent ID: 11968290
Assignee: KONINKLIJKE PHILIPS N.V.
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A circuit compiling device comprising:
a memory circuit,
wherein the memory circuit is configured to store a circuit,
wherein the circuit comprises a plurality of circuit wires and at least one conjunction subcircuit(s),
wherein the circuit wires comprise input wires and at least one output wire(s),
wherein the input wires correspond to a plurality of function input bits,
wherein the at least one output wires(s) correspond to at least one function output bit(s),
wherein the at least one function output bit(s) comprise a first function output bit,
wherein the at least one conjunction subcircuit(s) comprises a first conjunction subcircuit,
wherein each of the at least one conjunction subcircuit(s) is arranged to compute a conjunction of at least two function input bits and at least one XOR subcircuit(s),
wherein each of the at least one XOR subcircuit(s) is arranged to compute the first function output bit;

a processor circuit,
wherein the processor circuit is configured to compile a function into the circuit,
wherein the function computes the at least one function output bit(s) from the plurality of function input bits,

wherein the processor circuit is configured to represent each of the at least one function output bit(s) as a sum of interpolation terms,
wherein each of the sum of interpolation terms is a product of zero or more of the function input bits,
wherein the plurality of function input bits and the interpolation terms form a plurality of interpolation terms;

wherein the processor circuit is configured to select a first interpolation term and a second interpolation term from the plurality of interpolation terms for each current interpolation term of the plurality of interpolation terms, when the current interpolation term is a product of multiple function input bits,
wherein the current interpolation term is computed as a product of the first interpolation term and the second interpolation term,
wherein the current interpolation term is arranged to signal a selection error if no first interpolation term and second interpolation term can be selected; and

wherein the processor circuit is configured to compile the first conjunction subcircuit for each current interpolation term of the plurality of interpolation terms, when the current interpolation term is a product of multiple function input bits,
wherein the first conjunction subcircuit computes the current interpolation term,
wherein the compiling of the first conjunction subcircuit comprises providing a circuit wire corresponding to the current interpolation term as a conjunction of a first circuit wire corresponding to the first interpolation term and a second circuit wire corresponding to the second interpolation term; and

wherein the processor circuit is configured to compile at least one XOR subcircuit(s),
wherein the first function output bit is computed by a current XOR subcircuit,
wherein the first function output bit is represented as a sum of current interpolation terms,
wherein compiling the current XOR subcircuit comprises providing an output wire of the at least one output wires(s) corresponding to the first function output bit as a XOR of wires corresponding to the current interpolation terms.