Patent ID: 11940866
Assignee: IMAGINATION TECHNOLOGIES LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. A graphics processing unit configured to receive a test task comprising a predefined set of instructions for execution on the graphics processing unit, the predefined set of instructions being configured to perform a predetermined set of operations on the graphics processing unit when executed for predefined input data, the graphics processing unit comprising:
processing logic being configured to, in a test phase, process the test task by executing the predefined set of instructions for the predefined input data first and second times at the graphics processing unit so as to, respectively, generate first and second outputs;
a check unit being configured to raise a fault signal if the first and second outputs do not match;
the graphics processing unit being further configured to receive one or more non-test tasks for processing at the graphics processing unit;
the processing logic being configured to, in a non-test phase, process each of the one or more non-test tasks at the graphics processing unit a single time so as to generate a non-test output; and
for a period of time in which the test phase and the non-test phase are alternated between more than once, the processing logic being configured to operate in the test phase for x % of the time, and operate in the non-test phase for (100−x) % of the time;
wherein x is adaptive in dependence on:
a rate at which fault signals are being raised; and/or
an indicated safety-criticality of the non-test tasks to be processed by the graphics processing unit in the non-test phase.