Patent ID: 11927625
Assignee: POWERCHIP SEMICONDUCTOR MANUFACTURING CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A voltage contrast defect analysis method, comprising:
performing a voltage contrast defect detection on a die to be tested by using an electron beam inspection machine to find out a defect address of a voltage contrast defect;
obtaining a first scanning electron microscope image at the defect address of the die to be tested by using a scanning electron microscope;
measuring a first critical dimension of the first scanning electron microscope image at the defect address of the die to be tested;
comparing the first critical dimension on the die to be tested with a corresponding second critical dimension on a reference die where no voltage contrast defect occurs at the defect address to determine whether the first critical dimension and the second critical dimension are the same;
before obtaining the first scanning electron microscope image, obtaining a second scanning electron microscope image at the defect address of the die to be tested by using the scanning electron microscope, wherein an image quality of the first scanning electron microscope image is higher than an image quality of the second scanning electron microscope image; and
determining whether there is a physical defect according to the second scanning electron microscope image.