Patent ID: 11941339
Assignee: SYNOPSYS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A method for generating a routing for an integrated circuit (IC) design, the method comprising:
receiving information describing a set of pin-pairs of an integrated circuit (IC) design;
determining, by a processor, an initial routing of the IC design by (i) defining connected wires between each pin-pair in the set of pin-pairs, and (ii) evaluating a target resistance for the pin-pair over the connected wires, wherein each connected wire is routed with other connected wires;
determining, by the processor, after initial routing, a resistance adjustment to be applied to adjust wire resistance of the connected wires, the resistance adjustment being based on a square routing in response to a wire resistance being below the target resistance, and the resistance adjustment being based on a multi-layer stacking in response to the wire resistance being above the target resistance; and
providing routing in patterns as generated by the initial routing and the resistance adjustment.