Patent ID: 11927544
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Measurement (Instruments)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A wafer defect tracing method, comprising:
obtaining defect data of a wafer;
obtaining position data of fail bits of the wafer;
determining a defect area of a storage block in the wafer according to the defect data;
determining a fail bit count of the storage block in the wafer according to the position data of the fail bits;
processing the defect area and the fail bit count of the storage block in the wafer to obtain a correlation coefficient; and
determining an abnormal reason for the fail bits of the wafer according to the correlation coefficient;
wherein processing the defect area and the fail bit count of the storage block in the wafer to obtain the correlation coefficient comprises:
determining a defect affected region of the wafer according to the defect data;
determining a defect area index of the storage block in the wafer according to a ratio of the defect area of the storage block in the wafer to an area of the defect affected region;
determining a fail bit index of the storage block in the wafer according to a ratio of the fail bit count of the storage block in the wafer to the area of the defect affected region; and
performing correlation analysis on the defect area index and the corresponding fail bit index of the storage block in the wafer to obtain the correlation coefficient.