Patent ID: 11901428
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 8:
9. A method, comprising:
receiving a workpiece having a frontside and a backside, the workpiece including:
a first plurality of semiconductor layers over a first base portion on a frontside surface of a substrate and a second plurality of semiconductor layers over a second base portion on the frontside surface of the substrate;
a first dielectric feature on a first side of the first plurality of the semiconductor layers and between the first plurality of the semiconductor layers and the second plurality of the semiconductor layers; and
a second dielectric feature on a second side of the first plurality of the semiconductor layers, the second side being opposite to the first side, and the second dielectric feature having a feature surface facing the frontside;

forming a gate structure engaging the first plurality of semiconductor layers and the second plurality of semiconductor layers and interfacing with the first dielectric feature on the feature surface;
replacing the first base portion and the second base portion to form a first backside dielectric and a second backside dielectric, respectively;
removing the first dielectric feature but not the second dielectric feature, thereby forming an opening between the first plurality of semiconductor layers and the second plurality of semiconductor layers;
recessing the gate structure from the opening to form a gate cut opening, the gate cut opening extending from a front surface of the gate structure to a back surface of the gate structure;
forming a third dielectric feature in the gate cut opening.