Patent ID: 11900039
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A method comprising:
fabricating first multi-stage logic with a first stage, a second stage and a third stage, wherein the first stage and the second stage are activated with first signals, wherein the third stage has a first input coupled to the first stage, a second input coupled to the second stage, and a first output that provides a first output signal based on the first signals; and
fabricating second multi-stage logic with a fourth stage, a fifth stage and a sixth stage, wherein the fourth stage and the fifth stage are activated with second signals and the first output signal, wherein the sixth stage has a third input coupled to the fourth stage, a fourth input coupled to the fifth stage, and a second output that provides a second output signal based on the second signals and the first output signal,
wherein the second output signal refers to an XOR logic output signal or an XNOR logic output signal.