Patent ID: 11973025
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A three-dimensional semiconductor memory device, comprising:
a peripheral circuit structure; and
a cell array structure on the peripheral circuit structure,
wherein the peripheral circuit structure includes
a first wiring level including a first lower wiring and a second lower wiring that are each on a substrate, the second lower wiring isolated from direct contact with, and adjacent to, the first lower wiring in a horizontal direction,
a first insulating layer in the first wiring level, the first insulating layer insulating the first lower wiring from the second lower wiring,
a stopping insulating layer on an upper surface of the first lower wiring, an upper surface of the second lower wiring, and an upper surface of the first insulating layer, the stopping insulating layer exposing the second lower wiring,
a first support via on the stopping insulating layer, such that a bottom surface of the first support via is on an upper surface of the stopping insulating layer and at least partially overlapping the first lower wiring in a vertical direction that is perpendicular to the horizontal direction, the first support via not contacting the first lower wiring,
a contact via on the second lower wiring and at least partially overlapping the second lower wiring in the vertical direction, the contact via contacting the second lower wiring through a via hole in the stopping insulating layer,
a via insulating layer insulating the contact via from the first support via,
a second wiring level on the contact via, the second wiring level including an upper wiring contacting the contact via, and
a second insulating layer surrounding the upper wiring in the second wiring level,
wherein the first support via includes a different material form the contact via.