Patent ID: 11881256
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 16:
17. A semiconductor memory device comprising:
a plurality of data pads connected to a memory controller;
a plurality of wordlines extending in a row direction and arranged in a column direction, the plurality of wordlines being grouped into a plurality of wordline groups such that each wordline group includes wordlines adjacent in the column direction, a selection wordline being selected based on a row address;
a plurality of memory cells connected to the plurality of wordlines, the plurality of memory cells forming a plurality of memory banks, a selection memory bank being selected based on a bank address;
a plurality of global input-output lines extending in the column direction and arranged in the row direction to transfer data between the plurality of data pads and the plurality of memory cells, the plurality of global input-output lines being cut into a plurality of line segment groups respectively corresponding to the plurality of wordline groups;
a plurality of intra-bank switches configured to control, based on the bank address and the row address, electrical connections between two line segment groups among the plurality of line segment groups, the two line segment groups being adjacent in the column direction and included in one memory bank; and
a plurality of inter-bank switches configured to control, based on the bank address, electrical connections between two line segments groups respectively included in two memory banks adjacent in the column direction among the plurality of memory banks,
wherein the intra-bank switches that are included in the selection memory bank corresponding to the bank address are turned on or turned off based on the row address, and the intra-bank switches that are not included in the selection memory bank corresponding to the bank address are turned on regardless of the row address.