Patent ID: 11955977
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 5:
6. A method of adjusting a data clock signal provided to a memory device, the method comprising:
receiving, from a controller, a first mode register write command at a memory device;
writing a first value to a mode register responsive to the first mode register write command;
initiating testing of a plurality of adjustments on a duty cycle of the data clock signal responsive to the first value;
receiving, from the controller, a second mode register write command; and
writing a second value to the mode register responsive to the second mode register write command;
selecting one of a plurality of lookahead duty codes stored in the mode register responsive to the second value;
receiving, from the controller, a third mode register write command; and
terminating the testing responsive to the third mode register write command.