Patent ID: 11948624
Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. A method of setting data nodes in a plurality of bit cell circuits in a column circuit in a memory array, the column circuit comprising:
a bit line;
a complement bit line;
a first voltage supply line;
a first voltage supply circuit coupled to the first voltage supply line and a first voltage rail; and
a second voltage supply line;
a second voltage supply circuit comprising a transistor comprising a first terminal coupled to the first voltage rail, a second terminal coupled to the second voltage supply line, and a gate coupled directly to the second voltage rail;
each of the plurality of bit cell circuits coupled to the first voltage supply line, the second voltage supply line, and a second voltage rail, and each of the plurality of bit cell circuits comprising:
a cross-coupled inverter circuit comprising:
a data node; and
a complement data node;

a first pass-gate coupled to the data node and the bit line; and
a second pass-gate coupled to the complement data node and the complement bit line;
a plurality of word lines each coupled to a gate of the first pass-gate and a gate of the second pass-gate of a corresponding one of the plurality of bit cell circuits, and
a column set input coupled to the first voltage supply circuit and configured to receive a column set signal,

the method comprising:
in response to the column set signal:
supplying the first supply voltage to each of the plurality of word lines;
providing the second supply voltage on the bit line;
providing the first supply voltage on the complement bit line; and
controlling the first voltage supply circuit to decouple the first voltage supply line from the first voltage rail.