Patent ID: 11930721
Assignee: 1372934 B.C. LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B  G | IPC B  G  H

Claim 0:
1. A method of fabricating a superconducting integrated circuit, the method comprising:
depositing a first dielectric layer;
depositing a negative photoresist mask over the first dielectric layer that traces out a negative pattern of a desired circuit pattern such that the desired circuit pattern corresponds to regions of the first dielectric layer that are not directly covered by the negative photoresist mask;
etching the desired circuit pattern into the first dielectric layer to produce open features in the first dielectric layer;
depositing a first superconducting metal layer over the first dielectric layer to at least partially fill the open features in the first dielectric layer;
planarizing the first superconducting metal layer;
depositing a second dielectric layer to produce a desired inner layer dielectric thickness, wherein the inner layer dielectric thickness is controlled by a deposition process; and
depositing a second superconducting metal layer above the second dielectric layer.