Patent ID: 11948941
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 7:
8. A method of manufacturing a semiconductor device, comprising:
forming a gate layer over a substrate, the gate layer being electrically coupled to the substrate;
depositing a first dielectric layer over the gate layer, wherein sidewalls of the gate layer is free of the first dielectric layer;
forming a channel material layer over the first dielectric layer with a first low dimensional material, the first dielectric layer being sandwiched between the channel material layer and the gate layer; and
forming source/drain terminals over the substrate and in contact with the channel material layer, the channel material layer being at least partially sandwiched between the source/drain terminals and over the gate layer, and the gate layer being sandwiched between the substrate and the source/drain terminals.