Patent ID: 11950517
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 15:
16. A three-dimensional semiconductor memory device, comprising:
a substrate;
first conductive lines on the substrate and extending in a first direction parallel to a top surface of the substrate;
second conductive lines extending in a second direction crossing the first direction;
cell stacks at respective intersections of the first conductive lines and the second conductive lines, an upper width of the first conductive lines being smaller than a lower width of the cell stacks, a lower width of the second conductive lines being larger than an upper width of the cell stacks;
a first gapfill insulating pattern filling a region between the cell stacks; and
a second gapfill insulating pattern filling a region between the second conductive lines,
a bottom surface of the second gapfill insulating pattern being located at a level lower than top surfaces of the cell stacks.