Patent ID: 11935613
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 4:
5. The device of claim 1, wherein the processor is configured to execute the instructions stored in the memory to, based on a determination that the first value of the RD cycle is not equal to the second value of the RD cycle, determine an unsuccessful set of parameters that, when used by the processor, causes the SPI not to read successfully from the DDR flash memory, the unsuccessful set of parameters comprising:
one of the first value of the RD cycle and the second value of the RD cycle;
an unsuccessful value of the transmit clock delay between the smallest successful value of the transmit clock delay and the largest successful value of the transmit clock delay; and
an unsuccessful value of the receive clock delay between the smallest successful value of the receive clock delay and the largest successful value of the receive clock delay.