Patent ID: 11887895
Assignee: UNITED SEMICONDUCTOR JAPAN CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. A field effect transistor (FET) formed in a doped well, the FET having a source, a drain, and a gate stack having a gate length, the FET comprising: a screening region positioned above the doped well, the screening region being doped with a first type of dopant, the screening region being electrically coupled to the doped well, the screening region being positioned below the gate stack;
a substantially undoped semiconductive layer formed above the screening region, the substantially undoped semiconductive layer being adjacent to the screening region;
a threshold voltage setting region in the substantially undoped semiconductive layer, the threshold voltage setting region being doped with the first type of dopant, the threshold voltage setting region dopant concentration modifying a threshold voltage of the FET;
wherein the gate stack is positioned above the doped well to control conduction between a drain and a source, the source and the drain being doped with a second type of dopant;
wherein at least a portion of the substantially undoped semiconductive layer is maintained as a substantially undoped channel region having a dopant concentration less than 1×1017 atoms/cm3, with the substantially undoped channel region laterally positioned between the source and the drain and vertically positioned between the gate stack and the threshold voltage setting region, and the threshold voltage setting region is vertically positioned between the substantially undoped channel region and the screening region;
wherein the screening region has a dopant concentration greater than ten times the dopant concentration of the substantially undoped channel region and sets a depth of a depletion layer below the gate stack in a direction from the substantially undoped channel region toward the screening region;
wherein the FET is operated on a first bias mode, a second bias mode or a third bias mode,
the first bias mode is a first condition as a first voltage between the doped well and the source being equal to zero volt and a second voltage between the drain and the source being equal to 0.4 volts, more than 0.4 volts and less than 0.7 volts, or equal to 0.7 volts,
the second bias mode is a second condition as the first voltage being equal to 0.1 volts, more than 0.1 volts and less than 0.55 volts, or equal to 0.55 volts and the second voltage being equal to 0.5 volts, more than 0.5 volts and less than 0.7 volts, or equal to 0.7 volts, and
the third bias mode is a third condition as the first voltage being equal to −1.0 volts, more than −1.0 volts and less than 0.1 volts, or equal to 0.1 volts and the second voltage being equal to 0.3 volts, more than 0.3 volts and less than 0.5 volts, or equal to 0.5 volts.