Patent ID: 11876090
Assignee: CYPRESS SEMICONDUCTOR CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. The sensor circuit of claim 12, wherein the control circuit is further for sensing instructions to the ESD protection circuit, the instructions for, when Vpin exceeds the positive trigger voltage:
pulling-up the voltage of the VHigher-Driver node to Vpin;
clamping the voltage on the VHigher-Driver node to a clamping voltage of the NFET clamp;
forward biasing source junctions of the plurality of PFETs to the first DN-well coupled to the VHigher-Driver node; and
forward biasing parasitic PNP transistors formed by the source junctions of the plurality of PFETs, the first DN-well and a substrate in which the circuit is formed,
whereby a MOSFET current through the plurality of PFETs and a parasitic current through the parasitic PNP transistors brings Vpin down to the clamped voltage on the VHigher-Driver node.