Patent ID: 11907753
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. A device comprising:
a processor core;
a level-two (L2) cache memory configured to store a set of cache entries;
an L2 cache controller coupled between the processor core and the L2 cache memory;
a configuration register configured to store a set of configuration values; and
a level-three (L3) cache memory coupled to the L2 cache controller that includes a set of memory regions, wherein:
the set of configuration values includes a respective configuration value for each memory region of the set of memory regions that indicates whether to store data associated with the respective memory region in the L2 cache memory;
the set of configuration values includes a first configuration value associated with a first memory region of the set of memory regions that is associated with the set of cache entries; and
the L2 cache controller is configured to:
receive a memory request associated with a set of data stored in the first memory region;
retrieve the set of data from the L3 cache memory;
provide the set of data to the processor core;
determine whether to store the set of data in the L2 cache memory based on the first configuration value;
determine a change in the first configuration value such that the first configuration value indicates not to store cache entries associated with the first memory region in the L2 cache memory; and
based on the change, evict the set of cache entries from the L2 cache memory.