Patent ID: 11923040
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus, comprising:
a memory configured to receive a plurality of multilevel command and address signals that represent a command structure including a command operand and memory addresses, the multilevel command and address signals having respective voltages corresponding to a non-binary value, wherein the memory includes:
a means for providing internal command signals representing the command operand based on the multilevel command and address signals, wherein the means for providing internal command signals comprises a latching means that provides bits of the command operand based on two of the multilevel command and address signals;
a means for providing internal address signals representing the memory addresses, the memory addresses including a plurality of bits represented by the internal address signals wherein the means for providing internal address signals comprises a decoding means that provides bits of the memory addresses based on two of the multilevel command and address signals; and
a means for performing memory operations based on the internal command signals on memory locations based on the internal address signals.