Patent ID: 11922108
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 7:
8. A method of forming a memory cell array, the method comprising:
generating, by a processor, a layout design of the memory cell array, wherein the generating of the layout design comprises:
placing a first set of memory cell layout patterns in a first column, the first set of memory cell layout patterns corresponding to fabricating a first set of memory cells, each layout pattern of the first set of memory cell layout patterns being separated from an adjacent layout pattern of the first set of memory cell layout patterns in a first direction;
placing a second set of memory cell layout patterns in a second column separated from the first column in a second direction different from the first direction, the second set of memory cell layout patterns corresponding to fabricating a second set of memory cells, each layout pattern of the second set of memory cell layout patterns being separated from an adjacent layout pattern of the second set of memory cell layout patterns in the first direction;
placing a first set of conductive feature layout patterns in the first column, the first set of conductive feature layout patterns extending in the first direction and overlapping the first set of memory cell layout patterns, the first set of conductive feature layout patterns corresponding to fabricating a first bit line extending in the first direction and being coupled to the first set of memory cells, wherein the placing the first set of conductive feature layout patterns comprises:
placing a first conductive feature layout pattern on a first layout level, the first conductive feature layout pattern extending in the first direction, and the first conductive feature layout pattern corresponding to fabricating a first portion of the first bit line coupled to the first set of memory cells; and
placing a second conductive feature layout pattern on a second layout level different from the first layout level, the second conductive feature layout pattern extending in the first direction, and the second conductive feature layout pattern corresponding to fabricating a second portion of the first bit line coupled to the first set of memory cells, the first portion of the first bit line and the second portion of the first bit line overlap a source of a transistor of a memory cell of the first set of memory cells;

placing a first set of via layout patterns between the first layout level and the second layout level, and the first set of via layout patterns corresponding to fabricating vias coupled between the first portion of the first bit line and the second portion of the first bit line, a pair of vias of the first set of vias being located above where the first portion of the first bit line overlaps each memory cell of the first column of memory cells; and
placing a second set of conductive feature layout patterns in the second column, the second set of conductive feature layout patterns extending in the first direction and overlapping the second set of memory cell layout patterns, the second set of conductive feature layout patterns corresponding to fabricating a second bit line extending in the first direction and being coupled to the second set of memory cells; and

manufacturing the memory cell array based on the layout design.