Patent ID: 11869622
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus, comprising:
a memory device, wherein the memory device comprises a plurality of memory arrays that include a first memory array and a second memory array stacked on the first memory array, one or more column positions are common to each memory array of the plurality of memory arrays;
a first organic substrate comprising a plurality of first conductive lines arranged with a first pitch, the plurality of first conductive lines configured to power one or more components of the memory device; and
a second organic substrate coupled with the memory device and the first organic substrate, the second organic substrate comprising a plurality of second conductive lines arranged with a second pitch smaller than the first pitch, wherein the plurality of second conductive lines routed through the second organic substrate are configured to couple the memory device with a host device.