Patent ID: 11862232
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 15:
16. A method for data transmission, comprising:
controlling mode register decoding modules to generate a mode register unselected enable signal, a mode register read enable signal, or a mode register write enable signal in response to mode register address information, a mode register read control signal, or a mode register write control signal;
controlling mode register read-write modules disposed corresponding to the mode register decoding modules to cache data on a data line in a write state in response to the mode register write enable signal, and output selected data and unselected data after setting the unselected data to zero in a read state in response to the mode register read enable signal and the mode register unselected enable signal; and
controlling a logic gate module to calculate an OR value of the data outputted by each mode register read-write module in the read state and to output a calculation result.