Patent ID: 11967353
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. A system, comprising:
a memory controller; and
a memory device in communication with the memory controller, wherein the memory device includes a first memory region and a second memory region, and
wherein:
the memory controller is configured to issue a refresh command to the memory device instructing the memory device to refresh both the first memory region and the second memory region,

in response to the refresh command, the memory device is configured to:
perform a first refresh operation on the first memory region at a first time; and
perform a second refresh operation on the second memory region at a second time after the first time, and

the memory device is further configured to perform an access operation on the first memory region, the second memory region, or both the first and second memory regions after beginning the first refresh operation and before completing the second refresh operation.