Patent ID: 11881254
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 2:
3. The enable control circuit according to claim 1, wherein the second control subcircuit comprises a first flip-flop and a first NOT gate circuit, wherein
the first flip-flop is a Data Flip-Flop (DFF), and a clock terminal (CK) of the first flip-flop is connected to an output terminal of the first control subcircuit, and is configured to receive the first intermediate signal; an input terminal (D) of the first flip-flop is connected to a ground terminal, and an output terminal (Q) of the first flip-flop is configured to output a second intermediate signal; and
the first NOT gate circuit is configured to: receive the second intermediate signal, and perform a NOT operation on the second intermediate signal to obtain the ODT enable signal.