Patent ID: 11961323
Assignee: JAPAN DISPLAY INC.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 8:
9. A display device comprising:
a plurality of display elements arranged in a matrix having a row-column configuration in a display area;
a plurality of scan lines each coupled to the display elements arranged in a first direction; and
a drive circuit configured to drive the scan lines, wherein
the drive circuit comprises:
a first transistor configured to apply a first potential to each of the scan lines, the first transistor being configured as a p-type thin-film transistor (TFT);
a second transistor that is coupled in series to the first transistor, and is configured to apply a second potential lower than the first potential to the scan line; and
a third transistor that is coupled in parallel to the second transistor, and is configured to apply the second potential to the scan line, the second and the third transistors being configured as n-type TFTs;

a shift register;
a negative AND (NAND) circuit configured to calculate a negative AND between an output of the shift register and an enable signal; and
a logical inversion circuit configured to logically invert the output of the shift register,
gates of the first and the second transistors are configured to receive an output of the NAND circuit, and
a gate of the third transistor is configured to receive an output of the logical inversion circuit.