Patent ID: 11862625
Assignee: NXP USA, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. An integrated circuit device comprising a signal node and an electrostatic discharge protection circuit block operably coupled in a standard cell to protect a functional circuit block against electrostatic discharge events at the signal node, where the electrostatic discharge protection circuit block has a set of layout properties comprising:
adjacent n-well and p-well regions extending across the standard cell;
a tap region comprising:
a n-well tie located in a central section of the n-well region for connecting the n-well to a first supply voltage, and
a p-well tie located in a central section of the p-well region for connecting the p-well to a second supply voltage; and

a dummy FinFET diode layout region positioned on at least a first side of the tap region, comprising:
a first p-FinFET formed in the n-well region and connected as a first diode between the first supply voltage and the signal node with the gate, source, and drain regions of the first p-FinFET shorted to the signal node, and
a second n-FinFET formed in the p-well region and connected as a second diode between the second supply voltage and the signal node with the gate, source, and drain regions of the second n-FinFET shorted to the signal node.