Patent ID: 11935580
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A device comprising:
an array of sense amplifiers arranged in columns with first sense amplifiers in first columns and second amplifiers in second columns;
an array of precharge blocks arranged in the columns with first precharge blocks coupled to the first sense amplifiers in the first columns and second precharge blocks coupled to the second sense amplifiers in the second columns;
a first delay block coupled to the first precharge blocks in the first columns, wherein the first delay block delays precharging of first bitlines with a first precharge burst in a mufti-burst precharge event; and
a second delay block coupled to the second precharge blocks in the second columns, wherein the second delay block delays precharging of second bitlines with a second precharge burst in the multi-burst precharge event,
wherein the second precharge burst sequentially follows the first precharge burst in the multi-burst precharge event such that the second precharge burst occurs after the first precharge burst, or
wherein the multi-burst event provides a similar amount of current as a single burst event, and wherein the first precharge burst has a similar amount of current as the second precharge burst.