Patent ID: 11916559
Assignee: SAMBANOVA SYSTEMS, INC.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. The DLL of claim 1, wherein the gater comprises:
an enable (EN) input;
a first flipflop with a D input coupled with the EN input, a clock input coupled with the gater clock input, and a Q output;
a second flipflop with a D input coupled with the Q output of the first flipflop, a clock input coupled with the gater clock input, and a Q output;
a third flipflop with a D input coupled with the Q output of the second flipflop, an inverting clock input coupled with the first gater input, and a Q output;
a fourth flipflop with a D input, an inverting clock input coupled with the second gater input, and a Q output;
a first logic gate with a first input coupled with the Q output of the third flipflop, a second input coupled with the first gater input, and an output coupled with the first gater output; and
a second logic gate with a first input coupled with the Q output of the fourth flipflop, a second input coupled with the second gater input, and an output coupled with the second gater output.