Patent ID: 11894086
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device, comprising:
a plurality of memory cells arranged in an array;
an input/output (I/O) interface, connected to the plurality of memory cells to output data signal from each memory cell; and
a control circuit, comprising:
a first clock generator configured to generate a first clock signal and a second clock signal according to an input clock signal and a chip enable (CE) signal, and provide the first clock signal to the plurality of memory cells; and
a second clock generator distinct from the first clock generator, and configured to generate a third clock signal according to the input clock signal and provide the first clock generator with a design for testability (DFT) enable (DFTEN) signal;

wherein the control circuit generates an output clock signal according to the second clock signal or the third clock signal.