Patent ID: 11921578
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 2:
3. The semiconductor device of claim 1, wherein the core circuit includes:
a memory region configured to output the internal data stored through the word line selected by the address signal to an input and output (input/output) line when a read signal is input to the memory region, perform the refresh operation based on a refresh address signal, output the internal data stored through the word line activated by the failure address signal when an internal read signal is input to the memory region, and then, store the error-corrected internal data when an internal write signal is input to the memory region; and
an address storage circuit configured to store the address signal as the failure address signal when the failure detection signal is input to the address storage circuit, and output the stored failure address signal when the internal read signal and the internal write signal are input to the address storage circuit.