Patent ID: 11901180
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method comprising:
patterning a resist, the resist overlying a first dielectric layer;
etching the first dielectric layer based on a pattern of the resist to form an opening in the first dielectric layer, the etching stopping on an etch stop layer underlying the first dielectric layer;
while the resist is over the first dielectric layer, extending the opening through the etch stop layer;
after extending the opening through the etch stop layer, etching a second dielectric layer to expose a first metal feature underlying the second dielectric layer, the etched second dielectric layer serving as a mask layer; and
forming a conductive element in the opening in the first dielectric layer, the conductive element electrically coupled to the first metal feature underlying the mask layer.