Patent ID: 11948939
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An integrated circuit, comprising:
a substrate;
an active device cell comprising:
an array of source/drain (S/D) regions of a first conductivity type disposed on or within the substrate; and
an array of gate structures with a first gate fill material disposed on the substrate; and

a dummy device cell comprising:
a first array of S/D regions of the first conductivity type disposed on or within the substrate;
a second array of S/D regions of a second conductivity type disposed on or within the substrate; and
an array of dual gate structures disposed on the substrate, wherein each of the dual gate structures comprises:
a first gate structure comprising a first gate dielectric layer and the first gate fill material; and
a second gate structure comprising a second gate dielectric layer and a second gate fill material that is different from the first gate fill material,
wherein a vertical sidewall of the first gate dielectric layer is in contact with a vertical sidewall of the second dielectric layer.