Patent ID: 11894267
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A method for fabricating an integrated circuit device, comprising:
forming an interconnect layer over a substrate, wherein the interconnect layer has an interlayer dielectric layer and a conductive pad in the interlayer dielectric layer;
forming a memory structure over and in contact with the conductive pad, wherein the memory structure comprises at least a resistance switching element over the conductive pad and a top electrode over the resistance switching element; and
forming a first conductive line over and in direct contact with the top electrode, wherein a bottom surface of the first conductive line is in direct contact with a top surface of the top electrode and extends beyond an entire width of the top electrode along a lengthwise direction of the first conductive line from a top view, and the top electrode extends beyond opposite sidewalls of the first conductive line along a direction perpendicular to the lengthwise direction of the first conductive line from the top view.