Patent ID: 11907579
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 12:
13. A method of configuring a memory system that comprises a non-volatile memory including a memory cell array having a plurality of blocks, each block having a plurality of pages including a first page and a second page, each of the pages including a plurality of storage elements, said method comprising:
setting a first value in a control information storage unit for the first page having a pre-determined write operation speed that is slower than a first speed; and
setting a second value in the control information storage unit for the second page having a pre-determined write operation speed that is equal to or higher than the first speed, wherein
during a write operation, one of at least a first operation method and a second operation method is selected for writing to a page in accordance with a value set in the control information storage unit for the page and the write operation is performed using the selected operation method, wherein n-bit (n is a natural number) data is stored per storage element when the first operation method is used and m-bit (m is a natural number satisfying m>n) data is stored per storage element when the second operation method is used, wherein
the first page having the first value set in the control information storage unit is written to using the first operation method, and the second page having the second value set in the control information storage unit is written to using the second operation method, and
wherein the pre-determined write operation speed for each of the first and second pages is determined during a test of measuring a performance index of the memory system executed near the time of a shipment of the memory system or at the time of designing the memory system, and
a difference between a write operation speed during execution of the write operation in the first page using the first operation method and a write operation speed during execution of the write operation in the second page using the second operation method is smaller than a difference between the pre-determined write operation speed of the first page and the pre-determined write operation speed of the second page.