Patent ID: 11862108
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A shift register unit, comprising an output end, a node control end, a first output node control circuit, a second node control circuit, a second output node control circuit and an output circuit, wherein
the second node control circuit is electrically connected to a first clock signal line, the node control end, the first output node and the second node, is configured to control providing a node control signal provided by the node control end to the second node under a control of a first clock signal provided by the first clock signal line, and is further configured to control a potential of the second node according to a potential of the first output node and the first clock signal;
the first output node control circuit is electrically connected to the second node and the first output node and is configured to control a potential of the first output node;
the second output node control circuit is electrically connected to the second node and the second output node and is configured to control a potential of the second output node;
the output circuit is electrically connected to a first output node, a second output node, a first voltage line, a second voltage line and an output end, and is configured to control a light-emitting control signal output by the output end according to a first voltage signal provided by the first voltage line and a second voltage signal provided by the second voltage line under a control of the potential of the first output node and the potential of the second output node;
wherein the shift register unit further comprises an input end; the first output node control circuit is further electrically connected to the input end, the first output node, a first clock signal line, a second clock signal line, and a first voltage line, and is configured to, under the control of the first clock signal, write an input signal provided by the input end into the first output node, and control the potential of the first output node according to a potential of the second node, the second clock signal, and the first voltage signal;
the second clock signal line is configured to provide the second clock signal, and the first voltage line is configured to provide the first voltage signal;
the second node control circuit comprises a first transistor; a gate of the first transistor is electrically connected to a conductive connecting part, and the conductive connecting part is connected to the first clock signal line through a corresponding via hole, so that the gate of the first transistor is electrically connected to the first clock signal line;
the first output node control circuit comprises a third transistor, a gate of the third transistor is electrically connected to the conductive connecting part;
the gate of the first transistor, the conductive connecting part and the gate of the third transistor are integrally constructed.