Patent ID: 11922049
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A method comprising:
performing, by a processing device, a calibration process to determine a first voltage shift at a first plane of a memory device and a second voltage shift at a second plane of the memory device at a first time period, wherein the first voltage shift is between a first voltage distribution observed at the first plane during the first time period and a second voltage distribution observed at the second plane during a second time period, and wherein the second voltage shift is between a third voltage distribution observed at the second plane during the first time period and a fourth voltage distribution observed at the second plane during a third time period;
receiving, by the processing device, a request to perform a multi-plane operation with respect to first data residing on the first plane of the memory device and second data residing on the second plane of the memory device;
responsive to the request, identifying a first set of registers allocated to store a first set of trim values associated with the first plane and a second set of registers allocated to store a second set of trim values associated with the second plane;
retrieving, by the processing device, the first set of trim values loaded to the first set of registers of the memory device based on the calibration process, wherein the first set of trim values corresponds to the first voltage shift determined based on the calibration process;
retrieving, by the processing device, the second set of trim values loaded to the second set of registers based on the calibration process, wherein the second set of trim values corresponds to the second voltage shift determined based on the calibration process; and
performing, by the processing device, the multi-plane operation using the first set of trim values for the first data at the first plane and the second set of trim values for the second data at the second plane.