Patent ID: 11863303
Assignee: HUAWEI TECHNOLOGIES CO., LTD.
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A link bit error-based processing apparatus, comprising:
a non-transitory memory storing instructions; and
a processor coupled to the non-transitory memory, the processor configured to execute the instructions to cause the apparatus to be configured to:
detect a first bit error rate at which data traffic is sent through a first egress port of a first network device, wherein the first network device is configured to send the data traffic to a next-hop network device of the first network device along a first transmission path through the first egress port, and
send first link status information to a controller, wherein the first link status information comprises first egress port information and the first bit error rate, and the first egress port information indicates the first egress port, wherein
the first link status information is used to determine a first accumulated bit error rate of the first transmission path, the first accumulated bit error rate is a weighted sum of bit error rates of all egress ports configured to send data traffic on the first transmission path, the first accumulated bit error rate is used to determine whether the first accumulated bit error rate is greater than a first bit error rate threshold to switch a service flow from the first transmission path to a second transmission path, a head node network device of the first transmission path and a head node network device of the second transmission path are a same network device, and a tail node network device of the first transmission path and a tail node network device of the second transmission path are a same network device, and
wherein the first bit error rate threshold is a bit error rate threshold that is set corresponding to a service type of the service flow, while maintaining a service path for flows that exceed the first bit error rate threshold.