Patent ID: 11948857
Assignee: NANYA TECHNOLOGY CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method for fabricating a semiconductor device, comprising:
providing a substrate;
forming a first pad above the substrate;
forming a first redistribution conductive layer on the first pad; and
forming a first redistribution thermal release layer on the first redistribution conductive layer;
wherein the first redistribution conductive layer and the first redistribution thermal release layer together form a first redistribution structure and the first redistribution thermal release layer is configured to sustain a thermal resistance between about 0.04° C. cm2/Watt and about 0.25° C. cm2/Watt;
wherein the first redistribution thermal release layer comprises an organic material interstitially mingled with carbon nanotubes;
wherein the first redistribution conductive layer is formed of tungsten, titanium, tin, nickel, copper, gold, aluminum, platinum, cobalt, or a combination thereof;
wherein forming the first pad comprises:
forming a bottom passivation layer above the substrate;
forming a pad opening along the bottom passivation layer; and
forming the first pad in the pad opening.