Patent ID: 11923380
Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A manufacturing method of a display panel, comprising following steps:
providing a base substrate;
stacking a first active layer, a first gate insulating layer, a first gate layer, and a second gate insulating layer in sequence on the base substrate;
etching the second gate insulating layer to form a first through hole and a second through hole, wherein the first through hole passes through the second gate insulating layer and the first gate insulating layer and exposes a portion of a side of the first active layer, and the second through hole passes through the second gate insulating layer and the first gate insulating layer and exposes a portion of another side of the first active layer;
forming a patterned metal layer on the second gate insulating layer, wherein the metal layer comprises a first metal portion and a second metal portion, the first metal portion is electrically connected to the portion of the side of the first active layer through the first through hole, and the second metal portion is electrically connected to the portion of another side of the first active layer through the second through hole;
forming a first interlayer dielectric layer on the metal layer;
disposing a second active layer on the first interlayer dielectric layer, wherein projections of the second active layer and the first active layer projected on the base substrate do not overlap;
disposing a third gate insulating layer on the first interlayer dielectric layer and the second active layer;
disposing a second gate layer on the third gate insulating layer;
etching the first interlayer dielectric layer to form a third through hole and a fourth through hole, wherein the third through hole passes through the first interlayer dielectric layer and exposes the first metal portion, and the fourth through hole passes through the first interlayer dielectric layer and exposes the second metal portion; and
forming a first source and a first drain on the first interlayer dielectric layer, wherein the first source extends into the third through hole and is electrically connected to the first metal portion, and the first drain extends into the fourth through hole and is electrically connected to the second metal portion.