Patent ID: 11875835
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory, comprising:
a storage unit, comprising a storage element;
a source line, electrically connected to a first end of the storage element;
a bit line; and
a write bit line; wherein
the storage unit further comprises:
a first selective transistor, configured to electrically connect a second end of the storage element with the bit line in response to a first control signal;
a second selective transistor, configured to electrically connect a first end of the source line with the write bit line in response to a second control signal; and
a third selective transistor, configured to transmit a high level or a low level to a second end of the source line in response to a third control signal;
when a write operation is performed on the memory, the first selective transistor, the second selective transistor and the third selective transistor are all turned on;
when a read operation is performed on the memory, the first selective transistor and the third selective transistor are both turned on, and the second selective transistor is turned off;
the memory is configured to change a storage state of the storage element by a first current and a second current that exist simultaneously during the write operation being performed, the first current flowing through the storage element and the second current flowing through the source line without flowing through the storage element; and
the memory is further configured to read data stored within the storage element through a third current flowing from the bit line to the second end of the source line through the storage element.