Patent ID: 11960408
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. The semiconductor memory device of claim 6, wherein:
each of the first to fourth upper sub-selection blocks includes first to third upper unit selection blocks arranged in the column direction,
each of the first to fourth lower sub-selection blocks includes first to third unit selection blocks arranged in the column direction,
each of the first to third upper latch blocks is electrically connected to the upper first to third unit selection blocks of the first sub-selection block, respectively,
each of the fourth to sixth upper latch blocks is electrically connected to the upper first to third upper unit selection blocks of the second upper sub-selection block, respectively,
each of the seventh to ninth upper latch blocks is electrically connected to the first to third upper unit selection blocks of the upper third sub-selection block, respectively,
each of the tenth to twelfth upper latch blocks is electrically connected to the first to third upper unit selection blocks of the fourth upper sub-selection block, respectively,
each of the first to third lower latch blocks is electrically connected to the first to third lower unit selection blocks of the first lower sub-selection block, respectively,
each of the fourth to sixth lower latch blocks is electrically connected to the first to third lower unit selection blocks of the second lower sub-selection block, respectively,
each of the seventh to ninth lower latch blocks is electrically connected to the first to third lower unit selection blocks of the third lower sub-selection block, respectively, and
each of the tenth to twelfth lower latch blocks is electrically connected to the first to third lower unit selection blocks of the fourth lower sub-selection block, respectively.