Patent ID: 11880265
Assignee: NVIDIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 4:
5. A receiver device comprising:
detection logic to receive a first set of data frames, and detect one or more frame errors in the first set of data frames;
an error counter to store a count of the one or more frame errors detected in the first set of data frames; and
interrupt logic coupled to the error counter, the interrupt logic to specify a programmable period, the interrupt logic to decrement the count by a specified value at an end of each programmable period, and the interrupt logic to compare the count at the error counter with a threshold number of frame errors, and output an interrupt responsive to the count satisfying the threshold number of frame errors, wherein interrupt logic specifies the programmable period corresponding to a first clock having a first frequency, and wherein the receiver device is to receive the first set of data frames using a second clock having a second frequency greater than the first frequency.