Patent ID: 11862238
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus comprising:
a first deck including first memory cell strings;
a second deck located over the first deck, the second deck including second memory cell strings;
first data lines located between the first and second decks and coupled to the first memory cell strings;
second data lines located over the second deck and coupled to the second memory cell strings, the second data lines electrically separated from the first data lines;
first access lines, and second access lines separated from the first access lines;
a first memory cell block coupled to the first access lines and including a first portion located in the first deck and a second portion located in the second deck, the first portion of the first memory cell block including a first portion of the first memory cell strings, the second portion of the first memory cell block including a first portion of the second memory cell strings;
a second memory cell block coupled to the second access lines and including a first portion located in the first deck and a second portion located in the second deck, the first portion of the second memory cell block including a second portion of the first memory cell strings, the second portion of the second memory cell block including a second of the second memory cell strings;
the first portion of the first memory cell block sharing the first data lines with the first portion the second memory cell block;
the second portion of the first memory cell block sharing the second data lines with the second portion the second memory cell block;
first buffer circuitry located under the first memory cell strings of the first deck and coupled to the first data lines; and
second buffer circuitry located under the first memory cell strings of the first deck and coupled to the second data lines.