Patent ID: 11947834
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. A memory sub-system, comprising:
an interconnect connectable to a local host system having a microprocessor configured to function as a central processing unit for the memory sub-system;
a network interface connected to the interconnect and configured to receive storage access request from a remote host system in a first storage protocol;
a solid-state drive connected to the interconnect and operable according to a second storage protocol to provide storage services;
a processing device configured to generate, based on the storage access requests from the remote host system, first control messages and first data messages according to the second storage protocol; and
a random-access memory connected to the interconnect;
wherein the processing device is configured to:
buffer, in the random-access memory, the first control messages, wherein the microprocessor is configured via instructions to fetch the first control messages from the random-access memory, process the first control messages, and generate second control messages; and
send, via the interconnect, the first data messages to the solid-state drive using a peer to peer protocol without the first data messages being buffered in the random-access memory; and

wherein the solid-state drive is configured to process, the second control messages and the first data messages to provide network storage services to the remote host system.