Patent ID: 11862622
Assignee: WINBOND ELECTRONICS CORP.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC H

Claim 7:
8. The integrated circuit layout according to claim 1, wherein:
the second gate line width equals to a sum of the first gate line width and a variable;
the first gate lines comprise a first gate line space between edges of the first gate lines, the second gate lines comprise a second gate line space between the edges of the second gate lines, wherein the second gate line space is smaller than the first gate line space by the variable; and
an edge of the dummy gate lines and an edge of the first gate lines adjacent to the edge of the dummy gate lines comprise a first dummy gate line space, another edge of the dummy gate lines and an edge of the second gate lines adjacent to the another edge of the dummy gate lines comprise a second dummy gate line space, wherein the second dummy gate line space is smaller than the first dummy gate line space by 0.5 of the variable.