Patent ID: 11929762
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A low density parity check (LDPC) decoder, comprising:
a data buffer buffering data encoded with an irregular LDPC code and providing a value of the data to variable nodes;
a check node updater updating check nodes connected to the variable nodes;
a variable node updater updating the variable nodes connected to the updated check nodes; and
a syndrome checker outputting the values of the variable nodes as decoded data according to a syndrome check result of the updated variable nodes,
wherein the variable node updater includes one or more unit logic circuit groups, and controls each of the unit logic circuit groups to update one variable node in one cycle or each of the unit logic circuits included in each of the unit logic circuit group to update different variable nodes in parallel in one cycle according to an amount of computation required for each of the variable nodes.