Patent ID: 11934833
Assignee: TEXAS INSTRUMENTS INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 15:
16. A device comprising:
a processor core configured to provide a stream read instruction;
a cache memory configured to store a data stream that includes a first data element and a second data element is immediately subsequent to the first data element; and
a stream data unit coupled between the processor core and the cache memory, wherein the stream data unit includes:
a memory interface coupled to the cache memory and configured to retrieve the first data element and the second data element;
a first stream head register configured to store the first data element; and
a second stream head register configured to store the second data element concurrent with the first stream head register storing the first data element, wherein the stream read instruction specifies whether to:
provide the first data element from first stream head register to the processor core without providing the second data element from the second stream head register;
provide the second data element from second stream head register to the processor core without providing the first data element from the first stream head register; or
provide both the first data element and the second data element to the processor core.