Patent ID: 11966752
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 22:
23. A method, comprising:
storing, in a linked mapping, a sequence of logical addresses of a memory system that are accessed as part of a first boot-up procedure and a compressed mapping of logical addresses in a dedicated portion of the linked mapping, wherein the compressed mapping of logical addresses comprises information associated with two or more logical addresses that are indexed sequentially in the sequence of logical addresses;
incrementing, in the linked mapping and as part of the first boot-up procedure, a first counter associated with a first logical address of the sequence of logical addresses and a second counter associated with a second logical address of the sequence of logical addresses;
transferring, as part of a second boot-up procedure occurring after the first boot-up procedure, first information stored at the first logical address and second information stored at the second logical address from a non-volatile memory device to a volatile memory device based at least in part on the linked mapping;
receiving a command to access the first logical address as part of the second boot-up procedure; and
incrementing the first counter in the linked mapping based at least in part on receiving the command to access the first logical address.