Patent ID: 11934251
Assignee: ADVANCED MICRO DEVICES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. A memory controller, comprising:
a memory channel controller having a first interface circuit adapted to couple to data fabric operating in a first clock domain, and a second interface circuit adapted to couple to a physical layer interface circuit (PHY) operating in a third clock domain, wherein the memory channel controller operates in a second clock domain according to a set of timing parameters, wherein the first interface circuit includes a clock interface circuit for adapting transfers between the first clock domain and the second clock domain; and
a power controller coupled to the memory channel controller and responsive to a power state change request to send commands to the second interface circuit to change parameters of a memory system, the memory system comprising a memory channel and a memory, and to update the set of timing parameters of the memory channel controller according to a selected power state of a plurality of power states,
wherein the power controller is further responsive to a request to synchronize the first interface circuit with a new frequency of only a first clock signal of the first clock domain to change the set of timing parameters of the clock interface circuit without changing the set of timing parameters of the memory system or the selected power state.