Patent ID: 11960722
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. A memory device comprising:
an array of memory cells; and
a controller configured to access the array of memory cells,
wherein the controller is further configured to:
program a first number of bits to a first memory cell of the array of memory cells;
program a second number of bits to a second memory cell of the array of memory cells, the second number of bits being greater than or equal to the first number of bits;
following a period after programming the second number of bits to the second memory cell, merge at least a subset of the first number of bits stored in the first memory cell to the second number of bits stored in the second memory cell without erasing the second memory cell such that the second number of bits plus at least the subset of the first number of bits are stored in the second memory cell; and
prior to merging at least the subset of the first number of bits stored in the first memory cell to the second number of bits stored in the second memory cell, perform a touch up programming operation on the second memory cell to increase a threshold voltage of the second memory cell towards a respective desired threshold voltage of the second memory cell, and

an error correction code (ECC) engine configured to monitor the second memory cell and instruct the controller to perform the touch up programming operation on the second memory cell in response to the threshold voltage of the second memory cell having a reduced threshold voltage less than respective desired threshold voltage.