Patent ID: 11973123
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor structure, comprising:
an active region including a source region, a drain region, and a channel region extending between the source region and the drain region;
a gate stack;
a gate dielectric layer located between the gate stack and the active region; and
a dielectric matrix layer embedding the active region, wherein a top surface of the active region is located within a same horizontal plane as a top surface of the dielectric matrix layer,
wherein the gate stack comprises an electrically conductive gate electrode and a single crystalline III-nitride ferroelectric plate located between the electrically conductive gate electrode and the gate dielectric layer, and wherein an entirety of the single crystalline III-nitride ferroelectric plate is single crystalline, and wherein a top surface of the gate dielectric layer is in direct contact with the single crystalline III-nitride ferroelectric plate and a bottom surface of the gate dielectric layer is in direct contact with the top surface of the active layer and the top surface of the dielectric matrix layer.