Patent ID: 11954037
Assignee: NVIDIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A computing system comprising:
a volatile memory;
a cache coupled with the volatile memory; and
a processing device coupled with the cache, the processing device coupled with at least one of a storage device or a network port and is to:
generate a plurality of virtual addresses that are sequentially numbered for data that is to be at least one of processed or transferred in response to an input/output (I/O) request;
allocate, for the data, a continuous range of physical addresses of the volatile memory, wherein the continuous range of physical addresses is limited to a size of the cache;
generate a set of hash-based values based on mappings between the plurality of virtual addresses and respective physical addresses of the continuous range of physical addresses;
identify a unique cache line of the cache that corresponds to each respective hashed-based value of the set of hash-based values; and
cause the data to be directly stored in the unique cache lines of the cache.