Patent ID: 11937515
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 0:
1. A method, comprising:
forming a plurality of magneto-resistive random-access memory (MRAM) cells in a dielectric layer, top surfaces of top electrodes of the plurality of MRAM cells being coplanar with a top surface of the dielectric layer;
depositing a first etch stop layer (ESL) over the dielectric layer and the plurality of MRAM cells;
depositing a second ESL over the first ESL;
forming a common electrode opening in the first ESL and the second ESL to expose each of the top electrodes of the plurality of MRAM cells; and
forming a common electrode in the common electrode opening such that the top surfaces of the common electrode and the second ESL are coplanar,
wherein the common electrode is disposed directly on and in electrical communication with each of the top electrodes of the plurality of MRAM cells.