Patent ID: 11894043
Assignee: INTEGRATED SILICON SOLUTION INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. The management method of the power management circuit in the low-power double data rate memory of claim 15, wherein the another low dropout regulator comprises:
a second transistor electrically connected between the third transmitting terminal and the fourth transmitting terminal;
a third transistor electrically connected between the fourth transmitting terminal and the fifth transmitting terminal and controlled by the control signal;
a second comparator electrically connected to the third transmitting terminal, the fourth transmitting terminal and the second transistor, wherein the second comparator is configured to compare the another reference voltage and the first voltage to generate a second comparison signal, and the second comparison signal is electrically connected to the second transistor to adjust the second voltage difference between the third voltage and the first voltage; and
a fourth transistor electrically connected to the second comparator and controlled by the control signal;
wherein each of the second transistor and the third transistor is a PMOS transistor, and the fourth transistor is an NMOS transistor.