Patent ID: 11915116
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An arithmetic apparatus for a neural network comprising:
a plurality of digital-time conversion circuits connected in series, each of the digital-time conversion circuits being configured to
delay a first input time signal by a variable amount,
delay a second input time signal by a fixed amount, and
output the delayed first and second input time signals respectively as either first and second output time signals or second and first output time signals, in accordance with input data; and
a time-digital conversion circuit connected to a last digital-time conversion circuit in the series, and configured to
generate a digital output signal based on first and second output time signals from the last digital-time conversion circuit, wherein
the time-digital conversion circuit outputs, as the digital output signal, the first output time signal from the last digital-time conversion circuit at a timing of transition of a value of the second output time signal from the last digital-time conversion circuit.