Patent ID: 11972827
Assignee: WINBOND ELECTRONICS CORP.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. The semiconductor storage device according to claim 5, wherein,
when a page comprises n sectors, the ECC chip performs the error detection and correction of the data on a sector-by-sector basis, a time for reading the memory array is set as tARRAY, a time for the NAND chip to transmit the data of one sector to the ECC chip is set as tDOUT1, a time for the ECC chip to output the data of the one sector to the outside is set as tDOUT2, and there are limitation specified by the following equation:

tARRAY+tDOUT1×(n×¾)<tDOUT2×n.