Patent ID: 11954488
Assignee: REBELLIONS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A processing device comprising processing circuitry comprising:
at least one processor comprising at least one processing element; and
a shared memory shared by the at least one processor,
wherein the at least one processing element is configured to cause:
receiving a format conversion signal indicating a format of floating-point numbers between a first format and a second format,
receiving a first set of bits representing a first floating-point number, a second set of bits representing a second floating-point number, and a third set of bits representing a third floating-point number,
converting the first set of bits to a first sign bit, a first set of exponent bits and a first set of mantissa bits based on the format conversion signal,
converting the second set of bits to a second sign bit, a second set of exponent bits and a second set of mantissa bits based on the format conversion signal,
converting the third set of bits to a third sign bit, a third set of exponent bits and a third set of mantissa bits based on the format conversion signal,
performing a computation operation on the first sign, the first set of exponent bits, the first set of mantissa bits, the second sign bit, the second set of exponent bits, the second set of mantissa bits, the third sign bit, the third set of exponent bits, and the third set of mantissa bits, and
outputting a fourth set of bits representing an output floating-point number via the computation operation based on the format conversion signal,
wherein the at least one processing element is further configured to cause:
storing bits associated with the first set of exponent bits in a first register,
storing bits associated with the second set of exponent bits in a second register,
storing bits associated with the third set of exponent bits in a third register,
adding the bits in the first register, the bits in the second register, and the bits in the third register to generate alignment information, and
outputting the fourth set of bits based on the alignment information, and
wherein the alignment information is generated by using a carry save adder circuitry having a bit width equal to a positive margin number added by a maximum number of the number of exponent bits in the first format and the number of exponent bits in the second format and by using a carry-propagate adder adding a sum and a carry outputted from the carry save adder.