Patent ID: 11869426
Assignee: HEFEI BOE JOINT TECHNOLOGY CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. The shift register circuit according to claim 1, further comprising:
a fifth noise reduction sub-circuit coupled to a second pull-down node, the first signal output terminal and a first voltage terminal, the fifth noise reduction sub-circuit being configured to transmit a voltage of the first voltage terminal to the first signal output terminal under control of a voltage of the second pull-down node;
a sixth noise reduction sub-circuit coupled to the second pull-down node, the second signal output terminal and the first voltage terminal, the sixth noise reduction sub-circuit being configured to transmit the voltage of the first voltage terminal to the second signal output terminal under the control of the voltage of the second pull-down node;
a shift signal output sub-circuit coupled to a fourth clock signal terminal, the pull-up node and a shift signal output terminal, the shift signal output sub-circuit being configured to transmit a fourth clock signal received at the fourth clock signal terminal to the shift signal output terminal under the control of the voltage of the pull-up node; and
an eighth noise reduction sub-circuit coupled to the second pull-down node, the shift signal output terminal and a second voltage terminal, the eighth noise reduction sub-circuit being configured to transmit a voltage of the second voltage terminal to the shift signal output terminal under the control of the voltage of the second pull-down node; wherein
the pixel driving circuit includes a sensing sub-circuit coupled to a third scanning signal terminal, the second node and a sensing signal terminal, and configured to transmit a sensing signal received at the sensing signal terminal to the second node under control of a third scanning signal received at the third scanning signal terminal; and the shift register circuit further comprises:
a third output sub-circuit coupled to a third clock signal terminal, the pull-up node and a third signal output terminal, the third output sub-circuit being configured to transmit a third clock signal received at the third clock signal terminal to the third signal output terminal under the control of the voltage of the pull-up node, so as to transmit the third scanning signal to the third scanning signal terminal of the pixel driving circuit; and
a seventh noise reduction sub-circuit coupled to the second pull-down node, the third signal output terminal and the first voltage terminal, the seventh noise reduction sub-circuit being configured to transmit the voltage of the first voltage terminal to the third signal output terminal under the control of the voltage of the second pull-down node.