Patent ID: 11869563
Assignee: GLOBALFOUNDRIES DRESDEN MODULE ONE LIMITED LIABILITY COMPANY & KG
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. A memory structure comprising:
a comparator configured to receive a data output signal and a data input signal,
wherein the data input signal represents a multi-bit data value to be stored in a bitcell and the data output signal represents a currently stored multi-bit data value in the bitcell, and
wherein the comparator is further configured to perform a comparison of a data output signal and a data input signal and to output a data verification signal based on the comparison; and

a voltage driver configured to receive the data input signal and the data verification signal and to apply one specific voltage of multiple different voltages to at least one of a source-line and a bit-line depending upon the data verification signal and the data input signal,
wherein the multiple different voltages comprise: a programming inhibit voltage; and at least two variable programming assist voltages that are lower than the programming inhibit voltage.