Patent ID: 11916568
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A sampling circuit configured for digitizing an input signal, wherein said sampling circuit comprises:
a time-based analog-to-digital converter; and
a hierarchical time step generator comprising multiple levels, wherein said hierarchical time step generator is configured to generate multiphase clock signals in response to receiving a reference clock signal, wherein said time-based analog-to-digital converter is configured to be controlled to digitize said input signal by said multiphase clock signals from said hierarchical time step generator;, wherein said hierarchical time step generator comprises:
a first level comprising a time step generator configured to generate first level clock signals in response to receiving said reference clock signal;
a second level comprising a phase interpolator circuit configured to generate multiple second level clock signals between each of said multiple first level clock signals; and
a third level comprising a device sampling phase generator configured to generate said multiphase clock signals using a set of time staggered multi-phase phase locked loops synchronized to each of said second level clock signals.