Patent ID: 11961810
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  Y | IPC H

Claim 0:
1. A device comprising:
a trace extending along a substrate by a first length, the trace having a first end mounted to the substrate and having a second end distal to the first end, the first end having a first width, the second end having a second width, the first length greater than the first width and the second width; and
a chip comprising:
an integrated circuit;
an insulating layer on the integrated circuit;
a contact pad in the insulating layer;
a passivation layer on the contact pad and the insulating layer;
a polyimide layer on the passivation layer and in physical contact with the contact pad;
an under bump metallurgy extending through the polyimide layer and the passivation layer, the under bump metallurgy coupled to the contact pad;
a bump having a third end mounted to the under bump metallurgy and having a fourth end distal to the third end, the third end having a third width, the fourth end having a fourth width, the fourth width less than the third width, wherein the second end of the trace is directly bonded to the fourth end of the bump, the second end of the trace and the fourth end of the bump being free of solder and of intermetallic compounds; and
an oxide layer disposed on an entirety of a first sidewall of the bump, the first sidewall extending from the third end to the fourth end.