Patent ID: 11968823
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 4:
5. The semiconductor device of claim 1, further comprising:
a second direct contact passing through the first insulation layer and the second insulation layer of the insulation layer, and connected to the active pattern of the peripheral region of the substrate;
a third direct contact passing through the bit line capping layer of the bit line structure, and connected to the bit line pattern of the bit line structure; and
a fourth direct contact passing through the peripheral gate capping layer of the peripheral gate structure, and connected to the peripheral gate pattern of the peripheral gate structure,
wherein a vertical length of the first direct contact is greater than a vertical length of each of the second to fourth direct contacts in a third direction that is perpendicular to the top surface of the substrate.