Patent ID: 11950415
Assignee: MICRON TECHNOLOGY, INC.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 11:
12. An integrated assembly, comprising:
a first memory region, a second memory region offset from the first memory region, and an intermediate region between the first and second memory regions;
first channel-material-pillars arranged within the first memory region;
second channel-material-pillars arranged within the second memory region;
conductive posts arranged within the intermediate region;
a panel extending across the first memory region, the intermediate region and the second memory region; the panel being laterally between a first memory-block-region and a second memory-block-region;
doped-semiconductor-material within the first memory region, the second memory region and the intermediate region, and being directly adjacent to the panel; the doped-semiconductor-material being at least part of conductive source structures within the first and second memory regions; and
insulative rings laterally surrounding the conductive posts and being between the conductive posts and the doped-semiconductor-material; the doped-semiconductor-material directly contacting outer edges of the insulative rings, and the conductive posts directly contacting inner edges of the insulative rings.