Patent ID: 11922993
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. A device comprising:
an array of memory cells comprising a first word line coupled to at least a subset of the array of memory cells; and
control logic coupled to the first word line, the control logic to perform operations comprising:
detecting, within a queue, a first read command to read first data from a first page of the subset of the array and a second read command to read second data from a second page of the subset of the array;
causing a voltage applied to the first word line to move to a target value;
causing a page buffer to sense the first data from a first bit line coupled to the first page and to sense the second data from a second bit line coupled to the second page; and
causing the first word line to be discharged.