Patent ID: 11901115
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of forming a substrate assembly, comprising:
forming one or more traces on a dummy copper region that is coupled to a dummy core;
forming a first portion of a magnetic feature on the dummy copper region, wherein a portion of the one or more traces is encircled between the first portion of the magnetic feature and the dummy copper region;
forming a first dielectric region on the dummy copper region, wherein the first portion of the magnetic feature is encapsulated between the first dielectric region and the dummy copper region;
removing the dummy copper region and the dummy core;
forming a second portion of the magnetic feature on an opposite side of the one or more traces from which the first portion of the magnetic feature is located, wherein the portion of the one or more traces is encircled between the first portion of the magnetic feature and the second portion of the magnetic feature; and
forming a second dielectric region on the second portion of the magnetic feature, wherein the magnetic feature is encapsulated between the first dielectric region and the second dielectric region.