Patent ID: 11968039
Assignee: HUAWEI TECHNOLOGIES CO., LTD.
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. A processor for executing Forward Error Correction (FEC) coding, the processor being configured to:
acquire a stream of real data symbols from a communication medium,
the stream of real data symbols being arranged in a real matrix such that a given real data symbol is associated with a respective real row position and a respective real column position in the real matrix;

generate virtual data symbols being arranged in a virtual matrix such that a given virtual data symbol is associated with a respective first virtual row position and a respective first virtual column position in the virtual matrix,
to generate including applying an interleaver map onto the real matrix;

generate other virtual data symbols being arranged in an other virtual matrix such that a given other virtual data symbol is associated with a respective second virtual row position and a respective second virtual column position in the other virtual matrix,
to generate including applying an other interleaver map onto the real matrix, the interleaver map being different from the other interleaver map such that (i) the given virtual data symbol and the given other virtual data symbol are copies of the given real data symbol, and the respective first virtual row position is different from the respective second virtual row position;

decode codewords formed by the other virtual matrix, the virtual matrix and the real matrix, a given codeword represented by a given row of other virtual data symbols in the other virtual matrix, a corresponding row of virtual data symbols in the virtual matrix, and a corresponding row of data symbols in the real matrix.