Patent ID: 11950407
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. A memory device, comprising:
a first transistor including a first gate electrode, a first contact electrode, and a shared contact electrode, wherein the shared contact electrode is coupled to a source area or a drain area of the first transistor, and further coupled to a bit line, and the first gate electrode is coupled to a first word line;
a second transistor including a second gate electrode, a second contact electrode, and the shared contact electrode, wherein the shared contact electrode is coupled to a source area or a drain area of the second transistor, the second gate electrode is coupled to a second word line;
a channel layer shared between the first transistor and the second transistor, wherein the first gate electrode and the second gate electrode are located at a first side of the channel layer, and the first contact electrode, the shared contact electrode, and the second contact electrode are located at a second side of the channel layer opposite to the first side;
a first capacitor coupled to the first contact electrode; and
a second capacitor coupled to the second contact electrode, wherein the first transistor and the first capacitor form a first memory cell, and the second transistor and the second capacitor form a second memory cell.