Patent ID: 11881853
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 23:
24. A true complement dynamic circuit for combining, in particular comparing, binary data on dynamic first and second input signals to third and fourth input signals, comprising:
at least a 1-bit compare circuit, wherein a first input signal and a second input signal are dynamic signals, the dynamic first and second input signals are complementary signals during an evaluation phase, the 1-bit compare circuit comprising at least:
a first part, which logically combines the first input signal and a third input signal with a logical “A OR NOT B” operation creating a fifth signal;
a second part, which logically combines the second input signal and a fourth input signal with a logical “A OR NOT B” operation creating a sixth signal; and
a third part, which logically combines the fifth signal and the sixth signal creating a seventh signal as an output (CMP_R; CMP_R_C), with:
a logical NAND operation in the case of a precharge to “1” logic circuit to a seventh signal as an output (CMP_R), or
a logical NOR operation in the case of a precharge to “0” logic circuit to a seventh signal as an output (CMP_R_C);

wherein a logical behavior is determined by the third input signal and the fourth input signal.