Patent ID: 11940945
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. An apparatus comprising:
an instruction memory storing a sequence of executable instructions, the executable instructions comprising a mixture of single instruction multiple data (SIMD) executable instructions containing multiple operands, and executable instructions containing single operands;
a fetch stage retrieving an executable instruction from the instruction memory;
a decode stage configured to receive the executable instruction from the fetch stage, the decode stage identifying and separating data operands and generating control signals;
the decode stage transmitting the single operand instructions to an execution stage for processing;
a SIMD engine comprising a plurality of SIMD processing elements (SPEs), wherein each SPE of the plurality of SPEs comprises a data input receiving multiple operands from the decode stage, a control input receiving control signals from the decode stage, and a data output, wherein each SPE is configured to provide on the data output a result of a selected arithmetic logic unit (ALU) operation on the data input, and wherein the selected ALU operation is determined as a function of the control input;
a control memory having an address input and a data output, wherein the address input is operably coupled with a decode stage of a pipelined processor to receive an address determined as a function of an instruction decoded by the decode stage, wherein the control memory data output is operably coupled with the control inputs of the plurality of SPEs to provide a plurality of SPE control signals read from the control memory to the control inputs of the plurality of SPEs;
an input FIFO having a plurality of inputs configured to receive data and a plurality of outputs operably coupled with the data inputs of the plurality of SPEs; and
an output FIFO having a plurality of inputs operably coupled with the data outputs of the plurality of SPEs, wherein the output FIFO has an output configured to provide an output of the SIMD engine determined as a function of individual results output by the plurality of SPEs.