Patent ID: 11929433
Assignee: GLOBALFOUNDRIES U.S. INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. A semiconductor device comprising:
a semiconductor-on-insulator (SOI) layer above a substrate;
a first source region in the SOI layer;
a first channel region in the SOI layer;
a first drift region in the SOI layer;
a drain region in the SOI layer, wherein the first drift region adjoins the drain region and the first channel region;
a second drift region in the SOI layer, wherein the drain region is laterally between the first drift region and the second drift region;
a second channel region in the SOI layer, wherein the second drift region adjoins the drain region and the second channel region;
a second source region in the SOI layer;
a first gate structure on the first channel region;
a second gate structure on the second channel region;
a first well in the substrate, the first well is below the drain region, the first drift region, and the second drift region;
a second well in the substrate, the second well is adjacent to the first well, the second well is below the first source region, the second well is of an opposite polarity to the first well;
a third well in the substrate, the third well is adjacent to the first well, the third well is below the second source region, the third well is of an opposite polarity to the first well;
a first multilayer drain spacer on a drain-facing sidewall of the first gate structure and covers the first drift region;
a second multilayer drain spacer on a drain-facing sidewall of the second gate structure and covers the second drift region;
a first source spacer on a source-facing sidewall of the first gate structure, wherein the first source spacer is shaped asymmetrically compared to the first multilayer drain spacer; and
a second source spacer on a source-facing sidewall of the second gate structure, wherein the second source spacer is shaped asymmetrically compared to the second multilayer drain spacer.