Patent ID: 11935955
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A method comprising:
depositing a dummy gate over and along sidewalls of a fin;
forming a gate spacer along a sidewall of the dummy gate;
forming a recess in the fin adjacent the gate spacer; and
forming a source/drain region in the recess, the forming of the source/drain region comprising:
forming a first layer in the recess, the first layer comprising a first silicon-containing material doped with a first concentration of a first n-type dopant; and
epitaxially growing a second layer on the first layer, the second layer comprising a second silicon-containing material doped with a concentration of a second n-type dopant, wherein the second n-type dopant is different than the first n-type dopant, wherein the second layer has a second concentration of the first n-type dopant that is less than the first concentration of the first n-type dopant, and wherein the first layer separates the second layer 82B from the fin.