Patent ID: 11923449
Assignee: WINBOND ELECTRONICS CORP.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A manufacturing method of a semiconductor device, comprising:
forming a recess at a top surface of a substrate;
forming a first channel layer and a first barrier layer in order, to conformally cover surfaces of the recess;
forming a first dummy structure and a second dummy structure in the recess, wherein the first and second dummy structures are in lateral contact with vertically extending portions of the first barrier layer, and are laterally spaced apart from each other;
forming a mask structure between the first and second dummy structures;
removing the first and second dummy structures to form first and second gaps between the mask structure and the vertically extending portions of the first barrier layer;
forming a first gate electrode and a second gate electrode in the first and second gaps, respectively;
removing the mask structure; and
filling an insulating structure in the recess.