Patent ID: 11900979
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. The method of claim 16, wherein the time-varying resistance device is a ferroelectric gate tuned field effect transistor (FEFET) comprising a substrate including a source region, a drain region, and a channel region between the source region and the drain region; a dielectric layer formed on the channel region of the substrate; a ferroelectric (FE) layer formed on the dielectric layer; a top electrode (TE) layer formed on the FE layer; a bias terminal coupled to the TE layer; a first voltage input terminal coupled to the source region; and a second voltage input terminal coupled to the drain region, and wherein the method further comprises:
applying a bias signal to the bias terminal to change an FE polarization of the FE layer, wherein a channel resistance is created in the channel region based on the bias of the FE polarization, and the probabilistic resistance value is based on the channel resistance.