Patent ID: 11908790
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A method for forming a chip structure, comprising:
forming a first passivation layer over a first conductive line;
forming a first conductive via structure, a second conductive via structure, and a conductive pad over the first conductive line, wherein
the first conductive via structure and the second conductive via structure pass through the first passivation layer, the conductive pad is over the first passivation layer, the first conductive via structure, and the second conductive via structure, and the first conductive via structure has a stepped sidewall in a cross-sectional view of the first conductive via structure; and
forming a conductive pillar over the conductive pad.