Patent ID: 11922012
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device, comprising:
at least one memory storage array comprising physical blocks of memory cells;
a controller operable in response to instructions stored in the memory device, wherein the instructions, when executed by the controller, cause the controller to perform operations comprising:
in response to a first read request to the memory device, reading a sequential mapping table stored within the memory device, the sequential mapping table including multiple sequential write entries associating logical block addresses (LBAs) with physical block addresses (PBAs) of block of the storage array, wherein the sequential mapping table includes;
a sequential block write length indicator identifying a number of multiple sequential PBAs corresponding to a first group of sequential LBAs;
a starting PBA of the sequential PBAs; and
to only add an entry into the sequential mapping table if a new write is sequentially longer than a shortest entry in the sequential mapping table.