Patent ID: 11927981
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 16:
17. An apparatus comprising:
a clock counter configured to count a number of clock signals received from a clock management circuit;
a plurality of performance counters comprising:
a first performance counter configured to count a first parameter related to a calculation of a workload based on an event signal detected in a bus connecting a plurality of processing devices, and
a second performance counter configured to count a second parameter related to the calculation of the workload based on the event signal; and

an interface configured to transmit the number of clock signals, the first parameter and the second parameter to a dynamic voltage frequency scaling (DVFS) governor circuit, which is configured to determine an operation frequency and an operation voltage of each of the plurality of processing devices based on the workload.