Patent ID: 11868280
Assignee: MICRON TECHNOLOGY, INC.
Field: nan (nan)
Classification: CPC nan | IPC G

Claim 9:
10. A method, comprising:
asserting a primary enable signal provided to chaining circuitry coupled to a plurality of sequencers;
responsive to assertion of the primary enable signal, asserting, via the chaining circuitry and in accordance with a first sequence, respective sequencer enable signals provided to the plurality of sequencers;
responsive to deassertion of the primary enable signal, deasserting, via the chaining circuitry and in accordance with a second sequence, the respective sequencer enable signals provided to the plurality of sequencers, wherein the second sequence has a reverse order of the first sequence;
wherein the chaining circuitry comprises:
a first logic gate configured to receive the primary enable signal as a first input and an output signal of a second sequencer as a second input and provide its output as an input of a second logic gate, wherein an output of the second logic gate is a sequencer enable signal provided to a first sequencer of the plurality of sequencers.