Patent ID: 11967383
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. A method, comprising:
starting a programming process that concurrently programs a set of data into a set of non-volatile memory cells arranged in multiple planes, the programming process includes applying program voltage pulses to the set of non-volatile memory cells arranged in multiple planes;
completing the programming process for memory cells of the set of non-volatile memory cells arranged in multiple planes that are targeted to a first set of data states;
identifying a slow plane of the multiple planes based on the programming process, the slow plane includes non-volatile memory cells that experience smallest change in threshold voltage per program voltage pulse as compared to non-volatile memory cells of other planes of the multiple planes; and
completing the programming process for memory cells of the set of non-volatile memory cells arranged in multiple planes that are targeted to a second set of data states including increasing speed of programming for the slow plane relative to another plane of the multiple planes that is concurrently experiencing programming, the second set of one or more data states are higher in threshold voltage than the first set of data states.