Patent ID: 11876735
Assignee: CISCO TECHNOLOGY, INC.
Field: Digital communication (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 7:
8. A method, comprising:
controlling, by a processor, data packet transmissions received via an input to a primary memory and a secondary memory, wherein:
the primary memory and the secondary memory are communicatively coupled to one another;
the primary memory comprises a first buffering capacity and a first memory speed;
the secondary memory comprises a second buffering capacity and a second memory speed; and
the second memory speed is slower than the first memory speed;

monitoring, by the processor, a current buffering level of the primary memory;
comparing, by the processor, the current buffering level to a first buffering threshold, the first buffering threshold being indicative of a buffering capacity difference between the first buffering capacity and the second buffering capacity; and
in response to determining that the current buffering level is equal to or greater than the first buffering threshold, pausing the data packet transmissions via the input to primary memory and the secondary memory.