Patent ID: 11966740
Assignee: GRAPHCORE LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 18:
19. A method of operating a processor, the method comprising:
using at least one register file comprising a group of operand registers to hold data values loaded from memory or to be stored back to memory, each operand register being a fixed number of bits in length;
using processing logic comprising floating point logic to perform floating point operations on a first one of the data values in the at least one register file, whereby for the first one of the data values held in a first one of the operand registers, the floating point logic operations process the fixed number of bits in the first one of the data values according to a floating point format comprising a set of mantissa bits and a set of exponent bits, wherein the floating point logic performs each of the floating point operations in response to execution of a single respective instance of a respective type of machine code instruction in an instruction set of the processor; and
selecting among a plurality of different variants of the floating point format, at least some of the variants having different size sets of mantissa bits and different size sets of exponent bits relative to one another;
wherein a same one of the floating point operations, performed in response to execution of a same, single instance of a same one of said types of machine code instruction, operates on the first one of the data values held in a first one of the operand registers and on a second one of the data values held in a second one of the operand registers other than the first operand register, and wherein the same floating point operation includes applying a first of the variants of the floating point number format to the first data value in the first operand register and a second of the variants to the second data value in the second operand register;
programming a first programmable setting in a first control register and programming a second programmable setting in a second control register,
wherein the first variant of the floating point number format applied to the first data value as held in the first operand register is programmable via the first programmable setting in the first control register and the second variant of the floating point number format applied to the second data value as held in the second operand register is programmed via the second programmable setting in the second control register, and
wherein the first and second programmable settings select the first variant of the floating point number format for the first data value in the first operand register and the second variant of the floating point number format for the second floating point data value in the second operand register independently of one another for the same floating point operation.