Patent ID: 11940940
Assignee: GRAPHCORE LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G

Claim 14:
15. A non-transitory computer readable medium storing a computer program comprising a plurality of local programs, a first local program being associated with a first processor and a second local program being associated with a second processor, the first local program and the second local program together providing at least part of the computer program, wherein the first local program comprises a schedule defining, for different phases of execution of the computer program, which of a plurality of interfaces of a data processing device the first processor is scheduled to connect to,
wherein the first local program is configured to, in dependence upon the schedule, cause the first processor to:
control switching circuitry associated with the first processor to, during a first of the phases of execution of the computer program, connect to a first bus of a switching fabric so as to enable reception, at the first processor, of a first set of the ingress data packets from a first of the interfaces that is associated with the first bus; and
control the switching circuitry to, during a second of the phases of execution of the computer program, connect to a second bus of the switching fabric so as to enable reception, at the first processor, of a second set of the ingress data packets from a second of the interfaces that is associated with the second bus,
wherein the different phases of execution are exchange phases, wherein the plurality of processors are configured to alternate between operation in compute phases and the exchange phases, the compute phases and the exchange phases being separated by barrier synchronisations enforced between at least some of the processors.