Patent ID: 11903213
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A memory structure, comprising
a stack of insulating layers and gate electrode layers stacked in alteration;
a first dielectric column penetrating through the stack;
a source electrode and a drain electrode disposed on opposite sides of the first dielectric column;
a second dielectric column penetrating through the stack and disposed alongside the first dielectric column and between the source electrode and the drain electrode, wherein the source electrode and the drain electrode are located on opposite horizontal sides of the second dielectric column;
a memory arc wall structure, penetrating through the stack, disposed around the second dielectric column and extended from the source electrode to the drain electrode; and
a channel wall structure, penetrating through the stack, surrounded by the memory arc wall structure, and disposed between the memory arc wall structure and the drain electrode and the source electrode, wherein the channel wall structure connects the drain electrode and the source electrode, and the memory wall arc structure is sandwiched between the gate electrode layers and the channel wall structure,
wherein lateral surfaces of the second dielectric column, the source electrode, and the drain electrode are respectively exposed from a lateral edge of the stack.