Patent ID: 11862560
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 4:
5. The package structure of claim 3, wherein the second build-up layer further comprises a first inter-layer film, and the second metallization layer comprises a first portion and a second portion stacked on the first portion, wherein the first inter-layer film is sandwiched between the first dielectric layer and the second dielectric layer, and the first portion of the second metallization layer is located between the first metallization layer and the second portion of the second metallization layer,
wherein an interface of the first dielectric layer and the first inter-layer film is located at a sidewall of the first metallization layer, and an interface of the first inter-layer film and the second dielectric layer is located at a sidewall of the first portion of the second metallization layer.