Patent ID: 11908886
Assignee: DANMARKS TEKNISKE UNIVERSITET
Field: Electrical machinery, apparatus, energy (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A stack of semiconductor substrate members comprising at least a first semiconductor substrate member and a second semiconductor substrate member, each comprising;
a first region with at least one passive electrical component with a first electrically conductive layer pattern of a first electrically conductive material and a second electrically conductive layer pattern of a second electrically conductive material, wherein a trench or through-hole is formed in the semiconductor substrate member within the first region, and wherein the first electrically conductive material is deposited at least on a bottom portion of the trench or on a sidewall of the through-hole and electrically connected to one or both of the first conductive layer pattern and the second conductive layer pattern;
a second region with at least one active semiconductor component, said at least one active semiconductor component being a control part of a DC-DC power converter, embedded and fully integrated in the semiconductor substrate member by a semiconductor fabrication process, wherein the semiconductor fabrication process is a silicon fabrication process,
wherein the at least one passive electrical component is adapted and electrically connected to the active semiconductor component to provide power converter functionality,
wherein the power converter is embedded in a single semiconductor substrate piece by a semiconductor manufacturing process,
wherein the first electrically conductive layer pattern of the first electrically conductive material and the second electrically conductive layer pattern of the second electrically conductive material are deposited on respective sides of the semiconductor substrate member, which are at a respective top side and bottom side of the semiconductor substrate member, and wherein the first electrically conductive layer pattern and the second electrically conductive layer pattern extend in parallel horizontal planes at the top side and bottom side of the semiconductor substrate member, respectively, between the first region and the second region to connect the at least one passive electrical component with the at least one active semiconductor component.