Patent ID: 11886746
Assignee: DREAMBIG SEMICONDUCTOR INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G

Claim 12:
13. A method to control a content addressable memory that includes multiple integrated circuit memory devices that share common memory address locations and that are coupled for simultaneous access to the common memory address locations, the method comprising:
storing in a non-transitory storage device,
a hash information structure that stores multiple hash values determined using the hash logic, wherein the hash information structure associates each hash value with a corresponding common memory address location of the memory devices; and
an activity status storage status information structure that stores information that indicates, for multiple common memory address locations for each memory device, whether the memory device stores content data at the common memory address location;

receiving a key value;
generating a hash value using the hash logic, based upon the received key value, wherein the generated hash value is one of the hash values stored in the hash table;
storing the received key value in at least one of the integrated circuit memory devices at a common memory address location that is associated with the hash value that is generated by the hash logic; and
adjusting information stored in the storage activity status information structure for the common memory address location at which the key value is stored, to indicate which at least one of the integrated circuit memory devices stores the received key value.