Patent ID: 11917811
Assignee: WINBOND ELECTRONICS CORP.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 1:
2. The memory as claimed in claim 1, wherein the second insulating structure comprises:
a first portion extending upwardly from a top surface of the capacitor contact structure, wherein the first portion has a width that gradually decreases downwardly; and
a second portion extending downwardly from the top surface of the first connecting pad, wherein the second portion has a width that gradually decreases downwardly, wherein the top surface of the second insulating structure has a first width W1, wherein a maximum distance W2 is between a surface of the first portion of the second insulating structure and a sidewall surface of the bit line structure, and wherein a ratio (W1/W2) of the first width W1 to the maximum distance W2 is 1.5 to 10.0.