Patent ID: 11929746
Assignee: MINIMA PROCESSOR OY
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G  Y | IPC H

Claim 4:
5. An integrated circuit, comprising at least one register circuit for temporarily storing a digital value obtained from an output of a circuit element preceding the at least one register circuit in the integrated circuit, the at least one register circuit comprising:
a data input for receiving said digital value for temporary storage,
a data output for outputting the temporarily stored digital value,
a triggering event input for receiving a triggering signal, a triggering edge of which defines an allowable time limit before which a digital value must appear at said data input to become temporarily stored, and
on the data propagation path between said data input and data output a sequence of a first pulse-enabled subregister stage and second pulse-enabled subregister stage;
wherein said first pulse-enabled subregister stage is configured to receive said triggering signal delayed with respect to the triggering signal received by said second pulse-enabled subregister stage, the length of the delay being a fraction of a cycle of said triggering signal,
wherein said register circuit comprises a timing event observation logic configured to output a timing event observation signal at an output of said register circuit as an indicator of said digital value at said data input having changed within a time window that begins at said allowable time limit and is shorter than one cycle of said triggering signal,
wherein the register circuit is a dual edge triggered flip-flop, and
wherein said timing event observation logic comprises:
a TE data input coupled to said data input of the register circuit,
a TE clock input coupled to said triggering event input of the register circuit,
a TE delay element coupled to said TE clock input and configured to delay the triggering signal received at said TE clock input by the length of said delay,
an XOR gate coupled to said TE clock input and said TE delay element and configured to produce an active timing window indicator signal whenever the values received from said TE clock input and said TE delay element are unequal, and
a transition detector coupled to said TE data input and the output of said XOR gate and configured to produce said timing event observation signal in response to the value in said TE data input changing while said timing window indicator signal is active.