Patent ID: 11862523
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 16:
17. An apparatus, comprising:
a wafer fabricating apparatus, configured to encapsulate a plurality of dies of at least two types placed on a carrier with an insulating layer to form a reconstructed wafer;
a controller, configured to control a grinding apparatus to perform a grinding process on the reconstructed wafer and retrieve a thickness signal from a sensor that periodically senses an interface of the reconstructed wafer to calculate a plurality of thicknesses from a surface of the insulating layer of the reconstructed wafer to the interface of the reconstructed wafer and generate the thickness signal comprising the thicknesses, wherein the thicknesses in the thickness signal comprise thicknesses from the surface of the insulating layer to interfaces of the dies of a first type and thicknesses from the surface of the insulating layer to interfaces of the dies of a second type different from the thicknesses from the surface of the insulating layer to the interfaces of the dies of the first type; and
a timer, configured to generate a clock signal having a plurality of pulses with a time interval smaller than a time length of the thickness signal, wherein
the controller is further configured to filter the thickness signal according to the clock signal to output a thickness maximum or a thickness minimum among the thicknesses in the thickness signal generated within each time interval according to an average thickness of a target die among the dies of the first type and the second type to determine the endpoint of the grinding process, and control the grinding apparatus to end the grinding process at the endpoint.