Patent ID: 11934305
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 2:
3. The memory system according to claim 1, further comprising:
a third memory configured to store the data received from the host until the data is stored in the first memory, wherein
the management information associates a logical address and a location where the data is stored in the first memory or the third memory for each first data unit,
the fourth circuit is configured to:
transmit a second sub-command among the plurality of first sub-commands acquired from the third circuit to the fifth circuit without transmitting the second sub-command to the first circuit, the second sub-command being a first sub-command to which first location information indicating a location in the first memory is added; and
transmit a third sub-command among the plurality of first sub-commands acquired from the third circuit to the first circuit and the fifth circuit, the third sub-command being a first sub-command to which second location information indicating a location in the third memory is added,

the sixth circuit is configured to execute the read operation based on only the second sub-command among the plurality of reordered first sub-commands, and
the first circuit is configured to transmit, to the host, first data read from the first memory by the read operation and second data stored at the location indicated by the second location information added to the third sub-command in the third memory.