Patent ID: 11908948
Assignee: MICRON TECHNOLOGY, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. A 3D NAND Flash memory device, comprising:
a stack structure comprising conductive structures vertically alternating with insulative structures;
pillar structures comprising semiconductive material extending through the stack structure;
a staircase structure having steps partially defined by horizontal ends of at least some of the conductive structures of the stack structure;
conductive contact structures in physical contact with the steps of the staircase structure;
string driver transistors vertically overlying and horizontally overlapping the staircase structure, the string driver transistors individually comprising:
a heterogeneous lower contact structure in physical contact with one of the conductive contact structures and including a first material comprising:
a first atomic concentration of indium; and
a first atomic concentration of oxygen;

a channel structure in physical contact with the heterogeneous lower contact structure and including a second material comprising:
a second atomic concentration of indium less than the first atomic concentration of indium; and
a second atomic concentration of oxygen greater than the first atomic concentration of oxygen;

a heterogeneous upper contact structure in physical contact with the channel structure and having a non-planar lower boundary, the heterogeneous upper contact structure including a third material comprising:
a third atomic concentration of indium greater than the second atomic concentration of indium; and
a third atomic concentration of oxygen less than the second atomic concentration of oxygen;

gate dielectric material in physical contact with and substantially covering outer side surfaces of the channel structure, the channel structure and the gate dielectric material each substantially confined within a horizontal area of the heterogeneous lower contact structure; and
gate electrode material in physical contact with and partially covering outer side surfaces of the gate dielectric material.