Patent ID: 11972827
Assignee: WINBOND ELECTRONICS CORP.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A reading method, which is a reading method of a semiconductor storage device, wherein the semiconductor storage device comprises an NAND chip, comprising an NAND-type memory array and a page buffer/sensing circuit, wherein the page buffer/sensing circuit comprises a first latch and a second latch that are able to hold page data read from a memory array; and an ECC chip, comprising error detection and correction functions for data transmitted from the NAND chip, and
in the NAND chip, holding a first data portion and a second data portion of a page read from the memory array in the first latch, and transmitting the second data portion held in the first latch to the second latch, then transmitting the first data portion held in the first latch to the ECC chip, and transmitting the second data portion held in the second latch to the ECC chip,
in the ECC chip, performing error detection and correction of the second data portion after error detection and correction of the first data portion is performed,
reading a next page from the memory array in the NAND chip in response to the ECC chip outputting the error-corrected first data portion.