Patent ID: 11967600
Assignee: JAPAN DISPLAY INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. An electronic device with an electrostatic protection circuit comprising:
a transparent substrate;
a first metal film and a second metal film formed on the transparent substrate;
a first insulating layer formed on the first metal film and the second metal film;
a first semiconductor layer which overlaps with the first metal film which is between the first insulating layer and the transparent substrate;
a second semiconductor layer which overlaps with the second metal film which is between the first insulating layer and the transparent substrate;
a second insulating layer formed on the first semiconductor layer and the second semiconductor layer;
a first gate electrode formed on the second insulating layer and overlaps with the first semiconductor layer;
a second gate electrode formed on the second insulating layer and overlaps with the second semiconductor layer;
a third insulating layer formed on the first gate electrode and the second gate electrode;
a third electrode formed on the third insulating layer and between the first semiconductor layer and the second semiconductor layer in a plan view;
a first electrode which is formed on the third insulating layer; and a second electrode which is formed on the third insulating layer and which connects with the second semiconductor layer, wherein
the first electrode connects with the first semiconductor layer,
the second electrode connects with the second semiconductor layer,
the third electrode connects with the first semiconductor layer,
the third electrode connects with the second semiconductor layer,
the first metal film overlaps with a part of the third electrode,
the second metal film overlaps with a part of the third electrode,
the first metal film is separated from the second metal layer, and
a length of the first semiconductor layer is shorter than that of the first metal film in the plan view and a length of the second semiconductor layer is shorter than that of the second metal layer in the plan view.