Patent ID: 11907036
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 0:
1. An integrated circuit comprising:
a plurality of sub circuits configured to process an instruction according to an operating condition;
a plurality of active counters configured to count an individual active time, which is a time for each sub circuit of the plurality of sub circuits to process an instruction;
a total counter configured to count a total active time during which at least one sub circuit of the plurality of sub circuits is active; and
a Dynamic Voltage and Frequency Scaling (DVFS) circuit configured to
derive a workload for the plurality of sub circuits,
derive energy consumed by each sub circuit of the plurality of sub circuits during a sample period based on a product of an individual active time of each sub circuit and an individual power consumption of each sub circuit,
derive a total power consumption of the plurality of sub circuits during the sample period based on a ratio of a sum of the energy consumed by each sub circuit of the plurality of sub circuits to the total active time,
derive a power usage rate based on the total power consumption of the plurality of sub circuits; and
adjust an operating condition of the plurality of sub circuits based on the ratio of the workload to the power usage rate.