Patent ID: 11869916
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A method comprising:
receiving a device substrate;
forming an interconnect structure on a front side of the device substrate;
etching a recess into a backside of the device substrate until a portion of the interconnect structure is exposed, the recess having a recess depth and an edge of the recess being defined by an inner sidewall of the device substrate;
forming a conductive bond pad in the recess;
forming a first plurality of dielectric layers directly over the conductive bond pad, extending along the inner sidewall of the device substrate, and covering the backside of the device substrate,
forming a second dielectric layer directly over the first plurality of dielectric layers and directly over the conductive bond pad, the second dielectric layer having a material composition that differs from that of the first plurality of dielectric layers and extending along an inner sidewall of the first plurality of dielectric layers, wherein the first plurality of dielectric layers and the second dielectric layer collectively have a first total thickness that is less than the recess depth; and
performing a first chemical mechanical planarization (CMP) to remove uppermost portions of some of the first plurality of dielectric layers, thereby leaving at least one of the first plurality of dielectric layers with an uppermost planarized surface over an edge of the recess and leaving other portions of the first plurality of dielectric layers over the conductive bond pad intact, wherein the uppermost planarized surfaces are cut to be level with an upper surface of another of the first plurality of dielectric layers.