Patent ID: 11973080
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A structure, comprising:
a portion of a p-type substrate doped to form a deep n-type well;
a p-type well over the deep n-type well;
portions of the p-type well doped to form a drain region and a source region within the p-type well;
a first intrinsic embedded semiconductor region (ESR) on the deep n-type well, wherein the first intrinsic ESR abuts opposite sides of the p-type well;
an isolation structure on the first intrinsic ESR and surrounding the drain region and the source region;
a first n-type well on a top surface of the deep n-type well and abutting the first intrinsic ESR;
a second intrinsic ESR surrounding the first intrinsic ESR; and
a second n-type well abutting the second intrinsic ESR and the deep n-type well.