Patent ID: 11907141
Assignee: QUALCOMM INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. A computing device, comprising:
a first memory device;
a second memory device; and
a memory controller communicatively connected to the first memory device and the second memory device, and configured to:
receive a first memory access command and a first address at which to implement the first memory access command in a logical rank;
generate a first signal configured to indicate to the first memory device of the logical rank to implement the first memory access command via a first partial channel;
send the first signal to the first memory device;
generate a second signal configured to indicate to the second memory device of the logical rank that is different from the first memory device to implement the first memory access command via a second partial channel; and
send the second signal to the second memory device.