Patent ID: 11895845
Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 19:
20. The method according to claim 18, wherein the first dielectric layer in the stack is close to the vertical active region, the second dielectric layer in the stack is close to the electrode structure, and the first dielectric layer and the charge trapping layer in the stack of the first gate dielectric layer are respectively arranged in same layers as the first dielectric layer and the charge trapping layer in the stack of the second gate dielectric layer; and
wherein the forming the first gate dielectric layer and the second gate dielectric layer comprises:
before filling the semiconductor material, forming the charge trapping layer and the first dielectric layer that extend continuously along a sidewall of the each vertical hole;
when replacing the first sacrificial layer, forming the second dielectric layer of the first gate dielectric layer on a sidewall of the charge trapping layer formed on the sidewall of the each vertical hole; and
when replacing the second sacrificial layer, forming the second dielectric layer of the second gate dielectric layer on a sidewall of the charge trapping layer formed on the sidewall of the each vertical hole.