Patent ID: 11955152
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A semiconductor device comprising:
a bottom electrode contact disposed over one or more of a plurality of conductive lines;
magnetoresistive random access memory (MRAM) pillars constructed over the bottom electrode contact;
an encapsulation layer section disposed continuously between a pair of the MRAM pillars such that a thickness of the encapsulation layer in a tight pitch gap between the MRAM pillars is greater than a thickness of the encapsulation layer on sidewalls of the MRAM pillars so that an aspect ratio of the tight pitch gap is reduced by decreasing a height of the tight pitch gap; and
a dielectric disposed within the encapsulation layer section, wherein the dielectric fills an entirety of a space defined within the encapsulation layer section.