Patent ID: 11923007
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 6:
7. An apparatus, comprising:
a memory array comprising a plurality of memory cells; and
circuitry coupled with the memory array and configured to cause the apparatus to:
write at least a subset of the plurality of memory cells according to one or more parameters;
modify at least one of the one or more parameters for a write operation of the plurality of memory cells based at least in part on a power up for a device, the power up for the device after writing the at least the subset of the plurality of memory cells, wherein the at least one of the one or more parameters is associated with a first value before the modifying and a second value after the modifying; and
write the plurality of memory cells according to the second value of the modified at least one of the one or more parameters after writing the at least the subset of the plurality of memory cells according to the one or more parameters.