Patent ID: 11860732
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A system comprising:
a memory device comprising a plurality of fault tolerant stripes, wherein each of the plurality of fault tolerant stripes comprise one or more sets of memory cells; and
a processing device coupled to the memory device, the processing device to perform operations comprising:
receiving a first request to program first host data to the memory device, wherein the first host data is associated with a first logical address that corresponds to a first set of memory cells of a fault tolerant stripe of the plurality of fault tolerant stripes;
receiving a second request to program second host data to the memory device, wherein the second host data is associated with a second logical address that corresponds to a second set of memory cells of the fault tolerant stripe;
determining, based on a redundancy factor that corresponds to the first logical address and the second logical address, that redundancy metadata associated with the first host data and the second host data is to be stored at a third set of memory cells of the fault tolerant stripe;
generating redundancy metadata associated with the first host data and the second host data; and
programming the generated redundancy metadata to the second set of memory cells.