Patent ID: 11875095
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. A computer system, the computer system comprising:
a processor; and
a memory storing instructions that, when executed by the processor, configure the computer system to:
simulate a processor design model running an application within a hardware simulation accelerator, the hardware simulation accelerator comprising a plurality of application-specific integrated circuit processors, the processor design model comprising a plurality of logic gates represented using a hardware description language, the application comprising a plurality of transactions, the application loaded into a memory of the hardware simulation accelerator, the simulating comprising simulating, using the plurality of application-specific integrated circuit processors, execution of the plurality of logic gates;
set a previous measured latency to a target latency value; and
for each individual transaction of the application:
generate, by the hardware simulation accelerator at a start of an execution of the individual transaction, a first checkpoint file, the first checkpoint file comprising data of a meta state of the processor design model at said start, wherein the first checkpoint file comprises a value of a counter at said start;
generate, by the hardware simulation accelerator at a completion of the individual transaction, a second checkpoint file, the second checkpoint file comprising data of the meta state of the processor design model at said completion, wherein the second checkpoint file comprises a value of the counter, wherein the simulating continues after generating the second checkpoint file;
measure, by a software checker using the first checkpoint file and the second checkpoint file, a latency of said individual transaction from said start to said completion;
delete, responsive to determining that the measured latency is less than or equal to the previous measured latency, the first checkpoint file and the second checkpoint file;
replace, responsive to determining that the measured latency is greater than the previous measured latency, the previous measured latency with the measured latency, the replacing comprising saving the first checkpoint file and the second checkpoint file; and

delete, subsequent to measuring a latency of each individual transaction of the application, a first checkpoint file and a second checkpoint file corresponding to a measured latency that is less than a maximum measured latency.