Patent ID: 11877505
Assignee: QORVO US, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor device comprising:
a package substrate;
a semiconductor die on the package substrate, the semiconductor die comprising an active area and one or more metallization layers on the active area;
at least one fluorinated polymer layer on the semiconductor die and surfaces of the package substrate that are adjacent the semiconductor die;
at least one wire bond electrically connected between the semiconductor die and the package substrate, the at least one fluorinated polymer layer being arranged to conformally coat the at least one wire bond; and
an additional layer arranged between the at least one fluorinated polymer layer and the one or more metallization layers, the additional layer comprising at least one of a planarization layer and a diecoat film;
wherein the at least one wire bond is arranged to pass through an opening in the additional layer to electrically connect with the semiconductor die, and a portion of the at least one fluorinated polymer layer is arranged within the opening.