Patent ID: 11909409
Assignee: FARADAY TECHNOLOGY CORPORATION
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A method for generating an output clock with reduced jitter from a reference clock, the method comprising:
receiving a reference clock and a feedback clock, and comparing the phases of the reference clock and feedback clock to generate up and down control signals;
generating an oscillation signal according to the up and down control signals;
performing frequency division on the oscillation signal according to a modulated sequence to generate a modulated clock wherein an average of the modulated sequence over a plurality of clock cycles is a fractional number;
dividing the modulated clock by a fixed modulus to generate a divided clock; and
utilizing one of the modulated clock and the divided clock as the feedback clock;
wherein a frequency of the modulated clock is an integer multiple of the frequency of the divided clock.