Patent ID: 11908797
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. An integrated circuit device comprising:
a bit line comprising a lower conductive layer and an upper conductive layer on the lower conductive layer in a vertical direction, the lower conductive layer being on a substrate and the upper conductive layer having a width less than a width of the lower conductive layer in a horizontal direction;
an insulating capping pattern on the upper conductive layer in the vertical direction, the insulating capping pattern having a width greater than the width of the upper conductive layer in the horizontal direction; and
a main insulating spacer on a sidewall of the bit line and a sidewall of the insulating capping pattern, the main insulating spacer comprising an extended portion that is convex toward the upper conductive layer,
wherein the width of the upper conductive layer in the horizontal direction varies along the vertical direction.