Patent ID: 11908505
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 1:
2. The data processing device of claim 1, wherein:
the single-transistor memory element in each of the first and second data storage units has a gate, a source and a drain; and
each of the plurality of memory cells further comprises:
a first matchline (“ML”) switching transistor configured to switchably connect the drain of the single-transistor memory element of the first data storage unit of the memory cell to the drain of the single-transistor memory element of the second data storage unit of the same memory cell; and
a second ML switching transistor configured to switchably connect the drain of the single-transistor memory element of the second data storage unit of the memory cell to the drain of the single-transistor memory element of the first data storage unit of a different one of the plurality of memory cells.