Patent ID: 11887691
Assignee: UNIVERSITY OF MARYLAND, COLLEGE PARK
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A temporal memory comprising:
a group of tunable delay components in electrical communication with a set of input lines and a set of output lines;
a write circuit connected to the tunable delay components such that an electrical signal can be controllably applied to each of the tunable delay components in correspondence with relative timing of a set of arriving wavefronts at the input lines associated with the tunable delay components, wherein the set of arriving wavefronts temporally encode data in their relative delay; and
a read circuit connected to the tunable delay components such that an output signal can be controllably conducted through the tunable delay components so as to cause a set of memory recall wavefronts to be generated at the set of output lines having a relative delay corresponding to the relative delay of the set of arriving wavefronts.