Patent ID: 11880590
Assignee: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. A method implemented by a system including a heterogeneous memory system including a memory module and high bandwidth memory (HBM) including a processing-in-memory (PIM) circuit, the method comprising:
offloading, by a host processor, a kernel on the heterogeneous memory system;
storing, by a memory controller, a border index value that indicates which memory, among the memory module and the HBM, stores a data array to be processed in accordance with execution of a working code of the offloaded kernel;
receiving, by the memory controller, information on the offloaded kernel, which comprises an identification number of the data array, a base address of the data array corresponding to the identification number, an index value representing offset from the base address, and a data size;
comparing, by the memory controller, the index value of the data array with the border index value;
determining, by the memory controller, that the data array is stored in the HBM when the index value is less than the border index value and determining the data array is stored in the memory module when the index value is greater than the border index value;
generating, by the memory controller, a memory module command set instructing the PIM circuit of the HBM to execute the working code by using the data array stored in the memory module; and
generating, by the memory controller, an HBM command set instructing the PIM circuit of the HBM to execute the working code by using the data array stored in the HBM.