Patent ID: 11893419
Assignee: APPLE INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. An electronic device comprising:
a first hardware accelerator configured to assist in performing processes of a first type;
a second hardware accelerator configured to assist in performing processes of a second type;
a third hardware accelerator configured to assist in performing processes of a third type;
a plurality of interface registers accessible by both the first and second hardware accelerators, wherein the first and second hardware accelerators are non-blocking accelerators that use the plurality of interface registers, and the third hardware accelerator is a blocking accelerator that does not use the plurality of interface registers other than an accelerator identifier register to assist in performing processes of the third type;
a processor configured to execute instructions configured to cause the processor to:
initiate a first process of the first type in the first hardware accelerator using the plurality of interface registers;
perform additional processing while the first hardware accelerator performs the first process after the first process is initiated;
initiate a second process of the second type in the second hardware accelerator using the plurality of interface registers; and
receive an indication via the plurality of interface registers to indicate that the first hardware accelerator has completed the first process and that the processor is to operate on results from the first process.