Patent ID: 11915762
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A memory system comprising:
a memory device including a string arranged between a bit line and a common source line and coupled to a voltage supply circuit through a drain select line and at least one word line, the string including a drain select transistor and at least one memory cell in series, the drain select transistor coupled to the drain select line, the memory cell coupled to the word line; and
a controller coupled to the memory device and configured to control the memory device to perform a program operation on the memory cell, the program operation including a plurality of program loops,
wherein the voltage supply circuit increases a level of a set control voltage to be applied to the drain select line in one or more initial periods among the plurality of program loops, and
wherein the program operation is performed based on a program mode corresponding to a second program pulse applied to the memory cell after a first program pulse is applied, the program mode determined as one selected from a first mode, a second mode, and a third mode, the first mode to apply the program pulse to change or adjust a threshold voltage of the at least one non-volatile memory cell by a first level which is equal to, or larger than, that caused by the first program pulse; the second mode to apply the second program pulse to change or adjust the threshold voltage of the at least one non-volatile memory cell by a second level which is smaller than that caused by the first program pulse; and the third mode to apply the second program pulse to the at least one non-volatile memory cell of which a change of the threshold voltage is inhibited.