Patent ID: 11861225
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
generating a super management unit (SMU) memory access command;
splitting the SMU memory access command into a plurality of management unit (MU) memory access commands;
issuing, to the memory device, a sequence of MU memory access commands from the plurality of MU memory access commands;
recording a status of each MU memory access command from the sequence of MU memory access commands in a control register;
determining that a MU memory access command from the sequence of MU memory access commands experienced an error; and
identifying which MU memory access command experienced the error using the control register.