Patent ID: 11869828
Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A semiconductor package, comprising:
a first die comprising a semiconductor substrate, wherein the semiconductor substrate has a first surface, a second surface opposite to the first surface, and a through hole between the first surface and the second surface and having an inner wall, the inner wall has a first lever arm, and a length of the first lever arm is less than a thickness of the semiconductor substrate; and, a first dielectric layer disposed within the through hole and defining a substantially straight sidewall extending from the first surface to the second surface of the semiconductor substrate, wherein the substantially straight sidewall of the first dielectric layer completely penetrates the semiconductor substrate, the substantially straight sidewall of the first dielectric layer is spaced apart from the inner wall, the substantially straight sidewall and the inner wall define a step shape with a first portion and a second portion of the first dielectric layer, the second portion is more adjacent to an external connector than the first portion is, and the second portion is wider than the first portion is.