Patent ID: 11869574
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 9:
10. The semiconductor memory device of claim 5, wherein the duty cycle adjuster comprises:
a p-channel metal-oxide semiconductor (PMOS) transistor connected between a power supply voltage and a first node and comprising a gate configured to receive a first enable signal;
a current source connected between the first node and a second node;
a second PMOS transistor connected between the second node and a third node and comprising a gate configured to receive a first data clock signal of the pair of differential clock signals;
a plurality of third PMOS transistors connected to the second node in parallel with the second PMOS transistor, each of the plurality of third PMOS transistors comprising a gate configured to receive the first data clock signal;
a plurality of fourth PMOS transistors, each of the plurality of fourth PMOS transistors connected between respective one of the plurality of third PMOS transistors and the third node and comprising a gate configured to receive respective bit of the first control code set;
a fifth PMOS transistor connected between the second node and a fourth node and comprising a gate configured to receive a second data clock signal of the pair of differential clock signals;
a plurality of sixth PMOS transistors connected to the second node in parallel with the fifth PMOS transistor, each of the plurality of sixth PMOS transistors comprising a gate configured to receive the second data clock signal;
a plurality of seventh PMOS transistors, each of the plurality of seventh PMOS transistors connected between a respective one of the plurality of sixth PMOS transistors and the fourth node and comprising a gate configured to receive a respective bit of a first inverted control code set obtained by inverting the first control code set;
a first resistor connected between the third node and a fifth node;
a second resistor connected between the fourth node and the fifth node; and
a n-channel metal-oxide semiconductor (NMOS) transistor connected between the fifth node and a ground voltage and comprising a gate configured to receive a second enable signal, wherein the first and second enable signals are complementary.