Patent ID: 11962306
Assignee: NVIDIA CORPORATION
Field: Measurement (Instruments)
Classification: CPC H  G | IPC G  H

Claim 18:
19. Clock anomaly detection circuitry, comprising:
a clock signal input for coupling to a clock signal that, during normal operation, oscillates between first and second clock states, wherein the first clock state corresponds to a first phase having a first phase expected duration and the second clock state corresponds to a second phase having a second phase expected duration;
an anomaly detection output; and
clock stopped detection logic coupled to the clock signal input and operable to assert the anomaly detection output if the clock signal remains in the first clock state longer than the first phase expected duration or remains in the second clock state longer than the second phase expected duration; wherein
a first edge of the clock signal signifies a start of a new clock phase having a new phase expected duration equal to one of the first or the second phase expected durations; and
the clock stopped detection logic comprises:
at least one edge triggered pulse generator that, when triggered responsive to the first edge of the clock signal, generates a pulse at a pulse output, the pulse having a pulse duration at least as long the new phase expected duration but not longer than an expected cycle time of the clock signal; and
one or more Boolean logic circuits configured to compare the pulse output with at least one version of the clock signal and, based on the comparison, to indicate if the pulse ends before the clock signal exhibits a second edge in a direction opposite to that of the first edge.