Patent ID: 11908940
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A CMOS integrated circuit (IC), comprising:
an n-type field effect transistor (FET) over a first region of a substrate; and
a p-type FET over a second region of the substrate, wherein each of the n-type and p-type FETs further comprise:
a source material and a drain material separated by a channel material;
a gate stack over the channel material, the gate stack comprising a gate dielectric and a gate electrode material;
contact metallization coupled to the source material and the drain material;
a first dielectric material between a lower portion of a sidewall of the gate electrode material and at least one of the source material, drain material, or contact metallization;
a second dielectric material over the first dielectric material, the second dielectric material between an upper portion of the sidewall of the gate electrode material and the contact metallization and having a composition different than the first dielectric material; and
a third dielectric material between the first dielectric material and the source material, drain material, or contact metallization, wherein the third dielectric material has a different composition than the first dielectric material.