Patent ID: 11887532
Assignee: LG DISPLAY CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A gate driving circuit comprising:
a first gate output buffer circuit including a first pull-up transistor and a first pull-down transistor; and
a control circuit configured to control a voltage of a Q node connected to a gate node of the first pull-up transistor and a voltage of a QB node connected to a gate node of the first pull-down transistor;
wherein,
the first pull-up transistor is connected between a first clock signal input node and a first gate output node, the first pull-down transistor is connected between the first gate output node and a first low level voltage node,
the control circuit includes:
a first transistor connected between a first driving voltage node and the QB node;
two second transistors connected in series between the QB node and a second low level voltage node;
a third transistor connected between a connection node of the two second transistors and the first driving voltage node, the third transistor having a gate node connected to the QB node;
a fourth transistor connected between a gate node of the first transistor and the first driving voltage node; and
two fifth transistors connected in series between the gate node of the first transistor and the second low level voltage node, and

a connection node of the two fifth transistors is electrically connected to a source node or a drain node of the third transistor.