Patent ID: 11899746
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 10:
11. An integrated circuit device comprising:
a cascade chain implemented using a plurality of digital signal processing (DSP) blocks, wherein the cascade chain is configurable to determine a dot-product based at least in part on first data associated with a first matrix and second data associated with a second matrix, wherein the first data comprises a first vector and a second vector of the first matrix, wherein the second data comprises a third vector of the second matrix, wherein a first DSP block of the plurality of DSP blocks comprises:
input circuitry configurable to receive a first vector of a first matrix, a second vector of the first matrix, and a third vector of a second matrix;
a register communicatively coupled to the input circuitry, wherein the register is configurable to store at least a portion of the second vector;
multiplier circuitry comprising:
a first multiplier configurable to:
receive the first vector directly from the input circuitry and receive the second vector from the register; and
determine a first partial inner-product based at least in part on the first vector and the second vector; and

a second multiplier configurable to determine a second partial inner-product based at least in part on the second vector and the third vector; and
adder circuitry configurable to determine a first inner-product of a dot-product based at least in part on the first partial inner-product; and

an embedded memory communicatively coupled to an output of the cascade chain and configurable to:
receive the dot-product from the cascade chain; and
store the dot-product.