Patent ID: 11966736
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 18:
19. An artificial intelligence (AI) accelerator system comprising:
processing cores;
interconnect circuitries; and
a memory,
wherein the interconnect circuitries are connected to the processing cores and the memory, and
wherein one of the interconnect circuitries is configured to:
receive a command from at least one processing core among the processing cores;
perform, based on the received command, an operation including an accumulation operation on sets of data stored in the memory and an aggregation operation on results processed by the at least one processing core; and
provide the memory or the at least one processing core with a result of the performing of the accumulation operation and the aggregation operation,

wherein the one of the interconnect circuitries comprises:
control circuitry configured to generate a control signal based on the received command, and determine an address of the memory based on address information received from the processing core;
address circuitry configured to generate a signal corresponding to the address of the memory based on the received command;
command circuitry configured to transmit, to the memory, the control signal, in response to the control signal being received from the control circuitry; and
read data circuitry configured to transmit, to the processing core, data read from the memory and cumulative data in which sets of the data read from the memory are accumulated, based on the control signal,
wherein the read data circuitry comprises a plurality of sub-data circuitries, and is configured to provide the processing core with the cumulative data stored in one sub-data circuitry among the sub-data circuitries, based on the control signal, and
wherein the cumulative data is data in which the data read from the memory and data of the one sub-data circuitry are accumulated.