Patent ID: 11880590
Assignee: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. The system of claim 7, wherein the memory controller is further configured to generate an HBM command set instructing the PIM circuit of the HBM to perform the operation processing,
wherein the HBM command set includes an opcode parameter, a vector size parameter, a source parameter, and a destination parameter, and
wherein the opcode parameter indicates a command of the offloaded kernel, the vector size parameter indicates a correlation between an amount of data inputs and outputs of a DRAM cache line combined with the host processor and an amount of data inputs and outputs of the data array, the source parameter indicates an address of the HBM corresponding to the data array, and the destination parameter indicates an identification number of the allocated register.