Patent ID: 11941246
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A data processing system comprising:
a memory system configured to provide a host with a memory map segment including a plurality of map pieces, each of the plurality of map pieces including a mapping relationship between a logical address and a physical address; and
the host configured to store the memory map segment, which is provided from the memory system, as a host map segment and converting a logical address into a physical address by using the host map segment,
wherein the memory system is further configured to:
store, in a map cache, one or more changed map pieces among the plurality of map pieces,
insert the changed map pieces in a response to a first command of the host, and
provide the host with the response,
wherein the host is further configured to update the host map segment based on the changed map pieces provided through the response, and
wherein, when a read command from the host includes a logical address and a physical address, the memory system is further suitable for accessing a memory device by selectively using the physical address included in the read command according to whether the logical address included in the read command is stored in the map cache,
wherein the host includes a slot configured to queue the first command,
wherein the host is further configured to:
remove the first command from the slot after the updating of the host map segment,
queue a second command in the slot, and
provide the memory system with a doorbell signal indicating the slot, and
wherein the memory system is further configured to:
store identification of the slot, and
detect completion of the updating of the host map segment by receiving the doorbell signal.