Patent ID: 11915980
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 17:
18. A method comprising:
providing a first gate structure disposed on a fin structure, wherein the fin structure is at least partially embedded within a dielectric isolation structure and a first interlayer dielectric layer is disposed on the first gate structure;
forming a patterned material layer over the first gate structure and the first interlayer dielectric layer, wherein the patterned material layer defines an opening such that the first gate structure and the first interlayer dielectric layer are exposed by the opening;
removing a portion of the first gate structure and a portion of the first interlayer dielectric layer through the opening to thereby form a trench exposing the dielectric isolation structure, wherein the removing of the portion of the first gate structure and the portion of the first interlayer dielectric layer includes forming a protection layer directly on the portion of the first interlayer dielectric layer prior to the removing of the portion of the first gate structure and the portion of the first interlayer dielectric layer, wherein the removing of the portion of the first gate structure and the portion of the first interlayer dielectric layer includes removing by a plurality of etching cycles that occurs through the opening defined by the patterned material layer, and wherein at least one cycle of the plurality of etching cycles includes forming the protection layer directly on the portion of the first interlayer dielectric layer prior to performing the at least one cycle of the plurality of etching cycles; and
forming a second interlayer dielectric layer in the trench directly on the dielectric isolation structure.