Patent ID: 11934834
Assignee: AMPERE COMPUTING LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 18:
19. A non-transitory computer-readable medium having stored thereon computer executable instructions which, when executed by a processor, cause the processor to:
establish a first scheduler entry of a plurality of scheduler entries, the first scheduler entry comprising first operation source parent information;
provide the first operation source parent information to a parent selection circuit;
select a compare source parent from a plurality of source parents based on the first operation source parent information, wherein each of the plurality of source parents is associated with an execution pipeline of a plurality of execution pipelines; and
perform a dependency comparison associated with the first scheduler entry using the compare source parent;
wherein the computer executable instructions cause the processor to perform the dependency comparison by causing the processor to:
select, using the first operation source parent information, an associated execution pipeline from among the plurality of execution pipelines on which to perform the dependency comparison;
select, using the first operation source parent information, information from the associated execution pipeline; and
perform the dependency comparison only against the information from the associated execution pipeline.