Patent ID: 11934830
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. A non-transitory machine-readable medium containing instructions that, when performed by a processor, cause the performance of operations comprising:
fetching an instruction from a code storage by a fetch circuit, the instruction comprising an opcode, at least one source memory location identifier, a destination register identifier, a data readiness indicator identifying at least one data access condition, and a data readiness mask;
decoding the fetched instruction by a decode circuit; and
executing the decoded instruction by an execution circuit to, for each data element of the identified source memory location,
determine whether the data access condition for that data element is satisfied, and
in response to determining that the data access condition for the data element is not satisfied,
generating a prefetch request for the data element, and
setting a value in a corresponding data element position of the identified destination register, and
setting a masked value in a corresponding data element position of the data readiness mask.