Patent ID: 11942954
Assignee: GIGADEVICE SEMICONDUCTOR (SHANGHAI) INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. Delay locked loop (DLL) circuitry system, comprising:
a DLL circuit configured to receive an external clock signal and generate an internal clock signal delayed relative to the external clock signal and lock the internal clock signal in phase with the external clock signal; and
a timer unit coupled to an enable terminal of the DLL circuit and configured to be enabled in response to a signal instructing entry into a low power consumption mode from outside of the DLL circuitry system and generate, based on the signal instructing entry into the low power consumption mode and a predefined timer condition, a DLL enable signal which enables the DLL circuit to allow the DLL circuit to relock the internal clock signal in phase with the external clock signal.