Patent ID: 11875874
Assignee: GROQ, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 5:
6. The memory of claim 5, wherein the first access circuit is further configured to:
in response to both the first and second output read ports of the first access circuit receiving read requests to read data of the first subset of data during a same time period, provide data from the first memory sub-structure to satisfy the read request from the first output read port, and reconstruct, using the second difference circuit connected to the second output read port, data of the first subset of data to satisfy the read request from the second output read port; and
in response to the second output read port of the first access circuit receiving a read request to read data of the first subset of data without a concurrent read request to read data of the first subset of data from the first output read port of the first access circuit, provide data from the first memory sub-structure to satisfy the read request form the second output read port.