Patent ID: 11894095
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. A semiconductor memory device comprising:
a plurality of data latch circuits that are used for input and output of data between a sense amplifier circuit and an input/output circuit;
a first data wiring that is connected between the sense amplifier circuit and the plurality of data latch circuits; and
second data wirings, each of which is connected between one of the data latch circuits and the input/output circuit, wherein
each of the data latch circuits includes
a data storage unit that temporarily stores data input and output between the sense amplifier circuit and the input/output circuit, and
at least two N-channel type MOS transistors and at least one P-channel type MOS transistor provided between the data storage unit and a corresponding one of the second data wirings, and

a common signal line is connected to gates of the at least two N-channel type MOS transistors.