Patent ID: 11924008
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Digital communication (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 12:
13. An equalizer circuit comprising:
a decision feedback equalizer (DFE) configured to receive a received signal from the outside and to output an equalization signal by removing an intersymbol interference (ISI) from the received signal based on DFE coefficients;
a deserializer configured to generate a bit stream including first to N-th bits and an error bit stream including first to N-th bits based on the equalization signal;
a flip-flop configured to adjust an output timing of each of the first to N-th bits of the error bit stream;
a compensation circuit configured to generate a compensation stream including first to 2M-th compensation values based on the bit stream; and
a DFE coefficient calculator configured to generate the DFE coefficients based on the compensation stream and the bit stream from the compensation circuit and the error bit stream from the flip-flop and to output the DFE coefficients to the DFE,
wherein the compensation circuit includes:
a data analyzer configured to:
count a number of times of coincidence of each of first to 2M-th patterns from the bit stream, a size of each pattern of the first to 2M-th patterns being M bits, and
generate a pattern stream including first to 2M-th count values, each count value of the first to 2M-th count values corresponding to a result of counting a number of times of coincidence of a corresponding pattern of the first to 2M-th patterns;
a pattern table configured to store the pattern stream; and
a compensation calculator configured to:
determine the first to 2M-th compensation values based on the pattern stream from the data analyzer such that results of multiplying the first to 2M-th count values by the first to 2M-th compensation values, respectively, are even, and
wherein “N” is a natural number, and “M” is a natural number smaller than “N”.