Patent ID: 11862512
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A method of forming a semiconductor package, comprising:
providing a substrate having contacts therein and a dielectric material layer thereon;
forming a dual damascene opening with via openings and a trench opening disposed on and communicated with the via openings in the dielectric material layer, wherein a slant sidewall of each of the via openings is connected with a slant sidewall of the trench opening, and the slant sidewall of each of the via openings has a same slope as the slant sidewall of the trench opening, and the slant sidewall of each of the via openings is aligned with the slant sidewall of the trench opening;
forming a seed metallic layer over the dual damascene opening and over the dielectric material layer; and
forming a metallic pattern filled in the dual damascene opening and electrically connected with the contacts, wherein the metallic pattern in the dual damascene opening includes via portions located within the via openings and a routing line portion located within the trench opening, the routing line portion is laterally and directly connected with the via portions, and no interface is between the via portions and the routing line portion, and a top surface of the metallic pattern is lower than a top surface of the dielectric material layer, a rounded corner is between the top surface of the dielectric material layer and a slant sidewall of the dielectric material layer, and the slant sidewall of the dielectric material layer is in contact with the slant sidewall of the trench opening.