Patent ID: 11917809
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 18:
19. An apparatus, comprising:
a set of first memory cells in a first level above a semiconductor substrate;
a set of second memory cells in the first level above the semiconductor substrate;
circuitry of a second level operable for accessing the set of first memory cells and the set of second memory cells; and
a controller configured to:
identify a row of first memory cells of the set of first memory cells for an access operation; and
couple the row of first memory cells with the circuitry of the second level based at least in part on the identifying, wherein coupling the row of first memory cells with the circuitry of the second level comprises:
coupling respective storage elements of the row of memory cells with a set of access lines above the semiconductor substrate based at least in part on activating a plurality of first transistors of the first level; and
coupling the set of access lines with the circuitry of the second level based at least in part on activating a plurality of second transistors of the first level.