Patent ID: 11901435
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A method for forming a semiconductor structure, the method comprising:
forming a gate structure over a substrate;
depositing a sidewall spacer layer covering the substrate and lining sidewalls of the gate structure;
performing an etching process on the sidewall spacer layer to form a sidewall spacer on the sidewalls of the gate structure, wherein an etch rate of the sidewall spacer layer during the etching process is greater than 1 angstroms/minute and less than about 8 angstroms/minute and is performed at a temperature within a range of about 600 to 650 degrees Celsius; and
forming a pair of source/drain regions within the substrate on opposing sides of the gate structure.