Patent ID: 11941253
Assignee: EMC IP HOLDING COMPANY LLC
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 12:
13. A computing system comprising:
a memory; and
a processor configured to sense a failure within a system within a computing device, wherein the system includes a cache memory system and a vaulted memory comprising a random access memory (RAM) having a plurality of independent persistent areas, wherein the processor is further configured to provide a primary node and a secondary node, wherein the primary node occupies a first independent persistent area of the RAM of the vaulted memory and the secondary node occupies a second independent persistent area of the RAM of the vaulted memory, and wherein the processor is further configured to write data within the vaulted memory to a persistent media using an iterator, wherein the data includes at least one dirty page, and wherein writing data within the vaulted memory to the persistent media using the iterator includes:
flushing the at least one dirty page to the persistent media,
determining whether at least one of the plurality of components within the vaulted memory includes a bitmap,
in response to determining the at least one of the plurality of components within the vaulted memory includes the bitmap, determining if the bitmap is associated with a dirty page, and
iterating, in response to determining the bitmap is associated with the dirty page, the dirty page, wherein iterating the dirty page includes returning a size and an address of the bitmap to the vaulted memory.