Patent ID: 11955204
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A memory device comprising:
a memory array comprising a plurality of memory planes; and
control logic, operatively coupled with the memory array, wherein the control logic is to perform operations comprising:
receiving a plurality of memory access commands, wherein each memory access command is associated with a different respective memory plane of the plurality of memory planes and is associated with a different memory access operation type;
responsive to receiving the plurality of memory access commands, configuring, for concurrent memory access operations, a plurality of power circuits corresponding to the plurality of memory planes; and
performing, in parallel and based on the configured plurality of power circuits, a first memory access operation having a first memory access operation type on a first memory plane of the plurality of memory planes and a second memory access operation having a second memory access operation type on a second memory plane of the plurality of memory planes.