Patent ID: 11882692
Assignee: SK HYNIX INC.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 10:
11. A semiconductor device, comprising:
a substrate including an active area;
a first trench and a second trench spaced apart from each other and extending in the substrate;
a bit line contact plug positioned between the first trench and the second trench and formed in the substrate;
a first gate insulation layer formed on a surface of the first trench and a side wall of the bit line contact plug;
a second gate insulation layer formed on a surface of the second trench and another side wall of the bit line contact plug;
a first gate electrode partially filling the first trench, on the first gate insulation layer; and
a second gate electrode partially filling the second trench, on the second gate insulation layer,
wherein the first gate insulation layer includes an oxide of a side wall of the bit line contact plug,
wherein the second gate insulation layer includes an oxide of another side wall of the bit line contact plug, and
wherein top surfaces of the first and second gate insulation layer are positioned at the same level as a top surface of the bit line contact plug, respectively.