Patent ID: 11923472
Assignee: THE UNITED STATES OF AMERICA AS REPRESENTED BY THE SECRETARY OF THE ARMY
Field: Semiconductors (Electrical engineering)
Classification: CPC H  Y | IPC H

Claim 17:
18. A method of fabricating a deformable array of semiconductor devices according to claim 16, the method comprising:
providing a substrate comprising a SiO2 layer over a Si layer;
etching the SiO2 layer to form a SiO2 hard mask that defines an auxetic geometry comprising the islands and the serpentine interconnects between the islands;
etching through the Si layer to define the islands and serpentine interconnects in accordance with the hard mask on the Si so that the array exhibits a negative Poisson's ratio when loaded under tensile strain; and
depositing at least one material onto the etched substrate to form at least one semiconductor device on the islands.