Patent ID: 11972818
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 18:
19. The method as set forth in claim 15, wherein as part of the verify level trimming process, the method further includes the steps of:
programming the memory cells connected to the sample group of the plurality of word lines in at least one sample block with a predetermined test data pattern;
applying the predetermined refresh read voltage to the selected ones of the plurality of word lines in the at least one sample block for the predetermined period of time at the predetermined intervals of time to maintain the memory cells in the second read condition during the refresh read operation;
reading an obtained data test pattern from the memory cells of the at least one sample block after the predetermined sample test time; and
counting the quantities of the memory cells having threshold voltages crossing over between the plurality of data states in the plurality of crossovers and the total failure bit count based on a comparison of the obtained data test pattern read from the memory cells of the at least one sample block to the predetermined test data pattern.