Patent ID: 11921635
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A heterogeneous processing system comprising:
a graphics processor including a first cache memory and a first circuit, the first circuit to perform virtual to physical memory address translation and manage cache coherency metadata;
an application processor including a second cache memory and a second circuit, the second circuit to perform virtual to physical memory address translation and manage cache coherency metadata;
a third cache memory coupled to the graphics processor and the application processor, the third cache memory to cache data in a block of memory shared between the graphics processor and the application processor, wherein the graphics processor and the application processor have a unified virtual memory system including a common virtual memory address space in which a complete virtual address space of the graphics processor is shared with the application processor; and
system memory coupled to the third cache memory, the system memory to store a page table including a virtual to physical memory address mapping for the common virtual memory address space and cache coherency metadata, the cache coherency metadata stored contiguously with the virtual to physical memory address mapping, the cache coherency metadata including coherency ownership information for one or more cache lines associated with the block of memory; and
wherein in association with a write request to the block of memory by the application processor or the graphics processor, the first circuit or the second circuit is to:
perform a virtual to physical memory address translation for a virtual memory address of the block of memory based on an entry in the virtual to physical memory address mapping; and
concurrently with the virtual to physical memory address translation, determine coherency ownership associated with the block of memory, the coherency ownership and the entry in the virtual to physical memory address mapping determined via a single read operation that is performed based on the virtual memory address of the block of memory; and
transfer the coherency ownership associated with the block of memory between the graphics processor and the application processor, wherein the first circuit and the second circuit are to transfer the coherency ownership via a response sent between the graphics processor and application processor.