Patent ID: 11942928
Assignee: LAPIS TECHNOLOGY CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 5:
6. A power-on reset circuit comprising:
a first transistor having a first conductive type, the first transistor including a first terminal connected to a first power supply and is diode-connected;
a second transistor having a second conductive type which is different from the first conductive type, the second transistor including a first terminal connected to a second power supply different from the first power supply, and including a control terminal connected to a control terminal of the first transistor;
a third transistor having the second conductive type and receiving a predetermined voltage at a control terminal, the third transistor including a first terminal connected to the second power supply and a second terminal connected to the control terminal of the first transistor;
a fourth transistor including a first terminal connected to the first power supply and a second terminal connected to a second terminal of the second transistor and
a current mirror circuit to which the predetermined voltage is supplied to cause a first current to flow, wherein the current mirror circuit transmits a second current based on the first current to another transistor,
wherein a reset signal is switched when a voltage of the first power supply is equal to or greater than a sum of a threshold voltage of the first transistor and a threshold voltage of the second transistor,
wherein the power supply voltage monitoring circuit includes a first power supply voltage monitoring circuit including the first and third transistors, and a second power supply voltage monitoring circuit including the second and fourth transistors,
wherein the first power supply voltage monitoring circuit receives the second current from the current mirror circuit and causes a third current to flow to the first transistor, and
wherein the second power supply voltage monitoring circuit receives the second current from the current mirror circuit and causes a fourth current to flow to the second transistor.