Patent ID: 11948946
Assignee: BEIHAI HKC OPTOELECTRONICS TECHNOLOGY CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 8:
9. A method for manufacturing an array substrate, comprising:
forming on a substrate a first gate and a second gate spaced apart from the first gate;
forming on the substrate a gate insulation layer, the gate insulation layer covering the first gate and the second gate;
forming on the gate insulation layer an active layer to-be-processed;
forming on the active layer to-be-processed a first photoresist layer to-be-processed;
exposing and developing the first photoresist layer to-be-processed to form a first photoresist layer;
etching the active layer to-be-processed to form a first active layer and a second active layer, part of the first photoresist layer being on a side surface of the first active layer away from the gate insulation layer, and the rest of the first photoresist layer being on a side surface of the second active layer away from the gate insulation layer;
forming on the gate insulation layer a second photoresist layer to-be-processed, the second photoresist layer to-be-processed being connected with the first photoresist layer;
exposing and developing the second photoresist layer to-be-processed to form a second photoresist layer;
etching the gate insulation layer to define a through hole, the through hole facing the second gate;
removing the first photoresist layer and the second photoresist layer; and
forming on the gate insulation layer a first source, a first drain, a second source and a second drain, one of the first source or the first drain being connected with the second gate through the through hole.