Patent ID: 11880311
Assignee: REALTEK SEMICONDUCTOR CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 7:
8. A data transmission system, comprising:
a master device; and
an asynchronous FIFO memory, coupled between the master device and a slave device and comprising a plurality of entries for buffering data written by the master device,
wherein at least one of the master device and the asynchronous FIFO memory determines a current depth of the asynchronous FIFO memory according to at least one of a clock ratio, a burst length and a continuous transmission length, wherein the current depth is smaller than or equal to a total number of the entries and the clock ratio is a ratio of a frequency of a first clock signal a used by the master device to a frequency of a second clock signal used by the slave device, and
the asynchronous FIFO memory configures one or more entries to be used according to the current depth and controls a plurality of FIFO clock signals according to the current depth, wherein one FIFO clock signal corresponds to one entry, and one or more FIFO clock signals corresponding to one or more entries that are not configured according to the current depth are disabled.