Patent ID: 11861829
Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. The apparatus according to claim 8, wherein:
the N basic feature maps comprise A low-level feature maps and B high-level feature maps, both A and B being integers greater than 1; and
when the processor is configured to cause the apparatus to merge the features of the N basic feature maps of the slice by the deep neural network, to obtain the M enhanced feature maps of the slice, the processor is configured to cause the apparatus to:
perform convolution processing on an ith low-level feature map of the slice,
upsample a jth high-level feature map of the slice, and
add a feature map obtained by the convolution processing on the ith low-level feature map and a feature map obtained by the upsampling of the jth high-level feature map, to obtain a kth enhanced feature map of the slice,
wherein 1≤i<A, 1<j≤B, 1<k≤M, and i, j, and k are all integers.