Patent ID: 11963363
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A memory device, comprising:
a word line;
memory cells embedded in and penetrating through the word line;
source lines electrically connected the memory cells; and
bit lines electrically connected the memory cells, wherein each of the memory cells comprises:
a source pillar embedded in and penetrating through the word line;
a drain pillar embedded in and penetrating through the word line;
an isolation structure embedded in and penetrating through the word line, wherein the source pillar and the drain pillar are spaced apart by the isolation structure, the source pillar is electrically connected to one of the source lines, and the drain pillar is electrically connected to one of the bit lines; and
a channel layer and a charge storage dielectric layer, wherein the channel layer and the charge storage dielectric layer laterally surround the source pillar, the drain pillar and the isolation structure, and the channel layer is spaced apart from the word line by the charge storage dielectric layer,
wherein the perimeter of each of the source pillar and the drain pillar is enclosed by the isolation structure and the channel layer, and
wherein the isolation structure comprises a single material.