Patent ID: 11966748
Assignee: ATI TECHNOLOGIES ULC
Field: Digital communication (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 14:
15. A computing system comprising:
one or more processors; and
memory that stores instructions that, when executed by the one or more processors, cause:
in response to a request to adjust functionality of a boot-time feature, writing boot configuration information to persistent storage, the boot configuration information indicating the requested adjustment to the functionality of the boot-time feature;
after writing the boot configuration information to the persistent storage, a bootloader process implementing a boot sequence;
while implementing the boot sequence:
the bootloader process having at least two boot stages and reading the boot configuration information from persistent storage, and
the bootloader process implementing the requested adjustment to the functionality of the boot-time feature based on the boot configuration information, where one or more aspects of a first boot-time feature are incompatible with a second boot-time feature, wherein the first boot-time feature is enabled during a first boot stage and the first boot-time feature is disabled during a second boot stage.