Patent ID: 11893240
Assignee: QUALCOMM INCORPORATED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A pseudo channel based memory system, comprising:
a first pseudo channel selection device configured to selectively communicatively connect one of a plurality of pseudo channels to a first input/output (IO); and
a second pseudo channel selection device configured to selectively communicatively connect one of the plurality of pseudo channels to a second IO,
wherein the first pseudo channel selection device and the second pseudo channel selection device are operable to communicatively connect a first pseudo channel of the plurality of pseudo channels to the first IO and to the second IO concurrently in a first operation mode in response to the pseudo channel based memory system receiving a mode register write command configured to cause the pseudo channel based memory system to handle a successive memory access command as a low latency type memory access command and in response to the pseudo channel based memory system receiving a successive memory access command targeting the first pseudo channel.