Patent ID: 11930640
Assignee: SK HYNIX INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 11:
12. A semiconductor device comprising:
a logic device layer and a memory device layer stacked on the logic device layer,
wherein the logic device layer comprises:
a substrate having a cell area and a via area;
a logic interconnection disposed over the substrate;
a common source region disposed over the logic interconnection in the cell area;
a lower via plug in contact with the logic interconnection in the via area; and
a support pattern in contact with a side surface of the lower via plug in the via area,
wherein the memory device layer comprises:
a word line stack disposed on the common source region in the cell area, the word line stack including first insulating layers and word lines alternately stacked;
a plurality of vertical channel pillars penetrating the word line stack in a vertical direction to be commonly connected to the common source region in the cell area;
a dielectric layer stack in the via area;
an upper peripheral contact plug vertically penetrating the dielectric layer stack to be vertically aligned with the lower via plug in the via area,
wherein top surfaces of the lower via plug and the support pattern are co-planar,
wherein the lower via plug has a height greater than that of the support pattern in the vertical direction, and
wherein the support pattern is a conductor; and
wherein the semiconductor device further comprises:
a plurality of support patterns arranged to be spaced apart from each other in a horizontal direction by a portion of the lower insulating layer,
a plurality of lower via plugs, each of the plurality of lower via plugs in directly contact with each of the plurality of support patterns, respectively; and
wherein the support pattern has a pair of segments shaped to contact at least two side surfaces of the lower via plug having a plurality of side surfaces.