Patent ID: 11862723
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. The manufacturing method of claim 4, wherein the step of forming the annular gate dielectric layer on the sidewall of the through hole comprises the steps of:
forming a gate dielectric layer film in the through hole, with the gate dielectric layer film covering the sidewall of the through hole and a bottom wall of the through hole;
forming a protective layer film on the gate dielectric layer film; and
removing the gate dielectric layer film and the protective layer film on the bottom wall by an etching process to provide an opening exposing the bit line in the through hole; and
wherein a distance between a bottom of the opening and a top of the bit line is greater than or equal to 5 nm and less than or equal to 8 nm; and a distance between the bottom of the through hole and the top of the bit line is greater than or equal to 3 nm and less than or equal to 5 nm.