Patent ID: 11871552
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 16:
17. A memory device comprising:
a first fin-type field effect transistor having a source/drain region;
a contact above and physically interfacing the source/drain region;
a first via having an elongated oval shaped bottom surface and an elongated oval shaped top surface, wherein the elongated oval shaped bottom surface of the first via interfaces the contact and the elongated oval shaped top surface of the first via interfaces a first Vss node conductive component;
a second via having an elongated oval shaped bottom surface and an elongated oval shaped top surface, wherein the elongated oval shaped bottom surface of the second via interfaces the first Vss node conductive component;
a second Vss node conductive component over the second via, wherein the elongated oval shaped top surface of the second via interfaces the second Vss node conductive component; and
a Vss line coupled to the second Vss node conductive component by a third via extending from the second Vss node conductive component to the Vss line.