Patent ID: 11862248
Assignee: KIOXIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 7:
8. The semiconductor storage device according to claim 1, further comprising:
a third memory cell electrically connected to a third bit line and the first word line, the third bit line being between the first bit line and the second bit line; and
a fourth memory cell electrically connected to a fourth bit line and the first word line, the second bit line being between the third bit line and the fourth bit line, wherein
during the reading operation to read the page of the memory cells, while the first memory cell is selected as the read target during the first time period, the first circuit supplies:
a seventh voltage to the first bit line, and
an eighth voltage to the second bit line, the third bit line, and the fourth bit line, and

during the reading operation to read the page of the memory cells, while the second memory cell is selected as the read target during the second time period, the first circuit supplies:
the seventh voltage to the second bit line, and
the eighth voltage to the first bit line, the third bit line and the fourth bit line.