Patent ID: 11869623
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 2:
3. The device of claim 1, wherein the first latch circuit comprises:
a pull up circuit coupled to the first voltage terminal providing the third voltage, and configured to receive the first control signal;
a pull down circuit coupled to the second voltage terminal providing the second voltage, and configured to receive the second control signal; and
a fourth inverter and a fifth inverter that are coupled to the pull up circuit and the pull down circuit, wherein an input terminal of the fourth inverter, an output terminal of the fifth inverter and the first data line are coupled at a first node, and an output terminal of the fourth inverter, an input terminal of the fifth inverter, and the second data line are coupled at a second node.