Patent ID: 11933841
Assignee: SILICONCH SYSTEMS PVT LTD
Field: Measurement (Instruments)
Classification: CPC G | IPC G

Claim 10:
11. A method for testing a universal serial bus power delivery (USBPD) integrated circuit (IC), the method comprising:
sending custom USBPD signaling and USBPD packets on a configuration channel (CC) pin; configuring test modes by custom USBPD packets on the CC pin;
detecting a test mode entry based on received custom USBPD signaling data and packets on CC pin;
observing a test mode parameters on the CC pin;
causing an auto test mode exit or exiting with a short circuit or over current on the CC pin; and
applying design for testing (DFT) architecture in the testing of the USBPD integrated circuit for the DFT test mode entry detection through the custom USBPD signaling data and packets which are decoded,
wherein, during automatic test pattern generation (ATPG) test mode, the method further comprises:
configuring ATPG test mode parameters, the ATPG parameters comprising one or more of scan chain length, pattern count, launch on capture (LOC) or Launch-On Extra-Shift (LOES) mode select, and scan clock frequency with a USB PD packet on the CC pin;
triggering the ATPG test mode with the USBPD packet on the CC pin;
driving scan data-in and scan clock on single CC pin with Bi phase Mark Coding (BMC) encoding during scan shift-in phase of operation;
driving scan data-out and scan clock on single CC pin with BMC encoding during scan shift-out phase of operation;, automatically transitioning from scan shift-in to scan capture/reset, scan capture/reset to scan shift-out and scan shift-out to scan shift-in phases based on a programmed scan chain length and based on one or more of a pattern count without any external intervention in a first configuration and acknowledgement mechanism and the pattern count in a second configuration; and automatically resetting the design and exiting the scan test mode based on a programmed pattern count without any external intervention.