Patent ID: 11916055
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor structure, comprising:
a plurality of first logic cells each having a first cell height;
a plurality of second logic cells each having a second cell height that is different than the first cell height, wherein one of the plurality of second logic cells is immediately adjacent to one of the plurality of first logic cells; and
a plurality of metal lines parallel to each other in a metal layer, and comprising a first group of metal lines inside the plurality of first logic cells, a second group of metal lines inside the plurality of second logic cells and a third group of metal lines covering the plurality of first logic cells and the plurality of second logic cells,
wherein the plurality of first logic cells and the first group of metal lines are arranged in odd-numbered rows of a cell array, and the plurality of second logic cells and the second group of metal lines are arranged in even-numbered rows of the cell array,
wherein the third group of metal lines are wider than the first group of metal lines in the odd-numbered rows of the cell array, and the first group of metal lines in the odd-numbered rows of the cell array have a uniform first width, the second group of metal lines in the even-numbered rows of the cell array have a uniform second width, and the first width is greater than the second width, and
wherein the odd-numbered rows of the cell array are free of the plurality of second logic cells and the second group of metal lines, and the even-numbered rows of the cell array are free of the plurality of first logic cells and the first group of metal lines.