Patent ID: 11961585
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G  H

Claim 11:
12. A memory system, comprising:
a number of memory devices, each memory device of the number comprising:
a centralized command and address (CA) interface region including two or more CA input circuits operably coupled to two or more CA input signals, wherein at least two of the two or more CA input circuits are configured in CA pairs and each CA pair comprises:
a first CA input circuit including a first swap circuit for selecting a first CA output as a first internal CA signal when a control signal is negated; and
a second CA input circuit including a second swap circuit for selecting a second CA output as a second internal CA signal when the control signal is negated, the CA input circuit and the second CA input circuit arranged in a mirror relationship with the first swap circuit positioned adjacent the second swap circuit.