Patent ID: 11942140
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. The nonvolatile memory device of claim 1, further comprising:
first and second page buffers in the peripheral circuit region, the first and second page buffers connected to the first bit-line and the second bit-line respectively, and each configured to apply a bit-line voltage to each of the first and second bit-lines; and
a control circuit in the peripheral circuit region, the control circuit configured to control the bit-line voltage by:
applying a third voltage to at least one bit-line of the first and second bit-lines when the read operation is performed for only one of the first and second mats, and
applying a fourth voltage greater than the third voltage to the at least one bit-line of the first and second bit-lines when the read operation is performed for both of the first and second mats simultaneously.