Patent ID: 11955535
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A method, comprising:
receiving a workpiece, the workpiece comprising a channel region and a source/drain feature adjacent the channel region;
forming a dummy gate stack over the channel region;
forming a first spacer layer over the dummy gate stack and the source/drain feature;
forming a second spacer layer over the first spacer layer and the source/drain feature;
recessing the second spacer layer to expose top-facing surfaces of the first spacer layer while sidewalls of the first spacer layer remain covered by the second spacer layer;
depositing an etch stop layer on exposed surfaces of the first and second spacer layers;
depositing an interlayer dielectric layer over the etch stop layer;
planarizing the workpiece to expose the dummy gate stack such that top surfaces of the interlayer dielectric layer, the etch stop layer, the second spacer layer, and the first spacer layer are coplanar;
replacing the dummy gate stack with a gate structure;
recessing the gate structure, the first spacer layer, the second spacer layer, and the etch stop layer to form a contact opening; and
forming a dielectric feature in the contact opening to cover top surfaces of the recessed etch stop layer, second spacer layer, first spacer layer, and gate structure.