Patent ID: 11901306
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 14:
15. A semiconductor structure, comprising:
a semiconductor substrate;
a plurality of die areas on the semiconductor substrate, wherein the die areas are separated from each other by a plurality of scribe lines;
a plurality of first features in a first product region of each of the die areas and in a material layer;
a plurality of second features in a second product region of each of the die areas and in the material layer;
a plurality of third features in a third product region of each of the die areas and in the material layer;
a plurality of fourth features in a fourth product region of each of the die areas and in the material layer;
a plurality of fifth features in an alignment region surrounded by the first, second, third and fourth product regions of each of the die areas and in the material layer; and
a plurality of sixth features in each of the die areas and in the material layer, and the sixth features extend across two adjacent product regions of the first, second, third, and fourth product regions of each of the die areas,
wherein the sixth features are spaced apart from the first, second, third, and fourth features,
wherein the first product region is adjacent to and in physical contact with the second product region and the third product region, and the fourth product region is adjacent to and in physical contact with the second product region and the third product region,
wherein the alignment region is free of the first, second, third, and fourth features.