Patent ID: 11956970
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. An apparatus, comprising:
a tile of a memory array associated with a level above a substrate, the tile comprising:
a plurality of memory cells;
at least one plate node;
a plurality of digit lines each aligned along a first direction;
a plurality of word lines each aligned along a second direction and each operable to activate a plurality of first transistors of the tile to couple a respective storage element, of each memory cell of a respective row of memory cells, with a respective digit line of the plurality of digit lines; and
an activation line aligned along the second direction and operable to activate a plurality of second transistors of the tile, each second transistor of the plurality of second transistors operable to couple a respective digit line of a set of digit lines of the plurality of digit lines with a plate node of the at least one plate node.