Patent ID: 11868398
Assignee: TUBULAR LABS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. A system, comprising:
a processor configured to:
obtain a plurality of recorded video interactions;
obtain a plurality of recorded non-video interactions;
store, at a database, event data determined based at least in part on the plurality of recorded video interactions and the plurality of recorded non-video interactions, wherein the database comprises a plurality of storage nodes, wherein the non-video interactions comprise product interactions; and
determine a subset of the event data that comprises correlations between a video and non-video interactions, wherein to determine the subset of the event data that comprises correlations between the video and the non-video interactions comprises to:

receive a request to determine correlation values between a given set of products and video category identifiers (IDs);
search the database for a set of product event data that describes a set of panelist IDs' interactions with the given set of products, wherein data entries pertaining to a same panelist ID are stored contiguously on a single storage node from the plurality of storage nodes;
search the database for a set of video event data that describes the set of panelist IDs' interactions with the video category IDs;
for a video category ID included in the set of product event data, determine an overlap value comprising a number of distinct panelist IDs that have interacted with the given set of products and have performed video interactions associated with the video category ID within an attribution window;
determine a respective correlation value between the given set of products and the video category ID based at least in part on the overlap value; and
output, at a user interface, the video category ID in a ranked list of at least a portion of the video category IDs based on the respective correlation value between the given set of products and the video category ID; and

a memory coupled to the processor and configured to provide the processor with instructions.