Patent ID: 11972792
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An integrated circuit structure, comprising a first bank group and a second bank group, wherein the first bank group and the second bank group share one set of data read and write drive circuits, and the set of data read and write drive circuits comprises:
a read control module that is connected to a read data bus, a first read and write data bus, and a second read and write data bus, and the read control module is configured to read data of the first bank group onto the read data bus through the first read and write data bus, and to read data of the second bank group onto the read data bus through the second read and write data bus; and
a write control module that is connected to a write data bus, the first read and write data bus, and the second read and write data bus, and the write control module is configured to write data of the write data bus into the first bank group through the first read and write data bus, and to write data of the write data bus into the second bank group through the second read and write data bus;
wherein the read data bus comprises a plurality of read data lines, the write data bus comprises a plurality of write data lines, and the plurality of read data lines and the plurality of write data lines are arranged in an alternating manner.