Patent ID: 11875750
Assignee: HEFEI BOE JOINT TECHNOLOGY CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. The array substrate according to claim 14, wherein orthographic projections of the plurality of shift registers on the substrate are located in N rows of shift register regions, orthographic projections of the first group of shift registers on the substrate are located in X rows of shift register regions, orthographic projections of the second group of shift registers on the substrate are located in Y rows of shift register regions, orthographic projections of the third group of shift registers on the substrate are located in Z rows of shift register regions, and orthographic projections of the fourth group of shift registers on the substrate are located in (N−X−Y−Z) rows of shift register regions; and
the second portion of the first branch transmission section passes through the X rows of shift register regions;
the first portion of the second branch transmission section passes through the X rows of shift register regions, and the second portion of the second branch transmission section passes through the Y rows of shift register regions;
the first portion of the third branch transmission section passes through (X+Y) rows of shift register regions, and the second portion of the third branch transmission section passes through the Z rows of shift register regions;
the first portion of the fourth branch transmission section passes through (X+Y+Z) rows of shift register regions, and the second portion of the fourth branch transmission section passes through the (N−X−Y−Z) rows of shift register regions; and X, Y, Z, and N satisfy that:

X·C1=Y·C1+X·C2;

X·C1=Z·C1+(X+Y)·C2; and

X·C1=(N−X−Y−Z)·C1+(X+Y+Z)·C2;

wherein X, Y, Z, and N are all positive integers, and X, Y, and Z are all less than N;
C1 is a resistance-capacitance delay generated on a branch transmission section when the branch transmission section passes through a row of pixel region and a row of shift register region and is connected to a shift register; and
C2 is a resistance-capacitance delay generated on the branch transmission section when the branch transmission section passes through the row of pixel region and the row of shift register region.