Patent ID: 11922106
Assignee: SYNOPSYS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. A system comprising:
a memory storing instructions; and
a processor, coupled with the memory and to execute the instructions, the instructions when executed cause the processor to:
extract information associated with constraints and clock information from a file of a circuit design based on performing a lookahead scan comprising extracting one or more of the constraints and parasitics from the file,
determine a topological cone based on the extracted information for a partition of two or more partitions of the circuit design, the topological cone including objects associated with the partition,
associate a global identification and a local identification with an object included in multiple partitions,
associate the object with a primary partition,
assign the global identification to the object based on a sorting by names of objects of the circuit design, and
perform timing analysis on the partition based on the topological cone.