Patent ID: 11880332
Assignee: NUVOTON TECHNOLOGY CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 9:
10. A bus system, comprising:
a master device;
an enhanced serial peripheral interface (eSPI) bus; and
a plurality of slave devices electrically connected to the master device via the eSPI bus and comprising a first slave device and a plurality of second slave devices,
wherein each of the slave devices has a pin, and the pins of the slave devices are electrically connected together via a control line,
wherein the plurality of slave devices determine whether to communicate with the master device via the eSPI bus by driving the control line;
wherein after the first slave device provides a first clock signal to each of the second slave devices via the control line, each of the second slave devices is configured to control a phase difference between a second clock signal and the first clock signal;
wherein the phase differences between the second clock signals of the second slave devices and the first clock signal are different.