Patent ID: 11942326
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 19:
20. A process of forming an electronic device comprising:
forming a channel layer having a major surface and including AlzGa(1-z)N, where

0≤z≤0.1;

forming a barrier layer over the channel layer, wherein forming the barrier layer includes a III-N semiconductor base material;
forming a gate electrode layer over the barrier layer comprising:
forming a first film of the gate electrode layer, wherein the first film includes a first III-V material and has an exposed surface;
decomposing a Mg precursor to form a first set of Mg atoms within a first dopant region along the exposed surface of the first film;
forming a second film of the gate electrode layer after decomposing the Mg precursor, wherein the second film includes a second III-V material and has an exposed surface;
decomposing the Mg precursor to form a second set of Mg atoms within a second dopant region along the exposed surface of the second film; and
forming a third film of the gate electrode layer after decomposing the Mg precursor, wherein the third film includes a third III-V material;

merging the first dopant region and the second dopant region together to form a diffused doped region by diffusing Mg atoms from each of the first set of Mg atoms and the second set of Mg atoms;
patterning the gate electrode layer to form a gate electrode; and
forming a gate interconnect that contacts the gate electrode.