Patent ID: 11899982
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 14:
15. An apparatus, comprising:
a memory array;
circuitry operable to receive a command; and
a decoder coupled with the circuitry and the memory array and operable to decode the command received from the circuitry for execution by the apparatus,
wherein the apparatus is operable to:
determine that the command is absent from a set of valid commands based at least in part on evaluating the command and the set of valid commands;
set a mode register to a value indicating a safe mode of operation for the apparatus, the safe mode allowing execution of a read command and restricting execution of a write command; and
block, based at least in part on determining that the command is absent from the set of valid commands, the command from being decoded.