Patent ID: 11862512
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor package, comprising:
a substrate having contacts;
a dielectric layer disposed on the substrate;
a redistribution metallic pattern disposed on the substrate and disposed in the dielectric layer, wherein the redistribution metallic pattern includes via portions disposed on and connected with the contacts and a routing line portion disposed on the via portions, the routing line portion is laterally and directly connected with the via portions, the routing line portion and the via portions have slant sidewalls, the via portions and the routing line portion are continuous without interface, the slant sidewall of the routing line portion is aligned with the slant sidewall of each of the via portions, a top surface of the redistribution metallic pattern is lower than a top surface of the dielectric layer, a rounded corner is between the top surface of the dielectric layer and a slant sidewall of the dielectric layer, and the slant sidewall of the dielectric layer is in contact with the slant sidewall of the routing line portion; and
a seed metallic pattern sandwiched between the redistribution metallic pattern and the dielectric layer and between the via portions and the contacts.