Patent ID: 11961575
Assignee: SAMBANOVA SYSTEMS, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 3:
4. An integrated circuit (IC) comprising:
an input buffer enabled to load data during a first part of a clock period;
an array of storage elements, coupled to the input buffer, enabled to load data from the input buffer to a selected row in the array of storage elements in parallel during a second part of the clock period;
an output multiplexor, coupled to the array of storage elements, enabled to output data from a chosen row in the array of storage elements in parallel on a multi-line output data path;
a scan input for a scan chain;
an input multiplexor, coupled to the input buffer, a functional data path, the scan input, and a subset of lines of the multi-line output data path, and enabled to select between the functional data path and a set of inputs including the scan input and the subset of lines of the multi-line output data path as an input to the input buffer; and
a scan output for the scan chain coupled to a line of the output data path.