Patent ID: 11967622
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method comprising:
forming a metallic region in a first insulating layer;
forming a recess in the metallic region;
filling the recess with an inter block dielectric;
depositing a second insulating layer over the metallic region and the first insulating layer;
forming a first conductive structure extending through the second insulating layer and extending into the metallic region; and
forming a second conductive structure extending through the second insulating layer and extending into the metallic region, the first conductive structure being on a first side of the inter block dielectric, the second conductive structure being on a second side of the inter block dielectric, the second side being opposite the first side.