Patent ID: 11961472
Assignee: VIVO MOBILE COMMUNICATION CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 0:
1. A pixel driving circuit, comprising:
a pixel array comprising a plurality of pixel circuits (1), an RGBG pixel arrangement mode being adopted in the pixel array;
at least four gate lines (2), arranged in a first direction of the pixel array, one row of pixel circuits (1) being arranged between every two adjacent gate lines (2), and each row of pixel circuits (1) corresponding to one gate line (2);
at least eight data lines (3), arranged in a second direction perpendicular to the first direction and intersecting each gate line (2), each data line (3) being connected to pixel circuits (1) corresponding to sub-pixels of the same color in one column of pixel circuits (1); and
a demultiplexer circuit (4), connected to the data lines (3), and configured to control the data lines (3) to be in communication with an integrated circuit (IC) chip;
wherein the data lines (3) comprise first type data lines (31), second type data lines (32), and third type data lines (33);
each column of pixel circuits (1) is a circuit group, the circuit group corresponding to sub-pixels of the same color is a first circuit group, and the circuit group corresponding to sub-pixels of two colors is a second circuit group;
the first type data line (31) is connected to pixel circuits (1) corresponding to sub-pixels of a first color in the second circuit groups, and the second type data line (32) is connected to pixel circuits (1) corresponding to sub-pixels of a second color in the second circuit group; and
the third type data lines (33) are connected to the pixel circuits (1) in the first circuit group; and
wherein the demultiplexer circuit (4) comprises:
a first driving line (41), a second driving line (42) having a sequence opposite to that of the first driving line (41), at least four first switches (43), and at least four second switches (44), wherein
the first driving line (41) and the second driving line (42) are connected to the output terminal of the IC chip;
the first type data line (31) and one third type data line (33) in each first circuit group correspond to the first switch (43), and the second type data line (32) and another one third type data line (33) in each first circuit group correspond to the second switch (44);
a control terminal of the first switch (43) is connected to the first driving line (41) and is configured to allow communication between the first type data line (31) and a corresponding port data line and communication between a half of the third type data lines (33) and a corresponding port data line under the control of the first driving line (41);
a control terminal of the second switch (44) is connected to the second driving line (42) and is configured to allow communication between the second type data line (32) and a corresponding port data line and communication between a remaining half of the third type data lines (33) and a corresponding port data line under the control of the second driving line (42); and
each port data line is connected to the output terminal of the IC chip.