Patent ID: 11914900
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. A storage system comprising:
a memory;
a host interface;
a data path coupled with the memory and the host interface, wherein the data path comprises a direct memory access (DMA) controller; and
a processor coupled with data path, wherein the processor is configured to allow data associated with an in-progress read/write command to be processed by the data path even after the read/write command has been aborted in response to receiving an abort command from a host, wherein the abort command is required to be executed within a predetermined amount of time;
wherein the DMA controller is configured to, within the predetermined amount of time, identify that the read/write command was aborted and, in response, prevent the data being sent from the data path to the host or the memory.