Patent ID: 11961891
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 17:
18. A method, comprising:
forming a gate dielectric layer;
depositing a first work function metal layer over the gate dielectric layer;
depositing a fill-metal layer over the first work function metal layer, wherein the fill-metal layer defines a concave recess;
depositing a second work function metal layer in the concave recess;
etching the first work function metal layer, the fill-metal layer, and the second work function metal layer, wherein the fill-metal layer is etched at a first rate lower than that of the first work function metal layer and the second work function metal layer;
after the etching of the first work function metal layer, the fill-metal layer, and the second work function metal layer, forming a sacrificial layer over the first work function metal layer, the fill-metal layer, and the second work function metal layer, wherein a segment of the fill-metal layer protrudes vertically into the sacrificial layer;
etching the sacrificial layer, thereby forming an opening in the sacrificial layer that exposes side surfaces of the segment of the fill-metal layer; and
filling the opening with a conductive gate contact, wherein the segment of the fill-metal layer protrudes vertically into the conductive gate contact.