Patent ID: 11894072
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. The controller as set forth in claim 8, wherein the plurality of word lines comprises a total quantity of the plurality of word lines and the controller is further configured to instruct the memory apparatus to successively ramp voltages applied to each of the plurality of neighboring ones of the plurality of word lines from the read pass voltage to the reduced voltage beginning with ones of the plurality of neighboring ones of the plurality of word lines immediately adjacent the selected one of the plurality of word lines and progressing to others of the plurality of neighboring ones of the plurality of word lines disposed increasingly remotely from the selected one of the plurality of word lines during the at least one program-verify portion of the at least one program loop of the program operation until the voltages applied to each of the plurality of neighboring ones of the plurality of word lines have been ramped for a predetermined quantity of the plurality of word lines equal to the total quantity of the plurality of word lines.