Patent ID: 11955195
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H  B | IPC G

Claim 10:
11. A semiconductor memory device, comprising:
a memory cell region and a test region on a substrate;
a dummy pattern on the test region;
a first gate electrode that extends in a first direction on the dummy pattern;
a first common contact in contact with the dummy pattern and the first gate electrode;
a second gate electrode spaced apart from the first gate electrode in a second direction that intersects the first direction;
a second common contact spaced apart in the first direction from the first common contact; and
a first wiring layer provided on and coupled to the first and second common contacts,
wherein the first wiring layer comprises a first test line and a second test line that extend in the second direction, the first and second test lines being respectively electrically connected to the first and second common contacts,
wherein the first common contact comprises:
a first contact pattern in contact with the dummy pattern; and
a first gate contact electrically connected to the first gate electrode,

wherein the second common contact comprises:
a second contact pattern in contact with the dummy pattern; and
a second gate contact electrically connected to the second gate electrode, and

wherein the first gate contact comprises:
a first body part coupled to the first gate electrode; and
a first protrusion part that extends from the first body part and into the first contact pattern.