Patent ID: 11908546
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. A computing system comprising:
multiple memory devices configured as a system distributed shared memory for at least one host processing device of the computing system, wherein input/output (I/O) information is communicated among the multiple memory devices and the at least one host processing device using a packetized I/O protocol, and wherein each memory device includes:
multiple memory dies, wherein at least a portion of the memory of the memory dies is mapped to include at least a portion of a memory coherence directory; and
a logic base die excluding the at least one host processing device and including at least one memory controller configured to manage access to memory of the memory dies by the at least one host processing device, and logic circuitry configured to:
determine memory coherence state information for data stored in the memory of one or more of the memory dies;
store the memory coherence state information with the data in the memory dies;
grant access to the stored memory coherence state information in response to an atomic memory request, wherein the stored memory coherence information for a memory word is accessed by the logic circuitry remapping an address of the memory word received in the atomic memory request; and
include the memory coherence state information in a packetized message of the packetized I/O protocol sent in response to the atomic memory request.