Patent ID: 11868163
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H  Y | IPC G  H

Claim 19:
20. A system comprising:
an interconnection network;
a processor coupled to the interconnection network;
a synchronous network;
an asynchronous packet network; and
a plurality of configurable circuits arranged in an array, each configurable circuit comprising:
a configurable computation circuit;
a plurality of synchronous network inputs coupled to the synchronous network and to the configurable computation circuit;
a plurality of synchronous network outputs coupled to the synchronous network and to the configurable computation circuit;
an asynchronous network input queue coupled to the asynchronous packet network;
an asynchronous network output queue coupled to the asynchronous packet network; and
a control circuit coupled to the configurable computation circuit, the control circuit comprising:
a plurality of control registers configured to store a completion table having a plurality of thread identifiers, a corresponding data completion count for each thread identifier, for one or more current execution threads, of the plurality of thread identifiers, and a loop count of an active number of loop threads, the plurality of control registers further configured to store a thread identifier pool having a predetermined number of thread identifiers of the plurality of thread identifiers, and the plurality of control registers further configured to store, for each thread identifier for the one or more current execution threads, an identification of a last iteration or another thread identifier identifying a next execution thread for execution following execution of the current execution thread; and
a thread control circuit configured to self-schedule and queue a selected execution thread for execution when, for a thread identifier of the plurality of thread identifiers for the selected execution thread, the corresponding data completion count indicates completion of any data dependencies and the selected thread identifier is identified for the next execution thread, and wherein in response to receipt of an asynchronous packet network message returning a thread identifier of the plurality of thread identifiers to the thread identifier pool, the thread control circuit is further configured to decrement the loop count and, when the loop count reaches zero, to generate an asynchronous packet network completion message for transmission on the asynchronous packet network from the asynchronous network output queue.