Patent ID: 11955980
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A Phase Locked Loop (PLL) for reducing a coarse lock time, the PLL comprising:
a plurality of switchable voltage clamps configured to control voltage transients in an Automatic Bank Calibration (ABC) current Digital to Analog Converter (DAC), wherein the ABC current DAC comprises a plurality of Metal Oxide Silicon Field Effect Transistors (MOSFETs) and is configured to provide a bias current to a ring Current Controlled Oscillator (CCO) that is configured to generate a ring oscillator frequency;
a segmented loop filter capacitor configured to reduce a Low Pass Filter (LPF) settling time;
a bias generator configured to send a bias voltage to the plurality of MOSFETs and a bias current to the ABC current DAC, wherein the bias generator comprises an Operational Transconductance Amplifier (OTA); and
the ABC current DAC that is configured to generate at least one ABC code, wherein the at least one ABC code is generated based on a difference between the ring oscillator frequency and a target frequency to achieve coarse lock.