Patent ID: 11892972
Assignee: ARM LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 17:
18. A system comprising:
a multi-core processor having two or more processor cores; and
a control unit, configured to:
sequentially read a command stream comprising a plurality of commands including one or more wait commands and one or more setup commands, wherein each wait command has an associated state and one or more associated conditions;
issue each command that is encountered in the command stream, as the command stream is being sequentially read, to one or more cores of the multi-core processor, until a wait command is reached in the command stream;
when said wait command is reached, add said wait command to a wait queue and check the state of said wait command, and:
if said state is a blocking state, pause further processing of commands in the command stream until each of said wait command's associated conditions are met,
if said state is a non-blocking state, retrieve and process a next command in the command stream, wherein when said next command is a setup command, processing of said next command comprises sending said setup command to one or more cores of the multi-core processor for implementation, and
wherein when each of said wait command's associated conditions are met, said wait command is removed from the wait queue.