Patent ID: 11935920
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 15:
16. A device comprising:
an isolation region on a substrate;
a dielectric layer on the isolation region, the dielectric layer comprising a different dielectric material than the isolation region;
a first semiconductor fin extending above the dielectric layer;
a second semiconductor fin extending above the dielectric layer;
a gate structure on the first semiconductor fin, the second semiconductor fin, and the dielectric layer;
a first source/drain region adjacent the gate structure and in the first semiconductor fin;
a second source/drain region adjacent the gate structure and in the second semiconductor fin;
an inter-layer dielectric on the first source/drain region, the second source/drain region, and the dielectric layer, a top surface of the inter-layer dielectric being coplanar with a top surface of the gate structure;
a first source/drain contact extending through the inter-layer dielectric, the first source/drain contact connected to the first source/drain region;
a second source/drain contact extending through the inter-layer dielectric, the second source/drain contact connected to the second source/drain region; and
an isolation feature between the first source/drain contact and the second source/drain contact, the isolation feature comprising a liner layer and a void, the liner layer surrounding the void, the liner layer contacting the dielectric layer.