Patent ID: 11922533
Assignee: NVIDIA CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. The system of claim 10, wherein to adjust the delay, the one or more processing units further:
determine that the period of time between (i) processing of the second next frame at the execution stage preceding the execution stage of the plurality of execution stages associated with the largest weighted average execution time and (ii) processing of the first next frame at the execution stage of the plurality of execution stages associated with the largest weighted average execution time is less than zero; and
decrease the delay until the period of time between (i) processing of a second subsequent frame at the execution stage preceding the execution stage associated with the first largest weighted average execution time and (ii) processing of a first subsequent frame at the execution stage associated with the first largest weighted average execution time is equal to a predefined minimum value.