Patent ID: 11949007
Assignee: MITSUBISHI ELECTRIC CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. The semiconductor device according to claim 1, wherein
the two types of trap levels provided by the lattice defect in the second buffer layer include Trap A (photon energy: 1.0182 eV) and Trap B (photon energy: 1.0398 eV), and
with photoluminescence (PL) intensity of the Trap B defined as SPLB and PL intensity of the Trap A as SPLA, the ratio of the Trap B in the second buffer layer expressed by the following formula is in a range from 15 to 55%:

Trap B ratio ={SPLB/(SPLA+SPLB)}×100.