Patent ID: 11916127
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 1:
2. The method of claim 1, further comprising:
forming a lower inter-level dielectric (ILD) layer over the substrate;
forming a lower interconnect within the ILD layer;
forming a lower insulating structure over the lower ILD layer and the lower interconnect;
patterning the lower insulating structure to form an opening over the lower interconnect; and
wherein the non-oxidized first bottom electrode layer is formed over the lower insulating structure and the lower interconnect such that the non-oxidized first bottom electrode layer extends from an upper surface of the lower insulating structure, along sidewalls of the lower insulating structure defining the opening, to an upper surface of the lower interconnect.