Patent ID: 11935825
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 15:
16. An integrated circuit (IC) structure comprising:
a first dielectric;
a first fin structure that extends in a first direction and overlaps the first dielectric;
a first gate structure that overlies the first fin structure and extends in a second direction perpendicular to the first direction;
a second gate structure that overlies the first fin structure and extends in the second direction, wherein the first dielectric extends between the first and the second gate structures;
a contact that extends in the second direction between the first and second gate structures and overlaps with the first dielectric and the first fin structure, and with a second fin structure; and
an isolation layer that is stacked, at least partially, below the contact and is stacked directly over the first fin structure, the isolation layer configured to electrically isolate the contact from the first fin structure; and
a via stacked directly on the contact above the isolation layer and the first fin structure,
wherein
the contact has a first thickness that is reduced to a second thickness at a portion of the contact between the first fin structure and the via,
the first thickness includes a volume of the contact aligned with the isolation layer in the second direction and contacting the isolation layer along a plane perpendicular to the second direction, and
each of the first gate structure, the second gate structure, and the contact extends a same distance above the first dielectric in a third direction perpendicular to each of the first direction and the second direction.