Patent ID: 11914475
Assignee: INSTITUT MINES TELECOM
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 16:
17. An integrated circuit of ASIC or FPGA type comprising at least one device according to claim 15, and at least one device for coding data comprising means suitable for implementing the steps of a method for coding (k, r) data comprising:
dividing an initial datum a into k data blocks ai of the same size;
grouping the k data blocks into r−1 disconnected subsets Sj of data blocks;
generating, for each subset Sj, a linear function gj(a) defined as a linear combination of the data blocks assigned to said subset Sj; and
generating r parity functions comprising a primary parity function f0(a) as a linear combination of the k data blocks ai, and r−1 secondary parity functions, each secondary parity function fj(a) being defined as the sum of the primary parity function f0(a) and of a linear function gj(a).