Patent ID: 11955458
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A semiconductor package, comprising:
a logic die provided on an interposer substrate; and
a memory stack structure provided adjacent to the logic die,
wherein the memory stack structure comprises:
a buffer die provided on the interposer substrate; and
a plurality of memory dies stacked on the buffer die,
wherein the buffer die comprises an active layer, the active layer comprising:
a first active pattern provided on a first substrate;
a first device isolation layer provided on the first substrate and configured to define the first active pattern; and
a first gate electrode provided on a channel of the first active pattern,
wherein the channel of the first active pattern is positioned higher than an upper surface of the first device isolation layer.