Patent ID: 11956948
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A memory device, comprising:
a substrate;
first semiconductor layers and second semiconductor layers alternately stacked over the substrate, wherein a width of the first semiconductor layers is less than a width of the second semiconductor layers;
a metal gate structure crossing the first semiconductor layers and the second semiconductor layers;
gate spacers on opposite sidewalls of the metal gate structure, wherein along a direction vertical to a top surface of the substrate, the gate spacers overlap the first semiconductor layers and the second semiconductor layers;
source/drain structures on opposite sides of the metal gate structure, wherein each of the first semiconductor layers continuously extends from one of the source/drain structures to another one of the source/drain structures;
a word line electrically connected to the metal gate structure; and
a bit line electrically connected to one of the source/drain structures.