Patent ID: 11886874
Assignee: HITACHI ASTEMO, LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 3:
4. The arithmetic operation device according to claim 1, comprising
a reduced bit number calculator that calculates the third bit number on the basis of a size of the filter, a bit number of the target data, a bit number of the weight that is an element in the filter, and a bit number of an adder in the convolution arithmetic unit in a convolution layer to be subjected to a convolution arithmetic operation, and determines the first bit number and the second bit number on the basis of the third bit number,
wherein the bit reduction unit reduces a bit string corresponding to the first bit number determined by the reduced bit number calculator from the least significant bit of the target data, and reduces a bit string corresponding to the second bit number determined by the reduced bit number calculator from the least significant bit of the weight, and
the bit addition unit adds a bit string corresponding to the third bit number calculated by the reduced bit number calculator to the least significant bit of the convolution arithmetic operation result.