Patent ID: 11903192
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. An integrated chip, comprising:
a first gate structure disposed over a substrate and laterally surrounded by a first sidewall spacer, wherein the first gate structure protrudes outward from a top of the first sidewall spacer;
a second gate structure disposed over the substrate and laterally surrounded by a second sidewall spacer, wherein the second gate structure protrudes outward from a top of the second sidewall spacer;
a dielectric material disposed over the first gate structure and the second gate structure, wherein the dielectric material continuously extends from over the first sidewall spacer to directly between the first sidewall spacer and the second sidewall spacer;
an etch stop layer continuously extending from along a sidewall of the first sidewall spacer to along a sidewall of the first gate structure that is over the top of the first sidewall spacer, wherein interior sidewalls of the etch stop layer facing the first gate structure are steeper along the sidewall of the first gate structure than along the sidewall of the first sidewall spacer; and
a conductive contact extending from an upper surface of the dielectric material to contact the first gate structure, the conductive contact having a bottommost surface that contacts the first gate structure vertically above the top of the first sidewall spacer.