Patent ID: 11923042
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  Y | IPC G

Claim 8:
9. An apparatus comprising:
a host, and
a memory device connected to the host through a bus,
wherein the bus includes a clock bus portion configured to communicate a data clock controlling data write timing during a write operation executed by the memory device, and a read clock controlling data read timing during a read operation executed by the memory device, and
the memory device is configured to
perform first duty cycle monitoring that monitors a duty cycle of the data clock, generates a first result, and provides a timing-adjusted data clock,
perform second duty cycle monitoring that monitors a duty cycle of the read clock, generates a second result, and provides a timing-adjusted read clock,
calculate an offset of the read clock based on the timing-adjusted data clock, the result and the second result, and
correct a duty error of the read clock using a read clock offset code derived from the offset of the read clock.