Patent ID: 11861047
Assignee: CRYPTOGRAPHY RESEARCH, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 6:
7. A circuit comprising:
Boolean logic circuitry to receive cipher input values and masking values, wherein the Boolean logic circuitry outputs masked data values;
a mask generator circuit to determine a mask share, wherein a first portion of the mask share comprises a first number of zero-values and a second number of one-values, and a second portion of the mask share comprises the first number of one-values and the second number of zero-values;
a data store to store the mask share; and
masked gate logic circuitry coupled to the mask generator circuit, the Boolean logic circuitry, and the data store, wherein the masked gate logic circuitry comprises:
a first circuit to:
receive the masked data values from the Boolean logic circuitry;
receive the first portion of the mask share from the mask generator circuit; and
provide a first output;

a second circuit to:
receive the masked data values from the Boolean logic circuitry;
receive the second portion of the mask share from the mask generator circuit; and
provide a second output.