Patent ID: 11903193
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. A method of making a MOSFET device, the method comprising:
forming a first floating gate trench in a substrate;
forming a first tunnel dielectric layer on sidewalls of the first floating gate trench;
forming a first floating gate electrode in the first floating gate trench on the first tunnel dielectric layer;
forming a continuous control gate dielectric layer over a top surface of the floating gate electrode;
forming a control gate layer over a top surface of the control gate dielectric layer;
patterning the control gate layer and the continuous control gate dielectric layer, wherein patterned portions of the control gate layer and the continuous control gate dielectric layer comprise a first control gate electrode and a first control gate dielectric layer;
forming a first sidewall spacer on the first control gate dielectric layer and the first control gate electrode; and
forming a source region and drain region within an upper portion of the substrate, wherein a channel region continuously extends between the source region and the drain region underneath the first floating gate trench, a first p-n junction between the channel region and the source region has a first top edge that is aligned to, and adjoined to, a bottom edge a first outer sidewall of the first sidewall spacer, and a second p-n junction between the channel region and the drain region has a second top edge that is aligned to, and adjoined to, a bottom edge a second outer sidewall of the first sidewall spacer, wherein the source region and the drain region are laterally spaced from, and do not directly contact, the tunnel dielectric layer.