Patent ID: 11914253
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 15:
16. The manufacturing method according to claim 10, wherein the forming the passivation layer covering the thin film transistor, and the passivation layer being provided with a transferring through hole that exposes the pixel electrode and a drain electrode or a source electrode of the thin film transistor simultaneously comprises:
depositing a passivation film on a base on which the thin film transistor and the pixel electrode are formed;
coating a layer of photoresist on the passivation film, exposing and developing the photoresist using a monotone mask, forming an exposed region at a location of the transferring through hole without the photoresist, forming an unexposed region at other locations in which the photoresist is remained;
etching away the passivation film and the gate insulation layer in the fully exposed region by means of an etching process, forming the passivation layer in which the transferring through hole is formed and the transferring through hole exposing a drain electrode and a pixel electrode simultaneously,
wherein the transferring through hole comprises a first through hole portion and a second through hole portion, the passivation film in the first through hole portion is etched away and the drain electrode is exposed, and the passivation film and the gate insulation layer in the second through hole portion are etched away and the pixel electrode is exposed.