Patent ID: 11971827
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 16:
17. A system to authorize extended page table (EPT) mapping, the system comprising:
means for address width adjusting to:
identify a memory width value corresponding to a guest memory associated with a virtual machine (VM); and
generate an expanded emulated memory width value;

means for memory mirroring to:
generate a first guest physical address (GPA) range based on the memory width value; and
generate a second GPA range based on the expanded emulated memory width value; and

means for EPT generation to:
generate root paging structures of a first type of EPT with respective addresses within the first GPA range; and
generate root paging structures of a second type of EPT with respective addresses within (a) the first GPA range and (b) the second GPA range.