Patent ID: 11863189
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. An integrated circuit comprising:
an upper threshold circuit electrically connected to a first power domain and configured to set a logic level of a first enabling signal based on comparing an input voltage signal with an upper threshold voltage, wherein the upper threshold circuit includes a first tracker configured to receive the input voltage signal and an upper threshold detector configured to generate the first enabling signal in response to a first signal received from the first tracker;
a first switch electrically connected between an upper supply voltage and a buffer output node, wherein the first switch is configured to be controlled by the first enabling signal;
a lower threshold circuit electrically connected to a second power domain and configured to set a logic level of a second enabling signal based on comparing the input voltage signal with a lower threshold voltage, wherein the lower threshold circuit includes a second tracker configured to receive the input voltage signal and a lower threshold detector configured to generate the second enabling signal in response to a second signal received from the second tracker;
a second switch electrically connected between the buffer output node and a lower supply voltage wherein the second switch is configured to be controlled by the second enabling signal; and
a control circuit configured to change an output voltage signal from a first voltage level to a second voltage level when the logic level of the first enabling signal and the logic level of the second enabling signal are changed consecutively, the control circuit comprising a regenerative circuit having at least one switch, and wherein a connection state of the at least one switch between the buffer output node and one of the upper supply voltage or the lower supply voltage is configured to be controlled with a voltage on the buffer output node.