Patent ID: 11901036
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus comprising:
a bank including:
a first plurality of memory cells;
a second plurality of memory cells;
first sense amplifiers coupled to the first plurality of memory cells;
second sense amplifiers coupled to the second plurality of memory cells;
a first power control circuit coupled to the first sense amplifiers at a first common power supply node, the first power control circuit configured to receive a plurality of control signals; and
a second power control circuit coupled to the second sense amplifiers at a second common power supply node, the second power control circuit configured to receive the plurality of control signals,

wherein the first and second power control circuits are configured to have first and second drive strengths respectively responsive to activation of a control signal of the plurality of control signals,
wherein the control signal is activated earlier than activation of at least one other control sional of the plurality of control signals, and
wherein the first drive strength and the second drive strength are different from each other.