Patent ID: 11900503
Assignee: IMAGINATION TECHNOLOGIES LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 1:
2. The method of claim 1, wherein the first core comprises a slave unit, a first processing unit and a second processing unit, and wherein the method further comprises:
receiving, by the slave unit of the first core, the first trigger;
splitting, by the slave unit of the first core, the first trigger into at least a third trigger and a fourth trigger; wherein the third trigger comprises an indication of a third starting primitive in the element buffer and an instruction to render a third number of primitives starting from the third starting primitive, and the fourth trigger comprises an indication of a fourth starting primitive in the element buffer and an instruction to render a fourth number of primitives starting from the fourth starting primitive;
sending, by the slave unit of the first core, the third trigger to the first processing unit;
sending, by the slave unit of the first core, the fourth trigger to the second processing unit;
processing, by the first processing unit, the third trigger; and
processing, by the second processing unit, the fourth trigger.