Patent ID: 11877433
Assignee: FUJIAN JINHUA INTEGRATED CIRCUIT CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A storage node contact structure of a memory device, comprising:
a substrate having a dielectric layer, the dielectric comprises a recess;
a first tungsten metal layer disposed in the recess and filling the recess;
a spacer, disposed beside the first tungsten metal layer and directly contacts the first tungsten metal layer, wherein the spacer does not contact a bottom surface of the first tungsten metal layer directly;
a second tungsten metal layer disposed on the first tungsten metal layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD) method; and
an adhesive layer disposed between the first tungsten metal layer and the second tungsten metal layer, wherein a material of the adhesive layer comprises titanium or tantalum, wherein the adhesive layer directly contacts a top surface of the dielectric layer, wherein a width of the adhesive layer is same as a width of the second tungsten metal layer, and the width of the adhesive layer is larger than a width of the first tungsten metal layer.