Patent ID: 11968840
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 18:
19. A semiconductor structure comprising:
an active layer located over a substrate;
a first gate stack including a stack of a first gate dielectric and a first gate electrode and located on a first surface of the active layer;
a pair of first contact electrodes contacting peripheral portions of the first surface of the active layer and laterally spaced from each other along a first horizontal direction by the first gate electrode;
a second contact electrode contacting a second surface of the active layer that is vertically spaced from the first surface of the active layer; and
a pair of second gate stacks including a respective stack of a second gate dielectric and a second gate electrode and located on a respective peripheral portion of a second surface of the active layer and laterally spaced from each other along the first horizontal direction by the second contact electrode, wherein:
a top surface of the active layer comprises at least two first horizontal top surface segments that are vertically offset from at least one second horizontal top surface segment; and
a bottom surface of the active layer comprises at least two first horizontal bottom surface segments that are vertically offset from at least one second horizontal bottom surface segment.