Patent ID: 11894102
Assignee: SK HYNIX INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 6:
7. A semiconductor device, comprising:
a data pad and a data strobe pad;
a clock generation circuit configured to generate first to fourth write clock signals by dividing a write clock signal at a set ratio, the write clock signal received through the data strobe pad;
a first alignment circuit configured to align write data in response to the first to fourth write clock signals, the write data input through the data pad, and to transmit the first to fourth write clock signals and the write data through a first clock transmission path and a first data transmission path; and
first to fourth duty correction devices, each configured to receive the first to fourth write clock signals transferred through the first clock transmission path, to receive one of the first to fourth write clock signals as a reference clock signal and remaining ones of the first to fourth write clock signals as first to third divided clock signals alternatively according to phases of the first to fourth write clock signals, to detect a phase difference between the reference clock signal and the first to third divided clock signals, and to perform a duty correction operation on the reference clock signal.