Patent ID: 11881260
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 19:
20. A neuromorphic computing device comprising:
a first memory cell array including a plurality of resistive memory cells that are connected to a plurality of wordlines, a plurality of bitlines and a plurality of source lines;
a second memory cell array including a plurality of reference resistive memory cells and a plurality of offset resistors, the plurality of reference resistive memory cells being connected to a plurality of reference wordlines, a plurality of reference bitlines and a plurality of reference source lines;
a wordline driver configured to drive the plurality of wordlines such that such that at least one wordline among the plurality of wordlines is enabled based on element values of an input feature vector, and configured to drive the plurality of reference wordlines such that all of the plurality of reference wordlines are enabled;
an analog-to-digital converting circuit configured to convert a plurality of read currents into a plurality of digital signals based on a plurality of reference currents, the plurality of read currents being output from the first memory cell array through the plurality of bitlines or the plurality of source lines, the plurality of reference currents being output from the second memory cell array through the plurality of reference bitlines or the plurality of reference source lines; and
an adder circuit configured to generate output data by performing accumulation and summation operations based on the plurality of digital signals,
wherein each of the plurality of offset resistors is connected between a respective one of the plurality of reference bitlines and a respective one of the plurality of reference source lines,
wherein all of the plurality of offset resistors have the same resistance,
wherein the resistances of the plurality of offset resistors are determined based on a first resistance and a second resistance, or is obtained by performing a simulation based on a plurality of sample resistances associated with the plurality of reference currents, and
wherein the first resistance corresponds to a high resistance state of the plurality of reference resistive memory cells, and the second resistance corresponds to a low resistance state of the plurality of reference resistive memory cells.