Patent ID: 11871626
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 17:
18. The display panel according to claim 16, wherein the first gate driving sub-circuit comprises a second group of transistors, each of which comprising a second gate and a second active layer, wherein the second active layer comprises a third electrode area, a fourth electrode area, and a channel area located between the third area and the fourth area, the second group of transistors comprising:
a first transistor, wherein the second gate of the first transistor is electrically connected to a second clock signal line configured to provide a second clock signal, and the third electrode area of the first transistor serves as the input terminal;
a second transistor, wherein the second gate of the second transistor is electrically connected to the fourth electrode area of the first transistor, and the third electrode area of the second transistor is electrically connected to the second gate of the first transistor;
a third transistor, wherein the second gate of the third transistor is electrically connected to the second gate of the first transistor, the third electrode area of the third transistor is electrically connected to a second power signal line configured to receive a second power voltage, and the fourth electrode area of the third transistor is electrically connected to the fourth electrode area of the second transistor,
a sixth transistor, wherein the second gate of the sixth transistor is electrically connected to the fourth electrode area of the second transistor, the fourth electrode area of the third transistor and the first gate of the fourth transistor, and the third electrode area of the sixth transistor is electrically connected to the first electrode area of the fourth transistor;
a seventh transistor, wherein the second gate of the seventh transistor is electrically connected to the first electrode area of the fifth transistor, the third electrode area of the seventh transistor is electrically connected to the fourth electrode area of the sixth transistor, and the fourth electrode area of the seventh transistor is electrically connected to the second gate of the second transistor, and
an eighth transistor, wherein the second gate of the eighth transistor is electrically connected to the second power signal line, the third electrode area of the eighth transistor is electrically connected to the second gate of the second transistor, and the fourth electrode area of the eighth transistor is electrically connected to the first gate of the fifth transistor.