Patent ID: 11862588
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A device comprising:
a passivation layer on a semiconductor substrate;
a first redistribution line having a first via portion and a trace portion, the first via portion extending through the passivation layer, the trace portion disposed on and extending lengthwise along the passivation layer in a first direction of a top-down view;
a second redistribution line on and extending lengthwise along the passivation layer in the first direction of the top-down view;
a first dielectric layer on the first redistribution line, the second redistribution line, and the passivation layer; and
an under bump metallization having a bump portion and a second via portion, the bump portion disposed on and extending along the first dielectric layer, the bump portion overlapping the first redistribution line and the second redistribution line, the second via portion extending through the first dielectric layer to be physically and electrically coupled to the first redistribution line, a center of the first via portion laterally aligned with a center of the second via portion.