Patent ID: 11916121
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 12:
13. The semiconductor memory device of claim 11, further comprising an additional plurality of field effect transistors located on an additional insulating matrix layer that extends along the first direction and the second direction and spaced from the plurality of field effect transistors by the additional insulating matrix layer along the third direction, wherein each field effect transistor selected from the additional plurality of field effect transistors comprises:
a respective metal oxide semiconductor channel layer having a thickness along the third direction between a respective first major surface and a respective second major surface,
a respective drain region and a respective backside gate dielectric layer that are embedded in the additional insulating matrix layer and contact the respective first major surface of the respective metal oxide semiconductor channel layer,
a respective backside gate electrode embedded in the additional insulating matrix layer,
a respective first gate dielectric layer contacting a first portion of the respective second major surface of the respective metal oxide semiconductor channel layer, and
a respective first gate electrode located on the respective first gate dielectric layer and contacting a second portion of the respective second major surface of the respective metal oxide semiconductor channel layer.