Patent ID: 11888620
Assignee: INTEL CORPORATION
Field: Digital communication (Electrical engineering)
Classification: CPC H | IPC H

Claim 6:
7. The apparatus of claim 1 wherein the PPDU is a first PPDU, the MMPDU is a first MMPDU, and wherein the processing circuitry is further configured to:
in response to a timeout event, the timeout event indicating that an acknowledgement frame was not received from the second STA to acknowledge the first MMPDU,
encode a second MMPDU in a second PPDU, the second MMPDU comprising the sequence number and the address 1 field, the address 1 field indicating the address of the second STA, and a retry subfield, the retry subfield indicating the second MMPDU is a retransmission of the first MMPDU.