Patent ID: 11880597
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 4:
5. The read operation circuit according to claim 2, wherein the data selector comprises M data selection units, each of the M data selection units comprising:
a first inverter, an input terminal of the first inverter being configured to receive the inversion flag data through the inversion flag signal line;
a second inverter, an input terminal of the second inverter being configured to receive the current read data;
a first transmission gate, an input terminal of the first transmission gate being connected to an output terminal of the second inverter, an output terminal of the first transmission gate being connected to the global bus to output the global bus data, a negative control terminal of the first transmission gate being connected to an output terminal of the first inverter, and a positive control terminal of the first transmission gate being configured to receive the inversion flag data through the inversion flag signal line; and
a second transmission gate, an input terminal of the second transmission gate being configured to receive the current read data, an output terminal of the second transmission gate being connected to the global bus to output the global bus data, a negative control terminal of the second transmission gate being configured to receive the inversion flag data through the inversion flag signal line, and a positive control terminal of the second transmission gate being connected to the output terminal of the first inverter.