Patent ID: 11903208
Assignee: SK HYNIX INC.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 0:
1. A method of manufacturing a semiconductor memory device, the method comprising:
forming a lower stack structure including a first semiconductor layer and a sacrificial layer which is disposed over the first semiconductor layer;
forming a channel layer extending from an inside of the first semiconductor layer to pass through the sacrificial layer and having a sidewall and a bottom surface covered by a memory layer, wherein the channel layer protrudes farther than the lower stack structure;
forming a gate stack structure on the lower stack structure to surround the channel layer;
removing the sacrificial layer to expose a part of the memory layer between the gate stack structure and the first semiconductor layer;
removing the part of the memory layer to separate the memory layer into a first memory pattern between the gate stack structure and the channel layer and a second memory pattern between the first semiconductor layer and the channel layer; and
replacing a part of the channel layer exposed between the first memory pattern and the second memory pattern by a doped semiconductor pattern.