Patent ID: 11921578
Assignee: SK HYNIX INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 8:
9. The semiconductor device of claim 7, wherein the refresh control circuit includes:
a refresh address generation circuit configured to generate a refresh address signal that is sequentially counted when a refresh signal is input to the refresh address generation circuit;
an internal signal generation circuit configured to generate an internal read signal and an internal write signal that are sequentially generated when the refresh signal is input to the internal signal generation circuit; and
an address storage circuit configured to store the address signal for activating a word line of a first memory region in which the first internal data including an error is stored as the first failure address signal when the failure detection signal is input to the address storage circuit, store the address signal for activating a word line of a second memory region in which the second internal data including an error is stored as the second failure address signal when the failure detection signal is input to the address storage circuit, and output the first failure address signal and the second failure address signal when the internal read signal and the internal write signal are input to the address storage circuit.