Patent ID: 11901439
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  B | IPC H

Claim 14:
15. A method comprising:
forming a first semiconductor layer on a semiconductor substrate, the first semiconductor layer comprising a first semiconductor material;
etching sidewalls of the first semiconductor layer to form a sidewall recess;
depositing a first inner spacer layer in the sidewall recess;
depositing a second inner spacer layer on the first inner spacer layer;
depositing a third inner spacer layer filling the sidewall recess;
etching the first inner spacer layer, the second inner spacer layer, and the third inner spacer layer to form an inner spacer in the sidewall recess, wherein the second inner spacer layer is etched at a rate greater than the third inner spacer layer;
etching the first semiconductor layer and the first inner spacer layer to form a first recess adjacent the inner spacer, wherein the first inner spacer layer is etched at a rate less than the first semiconductor layer; and
forming a gate structure in the first recess.