Patent ID: 11887952
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 9:
10. A package structure, comprising:
a first dielectric layer;
a first semiconductor device above the first dielectric layer;
a first through-semiconductor-via (TSV) device above the first dielectric layer, the first TSV device comprising a first semiconductor substrate and a plurality of first TSVs extending through the first semiconductor substrate;
a second dielectric layer above the first dielectric layer, the first semiconductor device, and the TSV device;
a second semiconductor device above the second dielectric layer;
a redistribution line in the second dielectric layer and electrically connected to the second semiconductor device;
a conductive bump electrically connecting the redistribution line and the TSVs of the TSV device;
a first molding material molding the first semiconductor device and the TSV device, wherein the first molding material has a top surface not higher than top ends of the plurality of first TSVs; and
a second molding material molding the second semiconductor device.