Patent ID: 11959965
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Measurement (Instruments)
Classification: CPC G | IPC G

Claim 10:
11. An integrated circuit comprising:
an integrated circuit core; and
a test circuit configured to test the integrated circuit core or an external circuit of the integrated circuit core, and the test circuit including:
an input cell configured to transmit a first signal to the integrated circuit core, and the input cell including:
a first scan flip-flop;
a first bypass terminal configured to receive a bypass signal;
a first cell function input (CFI) terminal configured to receive a CFI signal from the external circuit;
a first cell function output (CFO) terminal configured to transmit the first signal to the integrated circuit core; and
a first multiplexer including a first selection terminal connected to the first bypass terminal, a first input terminal connected to the first CFI terminal, a second input terminal, and a first output terminal connected to the first CFO terminal, and the first multiplexer configured to transmit the CFI signal to the integrated circuit core through the first output terminal as the first signal in response to the bypass signal;
a second multiplexer including a second selection terminal connected to a safe mode terminal configured to receive a safe mode terminal, a third input terminal connected to an output terminal of the first scan flip-flop, a fourth input terminal connected to a safe value terminal configured to receive a safe value signal, and a second output terminal connected to the second input terminal of the first multiplexer; and
a cell test output (CTO) terminal connected to the output terminal of the first scan flip-flop.