Patent ID: 11861167
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 0:
1. An apparatus, comprising:
a memory sub-system controller configured to receive access commands and wear-leveling operation commands from a host device;
a first counter coupled with the memory sub-system controller and configured to count a quantity of the access commands received by the memory sub-system controller;
a comparator circuit coupled with the first counter and configured to compare an incremented value of the first counter with a threshold;
a first selector circuit coupled with the comparator circuit, wherein the first selector circuit comprises a second data input and a selection input, and wherein:
the second data input is configured to receive a baseline value associated with the first counter, and
the selection input is configured to receive a value indicating whether the incremented value of the first counter satisfies the threshold; and

a second counter coupled with the memory sub-system controller and the first counter, wherein the second counter is configured to count a quantity of the wear-leveling operation commands.