Patent ID: 11922846
Assignee: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
Field: Audio-visual technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 1:
2. The gate driving circuit according to claim 1, comprising 10 clock signal lines, wherein each shift register further comprises a clock signal terminal;
a clock signal terminal of a (10k−9)th shift register is electrically connected to a first clock signal line;
a clock signal terminal of a (10k−8)th shift register is electrically connected to a second clock signal line;
a clock signal terminal of a (10k−7)th shift register is electrically connected to a third clock signal line;
a clock signal terminal of a (10k−6)th shift register is electrically connected to a fourth clock signal line;
a clock signal terminal of a (10k−5)th shift register is electrically connected to a fifth clock signal line;
a clock signal terminal of a (10k−4)th shift register is electrically connected to a sixth clock signal line;
a clock signal terminal of a (10k−3)th shift register is electrically connected to a seventh clock signal line;
a clock signal terminal of a (10k−2)th shift register is electrically connected to an eighth clock signal line;
a clock signal terminal of a (10k−1)th shift register is electrically connected to a ninth clock signal line;
a clock signal terminal of a (10k)th shift register is electrically connected to a tenth clock signal line; and
k is a positive integer.