Patent ID: 11894045
Assignee: nan
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. A method for operating an apparatus, comprising:
issuing a compute request associated with bit vector operations, addressed to a virtual address, from control logic on a source separate from a memory device;
receiving the compute request at a sequencer separate from the memory device and coupled to the control logic;
using the sequencer to convert the virtual address of the compute request to a real address corresponding to a particular column and row in an array of memory cells on the memory device;
enabling a reduction in use of a processing resource on the memory device by reducing conversion of the virtual address to the real address by the memory device;
receiving microcode timing instructions for a compute operation, associated with the bit vector operations at the memory device to coordinate timing of a sequence of compute sub-operations associated with the bit vector operations;
receiving the timing instructions from the source;
performing the sequence of compute sub-operations at the memory device using the timing instructions; and
performing the compute operation using the timing instructions and using a compute component of the memory device.