Patent ID: 11888486
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Basic communication processes (Electrical engineering)
Classification: CPC H  G | IPC H

Claim 6:
7. A phase correcting circuit, comprising:
a delay circuit configured to receive an input clock signal and to delay the input clock signal as much as a first delay time to output an output clock signal to a 0-th node;
a load capacitor; and
one or more fine tuning circuits connected in series between the 0-th node and the load capacitor;
wherein each of the one or more fine tuning circuits includes an input terminal, a control terminal, and an output terminal;
wherein the input terminal is connected with the 0-th node or an output terminal of a previous fine tuning circuit, the control terminal receives a control signal, and the output terminal is connected with an input terminal of a next fine tuning circuit or the load capacitor;
wherein, in response to the control signal, a phase of the output clock signal is tuned as much as a second delay time shorter than the first delay time;
wherein each of the one or more fine tuning circuits includes an amplifier; and
wherein the input terminal corresponds to an input terminal of the amplifier, the control terminal corresponds to a power terminal of the amplifier, and the output terminal corresponds to an output terminal of the amplifier.