Patent ID: 11892871
Assignee: REALTEK SEMICONDUCTOR CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 11:
12. An operation method of a clock synchronization system, the clock synchronization system comprising a host circuit and a slave circuit, the host circuit comprising a first clock generator, the slave circuit comprising a second clock generator, the method comprising:
the first clock generator generating a first clock signal;
the second clock generator generating a second clock signal;
the host circuit outputting a trigger signal to the slave circuit;
when the trigger signal is issued, the host circuit simultaneously recording a first clock count of the first clock generator;
the host circuit outputting the first clock count to the slave circuit;
when the slave circuit receives the trigger signal, the slave circuit recording a second clock count of the second clock generator; and
the slave circuit calculating a time difference between the first clock signal and the second clock signal according to the first clock count and the second clock count.