Patent ID: 11876085
Assignee: QUALCOMM INCORPORATED
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A package comprising:
a substrate comprising:
at least one dielectric layer;
a plurality of interconnects comprising a first interconnect and a second interconnect;
a capacitor located at least partially in the substrate, the capacitor comprising a first terminal and a second terminal,
wherein a part of the capacitor directly touches the at least one dielectric layer of the substrate,
wherein the first terminal includes a first top surface, a first bottom surface and a first side surface, and
wherein the second terminal includes a second top surface, a second bottom surface and a second side surface;

a first solder interconnect coupled to the first side surface of the first terminal and a first side wall of the first interconnect, wherein the first side surface of the first terminal faces the first side wall of the first interconnect; and
a second solder interconnect coupled to the second side surface of the second terminal and a second side wall of the second interconnect, wherein the second side surface of the second terminal faces the second side wall of the second interconnect;
wherein the substrate comprises a first surface and a second surface,
wherein the capacitor is embedded partially in the substrate through the second surface of the substrate, and

an integrated device coupled to the first surface of the substrate, wherein the integrated device vertically overlaps with at least a portion of the capacitor.