Patent ID: 11928060
Assignee: ADVANCED MICRO DEVICES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 18:
19. A processing system comprising:
a plurality of compute units, each compute unit having an associated cache of a plurality of first caches; and
a cache shared by the plurality of compute units,
wherein a third cache is configured to transfer a valid copy of a requested cacheline from a first cache of the plurality of first caches having a lowest transfer cost to a second cache of the plurality of first caches, wherein the second cache is associated with a requesting compute unit, and wherein the lowest transfer cost is identified based on each distance between the requesting compute unit and the plurality of first caches having a valid copy of the requested cacheline and based on each corresponding distance between the third cache and the plurality of first caches having a valid copy of the requested cacheline.