Patent ID: 11875481
Assignee: REALTEK SEMICONDUCTOR CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. The system according to claim 17, wherein a vertical distance between the current pixel and upper-left and upper-right grids is D1, a vertical distance between the current pixel and bottom-left and bottom-right grids is D2, a horizontal distance between the current pixel and upper-left and bottom-left grids is D3, and a horizontal distance between the current pixel and upper-right and bottom-right is D4, wherein equations of the interpolation are:

gain_intp(k)=(D2/(D1+D2))−(D4/(D3+D4))×gain(i1,j1,k)+(D2/(D1+D2))×(D3/(D3+D4))×gain(i2,j2,k)+(D1/(D1+D2))×(D4/(D3+D4))×gain(i3,j3,k)+(D1/(D1+D2))×(D3/(D3+D4))×gain(i4,j4,k);

wherein, “gain_intp(k)” is the fixed pattern noise compensation coefficient for the current pixel obtained by the interpolation, and “gain(i1,j1,k), gain(i2,j2,k), gain(i3,j3,k) and gain(i4,j4,k)” are the fixed pattern noise compensation coefficients for the central pixels of the grids adjacent to the current pixel.