Patent ID: 11929282
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 8:
9. The method for preparing the semiconductor structure of claim 8, wherein forming the bit line protective layer comprises:
forming a bit line protective material layer, the bit line protective material layer at least covering the side wall of each of the bit line structures and a surface of the supporting layer;
forming a sacrificial layer, the sacrificial layer filling the second trench between two adjacent bit line structures, and an upper surface of the sacrificial layer being flush with the upper surface of the supporting layer;
removing the supporting layer, the second dielectric layer, a portion of the sacrificial layer and a portion of the bit line protective material layer, wherein a remaining portion of the bit line protective material layer forms the bit line protective layer; and
removing the sacrificial layer.