Patent ID: 11923869
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 0:
1. A data storage device comprising:
a memory including
a plurality of memory dies, and
support circuitry configured to support memory operations at the plurality of memory dies, the support circuitry including a plurality of low-density parity check (LDPC) engines and a plurality of flash controllers (FCs), each of the plurality of FCs corresponding to one of the plurality of memory dies; and

a data storage controller including an interface and a flash translation layer (FTL), the data storage controller is configured to control the interface to output the memory operations to the memory using the FTL and a bus,
wherein the support circuitry is configured to dynamically map the plurality of LDPC engines to the plurality of FCs.