Patent ID: 11907719
Assignee: INTEL CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 14:
15. A system comprising:
a first digital signal processing (DSP) block; and
a second DSP block communicatively coupled to the first DSP block, wherein the second DSP block comprises:
a plurality of columns of weight registers;
a plurality of inputs configurable to receive a first plurality of values and a second plurality of values, wherein the first plurality of values is stored in the plurality of columns of weight registers after being received;
conversion circuitry configurable to receive a shared exponent for the second plurality of values and convert fixed-point values to floating-point values based on the shared exponent and
a plurality of multipliers configurable to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.