Patent ID: 11923201
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 7:
8. A method of manufacturing a semiconductor device, the method comprising:
blanket depositing a high-k dielectric layer into a first opening and a second opening within an interlayer dielectric;
blanket depositing a first work function tuning layer into the first opening and the second opening;
applying a wet etchant onto a first portion, but not a second portion, of the first work function tuning layer, wherein the wet etchant sequentially removes the first portion of the first work function tuning layer and forms a protective layer on the high-k dielectric layer, the protective layer comprising a metal from the high-k dielectric layer; and
depositing a conductive fill material onto the second portion of the first work function tuning layer.