Patent ID: 11900036
Assignee: IMAGINATION TECHNOLOGIES LIMITED
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. A system for verifying a property of an integrated circuit hardware design, the system comprising:
memory configured to store:
the hardware design,
one or more assertions, linked to the hardware design, which set out the property to be verified, and
quiescent logic, linked to the hardware design, that is configured to implement a constraint that an instantiation of the hardware design will enter a quiescent state at a symbolic time, the quiescent logic comprising trigger logic configured to detect a quiescent trigger that occurs at a symbolic time, and transition logic configured to, in response to the trigger logic detecting the quiescent trigger, cause the instantiation of the hardware design to transition to a quiescent state; and

one or more processors configured to formally verify, using a formal verification tool, that the one or more assertions are true for the stored hardware design under the constraint.