Patent ID: 11862514
Assignee: SAMSUNG ELECTRONICS CO., LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 0:
1. A method of manufacturing an integrated circuit device, the method comprising:
forming a lower wiring structure and a first sacrificial pattern on the lower wiring structure;
conformally forming an insulating barrier layer on the lower wiring structure and the first sacrificial pattern;
forming a second sacrificial pattern to fill a portion of an opening defined by the insulating barrier layer;
forming a capping layer on the second sacrificial pattern and the insulating barrier layer;
polishing the capping layer and the insulating barrier layer until an upper surface of the first sacrificial pattern is exposed;
removing the first sacrificial pattern;
forming an air gap by removing the second sacrificial pattern;
conformally forming an etch stop layer on the lower wiring structure, the insulating barrier layer, and the capping layer;
forming an insulating layer on the etch stop layer; and
forming an upper wiring structure penetrating the insulating layer.