Patent ID: 11948898
Assignee: INTEL CORPORATION
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 12:
13. An integrated circuit package substrate comprising:
a first layer comprising a dielectric material;
a first structure having a first width, the first structure comprising a first conductive material over the first layer; wherein the first structure comprises a surface roughness of 50 nm or less;
a second structure between the first layer and the first structure comprising a second conductive material, the second structure having a second width greater than the first width;
a second layer over the second structure and the first structure, the second layer compositionally distinct from the first layer, wherein the second layer is a single layer conformal with the first structure, and wherein the second layer has an uppermost surface above an uppermost surface of the first structure;
a third layer over the first layer, the first structure, the second structure, and the second layer, the third layer comprising the dielectric material and being compositionally distinct from the second layer;
wherein the structure includes a first portion having a first width and a second portion having a second width that is wider than the first width;
wherein the second portion extends laterally beyond a first side of the first portion by 1 μm to 5 μm, and wherein the second portion extends laterally beyond a second side of the first portion by 1 μm to 5 μm; and
wherein the second layer comprises silicon and one or more of nitrogen, carbon, and oxygen.