Patent ID: 11929261
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 10:
11. A method comprising:
testing, by first connectors, a first die of a first substrate and a second die of the first substrate;
determining the first die and the second die to pass the testing;
separating the first die of the first substrate from the second die of the first substrate;
attaching a first side of the first die and a first side of the second die to a carrier, the first side of the first die and the first side of the second die comprising the first connectors;
filling a gap between the first die and the second die with a gap filling material, the gap filling material surrounding the first die and the second die;
thinning a second side of the first die to expose a first set of via structures;
forming an interconnect over the first set of via structures;
electrically coupling one or more device dies to the interconnect; and
cutting through the gap filling material to singulate the first die and the second die from other dies embedded in the gap filling material to form a first package.