Patent ID: 11960391
Assignee: REBELLIONS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 8:
9. A method of operating a processing device comprising a plurality of processors, a shared memory shared by the plurality of processors, and a cache, wherein the cache comprises a first table comprising a plurality of elements, each of the plurality of elements in the first table being associated with a respective one of a plurality of request identifiers, the method comprising:
receiving, by the cache from at least one of the plurality of processors, a memory read request including a request identifier and a memory address;
identifying, by the cache, an allocated memory address identifier for the memory address,
accessing, by the cache, the shared memory to read data of the memory address;
obtaining, by the cache from the first table, one or more request identifiers which requested data of the memory address based on the allocated memory address identifier; and
transmitting, by the cache, the data of the memory address to one or more processors which requested data of the memory address based on the one or more request identifiers,
wherein the cache further comprises:
a second table including a plurality of elements, each of the plurality of elements in the second table being associated with a respective one of a plurality of memory address identifiers,
wherein obtaining the one or more request identifiers comprises:
accessing an element of the second table based on the allocated memory address identifier to obtain a head request identifier and a tail request identifier, and
accessing the first table based on the head request identifier and the tail request identifier to obtain the one or more request identifiers.