Patent ID: 11961567
Assignee: PUFSECURITY CORPORATION
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. The key storage device of claim 13,
wherein the first inverter further comprises:
a first PMOS transistor having a third threshold voltage, comprising a drain coupled to the first node and comprising a gate coupled to the third node;
wherein the second inverter further comprises:
a second PMOS transistor having a fourth threshold voltage, comprising a drain coupled to the second node and comprising a gate coupled to the fourth node;
wherein the third inverter further comprises:
a third PMOS transistor having the fourth threshold voltage, comprising a drain coupled to the third node and comprising a gate coupled to the first input node;
wherein the fourth inverter further comprises:
a fourth PMOS transistor having the third threshold voltage, comprising a drain coupled to the fourth node and comprising a gate coupled to the second input node;
wherein an absolute value of the fourth threshold voltage is lower than an absolute value of the third threshold voltage.