Patent ID: 11934825
Assignee: MONTANA SYSTEMS INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 14:
15. A simulation system comprising:
a simulation processor configured to execute a set of compiled models to generate stimulus for testing a design of a digital circuit; and
a simulation accelerator configured to perform acts comprising:
receiving a plurality of groups of instructions emulating a behavior of the digital circuit by applying the generated stimulus;
maintaining a pending events table in an integrated circuit (IC), each bit of the pending events table indicating absence or presence of a pending event at an input of an instruction in the plurality of groups of instructions;
selecting a group of instructions having pending input events by examining the pending events table;
executing, in the IC, the selected group of instructions to produce outputs to serve as inputs for destination instructions in other groups of instructions; and
updating the pending events table by clearing bits in the pending events table that correspond to inputs of the selected group and setting bits in the pending events table that correspond to inputs of the destination instructions.