Patent ID: 11915942
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 16:
17. A method comprising:
forming a patterned mask layer over a wafer, wherein the patterned mask layer has a first pattern;
performing a first etching process on the patterned mask layer to modify the first pattern to a second pattern, wherein the first etching process comprises:
exposing the wafer to a first ion beam, wherein the wafer is tilted at a first tilt angle with respect to the first ion beam; and
moving the wafer along a first scan line with respect to the first ion beam, wherein a first scan angle is defined between the first scan line and a line perpendicular to an axis of the first ion beam, wherein the first scan angle is less than the first tilt angle; and

performing a second etching process on the wafer according to the second pattern, wherein the second etching process comprises exposing exposed portions of the wafer to a second ion beam, an axis of the second ion beam is perpendicular to a major surface of the wafer.