Patent ID: 11864475
Assignee: MICRON TECHNOLOGY, INC.
Field: nan (nan)
Classification: CPC H | IPC H

Claim 15:
16. A method, comprising:
forming a channel in a sidewall of a material stack, the channel being bounded by a first dielectric layer, a second dielectric layer, and a conductive layer of the material stack;
depositing, into the channel over the conductive layer and via a trench by the sidewall of the material stack, a first material associated with a first electrode;
depositing, into the channel over the first material and via the trench, a second material associated with a storage element, wherein a first side of the first material is covered by the second material and a first side of the second material is exposed to the trench based at least in part on depositing the second material;
depositing, into the channel over the second material and via the trench, a third material associated with a second electrode, wherein the first side of the second material is covered and a first side of the third material is exposed to the trench based at least in part on depositing the third material;
forming, through the first, second, and third materials, an opening that exposes a second side of the second material; and
replacing, via the opening, the second material with a chalcogenide material based at least in part on exposing the second side of the second material.