Patent ID: 11881266
Assignee: SANDISK TECHNOLOGIES, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G  H | IPC G  H

Claim 13:
14. A method of operating a memory apparatus including memory cells connected to one of a plurality of word lines and disposed in memory holes organized in rows grouped in a plurality of strings and configured to retain a threshold voltage corresponding to one of a plurality of data states, the rows include full circle rows and semi-circle rows, wherein the memory holes of the semi-circle rows are partially cut by a slit half etch, the memory holes of the semi-circle rows each coupled to one of a plurality of semi-circle bit lines and the memory holes of the full circle rows each coupled to one of a plurality of full circle bit lines, the method comprising the steps of:
erasing the memory cells in an erase operation; and
during the erase operation, creating a capacitive coupling between each of the plurality of semi-circle bit lines and at least one neighboring one of the plurality of full circle bit lines adjacent to each of the plurality of semi-circle bit lines to increase a semi-circle erase voltage applied to each of the plurality of semi-circle bit lines.