Patent ID: 11875861
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 13:
14. The memory of claim 8, wherein the sensing device is a first sensing device, wherein the pFET is a first pFET, wherein the data line is a first data line, wherein the string of series-connected memory cells is a first string of series-connected memory cells, and wherein the memory further comprises:
a second data line; and
a second sensing device selectively connected to the second data line;
wherein the array of memory cells further comprises a second string of series-connected memory cells selectively connected to the second data line; and
wherein the controller is further configured to cause the memory to:
precharge the second data line;
selectively connect the second data line to the common source through a selected memory cell of the second string of series-connected memory cells while applying the verify voltage level to a control gate of the selected memory cell of the second string of series-connected memory cells;
connect the second data line to a second voltage node through a second pFET while a control gate of the second pFET receives a fifth voltage level configured to place the second pFET in a cut-off state in response to the data line having a sixth voltage level lower than the third voltage level and higher than the fourth voltage level, wherein the second voltage node is configured to receive the fourth voltage level; and
determine whether the selected memory cell of the second string of series-connected memory cells has an intended threshold voltage in response to a voltage level developed on the second data line.