Patent ID: 11889675
Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
Field: Computer technology (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 12:
13. A method, comprising:
forming in a substrate, a first active area and a second active area spaced away from one another, forming the first active area including:
forming a first bit line node;
forming a first memory cell node;
forming a first power line node;
forming a second memory cell node; and
forming a first inverted bit line node;

forming the second active area including:
forming a third memory cell node; and
forming a fourth memory cell node; and

forming a first metallization level over the substrate, including:
forming a first routing line coupling the first memory cell node to the third memory cell node; and
forming a second routing line coupling the second memory cell node to the fourth memory cell node.