Patent ID: 11943931
Assignee: STMICROELECTRONICS (ROUSSET) SAS
Field: Semiconductors (Electrical engineering)
Classification: CPC H  G | IPC G  H

Claim 6:
7. A method for manufacturing a non-volatile memory device, the method comprising:
forming a source plane within a semiconductor substrate;
forming a semiconductor well over the source plane within the semiconductor substrate;
forming a trench extending vertically in the semiconductor well of the semiconductor substrate;
forming a gate dielectric layer disposed on sidewalls of a lower portion of the trench;
forming a selection gate over the gate dielectric layer in the lower portion of the trench;
forming a charge trapping dielectric interface proximate the semiconductor well on sidewalls of an upper portion of the trench;
forming a control gate in the upper portion of the trench, the charge trapping dielectric interface separating the control gate from the semiconductor well; and
forming a drain region proximate the upper portion of the trench, the charge trapping dielectric interface and the control gate forming part of a vertical state transistor configured to trap charges in the charge trapping dielectric interface, and the selection gate and the gate dielectric layer forming part of a vertical selection transistor.