Patent ID: 11901221
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Field: Semiconductors (Electrical engineering)
Classification: CPC H | IPC H

Claim 4:
5. A method for forming an interconnect structure, the method comprising:
depositing a first metal over a substrate;
patterning the first metal to form a first metal line over the substrate and a first opening adjacent to the first metal line;
depositing a first dielectric in the first opening to form a first dielectric structure in the first opening;
forming a blocking layer directly over a top surface of the first metal line;
depositing a second dielectric, different from the first dielectric, on a top surface of the first dielectric structure with the blocking layer in place to form a first protective etch-stop structure on the top surface of the first dielectric structure;
removing the blocking layer from directly over the top surface of the first metal line;
depositing an interlayer dielectric (ILD) layer over the first protective etch-stop structure and over the first metal line;
patterning the ILD layer to form a second opening in the ILD layer directly over the first metal line and directly over the first protective etch-stop structure, wherein patterning the ILD layer comprises etching the ILD layer with high selectivity relative to the first protective etch-stop structure; and
depositing a second metal in the second opening to form a metal via in the second opening directly over the first metal line and directly over the first protective etch-stop structure, wherein the metal via is vertically separated from the first dielectric structure by the first protective etch-stop structure after the second metal is deposited.