Patent ID: 11934688
Assignee: MICRON TECHNOLOGY, INC.
Field: Computer technology (Electrical engineering)
Classification: CPC G | IPC G

Claim 17:
18. An apparatus, comprising:
one or more memory devices; and
a controller for the one or more memory devices, the controller configured to cause the apparatus to:
read a set of bits from a set of memory cells within the one or more memory devices, each memory cell of the set of memory cells is configured to store one or more bits of the set of bits;
increment each counter of a plurality of counters based at least in part on reading the set of bits using a plurality of read thresholds;
determine, based at least in part on one or more expected quantities of respective logic values for the set of bits and the plurality of counters, a quantity of errors in the set of bits;
adjust a read threshold of the plurality of read thresholds corresponding to a logic value based at least in part on the quantity of errors in the set of bits satisfying a threshold quantity of errors; and
reread the set of bits from the set of memory cells using the adjusted read threshold.