# Copyright 2022 Google LLC
#
# This source code is licensed under the BSD-style license found in the
# LICENSE file in the root directory of this source tree.
#
# Description: microkernel filename lists.
#
# Auto-generated file. Do not edit!
#   Generator: tools/update-microkernels.py


SET(ALL_ARMSIMD32_MICROKERNEL_SRCS
  src/qs8-gemm/gen/qs8-gemm-1x1c4-minmax-fp32-armsimd32.c
  src/qs8-gemm/gen/qs8-gemm-1x2c4-minmax-fp32-armsimd32.c
  src/qs8-gemm/gen/qs8-gemm-2x1c4-minmax-fp32-armsimd32.c
  src/qs8-gemm/gen/qs8-gemm-2x2c4-minmax-fp32-armsimd32.c
  src/qs8-igemm/gen/qs8-igemm-1x1c4-minmax-fp32-armsimd32.c
  src/qs8-igemm/gen/qs8-igemm-1x2c4-minmax-fp32-armsimd32.c
  src/qs8-igemm/gen/qs8-igemm-2x1c4-minmax-fp32-armsimd32.c
  src/qs8-igemm/gen/qs8-igemm-2x2c4-minmax-fp32-armsimd32.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x1c4-minmax-fp32-armsimd32.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x2c4-minmax-fp32-armsimd32.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x1c4-minmax-fp32-armsimd32.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x2c4-minmax-fp32-armsimd32.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x1c4-minmax-fp32-armsimd32.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x2c4-minmax-fp32-armsimd32.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x1c4-minmax-fp32-armsimd32.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x2c4-minmax-fp32-armsimd32.c
  src/qs8-vcvt/gen/qs8-vcvt-armsimd32-x4.c
  src/qs8-vcvt/gen/qs8-vcvt-armsimd32-x8.c
  src/qs8-vlrelu/gen/qs8-vlrelu-armsimd32-x4.c
  src/qs8-vlrelu/gen/qs8-vlrelu-armsimd32-x8.c
  src/qu8-gemm/gen/qu8-gemm-1x1c4-minmax-fp32-armsimd32.c
  src/qu8-gemm/gen/qu8-gemm-1x2c4-minmax-fp32-armsimd32.c
  src/qu8-gemm/gen/qu8-gemm-2x1c4-minmax-fp32-armsimd32.c
  src/qu8-gemm/gen/qu8-gemm-2x2c4-minmax-fp32-armsimd32.c
  src/qu8-igemm/gen/qu8-igemm-1x1c4-minmax-fp32-armsimd32.c
  src/qu8-igemm/gen/qu8-igemm-1x2c4-minmax-fp32-armsimd32.c
  src/qu8-igemm/gen/qu8-igemm-2x1c4-minmax-fp32-armsimd32.c
  src/qu8-igemm/gen/qu8-igemm-2x2c4-minmax-fp32-armsimd32.c
  src/qu8-vcvt/gen/qu8-vcvt-armsimd32-x4.c
  src/qu8-vcvt/gen/qu8-vcvt-armsimd32-x8.c
  src/qu8-vlrelu/gen/qu8-vlrelu-armsimd32-x4.c
  src/qu8-vlrelu/gen/qu8-vlrelu-armsimd32-x8.c)

SET(ALL_AVX_MICROKERNEL_SRCS
  src/f16-f32-vcvt/gen/f16-f32-vcvt-avx-int16-x8.c
  src/f16-f32-vcvt/gen/f16-f32-vcvt-avx-int16-x16.c
  src/f16-f32-vcvt/gen/f16-f32-vcvt-avx-int16-x24.c
  src/f16-f32-vcvt/gen/f16-f32-vcvt-avx-int16-x32.c
  src/f16-f32-vcvt/gen/f16-f32-vcvt-avx-int32-x8.c
  src/f16-f32-vcvt/gen/f16-f32-vcvt-avx-int32-x16.c
  src/f16-f32-vcvt/gen/f16-f32-vcvt-avx-int32-x24.c
  src/f16-f32-vcvt/gen/f16-f32-vcvt-avx-int32-x32.c
  src/f32-dwconv/gen/f32-dwconv-3p8c-minmax-avx-acc2.c
  src/f32-dwconv/gen/f32-dwconv-3p8c-minmax-avx.c
  src/f32-dwconv/gen/f32-dwconv-3p16c-minmax-avx-acc2.c
  src/f32-dwconv/gen/f32-dwconv-3p16c-minmax-avx.c
  src/f32-dwconv/gen/f32-dwconv-4p8c-minmax-avx-acc2.c
  src/f32-dwconv/gen/f32-dwconv-4p8c-minmax-avx.c
  src/f32-dwconv/gen/f32-dwconv-4p16c-minmax-avx-acc2.c
  src/f32-dwconv/gen/f32-dwconv-4p16c-minmax-avx.c
  src/f32-dwconv/gen/f32-dwconv-5f5m5l8c8s4r-minmax-avx-acc2.c
  src/f32-dwconv/gen/f32-dwconv-5f5m5l8c8s4r-minmax-avx.c
  src/f32-dwconv/gen/f32-dwconv-5f5m5l16c8s4r-minmax-avx-acc2.c
  src/f32-dwconv/gen/f32-dwconv-5f5m5l16c8s4r-minmax-avx.c
  src/f32-dwconv/gen/f32-dwconv-6f6m7l8c8s4r-minmax-avx-acc2.c
  src/f32-dwconv/gen/f32-dwconv-6f6m7l8c8s4r-minmax-avx.c
  src/f32-dwconv/gen/f32-dwconv-6f6m7l16c8s4r-minmax-avx-acc2.c
  src/f32-dwconv/gen/f32-dwconv-6f6m7l16c8s4r-minmax-avx.c
  src/f32-dwconv/gen/f32-dwconv-8f8m9l8c8s4r-minmax-avx-acc2.c
  src/f32-dwconv/gen/f32-dwconv-8f8m9l8c8s4r-minmax-avx.c
  src/f32-dwconv/gen/f32-dwconv-8f8m9l16c8s4r-minmax-avx-acc2.c
  src/f32-dwconv/gen/f32-dwconv-8f8m9l16c8s4r-minmax-avx.c
  src/f32-dwconv/gen/f32-dwconv-9p8c-minmax-avx-acc2.c
  src/f32-dwconv/gen/f32-dwconv-9p8c-minmax-avx.c
  src/f32-dwconv/gen/f32-dwconv-9p16c-minmax-avx-acc2.c
  src/f32-dwconv/gen/f32-dwconv-9p16c-minmax-avx.c
  src/f32-dwconv/gen/f32-dwconv-25p8c-minmax-avx-acc2.c
  src/f32-dwconv/gen/f32-dwconv-25p8c-minmax-avx.c
  src/f32-dwconv/gen/f32-dwconv-25p16c-minmax-avx-acc2.c
  src/f32-dwconv/gen/f32-dwconv-25p16c-minmax-avx.c
  src/f32-f16-vcvt/gen/f32-f16-vcvt-avx-x8.c
  src/f32-f16-vcvt/gen/f32-f16-vcvt-avx-x16.c
  src/f32-f16-vcvt/gen/f32-f16-vcvt-avx-x24.c
  src/f32-f16-vcvt/gen/f32-f16-vcvt-avx-x32.c
  src/f32-gemm/gen/f32-gemm-1x8-minmax-avx-broadcast.c
  src/f32-gemm/gen/f32-gemm-1x16-minmax-avx-broadcast.c
  src/f32-gemm/gen/f32-gemm-3x16-minmax-avx-broadcast.c
  src/f32-gemm/gen/f32-gemm-4x8-minmax-avx-broadcast.c
  src/f32-gemm/gen/f32-gemm-4x16-minmax-avx-broadcast.c
  src/f32-gemm/gen/f32-gemm-5x8-minmax-avx-broadcast.c
  src/f32-gemm/gen/f32-gemm-5x16-minmax-avx-broadcast.c
  src/f32-gemm/gen/f32-gemm-6x8-minmax-avx-broadcast.c
  src/f32-gemm/gen/f32-gemm-6x16-minmax-avx-broadcast.c
  src/f32-gemm/gen/f32-gemm-7x8-minmax-avx-broadcast.c
  src/f32-gemminc/gen/f32-gemminc-1x8-minmax-avx-broadcast.c
  src/f32-gemminc/gen/f32-gemminc-1x16-minmax-avx-broadcast.c
  src/f32-gemminc/gen/f32-gemminc-3x16-minmax-avx-broadcast.c
  src/f32-gemminc/gen/f32-gemminc-4x8-minmax-avx-broadcast.c
  src/f32-gemminc/gen/f32-gemminc-4x16-minmax-avx-broadcast.c
  src/f32-gemminc/gen/f32-gemminc-5x8-minmax-avx-broadcast.c
  src/f32-gemminc/gen/f32-gemminc-5x16-minmax-avx-broadcast.c
  src/f32-gemminc/gen/f32-gemminc-6x8-minmax-avx-broadcast.c
  src/f32-gemminc/gen/f32-gemminc-6x16-minmax-avx-broadcast.c
  src/f32-gemminc/gen/f32-gemminc-7x8-minmax-avx-broadcast.c
  src/f32-igemm/gen/f32-igemm-1x8-minmax-avx-broadcast.c
  src/f32-igemm/gen/f32-igemm-1x16-minmax-avx-broadcast.c
  src/f32-igemm/gen/f32-igemm-3x16-minmax-avx-broadcast.c
  src/f32-igemm/gen/f32-igemm-4x8-minmax-avx-broadcast.c
  src/f32-igemm/gen/f32-igemm-4x16-minmax-avx-broadcast.c
  src/f32-igemm/gen/f32-igemm-5x8-minmax-avx-broadcast.c
  src/f32-igemm/gen/f32-igemm-5x16-minmax-avx-broadcast.c
  src/f32-igemm/gen/f32-igemm-6x8-minmax-avx-broadcast.c
  src/f32-igemm/gen/f32-igemm-6x16-minmax-avx-broadcast.c
  src/f32-igemm/gen/f32-igemm-7x8-minmax-avx-broadcast.c
  src/f32-prelu/gen/f32-prelu-avx-2x8.c
  src/f32-prelu/gen/f32-prelu-avx-2x16.c
  src/f32-qc4w-gemm/gen/f32-qc4w-gemm-1x8-minmax-avx-dup.c
  src/f32-qc4w-gemm/gen/f32-qc4w-gemm-3x8-minmax-avx-dup.c
  src/f32-qc4w-gemm/gen/f32-qc4w-gemm-4x8-minmax-avx-dup.c
  src/f32-qc4w-gemm/gen/f32-qc4w-gemm-5x8-minmax-avx-dup.c
  src/f32-qc4w-gemm/gen/f32-qc4w-gemm-6x8-minmax-avx-dup.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-avx-dup.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8-minmax-avx-dup.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-minmax-avx-dup.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-minmax-avx-dup.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-minmax-avx-dup.c
  src/f32-qs8-vcvt/gen/f32-qs8-vcvt-avx-x8.c
  src/f32-qs8-vcvt/gen/f32-qs8-vcvt-avx-x16.c
  src/f32-qs8-vcvt/gen/f32-qs8-vcvt-avx-x24.c
  src/f32-qs8-vcvt/gen/f32-qs8-vcvt-avx-x32.c
  src/f32-qu8-vcvt/gen/f32-qu8-vcvt-avx-x8.c
  src/f32-qu8-vcvt/gen/f32-qu8-vcvt-avx-x16.c
  src/f32-qu8-vcvt/gen/f32-qu8-vcvt-avx-x24.c
  src/f32-qu8-vcvt/gen/f32-qu8-vcvt-avx-x32.c
  src/f32-rmax/f32-rmax-avx.c
  src/f32-rsum/gen/f32-rsum-avx-x8.c
  src/f32-rsum/gen/f32-rsum-avx-x16-acc2.c
  src/f32-rsum/gen/f32-rsum-avx-x24-acc3.c
  src/f32-rsum/gen/f32-rsum-avx-x32-acc2.c
  src/f32-rsum/gen/f32-rsum-avx-x32-acc4.c
  src/f32-vbinary/gen/f32-vadd-minmax-avx-x8.c
  src/f32-vbinary/gen/f32-vadd-minmax-avx-x16.c
  src/f32-vbinary/gen/f32-vaddc-minmax-avx-x8.c
  src/f32-vbinary/gen/f32-vaddc-minmax-avx-x16.c
  src/f32-vbinary/gen/f32-vdiv-minmax-avx-x8.c
  src/f32-vbinary/gen/f32-vdiv-minmax-avx-x16.c
  src/f32-vbinary/gen/f32-vdivc-minmax-avx-x8.c
  src/f32-vbinary/gen/f32-vdivc-minmax-avx-x16.c
  src/f32-vbinary/gen/f32-vmax-avx-x8.c
  src/f32-vbinary/gen/f32-vmax-avx-x16.c
  src/f32-vbinary/gen/f32-vmaxc-avx-x8.c
  src/f32-vbinary/gen/f32-vmaxc-avx-x16.c
  src/f32-vbinary/gen/f32-vmin-avx-x8.c
  src/f32-vbinary/gen/f32-vmin-avx-x16.c
  src/f32-vbinary/gen/f32-vminc-avx-x8.c
  src/f32-vbinary/gen/f32-vminc-avx-x16.c
  src/f32-vbinary/gen/f32-vmul-minmax-avx-x8.c
  src/f32-vbinary/gen/f32-vmul-minmax-avx-x16.c
  src/f32-vbinary/gen/f32-vmulc-minmax-avx-x8.c
  src/f32-vbinary/gen/f32-vmulc-minmax-avx-x16.c
  src/f32-vbinary/gen/f32-vrdivc-minmax-avx-x8.c
  src/f32-vbinary/gen/f32-vrdivc-minmax-avx-x16.c
  src/f32-vbinary/gen/f32-vrsubc-minmax-avx-x8.c
  src/f32-vbinary/gen/f32-vrsubc-minmax-avx-x16.c
  src/f32-vbinary/gen/f32-vsqrdiff-avx-x8.c
  src/f32-vbinary/gen/f32-vsqrdiff-avx-x16.c
  src/f32-vbinary/gen/f32-vsqrdiffc-avx-x8.c
  src/f32-vbinary/gen/f32-vsqrdiffc-avx-x16.c
  src/f32-vbinary/gen/f32-vsub-minmax-avx-x8.c
  src/f32-vbinary/gen/f32-vsub-minmax-avx-x16.c
  src/f32-vbinary/gen/f32-vsubc-minmax-avx-x8.c
  src/f32-vbinary/gen/f32-vsubc-minmax-avx-x16.c
  src/f32-vclamp/gen/f32-vclamp-avx-x8.c
  src/f32-vclamp/gen/f32-vclamp-avx-x16.c
  src/f32-velu/gen/f32-velu-avx-rr2-lut4-p4-perm-x8.c
  src/f32-velu/gen/f32-velu-avx-rr2-lut4-p4-perm-x16.c
  src/f32-velu/gen/f32-velu-avx-rr2-lut4-p4-perm-x24.c
  src/f32-velu/gen/f32-velu-avx-rr2-lut4-p4-perm-x32.c
  src/f32-velu/gen/f32-velu-avx-rr2-lut4-p4-perm-x40.c
  src/f32-velu/gen/f32-velu-avx-rr2-lut4-p4-perm-x48.c
  src/f32-velu/gen/f32-velu-avx-rr2-lut16-p3-x8.c
  src/f32-velu/gen/f32-velu-avx-rr2-lut16-p3-x16.c
  src/f32-velu/gen/f32-velu-avx-rr2-lut16-p3-x24.c
  src/f32-velu/gen/f32-velu-avx-rr2-lut16-p3-x32.c
  src/f32-velu/gen/f32-velu-avx-rr2-lut16-p3-x40.c
  src/f32-velu/gen/f32-velu-avx-rr2-lut16-p3-x48.c
  src/f32-velu/gen/f32-velu-avx-rr2-p6-x8.c
  src/f32-velu/gen/f32-velu-avx-rr2-p6-x16.c
  src/f32-velu/gen/f32-velu-avx-rr2-p6-x24.c
  src/f32-velu/gen/f32-velu-avx-rr2-p6-x32.c
  src/f32-velu/gen/f32-velu-avx-rr2-p6-x40.c
  src/f32-velu/gen/f32-velu-avx-rr2-p6-x48.c
  src/f32-vhswish/gen/f32-vhswish-avx-x8.c
  src/f32-vhswish/gen/f32-vhswish-avx-x16.c
  src/f32-vlrelu/gen/f32-vlrelu-avx-x8.c
  src/f32-vlrelu/gen/f32-vlrelu-avx-x16.c
  src/f32-vrelu/gen/f32-vrelu-avx-x8.c
  src/f32-vrelu/gen/f32-vrelu-avx-x16.c
  src/f32-vrnd/gen/f32-vrndd-avx-x8.c
  src/f32-vrnd/gen/f32-vrndd-avx-x16.c
  src/f32-vrnd/gen/f32-vrndne-avx-x8.c
  src/f32-vrnd/gen/f32-vrndne-avx-x16.c
  src/f32-vrnd/gen/f32-vrndu-avx-x8.c
  src/f32-vrnd/gen/f32-vrndu-avx-x16.c
  src/f32-vrnd/gen/f32-vrndz-avx-x8.c
  src/f32-vrnd/gen/f32-vrndz-avx-x16.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-div-x8.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-div-x16.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-div-x24.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-div-x32.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-div-x40.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-div-x48.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-div-x56.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-div-x64.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-div-x72.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-div-x80.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-nr2-x8.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-nr2-x16.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-nr2-x24.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-nr2-x32.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-nr2-x40.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-nr2-x48.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-nr2-x56.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-nr2-x64.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-nr2-x72.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx-rr2-p5-nr2-x80.c
  src/f32-vsqrt/gen/f32-vsqrt-avx-sqrt-x8.c
  src/f32-vsqrt/gen/f32-vsqrt-avx-sqrt-x16.c
  src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut4-p4h2ts-perm-div-x8.c
  src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut4-p4h2ts-perm-div-x16.c
  src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut4-p4h2ts-perm-div-x24.c
  src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut4-p4h2ts-perm-div-x32.c
  src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut4-p4h2ts-perm-div-x40.c
  src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut4-p4h2ts-perm-div-x48.c
  src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut4-p4h2ts-perm-div-x56.c
  src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut4-p4h2ts-perm-div-x64.c
  src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut4-p4h2ts-perm-div-x72.c
  src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut4-p4h2ts-perm-div-x80.c
  src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut8-p4h3ts-div-x8.c
  src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut8-p4h3ts-div-x16.c
  src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut8-p4h3ts-div-x24.c
  src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-lut8-p4h3ts-div-x32.c
  src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-div-x8.c
  src/f32-vtanh/gen/f32-vtanh-avx-expm1minus-rr1-p6h5ts-div-x16.c
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  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c8-minmax-fp32-avx-ld128.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c2-minmax-fp32-avx-ld64.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c2-minmax-fp32-avx-ld128.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c2s4-minmax-fp32-avx-ld64.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c2s4-minmax-fp32-avx-ld128.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c8-minmax-fp32-avx-ld64.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c8-minmax-fp32-avx-ld128.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c2-minmax-fp32-avx-ld64.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c2-minmax-fp32-avx-ld128.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c2s4-minmax-fp32-avx-ld64.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c2s4-minmax-fp32-avx-ld128.c
  src/qs8-vadd/gen/qs8-vadd-minmax-avx-mul16-ld64-x8.c
  src/qs8-vadd/gen/qs8-vadd-minmax-avx-mul16-ld64-x16.c
  src/qs8-vadd/gen/qs8-vadd-minmax-avx-mul16-ld64-x24.c
  src/qs8-vadd/gen/qs8-vadd-minmax-avx-mul16-ld64-x32.c
  src/qs8-vadd/gen/qs8-vadd-minmax-avx-mul32-ld32-x8.c
  src/qs8-vadd/gen/qs8-vadd-minmax-avx-mul32-ld32-x16.c
  src/qs8-vadd/gen/qs8-vadd-minmax-avx-mul32-ld32-x24.c
  src/qs8-vadd/gen/qs8-vadd-minmax-avx-mul32-ld32-x32.c
  src/qs8-vaddc/gen/qs8-vaddc-minmax-avx-mul16-ld64-x8.c
  src/qs8-vaddc/gen/qs8-vaddc-minmax-avx-mul16-ld64-x16.c
  src/qs8-vaddc/gen/qs8-vaddc-minmax-avx-mul16-ld64-x24.c
  src/qs8-vaddc/gen/qs8-vaddc-minmax-avx-mul16-ld64-x32.c
  src/qs8-vaddc/gen/qs8-vaddc-minmax-avx-mul32-ld32-x8.c
  src/qs8-vaddc/gen/qs8-vaddc-minmax-avx-mul32-ld32-x16.c
  src/qs8-vaddc/gen/qs8-vaddc-minmax-avx-mul32-ld32-x24.c
  src/qs8-vaddc/gen/qs8-vaddc-minmax-avx-mul32-ld32-x32.c
  src/qs8-vcvt/gen/qs8-vcvt-avx-x8.c
  src/qs8-vcvt/gen/qs8-vcvt-avx-x16.c
  src/qs8-vcvt/gen/qs8-vcvt-avx-x32.c
  src/qs8-vlrelu/gen/qs8-vlrelu-avx-x8.c
  src/qs8-vlrelu/gen/qs8-vlrelu-avx-x16.c
  src/qs8-vlrelu/gen/qs8-vlrelu-avx-x32.c
  src/qs8-vmul/gen/qs8-vmul-minmax-fp32-avx-mul16-ld64-x8.c
  src/qs8-vmul/gen/qs8-vmul-minmax-fp32-avx-mul16-ld64-x16.c
  src/qs8-vmulc/gen/qs8-vmulc-minmax-fp32-avx-mul16-ld64-x8.c
  src/qs8-vmulc/gen/qs8-vmulc-minmax-fp32-avx-mul16-ld64-x16.c
  src/qs16-qs8-vcvt/gen/qs16-qs8-vcvt-avx-x4.c
  src/qs16-qs8-vcvt/gen/qs16-qs8-vcvt-avx-x8.c
  src/qs16-qs8-vcvt/gen/qs16-qs8-vcvt-avx-x16.c
  src/qu8-dwconv/gen/qu8-dwconv-5f5m5l8c4s4r-minmax-fp32-avx-mul32.c
  src/qu8-dwconv/gen/qu8-dwconv-5f5m5l16c4s4r-minmax-fp32-avx-mul32.c
  src/qu8-dwconv/gen/qu8-dwconv-6f6m7l8c4s4r-minmax-fp32-avx-mul32.c
  src/qu8-dwconv/gen/qu8-dwconv-6f6m7l16c4s4r-minmax-fp32-avx-mul32.c
  src/qu8-dwconv/gen/qu8-dwconv-8f8m9l8c4s4r-minmax-fp32-avx-mul32.c
  src/qu8-dwconv/gen/qu8-dwconv-8f8m9l16c4s4r-minmax-fp32-avx-mul32.c
  src/qu8-dwconv/gen/qu8-dwconv-9p8c-minmax-fp32-avx-mul16.c
  src/qu8-dwconv/gen/qu8-dwconv-9p8c-minmax-fp32-avx-mul32.c
  src/qu8-dwconv/gen/qu8-dwconv-9p16c-minmax-fp32-avx-mul16.c
  src/qu8-dwconv/gen/qu8-dwconv-9p16c-minmax-fp32-avx-mul32.c
  src/qu8-dwconv/gen/qu8-dwconv-25p8c-minmax-fp32-avx-mul16.c
  src/qu8-dwconv/gen/qu8-dwconv-25p8c-minmax-fp32-avx-mul32.c
  src/qu8-dwconv/gen/qu8-dwconv-25p16c-minmax-fp32-avx-mul16.c
  src/qu8-dwconv/gen/qu8-dwconv-25p16c-minmax-fp32-avx-mul32.c
  src/qu8-f32-vcvt/gen/qu8-f32-vcvt-avx-x8.c
  src/qu8-f32-vcvt/gen/qu8-f32-vcvt-avx-x16.c
  src/qu8-f32-vcvt/gen/qu8-f32-vcvt-avx-x24.c
  src/qu8-f32-vcvt/gen/qu8-f32-vcvt-avx-x32.c
  src/qu8-gemm/gen/qu8-gemm-1x4c2-minmax-fp32-avx-ld64.c
  src/qu8-gemm/gen/qu8-gemm-1x4c2-minmax-fp32-avx-ld128.c
  src/qu8-gemm/gen/qu8-gemm-1x4c2s4-minmax-fp32-avx-ld64.c
  src/qu8-gemm/gen/qu8-gemm-1x4c2s4-minmax-fp32-avx-ld128.c
  src/qu8-gemm/gen/qu8-gemm-1x4c8-minmax-fp32-avx-ld64.c
  src/qu8-gemm/gen/qu8-gemm-1x4c8-minmax-fp32-avx-ld128.c
  src/qu8-gemm/gen/qu8-gemm-2x4c2-minmax-fp32-avx-ld64.c
  src/qu8-gemm/gen/qu8-gemm-2x4c2-minmax-fp32-avx-ld128.c
  src/qu8-gemm/gen/qu8-gemm-2x4c2s4-minmax-fp32-avx-ld64.c
  src/qu8-gemm/gen/qu8-gemm-2x4c2s4-minmax-fp32-avx-ld128.c
  src/qu8-gemm/gen/qu8-gemm-2x4c8-minmax-fp32-avx-ld64.c
  src/qu8-gemm/gen/qu8-gemm-2x4c8-minmax-fp32-avx-ld128.c
  src/qu8-gemm/gen/qu8-gemm-3x4c2-minmax-fp32-avx-ld64.c
  src/qu8-gemm/gen/qu8-gemm-3x4c2-minmax-fp32-avx-ld128.c
  src/qu8-gemm/gen/qu8-gemm-3x4c2s4-minmax-fp32-avx-ld64.c
  src/qu8-gemm/gen/qu8-gemm-3x4c2s4-minmax-fp32-avx-ld128.c
  src/qu8-gemm/gen/qu8-gemm-3x4c8-minmax-fp32-avx-ld64.c
  src/qu8-gemm/gen/qu8-gemm-3x4c8-minmax-fp32-avx-ld128.c
  src/qu8-gemm/gen/qu8-gemm-4x4c2-minmax-fp32-avx-ld64.c
  src/qu8-gemm/gen/qu8-gemm-4x4c2-minmax-fp32-avx-ld128.c
  src/qu8-gemm/gen/qu8-gemm-4x4c2s4-minmax-fp32-avx-ld64.c
  src/qu8-gemm/gen/qu8-gemm-4x4c2s4-minmax-fp32-avx-ld128.c
  src/qu8-igemm/gen/qu8-igemm-1x4c2-minmax-fp32-avx-ld64.c
  src/qu8-igemm/gen/qu8-igemm-1x4c2-minmax-fp32-avx-ld128.c
  src/qu8-igemm/gen/qu8-igemm-1x4c2s4-minmax-fp32-avx-ld64.c
  src/qu8-igemm/gen/qu8-igemm-1x4c2s4-minmax-fp32-avx-ld128.c
  src/qu8-igemm/gen/qu8-igemm-1x4c8-minmax-fp32-avx-ld64.c
  src/qu8-igemm/gen/qu8-igemm-1x4c8-minmax-fp32-avx-ld128.c
  src/qu8-igemm/gen/qu8-igemm-2x4c2-minmax-fp32-avx-ld64.c
  src/qu8-igemm/gen/qu8-igemm-2x4c2-minmax-fp32-avx-ld128.c
  src/qu8-igemm/gen/qu8-igemm-2x4c2s4-minmax-fp32-avx-ld64.c
  src/qu8-igemm/gen/qu8-igemm-2x4c2s4-minmax-fp32-avx-ld128.c
  src/qu8-igemm/gen/qu8-igemm-2x4c8-minmax-fp32-avx-ld64.c
  src/qu8-igemm/gen/qu8-igemm-2x4c8-minmax-fp32-avx-ld128.c
  src/qu8-igemm/gen/qu8-igemm-3x4c2-minmax-fp32-avx-ld64.c
  src/qu8-igemm/gen/qu8-igemm-3x4c2-minmax-fp32-avx-ld128.c
  src/qu8-igemm/gen/qu8-igemm-3x4c2s4-minmax-fp32-avx-ld64.c
  src/qu8-igemm/gen/qu8-igemm-3x4c2s4-minmax-fp32-avx-ld128.c
  src/qu8-igemm/gen/qu8-igemm-3x4c8-minmax-fp32-avx-ld64.c
  src/qu8-igemm/gen/qu8-igemm-3x4c8-minmax-fp32-avx-ld128.c
  src/qu8-igemm/gen/qu8-igemm-4x4c2-minmax-fp32-avx-ld64.c
  src/qu8-igemm/gen/qu8-igemm-4x4c2-minmax-fp32-avx-ld128.c
  src/qu8-igemm/gen/qu8-igemm-4x4c2s4-minmax-fp32-avx-ld64.c
  src/qu8-igemm/gen/qu8-igemm-4x4c2s4-minmax-fp32-avx-ld128.c
  src/qu8-vadd/gen/qu8-vadd-minmax-avx-mul16-ld64-x8.c
  src/qu8-vadd/gen/qu8-vadd-minmax-avx-mul16-ld64-x16.c
  src/qu8-vadd/gen/qu8-vadd-minmax-avx-mul32-ld32-x8.c
  src/qu8-vadd/gen/qu8-vadd-minmax-avx-mul32-ld32-x16.c
  src/qu8-vaddc/gen/qu8-vaddc-minmax-avx-mul16-ld64-x8.c
  src/qu8-vaddc/gen/qu8-vaddc-minmax-avx-mul16-ld64-x16.c
  src/qu8-vaddc/gen/qu8-vaddc-minmax-avx-mul32-ld32-x8.c
  src/qu8-vaddc/gen/qu8-vaddc-minmax-avx-mul32-ld32-x16.c
  src/qu8-vcvt/gen/qu8-vcvt-avx-x8.c
  src/qu8-vcvt/gen/qu8-vcvt-avx-x16.c
  src/qu8-vcvt/gen/qu8-vcvt-avx-x32.c
  src/qu8-vlrelu/gen/qu8-vlrelu-avx-x8.c
  src/qu8-vlrelu/gen/qu8-vlrelu-avx-x16.c
  src/qu8-vlrelu/gen/qu8-vlrelu-avx-x32.c
  src/qu8-vmul/gen/qu8-vmul-minmax-fp32-avx-mul16-ld64-x8.c
  src/qu8-vmul/gen/qu8-vmul-minmax-fp32-avx-mul16-ld64-x16.c
  src/qu8-vmulc/gen/qu8-vmulc-minmax-fp32-avx-mul16-ld64-x8.c
  src/qu8-vmulc/gen/qu8-vmulc-minmax-fp32-avx-mul16-ld64-x16.c
  src/x8-lut/gen/x8-lut-avx-x16.c
  src/x8-lut/gen/x8-lut-avx-x32.c
  src/x8-lut/gen/x8-lut-avx-x48.c
  src/x8-lut/gen/x8-lut-avx-x64.c
  src/x32-packw/gen/x32-packw-x8-gemm-goi-avx-x4-prfm.c
  src/x32-packw/gen/x32-packw-x8-gemm-goi-avx-x4.c
  src/x32-packw/gen/x32-packw-x8s4-gemm-goi-avx-x4-prfm.c
  src/x32-packw/gen/x32-packw-x8s4-gemm-goi-avx-x4.c
  src/x32-packw/gen/x32-packw-x16-gemm-goi-avx-x4-prfm.c
  src/x32-packw/gen/x32-packw-x16-gemm-goi-avx-x4.c
  src/x32-packw/gen/x32-packw-x16s4-gemm-goi-avx-x4-prfm.c
  src/x32-packw/gen/x32-packw-x16s4-gemm-goi-avx-x4.c
  src/x32-transposec/gen/x32-transposec-8x8-multi-mov-avx.c
  src/x32-transposec/gen/x32-transposec-8x8-multi-switch-avx.c
  src/x32-transposec/gen/x32-transposec-8x8-reuse-mov-avx.c
  src/x32-transposec/gen/x32-transposec-8x8-reuse-multi-avx.c
  src/x32-transposec/gen/x32-transposec-8x8-reuse-switch-avx.c
  src/x64-transposec/gen/x64-transposec-4x4-multi-mov-avx.c
  src/x64-transposec/gen/x64-transposec-4x4-multi-multi-avx.c
  src/x64-transposec/gen/x64-transposec-4x4-multi-switch-avx.c
  src/x64-transposec/gen/x64-transposec-4x4-reuse-mov-avx.c
  src/x64-transposec/gen/x64-transposec-4x4-reuse-multi-avx.c
  src/x64-transposec/gen/x64-transposec-4x4-reuse-switch-avx.c)

SET(ALL_AVX2_MICROKERNEL_SRCS
  src/f16-f32acc-gemm/gen/f16-f32acc-gemm-1x8-minmax-avx2-broadcast.c
  src/f16-f32acc-gemm/gen/f16-f32acc-gemm-1x16-minmax-avx2-broadcast.c
  src/f16-f32acc-gemm/gen/f16-f32acc-gemm-3x16-minmax-avx2-broadcast.c
  src/f16-f32acc-gemm/gen/f16-f32acc-gemm-4x8-minmax-avx2-broadcast.c
  src/f16-f32acc-gemm/gen/f16-f32acc-gemm-4x16-minmax-avx2-broadcast.c
  src/f16-f32acc-gemm/gen/f16-f32acc-gemm-5x8-minmax-avx2-broadcast.c
  src/f16-f32acc-gemm/gen/f16-f32acc-gemm-5x16-minmax-avx2-broadcast.c
  src/f16-f32acc-gemm/gen/f16-f32acc-gemm-6x8-minmax-avx2-broadcast.c
  src/f16-f32acc-gemm/gen/f16-f32acc-gemm-7x8-minmax-avx2-broadcast.c
  src/f16-f32acc-igemm/gen/f16-f32acc-igemm-1x8-minmax-avx2-broadcast.c
  src/f16-f32acc-igemm/gen/f16-f32acc-igemm-1x16-minmax-avx2-broadcast.c
  src/f16-f32acc-igemm/gen/f16-f32acc-igemm-3x16-minmax-avx2-broadcast.c
  src/f16-f32acc-igemm/gen/f16-f32acc-igemm-4x8-minmax-avx2-broadcast.c
  src/f16-f32acc-igemm/gen/f16-f32acc-igemm-4x16-minmax-avx2-broadcast.c
  src/f16-f32acc-igemm/gen/f16-f32acc-igemm-5x8-minmax-avx2-broadcast.c
  src/f16-f32acc-igemm/gen/f16-f32acc-igemm-5x16-minmax-avx2-broadcast.c
  src/f16-f32acc-igemm/gen/f16-f32acc-igemm-6x8-minmax-avx2-broadcast.c
  src/f16-f32acc-igemm/gen/f16-f32acc-igemm-7x8-minmax-avx2-broadcast.c
  src/f16-gemm/gen/f16-gemm-1x8-minmax-avx2-broadcast.c
  src/f16-gemm/gen/f16-gemm-1x16-minmax-avx2-broadcast.c
  src/f16-gemm/gen/f16-gemm-3x16-minmax-avx2-broadcast.c
  src/f16-gemm/gen/f16-gemm-4x8-minmax-avx2-broadcast.c
  src/f16-gemm/gen/f16-gemm-4x16-minmax-avx2-broadcast.c
  src/f16-gemm/gen/f16-gemm-5x8-minmax-avx2-broadcast.c
  src/f16-gemm/gen/f16-gemm-5x16-minmax-avx2-broadcast.c
  src/f16-gemm/gen/f16-gemm-6x8-minmax-avx2-broadcast.c
  src/f16-gemm/gen/f16-gemm-7x8-minmax-avx2-broadcast.c
  src/f16-igemm/gen/f16-igemm-1x8-minmax-avx2-broadcast.c
  src/f16-igemm/gen/f16-igemm-1x16-minmax-avx2-broadcast.c
  src/f16-igemm/gen/f16-igemm-3x16-minmax-avx2-broadcast.c
  src/f16-igemm/gen/f16-igemm-4x8-minmax-avx2-broadcast.c
  src/f16-igemm/gen/f16-igemm-4x16-minmax-avx2-broadcast.c
  src/f16-igemm/gen/f16-igemm-5x8-minmax-avx2-broadcast.c
  src/f16-igemm/gen/f16-igemm-5x16-minmax-avx2-broadcast.c
  src/f16-igemm/gen/f16-igemm-6x8-minmax-avx2-broadcast.c
  src/f16-igemm/gen/f16-igemm-7x8-minmax-avx2-broadcast.c
  src/f16-pavgpool/f16-pavgpool-9p8x-minmax-avx2-c8.c
  src/f16-pavgpool/f16-pavgpool-9x-minmax-avx2-c8.c
  src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-x32-acc2.c
  src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-x32-acc4.c
  src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-x32.c
  src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-x40-acc2.c
  src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-x40-acc5.c
  src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-x40.c
  src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-x48-acc2.c
  src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-x48-acc3.c
  src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-x48.c
  src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-x64-acc2.c
  src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-x64-acc4.c
  src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-x64.c
  src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-x72-acc3.c
  src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-x72.c
  src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-x80-acc2.c
  src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-x80-acc5.c
  src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-x80.c
  src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-x96-acc2.c
  src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-x96-acc3.c
  src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-x96-acc6.c
  src/f16-raddstoreexpminusmax/gen/f16-raddstoreexpminusmax-avx2-rr1-p2-x96.c
  src/f16-velu/gen/f16-velu-avx2-rr1-p3-x8.c
  src/f16-velu/gen/f16-velu-avx2-rr1-p3-x16.c
  src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-div-x8.c
  src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-div-x16.c
  src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-div-x24.c
  src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-div-x32.c
  src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-div-x40.c
  src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-div-x48.c
  src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-div-x56.c
  src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-div-x64.c
  src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-rcp-x8.c
  src/f16-vsigmoid/gen/f16-vsigmoid-avx2-rr1-p2-rcp-x16.c
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  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l8c8s8r-minmax-fp32-avx2-mul32.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l16c8s8r-minmax-fp32-avx2-mul32.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l16c16s16r-minmax-fp32-avx2-mul16-add16-vpunpck.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l16c16s16r-minmax-fp32-avx2-mul16-vpmovsx.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l16c16s16r-minmax-fp32-avx2-mul16-vpunpck.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l32c8s8r-minmax-fp32-avx2-mul32.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l32c16s16r-minmax-fp32-avx2-mul16-add16-vpunpck.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l32c16s16r-minmax-fp32-avx2-mul16-vpmovsx.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l32c16s16r-minmax-fp32-avx2-mul16-vpunpck.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l8c8s8r-minmax-fp32-avx2-mul32.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l16c8s8r-minmax-fp32-avx2-mul32.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l16c16s16r-minmax-fp32-avx2-mul16-add16-vpunpck.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l16c16s16r-minmax-fp32-avx2-mul16-vpmovsx.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l16c16s16r-minmax-fp32-avx2-mul16-vpunpck.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l32c8s8r-minmax-fp32-avx2-mul32.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l32c16s16r-minmax-fp32-avx2-mul16-add16-vpunpck.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l32c16s16r-minmax-fp32-avx2-mul16-vpmovsx.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l32c16s16r-minmax-fp32-avx2-mul16-vpunpck.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l8c8s8r-minmax-fp32-avx2-mul32.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l16c8s8r-minmax-fp32-avx2-mul32.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l16c16s16r-minmax-fp32-avx2-mul16-add16-vpunpck.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l16c16s16r-minmax-fp32-avx2-mul16-vpmovsx.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l16c16s16r-minmax-fp32-avx2-mul16-vpunpck.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l32c8s8r-minmax-fp32-avx2-mul32.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l32c16s16r-minmax-fp32-avx2-mul16-add16-vpunpck.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l32c16s16r-minmax-fp32-avx2-mul16-vpmovsx.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l32c16s16r-minmax-fp32-avx2-mul16-vpunpck.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p8c-minmax-fp32-avx2-mul32.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-avx2-mul16-add16-vpunpck.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-avx2-mul16-vpmovsx.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-avx2-mul16-vpunpck.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-avx2-mul32.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p32c-minmax-fp32-avx2-mul16-add16-vpunpck.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p32c-minmax-fp32-avx2-mul16-vpmovsx.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p32c-minmax-fp32-avx2-mul16-vpunpck.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p32c-minmax-fp32-avx2-mul32.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p8c-minmax-fp32-avx2-mul32.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-avx2-mul16-add16-vpunpck.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-avx2-mul16-vpmovsx.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-avx2-mul16-vpunpck.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-avx2-mul32.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p32c-minmax-fp32-avx2-mul16-add16-vpunpck.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p32c-minmax-fp32-avx2-mul16-vpmovsx.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p32c-minmax-fp32-avx2-mul16-vpunpck.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p32c-minmax-fp32-avx2-mul32.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8c8-minmax-fp32-avx2.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8c8-xw-minmax-fp32-avx2.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8c8-minmax-fp32-avx2.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8c8-xw-minmax-fp32-avx2.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x8c8-minmax-fp32-avx2.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x8c8-xw-minmax-fp32-avx2.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8c8-minmax-fp32-avx2.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8c8-minmax-fp32-avx2.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x8c8-minmax-fp32-avx2.c
  src/qs8-vadd/gen/qs8-vadd-minmax-avx2-mul32-ld64-x8.c
  src/qs8-vadd/gen/qs8-vadd-minmax-avx2-mul32-ld64-x16.c
  src/qs8-vadd/gen/qs8-vadd-minmax-avx2-mul32-ld64-x24.c
  src/qs8-vadd/gen/qs8-vadd-minmax-avx2-mul32-ld64-x32.c
  src/qs8-vaddc/gen/qs8-vaddc-minmax-avx2-mul32-ld64-x8.c
  src/qs8-vaddc/gen/qs8-vaddc-minmax-avx2-mul32-ld64-x16.c
  src/qs8-vaddc/gen/qs8-vaddc-minmax-avx2-mul32-ld64-x24.c
  src/qs8-vaddc/gen/qs8-vaddc-minmax-avx2-mul32-ld64-x32.c
  src/qs8-vcvt/gen/qs8-vcvt-avx2-x16.c
  src/qs8-vcvt/gen/qs8-vcvt-avx2-x32.c
  src/qs8-vcvt/gen/qs8-vcvt-avx2-x64.c
  src/qs8-vlrelu/gen/qs8-vlrelu-avx2-x16.c
  src/qs8-vlrelu/gen/qs8-vlrelu-avx2-x32.c
  src/qs8-vlrelu/gen/qs8-vlrelu-avx2-x64.c
  src/qu8-dwconv/gen/qu8-dwconv-5f5m5l8c8s8r-minmax-fp32-avx2-mul32.c
  src/qu8-dwconv/gen/qu8-dwconv-5f5m5l16c8s8r-minmax-fp32-avx2-mul32.c
  src/qu8-dwconv/gen/qu8-dwconv-5f5m5l32c8s8r-minmax-fp32-avx2-mul32.c
  src/qu8-dwconv/gen/qu8-dwconv-6f6m7l8c8s8r-minmax-fp32-avx2-mul32.c
  src/qu8-dwconv/gen/qu8-dwconv-6f6m7l16c8s8r-minmax-fp32-avx2-mul32.c
  src/qu8-dwconv/gen/qu8-dwconv-6f6m7l32c8s8r-minmax-fp32-avx2-mul32.c
  src/qu8-dwconv/gen/qu8-dwconv-8f8m9l8c8s8r-minmax-fp32-avx2-mul32.c
  src/qu8-dwconv/gen/qu8-dwconv-8f8m9l16c8s8r-minmax-fp32-avx2-mul32.c
  src/qu8-dwconv/gen/qu8-dwconv-8f8m9l32c8s8r-minmax-fp32-avx2-mul32.c
  src/qu8-dwconv/gen/qu8-dwconv-9p8c-minmax-fp32-avx2-mul32.c
  src/qu8-dwconv/gen/qu8-dwconv-9p16c-minmax-fp32-avx2-mul32.c
  src/qu8-dwconv/gen/qu8-dwconv-9p32c-minmax-fp32-avx2-mul32.c
  src/qu8-dwconv/gen/qu8-dwconv-25p8c-minmax-fp32-avx2-mul32.c
  src/qu8-dwconv/gen/qu8-dwconv-25p16c-minmax-fp32-avx2-mul32.c
  src/qu8-dwconv/gen/qu8-dwconv-25p32c-minmax-fp32-avx2-mul32.c
  src/qu8-f32-vcvt/gen/qu8-f32-vcvt-avx2-x8.c
  src/qu8-f32-vcvt/gen/qu8-f32-vcvt-avx2-x16.c
  src/qu8-f32-vcvt/gen/qu8-f32-vcvt-avx2-x24.c
  src/qu8-f32-vcvt/gen/qu8-f32-vcvt-avx2-x32.c
  src/qu8-gemm/gen/qu8-gemm-1x8c8-minmax-fp32-avx2.c
  src/qu8-gemm/gen/qu8-gemm-2x8c8-minmax-fp32-avx2.c
  src/qu8-gemm/gen/qu8-gemm-3x8c8-minmax-fp32-avx2.c
  src/qu8-igemm/gen/qu8-igemm-1x8c8-minmax-fp32-avx2.c
  src/qu8-igemm/gen/qu8-igemm-2x8c8-minmax-fp32-avx2.c
  src/qu8-igemm/gen/qu8-igemm-3x8c8-minmax-fp32-avx2.c
  src/qu8-vadd/gen/qu8-vadd-minmax-avx2-mul32-ld64-x8.c
  src/qu8-vadd/gen/qu8-vadd-minmax-avx2-mul32-ld64-x16.c
  src/qu8-vaddc/gen/qu8-vaddc-minmax-avx2-mul32-ld64-x8.c
  src/qu8-vaddc/gen/qu8-vaddc-minmax-avx2-mul32-ld64-x16.c
  src/qu8-vcvt/gen/qu8-vcvt-avx2-x16.c
  src/qu8-vcvt/gen/qu8-vcvt-avx2-x32.c
  src/qu8-vcvt/gen/qu8-vcvt-avx2-x64.c
  src/qu8-vlrelu/gen/qu8-vlrelu-avx2-x16.c
  src/qu8-vlrelu/gen/qu8-vlrelu-avx2-x32.c
  src/qu8-vlrelu/gen/qu8-vlrelu-avx2-x64.c
  src/x8-lut/gen/x8-lut-avx2-x32.c
  src/x8-lut/gen/x8-lut-avx2-x64.c
  src/x8-lut/gen/x8-lut-avx2-x96.c
  src/x8-lut/gen/x8-lut-avx2-x128.c
  src/x8-transposec/gen/x8-transposec-32x32-reuse-mov-avx2.c
  src/x8-transposec/gen/x8-transposec-32x32-reuse-switch-avx2.c
  src/x16-packw/gen/x16-packw-x8-gemm-goi-avx2-x16-prfm.c
  src/x16-packw/gen/x16-packw-x8-gemm-goi-avx2-x16.c
  src/x16-packw/gen/x16-packw-x16-gemm-goi-avx2-x16-prfm.c
  src/x16-packw/gen/x16-packw-x16-gemm-goi-avx2-x16.c
  src/x16-transposec/gen/x16-transposec-16x16-reuse-mov-avx2.c
  src/x16-transposec/gen/x16-transposec-16x16-reuse-switch-avx2.c)

SET(ALL_AVX512F_MICROKERNEL_SRCS
  src/f32-dwconv/gen/f32-dwconv-3p16c-minmax-avx512f-acc2.c
  src/f32-dwconv/gen/f32-dwconv-3p16c-minmax-avx512f.c
  src/f32-dwconv/gen/f32-dwconv-3p32c-minmax-avx512f-acc2.c
  src/f32-dwconv/gen/f32-dwconv-3p32c-minmax-avx512f.c
  src/f32-dwconv/gen/f32-dwconv-4p16c-minmax-avx512f-acc2.c
  src/f32-dwconv/gen/f32-dwconv-4p16c-minmax-avx512f.c
  src/f32-dwconv/gen/f32-dwconv-4p32c-minmax-avx512f-acc2.c
  src/f32-dwconv/gen/f32-dwconv-4p32c-minmax-avx512f.c
  src/f32-dwconv/gen/f32-dwconv-5f5m5l16c16s1r-minmax-avx512f-acc2.c
  src/f32-dwconv/gen/f32-dwconv-5f5m5l16c16s1r-minmax-avx512f.c
  src/f32-dwconv/gen/f32-dwconv-5f5m5l32c16s1r-minmax-avx512f-acc2.c
  src/f32-dwconv/gen/f32-dwconv-5f5m5l32c16s1r-minmax-avx512f.c
  src/f32-dwconv/gen/f32-dwconv-9p16c-minmax-avx512f-acc2.c
  src/f32-dwconv/gen/f32-dwconv-9p16c-minmax-avx512f.c
  src/f32-dwconv/gen/f32-dwconv-9p32c-minmax-avx512f-acc2.c
  src/f32-dwconv/gen/f32-dwconv-9p32c-minmax-avx512f.c
  src/f32-dwconv/gen/f32-dwconv-25p16c-minmax-avx512f-acc2.c
  src/f32-dwconv/gen/f32-dwconv-25p16c-minmax-avx512f.c
  src/f32-dwconv/gen/f32-dwconv-25p32c-minmax-avx512f-acc2.c
  src/f32-dwconv/gen/f32-dwconv-25p32c-minmax-avx512f.c
  src/f32-gemm/gen/f32-gemm-1x16-minmax-avx512f-broadcast.c
  src/f32-gemm/gen/f32-gemm-4x16-minmax-avx512f-broadcast.c
  src/f32-gemm/gen/f32-gemm-5x16-minmax-avx512f-broadcast.c
  src/f32-gemm/gen/f32-gemm-6x16-minmax-avx512f-broadcast.c
  src/f32-gemm/gen/f32-gemm-7x16-minmax-avx512f-broadcast.c
  src/f32-gemm/gen/f32-gemm-8x16-minmax-avx512f-broadcast.c
  src/f32-gemminc/gen/f32-gemminc-1x16-minmax-avx512f-broadcast.c
  src/f32-gemminc/gen/f32-gemminc-4x16-minmax-avx512f-broadcast.c
  src/f32-gemminc/gen/f32-gemminc-5x16-minmax-avx512f-broadcast.c
  src/f32-gemminc/gen/f32-gemminc-6x16-minmax-avx512f-broadcast.c
  src/f32-gemminc/gen/f32-gemminc-7x16-minmax-avx512f-broadcast.c
  src/f32-gemminc/gen/f32-gemminc-8x16-minmax-avx512f-broadcast.c
  src/f32-igemm/gen/f32-igemm-1x16-minmax-avx512f-broadcast.c
  src/f32-igemm/gen/f32-igemm-4x16-minmax-avx512f-broadcast.c
  src/f32-igemm/gen/f32-igemm-5x16-minmax-avx512f-broadcast.c
  src/f32-igemm/gen/f32-igemm-6x16-minmax-avx512f-broadcast.c
  src/f32-igemm/gen/f32-igemm-7x16-minmax-avx512f-broadcast.c
  src/f32-igemm/gen/f32-igemm-8x16-minmax-avx512f-broadcast.c
  src/f32-prelu/gen/f32-prelu-avx512f-2x16.c
  src/f32-prelu/gen/f32-prelu-avx512f-2x32.c
  src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx512f-p5-scalef-x128-acc2.c
  src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx512f-p5-scalef-x128-acc4.c
  src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx512f-p5-scalef-x128.c
  src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx512f-p5-scalef-x144-acc3.c
  src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx512f-p5-scalef-x144.c
  src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx512f-p5-scalef-x160-acc2.c
  src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx512f-p5-scalef-x160-acc5.c
  src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx512f-p5-scalef-x160.c
  src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx512f-p5-scalef-x192-acc2.c
  src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx512f-p5-scalef-x192-acc3.c
  src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx512f-p5-scalef-x192-acc6.c
  src/f32-raddexpminusmax/gen/f32-raddexpminusmax-avx512f-p5-scalef-x192.c
  src/f32-raddextexp/gen/f32-raddextexp-avx512f-p5-scalef-x128-acc2.c
  src/f32-raddextexp/gen/f32-raddextexp-avx512f-p5-scalef-x128-acc4.c
  src/f32-raddextexp/gen/f32-raddextexp-avx512f-p5-scalef-x128.c
  src/f32-raddextexp/gen/f32-raddextexp-avx512f-p5-scalef-x144-acc3.c
  src/f32-raddextexp/gen/f32-raddextexp-avx512f-p5-scalef-x144.c
  src/f32-raddextexp/gen/f32-raddextexp-avx512f-p5-scalef-x160-acc2.c
  src/f32-raddextexp/gen/f32-raddextexp-avx512f-p5-scalef-x160-acc5.c
  src/f32-raddextexp/gen/f32-raddextexp-avx512f-p5-scalef-x160.c
  src/f32-raddextexp/gen/f32-raddextexp-avx512f-p5-scalef-x192-acc2.c
  src/f32-raddextexp/gen/f32-raddextexp-avx512f-p5-scalef-x192-acc3.c
  src/f32-raddextexp/gen/f32-raddextexp-avx512f-p5-scalef-x192-acc6.c
  src/f32-raddextexp/gen/f32-raddextexp-avx512f-p5-scalef-x192.c
  src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx512f-rr1-p5-scalef-x128-acc2.c
  src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx512f-rr1-p5-scalef-x128-acc4.c
  src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx512f-rr1-p5-scalef-x128.c
  src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx512f-rr1-p5-scalef-x144-acc3.c
  src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx512f-rr1-p5-scalef-x144.c
  src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx512f-rr1-p5-scalef-x160-acc2.c
  src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx512f-rr1-p5-scalef-x160-acc5.c
  src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx512f-rr1-p5-scalef-x160.c
  src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx512f-rr1-p5-scalef-x192-acc2.c
  src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx512f-rr1-p5-scalef-x192-acc3.c
  src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx512f-rr1-p5-scalef-x192-acc6.c
  src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-avx512f-rr1-p5-scalef-x192.c
  src/f32-rmax/f32-rmax-avx512f.c
  src/f32-vbinary/gen/f32-vadd-minmax-avx512f-x16.c
  src/f32-vbinary/gen/f32-vadd-minmax-avx512f-x32.c
  src/f32-vbinary/gen/f32-vaddc-minmax-avx512f-x16.c
  src/f32-vbinary/gen/f32-vaddc-minmax-avx512f-x32.c
  src/f32-vbinary/gen/f32-vdiv-minmax-avx512f-x16.c
  src/f32-vbinary/gen/f32-vdiv-minmax-avx512f-x32.c
  src/f32-vbinary/gen/f32-vdivc-minmax-avx512f-x16.c
  src/f32-vbinary/gen/f32-vdivc-minmax-avx512f-x32.c
  src/f32-vbinary/gen/f32-vmax-avx512f-x16.c
  src/f32-vbinary/gen/f32-vmax-avx512f-x32.c
  src/f32-vbinary/gen/f32-vmaxc-avx512f-x16.c
  src/f32-vbinary/gen/f32-vmaxc-avx512f-x32.c
  src/f32-vbinary/gen/f32-vmin-avx512f-x16.c
  src/f32-vbinary/gen/f32-vmin-avx512f-x32.c
  src/f32-vbinary/gen/f32-vminc-avx512f-x16.c
  src/f32-vbinary/gen/f32-vminc-avx512f-x32.c
  src/f32-vbinary/gen/f32-vmul-minmax-avx512f-x16.c
  src/f32-vbinary/gen/f32-vmul-minmax-avx512f-x32.c
  src/f32-vbinary/gen/f32-vmulc-minmax-avx512f-x16.c
  src/f32-vbinary/gen/f32-vmulc-minmax-avx512f-x32.c
  src/f32-vbinary/gen/f32-vrdivc-minmax-avx512f-x16.c
  src/f32-vbinary/gen/f32-vrdivc-minmax-avx512f-x32.c
  src/f32-vbinary/gen/f32-vrsubc-minmax-avx512f-x16.c
  src/f32-vbinary/gen/f32-vrsubc-minmax-avx512f-x32.c
  src/f32-vbinary/gen/f32-vsqrdiff-avx512f-x16.c
  src/f32-vbinary/gen/f32-vsqrdiff-avx512f-x32.c
  src/f32-vbinary/gen/f32-vsqrdiffc-avx512f-x16.c
  src/f32-vbinary/gen/f32-vsqrdiffc-avx512f-x32.c
  src/f32-vbinary/gen/f32-vsub-minmax-avx512f-x16.c
  src/f32-vbinary/gen/f32-vsub-minmax-avx512f-x32.c
  src/f32-vbinary/gen/f32-vsubc-minmax-avx512f-x16.c
  src/f32-vbinary/gen/f32-vsubc-minmax-avx512f-x32.c
  src/f32-vclamp/gen/f32-vclamp-avx512f-x16.c
  src/f32-vclamp/gen/f32-vclamp-avx512f-x32.c
  src/f32-velu/gen/f32-velu-avx512f-rr1-lut16-p3-perm-x16.c
  src/f32-velu/gen/f32-velu-avx512f-rr1-lut16-p3-perm-x32.c
  src/f32-velu/gen/f32-velu-avx512f-rr1-lut16-p3-perm-x48.c
  src/f32-velu/gen/f32-velu-avx512f-rr1-lut16-p3-perm-x64.c
  src/f32-velu/gen/f32-velu-avx512f-rr1-lut16-p3-perm-x80.c
  src/f32-velu/gen/f32-velu-avx512f-rr1-lut16-p3-perm-x96.c
  src/f32-velu/gen/f32-velu-avx512f-rr1-lut16-p3-perm-x112.c
  src/f32-velu/gen/f32-velu-avx512f-rr1-lut16-p3-perm-x128.c
  src/f32-velu/gen/f32-velu-avx512f-rr1-p6-x16.c
  src/f32-velu/gen/f32-velu-avx512f-rr1-p6-x32.c
  src/f32-velu/gen/f32-velu-avx512f-rr1-p6-x48.c
  src/f32-velu/gen/f32-velu-avx512f-rr1-p6-x64.c
  src/f32-velu/gen/f32-velu-avx512f-rr1-p6-x80.c
  src/f32-velu/gen/f32-velu-avx512f-rr1-p6-x96.c
  src/f32-velu/gen/f32-velu-avx512f-rr1-p6-x112.c
  src/f32-velu/gen/f32-velu-avx512f-rr1-p6-x128.c
  src/f32-vhswish/gen/f32-vhswish-avx512f-x16.c
  src/f32-vhswish/gen/f32-vhswish-avx512f-x32.c
  src/f32-vlrelu/gen/f32-vlrelu-avx512f-x16.c
  src/f32-vlrelu/gen/f32-vlrelu-avx512f-x32.c
  src/f32-vrelu/gen/f32-vrelu-avx512f-x16.c
  src/f32-vrelu/gen/f32-vrelu-avx512f-x32.c
  src/f32-vrnd/gen/f32-vrndd-avx512f-x16.c
  src/f32-vrnd/gen/f32-vrndd-avx512f-x32.c
  src/f32-vrnd/gen/f32-vrndne-avx512f-x16.c
  src/f32-vrnd/gen/f32-vrndne-avx512f-x32.c
  src/f32-vrnd/gen/f32-vrndu-avx512f-x16.c
  src/f32-vrnd/gen/f32-vrndu-avx512f-x32.c
  src/f32-vrnd/gen/f32-vrndz-avx512f-x16.c
  src/f32-vrnd/gen/f32-vrndz-avx512f-x32.c
  src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx512f-p5-scalef-x16.c
  src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx512f-p5-scalef-x32.c
  src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx512f-p5-scalef-x48.c
  src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx512f-p5-scalef-x64.c
  src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx512f-p5-scalef-x80.c
  src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx512f-p5-scalef-x96.c
  src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx512f-p5-scalef-x112.c
  src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx512f-p5-scalef-x128.c
  src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx512f-p5-scalef-x144.c
  src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx512f-p5-scalef-x160.c
  src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx512f-p5-scalef-x176.c
  src/f32-vscaleexpminusmax/gen/f32-vscaleexpminusmax-avx512f-p5-scalef-x192.c
  src/f32-vscaleextexp/gen/f32-vscaleextexp-avx512f-p5-scalef-x16.c
  src/f32-vscaleextexp/gen/f32-vscaleextexp-avx512f-p5-scalef-x32.c
  src/f32-vscaleextexp/gen/f32-vscaleextexp-avx512f-p5-scalef-x48.c
  src/f32-vscaleextexp/gen/f32-vscaleextexp-avx512f-p5-scalef-x64.c
  src/f32-vscaleextexp/gen/f32-vscaleextexp-avx512f-p5-scalef-x80.c
  src/f32-vscaleextexp/gen/f32-vscaleextexp-avx512f-p5-scalef-x96.c
  src/f32-vscaleextexp/gen/f32-vscaleextexp-avx512f-p5-scalef-x112.c
  src/f32-vscaleextexp/gen/f32-vscaleextexp-avx512f-p5-scalef-x128.c
  src/f32-vscaleextexp/gen/f32-vscaleextexp-avx512f-p5-scalef-x144.c
  src/f32-vscaleextexp/gen/f32-vscaleextexp-avx512f-p5-scalef-x160.c
  src/f32-vscaleextexp/gen/f32-vscaleextexp-avx512f-p5-scalef-x176.c
  src/f32-vscaleextexp/gen/f32-vscaleextexp-avx512f-p5-scalef-x192.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-div-x16.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-div-x32.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-div-x48.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-div-x64.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-div-x80.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-div-x96.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-div-x112.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-div-x128.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-nr1fma-x16.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-nr1fma-x32.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-nr1fma-x48.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-nr1fma-x64.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-nr1fma-x80.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-nr1fma-x96.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-nr1fma-x112.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-nr1fma-x128.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-p5-scalef-div-x16.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-p5-scalef-div-x32.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-p5-scalef-div-x48.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-p5-scalef-div-x64.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-p5-scalef-div-x80.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-p5-scalef-div-x96.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-p5-scalef-div-x112.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-p5-scalef-div-x128.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-p5-scalef-nr1fma-x16.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-p5-scalef-nr1fma-x32.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-p5-scalef-nr1fma-x48.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-p5-scalef-nr1fma-x64.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-p5-scalef-nr1fma-x80.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-p5-scalef-nr1fma-x96.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-p5-scalef-nr1fma-x112.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr1-p5-scalef-nr1fma-x128.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-div-x16.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-div-x32.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-div-x48.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-div-x64.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-div-x80.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-div-x96.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-div-x112.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-div-x128.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-nr1fma-x16.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-nr1fma-x32.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-nr1fma-x48.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-nr1fma-x64.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-nr1fma-x80.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-nr1fma-x96.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-nr1fma-x112.c
  src/f32-vsigmoid/gen/f32-vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-nr1fma-x128.c
  src/f32-vsqrt/gen/f32-vsqrt-avx512f-nr1fma1adj-x16.c
  src/f32-vsqrt/gen/f32-vsqrt-avx512f-nr1fma1adj-x32.c
  src/f32-vsqrt/gen/f32-vsqrt-avx512f-nr1fma1adj-x48.c
  src/f32-vsqrt/gen/f32-vsqrt-avx512f-nr1fma1adj-x64.c
  src/f32-vsqrt/gen/f32-vsqrt-avx512f-nr1fma1adj-x80.c
  src/f32-vsqrt/gen/f32-vsqrt-avx512f-nr1fma1adj-x96.c
  src/f32-vsqrt/gen/f32-vsqrt-avx512f-nr1fma1adj-x112.c
  src/f32-vsqrt/gen/f32-vsqrt-avx512f-nr1fma1adj-x128.c
  src/f32-vunary/gen/f32-vabs-avx512f-x16.c
  src/f32-vunary/gen/f32-vabs-avx512f-x32.c
  src/f32-vunary/gen/f32-vneg-avx512f-x16.c
  src/f32-vunary/gen/f32-vneg-avx512f-x32.c
  src/f32-vunary/gen/f32-vsqr-avx512f-x16.c
  src/f32-vunary/gen/f32-vsqr-avx512f-x32.c
  src/math/f32-exp-avx512f-rr2-lut16-p3-perm-scalef.c
  src/math/f32-exp-avx512f-rr2-lut16-p3-perm.c
  src/math/f32-exp-avx512f-rr2-lut32-p2-perm2-scalef.c
  src/math/f32-exp-avx512f-rr2-lut32-p2-perm2.c
  src/math/f32-exp-avx512f-rr2-p5-scalef.c
  src/math/f32-exp-avx512f-rr2-p5.c
  src/math/f32-expm1minus-avx512f-rr1-lut16-p3-perm.c
  src/math/f32-expm1minus-avx512f-rr1-p6.c
  src/math/f32-extexp-avx512f-p5.c
  src/math/f32-sigmoid-avx512f-rr1-lut16-p3-perm-scalef-div.c
  src/math/f32-sigmoid-avx512f-rr1-lut16-p3-perm-scalef-nr1fma1adj.c
  src/math/f32-sigmoid-avx512f-rr1-lut16-p3-perm-scalef-nr1fma.c
  src/math/f32-sigmoid-avx512f-rr1-lut32-p2-perm2-scalef-div.c
  src/math/f32-sigmoid-avx512f-rr1-lut32-p2-perm2-scalef-nr1fma1adj.c
  src/math/f32-sigmoid-avx512f-rr1-lut32-p2-perm2-scalef-nr1fma.c
  src/math/f32-sigmoid-avx512f-rr1-lut64-p2-gather-scalef-div.c
  src/math/f32-sigmoid-avx512f-rr1-lut64-p2-gather-scalef-nr1fma1adj.c
  src/math/f32-sigmoid-avx512f-rr1-lut64-p2-gather-scalef-nr1fma.c
  src/math/f32-sigmoid-avx512f-rr1-p5-scalef-div.c
  src/math/f32-sigmoid-avx512f-rr1-p5-scalef-nr1fma1adj.c
  src/math/f32-sigmoid-avx512f-rr1-p5-scalef-nr1fma.c
  src/math/f32-sigmoid-avx512f-rr2-lut16-p3-perm-scalef-div.c
  src/math/f32-sigmoid-avx512f-rr2-lut16-p3-perm-scalef-nr1fma1adj.c
  src/math/f32-sigmoid-avx512f-rr2-lut16-p3-perm-scalef-nr1fma.c
  src/math/f32-sigmoid-avx512f-rr2-lut32-p2-perm2-scalef-div.c
  src/math/f32-sigmoid-avx512f-rr2-lut32-p2-perm2-scalef-nr1fma1adj.c
  src/math/f32-sigmoid-avx512f-rr2-lut32-p2-perm2-scalef-nr1fma.c
  src/math/f32-sigmoid-avx512f-rr2-lut64-p2-gather-scalef-div.c
  src/math/f32-sigmoid-avx512f-rr2-lut64-p2-gather-scalef-nr1fma1adj.c
  src/math/f32-sigmoid-avx512f-rr2-lut64-p2-gather-scalef-nr1fma.c
  src/math/f32-sigmoid-avx512f-rr2-p5-scalef-div.c
  src/math/f32-sigmoid-avx512f-rr2-p5-scalef-nr1fma1adj.c
  src/math/f32-sigmoid-avx512f-rr2-p5-scalef-nr1fma.c
  src/math/f32-sqrt-avx512f-nr1fma1adj.c
  src/math/f32-sqrt-avx512f-nr1fma.c
  src/math/f32-sqrt-avx512f-nr2fma.c
  src/x32-packw/gen/x32-packw-x16-gemm-goi-avx512f-x4-prfm.c
  src/x32-packw/gen/x32-packw-x16-gemm-goi-avx512f-x4.c)

SET(ALL_AVX512SKX_MICROKERNEL_SRCS
  src/f16-f32-vcvt/gen/f16-f32-vcvt-avx512skx-x16.c
  src/f16-f32-vcvt/gen/f16-f32-vcvt-avx512skx-x32.c
  src/f32-f16-vcvt/gen/f32-f16-vcvt-avx512skx-x16.c
  src/f32-f16-vcvt/gen/f32-f16-vcvt-avx512skx-x32.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x16-minmax-avx512skx-broadcast.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-2x16-minmax-avx512skx-broadcast.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x16-minmax-avx512skx-broadcast.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x16-minmax-avx512skx-broadcast.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x16-minmax-avx512skx-broadcast.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x16-minmax-avx512skx-broadcast.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-7x16-minmax-avx512skx-broadcast.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-8x16-minmax-avx512skx-broadcast.c
  src/f32-qs8-vcvt/gen/f32-qs8-vcvt-avx512skx-x32.c
  src/f32-qs8-vcvt/gen/f32-qs8-vcvt-avx512skx-x64.c
  src/f32-qs8-vcvt/gen/f32-qs8-vcvt-avx512skx-x96.c
  src/f32-qs8-vcvt/gen/f32-qs8-vcvt-avx512skx-x128.c
  src/f32-qu8-vcvt/gen/f32-qu8-vcvt-avx512skx-x32.c
  src/f32-qu8-vcvt/gen/f32-qu8-vcvt-avx512skx-x64.c
  src/f32-qu8-vcvt/gen/f32-qu8-vcvt-avx512skx-x96.c
  src/f32-qu8-vcvt/gen/f32-qu8-vcvt-avx512skx-x128.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut4-p4h3ts-perm-div-x16.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut4-p4h3ts-perm-div-x32.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut4-p4h3ts-perm-div-x48.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut4-p4h3ts-perm-div-x64.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut4-p4h3ts-perm-div-x80.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut4-p4h3ts-perm-div-x96.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut4-p4h3ts-perm-div-x112.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut4-p4h3ts-perm-div-x128.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut4-p4h3ts-perm-div-x144.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut4-p4h3ts-perm-div-x160.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-x16.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-x32.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-x48.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-x64.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-x80.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-x96.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-x112.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-x128.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-x144.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj-x160.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-gather-div-x16.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-gather-div-x32.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-gather-div-x48.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-gather-div-x64.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-gather-div-x80.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-gather-div-x96.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-gather-div-x112.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-gather-div-x128.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-gather-div-x144.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-gather-div-x160.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-gather-nr1adj-x16.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-gather-nr1adj-x32.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-gather-nr1adj-x48.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-gather-nr1adj-x64.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-gather-nr1adj-x80.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-gather-nr1adj-x96.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-gather-nr1adj-x112.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-gather-nr1adj-x128.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-gather-nr1adj-x144.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-gather-nr1adj-x160.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-perm-div-x16.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-perm-div-x32.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-perm-div-x48.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-perm-div-x64.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-perm-div-x80.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-perm-div-x96.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-perm-div-x112.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-perm-div-x128.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-perm-div-x144.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-perm-div-x160.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-perm-nr1adj-x16.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-perm-nr1adj-x32.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-perm-nr1adj-x48.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-perm-nr1adj-x64.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-perm-nr1adj-x80.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-perm-nr1adj-x96.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-perm-nr1adj-x112.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-perm-nr1adj-x128.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-perm-nr1adj-x144.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-lut8-p4h3ts-perm-nr1adj-x160.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-p6h5ts-div-x16.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-p6h5ts-div-x32.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-p6h5ts-div-x48.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-p6h5ts-div-x64.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-p6h5ts-div-x80.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-p6h5ts-div-x96.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-p6h5ts-div-x112.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-p6h5ts-div-x128.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-p6h5ts-div-x144.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-p6h5ts-div-x160.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-p6h5ts-nr1-x16.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-p6h5ts-nr1-x32.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-p6h5ts-nr1-x48.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-p6h5ts-nr1-x64.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-p6h5ts-nr1-x80.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-p6h5ts-nr1-x96.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-p6h5ts-nr1-x112.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-p6h5ts-nr1-x128.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-p6h5ts-nr1-x144.c
  src/f32-vtanh/gen/f32-vtanh-avx512skx-expm1minus-rr1-p6h5ts-nr1-x160.c
  src/math/gen/f32-tanh-avx512skx-expm1minus-rr1-lut4-p4h3ts-perm-div.c
  src/math/gen/f32-tanh-avx512skx-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj.c
  src/math/gen/f32-tanh-avx512skx-expm1minus-rr1-lut8-p4h3ps-gather-div.c
  src/math/gen/f32-tanh-avx512skx-expm1minus-rr1-lut8-p4h3ps-gather-nr1.c
  src/math/gen/f32-tanh-avx512skx-expm1minus-rr1-lut8-p4h3ps-gather-nr1adj.c
  src/math/gen/f32-tanh-avx512skx-expm1minus-rr1-lut8-p4h3ps-perm-div.c
  src/math/gen/f32-tanh-avx512skx-expm1minus-rr1-lut8-p4h3ps-perm-nr1.c
  src/math/gen/f32-tanh-avx512skx-expm1minus-rr1-lut8-p4h3ps-perm-nr1adj.c
  src/math/gen/f32-tanh-avx512skx-expm1minus-rr1-p6h5ts-div.c
  src/math/gen/f32-tanh-avx512skx-expm1minus-rr1-p6h5ts-nr1.c
  src/math/gen/f32-tanh-avx512skx-expm1minus-rr1-p6h5ts-nr1adj.c
  src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x16c8-minmax-avx512skx.c
  src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x16c8-minmax-avx512skx.c
  src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-3x16c8-minmax-avx512skx.c
  src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-4x16c8-minmax-avx512skx.c
  src/qs8-dwconv/gen/qs8-dwconv-5f5m5l16c16s1r-minmax-fp32-avx512skx-mul32.c
  src/qs8-dwconv/gen/qs8-dwconv-5f5m5l32c16s1r-minmax-fp32-avx512skx-mul32.c
  src/qs8-dwconv/gen/qs8-dwconv-6f6m7l16c16s1r-minmax-fp32-avx512skx-mul32.c
  src/qs8-dwconv/gen/qs8-dwconv-6f6m7l32c16s1r-minmax-fp32-avx512skx-mul32.c
  src/qs8-dwconv/gen/qs8-dwconv-8f8m9l16c16s1r-minmax-fp32-avx512skx-mul32.c
  src/qs8-dwconv/gen/qs8-dwconv-8f8m9l32c16s1r-minmax-fp32-avx512skx-mul32.c
  src/qs8-dwconv/gen/qs8-dwconv-9p16c-minmax-fp32-avx512skx-mul32.c
  src/qs8-dwconv/gen/qs8-dwconv-9p32c-minmax-fp32-avx512skx-mul32.c
  src/qs8-dwconv/gen/qs8-dwconv-25p16c-minmax-fp32-avx512skx-mul32.c
  src/qs8-dwconv/gen/qs8-dwconv-25p32c-minmax-fp32-avx512skx-mul32.c
  src/qs8-f32-vcvt/gen/qs8-f32-vcvt-avx512skx-x16.c
  src/qs8-f32-vcvt/gen/qs8-f32-vcvt-avx512skx-x32.c
  src/qs8-f32-vcvt/gen/qs8-f32-vcvt-avx512skx-x48.c
  src/qs8-f32-vcvt/gen/qs8-f32-vcvt-avx512skx-x64.c
  src/qs8-gemm/gen/qs8-gemm-1x16c8-minmax-fp32-avx512skx.c
  src/qs8-gemm/gen/qs8-gemm-2x16c8-minmax-fp32-avx512skx.c
  src/qs8-gemm/gen/qs8-gemm-3x16c8-minmax-fp32-avx512skx.c
  src/qs8-gemm/gen/qs8-gemm-4x16c8-minmax-fp32-avx512skx.c
  src/qs8-igemm/gen/qs8-igemm-1x16c8-minmax-fp32-avx512skx.c
  src/qs8-igemm/gen/qs8-igemm-2x16c8-minmax-fp32-avx512skx.c
  src/qs8-igemm/gen/qs8-igemm-3x16c8-minmax-fp32-avx512skx.c
  src/qs8-igemm/gen/qs8-igemm-4x16c8-minmax-fp32-avx512skx.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-3p32c-minmax-fp32-avx512skx-mul32.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l16c16s1r-minmax-fp32-avx512skx-mul32.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l32c16s1r-minmax-fp32-avx512skx-mul32.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l16c16s1r-minmax-fp32-avx512skx-mul32.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l32c16s1r-minmax-fp32-avx512skx-mul32.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l16c16s1r-minmax-fp32-avx512skx-mul32.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l32c16s1r-minmax-fp32-avx512skx-mul32.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-avx512skx-mul32.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p32c-minmax-fp32-avx512skx-mul32.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-avx512skx-mul32.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p32c-minmax-fp32-avx512skx-mul32.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x16c8-minmax-fp32-avx512skx.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x16c8-minmax-fp32-avx512skx.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x16c8-minmax-fp32-avx512skx.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x16c8-minmax-fp32-avx512skx.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x16c8-minmax-fp32-avx512skx.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x16c8-minmax-fp32-avx512skx.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x16c8-minmax-fp32-avx512skx.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x16c8-minmax-fp32-avx512skx.c
  src/qs8-vadd/gen/qs8-vadd-minmax-avx512skx-mul32-ld128-x16.c
  src/qs8-vadd/gen/qs8-vadd-minmax-avx512skx-mul32-ld128-x32.c
  src/qs8-vaddc/gen/qs8-vaddc-minmax-avx512skx-mul32-ld128-x16.c
  src/qs8-vaddc/gen/qs8-vaddc-minmax-avx512skx-mul32-ld128-x32.c
  src/qu8-dwconv/gen/qu8-dwconv-5f5m5l16c16s1r-minmax-fp32-avx512skx-mul32.c
  src/qu8-dwconv/gen/qu8-dwconv-5f5m5l32c16s1r-minmax-fp32-avx512skx-mul32.c
  src/qu8-dwconv/gen/qu8-dwconv-6f6m7l16c16s1r-minmax-fp32-avx512skx-mul32.c
  src/qu8-dwconv/gen/qu8-dwconv-6f6m7l32c16s1r-minmax-fp32-avx512skx-mul32.c
  src/qu8-dwconv/gen/qu8-dwconv-8f8m9l16c16s1r-minmax-fp32-avx512skx-mul32.c
  src/qu8-dwconv/gen/qu8-dwconv-8f8m9l32c16s1r-minmax-fp32-avx512skx-mul32.c
  src/qu8-dwconv/gen/qu8-dwconv-9p16c-minmax-fp32-avx512skx-mul32.c
  src/qu8-dwconv/gen/qu8-dwconv-9p32c-minmax-fp32-avx512skx-mul32.c
  src/qu8-dwconv/gen/qu8-dwconv-25p16c-minmax-fp32-avx512skx-mul32.c
  src/qu8-dwconv/gen/qu8-dwconv-25p32c-minmax-fp32-avx512skx-mul32.c
  src/qu8-f32-vcvt/gen/qu8-f32-vcvt-avx512skx-x16.c
  src/qu8-f32-vcvt/gen/qu8-f32-vcvt-avx512skx-x32.c
  src/qu8-f32-vcvt/gen/qu8-f32-vcvt-avx512skx-x48.c
  src/qu8-f32-vcvt/gen/qu8-f32-vcvt-avx512skx-x64.c
  src/qu8-gemm/gen/qu8-gemm-1x16c8-minmax-fp32-avx512skx.c
  src/qu8-gemm/gen/qu8-gemm-2x16c8-minmax-fp32-avx512skx.c
  src/qu8-gemm/gen/qu8-gemm-3x16c8-minmax-fp32-avx512skx.c
  src/qu8-gemm/gen/qu8-gemm-4x16c8-minmax-fp32-avx512skx.c
  src/qu8-igemm/gen/qu8-igemm-1x16c8-minmax-fp32-avx512skx.c
  src/qu8-igemm/gen/qu8-igemm-2x16c8-minmax-fp32-avx512skx.c
  src/qu8-igemm/gen/qu8-igemm-3x16c8-minmax-fp32-avx512skx.c
  src/qu8-igemm/gen/qu8-igemm-4x16c8-minmax-fp32-avx512skx.c
  src/qu8-vadd/gen/qu8-vadd-minmax-avx512skx-mul32-ld128-x16.c
  src/qu8-vadd/gen/qu8-vadd-minmax-avx512skx-mul32-ld128-x32.c
  src/qu8-vaddc/gen/qu8-vaddc-minmax-avx512skx-mul32-ld128-x16.c
  src/qu8-vaddc/gen/qu8-vaddc-minmax-avx512skx-mul32-ld128-x32.c
  src/x8-lut/gen/x8-lut-avx512skx-vpshufb-x64.c
  src/x8-lut/gen/x8-lut-avx512skx-vpshufb-x128.c
  src/x8-lut/gen/x8-lut-avx512skx-vpshufb-x192.c
  src/x8-lut/gen/x8-lut-avx512skx-vpshufb-x256.c)

SET(ALL_AVX512VBMI_MICROKERNEL_SRCS
  src/x8-lut/gen/x8-lut-avx512vbmi-vpermx2b-x64.c
  src/x8-lut/gen/x8-lut-avx512vbmi-vpermx2b-x128.c
  src/x8-lut/gen/x8-lut-avx512vbmi-vpermx2b-x192.c
  src/x8-lut/gen/x8-lut-avx512vbmi-vpermx2b-x256.c)

SET(ALL_F16C_MICROKERNEL_SRCS
  src/f16-avgpool/f16-avgpool-9p8x-minmax-f16c-c8.c
  src/f16-avgpool/f16-avgpool-9x-minmax-f16c-c8.c
  src/f16-f32-vcvt/gen/f16-f32-vcvt-f16c-x8.c
  src/f16-f32-vcvt/gen/f16-f32-vcvt-f16c-x16.c
  src/f16-f32acc-rsum/gen/f16-f32acc-rsum-f16c-x8.c
  src/f16-f32acc-rsum/gen/f16-f32acc-rsum-f16c-x16-acc2.c
  src/f16-f32acc-rsum/gen/f16-f32acc-rsum-f16c-x24-acc3.c
  src/f16-f32acc-rsum/gen/f16-f32acc-rsum-f16c-x32-acc2.c
  src/f16-f32acc-rsum/gen/f16-f32acc-rsum-f16c-x32-acc4.c
  src/f16-gavgpool/gen/f16-gavgpool-7p7x-minmax-f16c-c8.c
  src/f16-gavgpool/gen/f16-gavgpool-7p7x-minmax-f16c-c16.c
  src/f16-gavgpool/gen/f16-gavgpool-7p7x-minmax-f16c-c24.c
  src/f16-gavgpool/gen/f16-gavgpool-7p7x-minmax-f16c-c32.c
  src/f16-gavgpool/gen/f16-gavgpool-7x-minmax-f16c-c8.c
  src/f16-gavgpool/gen/f16-gavgpool-7x-minmax-f16c-c16.c
  src/f16-gavgpool/gen/f16-gavgpool-7x-minmax-f16c-c24.c
  src/f16-gavgpool/gen/f16-gavgpool-7x-minmax-f16c-c32.c
  src/f16-maxpool/f16-maxpool-9p8x-minmax-f16c-c8.c
  src/f16-prelu/gen/f16-prelu-f16c-2x8.c
  src/f16-prelu/gen/f16-prelu-f16c-2x16.c
  src/f16-rmax/f16-rmax-f16c.c
  src/f16-vbinary/gen/f16-vadd-minmax-f16c-x8.c
  src/f16-vbinary/gen/f16-vadd-minmax-f16c-x16.c
  src/f16-vbinary/gen/f16-vaddc-minmax-f16c-x8.c
  src/f16-vbinary/gen/f16-vaddc-minmax-f16c-x16.c
  src/f16-vbinary/gen/f16-vdiv-minmax-f16c-x8.c
  src/f16-vbinary/gen/f16-vdiv-minmax-f16c-x16.c
  src/f16-vbinary/gen/f16-vdivc-minmax-f16c-x8.c
  src/f16-vbinary/gen/f16-vdivc-minmax-f16c-x16.c
  src/f16-vbinary/gen/f16-vmax-f16c-x8.c
  src/f16-vbinary/gen/f16-vmax-f16c-x16.c
  src/f16-vbinary/gen/f16-vmaxc-f16c-x8.c
  src/f16-vbinary/gen/f16-vmaxc-f16c-x16.c
  src/f16-vbinary/gen/f16-vmin-f16c-x8.c
  src/f16-vbinary/gen/f16-vmin-f16c-x16.c
  src/f16-vbinary/gen/f16-vminc-f16c-x8.c
  src/f16-vbinary/gen/f16-vminc-f16c-x16.c
  src/f16-vbinary/gen/f16-vmul-minmax-f16c-x8.c
  src/f16-vbinary/gen/f16-vmul-minmax-f16c-x16.c
  src/f16-vbinary/gen/f16-vmulc-minmax-f16c-x8.c
  src/f16-vbinary/gen/f16-vmulc-minmax-f16c-x16.c
  src/f16-vbinary/gen/f16-vrdivc-minmax-f16c-x8.c
  src/f16-vbinary/gen/f16-vrdivc-minmax-f16c-x16.c
  src/f16-vbinary/gen/f16-vrsubc-minmax-f16c-x8.c
  src/f16-vbinary/gen/f16-vrsubc-minmax-f16c-x16.c
  src/f16-vbinary/gen/f16-vsqrdiff-f16c-x8.c
  src/f16-vbinary/gen/f16-vsqrdiff-f16c-x16.c
  src/f16-vbinary/gen/f16-vsqrdiffc-f16c-x8.c
  src/f16-vbinary/gen/f16-vsqrdiffc-f16c-x16.c
  src/f16-vbinary/gen/f16-vsub-minmax-f16c-x8.c
  src/f16-vbinary/gen/f16-vsub-minmax-f16c-x16.c
  src/f16-vbinary/gen/f16-vsubc-minmax-f16c-x8.c
  src/f16-vbinary/gen/f16-vsubc-minmax-f16c-x16.c
  src/f16-vclamp/gen/f16-vclamp-f16c-x8.c
  src/f16-vclamp/gen/f16-vclamp-f16c-x16.c
  src/f16-vhswish/gen/f16-vhswish-f16c-x8.c
  src/f16-vhswish/gen/f16-vhswish-f16c-x16.c
  src/f16-vlrelu/gen/f16-vlrelu-f16c-x8.c
  src/f16-vlrelu/gen/f16-vlrelu-f16c-x16.c
  src/f16-vrnd/gen/f16-vrndd-f16c-x8.c
  src/f16-vrnd/gen/f16-vrndd-f16c-x16.c
  src/f16-vrnd/gen/f16-vrndne-f16c-x8.c
  src/f16-vrnd/gen/f16-vrndne-f16c-x16.c
  src/f16-vrnd/gen/f16-vrndu-f16c-x8.c
  src/f16-vrnd/gen/f16-vrndu-f16c-x16.c
  src/f16-vrnd/gen/f16-vrndz-f16c-x8.c
  src/f16-vrnd/gen/f16-vrndz-f16c-x16.c
  src/f16-vsqrt/gen/f16-vsqrt-f16c-sqrt-x8.c
  src/f16-vsqrt/gen/f16-vsqrt-f16c-sqrt-x16.c
  src/f16-vtanh/gen/f16-vtanh-f16c-expm1minus-rr1-p3h2ts-div-x8.c
  src/f16-vtanh/gen/f16-vtanh-f16c-expm1minus-rr1-p3h2ts-div-x16.c
  src/f16-vtanh/gen/f16-vtanh-f16c-expm1minus-rr1-p3h2ts-div-x24.c
  src/f16-vtanh/gen/f16-vtanh-f16c-expm1minus-rr1-p3h2ts-div-x32.c
  src/f16-vtanh/gen/f16-vtanh-f16c-expm1minus-rr1-p3h2ts-div-x40.c
  src/f16-vtanh/gen/f16-vtanh-f16c-expm1minus-rr1-p3h2ts-div-x48.c
  src/f16-vtanh/gen/f16-vtanh-f16c-expm1minus-rr1-p3h2ts-div-x56.c
  src/f16-vtanh/gen/f16-vtanh-f16c-expm1minus-rr1-p3h2ts-div-x64.c
  src/f16-vtanh/gen/f16-vtanh-f16c-expm1minus-rr1-p3h2ts-div-x72.c
  src/f16-vtanh/gen/f16-vtanh-f16c-expm1minus-rr1-p3h2ts-div-x80.c
  src/f16-vtanh/gen/f16-vtanh-f16c-expm1minus-rr1-p3h2ts-rcp-x8.c
  src/f16-vtanh/gen/f16-vtanh-f16c-expm1minus-rr1-p3h2ts-rcp-x16.c
  src/f16-vtanh/gen/f16-vtanh-f16c-expm1minus-rr1-p3h2ts-rcp-x24.c
  src/f16-vtanh/gen/f16-vtanh-f16c-expm1minus-rr1-p3h2ts-rcp-x32.c
  src/f16-vtanh/gen/f16-vtanh-f16c-expm1minus-rr1-p3h2ts-rcp-x40.c
  src/f16-vtanh/gen/f16-vtanh-f16c-expm1minus-rr1-p3h2ts-rcp-x48.c
  src/f16-vtanh/gen/f16-vtanh-f16c-expm1minus-rr1-p3h2ts-rcp-x56.c
  src/f16-vtanh/gen/f16-vtanh-f16c-expm1minus-rr1-p3h2ts-rcp-x64.c
  src/f16-vtanh/gen/f16-vtanh-f16c-expm1minus-rr1-p3h2ts-rcp-x72.c
  src/f16-vtanh/gen/f16-vtanh-f16c-expm1minus-rr1-p3h2ts-rcp-x80.c
  src/f16-vtanh/gen/f16-vtanh-f16c-polynomial-p19h9t2-x8.c
  src/f16-vtanh/gen/f16-vtanh-f16c-polynomial-p19h9t2-x16.c
  src/f16-vtanh/gen/f16-vtanh-f16c-polynomial-p19h9t2-x24.c
  src/f16-vtanh/gen/f16-vtanh-f16c-polynomial-p19h9t2-x32.c
  src/f16-vtanh/gen/f16-vtanh-f16c-polynomial-p19h9t2-x40.c
  src/f16-vtanh/gen/f16-vtanh-f16c-polynomial-p19h9t2-x48.c
  src/f16-vtanh/gen/f16-vtanh-f16c-polynomial-p19h9t2-x56.c
  src/f16-vtanh/gen/f16-vtanh-f16c-polynomial-p19h9t2-x64.c
  src/f16-vtanh/gen/f16-vtanh-f16c-polynomial-p19h9t2-x72.c
  src/f16-vtanh/gen/f16-vtanh-f16c-polynomial-p19h9t2-x80.c
  src/f16-vunary/gen/f16-vsqr-f16c-x8.c
  src/f16-vunary/gen/f16-vsqr-f16c-x16.c
  src/f32-f16-vcvt/gen/f32-f16-vcvt-f16c-x8.c
  src/f32-f16-vcvt/gen/f32-f16-vcvt-f16c-x16.c
  src/math/f16-f32-cvt-f16c.c
  src/math/f32-f16-cvt-f16c.c
  src/math/gen/f16-tanh-f16c-expm1minus-rr1-p3h2ts-div.c
  src/math/gen/f16-tanh-f16c-expm1minus-rr1-p3h2ts-rcp.c
  src/math/gen/f16-tanh-f16c-polynomial-p17h8t2.c
  src/math/gen/f16-tanh-f16c-polynomial-p19h9t2.c)

SET(ALL_FMA_MICROKERNEL_SRCS
  src/f32-vtanh/gen/f32-vtanh-fma-expm1minus-rr1-lut8-p4h3ts-div-x1.c
  src/f32-vtanh/gen/f32-vtanh-fma-expm1minus-rr1-lut8-p4h3ts-div-x2.c
  src/f32-vtanh/gen/f32-vtanh-fma-expm1minus-rr1-lut8-p4h3ts-div-x4.c
  src/f32-vtanh/gen/f32-vtanh-fma-expm1minus-rr1-p6h5ts-div-x1.c
  src/f32-vtanh/gen/f32-vtanh-fma-expm1minus-rr1-p6h5ts-div-x2.c
  src/f32-vtanh/gen/f32-vtanh-fma-expm1minus-rr1-p6h5ts-div-x4.c
  src/math/gen/f32-tanh-fma-expm1minus-rr1-lut4-p4h2ts-div.c
  src/math/gen/f32-tanh-fma-expm1minus-rr1-lut4-p4h2ts-rcp.c
  src/math/gen/f32-tanh-fma-expm1minus-rr1-lut4-p4h3ps-div.c
  src/math/gen/f32-tanh-fma-expm1minus-rr1-lut4-p4h3ps-rcp.c
  src/math/gen/f32-tanh-fma-expm1minus-rr1-lut4-p4h3ts-div.c
  src/math/gen/f32-tanh-fma-expm1minus-rr1-lut4-p4h3ts-rcp.c
  src/math/gen/f32-tanh-fma-expm1minus-rr1-lut8-p3h1ts-div.c
  src/math/gen/f32-tanh-fma-expm1minus-rr1-lut8-p4h2ts-div.c
  src/math/gen/f32-tanh-fma-expm1minus-rr1-lut8-p4h2ts-rcp.c
  src/math/gen/f32-tanh-fma-expm1minus-rr1-lut8-p4h3ps-div.c
  src/math/gen/f32-tanh-fma-expm1minus-rr1-lut8-p4h3ps-rcp.c
  src/math/gen/f32-tanh-fma-expm1minus-rr1-lut8-p4h3ts-div.c
  src/math/gen/f32-tanh-fma-expm1minus-rr1-lut8-p4h3ts-rcp.c
  src/math/gen/f32-tanh-fma-expm1minus-rr1-lut16-p3h1ts-div.c
  src/math/gen/f32-tanh-fma-expm1minus-rr1-lut16-p4h2ts-div.c
  src/math/gen/f32-tanh-fma-expm1minus-rr1-lut16-p4h2ts-rcp.c
  src/math/gen/f32-tanh-fma-expm1minus-rr1-lut16-p4h3ps-div.c
  src/math/gen/f32-tanh-fma-expm1minus-rr1-lut16-p4h3ts-div.c
  src/math/gen/f32-tanh-fma-expm1minus-rr1-lut32-p3h1ts-div.c
  src/math/gen/f32-tanh-fma-expm1minus-rr1-lut64-p3h1ts-div.c
  src/math/gen/f32-tanh-fma-expm1minus-rr1-p6h4ts-div.c
  src/math/gen/f32-tanh-fma-expm1minus-rr1-p6h5ps-div.c
  src/math/gen/f32-tanh-fma-expm1minus-rr1-p6h5ps-rcp.c
  src/math/gen/f32-tanh-fma-expm1minus-rr1-p6h5ts-div.c
  src/math/gen/f32-tanh-fma-expm1minus-rr1-p6h5ts-rcp.c
  src/math/gen/f32-tanh-fma-expm1minus-rr2-lut4-p4h2ts-div.c
  src/math/gen/f32-tanh-fma-expm1minus-rr2-lut4-p4h3ps-div.c
  src/math/gen/f32-tanh-fma-expm1minus-rr2-lut4-p4h3ts-div.c
  src/math/gen/f32-tanh-fma-expm1minus-rr2-lut8-p3h1ts-div.c
  src/math/gen/f32-tanh-fma-expm1minus-rr2-lut8-p4h2ts-div.c
  src/math/gen/f32-tanh-fma-expm1minus-rr2-lut8-p4h2ts-rcp.c
  src/math/gen/f32-tanh-fma-expm1minus-rr2-lut8-p4h3ps-div.c
  src/math/gen/f32-tanh-fma-expm1minus-rr2-lut8-p4h3ts-div.c
  src/math/gen/f32-tanh-fma-expm1minus-rr2-lut16-p3h1ts-div.c
  src/math/gen/f32-tanh-fma-expm1minus-rr2-lut16-p4h2ts-div.c
  src/math/gen/f32-tanh-fma-expm1minus-rr2-lut16-p4h3ps-div.c
  src/math/gen/f32-tanh-fma-expm1minus-rr2-lut16-p4h3ts-div.c
  src/math/gen/f32-tanh-fma-expm1minus-rr2-lut32-p3h1ts-div.c
  src/math/gen/f32-tanh-fma-expm1minus-rr2-lut64-p3h1ts-div.c
  src/math/gen/f32-tanh-fma-expm1minus-rr2-p6h4ts-div.c
  src/math/gen/f32-tanh-fma-expm1minus-rr2-p6h5ps-div.c
  src/math/gen/f32-tanh-fma-expm1minus-rr2-p6h5ts-div.c
  src/math/gen/f32-tanh-fma-expm1plus-rr1-lut4-p4h2ts-div.c
  src/math/gen/f32-tanh-fma-expm1plus-rr1-lut4-p4h3ps-div.c
  src/math/gen/f32-tanh-fma-expm1plus-rr1-lut4-p4h3ts-div.c
  src/math/gen/f32-tanh-fma-expm1plus-rr1-lut8-p3h1ts-div.c
  src/math/gen/f32-tanh-fma-expm1plus-rr1-lut8-p4h2ts-div.c
  src/math/gen/f32-tanh-fma-expm1plus-rr1-lut8-p4h3ps-div.c
  src/math/gen/f32-tanh-fma-expm1plus-rr1-lut8-p4h3ts-div.c
  src/math/gen/f32-tanh-fma-expm1plus-rr1-lut16-p3h1ts-div.c
  src/math/gen/f32-tanh-fma-expm1plus-rr1-lut16-p4h2ts-div.c
  src/math/gen/f32-tanh-fma-expm1plus-rr1-lut16-p4h3ps-div.c
  src/math/gen/f32-tanh-fma-expm1plus-rr1-lut16-p4h3ts-div.c
  src/math/gen/f32-tanh-fma-expm1plus-rr1-lut32-p3h1ts-div.c
  src/math/gen/f32-tanh-fma-expm1plus-rr1-lut64-p3h1ts-div.c
  src/math/gen/f32-tanh-fma-expm1plus-rr1-p6h4ts-div.c
  src/math/gen/f32-tanh-fma-expm1plus-rr1-p6h5ps-div.c
  src/math/gen/f32-tanh-fma-expm1plus-rr1-p6h5ts-div.c
  src/math/gen/f32-tanh-fma-expm1plus-rr2-lut4-p4h2ts-div.c
  src/math/gen/f32-tanh-fma-expm1plus-rr2-lut4-p4h3ps-div.c
  src/math/gen/f32-tanh-fma-expm1plus-rr2-lut4-p4h3ts-div.c
  src/math/gen/f32-tanh-fma-expm1plus-rr2-lut8-p3h1ts-div.c
  src/math/gen/f32-tanh-fma-expm1plus-rr2-lut8-p4h2ts-div.c
  src/math/gen/f32-tanh-fma-expm1plus-rr2-lut8-p4h3ps-div.c
  src/math/gen/f32-tanh-fma-expm1plus-rr2-lut8-p4h3ts-div.c
  src/math/gen/f32-tanh-fma-expm1plus-rr2-lut16-p3h1ts-div.c
  src/math/gen/f32-tanh-fma-expm1plus-rr2-lut16-p4h2ts-div.c
  src/math/gen/f32-tanh-fma-expm1plus-rr2-lut16-p4h3ps-div.c
  src/math/gen/f32-tanh-fma-expm1plus-rr2-lut16-p4h3ts-div.c
  src/math/gen/f32-tanh-fma-expm1plus-rr2-lut32-p3h1ts-div.c
  src/math/gen/f32-tanh-fma-expm1plus-rr2-lut64-p3h1ts-div.c
  src/math/gen/f32-tanh-fma-expm1plus-rr2-p6h4ts-div.c
  src/math/gen/f32-tanh-fma-expm1plus-rr2-p6h5ps-div.c
  src/math/gen/f32-tanh-fma-expm1plus-rr2-p6h5ts-div.c)

SET(ALL_FMA3_MICROKERNEL_SRCS
  src/f16-dwconv/gen/f16-dwconv-3p8c-minmax-fma3-acc2.c
  src/f16-dwconv/gen/f16-dwconv-3p8c-minmax-fma3.c
  src/f16-dwconv/gen/f16-dwconv-3p16c-minmax-fma3-acc2.c
  src/f16-dwconv/gen/f16-dwconv-3p16c-minmax-fma3.c
  src/f16-dwconv/gen/f16-dwconv-3p32c-minmax-fma3-acc2.c
  src/f16-dwconv/gen/f16-dwconv-3p32c-minmax-fma3.c
  src/f16-dwconv/gen/f16-dwconv-4p8c-minmax-fma3-acc2.c
  src/f16-dwconv/gen/f16-dwconv-4p8c-minmax-fma3.c
  src/f16-dwconv/gen/f16-dwconv-4p16c-minmax-fma3-acc2.c
  src/f16-dwconv/gen/f16-dwconv-4p16c-minmax-fma3.c
  src/f16-dwconv/gen/f16-dwconv-4p32c-minmax-fma3-acc2.c
  src/f16-dwconv/gen/f16-dwconv-4p32c-minmax-fma3.c
  src/f16-dwconv/gen/f16-dwconv-5f5m5l8c8s4r-minmax-fma3-acc2.c
  src/f16-dwconv/gen/f16-dwconv-5f5m5l8c8s4r-minmax-fma3.c
  src/f16-dwconv/gen/f16-dwconv-5f5m5l16c8s4r-minmax-fma3-acc2.c
  src/f16-dwconv/gen/f16-dwconv-5f5m5l16c8s4r-minmax-fma3.c
  src/f16-dwconv/gen/f16-dwconv-5f5m5l32c8s4r-minmax-fma3-acc2.c
  src/f16-dwconv/gen/f16-dwconv-5f5m5l32c8s4r-minmax-fma3.c
  src/f16-dwconv/gen/f16-dwconv-6f6m7l8c8s4r-minmax-fma3-acc2.c
  src/f16-dwconv/gen/f16-dwconv-6f6m7l8c8s4r-minmax-fma3.c
  src/f16-dwconv/gen/f16-dwconv-6f6m7l16c8s4r-minmax-fma3-acc2.c
  src/f16-dwconv/gen/f16-dwconv-6f6m7l16c8s4r-minmax-fma3.c
  src/f16-dwconv/gen/f16-dwconv-6f6m7l32c8s4r-minmax-fma3-acc2.c
  src/f16-dwconv/gen/f16-dwconv-6f6m7l32c8s4r-minmax-fma3.c
  src/f16-dwconv/gen/f16-dwconv-8f8m9l8c8s4r-minmax-fma3-acc2.c
  src/f16-dwconv/gen/f16-dwconv-8f8m9l8c8s4r-minmax-fma3.c
  src/f16-dwconv/gen/f16-dwconv-8f8m9l16c8s4r-minmax-fma3-acc2.c
  src/f16-dwconv/gen/f16-dwconv-8f8m9l16c8s4r-minmax-fma3.c
  src/f16-dwconv/gen/f16-dwconv-8f8m9l32c8s4r-minmax-fma3-acc2.c
  src/f16-dwconv/gen/f16-dwconv-8f8m9l32c8s4r-minmax-fma3.c
  src/f16-dwconv/gen/f16-dwconv-9p8c-minmax-fma3-acc2.c
  src/f16-dwconv/gen/f16-dwconv-9p8c-minmax-fma3.c
  src/f16-dwconv/gen/f16-dwconv-9p16c-minmax-fma3-acc2.c
  src/f16-dwconv/gen/f16-dwconv-9p16c-minmax-fma3.c
  src/f16-dwconv/gen/f16-dwconv-9p32c-minmax-fma3-acc2.c
  src/f16-dwconv/gen/f16-dwconv-9p32c-minmax-fma3.c
  src/f16-dwconv/gen/f16-dwconv-25p8c-minmax-fma3-acc2.c
  src/f16-dwconv/gen/f16-dwconv-25p8c-minmax-fma3.c
  src/f16-dwconv/gen/f16-dwconv-25p16c-minmax-fma3-acc2.c
  src/f16-dwconv/gen/f16-dwconv-25p16c-minmax-fma3.c
  src/f16-dwconv/gen/f16-dwconv-25p32c-minmax-fma3-acc2.c
  src/f16-dwconv/gen/f16-dwconv-25p32c-minmax-fma3.c
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  src/math/gen/f32-tanh-fma3-expm1minus-rr1-lut4-p4h3ts-perm-div.c
  src/math/gen/f32-tanh-fma3-expm1minus-rr1-lut4-p4h3ts-perm-nr1adj.c
  src/math/gen/f32-tanh-fma3-expm1minus-rr1-lut8-p4h3ps-div.c
  src/math/gen/f32-tanh-fma3-expm1minus-rr1-lut8-p4h3ps-nr1.c
  src/math/gen/f32-tanh-fma3-expm1minus-rr1-lut8-p4h3ps-nr1adj.c
  src/math/gen/f32-tanh-fma3-expm1minus-rr1-p6h5ts-div.c
  src/math/gen/f32-tanh-fma3-expm1minus-rr1-p6h5ts-nr1.c
  src/math/gen/f32-tanh-fma3-expm1minus-rr1-p6h5ts-nr1adj.c)

SET(ALL_FP16ARITH_MICROKERNEL_SRCS
  src/f16-vbinary/gen/f16-vadd-minmax-fp16arith-x1.c
  src/f16-vbinary/gen/f16-vadd-minmax-fp16arith-x2.c
  src/f16-vbinary/gen/f16-vadd-minmax-fp16arith-x4.c
  src/f16-vbinary/gen/f16-vaddc-minmax-fp16arith-x1.c
  src/f16-vbinary/gen/f16-vaddc-minmax-fp16arith-x2.c
  src/f16-vbinary/gen/f16-vaddc-minmax-fp16arith-x4.c
  src/f16-vbinary/gen/f16-vdiv-minmax-fp16arith-x1.c
  src/f16-vbinary/gen/f16-vdiv-minmax-fp16arith-x2.c
  src/f16-vbinary/gen/f16-vdiv-minmax-fp16arith-x4.c
  src/f16-vbinary/gen/f16-vdivc-minmax-fp16arith-x1.c
  src/f16-vbinary/gen/f16-vdivc-minmax-fp16arith-x2.c
  src/f16-vbinary/gen/f16-vdivc-minmax-fp16arith-x4.c
  src/f16-vbinary/gen/f16-vmax-fp16arith-x1.c
  src/f16-vbinary/gen/f16-vmax-fp16arith-x2.c
  src/f16-vbinary/gen/f16-vmax-fp16arith-x4.c
  src/f16-vbinary/gen/f16-vmaxc-fp16arith-x1.c
  src/f16-vbinary/gen/f16-vmaxc-fp16arith-x2.c
  src/f16-vbinary/gen/f16-vmaxc-fp16arith-x4.c
  src/f16-vbinary/gen/f16-vmin-fp16arith-x1.c
  src/f16-vbinary/gen/f16-vmin-fp16arith-x2.c
  src/f16-vbinary/gen/f16-vmin-fp16arith-x4.c
  src/f16-vbinary/gen/f16-vminc-fp16arith-x1.c
  src/f16-vbinary/gen/f16-vminc-fp16arith-x2.c
  src/f16-vbinary/gen/f16-vminc-fp16arith-x4.c
  src/f16-vbinary/gen/f16-vmul-minmax-fp16arith-x1.c
  src/f16-vbinary/gen/f16-vmul-minmax-fp16arith-x2.c
  src/f16-vbinary/gen/f16-vmul-minmax-fp16arith-x4.c
  src/f16-vbinary/gen/f16-vmulc-minmax-fp16arith-x1.c
  src/f16-vbinary/gen/f16-vmulc-minmax-fp16arith-x2.c
  src/f16-vbinary/gen/f16-vmulc-minmax-fp16arith-x4.c
  src/f16-vbinary/gen/f16-vrdivc-minmax-fp16arith-x1.c
  src/f16-vbinary/gen/f16-vrdivc-minmax-fp16arith-x2.c
  src/f16-vbinary/gen/f16-vrdivc-minmax-fp16arith-x4.c
  src/f16-vbinary/gen/f16-vrsubc-minmax-fp16arith-x1.c
  src/f16-vbinary/gen/f16-vrsubc-minmax-fp16arith-x2.c
  src/f16-vbinary/gen/f16-vrsubc-minmax-fp16arith-x4.c
  src/f16-vbinary/gen/f16-vsqrdiff-fp16arith-x1.c
  src/f16-vbinary/gen/f16-vsqrdiff-fp16arith-x2.c
  src/f16-vbinary/gen/f16-vsqrdiff-fp16arith-x4.c
  src/f16-vbinary/gen/f16-vsqrdiffc-fp16arith-x1.c
  src/f16-vbinary/gen/f16-vsqrdiffc-fp16arith-x2.c
  src/f16-vbinary/gen/f16-vsqrdiffc-fp16arith-x4.c
  src/f16-vbinary/gen/f16-vsub-minmax-fp16arith-x1.c
  src/f16-vbinary/gen/f16-vsub-minmax-fp16arith-x2.c
  src/f16-vbinary/gen/f16-vsub-minmax-fp16arith-x4.c
  src/f16-vbinary/gen/f16-vsubc-minmax-fp16arith-x1.c
  src/f16-vbinary/gen/f16-vsubc-minmax-fp16arith-x2.c
  src/f16-vbinary/gen/f16-vsubc-minmax-fp16arith-x4.c
  src/f16-vsqrt/gen/f16-vsqrt-fp16arith-sqrt-x1.c
  src/f16-vsqrt/gen/f16-vsqrt-fp16arith-sqrt-x2.c
  src/f16-vsqrt/gen/f16-vsqrt-fp16arith-sqrt-x4.c)

SET(ALL_HEXAGON_MICROKERNEL_SRCS
  src/cs16-vsquareabs/gen/cs16-vsquareabs-hexagon-x2.c
  src/cs16-vsquareabs/gen/cs16-vsquareabs-hexagon-x4.c
  src/cs16-vsquareabs/gen/cs16-vsquareabs-hexagon-x6.c
  src/cs16-vsquareabs/gen/cs16-vsquareabs-hexagon-x8.c
  src/cs16-vsquareabs/gen/cs16-vsquareabs-hexagon-x10.c
  src/cs16-vsquareabs/gen/cs16-vsquareabs-hexagon-x12.c)

SET(ALL_NEON_MICROKERNEL_SRCS
  src/cs16-bfly4/cs16-bfly4-neon-x1.c
  src/cs16-bfly4/cs16-bfly4-neon-x4.c
  src/cs16-bfly4/cs16-bfly4-samples1-neon.c
  src/cs16-bfly4/cs16-bfly4-samples4-neon.c
  src/cs16-fftr/cs16-fftr-neon-x4.c
  src/cs16-vsquareabs/gen/cs16-vsquareabs-neon-mlal-ld128-x4.c
  src/cs16-vsquareabs/gen/cs16-vsquareabs-neon-mlal-ld128-x8.c
  src/cs16-vsquareabs/gen/cs16-vsquareabs-neon-mlal-ld128-x12.c
  src/cs16-vsquareabs/gen/cs16-vsquareabs-neon-mlal-ld128-x16.c
  src/f16-f32-vcvt/gen/f16-f32-vcvt-neon-int16-x8.c
  src/f16-f32-vcvt/gen/f16-f32-vcvt-neon-int16-x16.c
  src/f16-f32-vcvt/gen/f16-f32-vcvt-neon-int16-x24.c
  src/f16-f32-vcvt/gen/f16-f32-vcvt-neon-int16-x32.c
  src/f16-f32-vcvt/gen/f16-f32-vcvt-neon-int32-x8.c
  src/f16-f32-vcvt/gen/f16-f32-vcvt-neon-int32-x16.c
  src/f16-f32-vcvt/gen/f16-f32-vcvt-neon-int32-x24.c
  src/f16-f32-vcvt/gen/f16-f32-vcvt-neon-int32-x32.c
  src/f32-argmaxpool/f32-argmaxpool-4x-neon-c4.c
  src/f32-argmaxpool/f32-argmaxpool-9p8x-neon-c4.c
  src/f32-argmaxpool/f32-argmaxpool-9x-neon-c4.c
  src/f32-avgpool/f32-avgpool-9p8x-minmax-neon-c4.c
  src/f32-avgpool/f32-avgpool-9x-minmax-neon-c4.c
  src/f32-conv-hwc2chw/f32-conv-hwc2chw-3x3s2p1c3x4-neon-2x2.c
  src/f32-conv-hwc/gen/f32-conv-hwc-3x3s2p0p1c3x4-neon-2x1.c
  src/f32-conv-hwc/gen/f32-conv-hwc-3x3s2p0p1c3x4-neon-2x2.c
  src/f32-conv-hwc/gen/f32-conv-hwc-3x3s2p0p1c3x8-neon-2x1.c
  src/f32-conv-hwc/gen/f32-conv-hwc-3x3s2p0p1c3x8-neon-2x2.c
  src/f32-conv-hwc/gen/f32-conv-hwc-3x3s2p1c3x4-neon-2x1.c
  src/f32-conv-hwc/gen/f32-conv-hwc-3x3s2p1c3x4-neon-2x2.c
  src/f32-conv-hwc/gen/f32-conv-hwc-3x3s2p1c3x8-neon-2x1.c
  src/f32-conv-hwc/gen/f32-conv-hwc-3x3s2p1c3x8-neon-2x2.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-neon-1x4-acc2.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-neon-1x4-acc3.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-neon-1x4-acc4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-neon-1x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-neon-2x4-acc2.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-neon-2x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-neon-3x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-neon-4x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-neon-5x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-neon-6x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-neon-1x4-acc2.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-neon-1x4-acc3.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-neon-1x4-acc4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-neon-1x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-neon-2x4-acc2.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-neon-2x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-neon-3x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-neon-4x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-neon-1x4-acc2.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-neon-1x4-acc3.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-neon-1x4-acc4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-neon-1x4-acc5.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-neon-1x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-neon-2x4-acc2.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-neon-2x4-acc3.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-neon-2x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-neon-3x4-acc2.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-neon-3x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-neon-4x4-acc2.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-neon-4x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-neon-5x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-neon-1x4-acc2.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-neon-1x4-acc3.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-neon-1x4-acc4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-neon-1x4-acc5.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-neon-1x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-neon-2x4-acc2.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-neon-2x4-acc3.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-neon-2x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-neon-3x4-acc2.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-neon-3x4.c
  src/f32-dwconv/gen/f32-dwconv-2f2m2l4c4s4r-minmax-neon-acc2.c
  src/f32-dwconv/gen/f32-dwconv-2f2m2l4c4s4r-minmax-neon.c
  src/f32-dwconv/gen/f32-dwconv-2f2m2l8c4s4r-minmax-neon-acc2.c
  src/f32-dwconv/gen/f32-dwconv-2f2m2l8c4s4r-minmax-neon.c
  src/f32-dwconv/gen/f32-dwconv-2f2m2l16c4s4r-minmax-neon-acc2.c
  src/f32-dwconv/gen/f32-dwconv-2f2m2l16c4s4r-minmax-neon.c
  src/f32-dwconv/gen/f32-dwconv-3p4c-minmax-neon-acc2.c
  src/f32-dwconv/gen/f32-dwconv-3p4c-minmax-neon.c
  src/f32-dwconv/gen/f32-dwconv-3p8c-minmax-neon-acc2.c
  src/f32-dwconv/gen/f32-dwconv-3p8c-minmax-neon.c
  src/f32-dwconv/gen/f32-dwconv-3p16c-minmax-neon-acc2.c
  src/f32-dwconv/gen/f32-dwconv-3p16c-minmax-neon.c
  src/f32-dwconv/gen/f32-dwconv-4p4c-minmax-neon-acc2.c
  src/f32-dwconv/gen/f32-dwconv-4p4c-minmax-neon.c
  src/f32-dwconv/gen/f32-dwconv-4p8c-minmax-neon-acc2.c
  src/f32-dwconv/gen/f32-dwconv-4p8c-minmax-neon.c
  src/f32-dwconv/gen/f32-dwconv-4p16c-minmax-neon-acc2.c
  src/f32-dwconv/gen/f32-dwconv-4p16c-minmax-neon.c
  src/f32-dwconv/gen/f32-dwconv-5f5m5l4c4s4r-minmax-neon-acc2.c
  src/f32-dwconv/gen/f32-dwconv-5f5m5l4c4s4r-minmax-neon.c
  src/f32-dwconv/gen/f32-dwconv-5f5m5l8c4s4r-minmax-neon-acc2.c
  src/f32-dwconv/gen/f32-dwconv-5f5m5l8c4s4r-minmax-neon.c
  src/f32-dwconv/gen/f32-dwconv-6f6m7l4c4s4r-minmax-neon-acc2.c
  src/f32-dwconv/gen/f32-dwconv-6f6m7l4c4s4r-minmax-neon.c
  src/f32-dwconv/gen/f32-dwconv-6f6m7l8c4s4r-minmax-neon-acc2.c
  src/f32-dwconv/gen/f32-dwconv-6f6m7l8c4s4r-minmax-neon.c
  src/f32-dwconv/gen/f32-dwconv-8f8m9l4c4s4r-minmax-neon-acc2.c
  src/f32-dwconv/gen/f32-dwconv-8f8m9l4c4s4r-minmax-neon.c
  src/f32-dwconv/gen/f32-dwconv-8f8m9l8c4s4r-minmax-neon-acc2.c
  src/f32-dwconv/gen/f32-dwconv-8f8m9l8c4s4r-minmax-neon.c
  src/f32-dwconv/gen/f32-dwconv-9p4c-minmax-neon-acc2.c
  src/f32-dwconv/gen/f32-dwconv-9p4c-minmax-neon.c
  src/f32-dwconv/gen/f32-dwconv-9p8c-minmax-neon-acc2.c
  src/f32-dwconv/gen/f32-dwconv-9p8c-minmax-neon.c
  src/f32-dwconv/gen/f32-dwconv-9p16c-minmax-neon-acc2.c
  src/f32-dwconv/gen/f32-dwconv-9p16c-minmax-neon.c
  src/f32-dwconv/gen/f32-dwconv-25p4c-minmax-neon-acc2.c
  src/f32-dwconv/gen/f32-dwconv-25p4c-minmax-neon.c
  src/f32-dwconv/gen/f32-dwconv-25p8c-minmax-neon-acc2.c
  src/f32-dwconv/gen/f32-dwconv-25p8c-minmax-neon.c
  src/f32-dwconv/gen/f32-dwconv-25p16c-minmax-neon-acc2.c
  src/f32-dwconv/gen/f32-dwconv-25p16c-minmax-neon.c
  src/f32-f16-vcvt/gen/f32-f16-vcvt-neon-x8.c
  src/f32-f16-vcvt/gen/f32-f16-vcvt-neon-x16.c
  src/f32-f16-vcvt/gen/f32-f16-vcvt-neon-x24.c
  src/f32-f16-vcvt/gen/f32-f16-vcvt-neon-x32.c
  src/f32-gavgpool-cw/f32-gavgpool-cw-neon-x4.c
  src/f32-gavgpool/f32-gavgpool-7p7x-minmax-neon-c4.c
  src/f32-gavgpool/f32-gavgpool-7x-minmax-neon-c4.c
  src/f32-gemm/gen/f32-gemm-1x8-minmax-neon-dup-ld64.c
  src/f32-gemm/gen/f32-gemm-1x8-minmax-neon-lane-ld64.c
  src/f32-gemm/gen/f32-gemm-1x8s4-minmax-neon.c
  src/f32-gemm/gen/f32-gemm-4x2-minmax-neon-lane-ld64.c
  src/f32-gemm/gen/f32-gemm-4x8-minmax-neon-dup-ld64.c
  src/f32-gemm/gen/f32-gemm-4x8-minmax-neon-dup-ld128.c
  src/f32-gemm/gen/f32-gemm-4x8-minmax-neon-lane-ld64.c
  src/f32-gemm/gen/f32-gemm-4x8-minmax-neon-lane-ld128.c
  src/f32-gemm/gen/f32-gemm-4x8s4-minmax-neon.c
  src/f32-gemm/gen/f32-gemm-5x8-minmax-neon-lane-ld64.c
  src/f32-gemm/gen/f32-gemm-6x2-minmax-neon-lane-ld64.c
  src/f32-gemm/gen/f32-gemm-6x8-minmax-neon-dup-ld64.c
  src/f32-gemm/gen/f32-gemm-6x8-minmax-neon-dup-ld128.c
  src/f32-gemm/gen/f32-gemm-6x8-minmax-neon-lane-ld64.c
  src/f32-gemm/gen/f32-gemm-6x8-minmax-neon-lane-ld128.c
  src/f32-gemm/gen/f32-gemm-6x8s4-minmax-neon.c
  src/f32-gemm/gen/f32-gemm-8x8s4-minmax-neon.c
  src/f32-gemminc/gen/f32-gemminc-1x8-minmax-neon-dup-ld64.c
  src/f32-gemminc/gen/f32-gemminc-1x8-minmax-neon-lane-ld64.c
  src/f32-gemminc/gen/f32-gemminc-1x8s4-minmax-neon.c
  src/f32-gemminc/gen/f32-gemminc-4x8-minmax-neon-dup-ld64.c
  src/f32-gemminc/gen/f32-gemminc-4x8-minmax-neon-dup-ld128.c
  src/f32-gemminc/gen/f32-gemminc-4x8-minmax-neon-lane-ld64.c
  src/f32-gemminc/gen/f32-gemminc-4x8-minmax-neon-lane-ld128.c
  src/f32-gemminc/gen/f32-gemminc-4x8s4-minmax-neon.c
  src/f32-gemminc/gen/f32-gemminc-5x8-minmax-neon-lane-ld64.c
  src/f32-gemminc/gen/f32-gemminc-6x8-minmax-neon-dup-ld64.c
  src/f32-gemminc/gen/f32-gemminc-6x8-minmax-neon-dup-ld128.c
  src/f32-gemminc/gen/f32-gemminc-6x8-minmax-neon-lane-ld64.c
  src/f32-gemminc/gen/f32-gemminc-6x8-minmax-neon-lane-ld128.c
  src/f32-gemminc/gen/f32-gemminc-6x8s4-minmax-neon.c
  src/f32-gemminc/gen/f32-gemminc-8x8s4-minmax-neon.c
  src/f32-ibilinear-chw/gen/f32-ibilinear-chw-neon-p4.c
  src/f32-ibilinear-chw/gen/f32-ibilinear-chw-neon-p8.c
  src/f32-ibilinear-chw/gen/f32-ibilinear-chw-neon-p16.c
  src/f32-ibilinear/gen/f32-ibilinear-neon-c4.c
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  src/qu8-dwconv/gen/qu8-dwconv-25p8c-minmax-rndnu-neon-mul8.c
  src/qu8-dwconv/gen/qu8-dwconv-25p8c-minmax-rndnu-neon-mul16.c
  src/qu8-dwconv/gen/qu8-dwconv-25p16c-minmax-fp32-neon-mul16.c
  src/qu8-dwconv/gen/qu8-dwconv-25p16c-minmax-rndnu-neon-mul8.c
  src/qu8-dwconv/gen/qu8-dwconv-25p16c-minmax-rndnu-neon-mul16.c
  src/qu8-dwconv/gen/qu8-dwconv-25p32c-minmax-fp32-neon-mul16.c
  src/qu8-dwconv/gen/qu8-dwconv-25p32c-minmax-rndnu-neon-mul8.c
  src/qu8-dwconv/gen/qu8-dwconv-25p32c-minmax-rndnu-neon-mul16.c
  src/qu8-f32-vcvt/gen/qu8-f32-vcvt-neon-x8.c
  src/qu8-f32-vcvt/gen/qu8-f32-vcvt-neon-x16.c
  src/qu8-f32-vcvt/gen/qu8-f32-vcvt-neon-x24.c
  src/qu8-f32-vcvt/gen/qu8-f32-vcvt-neon-x32.c
  src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-fp32-neon-c8.c
  src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-fp32-neon-c16.c
  src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-fp32-neon-c24.c
  src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-fp32-neon-c32.c
  src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-rndnu-neon-c8.c
  src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-rndnu-neon-c16.c
  src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-rndnu-neon-c24.c
  src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-rndnu-neon-c32.c
  src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-fp32-neon-c8.c
  src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-fp32-neon-c16.c
  src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-fp32-neon-c24.c
  src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-fp32-neon-c32.c
  src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-rndnu-neon-c8.c
  src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-rndnu-neon-c16.c
  src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-rndnu-neon-c24.c
  src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-rndnu-neon-c32.c
  src/qu8-gemm/gen/qu8-gemm-1x8-minmax-fp32-neon-mlal-lane.c
  src/qu8-gemm/gen/qu8-gemm-1x8-minmax-rndnu-neon-mlal-lane.c
  src/qu8-gemm/gen/qu8-gemm-1x16-minmax-fp32-neon-mlal-lane.c
  src/qu8-gemm/gen/qu8-gemm-1x16-minmax-rndnu-neon-mlal-lane.c
  src/qu8-gemm/gen/qu8-gemm-2x8-minmax-rndnu-neon-mlal-lane.c
  src/qu8-gemm/gen/qu8-gemm-2x16-minmax-rndnu-neon-mlal-lane.c
  src/qu8-gemm/gen/qu8-gemm-3x8-minmax-rndnu-neon-mlal-lane.c
  src/qu8-gemm/gen/qu8-gemm-3x16-minmax-rndnu-neon-mlal-lane.c
  src/qu8-gemm/gen/qu8-gemm-4x8-minmax-fp32-neon-mlal-lane.c
  src/qu8-gemm/gen/qu8-gemm-4x8-minmax-rndnu-neon-mlal-lane.c
  src/qu8-gemm/gen/qu8-gemm-4x16-minmax-fp32-neon-mlal-lane.c
  src/qu8-gemm/gen/qu8-gemm-4x16-minmax-rndnu-neon-mlal-lane.c
  src/qu8-gemm/gen/qu8-gemm-6x8-minmax-rndnu-neon-mlal-lane.c
  src/qu8-gemm/gen/qu8-gemm-6x16-minmax-rndnu-neon-mlal-lane.c
  src/qu8-igemm/gen/qu8-igemm-1x8-minmax-fp32-neon-mlal-lane.c
  src/qu8-igemm/gen/qu8-igemm-1x8-minmax-rndnu-neon-mlal-lane.c
  src/qu8-igemm/gen/qu8-igemm-1x16-minmax-fp32-neon-mlal-lane.c
  src/qu8-igemm/gen/qu8-igemm-1x16-minmax-rndnu-neon-mlal-lane.c
  src/qu8-igemm/gen/qu8-igemm-2x8-minmax-rndnu-neon-mlal-lane.c
  src/qu8-igemm/gen/qu8-igemm-2x16-minmax-rndnu-neon-mlal-lane.c
  src/qu8-igemm/gen/qu8-igemm-3x8-minmax-rndnu-neon-mlal-lane.c
  src/qu8-igemm/gen/qu8-igemm-3x16-minmax-rndnu-neon-mlal-lane.c
  src/qu8-igemm/gen/qu8-igemm-4x8-minmax-fp32-neon-mlal-lane.c
  src/qu8-igemm/gen/qu8-igemm-4x8-minmax-rndnu-neon-mlal-lane.c
  src/qu8-igemm/gen/qu8-igemm-4x16-minmax-fp32-neon-mlal-lane.c
  src/qu8-igemm/gen/qu8-igemm-4x16-minmax-rndnu-neon-mlal-lane.c
  src/qu8-igemm/gen/qu8-igemm-6x8-minmax-rndnu-neon-mlal-lane.c
  src/qu8-igemm/gen/qu8-igemm-6x16-minmax-rndnu-neon-mlal-lane.c
  src/qu8-requantization/qu8-requantization-fp32-neon.c
  src/qu8-requantization/qu8-requantization-gemmlowp-neon.c
  src/qu8-requantization/qu8-requantization-rndna-neon.c
  src/qu8-vadd/gen/qu8-vadd-minmax-neon-ld64-x8.c
  src/qu8-vadd/gen/qu8-vadd-minmax-neon-ld64-x16.c
  src/qu8-vadd/gen/qu8-vadd-minmax-neon-ld64-x32.c
  src/qu8-vadd/gen/qu8-vadd-minmax-neon-ld128-x16.c
  src/qu8-vaddc/gen/qu8-vaddc-minmax-neon-ld64-x8.c
  src/qu8-vaddc/gen/qu8-vaddc-minmax-neon-ld64-x16.c
  src/qu8-vaddc/gen/qu8-vaddc-minmax-neon-ld64-x32.c
  src/qu8-vaddc/gen/qu8-vaddc-minmax-neon-ld128-x16.c
  src/qu8-vcvt/gen/qu8-vcvt-neon-x8.c
  src/qu8-vcvt/gen/qu8-vcvt-neon-x16.c
  src/qu8-vcvt/gen/qu8-vcvt-neon-x32.c
  src/qu8-vhswish/gen/qu8-vhswish-neon-x8.c
  src/qu8-vhswish/gen/qu8-vhswish-neon-x16.c
  src/qu8-vhswish/gen/qu8-vhswish-neon-x32.c
  src/qu8-vlrelu/gen/qu8-vlrelu-neon-x8.c
  src/qu8-vlrelu/gen/qu8-vlrelu-neon-x16.c
  src/qu8-vlrelu/gen/qu8-vlrelu-neon-x32.c
  src/qu8-vmul/gen/qu8-vmul-minmax-fp32-neon-ld64-x8.c
  src/qu8-vmul/gen/qu8-vmul-minmax-fp32-neon-ld64-x16.c
  src/qu8-vmul/gen/qu8-vmul-minmax-fp32-neon-ld128-x16.c
  src/qu8-vmul/gen/qu8-vmul-minmax-rndnu-neon-ld64-x8.c
  src/qu8-vmul/gen/qu8-vmul-minmax-rndnu-neon-ld64-x16.c
  src/qu8-vmul/gen/qu8-vmul-minmax-rndnu-neon-ld128-x16.c
  src/qu8-vmulc/gen/qu8-vmulc-minmax-fp32-neon-ld64-x8.c
  src/qu8-vmulc/gen/qu8-vmulc-minmax-fp32-neon-ld64-x16.c
  src/qu8-vmulc/gen/qu8-vmulc-minmax-fp32-neon-ld128-x16.c
  src/qu8-vmulc/gen/qu8-vmulc-minmax-rndnu-neon-ld64-x8.c
  src/qu8-vmulc/gen/qu8-vmulc-minmax-rndnu-neon-ld64-x16.c
  src/qu8-vmulc/gen/qu8-vmulc-minmax-rndnu-neon-ld128-x16.c
  src/s8-ibilinear/gen/s8-ibilinear-neon-c8.c
  src/s8-ibilinear/gen/s8-ibilinear-neon-c16.c
  src/s8-maxpool/s8-maxpool-2p2x-minmax-neon-c16.c
  src/s8-maxpool/s8-maxpool-4p3x-minmax-neon-c16.c
  src/s8-maxpool/s8-maxpool-9p8x-minmax-neon-c16.c
  src/s8-vclamp/s8-vclamp-neon-x64.c
  src/s16-rmaxabs/gen/s16-rmaxabs-neon-x8.c
  src/s16-rmaxabs/gen/s16-rmaxabs-neon-x16.c
  src/s16-rmaxabs/gen/s16-rmaxabs-neon-x24.c
  src/s16-rmaxabs/gen/s16-rmaxabs-neon-x32.c
  src/s16-window/gen/s16-window-neon-x8.c
  src/s16-window/gen/s16-window-neon-x16.c
  src/s16-window/gen/s16-window-neon-x24.c
  src/s16-window/gen/s16-window-neon-x32.c
  src/s16-window/gen/s16-window-shift12-neon-x8.c
  src/s16-window/gen/s16-window-shift12-neon-x16.c
  src/s16-window/gen/s16-window-shift12-neon-x24.c
  src/s16-window/gen/s16-window-shift12-neon-x32.c
  src/s16-window/gen/s16-window-shift15-neon-x8.c
  src/s16-window/gen/s16-window-shift15-neon-x16.c
  src/s16-window/gen/s16-window-shift15-neon-x24.c
  src/s16-window/gen/s16-window-shift15-neon-x32.c
  src/u8-ibilinear/gen/u8-ibilinear-neon-c8.c
  src/u8-ibilinear/gen/u8-ibilinear-neon-c16.c
  src/u8-maxpool/u8-maxpool-9p8x-minmax-neon-c16.c
  src/u8-rmax/u8-rmax-neon.c
  src/u8-vclamp/u8-vclamp-neon-x64.c
  src/u32-filterbank-accumulate/gen/u32-filterbank-accumulate-neon-x1.c
  src/u32-filterbank-accumulate/gen/u32-filterbank-accumulate-neon-x2.c
  src/x8-transposec/gen/x8-transposec-8x8-multi-dec-zip-neon.c
  src/x8-transposec/gen/x8-transposec-8x8-multi-mov-zip-neon.c
  src/x8-transposec/gen/x8-transposec-8x8-multi-switch-zip-neon.c
  src/x8-transposec/gen/x8-transposec-8x8-reuse-dec-zip-neon.c
  src/x8-transposec/gen/x8-transposec-8x8-reuse-mov-zip-neon.c
  src/x8-transposec/gen/x8-transposec-8x8-reuse-multi-zip-neon.c
  src/x8-transposec/gen/x8-transposec-8x8-reuse-switch-zip-neon.c
  src/x8-transposec/gen/x8-transposec-16x16-reuse-dec-zip-neon.c
  src/x8-transposec/gen/x8-transposec-16x16-reuse-mov-zip-neon.c
  src/x8-transposec/gen/x8-transposec-16x16-reuse-switch-zip-neon.c
  src/x8-zip/x8-zip-x2-neon.c
  src/x8-zip/x8-zip-x3-neon.c
  src/x8-zip/x8-zip-x4-neon.c
  src/x8-zip/x8-zip-xm-neon.c
  src/x16-packw/gen/x16-packw-x8-gemm-goi-neon-ld4lane-x4-prfm.c
  src/x16-packw/gen/x16-packw-x8-gemm-goi-neon-ld4lane-x4.c
  src/x16-packw/gen/x16-packw-x8-gemm-goi-neon-ld4lane-x8-prfm.c
  src/x16-packw/gen/x16-packw-x8-gemm-goi-neon-ld4lane-x8.c
  src/x16-packw/gen/x16-packw-x8-gemm-goi-neon-ld4lane-x12-prfm.c
  src/x16-packw/gen/x16-packw-x8-gemm-goi-neon-ld4lane-x12.c
  src/x16-packw/gen/x16-packw-x8-gemm-goi-neon-ld4lane-x16-prfm.c
  src/x16-packw/gen/x16-packw-x8-gemm-goi-neon-ld4lane-x16.c
  src/x16-packw/gen/x16-packw-x16-gemm-goi-neon-ld4lane-x4-prfm.c
  src/x16-packw/gen/x16-packw-x16-gemm-goi-neon-ld4lane-x4.c
  src/x16-packw/gen/x16-packw-x16-gemm-goi-neon-ld4lane-x8-prfm.c
  src/x16-packw/gen/x16-packw-x16-gemm-goi-neon-ld4lane-x8.c
  src/x16-packw/gen/x16-packw-x16-gemm-goi-neon-ld4lane-x12-prfm.c
  src/x16-packw/gen/x16-packw-x16-gemm-goi-neon-ld4lane-x12.c
  src/x16-packw/gen/x16-packw-x16-gemm-goi-neon-ld4lane-x16-prfm.c
  src/x16-packw/gen/x16-packw-x16-gemm-goi-neon-ld4lane-x16.c
  src/x16-transposec/gen/x16-transposec-4x4-multi-dec-zip-neon.c
  src/x16-transposec/gen/x16-transposec-4x4-multi-mov-zip-neon.c
  src/x16-transposec/gen/x16-transposec-4x4-multi-multi-zip-neon.c
  src/x16-transposec/gen/x16-transposec-4x4-multi-switch-zip-neon.c
  src/x16-transposec/gen/x16-transposec-4x4-reuse-dec-zip-neon.c
  src/x16-transposec/gen/x16-transposec-4x4-reuse-mov-zip-neon.c
  src/x16-transposec/gen/x16-transposec-4x4-reuse-multi-zip-neon.c
  src/x16-transposec/gen/x16-transposec-4x4-reuse-switch-zip-neon.c
  src/x16-transposec/gen/x16-transposec-8x8-multi-dec-zip-neon.c
  src/x16-transposec/gen/x16-transposec-8x8-multi-mov-zip-neon.c
  src/x16-transposec/gen/x16-transposec-8x8-multi-switch-zip-neon.c
  src/x16-transposec/gen/x16-transposec-8x8-reuse-dec-zip-neon.c
  src/x16-transposec/gen/x16-transposec-8x8-reuse-mov-zip-neon.c
  src/x16-transposec/gen/x16-transposec-8x8-reuse-multi-zip-neon.c
  src/x16-transposec/gen/x16-transposec-8x8-reuse-switch-zip-neon.c
  src/x24-transposec/x24-transposec-2x2-neon-tbl64.c
  src/x32-packw/gen/x32-packw-x2-gemm-goi-neon-ld2lane-x2-prfm.c
  src/x32-packw/gen/x32-packw-x2-gemm-goi-neon-ld2lane-x2.c
  src/x32-packw/gen/x32-packw-x8-gemm-goi-neon-ld4lane-x4-prfm.c
  src/x32-packw/gen/x32-packw-x8-gemm-goi-neon-ld4lane-x4.c
  src/x32-packw/gen/x32-packw-x8-gemm-goi-neon-ld4lane-x8-prfm.c
  src/x32-packw/gen/x32-packw-x8-gemm-goi-neon-ld4lane-x8.c
  src/x32-packw/gen/x32-packw-x8s4-gemm-goi-neon-ld4lane-x4-prfm.c
  src/x32-packw/gen/x32-packw-x8s4-gemm-goi-neon-ld4lane-x4.c
  src/x32-packw/gen/x32-packw-x8s4-gemm-goi-neon-ld4lane-x8-prfm.c
  src/x32-packw/gen/x32-packw-x8s4-gemm-goi-neon-ld4lane-x8.c
  src/x32-packw/gen/x32-packw-x12-gemm-goi-neon-ld4lane-x4-prfm.c
  src/x32-packw/gen/x32-packw-x12-gemm-goi-neon-ld4lane-x4.c
  src/x32-packw/gen/x32-packw-x12-gemm-goi-neon-ld4lane-x8-prfm.c
  src/x32-packw/gen/x32-packw-x12-gemm-goi-neon-ld4lane-x8.c
  src/x32-packw/gen/x32-packw-x16-gemm-goi-neon-ld4lane-x4-prfm.c
  src/x32-packw/gen/x32-packw-x16-gemm-goi-neon-ld4lane-x4.c
  src/x32-packw/gen/x32-packw-x16-gemm-goi-neon-ld4lane-x8-prfm.c
  src/x32-packw/gen/x32-packw-x16-gemm-goi-neon-ld4lane-x8.c
  src/x32-packx/gen/x32-packx-4x-neon-st4-x4-prfm.c
  src/x32-packx/gen/x32-packx-4x-neon-st4-x4.c
  src/x32-packx/gen/x32-packx-4x-neon-st4-x8-prfm.c
  src/x32-packx/gen/x32-packx-4x-neon-st4-x8.c
  src/x32-packx/gen/x32-packx-8x-neon-st4-x4-prfm.c
  src/x32-packx/gen/x32-packx-8x-neon-st4-x4.c
  src/x32-packx/gen/x32-packx-8x-neon-st4-x8-prfm.c
  src/x32-packx/gen/x32-packx-8x-neon-st4-x8.c
  src/x32-transposec/gen/x32-transposec-2x2-multi-dec-zip-neon.c
  src/x32-transposec/gen/x32-transposec-2x2-multi-mov-zip-neon.c
  src/x32-transposec/gen/x32-transposec-2x2-multi-multi-zip-neon.c
  src/x32-transposec/gen/x32-transposec-2x2-multi-switch-zip-neon.c
  src/x32-transposec/gen/x32-transposec-2x2-reuse-dec-zip-neon.c
  src/x32-transposec/gen/x32-transposec-2x2-reuse-mov-zip-neon.c
  src/x32-transposec/gen/x32-transposec-2x2-reuse-multi-zip-neon.c
  src/x32-transposec/gen/x32-transposec-2x2-reuse-switch-zip-neon.c
  src/x32-transposec/gen/x32-transposec-4x4-multi-dec-zip-neon.c
  src/x32-transposec/gen/x32-transposec-4x4-multi-mov-zip-neon.c
  src/x32-transposec/gen/x32-transposec-4x4-multi-multi-zip-neon.c
  src/x32-transposec/gen/x32-transposec-4x4-multi-switch-zip-neon.c
  src/x32-transposec/gen/x32-transposec-4x4-reuse-dec-zip-neon.c
  src/x32-transposec/gen/x32-transposec-4x4-reuse-mov-zip-neon.c
  src/x32-transposec/gen/x32-transposec-4x4-reuse-multi-zip-neon.c
  src/x32-transposec/gen/x32-transposec-4x4-reuse-switch-zip-neon.c
  src/x32-unpool/x32-unpool-neon.c
  src/x32-zip/x32-zip-x2-neon.c
  src/x32-zip/x32-zip-x3-neon.c
  src/x32-zip/x32-zip-x4-neon.c
  src/x32-zip/x32-zip-xm-neon.c
  src/x64-transposec/gen/x64-transposec-2x2-multi-dec-zip-neon.c
  src/x64-transposec/gen/x64-transposec-2x2-multi-mov-zip-neon.c
  src/x64-transposec/gen/x64-transposec-2x2-multi-multi-zip-neon.c
  src/x64-transposec/gen/x64-transposec-2x2-multi-switch-zip-neon.c
  src/x64-transposec/gen/x64-transposec-2x2-reuse-dec-zip-neon.c
  src/x64-transposec/gen/x64-transposec-2x2-reuse-mov-zip-neon.c
  src/x64-transposec/gen/x64-transposec-2x2-reuse-multi-zip-neon.c
  src/x64-transposec/gen/x64-transposec-2x2-reuse-switch-zip-neon.c
  src/xx-fill/xx-fill-neon-x64.c
  src/xx-pad/xx-pad-neon.c)

SET(ALL_NEON_AARCH64_MICROKERNEL_SRCS
  src/f32-vbinary/gen/f32-vdiv-minmax-aarch64-neon-x4.c
  src/f32-vbinary/gen/f32-vdiv-minmax-aarch64-neon-x8.c
  src/f32-vbinary/gen/f32-vdivc-minmax-aarch64-neon-x4.c
  src/f32-vbinary/gen/f32-vdivc-minmax-aarch64-neon-x8.c
  src/f32-vbinary/gen/f32-vrdivc-minmax-aarch64-neon-x4.c
  src/f32-vbinary/gen/f32-vrdivc-minmax-aarch64-neon-x8.c
  src/f32-vsqrt/gen/f32-vsqrt-aarch64-neon-sqrt-x4.c
  src/f32-vsqrt/gen/f32-vsqrt-aarch64-neon-sqrt-x8.c
  src/x8-lut/gen/x8-lut-aarch64-neon-tbx128x4-x16.c
  src/x8-lut/gen/x8-lut-aarch64-neon-tbx128x4-x32.c
  src/x8-lut/gen/x8-lut-aarch64-neon-tbx128x4-x48.c
  src/x8-lut/gen/x8-lut-aarch64-neon-tbx128x4-x64.c
  src/x24-transposec/x24-transposec-4x4-aarch64-neon-tbl128.c
  src/x32-transposec/x32-transposec-4x4-aarch64-neon-tbl128.c)

SET(ALL_NEONBF16_MICROKERNEL_SRCS
  src/bf16-gemm/gen/bf16-gemm-1x4c8-minmax-neonbf16-bfdot.c
  src/bf16-gemm/gen/bf16-gemm-1x4c8-minmax-neonbf16-bfmlal.c
  src/bf16-gemm/gen/bf16-gemm-1x8c2-minmax-neonbf16-bfdot-lane-ld128.c
  src/bf16-gemm/gen/bf16-gemm-2x4c8-minmax-neonbf16-bfdot.c
  src/bf16-gemm/gen/bf16-gemm-2x4c8-minmax-neonbf16-bfmlal.c
  src/bf16-gemm/gen/bf16-gemm-3x4c8-minmax-neonbf16-bfdot.c
  src/bf16-gemm/gen/bf16-gemm-3x4c8-minmax-neonbf16-bfmlal.c
  src/bf16-gemm/gen/bf16-gemm-4x4c8-minmax-neonbf16-bfdot.c
  src/bf16-gemm/gen/bf16-gemm-4x4c8-minmax-neonbf16-bfmlal.c
  src/bf16-gemm/gen/bf16-gemm-4x8c2-minmax-neonbf16-bfdot-lane-ld128.c
  src/bf16-gemm/gen/bf16-gemm-5x4c8-minmax-neonbf16-bfdot.c
  src/bf16-gemm/gen/bf16-gemm-5x4c8-minmax-neonbf16-bfmlal.c
  src/bf16-gemm/gen/bf16-gemm-5x8c2-minmax-neonbf16-bfdot-lane-ld128.c
  src/bf16-gemm/gen/bf16-gemm-6x8c2-minmax-neonbf16-bfdot-lane-ld128.c)

SET(ALL_NEONBF16_AARCH64_MICROKERNEL_SRCS)

SET(ALL_NEONDOT_MICROKERNEL_SRCS
  src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x8c4-minmax-neondot.c
  src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x16c4-minmax-neondot.c
  src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x8c4-minmax-neondot.c
  src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x16c4-minmax-neondot.c
  src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-3x16c4-minmax-neondot.c
  src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-4x8c4-minmax-neondot.c
  src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-4x16c4-minmax-neondot.c
  src/qs8-gemm/gen/qs8-gemm-1x8c4-minmax-fp32-neondot.c
  src/qs8-gemm/gen/qs8-gemm-1x8c4-minmax-rndnu-neondot.c
  src/qs8-gemm/gen/qs8-gemm-1x16c4-minmax-rndnu-neondot.c
  src/qs8-gemm/gen/qs8-gemm-4x8c4-minmax-rndnu-neondot.c
  src/qs8-gemm/gen/qs8-gemm-4x16c4-minmax-rndnu-neondot.c
  src/qs8-gemm/gen/qs8-gemm-6x8c4-minmax-rndnu-neondot.c
  src/qs8-gemm/gen/qs8-gemm-6x16c4-minmax-rndnu-neondot.c
  src/qs8-gemm/gen/qs8-gemm-8x8c4-minmax-rndnu-neondot.c
  src/qs8-gemm/gen/qs8-gemm-8x16c4-minmax-rndnu-neondot.c
  src/qs8-igemm/gen/qs8-igemm-1x8c4-minmax-fp32-neondot.c
  src/qs8-igemm/gen/qs8-igemm-1x8c4-minmax-rndnu-neondot.c
  src/qs8-igemm/gen/qs8-igemm-1x16c4-minmax-rndnu-neondot.c
  src/qs8-igemm/gen/qs8-igemm-4x8c4-minmax-rndnu-neondot.c
  src/qs8-igemm/gen/qs8-igemm-4x16c4-minmax-rndnu-neondot.c
  src/qs8-igemm/gen/qs8-igemm-6x8c4-minmax-rndnu-neondot.c
  src/qs8-igemm/gen/qs8-igemm-6x16c4-minmax-rndnu-neondot.c
  src/qs8-igemm/gen/qs8-igemm-8x8c4-minmax-rndnu-neondot.c
  src/qs8-igemm/gen/qs8-igemm-8x16c4-minmax-rndnu-neondot.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8c4-minmax-fp32-neondot.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x16c4-minmax-fp32-neondot.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x8c4-minmax-fp32-neondot.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x16c4-minmax-fp32-neondot.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-6x8c4-minmax-fp32-neondot.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-6x16c4-minmax-fp32-neondot.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-8x8c4-minmax-fp32-neondot.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-8x16c4-minmax-fp32-neondot.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8c4-minmax-fp32-neondot.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x16c4-minmax-fp32-neondot.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x8c4-minmax-fp32-neondot.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x16c4-minmax-fp32-neondot.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-6x8c4-minmax-fp32-neondot.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-6x16c4-minmax-fp32-neondot.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-8x8c4-minmax-fp32-neondot.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-8x16c4-minmax-fp32-neondot.c
  src/qu8-gemm/gen/qu8-gemm-1x8c4-minmax-rndnu-neondot.c
  src/qu8-gemm/gen/qu8-gemm-1x16c4-minmax-fp32-neondot.c
  src/qu8-gemm/gen/qu8-gemm-1x16c4-minmax-rndnu-neondot.c
  src/qu8-gemm/gen/qu8-gemm-1x32c4-minmax-rndnu-neondot.c
  src/qu8-gemm/gen/qu8-gemm-2x8c4-minmax-rndnu-neondot.c
  src/qu8-gemm/gen/qu8-gemm-2x16c4-minmax-fp32-neondot.c
  src/qu8-gemm/gen/qu8-gemm-2x16c4-minmax-rndnu-neondot.c
  src/qu8-gemm/gen/qu8-gemm-2x32c4-minmax-rndnu-neondot.c
  src/qu8-gemm/gen/qu8-gemm-3x8c4-minmax-rndnu-neondot.c
  src/qu8-gemm/gen/qu8-gemm-3x16c4-minmax-rndnu-neondot.c
  src/qu8-gemm/gen/qu8-gemm-3x32c4-minmax-rndnu-neondot.c
  src/qu8-gemm/gen/qu8-gemm-4x8c4-minmax-rndnu-neondot.c
  src/qu8-gemm/gen/qu8-gemm-4x16c4-minmax-fp32-neondot.c
  src/qu8-gemm/gen/qu8-gemm-4x16c4-minmax-rndnu-neondot.c
  src/qu8-gemm/gen/qu8-gemm-5x8c4-minmax-rndnu-neondot.c
  src/qu8-gemm/gen/qu8-gemm-5x16c4-minmax-rndnu-neondot.c
  src/qu8-gemm/gen/qu8-gemm-6x8c4-minmax-rndnu-neondot.c
  src/qu8-gemm/gen/qu8-gemm-6x16c4-minmax-rndnu-neondot.c
  src/qu8-gemm/gen/qu8-gemm-8x8c4-minmax-rndnu-neondot.c
  src/qu8-gemm/gen/qu8-gemm-8x16c4-minmax-rndnu-neondot.c
  src/qu8-igemm/gen/qu8-igemm-1x8c4-minmax-rndnu-neondot.c
  src/qu8-igemm/gen/qu8-igemm-1x16c4-minmax-fp32-neondot.c
  src/qu8-igemm/gen/qu8-igemm-1x16c4-minmax-rndnu-neondot.c
  src/qu8-igemm/gen/qu8-igemm-1x32c4-minmax-rndnu-neondot.c
  src/qu8-igemm/gen/qu8-igemm-2x8c4-minmax-rndnu-neondot.c
  src/qu8-igemm/gen/qu8-igemm-2x16c4-minmax-fp32-neondot.c
  src/qu8-igemm/gen/qu8-igemm-2x16c4-minmax-rndnu-neondot.c
  src/qu8-igemm/gen/qu8-igemm-2x32c4-minmax-rndnu-neondot.c
  src/qu8-igemm/gen/qu8-igemm-3x8c4-minmax-rndnu-neondot.c
  src/qu8-igemm/gen/qu8-igemm-3x16c4-minmax-rndnu-neondot.c
  src/qu8-igemm/gen/qu8-igemm-3x32c4-minmax-rndnu-neondot.c
  src/qu8-igemm/gen/qu8-igemm-4x8c4-minmax-rndnu-neondot.c
  src/qu8-igemm/gen/qu8-igemm-4x16c4-minmax-fp32-neondot.c
  src/qu8-igemm/gen/qu8-igemm-4x16c4-minmax-rndnu-neondot.c
  src/qu8-igemm/gen/qu8-igemm-5x8c4-minmax-rndnu-neondot.c
  src/qu8-igemm/gen/qu8-igemm-5x16c4-minmax-rndnu-neondot.c
  src/qu8-igemm/gen/qu8-igemm-6x8c4-minmax-rndnu-neondot.c
  src/qu8-igemm/gen/qu8-igemm-6x16c4-minmax-rndnu-neondot.c
  src/qu8-igemm/gen/qu8-igemm-8x8c4-minmax-rndnu-neondot.c
  src/qu8-igemm/gen/qu8-igemm-8x16c4-minmax-rndnu-neondot.c)

SET(ALL_NEONFMA_MICROKERNEL_SRCS
  src/bf16-gemm/gen/bf16-gemm-1x4c8-minmax-neonfma-shland.c
  src/bf16-gemm/gen/bf16-gemm-1x4c8-minmax-neonfma-zip.c
  src/bf16-gemm/gen/bf16-gemm-2x4c8-minmax-neonfma-shland.c
  src/bf16-gemm/gen/bf16-gemm-2x4c8-minmax-neonfma-zip.c
  src/bf16-gemm/gen/bf16-gemm-3x4c8-minmax-neonfma-shland.c
  src/bf16-gemm/gen/bf16-gemm-3x4c8-minmax-neonfma-zip.c
  src/bf16-gemm/gen/bf16-gemm-4x4c8-minmax-neonfma-shland.c
  src/bf16-gemm/gen/bf16-gemm-4x4c8-minmax-neonfma-zip.c
  src/bf16-gemm/gen/bf16-gemm-5x4c8-minmax-neonfma-shland.c
  src/bf16-gemm/gen/bf16-gemm-5x4c8-minmax-neonfma-zip.c
  src/f32-dwconv/gen/f32-dwconv-2f2m2l4c4s4r-minmax-neonfma-acc2.c
  src/f32-dwconv/gen/f32-dwconv-2f2m2l4c4s4r-minmax-neonfma.c
  src/f32-dwconv/gen/f32-dwconv-2f2m2l8c4s4r-minmax-neonfma-acc2.c
  src/f32-dwconv/gen/f32-dwconv-2f2m2l8c4s4r-minmax-neonfma.c
  src/f32-dwconv/gen/f32-dwconv-2f2m2l16c4s4r-minmax-neonfma-acc2.c
  src/f32-dwconv/gen/f32-dwconv-2f2m2l16c4s4r-minmax-neonfma.c
  src/f32-dwconv/gen/f32-dwconv-3p4c-minmax-neonfma-acc2.c
  src/f32-dwconv/gen/f32-dwconv-3p4c-minmax-neonfma.c
  src/f32-dwconv/gen/f32-dwconv-3p8c-minmax-neonfma-acc2.c
  src/f32-dwconv/gen/f32-dwconv-3p8c-minmax-neonfma.c
  src/f32-dwconv/gen/f32-dwconv-3p16c-minmax-neonfma-acc2.c
  src/f32-dwconv/gen/f32-dwconv-3p16c-minmax-neonfma.c
  src/f32-dwconv/gen/f32-dwconv-4p4c-minmax-neonfma-acc2.c
  src/f32-dwconv/gen/f32-dwconv-4p4c-minmax-neonfma.c
  src/f32-dwconv/gen/f32-dwconv-4p8c-minmax-neonfma-acc2.c
  src/f32-dwconv/gen/f32-dwconv-4p8c-minmax-neonfma.c
  src/f32-dwconv/gen/f32-dwconv-4p16c-minmax-neonfma-acc2.c
  src/f32-dwconv/gen/f32-dwconv-4p16c-minmax-neonfma.c
  src/f32-dwconv/gen/f32-dwconv-5f5m5l4c4s4r-minmax-neonfma-acc2.c
  src/f32-dwconv/gen/f32-dwconv-5f5m5l4c4s4r-minmax-neonfma.c
  src/f32-dwconv/gen/f32-dwconv-5f5m5l8c4s4r-minmax-neonfma-acc2.c
  src/f32-dwconv/gen/f32-dwconv-5f5m5l8c4s4r-minmax-neonfma.c
  src/f32-dwconv/gen/f32-dwconv-6f6m7l4c4s4r-minmax-neonfma-acc2.c
  src/f32-dwconv/gen/f32-dwconv-6f6m7l4c4s4r-minmax-neonfma.c
  src/f32-dwconv/gen/f32-dwconv-6f6m7l8c4s4r-minmax-neonfma-acc2.c
  src/f32-dwconv/gen/f32-dwconv-6f6m7l8c4s4r-minmax-neonfma.c
  src/f32-dwconv/gen/f32-dwconv-8f8m9l4c4s4r-minmax-neonfma-acc2.c
  src/f32-dwconv/gen/f32-dwconv-8f8m9l4c4s4r-minmax-neonfma.c
  src/f32-dwconv/gen/f32-dwconv-8f8m9l8c4s4r-minmax-neonfma-acc2.c
  src/f32-dwconv/gen/f32-dwconv-8f8m9l8c4s4r-minmax-neonfma.c
  src/f32-dwconv/gen/f32-dwconv-9p4c-minmax-neonfma-acc2.c
  src/f32-dwconv/gen/f32-dwconv-9p4c-minmax-neonfma.c
  src/f32-dwconv/gen/f32-dwconv-9p8c-minmax-neonfma-acc2.c
  src/f32-dwconv/gen/f32-dwconv-9p8c-minmax-neonfma.c
  src/f32-dwconv/gen/f32-dwconv-9p16c-minmax-neonfma-acc2.c
  src/f32-dwconv/gen/f32-dwconv-9p16c-minmax-neonfma.c
  src/f32-dwconv/gen/f32-dwconv-25p4c-minmax-neonfma-acc2.c
  src/f32-dwconv/gen/f32-dwconv-25p4c-minmax-neonfma.c
  src/f32-dwconv/gen/f32-dwconv-25p8c-minmax-neonfma-acc2.c
  src/f32-dwconv/gen/f32-dwconv-25p8c-minmax-neonfma.c
  src/f32-dwconv/gen/f32-dwconv-25p16c-minmax-neonfma-acc2.c
  src/f32-dwconv/gen/f32-dwconv-25p16c-minmax-neonfma.c
  src/f32-gemm/gen/f32-gemm-1x8-minmax-neonfma-dup-ld64.c
  src/f32-gemm/gen/f32-gemm-1x8s4-minmax-neonfma.c
  src/f32-gemm/gen/f32-gemm-4x8-minmax-neonfma-dup-ld64.c
  src/f32-gemm/gen/f32-gemm-4x8-minmax-neonfma-dup-ld128.c
  src/f32-gemm/gen/f32-gemm-4x8s4-minmax-neonfma.c
  src/f32-gemm/gen/f32-gemm-6x8-minmax-neonfma-dup-ld64.c
  src/f32-gemm/gen/f32-gemm-6x8-minmax-neonfma-dup-ld128.c
  src/f32-gemm/gen/f32-gemm-6x8s4-minmax-neonfma.c
  src/f32-gemm/gen/f32-gemm-8x8s4-minmax-neonfma.c
  src/f32-gemminc/gen/f32-gemminc-1x8-minmax-neonfma-dup-ld64.c
  src/f32-gemminc/gen/f32-gemminc-1x8s4-minmax-neonfma.c
  src/f32-gemminc/gen/f32-gemminc-4x8-minmax-neonfma-dup-ld64.c
  src/f32-gemminc/gen/f32-gemminc-4x8-minmax-neonfma-dup-ld128.c
  src/f32-gemminc/gen/f32-gemminc-4x8s4-minmax-neonfma.c
  src/f32-gemminc/gen/f32-gemminc-6x8-minmax-neonfma-dup-ld64.c
  src/f32-gemminc/gen/f32-gemminc-6x8-minmax-neonfma-dup-ld128.c
  src/f32-gemminc/gen/f32-gemminc-6x8s4-minmax-neonfma.c
  src/f32-gemminc/gen/f32-gemminc-8x8s4-minmax-neonfma.c
  src/f32-ibilinear-chw/gen/f32-ibilinear-chw-neonfma-p4.c
  src/f32-ibilinear-chw/gen/f32-ibilinear-chw-neonfma-p8.c
  src/f32-ibilinear-chw/gen/f32-ibilinear-chw-neonfma-p16.c
  src/f32-ibilinear/gen/f32-ibilinear-neonfma-c4.c
  src/f32-ibilinear/gen/f32-ibilinear-neonfma-c8.c
  src/f32-igemm/gen/f32-igemm-1x8-minmax-neonfma-dup-ld64.c
  src/f32-igemm/gen/f32-igemm-1x8s4-minmax-neonfma.c
  src/f32-igemm/gen/f32-igemm-4x8-minmax-neonfma-dup-ld64.c
  src/f32-igemm/gen/f32-igemm-4x8-minmax-neonfma-dup-ld128.c
  src/f32-igemm/gen/f32-igemm-4x8s4-minmax-neonfma.c
  src/f32-igemm/gen/f32-igemm-6x8-minmax-neonfma-dup-ld64.c
  src/f32-igemm/gen/f32-igemm-6x8-minmax-neonfma-dup-ld128.c
  src/f32-igemm/gen/f32-igemm-6x8s4-minmax-neonfma.c
  src/f32-igemm/gen/f32-igemm-8x8s4-minmax-neonfma.c
  src/f32-qc4w-gemm/gen/f32-qc4w-gemm-1x8-minmax-neonfma-dup-ld64.c
  src/f32-qc4w-gemm/gen/f32-qc4w-gemm-4x8-minmax-neonfma-dup-ld64.c
  src/f32-qc4w-gemm/gen/f32-qc4w-gemm-6x8-minmax-neonfma-dup-ld64.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-neonfma-dup-ld64.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8s4-minmax-neonfma.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-minmax-neonfma-dup-ld64.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8s4-minmax-neonfma.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-minmax-neonfma-dup-ld64.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8s4-minmax-neonfma.c
  src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neonfma-rr1-lut64-p2-x4.c
  src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neonfma-rr1-lut64-p2-x8-acc2.c
  src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neonfma-rr1-lut64-p2-x8.c
  src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neonfma-rr1-lut64-p2-x12-acc2.c
  src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neonfma-rr1-lut64-p2-x12-acc3.c
  src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neonfma-rr1-lut64-p2-x12.c
  src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neonfma-rr1-lut64-p2-x16-acc2.c
  src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neonfma-rr1-lut64-p2-x16-acc4.c
  src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neonfma-rr1-lut64-p2-x16.c
  src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neonfma-rr1-lut64-p2-x20-acc2.c
  src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neonfma-rr1-lut64-p2-x20-acc5.c
  src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neonfma-rr1-lut64-p2-x20.c
  src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neonfma-rr1-p5-x4.c
  src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neonfma-rr1-p5-x8-acc2.c
  src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neonfma-rr1-p5-x8.c
  src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neonfma-rr1-p5-x12-acc2.c
  src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neonfma-rr1-p5-x12-acc3.c
  src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neonfma-rr1-p5-x12.c
  src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neonfma-rr1-p5-x16-acc2.c
  src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neonfma-rr1-p5-x16-acc4.c
  src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neonfma-rr1-p5-x16.c
  src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neonfma-rr1-p5-x20-acc2.c
  src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neonfma-rr1-p5-x20-acc5.c
  src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-neonfma-rr1-p5-x20.c
  src/f32-spmm/gen/f32-spmm-4x1-minmax-neonfma-pipelined.c
  src/f32-spmm/gen/f32-spmm-4x1-minmax-neonfma-x2.c
  src/f32-spmm/gen/f32-spmm-4x1-minmax-neonfma.c
  src/f32-spmm/gen/f32-spmm-8x1-minmax-neonfma-pipelined.c
  src/f32-spmm/gen/f32-spmm-8x1-minmax-neonfma-x2.c
  src/f32-spmm/gen/f32-spmm-8x1-minmax-neonfma.c
  src/f32-spmm/gen/f32-spmm-12x1-minmax-neonfma.c
  src/f32-spmm/gen/f32-spmm-16x1-minmax-neonfma-pipelined.c
  src/f32-spmm/gen/f32-spmm-16x1-minmax-neonfma-x2.c
  src/f32-spmm/gen/f32-spmm-16x1-minmax-neonfma.c
  src/f32-spmm/gen/f32-spmm-32x1-minmax-neonfma-pipelined.c
  src/f32-spmm/gen/f32-spmm-32x1-minmax-neonfma-x2.c
  src/f32-spmm/gen/f32-spmm-32x1-minmax-neonfma.c
  src/f32-velu/gen/f32-velu-neonfma-rr1-lut16-p3-x4.c
  src/f32-velu/gen/f32-velu-neonfma-rr1-lut16-p3-x8.c
  src/f32-velu/gen/f32-velu-neonfma-rr1-lut16-p3-x12.c
  src/f32-velu/gen/f32-velu-neonfma-rr1-lut16-p3-x16.c
  src/f32-velu/gen/f32-velu-neonfma-rr1-lut16-p3-x20.c
  src/f32-velu/gen/f32-velu-neonfma-rr1-lut16-p3-x24.c
  src/f32-velu/gen/f32-velu-neonfma-rr1-p6-x4.c
  src/f32-velu/gen/f32-velu-neonfma-rr1-p6-x8.c
  src/f32-velu/gen/f32-velu-neonfma-rr1-p6-x12.c
  src/f32-velu/gen/f32-velu-neonfma-rr1-p6-x16.c
  src/f32-velu/gen/f32-velu-neonfma-rr1-p6-x20.c
  src/f32-velu/gen/f32-velu-neonfma-rr1-p6-x24.c
  src/f32-vmulcaddc/gen/f32-vmulcaddc-c4-minmax-neonfma-2x.c
  src/f32-vmulcaddc/gen/f32-vmulcaddc-c8-minmax-neonfma-2x.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut64-p2-nr1recps1fma-x4.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut64-p2-nr1recps1fma-x8.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut64-p2-nr1recps1fma-x12.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut64-p2-nr1recps1fma-x16.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut64-p2-nr1recps1fma-x20.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut64-p2-nr1recps1fma-x24.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut64-p2-nr2fma-x4.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut64-p2-nr2fma-x8.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut64-p2-nr2fma-x12.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut64-p2-nr2fma-x16.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut64-p2-nr2fma-x20.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut64-p2-nr2fma-x24.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut64-p2-nr2recps-x4.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut64-p2-nr2recps-x8.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut64-p2-nr2recps-x12.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut64-p2-nr2recps-x16.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut64-p2-nr2recps-x20.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut64-p2-nr2recps-x24.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut2048-p1-nr1recps1fma-x4.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut2048-p1-nr1recps1fma-x8.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut2048-p1-nr1recps1fma-x12.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut2048-p1-nr1recps1fma-x16.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut2048-p1-nr1recps1fma-x20.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut2048-p1-nr1recps1fma-x24.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut2048-p1-nr2fma-x4.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut2048-p1-nr2fma-x8.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut2048-p1-nr2fma-x12.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut2048-p1-nr2fma-x16.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut2048-p1-nr2fma-x20.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut2048-p1-nr2fma-x24.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut2048-p1-nr2recps-x4.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut2048-p1-nr2recps-x8.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut2048-p1-nr2recps-x12.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut2048-p1-nr2recps-x16.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut2048-p1-nr2recps-x20.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-lut2048-p1-nr2recps-x24.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-p5-nr1recps1fma-x4.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-p5-nr1recps1fma-x8.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-p5-nr1recps1fma-x12.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-p5-nr1recps1fma-x16.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-p5-nr1recps1fma-x20.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-p5-nr1recps1fma-x24.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-p5-nr2fma-x4.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-p5-nr2fma-x8.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-p5-nr2fma-x12.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-p5-nr2fma-x16.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-p5-nr2fma-x20.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-p5-nr2fma-x24.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-p5-nr2recps-x4.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-p5-nr2recps-x8.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-p5-nr2recps-x12.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-p5-nr2recps-x16.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-p5-nr2recps-x20.c
  src/f32-vsigmoid/gen/f32-vsigmoid-neonfma-rr1-p5-nr2recps-x24.c
  src/f32-vsqrt/gen/f32-vsqrt-neonfma-nr1rsqrts1fma1adj-x4.c
  src/f32-vsqrt/gen/f32-vsqrt-neonfma-nr1rsqrts1fma1adj-x8.c
  src/f32-vsqrt/gen/f32-vsqrt-neonfma-nr1rsqrts1fma1adj-x12.c
  src/f32-vsqrt/gen/f32-vsqrt-neonfma-nr1rsqrts1fma1adj-x16.c
  src/f32-vsqrt/gen/f32-vsqrt-neonfma-nr1rsqrts1fma1adj-x20.c
  src/f32-vsqrt/gen/f32-vsqrt-neonfma-nr1rsqrts1fma1adj-x24.c
  src/f32-vsqrt/gen/f32-vsqrt-neonfma-nr1rsqrts1fma1adj-x28.c
  src/f32-vsqrt/gen/f32-vsqrt-neonfma-nr1rsqrts1fma1adj-x32.c
  src/f32-vsqrt/gen/f32-vsqrt-neonfma-nr1rsqrts1fma1adj-x36.c
  src/f32-vsqrt/gen/f32-vsqrt-neonfma-nr1rsqrts1fma1adj-x40.c
  src/f32-vsqrt/gen/f32-vsqrt-neonfma-nr2fma1adj-x4.c
  src/f32-vsqrt/gen/f32-vsqrt-neonfma-nr2fma1adj-x8.c
  src/f32-vsqrt/gen/f32-vsqrt-neonfma-nr2fma1adj-x12.c
  src/f32-vsqrt/gen/f32-vsqrt-neonfma-nr2fma1adj-x16.c
  src/f32-vsqrt/gen/f32-vsqrt-neonfma-nr2fma1adj-x20.c
  src/f32-vsqrt/gen/f32-vsqrt-neonfma-nr2fma1adj-x24.c
  src/f32-vsqrt/gen/f32-vsqrt-neonfma-nr2fma1adj-x28.c
  src/f32-vsqrt/gen/f32-vsqrt-neonfma-nr2fma1adj-x32.c
  src/f32-vsqrt/gen/f32-vsqrt-neonfma-nr2fma1adj-x36.c
  src/f32-vsqrt/gen/f32-vsqrt-neonfma-nr2fma1adj-x40.c
  src/f32-vtanh/gen/f32-vtanh-neonfma-expm1minus-rr1-lut8-p4h3ts-nr1recps1fma-x4.c
  src/f32-vtanh/gen/f32-vtanh-neonfma-expm1minus-rr1-lut8-p4h3ts-nr1recps1fma-x8.c
  src/f32-vtanh/gen/f32-vtanh-neonfma-expm1minus-rr1-lut8-p4h3ts-nr1recps1fma-x12.c
  src/f32-vtanh/gen/f32-vtanh-neonfma-expm1minus-rr1-lut8-p4h3ts-nr1recps1fma-x16.c
  src/f32-vtanh/gen/f32-vtanh-neonfma-expm1minus-rr1-lut8-p4h3ts-nr2fma-x4.c
  src/f32-vtanh/gen/f32-vtanh-neonfma-expm1minus-rr1-lut8-p4h3ts-nr2fma-x8.c
  src/f32-vtanh/gen/f32-vtanh-neonfma-expm1minus-rr1-lut8-p4h3ts-nr2fma-x12.c
  src/f32-vtanh/gen/f32-vtanh-neonfma-expm1minus-rr1-lut8-p4h3ts-nr2fma-x16.c
  src/f32-vtanh/gen/f32-vtanh-neonfma-expm1minus-rr1-p6h5ts-nr1recps1fma-x4.c
  src/f32-vtanh/gen/f32-vtanh-neonfma-expm1minus-rr1-p6h5ts-nr1recps1fma-x8.c
  src/f32-vtanh/gen/f32-vtanh-neonfma-expm1minus-rr1-p6h5ts-nr1recps1fma-x12.c
  src/f32-vtanh/gen/f32-vtanh-neonfma-expm1minus-rr1-p6h5ts-nr1recps1fma-x16.c
  src/f32-vtanh/gen/f32-vtanh-neonfma-expm1minus-rr1-p6h5ts-nr2fma-x4.c
  src/f32-vtanh/gen/f32-vtanh-neonfma-expm1minus-rr1-p6h5ts-nr2fma-x8.c
  src/f32-vtanh/gen/f32-vtanh-neonfma-expm1minus-rr1-p6h5ts-nr2fma-x12.c
  src/f32-vtanh/gen/f32-vtanh-neonfma-expm1minus-rr1-p6h5ts-nr2fma-x16.c
  src/f32-vtanh/gen/f32-vtanh-neonfma-expm1minus-rr1-p6h5ts-nr2recps-x4.c
  src/f32-vtanh/gen/f32-vtanh-neonfma-expm1minus-rr1-p6h5ts-nr2recps-x8.c
  src/f32-vtanh/gen/f32-vtanh-neonfma-expm1minus-rr1-p6h5ts-nr2recps-x12.c
  src/f32-vtanh/gen/f32-vtanh-neonfma-expm1minus-rr1-p6h5ts-nr2recps-x16.c
  src/math/f32-exp-neonfma-rr2-lut64-p2.c
  src/math/f32-exp-neonfma-rr2-p5.c
  src/math/f32-expm1minus-neonfma-rr1-lut16-p3.c
  src/math/f32-expm1minus-neonfma-rr1-p6.c
  src/math/f32-expminus-neonfma-rr2-lut64-p2.c
  src/math/f32-expminus-neonfma-rr2-lut2048-p1.c
  src/math/f32-expminus-neonfma-rr2-p5.c
  src/math/f32-sigmoid-neonfma-rr1-lut64-p2-nr1recps1fma.c
  src/math/f32-sigmoid-neonfma-rr1-lut64-p2-nr2fma.c
  src/math/f32-sigmoid-neonfma-rr1-lut64-p2-nr2recps.c
  src/math/f32-sigmoid-neonfma-rr1-lut2048-p1-nr1recps1fma.c
  src/math/f32-sigmoid-neonfma-rr1-lut2048-p1-nr2fma.c
  src/math/f32-sigmoid-neonfma-rr1-lut2048-p1-nr2recps.c
  src/math/f32-sigmoid-neonfma-rr1-p5-nr1recps1fma.c
  src/math/f32-sigmoid-neonfma-rr1-p5-nr2fma.c
  src/math/f32-sigmoid-neonfma-rr1-p5-nr2recps.c
  src/math/f32-sigmoid-neonfma-rr2-lut64-p2-nr1recps1fma.c
  src/math/f32-sigmoid-neonfma-rr2-lut64-p2-nr2fma.c
  src/math/f32-sigmoid-neonfma-rr2-lut64-p2-nr2recps.c
  src/math/f32-sigmoid-neonfma-rr2-lut2048-p1-nr1recps1fma.c
  src/math/f32-sigmoid-neonfma-rr2-lut2048-p1-nr2fma.c
  src/math/f32-sigmoid-neonfma-rr2-lut2048-p1-nr2recps.c
  src/math/f32-sigmoid-neonfma-rr2-p5-nr1recps1fma.c
  src/math/f32-sigmoid-neonfma-rr2-p5-nr2fma.c
  src/math/f32-sigmoid-neonfma-rr2-p5-nr2recps.c
  src/math/f32-sqrt-neonfma-nr1fma.c
  src/math/f32-sqrt-neonfma-nr1rsqrts1fma1adj.c
  src/math/f32-sqrt-neonfma-nr2fma1adj.c
  src/math/f32-sqrt-neonfma-nr2fma.c
  src/math/f32-sqrt-neonfma-nr3fma.c
  src/math/gen/f32-tanh-neonfma-expm1minus-rr1-lut8-p4h2ts-nr1recps1fma.c
  src/math/gen/f32-tanh-neonfma-expm1minus-rr1-lut8-p4h2ts-nr2fma.c
  src/math/gen/f32-tanh-neonfma-expm1minus-rr1-lut8-p4h2ts-nr2recps.c
  src/math/gen/f32-tanh-neonfma-expm1minus-rr1-lut8-p4h3ps-nr1recps1fma.c
  src/math/gen/f32-tanh-neonfma-expm1minus-rr1-lut8-p4h3ps-nr1recps1fmaadj.c
  src/math/gen/f32-tanh-neonfma-expm1minus-rr1-lut8-p4h3ps-nr2fma.c
  src/math/gen/f32-tanh-neonfma-expm1minus-rr1-lut8-p4h3ps-nr2fmaadj.c
  src/math/gen/f32-tanh-neonfma-expm1minus-rr1-lut8-p4h3ps-nr2recps.c
  src/math/gen/f32-tanh-neonfma-expm1minus-rr1-lut8-p4h3ps-nr2recpsadj.c
  src/math/gen/f32-tanh-neonfma-expm1minus-rr1-p6h5ts-nr1recps1fma.c
  src/math/gen/f32-tanh-neonfma-expm1minus-rr1-p6h5ts-nr1recps1fmaadj.c
  src/math/gen/f32-tanh-neonfma-expm1minus-rr1-p6h5ts-nr2fma.c
  src/math/gen/f32-tanh-neonfma-expm1minus-rr1-p6h5ts-nr2fmaadj.c
  src/math/gen/f32-tanh-neonfma-expm1minus-rr1-p6h5ts-nr2recps.c
  src/math/gen/f32-tanh-neonfma-expm1minus-rr1-p6h5ts-nr2recpsadj.c)

SET(ALL_NEONFMA_AARCH64_MICROKERNEL_SRCS
  src/f32-conv-hwc2chw/f32-conv-hwc2chw-3x3s2p1c3x4-aarch64-neonfma-2x2.c
  src/f32-conv-hwc/gen/f32-conv-hwc-3x3s2p0p1c3x4-aarch64-neonfma-2x1.c
  src/f32-conv-hwc/gen/f32-conv-hwc-3x3s2p0p1c3x4-aarch64-neonfma-2x2.c
  src/f32-conv-hwc/gen/f32-conv-hwc-3x3s2p0p1c3x8-aarch64-neonfma-2x1.c
  src/f32-conv-hwc/gen/f32-conv-hwc-3x3s2p0p1c3x8-aarch64-neonfma-2x2.c
  src/f32-conv-hwc/gen/f32-conv-hwc-3x3s2p1c3x4-aarch64-neonfma-2x1.c
  src/f32-conv-hwc/gen/f32-conv-hwc-3x3s2p1c3x4-aarch64-neonfma-2x2.c
  src/f32-conv-hwc/gen/f32-conv-hwc-3x3s2p1c3x8-aarch64-neonfma-2x1.c
  src/f32-conv-hwc/gen/f32-conv-hwc-3x3s2p1c3x8-aarch64-neonfma-2x2.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-aarch64-neonfma-1x4-acc2.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-aarch64-neonfma-1x4-acc3.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-aarch64-neonfma-1x4-acc4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-aarch64-neonfma-1x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-aarch64-neonfma-2x4-acc2.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-aarch64-neonfma-2x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-aarch64-neonfma-3x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-aarch64-neonfma-4x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-aarch64-neonfma-5x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-aarch64-neonfma-6x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-aarch64-neonfma-1x4-acc2.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-aarch64-neonfma-1x4-acc3.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-aarch64-neonfma-1x4-acc4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-aarch64-neonfma-1x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-aarch64-neonfma-2x4-acc2.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-aarch64-neonfma-2x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-aarch64-neonfma-3x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-aarch64-neonfma-4x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-aarch64-neonfma-1x4-acc2.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-aarch64-neonfma-1x4-acc3.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-aarch64-neonfma-1x4-acc4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-aarch64-neonfma-1x4-acc5.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-aarch64-neonfma-1x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-aarch64-neonfma-2x4-acc2.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-aarch64-neonfma-2x4-acc3.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-aarch64-neonfma-2x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-aarch64-neonfma-3x4-acc2.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-aarch64-neonfma-3x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-aarch64-neonfma-4x4-acc2.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-aarch64-neonfma-4x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-aarch64-neonfma-5x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-aarch64-neonfma-1x4-acc2.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-aarch64-neonfma-1x4-acc3.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-aarch64-neonfma-1x4-acc4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-aarch64-neonfma-1x4-acc5.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-aarch64-neonfma-1x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-aarch64-neonfma-2x4-acc2.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-aarch64-neonfma-2x4-acc3.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-aarch64-neonfma-2x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-aarch64-neonfma-3x4-acc2.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-aarch64-neonfma-3x4.c
  src/f32-gemm/gen/f32-gemm-1x8-minmax-aarch64-neonfma-lane-ld64.c
  src/f32-gemm/gen/f32-gemm-1x16-minmax-aarch64-neonfma-lane-ld128.c
  src/f32-gemm/gen/f32-gemm-4x2-minmax-aarch64-neonfma-lane-ld64.c
  src/f32-gemm/gen/f32-gemm-4x8-minmax-aarch64-neonfma-lane-ld64.c
  src/f32-gemm/gen/f32-gemm-4x8-minmax-aarch64-neonfma-lane-ld128.c
  src/f32-gemm/gen/f32-gemm-4x16-minmax-aarch64-neonfma-lane-ld128.c
  src/f32-gemm/gen/f32-gemm-5x8-minmax-aarch64-neonfma-lane-ld64.c
  src/f32-gemm/gen/f32-gemm-6x2-minmax-aarch64-neonfma-lane-ld64.c
  src/f32-gemm/gen/f32-gemm-6x8-minmax-aarch64-neonfma-lane-ld64.c
  src/f32-gemm/gen/f32-gemm-6x8-minmax-aarch64-neonfma-lane-ld128.c
  src/f32-gemminc/gen/f32-gemminc-1x8-minmax-aarch64-neonfma-lane-ld64.c
  src/f32-gemminc/gen/f32-gemminc-4x8-minmax-aarch64-neonfma-lane-ld64.c
  src/f32-gemminc/gen/f32-gemminc-4x8-minmax-aarch64-neonfma-lane-ld128.c
  src/f32-gemminc/gen/f32-gemminc-5x8-minmax-aarch64-neonfma-lane-ld64.c
  src/f32-gemminc/gen/f32-gemminc-6x8-minmax-aarch64-neonfma-lane-ld64.c
  src/f32-gemminc/gen/f32-gemminc-6x8-minmax-aarch64-neonfma-lane-ld128.c
  src/f32-igemm/gen/f32-igemm-1x8-minmax-aarch64-neonfma-lane-ld64.c
  src/f32-igemm/gen/f32-igemm-4x2-minmax-aarch64-neonfma-lane-ld64.c
  src/f32-igemm/gen/f32-igemm-4x4-minmax-aarch64-neonfma-lane-ld64.c
  src/f32-igemm/gen/f32-igemm-4x8-minmax-aarch64-neonfma-lane-ld64.c
  src/f32-igemm/gen/f32-igemm-4x8-minmax-aarch64-neonfma-lane-ld128.c
  src/f32-igemm/gen/f32-igemm-6x2-minmax-aarch64-neonfma-lane-ld64.c
  src/f32-igemm/gen/f32-igemm-6x8-minmax-aarch64-neonfma-lane-ld64.c
  src/f32-igemm/gen/f32-igemm-6x8-minmax-aarch64-neonfma-lane-ld128.c
  src/f32-ppmm/gen/f32-ppmm-4x8-minmax-aarch64-neonfma-prfm.c
  src/f32-ppmm/gen/f32-ppmm-4x8-minmax-aarch64-neonfma.c
  src/f32-ppmm/gen/f32-ppmm-4x16-minmax-aarch64-neonfma-prfm.c
  src/f32-ppmm/gen/f32-ppmm-4x16-minmax-aarch64-neonfma.c
  src/f32-ppmm/gen/f32-ppmm-8x8-minmax-aarch64-neonfma-prfm.c
  src/f32-ppmm/gen/f32-ppmm-8x8-minmax-aarch64-neonfma.c
  src/f32-qc4w-gemm/gen/f32-qc4w-gemm-1x8-minmax-aarch64-neonfma-lane-ld64.c
  src/f32-qc4w-gemm/gen/f32-qc4w-gemm-1x8-minmax-aarch64-neonfma-lane-ld128.c
  src/f32-qc4w-gemm/gen/f32-qc4w-gemm-4x8-minmax-aarch64-neonfma-lane-ld64.c
  src/f32-qc4w-gemm/gen/f32-qc4w-gemm-4x8-minmax-aarch64-neonfma-lane-ld128.c
  src/f32-qc4w-gemm/gen/f32-qc4w-gemm-5x8-minmax-aarch64-neonfma-lane-ld64.c
  src/f32-qc4w-gemm/gen/f32-qc4w-gemm-6x8-minmax-aarch64-neonfma-lane-ld64.c
  src/f32-qc4w-gemm/gen/f32-qc4w-gemm-6x8-minmax-aarch64-neonfma-lane-ld128.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-aarch64-neonfma-lane-ld64.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-aarch64-neonfma-lane-ld128.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x16-minmax-aarch64-neonfma-lane-ld128.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x2-minmax-aarch64-neonfma-lane-ld64.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-minmax-aarch64-neonfma-lane-ld64.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-minmax-aarch64-neonfma-lane-ld128.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x16-minmax-aarch64-neonfma-lane-ld128.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-minmax-aarch64-neonfma-lane-ld64.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x2-minmax-aarch64-neonfma-lane-ld64.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-minmax-aarch64-neonfma-lane-ld64.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-minmax-aarch64-neonfma-lane-ld128.c
  src/f32-spmm/gen/f32-spmm-4x2-minmax-aarch64-neonfma.c
  src/f32-spmm/gen/f32-spmm-4x4-minmax-aarch64-neonfma.c
  src/f32-spmm/gen/f32-spmm-8x2-minmax-aarch64-neonfma.c
  src/f32-spmm/gen/f32-spmm-8x4-minmax-aarch64-neonfma.c
  src/f32-spmm/gen/f32-spmm-12x2-minmax-aarch64-neonfma.c
  src/f32-spmm/gen/f32-spmm-12x4-minmax-aarch64-neonfma.c
  src/f32-spmm/gen/f32-spmm-16x2-minmax-aarch64-neonfma.c
  src/f32-spmm/gen/f32-spmm-16x4-minmax-aarch64-neonfma.c
  src/f32-spmm/gen/f32-spmm-32x2-minmax-aarch64-neonfma.c
  src/f32-spmm/gen/f32-spmm-32x4-minmax-aarch64-neonfma.c
  src/f32-vsigmoid/gen/f32-vsigmoid-aarch64-neonfma-rr1-lut64-p2-div-x4.c
  src/f32-vsigmoid/gen/f32-vsigmoid-aarch64-neonfma-rr1-lut64-p2-div-x8.c
  src/f32-vsigmoid/gen/f32-vsigmoid-aarch64-neonfma-rr1-lut64-p2-div-x12.c
  src/f32-vsigmoid/gen/f32-vsigmoid-aarch64-neonfma-rr1-lut64-p2-div-x16.c
  src/f32-vsigmoid/gen/f32-vsigmoid-aarch64-neonfma-rr1-lut64-p2-div-x20.c
  src/f32-vsigmoid/gen/f32-vsigmoid-aarch64-neonfma-rr1-lut64-p2-div-x24.c
  src/f32-vsigmoid/gen/f32-vsigmoid-aarch64-neonfma-rr1-lut2048-p1-div-x4.c
  src/f32-vsigmoid/gen/f32-vsigmoid-aarch64-neonfma-rr1-lut2048-p1-div-x8.c
  src/f32-vsigmoid/gen/f32-vsigmoid-aarch64-neonfma-rr1-lut2048-p1-div-x12.c
  src/f32-vsigmoid/gen/f32-vsigmoid-aarch64-neonfma-rr1-lut2048-p1-div-x16.c
  src/f32-vsigmoid/gen/f32-vsigmoid-aarch64-neonfma-rr1-lut2048-p1-div-x20.c
  src/f32-vsigmoid/gen/f32-vsigmoid-aarch64-neonfma-rr1-lut2048-p1-div-x24.c
  src/f32-vsigmoid/gen/f32-vsigmoid-aarch64-neonfma-rr1-p5-div-x4.c
  src/f32-vsigmoid/gen/f32-vsigmoid-aarch64-neonfma-rr1-p5-div-x8.c
  src/f32-vsigmoid/gen/f32-vsigmoid-aarch64-neonfma-rr1-p5-div-x12.c
  src/f32-vsigmoid/gen/f32-vsigmoid-aarch64-neonfma-rr1-p5-div-x16.c
  src/f32-vsigmoid/gen/f32-vsigmoid-aarch64-neonfma-rr1-p5-div-x20.c
  src/f32-vsigmoid/gen/f32-vsigmoid-aarch64-neonfma-rr1-p5-div-x24.c
  src/f32-vtanh/gen/f32-vtanh-aarch64-neonfma-expm1minus-rr1-lut8-p4h3ts-div-x4.c
  src/f32-vtanh/gen/f32-vtanh-aarch64-neonfma-expm1minus-rr1-lut8-p4h3ts-div-x8.c
  src/f32-vtanh/gen/f32-vtanh-aarch64-neonfma-expm1minus-rr1-lut8-p4h3ts-div-x12.c
  src/f32-vtanh/gen/f32-vtanh-aarch64-neonfma-expm1minus-rr1-lut8-p4h3ts-div-x16.c
  src/f32-vtanh/gen/f32-vtanh-aarch64-neonfma-expm1minus-rr1-p6h5ts-div-x4.c
  src/f32-vtanh/gen/f32-vtanh-aarch64-neonfma-expm1minus-rr1-p6h5ts-div-x8.c
  src/f32-vtanh/gen/f32-vtanh-aarch64-neonfma-expm1minus-rr1-p6h5ts-div-x12.c
  src/f32-vtanh/gen/f32-vtanh-aarch64-neonfma-expm1minus-rr1-p6h5ts-div-x16.c
  src/math/f32-sigmoid-aarch64-neonfma-rr1-lut64-p2-div.c
  src/math/f32-sigmoid-aarch64-neonfma-rr1-lut2048-p1-div.c
  src/math/f32-sigmoid-aarch64-neonfma-rr1-p5-div.c
  src/math/f32-sigmoid-aarch64-neonfma-rr2-lut64-p2-div.c
  src/math/f32-sigmoid-aarch64-neonfma-rr2-lut2048-p1-div.c
  src/math/f32-sigmoid-aarch64-neonfma-rr2-p5-div.c
  src/math/gen/f32-tanh-aarch64-neonfma-expm1minus-rr1-lut8-p4h3ps-div.c
  src/math/gen/f32-tanh-aarch64-neonfma-expm1minus-rr1-p6h5ts-div.c)

SET(ALL_NEONFP16_MICROKERNEL_SRCS
  src/f16-f32-vcvt/gen/f16-f32-vcvt-neonfp16-x8.c
  src/f16-f32-vcvt/gen/f16-f32-vcvt-neonfp16-x16.c
  src/f16-f32acc-rsum/gen/f16-f32acc-rsum-neonfp16-x4.c
  src/f16-f32acc-rsum/gen/f16-f32acc-rsum-neonfp16-x8.c
  src/f16-f32acc-rsum/gen/f16-f32acc-rsum-neonfp16-x16-acc2.c
  src/f16-f32acc-rsum/gen/f16-f32acc-rsum-neonfp16-x24-acc3.c
  src/f16-f32acc-rsum/gen/f16-f32acc-rsum-neonfp16-x32-acc2.c
  src/f16-f32acc-rsum/gen/f16-f32acc-rsum-neonfp16-x32-acc4.c
  src/f32-f16-vcvt/gen/f32-f16-vcvt-neonfp16-x8.c
  src/f32-f16-vcvt/gen/f32-f16-vcvt-neonfp16-x16.c
  src/math/f16-f32-cvt-neonfp16.c
  src/math/f32-f16-cvt-neonfp16.c)

SET(ALL_NEONFP16ARITH_MICROKERNEL_SRCS
  src/f16-avgpool/f16-avgpool-9p8x-minmax-neonfp16arith-c8.c
  src/f16-avgpool/f16-avgpool-9x-minmax-neonfp16arith-c8.c
  src/f16-conv-hwc2chw/f16-conv-hwc2chw-3x3s2p1c3x4-neonfp16arith-2x2.c
  src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-3x3p1-minmax-neonfp16arith-1x8-acc2.c
  src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-3x3p1-minmax-neonfp16arith-1x8-acc3.c
  src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-3x3p1-minmax-neonfp16arith-1x8-acc4.c
  src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-3x3p1-minmax-neonfp16arith-1x8.c
  src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-3x3p1-minmax-neonfp16arith-2x8-acc2.c
  src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-3x3p1-minmax-neonfp16arith-2x8.c
  src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-3x3p1-minmax-neonfp16arith-3x8.c
  src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-3x3p1-minmax-neonfp16arith-4x8.c
  src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-3x3p1-minmax-neonfp16arith-5x8.c
  src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-3x3p1-minmax-neonfp16arith-6x8.c
  src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-3x3s2p1-minmax-neonfp16arith-1x8-acc2.c
  src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-3x3s2p1-minmax-neonfp16arith-1x8-acc3.c
  src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-3x3s2p1-minmax-neonfp16arith-1x8-acc4.c
  src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-3x3s2p1-minmax-neonfp16arith-1x8.c
  src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-3x3s2p1-minmax-neonfp16arith-2x8-acc2.c
  src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-3x3s2p1-minmax-neonfp16arith-2x8.c
  src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-3x3s2p1-minmax-neonfp16arith-3x8.c
  src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-3x3s2p1-minmax-neonfp16arith-4x8.c
  src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-5x5p2-minmax-neonfp16arith-1x8-acc2.c
  src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-5x5p2-minmax-neonfp16arith-1x8-acc3.c
  src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-5x5p2-minmax-neonfp16arith-1x8-acc4.c
  src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-5x5p2-minmax-neonfp16arith-1x8-acc5.c
  src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-5x5p2-minmax-neonfp16arith-1x8.c
  src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-5x5p2-minmax-neonfp16arith-2x8-acc2.c
  src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-5x5p2-minmax-neonfp16arith-2x8-acc3.c
  src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-5x5p2-minmax-neonfp16arith-2x8.c
  src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-5x5p2-minmax-neonfp16arith-3x8-acc2.c
  src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-5x5p2-minmax-neonfp16arith-3x8.c
  src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-5x5p2-minmax-neonfp16arith-4x8-acc2.c
  src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-5x5p2-minmax-neonfp16arith-4x8.c
  src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-5x5p2-minmax-neonfp16arith-5x8.c
  src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-5x5s2p2-minmax-neonfp16arith-1x8-acc2.c
  src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-5x5s2p2-minmax-neonfp16arith-1x8-acc3.c
  src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-5x5s2p2-minmax-neonfp16arith-1x8-acc4.c
  src/f16-dwconv2d-chw/gen/f16-dwconv2d-chw-5x5s2p2-minmax-neonfp16arith-1x8-acc5.c
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  src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-nr1recps-x8.c
  src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-nr1recps-x16.c
  src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-nr1recps-x24.c
  src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-nr1recps-x32.c
  src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-nr1recps-x40.c
  src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-nr1recps-x48.c
  src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-nr1recps-x56.c
  src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-nr1recps-x64.c
  src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-nr1recps-x72.c
  src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-nr1recps-x80.c
  src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-recpeadj-x8.c
  src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-recpeadj-x16.c
  src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-recpeadj-x24.c
  src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-recpeadj-x32.c
  src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-recpeadj-x40.c
  src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-recpeadj-x48.c
  src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-recpeadj-x56.c
  src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-recpeadj-x64.c
  src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-recpeadj-x72.c
  src/f16-vtanh/gen/f16-vtanh-neonfp16arith-expm1minus-rr1-p3h2ts-recpeadj-x80.c
  src/f16-vunary/gen/f16-vabs-neonfp16arith-x8.c
  src/f16-vunary/gen/f16-vabs-neonfp16arith-x16.c
  src/f16-vunary/gen/f16-vneg-neonfp16arith-x8.c
  src/f16-vunary/gen/f16-vneg-neonfp16arith-x16.c
  src/f16-vunary/gen/f16-vsqr-neonfp16arith-x8.c
  src/f16-vunary/gen/f16-vsqr-neonfp16arith-x16.c
  src/math/f16-exp-neonfp16arith-rr2-p3.c
  src/math/f16-expm1minus-neonfp16arith-rr1-p3.c
  src/math/f16-expm1minus-neonfp16arith-rr2-p3.c
  src/math/f16-expminus-neonfp16arith-rr1-p2.c
  src/math/f16-expminus-neonfp16arith-rr1-p3.c
  src/math/f16-expminus-neonfp16arith-rr2-p2.c
  src/math/f16-expminus-neonfp16arith-rr2-p3.c
  src/math/f16-sigmoid-neonfp16arith-rr2-p2-nr1fma.c
  src/math/f16-sigmoid-neonfp16arith-rr2-p2-nr1recps.c
  src/math/f16-sigmoid-neonfp16arith-rr2-p2-recpe.c
  src/math/f16-sigmoid-neonfp16arith-rr2-p3-nr1fma.c
  src/math/f16-sigmoid-neonfp16arith-rr2-p3-nr1recps.c
  src/math/f16-sigmoid-neonfp16arith-rr2-p3-recpe.c
  src/math/f16-sqrt-neonfp16arith-nr1fma1adj.c
  src/math/f16-sqrt-neonfp16arith-nr1fma.c
  src/math/f16-sqrt-neonfp16arith-nr1rsqrts.c
  src/math/gen/f16-tanh-neonfp16arith-expm1minus-rr1-p3h1ts-nr1fma.c
  src/math/gen/f16-tanh-neonfp16arith-expm1minus-rr1-p3h1ts-nr1fmaadj.c
  src/math/gen/f16-tanh-neonfp16arith-expm1minus-rr1-p3h1ts-nr1recps.c
  src/math/gen/f16-tanh-neonfp16arith-expm1minus-rr1-p3h1ts-nr1recpsadj.c
  src/math/gen/f16-tanh-neonfp16arith-expm1minus-rr1-p3h1ts-recpe.c
  src/math/gen/f16-tanh-neonfp16arith-expm1minus-rr1-p3h1ts-recpeadj.c
  src/math/gen/f16-tanh-neonfp16arith-expm1minus-rr1-p3h2ts-nr1fma.c
  src/math/gen/f16-tanh-neonfp16arith-expm1minus-rr1-p3h2ts-nr1fmaadj.c
  src/math/gen/f16-tanh-neonfp16arith-expm1minus-rr1-p3h2ts-nr1recps.c
  src/math/gen/f16-tanh-neonfp16arith-expm1minus-rr1-p3h2ts-nr1recpsadj.c
  src/math/gen/f16-tanh-neonfp16arith-expm1minus-rr1-p3h2ts-recpe.c
  src/math/gen/f16-tanh-neonfp16arith-expm1minus-rr1-p3h2ts-recpeadj.c)

SET(ALL_NEONFP16ARITH_AARCH64_MICROKERNEL_SRCS
  src/f16-vbinary/gen/f16-vdiv-minmax-aarch64-neonfp16arith-x8.c
  src/f16-vbinary/gen/f16-vdiv-minmax-aarch64-neonfp16arith-x16.c
  src/f16-vbinary/gen/f16-vdivc-minmax-aarch64-neonfp16arith-x8.c
  src/f16-vbinary/gen/f16-vdivc-minmax-aarch64-neonfp16arith-x16.c
  src/f16-vbinary/gen/f16-vrdivc-minmax-aarch64-neonfp16arith-x8.c
  src/f16-vbinary/gen/f16-vrdivc-minmax-aarch64-neonfp16arith-x16.c
  src/f16-vsigmoid/gen/f16-vsigmoid-aarch64-neonfp16arith-rr2-p2-div-x8.c
  src/f16-vsigmoid/gen/f16-vsigmoid-aarch64-neonfp16arith-rr2-p2-div-x16.c
  src/f16-vsigmoid/gen/f16-vsigmoid-aarch64-neonfp16arith-rr2-p2-div-x24.c
  src/f16-vsigmoid/gen/f16-vsigmoid-aarch64-neonfp16arith-rr2-p2-div-x32.c
  src/f16-vsigmoid/gen/f16-vsigmoid-aarch64-neonfp16arith-rr2-p2-div-x40.c
  src/f16-vsigmoid/gen/f16-vsigmoid-aarch64-neonfp16arith-rr2-p2-div-x48.c
  src/f16-vsigmoid/gen/f16-vsigmoid-aarch64-neonfp16arith-rr2-p2-div-x56.c
  src/f16-vsigmoid/gen/f16-vsigmoid-aarch64-neonfp16arith-rr2-p2-div-x64.c
  src/f16-vsqrt/gen/f16-vsqrt-aarch64-neonfp16arith-sqrt-x8.c
  src/f16-vsqrt/gen/f16-vsqrt-aarch64-neonfp16arith-sqrt-x16.c
  src/f16-vtanh/gen/f16-vtanh-aarch64-neonfp16arith-expm1minus-rr1-p3h2ts-div-x8.c
  src/f16-vtanh/gen/f16-vtanh-aarch64-neonfp16arith-expm1minus-rr1-p3h2ts-div-x16.c
  src/f16-vtanh/gen/f16-vtanh-aarch64-neonfp16arith-expm1minus-rr1-p3h2ts-div-x24.c
  src/f16-vtanh/gen/f16-vtanh-aarch64-neonfp16arith-expm1minus-rr1-p3h2ts-div-x32.c
  src/f16-vtanh/gen/f16-vtanh-aarch64-neonfp16arith-expm1minus-rr1-p3h2ts-div-x40.c
  src/f16-vtanh/gen/f16-vtanh-aarch64-neonfp16arith-expm1minus-rr1-p3h2ts-div-x48.c
  src/f16-vtanh/gen/f16-vtanh-aarch64-neonfp16arith-expm1minus-rr1-p3h2ts-div-x56.c
  src/f16-vtanh/gen/f16-vtanh-aarch64-neonfp16arith-expm1minus-rr1-p3h2ts-div-x64.c
  src/f16-vtanh/gen/f16-vtanh-aarch64-neonfp16arith-expm1minus-rr1-p3h2ts-div-x72.c
  src/f16-vtanh/gen/f16-vtanh-aarch64-neonfp16arith-expm1minus-rr1-p3h2ts-div-x80.c
  src/math/f16-sigmoid-aarch64-neonfp16arith-rr1-p2-div.c
  src/math/f16-sigmoid-aarch64-neonfp16arith-rr1-p3-div.c
  src/math/f16-sigmoid-aarch64-neonfp16arith-rr2-p2-div.c
  src/math/f16-sigmoid-aarch64-neonfp16arith-rr2-p3-div.c
  src/math/f16-sqrt-aarch64-neonfp16arith-sqrt.c
  src/math/gen/f16-tanh-aarch64-neonfp16arith-expm1minus-rr1-p3h1ts-div.c
  src/math/gen/f16-tanh-aarch64-neonfp16arith-expm1minus-rr1-p3h2ts-div.c)

SET(ALL_NEONV8_MICROKERNEL_SRCS
  src/f32-qs8-vcvt/gen/f32-qs8-vcvt-neonv8-x8.c
  src/f32-qs8-vcvt/gen/f32-qs8-vcvt-neonv8-x16.c
  src/f32-qs8-vcvt/gen/f32-qs8-vcvt-neonv8-x24.c
  src/f32-qs8-vcvt/gen/f32-qs8-vcvt-neonv8-x32.c
  src/f32-qu8-vcvt/gen/f32-qu8-vcvt-neonv8-x8.c
  src/f32-qu8-vcvt/gen/f32-qu8-vcvt-neonv8-x16.c
  src/f32-qu8-vcvt/gen/f32-qu8-vcvt-neonv8-x24.c
  src/f32-qu8-vcvt/gen/f32-qu8-vcvt-neonv8-x32.c
  src/f32-vrnd/gen/f32-vrndd-neonv8-x4.c
  src/f32-vrnd/gen/f32-vrndd-neonv8-x8.c
  src/f32-vrnd/gen/f32-vrndne-neonv8-x4.c
  src/f32-vrnd/gen/f32-vrndne-neonv8-x8.c
  src/f32-vrnd/gen/f32-vrndu-neonv8-x4.c
  src/f32-vrnd/gen/f32-vrndu-neonv8-x8.c
  src/f32-vrnd/gen/f32-vrndz-neonv8-x4.c
  src/f32-vrnd/gen/f32-vrndz-neonv8-x8.c
  src/math/f32-qs8-cvt-neonv8.c
  src/math/f32-qu8-cvt-neonv8.c
  src/math/f32-roundd-neonv8.c
  src/math/f32-roundne-neonv8.c
  src/math/f32-roundu-neonv8.c
  src/math/f32-roundz-neonv8.c
  src/qs8-dwconv/gen/qs8-dwconv-5f5m5l8c8s8r-minmax-fp32-neonv8-mul16.c
  src/qs8-dwconv/gen/qs8-dwconv-5f5m5l16c8s8r-minmax-fp32-neonv8-mul16.c
  src/qs8-dwconv/gen/qs8-dwconv-5f5m5l32c8s8r-minmax-fp32-neonv8-mul16.c
  src/qs8-dwconv/gen/qs8-dwconv-6f6m7l8c8s8r-minmax-fp32-neonv8-mul16.c
  src/qs8-dwconv/gen/qs8-dwconv-6f6m7l16c8s8r-minmax-fp32-neonv8-mul16.c
  src/qs8-dwconv/gen/qs8-dwconv-6f6m7l32c8s8r-minmax-fp32-neonv8-mul16.c
  src/qs8-dwconv/gen/qs8-dwconv-8f8m9l8c8s8r-minmax-fp32-neonv8-mul16.c
  src/qs8-dwconv/gen/qs8-dwconv-8f8m9l16c8s8r-minmax-fp32-neonv8-mul16.c
  src/qs8-dwconv/gen/qs8-dwconv-8f8m9l32c8s8r-minmax-fp32-neonv8-mul16.c
  src/qs8-dwconv/gen/qs8-dwconv-9p8c-minmax-fp32-neonv8-mul16.c
  src/qs8-dwconv/gen/qs8-dwconv-9p16c-minmax-fp32-neonv8-mul16.c
  src/qs8-dwconv/gen/qs8-dwconv-9p32c-minmax-fp32-neonv8-mul16.c
  src/qs8-dwconv/gen/qs8-dwconv-25p8c-minmax-fp32-neonv8-mul16.c
  src/qs8-dwconv/gen/qs8-dwconv-25p16c-minmax-fp32-neonv8-mul16.c
  src/qs8-dwconv/gen/qs8-dwconv-25p32c-minmax-fp32-neonv8-mul16.c
  src/qs8-gavgpool/gen/qs8-gavgpool-7p7x-minmax-fp32-neonv8-c8.c
  src/qs8-gavgpool/gen/qs8-gavgpool-7p7x-minmax-fp32-neonv8-c16.c
  src/qs8-gavgpool/gen/qs8-gavgpool-7p7x-minmax-fp32-neonv8-c24.c
  src/qs8-gavgpool/gen/qs8-gavgpool-7p7x-minmax-fp32-neonv8-c32.c
  src/qs8-gavgpool/gen/qs8-gavgpool-7x-minmax-fp32-neonv8-c8.c
  src/qs8-gavgpool/gen/qs8-gavgpool-7x-minmax-fp32-neonv8-c16.c
  src/qs8-gavgpool/gen/qs8-gavgpool-7x-minmax-fp32-neonv8-c24.c
  src/qs8-gavgpool/gen/qs8-gavgpool-7x-minmax-fp32-neonv8-c32.c
  src/qs8-gemm/gen/qs8-gemm-1x8c2-minmax-fp32-neonv8-mlal-dup.c
  src/qs8-gemm/gen/qs8-gemm-1x8c2-minmax-fp32-neonv8-mlal-ld1r.c
  src/qs8-gemm/gen/qs8-gemm-1x8c2-minmax-fp32-neonv8-mlal-ld2r.c
  src/qs8-gemm/gen/qs8-gemm-1x8c2-minmax-fp32-neonv8-mlal-ld4r.c
  src/qs8-gemm/gen/qs8-gemm-1x8c2s4-minmax-fp32-neonv8-mlal.c
  src/qs8-gemm/gen/qs8-gemm-1x8c4-minmax-fp32-neonv8-mlal-dup.c
  src/qs8-gemm/gen/qs8-gemm-1x8c4-minmax-fp32-neonv8-mlal-ld1r.c
  src/qs8-gemm/gen/qs8-gemm-1x8c4-minmax-fp32-neonv8-mlal-ld2r.c
  src/qs8-gemm/gen/qs8-gemm-1x8c4s2-minmax-fp32-neonv8-mlal.c
  src/qs8-gemm/gen/qs8-gemm-1x8c8-minmax-fp32-neonv8-mlal.c
  src/qs8-gemm/gen/qs8-gemm-1x16-minmax-fp32-neonv8-mlal-lane.c
  src/qs8-gemm/gen/qs8-gemm-2x8c2-minmax-fp32-neonv8-mlal-dup.c
  src/qs8-gemm/gen/qs8-gemm-2x8c2-minmax-fp32-neonv8-mlal-ld1r.c
  src/qs8-gemm/gen/qs8-gemm-2x8c2-minmax-fp32-neonv8-mlal-ld2r.c
  src/qs8-gemm/gen/qs8-gemm-2x8c2-minmax-fp32-neonv8-mlal-ld4r.c
  src/qs8-gemm/gen/qs8-gemm-2x8c2s4-minmax-fp32-neonv8-mlal.c
  src/qs8-gemm/gen/qs8-gemm-2x8c4-minmax-fp32-neonv8-mlal-dup.c
  src/qs8-gemm/gen/qs8-gemm-2x8c4-minmax-fp32-neonv8-mlal-ld1r.c
  src/qs8-gemm/gen/qs8-gemm-2x8c4-minmax-fp32-neonv8-mlal-ld2r.c
  src/qs8-gemm/gen/qs8-gemm-2x8c4s2-minmax-fp32-neonv8-mlal.c
  src/qs8-gemm/gen/qs8-gemm-2x8c8-minmax-fp32-neonv8-mlal.c
  src/qs8-gemm/gen/qs8-gemm-4x16-minmax-fp32-neonv8-mlal-lane.c
  src/qs8-igemm/gen/qs8-igemm-1x8c2-minmax-fp32-neonv8-mlal-dup.c
  src/qs8-igemm/gen/qs8-igemm-1x8c2-minmax-fp32-neonv8-mlal-ld1r.c
  src/qs8-igemm/gen/qs8-igemm-1x8c2-minmax-fp32-neonv8-mlal-ld2r.c
  src/qs8-igemm/gen/qs8-igemm-1x8c2-minmax-fp32-neonv8-mlal-ld4r.c
  src/qs8-igemm/gen/qs8-igemm-1x8c2s4-minmax-fp32-neonv8-mlal.c
  src/qs8-igemm/gen/qs8-igemm-1x8c4-minmax-fp32-neonv8-mlal-dup.c
  src/qs8-igemm/gen/qs8-igemm-1x8c4-minmax-fp32-neonv8-mlal-ld1r.c
  src/qs8-igemm/gen/qs8-igemm-1x8c4-minmax-fp32-neonv8-mlal-ld2r.c
  src/qs8-igemm/gen/qs8-igemm-1x8c4s2-minmax-fp32-neonv8-mlal.c
  src/qs8-igemm/gen/qs8-igemm-1x8c8-minmax-fp32-neonv8-mlal.c
  src/qs8-igemm/gen/qs8-igemm-1x16-minmax-fp32-neonv8-mlal-lane.c
  src/qs8-igemm/gen/qs8-igemm-2x8c2-minmax-fp32-neonv8-mlal-dup.c
  src/qs8-igemm/gen/qs8-igemm-2x8c2-minmax-fp32-neonv8-mlal-ld1r.c
  src/qs8-igemm/gen/qs8-igemm-2x8c2-minmax-fp32-neonv8-mlal-ld2r.c
  src/qs8-igemm/gen/qs8-igemm-2x8c2-minmax-fp32-neonv8-mlal-ld4r.c
  src/qs8-igemm/gen/qs8-igemm-2x8c2s4-minmax-fp32-neonv8-mlal.c
  src/qs8-igemm/gen/qs8-igemm-2x8c4-minmax-fp32-neonv8-mlal-dup.c
  src/qs8-igemm/gen/qs8-igemm-2x8c4-minmax-fp32-neonv8-mlal-ld1r.c
  src/qs8-igemm/gen/qs8-igemm-2x8c4-minmax-fp32-neonv8-mlal-ld2r.c
  src/qs8-igemm/gen/qs8-igemm-2x8c4s2-minmax-fp32-neonv8-mlal.c
  src/qs8-igemm/gen/qs8-igemm-2x8c8-minmax-fp32-neonv8-mlal.c
  src/qs8-igemm/gen/qs8-igemm-4x16-minmax-fp32-neonv8-mlal-lane.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-3p8c-minmax-fp32-neonv8-mla8-ld64.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-3p16c-minmax-fp32-neonv8-mla8-ld64.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-3p16c-minmax-fp32-neonv8-mla8-ld128.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l8c8s8r-minmax-fp32-neonv8-mla8-ld64.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l8c8s8r-minmax-fp32-neonv8-mul8-ld64.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l8c8s8r-minmax-fp32-neonv8-mul16.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l16c8s8r-minmax-fp32-neonv8-mla8-ld64.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l16c8s8r-minmax-fp32-neonv8-mla8-ld128.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l16c8s8r-minmax-fp32-neonv8-mul8-ld64.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l16c8s8r-minmax-fp32-neonv8-mul8-ld128.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l16c8s8r-minmax-fp32-neonv8-mul16.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l32c8s8r-minmax-fp32-neonv8-mul16.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l8c8s8r-minmax-fp32-neonv8-mla8-ld64.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l8c8s8r-minmax-fp32-neonv8-mul8-ld64.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l8c8s8r-minmax-fp32-neonv8-mul16.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l16c8s8r-minmax-fp32-neonv8-mla8-ld64.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l16c8s8r-minmax-fp32-neonv8-mla8-ld128.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l16c8s8r-minmax-fp32-neonv8-mul8-ld64.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l16c8s8r-minmax-fp32-neonv8-mul8-ld128.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l16c8s8r-minmax-fp32-neonv8-mul16.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l32c8s8r-minmax-fp32-neonv8-mul16.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l8c8s8r-minmax-fp32-neonv8-mla8-ld64.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l8c8s8r-minmax-fp32-neonv8-mul8-ld64.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l8c8s8r-minmax-fp32-neonv8-mul16.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l16c8s8r-minmax-fp32-neonv8-mla8-ld64.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l16c8s8r-minmax-fp32-neonv8-mla8-ld128.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l16c8s8r-minmax-fp32-neonv8-mul8-ld64.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l16c8s8r-minmax-fp32-neonv8-mul8-ld128.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l16c8s8r-minmax-fp32-neonv8-mul16.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l32c8s8r-minmax-fp32-neonv8-mul16.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p8c-minmax-fp32-neonv8-mla8-ld64.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p8c-minmax-fp32-neonv8-mul8-ld64.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p8c-minmax-fp32-neonv8-mul16.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-neonv8-mla8-ld64.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-neonv8-mla8-ld128.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-neonv8-mul8-ld64.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-neonv8-mul8-ld128.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-neonv8-mul16.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p32c-minmax-fp32-neonv8-mul16.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p8c-minmax-fp32-neonv8-mla8-ld64.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p8c-minmax-fp32-neonv8-mul8-ld64.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p8c-minmax-fp32-neonv8-mul16.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-neonv8-mla8-ld64.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-neonv8-mla8-ld128.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-neonv8-mul8-ld64.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-neonv8-mul8-ld128.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-neonv8-mul16.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p32c-minmax-fp32-neonv8-mul16.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8-minmax-fp32-neonv8-mlal-lane-prfm.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8-minmax-fp32-neonv8-mlal-lane.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8c2-minmax-fp32-neonv8-mlal-dup.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8c2-minmax-fp32-neonv8-mlal-ld1r.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8c2-minmax-fp32-neonv8-mlal-ld2r.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8c2-minmax-fp32-neonv8-mlal-ld4r.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8c2s4-minmax-fp32-neonv8-mlal.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8c4-minmax-fp32-neonv8-mlal-dup.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8c4-minmax-fp32-neonv8-mlal-ld1r.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8c4-minmax-fp32-neonv8-mlal-ld2r.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8c4s2-minmax-fp32-neonv8-mlal.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8c8-minmax-fp32-neonv8-mlal.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x16-minmax-fp32-neonv8-mlal-lane-prfm.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x16-minmax-fp32-neonv8-mlal-lane.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8-minmax-fp32-neonv8-mlal-lane-prfm.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8-minmax-fp32-neonv8-mlal-lane.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8c2-minmax-fp32-neonv8-mlal-dup.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8c2-minmax-fp32-neonv8-mlal-ld1r.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8c2-minmax-fp32-neonv8-mlal-ld2r.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8c2-minmax-fp32-neonv8-mlal-ld4r.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8c2s4-minmax-fp32-neonv8-mlal.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8c4-minmax-fp32-neonv8-mlal-dup.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8c4-minmax-fp32-neonv8-mlal-ld1r.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8c4-minmax-fp32-neonv8-mlal-ld2r.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8c4s2-minmax-fp32-neonv8-mlal.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8c8-minmax-fp32-neonv8-mlal.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x16-minmax-fp32-neonv8-mlal-lane-prfm.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x16-minmax-fp32-neonv8-mlal-lane.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x8-minmax-fp32-neonv8-mlal-lane-prfm.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x8-minmax-fp32-neonv8-mlal-lane.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x16-minmax-fp32-neonv8-mlal-lane-prfm.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x16-minmax-fp32-neonv8-mlal-lane.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x8-minmax-fp32-neonv8-mlal-lane-prfm.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x8-minmax-fp32-neonv8-mlal-lane.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x16-minmax-fp32-neonv8-mlal-lane-prfm.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x16-minmax-fp32-neonv8-mlal-lane.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-6x8-minmax-fp32-neonv8-mlal-lane-prfm.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-6x8-minmax-fp32-neonv8-mlal-lane.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-6x16-minmax-fp32-neonv8-mlal-lane-prfm.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-6x16-minmax-fp32-neonv8-mlal-lane.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8-minmax-fp32-neonv8-mlal-lane-prfm.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8-minmax-fp32-neonv8-mlal-lane.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8c2-minmax-fp32-neonv8-mlal-dup.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8c2-minmax-fp32-neonv8-mlal-ld1r.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8c2-minmax-fp32-neonv8-mlal-ld2r.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8c2-minmax-fp32-neonv8-mlal-ld4r.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8c2s4-minmax-fp32-neonv8-mlal.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8c4-minmax-fp32-neonv8-mlal-dup.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8c4-minmax-fp32-neonv8-mlal-ld1r.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8c4-minmax-fp32-neonv8-mlal-ld2r.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8c4s2-minmax-fp32-neonv8-mlal.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8c8-minmax-fp32-neonv8-mlal.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x16-minmax-fp32-neonv8-mlal-lane-prfm.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x16-minmax-fp32-neonv8-mlal-lane.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8-minmax-fp32-neonv8-mlal-lane-prfm.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8-minmax-fp32-neonv8-mlal-lane.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8c2-minmax-fp32-neonv8-mlal-dup.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8c2-minmax-fp32-neonv8-mlal-ld1r.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8c2-minmax-fp32-neonv8-mlal-ld2r.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8c2-minmax-fp32-neonv8-mlal-ld4r.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8c2s4-minmax-fp32-neonv8-mlal.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8c4-minmax-fp32-neonv8-mlal-dup.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8c4-minmax-fp32-neonv8-mlal-ld1r.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8c4-minmax-fp32-neonv8-mlal-ld2r.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8c4s2-minmax-fp32-neonv8-mlal.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8c8-minmax-fp32-neonv8-mlal.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x16-minmax-fp32-neonv8-mlal-lane-prfm.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x16-minmax-fp32-neonv8-mlal-lane.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x8-minmax-fp32-neonv8-mlal-lane-prfm.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x8-minmax-fp32-neonv8-mlal-lane.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x16-minmax-fp32-neonv8-mlal-lane-prfm.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x16-minmax-fp32-neonv8-mlal-lane.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x8-minmax-fp32-neonv8-mlal-lane-prfm.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x8-minmax-fp32-neonv8-mlal-lane.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x16-minmax-fp32-neonv8-mlal-lane-prfm.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x16-minmax-fp32-neonv8-mlal-lane.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-6x8-minmax-fp32-neonv8-mlal-lane-prfm.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-6x8-minmax-fp32-neonv8-mlal-lane.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-6x16-minmax-fp32-neonv8-mlal-lane-prfm.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-6x16-minmax-fp32-neonv8-mlal-lane.c
  src/qs8-vmul/gen/qs8-vmul-minmax-fp32-neonv8-ld64-x8.c
  src/qs8-vmul/gen/qs8-vmul-minmax-fp32-neonv8-ld64-x16.c
  src/qs8-vmul/gen/qs8-vmul-minmax-fp32-neonv8-ld128-x16.c
  src/qs8-vmulc/gen/qs8-vmulc-minmax-fp32-neonv8-ld64-x8.c
  src/qs8-vmulc/gen/qs8-vmulc-minmax-fp32-neonv8-ld64-x16.c
  src/qs8-vmulc/gen/qs8-vmulc-minmax-fp32-neonv8-ld128-x16.c
  src/qu8-dwconv/gen/qu8-dwconv-5f5m5l8c8s8r-minmax-fp32-neonv8-mul16.c
  src/qu8-dwconv/gen/qu8-dwconv-5f5m5l16c8s8r-minmax-fp32-neonv8-mul16.c
  src/qu8-dwconv/gen/qu8-dwconv-5f5m5l32c8s8r-minmax-fp32-neonv8-mul16.c
  src/qu8-dwconv/gen/qu8-dwconv-6f6m7l8c8s8r-minmax-fp32-neonv8-mul16.c
  src/qu8-dwconv/gen/qu8-dwconv-6f6m7l16c8s8r-minmax-fp32-neonv8-mul16.c
  src/qu8-dwconv/gen/qu8-dwconv-6f6m7l32c8s8r-minmax-fp32-neonv8-mul16.c
  src/qu8-dwconv/gen/qu8-dwconv-8f8m9l8c8s8r-minmax-fp32-neonv8-mul16.c
  src/qu8-dwconv/gen/qu8-dwconv-8f8m9l16c8s8r-minmax-fp32-neonv8-mul16.c
  src/qu8-dwconv/gen/qu8-dwconv-8f8m9l32c8s8r-minmax-fp32-neonv8-mul16.c
  src/qu8-dwconv/gen/qu8-dwconv-9p8c-minmax-fp32-neonv8-mul16.c
  src/qu8-dwconv/gen/qu8-dwconv-9p16c-minmax-fp32-neonv8-mul16.c
  src/qu8-dwconv/gen/qu8-dwconv-9p32c-minmax-fp32-neonv8-mul16.c
  src/qu8-dwconv/gen/qu8-dwconv-25p8c-minmax-fp32-neonv8-mul16.c
  src/qu8-dwconv/gen/qu8-dwconv-25p16c-minmax-fp32-neonv8-mul16.c
  src/qu8-dwconv/gen/qu8-dwconv-25p32c-minmax-fp32-neonv8-mul16.c
  src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-fp32-neonv8-c8.c
  src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-fp32-neonv8-c16.c
  src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-fp32-neonv8-c24.c
  src/qu8-gavgpool/gen/qu8-gavgpool-7p7x-minmax-fp32-neonv8-c32.c
  src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-fp32-neonv8-c8.c
  src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-fp32-neonv8-c16.c
  src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-fp32-neonv8-c24.c
  src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-fp32-neonv8-c32.c
  src/qu8-gemm/gen/qu8-gemm-1x16-minmax-fp32-neonv8-mlal-lane.c
  src/qu8-gemm/gen/qu8-gemm-4x16-minmax-fp32-neonv8-mlal-lane.c
  src/qu8-igemm/gen/qu8-igemm-1x16-minmax-fp32-neonv8-mlal-lane.c
  src/qu8-igemm/gen/qu8-igemm-4x16-minmax-fp32-neonv8-mlal-lane.c
  src/qu8-vmul/gen/qu8-vmul-minmax-fp32-neonv8-ld64-x8.c
  src/qu8-vmul/gen/qu8-vmul-minmax-fp32-neonv8-ld64-x16.c
  src/qu8-vmul/gen/qu8-vmul-minmax-fp32-neonv8-ld128-x16.c
  src/qu8-vmulc/gen/qu8-vmulc-minmax-fp32-neonv8-ld64-x8.c
  src/qu8-vmulc/gen/qu8-vmulc-minmax-fp32-neonv8-ld64-x16.c
  src/qu8-vmulc/gen/qu8-vmulc-minmax-fp32-neonv8-ld128-x16.c)

SET(ALL_RVV_MICROKERNEL_SRCS
  src/f32-vclamp/gen/f32-vclamp-rvv-x1v.c
  src/f32-vclamp/gen/f32-vclamp-rvv-x2v.c
  src/f32-vclamp/gen/f32-vclamp-rvv-x4v.c
  src/f32-vclamp/gen/f32-vclamp-rvv-x8v.c
  src/f32-vhswish/gen/f32-vhswish-rvv-x1v.c
  src/f32-vhswish/gen/f32-vhswish-rvv-x2v.c
  src/f32-vhswish/gen/f32-vhswish-rvv-x4v.c
  src/f32-vhswish/gen/f32-vhswish-rvv-x8v.c
  src/f32-vsqrt/gen/f32-vsqrt-rvv-sqrt-x1v.c
  src/f32-vsqrt/gen/f32-vsqrt-rvv-sqrt-x2v.c
  src/f32-vsqrt/gen/f32-vsqrt-rvv-sqrt-x4v.c
  src/f32-vsqrt/gen/f32-vsqrt-rvv-sqrt-x8v.c
  src/f32-vunary/gen/f32-vabs-rvv-x1v.c
  src/f32-vunary/gen/f32-vabs-rvv-x2v.c
  src/f32-vunary/gen/f32-vabs-rvv-x4v.c
  src/f32-vunary/gen/f32-vabs-rvv-x8v.c
  src/f32-vunary/gen/f32-vneg-rvv-x1v.c
  src/f32-vunary/gen/f32-vneg-rvv-x2v.c
  src/f32-vunary/gen/f32-vneg-rvv-x4v.c
  src/f32-vunary/gen/f32-vneg-rvv-x8v.c
  src/f32-vunary/gen/f32-vsqr-rvv-x1v.c
  src/f32-vunary/gen/f32-vsqr-rvv-x2v.c
  src/f32-vunary/gen/f32-vsqr-rvv-x4v.c
  src/f32-vunary/gen/f32-vsqr-rvv-x8v.c)

SET(ALL_SCALAR_MICROKERNEL_SRCS
  src/cs16-bfly4/cs16-bfly4-samples1-scalar.c
  src/cs16-bfly4/cs16-bfly4-samples4-scalar.c
  src/cs16-bfly4/gen/cs16-bfly4-scalar-x1.c
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  src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-fp32-scalar-imagic-c4.c
  src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-fp32-scalar-lrintf-c1.c
  src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-fp32-scalar-lrintf-c2.c
  src/qu8-gavgpool/gen/qu8-gavgpool-7x-minmax-fp32-scalar-lrintf-c4.c
  src/qu8-gemm/gen/qu8-gemm-1x2-minmax-fp32-scalar-fmagic.c
  src/qu8-gemm/gen/qu8-gemm-1x2-minmax-fp32-scalar-imagic.c
  src/qu8-gemm/gen/qu8-gemm-1x2-minmax-fp32-scalar-lrintf.c
  src/qu8-gemm/gen/qu8-gemm-1x2-minmax-rndnu-scalar.c
  src/qu8-gemm/gen/qu8-gemm-1x4-minmax-fp32-scalar-fmagic.c
  src/qu8-gemm/gen/qu8-gemm-1x4-minmax-fp32-scalar-imagic.c
  src/qu8-gemm/gen/qu8-gemm-1x4-minmax-fp32-scalar-lrintf.c
  src/qu8-gemm/gen/qu8-gemm-1x4-minmax-rndnu-scalar.c
  src/qu8-gemm/gen/qu8-gemm-2x2-minmax-fp32-scalar-fmagic.c
  src/qu8-gemm/gen/qu8-gemm-2x2-minmax-fp32-scalar-imagic.c
  src/qu8-gemm/gen/qu8-gemm-2x2-minmax-fp32-scalar-lrintf.c
  src/qu8-gemm/gen/qu8-gemm-2x2-minmax-rndnu-scalar.c
  src/qu8-gemm/gen/qu8-gemm-2x4-minmax-fp32-scalar-fmagic.c
  src/qu8-gemm/gen/qu8-gemm-2x4-minmax-fp32-scalar-imagic.c
  src/qu8-gemm/gen/qu8-gemm-2x4-minmax-fp32-scalar-lrintf.c
  src/qu8-gemm/gen/qu8-gemm-2x4-minmax-rndnu-scalar.c
  src/qu8-gemm/gen/qu8-gemm-3x2-minmax-fp32-scalar-fmagic.c
  src/qu8-gemm/gen/qu8-gemm-3x2-minmax-fp32-scalar-imagic.c
  src/qu8-gemm/gen/qu8-gemm-3x2-minmax-fp32-scalar-lrintf.c
  src/qu8-gemm/gen/qu8-gemm-3x2-minmax-rndnu-scalar.c
  src/qu8-gemm/gen/qu8-gemm-3x4-minmax-fp32-scalar-fmagic.c
  src/qu8-gemm/gen/qu8-gemm-3x4-minmax-fp32-scalar-imagic.c
  src/qu8-gemm/gen/qu8-gemm-3x4-minmax-fp32-scalar-lrintf.c
  src/qu8-gemm/gen/qu8-gemm-3x4-minmax-rndnu-scalar.c
  src/qu8-gemm/gen/qu8-gemm-4x2-minmax-fp32-scalar-fmagic.c
  src/qu8-gemm/gen/qu8-gemm-4x2-minmax-fp32-scalar-imagic.c
  src/qu8-gemm/gen/qu8-gemm-4x2-minmax-fp32-scalar-lrintf.c
  src/qu8-gemm/gen/qu8-gemm-4x2-minmax-rndnu-scalar.c
  src/qu8-gemm/gen/qu8-gemm-4x4-minmax-fp32-scalar-fmagic.c
  src/qu8-gemm/gen/qu8-gemm-4x4-minmax-fp32-scalar-imagic.c
  src/qu8-gemm/gen/qu8-gemm-4x4-minmax-fp32-scalar-lrintf.c
  src/qu8-gemm/gen/qu8-gemm-4x4-minmax-rndnu-scalar.c
  src/qu8-igemm/gen/qu8-igemm-1x2-minmax-fp32-scalar-fmagic.c
  src/qu8-igemm/gen/qu8-igemm-1x2-minmax-fp32-scalar-imagic.c
  src/qu8-igemm/gen/qu8-igemm-1x2-minmax-fp32-scalar-lrintf.c
  src/qu8-igemm/gen/qu8-igemm-1x2-minmax-rndnu-scalar.c
  src/qu8-igemm/gen/qu8-igemm-1x4-minmax-fp32-scalar-fmagic.c
  src/qu8-igemm/gen/qu8-igemm-1x4-minmax-fp32-scalar-imagic.c
  src/qu8-igemm/gen/qu8-igemm-1x4-minmax-fp32-scalar-lrintf.c
  src/qu8-igemm/gen/qu8-igemm-1x4-minmax-rndnu-scalar.c
  src/qu8-igemm/gen/qu8-igemm-2x2-minmax-fp32-scalar-fmagic.c
  src/qu8-igemm/gen/qu8-igemm-2x2-minmax-fp32-scalar-imagic.c
  src/qu8-igemm/gen/qu8-igemm-2x2-minmax-fp32-scalar-lrintf.c
  src/qu8-igemm/gen/qu8-igemm-2x2-minmax-rndnu-scalar.c
  src/qu8-igemm/gen/qu8-igemm-2x4-minmax-fp32-scalar-fmagic.c
  src/qu8-igemm/gen/qu8-igemm-2x4-minmax-fp32-scalar-imagic.c
  src/qu8-igemm/gen/qu8-igemm-2x4-minmax-fp32-scalar-lrintf.c
  src/qu8-igemm/gen/qu8-igemm-2x4-minmax-rndnu-scalar.c
  src/qu8-igemm/gen/qu8-igemm-3x2-minmax-fp32-scalar-fmagic.c
  src/qu8-igemm/gen/qu8-igemm-3x2-minmax-fp32-scalar-imagic.c
  src/qu8-igemm/gen/qu8-igemm-3x2-minmax-fp32-scalar-lrintf.c
  src/qu8-igemm/gen/qu8-igemm-3x2-minmax-rndnu-scalar.c
  src/qu8-igemm/gen/qu8-igemm-3x4-minmax-fp32-scalar-fmagic.c
  src/qu8-igemm/gen/qu8-igemm-3x4-minmax-fp32-scalar-imagic.c
  src/qu8-igemm/gen/qu8-igemm-3x4-minmax-fp32-scalar-lrintf.c
  src/qu8-igemm/gen/qu8-igemm-3x4-minmax-rndnu-scalar.c
  src/qu8-igemm/gen/qu8-igemm-4x2-minmax-fp32-scalar-fmagic.c
  src/qu8-igemm/gen/qu8-igemm-4x2-minmax-fp32-scalar-imagic.c
  src/qu8-igemm/gen/qu8-igemm-4x2-minmax-fp32-scalar-lrintf.c
  src/qu8-igemm/gen/qu8-igemm-4x2-minmax-rndnu-scalar.c
  src/qu8-igemm/gen/qu8-igemm-4x4-minmax-fp32-scalar-fmagic.c
  src/qu8-igemm/gen/qu8-igemm-4x4-minmax-fp32-scalar-imagic.c
  src/qu8-igemm/gen/qu8-igemm-4x4-minmax-fp32-scalar-lrintf.c
  src/qu8-igemm/gen/qu8-igemm-4x4-minmax-rndnu-scalar.c
  src/qu8-requantization/qu8-requantization-fp32-scalar-fmagic.c
  src/qu8-requantization/qu8-requantization-fp32-scalar-lrintf.c
  src/qu8-requantization/qu8-requantization-gemmlowp-scalar.c
  src/qu8-requantization/qu8-requantization-rndna-scalar-signed64.c
  src/qu8-requantization/qu8-requantization-rndna-scalar-unsigned32.c
  src/qu8-requantization/qu8-requantization-rndna-scalar-unsigned64.c
  src/qu8-vadd/gen/qu8-vadd-minmax-scalar-x1.c
  src/qu8-vadd/gen/qu8-vadd-minmax-scalar-x2.c
  src/qu8-vadd/gen/qu8-vadd-minmax-scalar-x4.c
  src/qu8-vaddc/gen/qu8-vaddc-minmax-scalar-x1.c
  src/qu8-vaddc/gen/qu8-vaddc-minmax-scalar-x2.c
  src/qu8-vaddc/gen/qu8-vaddc-minmax-scalar-x4.c
  src/qu8-vcvt/gen/qu8-vcvt-scalar-x1.c
  src/qu8-vcvt/gen/qu8-vcvt-scalar-x2.c
  src/qu8-vcvt/gen/qu8-vcvt-scalar-x4.c
  src/qu8-vhswish/gen/qu8-vhswish-scalar-x1.c
  src/qu8-vhswish/gen/qu8-vhswish-scalar-x2.c
  src/qu8-vhswish/gen/qu8-vhswish-scalar-x4.c
  src/qu8-vlrelu/gen/qu8-vlrelu-scalar-andxor-x1.c
  src/qu8-vlrelu/gen/qu8-vlrelu-scalar-andxor-x2.c
  src/qu8-vlrelu/gen/qu8-vlrelu-scalar-andxor-x4.c
  src/qu8-vlrelu/gen/qu8-vlrelu-scalar-select-x1.c
  src/qu8-vlrelu/gen/qu8-vlrelu-scalar-select-x2.c
  src/qu8-vlrelu/gen/qu8-vlrelu-scalar-select-x4.c
  src/qu8-vmul/gen/qu8-vmul-minmax-fp32-scalar-x1.c
  src/qu8-vmul/gen/qu8-vmul-minmax-fp32-scalar-x2.c
  src/qu8-vmul/gen/qu8-vmul-minmax-fp32-scalar-x4.c
  src/qu8-vmulc/gen/qu8-vmulc-minmax-fp32-scalar-x1.c
  src/qu8-vmulc/gen/qu8-vmulc-minmax-fp32-scalar-x2.c
  src/qu8-vmulc/gen/qu8-vmulc-minmax-fp32-scalar-x4.c
  src/s8-ibilinear/gen/s8-ibilinear-scalar-c1.c
  src/s8-ibilinear/gen/s8-ibilinear-scalar-c2.c
  src/s8-ibilinear/gen/s8-ibilinear-scalar-c4.c
  src/s8-maxpool/s8-maxpool-9p8x-minmax-scalar-c1.c
  src/s8-vclamp/s8-vclamp-scalar-x4.c
  src/s16-rmaxabs/gen/s16-rmaxabs-scalar-x1.c
  src/s16-rmaxabs/gen/s16-rmaxabs-scalar-x2.c
  src/s16-rmaxabs/gen/s16-rmaxabs-scalar-x3.c
  src/s16-rmaxabs/gen/s16-rmaxabs-scalar-x4.c
  src/s16-window/gen/s16-window-scalar-x1.c
  src/s16-window/gen/s16-window-scalar-x2.c
  src/s16-window/gen/s16-window-scalar-x3.c
  src/s16-window/gen/s16-window-scalar-x4.c
  src/u8-ibilinear/gen/u8-ibilinear-scalar-c1.c
  src/u8-ibilinear/gen/u8-ibilinear-scalar-c2.c
  src/u8-ibilinear/gen/u8-ibilinear-scalar-c4.c
  src/u8-lut32norm/u8-lut32norm-scalar.c
  src/u8-maxpool/u8-maxpool-9p8x-minmax-scalar-c1.c
  src/u8-rmax/u8-rmax-scalar.c
  src/u8-vclamp/u8-vclamp-scalar-x4.c
  src/u32-filterbank-accumulate/gen/u32-filterbank-accumulate-scalar-x1.c
  src/u32-filterbank-subtract/u32-filterbank-subtract-scalar-x2.c
  src/u32-vlog/gen/u32-vlog-scalar-x1.c
  src/u32-vlog/gen/u32-vlog-scalar-x2.c
  src/u32-vlog/gen/u32-vlog-scalar-x3.c
  src/u32-vlog/gen/u32-vlog-scalar-x4.c
  src/u64-u32-vsqrtshift/u64-u32-vsqrtshift-scalar-cvtu32-sqrt-cvtu32f64-x1.c
  src/x8-lut/gen/x8-lut-scalar-x1.c
  src/x8-lut/gen/x8-lut-scalar-x2.c
  src/x8-lut/gen/x8-lut-scalar-x4.c
  src/x8-lut/gen/x8-lut-scalar-x8.c
  src/x8-lut/gen/x8-lut-scalar-x16.c
  src/x8-packw/gen/x8-packw-x2-gemm-goi-scalar-int-x4.c
  src/x8-packw/gen/x8-packw-x4-gemm-goi-scalar-int-x4.c
  src/x8-packw/gen/x8-packw-x8-gemm-goi-scalar-int-x4.c
  src/x8-packw/gen/x8-packw-x16-gemm-goi-scalar-int-x4.c
  src/x8-transposec/gen/x8-transposec-1x2-scalar-int.c
  src/x8-transposec/gen/x8-transposec-1x4-scalar-int.c
  src/x8-transposec/gen/x8-transposec-2x1-scalar-int.c
  src/x8-transposec/gen/x8-transposec-2x2-scalar-int.c
  src/x8-transposec/gen/x8-transposec-2x4-scalar-int.c
  src/x8-transposec/gen/x8-transposec-4x1-scalar-int.c
  src/x8-transposec/gen/x8-transposec-4x2-scalar-int.c
  src/x8-transposec/gen/x8-transposec-4x4-scalar-int.c
  src/x8-zip/x8-zip-x2-scalar.c
  src/x8-zip/x8-zip-x3-scalar.c
  src/x8-zip/x8-zip-x4-scalar.c
  src/x8-zip/x8-zip-xm-scalar.c
  src/x16-packw/gen/x16-packw-x8-gemm-goi-scalar-int-x4.c
  src/x16-packw/gen/x16-packw-x16-gemm-goi-scalar-int-x4.c
  src/x16-transposec/gen/x16-transposec-1x2-scalar-int.c
  src/x16-transposec/gen/x16-transposec-1x4-scalar-int.c
  src/x16-transposec/gen/x16-transposec-2x1-scalar-int.c
  src/x16-transposec/gen/x16-transposec-2x2-scalar-int.c
  src/x16-transposec/gen/x16-transposec-2x4-scalar-int.c
  src/x16-transposec/gen/x16-transposec-4x1-scalar-int.c
  src/x16-transposec/gen/x16-transposec-4x2-scalar-int.c
  src/x16-transposec/gen/x16-transposec-4x4-scalar-int.c
  src/x24-transposec/gen/x24-transposec-1x2-scalar.c
  src/x24-transposec/gen/x24-transposec-1x4-scalar.c
  src/x24-transposec/gen/x24-transposec-2x1-scalar.c
  src/x24-transposec/gen/x24-transposec-2x2-scalar.c
  src/x24-transposec/gen/x24-transposec-2x4-scalar.c
  src/x24-transposec/gen/x24-transposec-4x1-scalar.c
  src/x24-transposec/gen/x24-transposec-4x2-scalar.c
  src/x24-transposec/gen/x24-transposec-4x4-scalar.c
  src/x32-packb/gen/x32-packb-2c1s1r-gemm-scalar-float.c
  src/x32-packb/gen/x32-packb-2c1s1r-gemm-scalar-int.c
  src/x32-packb/gen/x32-packb-2c2s1r-gemm-scalar-float.c
  src/x32-packb/gen/x32-packb-2c2s1r-gemm-scalar-int.c
  src/x32-packb/gen/x32-packb-4c1s1r-gemm-scalar-float.c
  src/x32-packb/gen/x32-packb-4c1s1r-gemm-scalar-int.c
  src/x32-packb/gen/x32-packb-4c4s1r-gemm-scalar-float.c
  src/x32-packb/gen/x32-packb-4c4s1r-gemm-scalar-int.c
  src/x32-packw/gen/x32-packw-x2-gemm-goi-scalar-float-x4.c
  src/x32-packw/gen/x32-packw-x2-gemm-goi-scalar-int-x4.c
  src/x32-packw/gen/x32-packw-x3-gemm-goi-scalar-float-x4.c
  src/x32-packw/gen/x32-packw-x3-gemm-goi-scalar-int-x4.c
  src/x32-packw/gen/x32-packw-x4-gemm-goi-scalar-float-x4.c
  src/x32-packw/gen/x32-packw-x4-gemm-goi-scalar-int-x4.c
  src/x32-packw/gen/x32-packw-x8-gemm-goi-scalar-float-x4.c
  src/x32-packw/gen/x32-packw-x8-gemm-goi-scalar-int-x4.c
  src/x32-packw/gen/x32-packw-x16-gemm-goi-scalar-float-x4.c
  src/x32-packw/gen/x32-packw-x16-gemm-goi-scalar-int-x4.c
  src/x32-packx/x32-packx-2x-scalar.c
  src/x32-packx/x32-packx-3x-scalar.c
  src/x32-packx/x32-packx-4x-scalar.c
  src/x32-transposec/gen/x32-transposec-1x2-scalar-float.c
  src/x32-transposec/gen/x32-transposec-1x2-scalar-int.c
  src/x32-transposec/gen/x32-transposec-1x4-scalar-float.c
  src/x32-transposec/gen/x32-transposec-1x4-scalar-int.c
  src/x32-transposec/gen/x32-transposec-2x1-scalar-float.c
  src/x32-transposec/gen/x32-transposec-2x1-scalar-int.c
  src/x32-transposec/gen/x32-transposec-2x2-scalar-float.c
  src/x32-transposec/gen/x32-transposec-2x2-scalar-int.c
  src/x32-transposec/gen/x32-transposec-2x4-scalar-float.c
  src/x32-transposec/gen/x32-transposec-2x4-scalar-int.c
  src/x32-transposec/gen/x32-transposec-4x1-scalar-float.c
  src/x32-transposec/gen/x32-transposec-4x1-scalar-int.c
  src/x32-transposec/gen/x32-transposec-4x2-scalar-float.c
  src/x32-transposec/gen/x32-transposec-4x2-scalar-int.c
  src/x32-transposec/gen/x32-transposec-4x4-scalar-float.c
  src/x32-transposec/gen/x32-transposec-4x4-scalar-int.c
  src/x32-unpool/x32-unpool-scalar.c
  src/x32-zerob/gen/x32-zerob-2c1s1r-gemm-scalar-float.c
  src/x32-zerob/gen/x32-zerob-2c1s1r-gemm-scalar-int.c
  src/x32-zerob/gen/x32-zerob-2c2s1r-gemm-scalar-float.c
  src/x32-zerob/gen/x32-zerob-2c2s1r-gemm-scalar-int.c
  src/x32-zerob/gen/x32-zerob-4c1s1r-gemm-scalar-float.c
  src/x32-zerob/gen/x32-zerob-4c1s1r-gemm-scalar-int.c
  src/x32-zerob/gen/x32-zerob-4c4s1r-gemm-scalar-float.c
  src/x32-zerob/gen/x32-zerob-4c4s1r-gemm-scalar-int.c
  src/x32-zip/x32-zip-x2-scalar.c
  src/x32-zip/x32-zip-x3-scalar.c
  src/x32-zip/x32-zip-x4-scalar.c
  src/x32-zip/x32-zip-xm-scalar.c
  src/x64-transposec/gen/x64-transposec-1x2-scalar-float.c
  src/x64-transposec/gen/x64-transposec-1x2-scalar-int.c
  src/x64-transposec/gen/x64-transposec-2x1-scalar-float.c
  src/x64-transposec/gen/x64-transposec-2x1-scalar-int.c
  src/x64-transposec/gen/x64-transposec-2x2-scalar-float.c
  src/x64-transposec/gen/x64-transposec-2x2-scalar-int.c
  src/x64-transposec/gen/x64-transposec-4x1-scalar-float.c
  src/x64-transposec/gen/x64-transposec-4x1-scalar-int.c
  src/x64-transposec/gen/x64-transposec-4x2-scalar-float.c
  src/x64-transposec/gen/x64-transposec-4x2-scalar-int.c
  src/xx-copy/xx-copy-scalar-memcpy.c
  src/xx-fill/xx-fill-scalar-x16.c
  src/xx-pad/xx-pad-scalar.c
  src/xx-transposev/xx-transposev-1x1-scalar-memcpy.c)

SET(ALL_SSE_MICROKERNEL_SRCS
  src/f32-avgpool/f32-avgpool-9p8x-minmax-sse-c4.c
  src/f32-avgpool/f32-avgpool-9x-minmax-sse-c4.c
  src/f32-conv-hwc2chw/f32-conv-hwc2chw-3x3s2p1c3x4-sse-1x1.c
  src/f32-conv-hwc2chw/f32-conv-hwc2chw-3x3s2p1c3x4-sse-2x2.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-sse-1x4-acc2.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-sse-1x4-acc3.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-sse-1x4-acc4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-sse-1x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-sse-2x4-acc2.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-sse-2x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-sse-3x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-sse-4x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-sse-5x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-sse-6x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-sse-1x4-acc2.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-sse-1x4-acc3.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-sse-1x4-acc4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-sse-1x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-sse-2x4-acc2.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-sse-2x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-sse-3x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3s2p1-minmax-sse-4x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-sse-1x4-acc2.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-sse-1x4-acc3.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-sse-1x4-acc4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-sse-1x4-acc5.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-sse-1x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-sse-2x4-acc2.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-sse-2x4-acc3.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-sse-2x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-sse-3x4-acc2.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-sse-3x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-sse-4x4-acc2.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-sse-4x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5p2-minmax-sse-5x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-sse-1x4-acc2.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-sse-1x4-acc3.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-sse-1x4-acc4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-sse-1x4-acc5.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-sse-1x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-sse-2x4-acc2.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-sse-2x4-acc3.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-sse-2x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-sse-3x4-acc2.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-5x5s2p2-minmax-sse-3x4.c
  src/f32-dwconv/gen/f32-dwconv-3p4c-minmax-sse-acc2.c
  src/f32-dwconv/gen/f32-dwconv-3p4c-minmax-sse.c
  src/f32-dwconv/gen/f32-dwconv-3p8c-minmax-sse-acc2.c
  src/f32-dwconv/gen/f32-dwconv-3p8c-minmax-sse.c
  src/f32-dwconv/gen/f32-dwconv-4p4c-minmax-sse-acc2.c
  src/f32-dwconv/gen/f32-dwconv-4p4c-minmax-sse.c
  src/f32-dwconv/gen/f32-dwconv-4p8c-minmax-sse-acc2.c
  src/f32-dwconv/gen/f32-dwconv-4p8c-minmax-sse.c
  src/f32-dwconv/gen/f32-dwconv-5f5m5l4c4s4r-minmax-sse-acc2.c
  src/f32-dwconv/gen/f32-dwconv-5f5m5l4c4s4r-minmax-sse.c
  src/f32-dwconv/gen/f32-dwconv-5f5m5l8c4s4r-minmax-sse-acc2.c
  src/f32-dwconv/gen/f32-dwconv-5f5m5l8c4s4r-minmax-sse.c
  src/f32-dwconv/gen/f32-dwconv-5f5m5l16c4s4r-minmax-sse-acc2.c
  src/f32-dwconv/gen/f32-dwconv-5f5m5l16c4s4r-minmax-sse.c
  src/f32-dwconv/gen/f32-dwconv-6f6m7l4c4s4r-minmax-sse-acc2.c
  src/f32-dwconv/gen/f32-dwconv-6f6m7l4c4s4r-minmax-sse.c
  src/f32-dwconv/gen/f32-dwconv-6f6m7l8c4s4r-minmax-sse-acc2.c
  src/f32-dwconv/gen/f32-dwconv-6f6m7l8c4s4r-minmax-sse.c
  src/f32-dwconv/gen/f32-dwconv-6f6m7l16c4s4r-minmax-sse-acc2.c
  src/f32-dwconv/gen/f32-dwconv-6f6m7l16c4s4r-minmax-sse.c
  src/f32-dwconv/gen/f32-dwconv-8f8m9l4c4s4r-minmax-sse-acc2.c
  src/f32-dwconv/gen/f32-dwconv-8f8m9l4c4s4r-minmax-sse.c
  src/f32-dwconv/gen/f32-dwconv-8f8m9l8c4s4r-minmax-sse-acc2.c
  src/f32-dwconv/gen/f32-dwconv-8f8m9l8c4s4r-minmax-sse.c
  src/f32-dwconv/gen/f32-dwconv-8f8m9l16c4s4r-minmax-sse-acc2.c
  src/f32-dwconv/gen/f32-dwconv-8f8m9l16c4s4r-minmax-sse.c
  src/f32-dwconv/gen/f32-dwconv-9p4c-minmax-sse-acc2.c
  src/f32-dwconv/gen/f32-dwconv-9p4c-minmax-sse.c
  src/f32-dwconv/gen/f32-dwconv-9p8c-minmax-sse-acc2.c
  src/f32-dwconv/gen/f32-dwconv-9p8c-minmax-sse.c
  src/f32-dwconv/gen/f32-dwconv-25p4c-minmax-sse-acc2.c
  src/f32-dwconv/gen/f32-dwconv-25p4c-minmax-sse.c
  src/f32-dwconv/gen/f32-dwconv-25p8c-minmax-sse-acc2.c
  src/f32-dwconv/gen/f32-dwconv-25p8c-minmax-sse.c
  src/f32-gavgpool-cw/f32-gavgpool-cw-sse-x4.c
  src/f32-gavgpool/f32-gavgpool-7p7x-minmax-sse-c4.c
  src/f32-gavgpool/f32-gavgpool-7x-minmax-sse-c4.c
  src/f32-gemm/gen/f32-gemm-1x8-minmax-sse-dup.c
  src/f32-gemm/gen/f32-gemm-1x8-minmax-sse-load1.c
  src/f32-gemm/gen/f32-gemm-1x8s4-minmax-sse.c
  src/f32-gemm/gen/f32-gemm-3x8-minmax-sse-dup.c
  src/f32-gemm/gen/f32-gemm-3x8-minmax-sse-load1.c
  src/f32-gemm/gen/f32-gemm-3x8s4-minmax-sse.c
  src/f32-gemm/gen/f32-gemm-4x2c4-minmax-sse.c
  src/f32-gemm/gen/f32-gemm-4x8-minmax-sse-dup.c
  src/f32-gemm/gen/f32-gemm-4x8-minmax-sse-load1.c
  src/f32-gemm/gen/f32-gemm-4x8s4-minmax-sse.c
  src/f32-gemm/gen/f32-gemm-5x8-minmax-sse-dup.c
  src/f32-gemm/gen/f32-gemm-5x8-minmax-sse-load1.c
  src/f32-gemm/gen/f32-gemm-5x8s4-minmax-sse.c
  src/f32-gemm/gen/f32-gemm-6x2c4-minmax-sse.c
  src/f32-gemm/gen/f32-gemm-6x8-minmax-sse-dup.c
  src/f32-gemm/gen/f32-gemm-6x8-minmax-sse-load1.c
  src/f32-gemm/gen/f32-gemm-6x8s4-minmax-sse.c
  src/f32-gemminc/gen/f32-gemminc-1x8-minmax-sse-dup.c
  src/f32-gemminc/gen/f32-gemminc-1x8-minmax-sse-load1.c
  src/f32-gemminc/gen/f32-gemminc-1x8s4-minmax-sse.c
  src/f32-gemminc/gen/f32-gemminc-3x8-minmax-sse-dup.c
  src/f32-gemminc/gen/f32-gemminc-3x8-minmax-sse-load1.c
  src/f32-gemminc/gen/f32-gemminc-3x8s4-minmax-sse.c
  src/f32-gemminc/gen/f32-gemminc-4x8-minmax-sse-dup.c
  src/f32-gemminc/gen/f32-gemminc-4x8-minmax-sse-load1.c
  src/f32-gemminc/gen/f32-gemminc-4x8s4-minmax-sse.c
  src/f32-gemminc/gen/f32-gemminc-5x8-minmax-sse-dup.c
  src/f32-gemminc/gen/f32-gemminc-5x8-minmax-sse-load1.c
  src/f32-gemminc/gen/f32-gemminc-5x8s4-minmax-sse.c
  src/f32-gemminc/gen/f32-gemminc-6x8-minmax-sse-dup.c
  src/f32-gemminc/gen/f32-gemminc-6x8-minmax-sse-load1.c
  src/f32-gemminc/gen/f32-gemminc-6x8s4-minmax-sse.c
  src/f32-ibilinear-chw/gen/f32-ibilinear-chw-sse-p4.c
  src/f32-ibilinear-chw/gen/f32-ibilinear-chw-sse-p8.c
  src/f32-ibilinear/gen/f32-ibilinear-sse-c4.c
  src/f32-ibilinear/gen/f32-ibilinear-sse-c8.c
  src/f32-igemm/gen/f32-igemm-1x8-minmax-sse-dup.c
  src/f32-igemm/gen/f32-igemm-1x8-minmax-sse-load1.c
  src/f32-igemm/gen/f32-igemm-1x8s4-minmax-sse.c
  src/f32-igemm/gen/f32-igemm-3x8-minmax-sse-dup.c
  src/f32-igemm/gen/f32-igemm-3x8-minmax-sse-load1.c
  src/f32-igemm/gen/f32-igemm-3x8s4-minmax-sse.c
  src/f32-igemm/gen/f32-igemm-4x2c4-minmax-sse.c
  src/f32-igemm/gen/f32-igemm-4x8-minmax-sse-dup.c
  src/f32-igemm/gen/f32-igemm-4x8-minmax-sse-load1.c
  src/f32-igemm/gen/f32-igemm-4x8s4-minmax-sse.c
  src/f32-igemm/gen/f32-igemm-5x8-minmax-sse-dup.c
  src/f32-igemm/gen/f32-igemm-5x8-minmax-sse-load1.c
  src/f32-igemm/gen/f32-igemm-5x8s4-minmax-sse.c
  src/f32-igemm/gen/f32-igemm-6x2c4-minmax-sse.c
  src/f32-igemm/gen/f32-igemm-6x8-minmax-sse-dup.c
  src/f32-igemm/gen/f32-igemm-6x8-minmax-sse-load1.c
  src/f32-igemm/gen/f32-igemm-6x8s4-minmax-sse.c
  src/f32-maxpool/f32-maxpool-9p8x-minmax-sse-c4.c
  src/f32-pavgpool/f32-pavgpool-9p8x-minmax-sse-c4.c
  src/f32-pavgpool/f32-pavgpool-9x-minmax-sse-c4.c
  src/f32-ppmm/gen/f32-ppmm-4x8-minmax-sse.c
  src/f32-prelu/gen/f32-prelu-sse-2x4.c
  src/f32-prelu/gen/f32-prelu-sse-2x8.c
  src/f32-rmax/f32-rmax-sse.c
  src/f32-rminmax/gen/f32-rmax-sse-x4.c
  src/f32-rminmax/gen/f32-rmax-sse-x8-acc2.c
  src/f32-rminmax/gen/f32-rmax-sse-x12-acc3.c
  src/f32-rminmax/gen/f32-rmax-sse-x16-acc2.c
  src/f32-rminmax/gen/f32-rmax-sse-x16-acc4.c
  src/f32-rminmax/gen/f32-rmin-sse-x4.c
  src/f32-rminmax/gen/f32-rmin-sse-x8-acc2.c
  src/f32-rminmax/gen/f32-rmin-sse-x12-acc3.c
  src/f32-rminmax/gen/f32-rmin-sse-x16-acc2.c
  src/f32-rminmax/gen/f32-rmin-sse-x16-acc4.c
  src/f32-rminmax/gen/f32-rminmax-sse-x4.c
  src/f32-rminmax/gen/f32-rminmax-sse-x8-acc2.c
  src/f32-rminmax/gen/f32-rminmax-sse-x12-acc3.c
  src/f32-rminmax/gen/f32-rminmax-sse-x16-acc2.c
  src/f32-rminmax/gen/f32-rminmax-sse-x16-acc4.c
  src/f32-rsum/gen/f32-rsum-sse-x4.c
  src/f32-rsum/gen/f32-rsum-sse-x8-acc2.c
  src/f32-rsum/gen/f32-rsum-sse-x12-acc3.c
  src/f32-rsum/gen/f32-rsum-sse-x16-acc2.c
  src/f32-rsum/gen/f32-rsum-sse-x16-acc4.c
  src/f32-spmm/gen/f32-spmm-4x1-minmax-sse.c
  src/f32-spmm/gen/f32-spmm-8x1-minmax-sse.c
  src/f32-spmm/gen/f32-spmm-16x1-minmax-sse.c
  src/f32-spmm/gen/f32-spmm-32x1-minmax-sse.c
  src/f32-vbinary/gen/f32-vadd-minmax-sse-x4.c
  src/f32-vbinary/gen/f32-vadd-minmax-sse-x8.c
  src/f32-vbinary/gen/f32-vaddc-minmax-sse-x4.c
  src/f32-vbinary/gen/f32-vaddc-minmax-sse-x8.c
  src/f32-vbinary/gen/f32-vdiv-minmax-sse-x4.c
  src/f32-vbinary/gen/f32-vdiv-minmax-sse-x8.c
  src/f32-vbinary/gen/f32-vdivc-minmax-sse-x4.c
  src/f32-vbinary/gen/f32-vdivc-minmax-sse-x8.c
  src/f32-vbinary/gen/f32-vmax-sse-x4.c
  src/f32-vbinary/gen/f32-vmax-sse-x8.c
  src/f32-vbinary/gen/f32-vmaxc-sse-x4.c
  src/f32-vbinary/gen/f32-vmaxc-sse-x8.c
  src/f32-vbinary/gen/f32-vmin-sse-x4.c
  src/f32-vbinary/gen/f32-vmin-sse-x8.c
  src/f32-vbinary/gen/f32-vminc-sse-x4.c
  src/f32-vbinary/gen/f32-vminc-sse-x8.c
  src/f32-vbinary/gen/f32-vmul-minmax-sse-x4.c
  src/f32-vbinary/gen/f32-vmul-minmax-sse-x8.c
  src/f32-vbinary/gen/f32-vmulc-minmax-sse-x4.c
  src/f32-vbinary/gen/f32-vmulc-minmax-sse-x8.c
  src/f32-vbinary/gen/f32-vrdivc-minmax-sse-x4.c
  src/f32-vbinary/gen/f32-vrdivc-minmax-sse-x8.c
  src/f32-vbinary/gen/f32-vrsubc-minmax-sse-x4.c
  src/f32-vbinary/gen/f32-vrsubc-minmax-sse-x8.c
  src/f32-vbinary/gen/f32-vsqrdiff-sse-x4.c
  src/f32-vbinary/gen/f32-vsqrdiff-sse-x8.c
  src/f32-vbinary/gen/f32-vsqrdiffc-sse-x4.c
  src/f32-vbinary/gen/f32-vsqrdiffc-sse-x8.c
  src/f32-vbinary/gen/f32-vsub-minmax-sse-x4.c
  src/f32-vbinary/gen/f32-vsub-minmax-sse-x8.c
  src/f32-vbinary/gen/f32-vsubc-minmax-sse-x4.c
  src/f32-vbinary/gen/f32-vsubc-minmax-sse-x8.c
  src/f32-vclamp/gen/f32-vclamp-sse-x4.c
  src/f32-vclamp/gen/f32-vclamp-sse-x8.c
  src/f32-vcmul/gen/f32-vcmul-sse-x4.c
  src/f32-vcmul/gen/f32-vcmul-sse-x8.c
  src/f32-vcmul/gen/f32-vcmul-sse-x12.c
  src/f32-vcmul/gen/f32-vcmul-sse-x16.c
  src/f32-vhswish/gen/f32-vhswish-sse-x4.c
  src/f32-vhswish/gen/f32-vhswish-sse-x8.c
  src/f32-vlrelu/gen/f32-vlrelu-sse-x4.c
  src/f32-vlrelu/gen/f32-vlrelu-sse-x8.c
  src/f32-vmulcaddc/gen/f32-vmulcaddc-c4-minmax-sse-2x.c
  src/f32-vmulcaddc/gen/f32-vmulcaddc-c8-minmax-sse-2x.c
  src/f32-vrelu/gen/f32-vrelu-sse-x4.c
  src/f32-vrelu/gen/f32-vrelu-sse-x8.c
  src/f32-vsqrt/gen/f32-vsqrt-sse-sqrt-x4.c
  src/f32-vsqrt/gen/f32-vsqrt-sse-sqrt-x8.c
  src/f32-vunary/gen/f32-vabs-sse-x4.c
  src/f32-vunary/gen/f32-vabs-sse-x8.c
  src/f32-vunary/gen/f32-vneg-sse-x4.c
  src/f32-vunary/gen/f32-vneg-sse-x8.c
  src/f32-vunary/gen/f32-vsqr-sse-x4.c
  src/f32-vunary/gen/f32-vsqr-sse-x8.c
  src/math/f32-roundd-sse-addsub.c
  src/math/f32-roundne-sse-addsub.c
  src/math/f32-roundu-sse-addsub.c
  src/math/f32-roundz-sse-addsub.c
  src/math/f32-sqrt-sse-hh1mac.c
  src/math/f32-sqrt-sse-nr1mac.c
  src/math/f32-sqrt-sse-nr2mac.c
  src/x32-packx/x32-packx-4x-sse.c
  src/x32-transposec/x32-transposec-4x4-sse.c)

SET(ALL_SSE2_MICROKERNEL_SRCS
  src/f16-f32-vcvt/gen/f16-f32-vcvt-sse2-int16-x8.c
  src/f16-f32-vcvt/gen/f16-f32-vcvt-sse2-int16-x16.c
  src/f16-f32-vcvt/gen/f16-f32-vcvt-sse2-int16-x24.c
  src/f16-f32-vcvt/gen/f16-f32-vcvt-sse2-int16-x32.c
  src/f16-f32-vcvt/gen/f16-f32-vcvt-sse2-int32-x8.c
  src/f16-f32-vcvt/gen/f16-f32-vcvt-sse2-int32-x16.c
  src/f16-f32-vcvt/gen/f16-f32-vcvt-sse2-int32-x24.c
  src/f16-f32-vcvt/gen/f16-f32-vcvt-sse2-int32-x32.c
  src/f16-vunary/gen/f16-vabs-sse2-x8.c
  src/f16-vunary/gen/f16-vabs-sse2-x16.c
  src/f16-vunary/gen/f16-vneg-sse2-x8.c
  src/f16-vunary/gen/f16-vneg-sse2-x16.c
  src/f32-argmaxpool/f32-argmaxpool-4x-sse2-c4.c
  src/f32-argmaxpool/f32-argmaxpool-9p8x-sse2-c4.c
  src/f32-argmaxpool/f32-argmaxpool-9x-sse2-c4.c
  src/f32-f16-vcvt/gen/f32-f16-vcvt-sse2-x8.c
  src/f32-f16-vcvt/gen/f32-f16-vcvt-sse2-x16.c
  src/f32-f16-vcvt/gen/f32-f16-vcvt-sse2-x24.c
  src/f32-f16-vcvt/gen/f32-f16-vcvt-sse2-x32.c
  src/f32-gemm/gen/f32-gemm-1x8-minmax-sse2-dup.c
  src/f32-gemm/gen/f32-gemm-3x8-minmax-sse2-dup.c
  src/f32-gemm/gen/f32-gemm-4x8-minmax-sse2-dup.c
  src/f32-gemm/gen/f32-gemm-5x8-minmax-sse2-dup.c
  src/f32-gemm/gen/f32-gemm-6x8-minmax-sse2-dup.c
  src/f32-gemminc/gen/f32-gemminc-1x8-minmax-sse2-dup.c
  src/f32-gemminc/gen/f32-gemminc-3x8-minmax-sse2-dup.c
  src/f32-gemminc/gen/f32-gemminc-4x8-minmax-sse2-dup.c
  src/f32-gemminc/gen/f32-gemminc-5x8-minmax-sse2-dup.c
  src/f32-gemminc/gen/f32-gemminc-6x8-minmax-sse2-dup.c
  src/f32-igemm/gen/f32-igemm-1x8-minmax-sse2-dup.c
  src/f32-igemm/gen/f32-igemm-3x8-minmax-sse2-dup.c
  src/f32-igemm/gen/f32-igemm-4x8-minmax-sse2-dup.c
  src/f32-igemm/gen/f32-igemm-5x8-minmax-sse2-dup.c
  src/f32-igemm/gen/f32-igemm-6x8-minmax-sse2-dup.c
  src/f32-prelu/gen/f32-prelu-sse2-2x4.c
  src/f32-prelu/gen/f32-prelu-sse2-2x8.c
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  src/x32-packw/gen/x32-packw-x8-gemm-goi-sse2-x4-prfm.c
  src/x32-packw/gen/x32-packw-x8-gemm-goi-sse2-x4.c
  src/x32-packw/gen/x32-packw-x8-gemm-goi-sse2-x8-prfm.c
  src/x32-packw/gen/x32-packw-x8-gemm-goi-sse2-x8.c
  src/x32-packw/gen/x32-packw-x8s4-gemm-goi-sse2-x4-prfm.c
  src/x32-packw/gen/x32-packw-x8s4-gemm-goi-sse2-x4.c
  src/x32-packw/gen/x32-packw-x8s4-gemm-goi-sse2-x8-prfm.c
  src/x32-packw/gen/x32-packw-x8s4-gemm-goi-sse2-x8.c
  src/x32-packw/gen/x32-packw-x16-gemm-goi-sse2-x4-prfm.c
  src/x32-packw/gen/x32-packw-x16-gemm-goi-sse2-x4.c
  src/x32-packw/gen/x32-packw-x16-gemm-goi-sse2-x8-prfm.c
  src/x32-packw/gen/x32-packw-x16-gemm-goi-sse2-x8.c
  src/x32-packw/gen/x32-packw-x16s4-gemm-goi-sse2-x4-prfm.c
  src/x32-packw/gen/x32-packw-x16s4-gemm-goi-sse2-x4.c
  src/x32-packw/gen/x32-packw-x16s4-gemm-goi-sse2-x8-prfm.c
  src/x32-packw/gen/x32-packw-x16s4-gemm-goi-sse2-x8.c
  src/x32-transposec/gen/x32-transposec-4x4-multi-mov-sse2.c
  src/x32-transposec/gen/x32-transposec-4x4-multi-multi-sse2.c
  src/x32-transposec/gen/x32-transposec-4x4-multi-switch-sse2.c
  src/x32-transposec/gen/x32-transposec-4x4-reuse-mov-sse2.c
  src/x32-transposec/gen/x32-transposec-4x4-reuse-multi-sse2.c
  src/x32-transposec/gen/x32-transposec-4x4-reuse-switch-sse2.c
  src/x32-unpool/x32-unpool-sse2.c
  src/x32-zip/x32-zip-x2-sse2.c
  src/x32-zip/x32-zip-x3-sse2.c
  src/x32-zip/x32-zip-x4-sse2.c
  src/x32-zip/x32-zip-xm-sse2.c
  src/x64-transposec/gen/x64-transposec-2x2-multi-mov-sse2.c
  src/x64-transposec/gen/x64-transposec-2x2-multi-multi-sse2.c
  src/x64-transposec/gen/x64-transposec-2x2-multi-switch-sse2.c
  src/x64-transposec/gen/x64-transposec-2x2-reuse-mov-sse2.c
  src/x64-transposec/gen/x64-transposec-2x2-reuse-multi-sse2.c
  src/x64-transposec/gen/x64-transposec-2x2-reuse-switch-sse2.c
  src/xx-fill/xx-fill-sse2-x64.c
  src/xx-pad/xx-pad-sse2.c)

SET(ALL_SSE41_MICROKERNEL_SRCS
  src/f16-f32-vcvt/gen/f16-f32-vcvt-sse41-int16-x8.c
  src/f16-f32-vcvt/gen/f16-f32-vcvt-sse41-int16-x16.c
  src/f16-f32-vcvt/gen/f16-f32-vcvt-sse41-int16-x24.c
  src/f16-f32-vcvt/gen/f16-f32-vcvt-sse41-int16-x32.c
  src/f16-f32-vcvt/gen/f16-f32-vcvt-sse41-int32-x8.c
  src/f16-f32-vcvt/gen/f16-f32-vcvt-sse41-int32-x16.c
  src/f16-f32-vcvt/gen/f16-f32-vcvt-sse41-int32-x24.c
  src/f16-f32-vcvt/gen/f16-f32-vcvt-sse41-int32-x32.c
  src/f32-f16-vcvt/gen/f32-f16-vcvt-sse41-x8.c
  src/f32-f16-vcvt/gen/f32-f16-vcvt-sse41-x16.c
  src/f32-f16-vcvt/gen/f32-f16-vcvt-sse41-x24.c
  src/f32-f16-vcvt/gen/f32-f16-vcvt-sse41-x32.c
  src/f32-prelu/gen/f32-prelu-sse41-2x4.c
  src/f32-prelu/gen/f32-prelu-sse41-2x8.c
  src/f32-qc4w-gemm/gen/f32-qc4w-gemm-1x8-minmax-sse41-dup.c
  src/f32-qc4w-gemm/gen/f32-qc4w-gemm-3x8-minmax-sse41-dup.c
  src/f32-qc4w-gemm/gen/f32-qc4w-gemm-4x8-minmax-sse41-dup.c
  src/f32-qc4w-gemm/gen/f32-qc4w-gemm-5x8-minmax-sse41-dup.c
  src/f32-qc4w-gemm/gen/f32-qc4w-gemm-6x8-minmax-sse41-dup.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-sse41-dup.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-sse41-load1.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8s4-minmax-sse41.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8-minmax-sse41-dup.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8-minmax-sse41-load1.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8s4-minmax-sse41.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x2c4-minmax-sse41.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-minmax-sse41-dup.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-minmax-sse41-load1.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8s4-minmax-sse41.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-minmax-sse41-dup.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-minmax-sse41-load1.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8s4-minmax-sse41.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x2c4-minmax-sse41.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-minmax-sse41-dup.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-minmax-sse41-load1.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8s4-minmax-sse41.c
  src/f32-qs8-vcvt/gen/f32-qs8-vcvt-sse41-x8.c
  src/f32-qs8-vcvt/gen/f32-qs8-vcvt-sse41-x16.c
  src/f32-qs8-vcvt/gen/f32-qs8-vcvt-sse41-x24.c
  src/f32-qs8-vcvt/gen/f32-qs8-vcvt-sse41-x32.c
  src/f32-velu/gen/f32-velu-sse41-rr2-lut16-p3-x4.c
  src/f32-velu/gen/f32-velu-sse41-rr2-lut16-p3-x8.c
  src/f32-velu/gen/f32-velu-sse41-rr2-lut16-p3-x12.c
  src/f32-velu/gen/f32-velu-sse41-rr2-lut16-p3-x16.c
  src/f32-velu/gen/f32-velu-sse41-rr2-lut16-p3-x20.c
  src/f32-velu/gen/f32-velu-sse41-rr2-lut16-p3-x24.c
  src/f32-velu/gen/f32-velu-sse41-rr2-p6-x4.c
  src/f32-velu/gen/f32-velu-sse41-rr2-p6-x8.c
  src/f32-velu/gen/f32-velu-sse41-rr2-p6-x12.c
  src/f32-velu/gen/f32-velu-sse41-rr2-p6-x16.c
  src/f32-velu/gen/f32-velu-sse41-rr2-p6-x20.c
  src/f32-velu/gen/f32-velu-sse41-rr2-p6-x24.c
  src/f32-vlrelu/gen/f32-vlrelu-sse41-x4.c
  src/f32-vlrelu/gen/f32-vlrelu-sse41-x8.c
  src/f32-vrnd/gen/f32-vrndd-sse41-x4.c
  src/f32-vrnd/gen/f32-vrndd-sse41-x8.c
  src/f32-vrnd/gen/f32-vrndne-sse41-x4.c
  src/f32-vrnd/gen/f32-vrndne-sse41-x8.c
  src/f32-vrnd/gen/f32-vrndu-sse41-x4.c
  src/f32-vrnd/gen/f32-vrndu-sse41-x8.c
  src/f32-vrnd/gen/f32-vrndz-sse41-x4.c
  src/f32-vrnd/gen/f32-vrndz-sse41-x8.c
  src/f32-vsigmoid/gen/f32-vsigmoid-sse41-rr2-lut64-p2-div-x4.c
  src/f32-vsigmoid/gen/f32-vsigmoid-sse41-rr2-lut64-p2-div-x8.c
  src/f32-vsigmoid/gen/f32-vsigmoid-sse41-rr2-lut64-p2-div-x12.c
  src/f32-vsigmoid/gen/f32-vsigmoid-sse41-rr2-lut64-p2-div-x16.c
  src/f32-vsigmoid/gen/f32-vsigmoid-sse41-rr2-lut64-p2-div-x20.c
  src/f32-vsigmoid/gen/f32-vsigmoid-sse41-rr2-lut64-p2-div-x24.c
  src/f32-vsigmoid/gen/f32-vsigmoid-sse41-rr2-p5-div-x4.c
  src/f32-vsigmoid/gen/f32-vsigmoid-sse41-rr2-p5-div-x8.c
  src/f32-vsigmoid/gen/f32-vsigmoid-sse41-rr2-p5-div-x12.c
  src/f32-vsigmoid/gen/f32-vsigmoid-sse41-rr2-p5-div-x16.c
  src/f32-vsigmoid/gen/f32-vsigmoid-sse41-rr2-p5-div-x20.c
  src/f32-vsigmoid/gen/f32-vsigmoid-sse41-rr2-p5-div-x24.c
  src/f32-vtanh/gen/f32-vtanh-sse41-expm1minus-rr1-lut8-p4h3ts-div-x4.c
  src/f32-vtanh/gen/f32-vtanh-sse41-expm1minus-rr1-lut8-p4h3ts-div-x8.c
  src/f32-vtanh/gen/f32-vtanh-sse41-expm1minus-rr1-lut8-p4h3ts-div-x12.c
  src/f32-vtanh/gen/f32-vtanh-sse41-expm1minus-rr1-lut8-p4h3ts-div-x16.c
  src/f32-vtanh/gen/f32-vtanh-sse41-expm1minus-rr1-lut8-p4h3ts-div-x20.c
  src/f32-vtanh/gen/f32-vtanh-sse41-expm1minus-rr1-lut8-p4h3ts-div-x24.c
  src/f32-vtanh/gen/f32-vtanh-sse41-expm1minus-rr1-p6h5ts-div-x4.c
  src/f32-vtanh/gen/f32-vtanh-sse41-expm1minus-rr1-p6h5ts-div-x8.c
  src/f32-vtanh/gen/f32-vtanh-sse41-expm1minus-rr1-p6h5ts-div-x12.c
  src/f32-vtanh/gen/f32-vtanh-sse41-expm1minus-rr1-p6h5ts-div-x16.c
  src/f32-vtanh/gen/f32-vtanh-sse41-expm1minus-rr1-p6h5ts-div-x20.c
  src/f32-vtanh/gen/f32-vtanh-sse41-expm1minus-rr1-p6h5ts-div-x24.c
  src/f32-vtanh/gen/f32-vtanh-sse41-expm1minus-rr1-p6h5ts-nr1-x4.c
  src/f32-vtanh/gen/f32-vtanh-sse41-expm1minus-rr1-p6h5ts-nr1-x8.c
  src/f32-vtanh/gen/f32-vtanh-sse41-expm1minus-rr1-p6h5ts-nr1-x12.c
  src/f32-vtanh/gen/f32-vtanh-sse41-expm1minus-rr1-p6h5ts-nr1-x16.c
  src/f32-vtanh/gen/f32-vtanh-sse41-expm1minus-rr1-p6h5ts-nr1-x20.c
  src/f32-vtanh/gen/f32-vtanh-sse41-expm1minus-rr1-p6h5ts-nr1-x24.c
  src/f32-vtanh/gen/f32-vtanh-sse41-expm1minus-rr1-p6h5ts-nr2-x4.c
  src/f32-vtanh/gen/f32-vtanh-sse41-expm1minus-rr1-p6h5ts-nr2-x8.c
  src/f32-vtanh/gen/f32-vtanh-sse41-expm1minus-rr1-p6h5ts-nr2-x12.c
  src/f32-vtanh/gen/f32-vtanh-sse41-expm1minus-rr1-p6h5ts-nr2-x16.c
  src/f32-vtanh/gen/f32-vtanh-sse41-expm1minus-rr1-p6h5ts-nr2-x20.c
  src/f32-vtanh/gen/f32-vtanh-sse41-expm1minus-rr1-p6h5ts-nr2-x24.c
  src/math/f16-f32-cvt-sse41-int16.c
  src/math/f16-f32-cvt-sse41-int32.c
  src/math/f32-f16-cvt-sse41.c
  src/math/f32-roundd-sse41.c
  src/math/f32-roundne-sse41.c
  src/math/f32-roundu-sse41.c
  src/math/f32-roundz-sse41.c
  src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x4c8-minmax-sse41-ld64.c
  src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x4c8-minmax-sse41-ld128.c
  src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x4c8-minmax-sse41-ld64.c
  src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x4c8-minmax-sse41-ld128.c
  src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-3x4c8-minmax-sse41-ld64.c
  src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-3x4c8-minmax-sse41-ld128.c
  src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-4x4c8-minmax-sse41-ld64.c
  src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-4x4c8-minmax-sse41-ld128.c
  src/qs8-dwconv/gen/qs8-dwconv-5f5m5l8c4s4r-minmax-fp32-sse41-mul32.c
  src/qs8-dwconv/gen/qs8-dwconv-5f5m5l8c8s8r-minmax-fp32-sse41-mul16-add16.c
  src/qs8-dwconv/gen/qs8-dwconv-5f5m5l8c8s8r-minmax-fp32-sse41-mul16.c
  src/qs8-dwconv/gen/qs8-dwconv-5f5m5l16c4s4r-minmax-fp32-sse41-mul32.c
  src/qs8-dwconv/gen/qs8-dwconv-5f5m5l16c8s8r-minmax-fp32-sse41-mul16-add16.c
  src/qs8-dwconv/gen/qs8-dwconv-5f5m5l16c8s8r-minmax-fp32-sse41-mul16.c
  src/qs8-dwconv/gen/qs8-dwconv-6f6m7l8c4s4r-minmax-fp32-sse41-mul32.c
  src/qs8-dwconv/gen/qs8-dwconv-6f6m7l8c8s8r-minmax-fp32-sse41-mul16-add16.c
  src/qs8-dwconv/gen/qs8-dwconv-6f6m7l8c8s8r-minmax-fp32-sse41-mul16.c
  src/qs8-dwconv/gen/qs8-dwconv-6f6m7l16c4s4r-minmax-fp32-sse41-mul32.c
  src/qs8-dwconv/gen/qs8-dwconv-6f6m7l16c8s8r-minmax-fp32-sse41-mul16-add16.c
  src/qs8-dwconv/gen/qs8-dwconv-6f6m7l16c8s8r-minmax-fp32-sse41-mul16.c
  src/qs8-dwconv/gen/qs8-dwconv-8f8m9l8c4s4r-minmax-fp32-sse41-mul32.c
  src/qs8-dwconv/gen/qs8-dwconv-8f8m9l8c8s8r-minmax-fp32-sse41-mul16-add16.c
  src/qs8-dwconv/gen/qs8-dwconv-8f8m9l8c8s8r-minmax-fp32-sse41-mul16.c
  src/qs8-dwconv/gen/qs8-dwconv-8f8m9l16c4s4r-minmax-fp32-sse41-mul32.c
  src/qs8-dwconv/gen/qs8-dwconv-8f8m9l16c8s8r-minmax-fp32-sse41-mul16-add16.c
  src/qs8-dwconv/gen/qs8-dwconv-8f8m9l16c8s8r-minmax-fp32-sse41-mul16.c
  src/qs8-dwconv/gen/qs8-dwconv-9p8c-minmax-fp32-sse41-mul16-add16.c
  src/qs8-dwconv/gen/qs8-dwconv-9p8c-minmax-fp32-sse41-mul16.c
  src/qs8-dwconv/gen/qs8-dwconv-9p8c-minmax-fp32-sse41-mul32.c
  src/qs8-dwconv/gen/qs8-dwconv-9p16c-minmax-fp32-sse41-mul16-add16.c
  src/qs8-dwconv/gen/qs8-dwconv-9p16c-minmax-fp32-sse41-mul16.c
  src/qs8-dwconv/gen/qs8-dwconv-9p16c-minmax-fp32-sse41-mul32.c
  src/qs8-dwconv/gen/qs8-dwconv-25p8c-minmax-fp32-sse41-mul16-add16.c
  src/qs8-dwconv/gen/qs8-dwconv-25p8c-minmax-fp32-sse41-mul16.c
  src/qs8-dwconv/gen/qs8-dwconv-25p8c-minmax-fp32-sse41-mul32.c
  src/qs8-dwconv/gen/qs8-dwconv-25p16c-minmax-fp32-sse41-mul16-add16.c
  src/qs8-dwconv/gen/qs8-dwconv-25p16c-minmax-fp32-sse41-mul16.c
  src/qs8-dwconv/gen/qs8-dwconv-25p16c-minmax-fp32-sse41-mul32.c
  src/qs8-f32-vcvt/gen/qs8-f32-vcvt-sse41-x8.c
  src/qs8-f32-vcvt/gen/qs8-f32-vcvt-sse41-x16.c
  src/qs8-f32-vcvt/gen/qs8-f32-vcvt-sse41-x24.c
  src/qs8-f32-vcvt/gen/qs8-f32-vcvt-sse41-x32.c
  src/qs8-gavgpool/gen/qs8-gavgpool-7p7x-minmax-fp32-sse41-c8.c
  src/qs8-gavgpool/gen/qs8-gavgpool-7p7x-minmax-fp32-sse41-c16.c
  src/qs8-gavgpool/gen/qs8-gavgpool-7p7x-minmax-fp32-sse41-c24.c
  src/qs8-gavgpool/gen/qs8-gavgpool-7x-minmax-fp32-sse41-c8.c
  src/qs8-gavgpool/gen/qs8-gavgpool-7x-minmax-fp32-sse41-c16.c
  src/qs8-gavgpool/gen/qs8-gavgpool-7x-minmax-fp32-sse41-c24.c
  src/qs8-gemm/gen/qs8-gemm-1x4c2-minmax-fp32-sse41-ld64.c
  src/qs8-gemm/gen/qs8-gemm-1x4c2-minmax-fp32-sse41-ld128.c
  src/qs8-gemm/gen/qs8-gemm-1x4c2-xw-minmax-fp32-sse41.c
  src/qs8-gemm/gen/qs8-gemm-1x4c2s4-minmax-fp32-sse41-ld64.c
  src/qs8-gemm/gen/qs8-gemm-1x4c2s4-minmax-fp32-sse41-ld128.c
  src/qs8-gemm/gen/qs8-gemm-1x4c2s4-xw-minmax-fp32-sse41.c
  src/qs8-gemm/gen/qs8-gemm-1x4c8-minmax-fp32-sse41-ld64.c
  src/qs8-gemm/gen/qs8-gemm-1x4c8-minmax-fp32-sse41-ld128.c
  src/qs8-gemm/gen/qs8-gemm-1x4c8-xw-minmax-fp32-sse41.c
  src/qs8-gemm/gen/qs8-gemm-2x4c2-minmax-fp32-sse41-ld64.c
  src/qs8-gemm/gen/qs8-gemm-2x4c2-minmax-fp32-sse41-ld128.c
  src/qs8-gemm/gen/qs8-gemm-2x4c2-xw-minmax-fp32-sse41.c
  src/qs8-gemm/gen/qs8-gemm-2x4c2s4-minmax-fp32-sse41-ld64.c
  src/qs8-gemm/gen/qs8-gemm-2x4c2s4-minmax-fp32-sse41-ld128.c
  src/qs8-gemm/gen/qs8-gemm-2x4c2s4-xw-minmax-fp32-sse41.c
  src/qs8-gemm/gen/qs8-gemm-2x4c8-minmax-fp32-sse41-ld64.c
  src/qs8-gemm/gen/qs8-gemm-2x4c8-minmax-fp32-sse41-ld128.c
  src/qs8-gemm/gen/qs8-gemm-2x4c8-xw-minmax-fp32-sse41.c
  src/qs8-gemm/gen/qs8-gemm-3x4c2-minmax-fp32-sse41-ld64.c
  src/qs8-gemm/gen/qs8-gemm-3x4c2-minmax-fp32-sse41-ld128.c
  src/qs8-gemm/gen/qs8-gemm-3x4c2-xw-minmax-fp32-sse41.c
  src/qs8-gemm/gen/qs8-gemm-3x4c2s4-minmax-fp32-sse41-ld64.c
  src/qs8-gemm/gen/qs8-gemm-3x4c2s4-minmax-fp32-sse41-ld128.c
  src/qs8-gemm/gen/qs8-gemm-3x4c2s4-xw-minmax-fp32-sse41.c
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  src/qu8-gemm/gen/qu8-gemm-3x4c2s4-minmax-fp32-sse41-ld128.c
  src/qu8-gemm/gen/qu8-gemm-3x4c8-minmax-fp32-sse41-ld64.c
  src/qu8-gemm/gen/qu8-gemm-3x4c8-minmax-fp32-sse41-ld128.c
  src/qu8-gemm/gen/qu8-gemm-4x4c2-minmax-fp32-sse41-ld64.c
  src/qu8-gemm/gen/qu8-gemm-4x4c2-minmax-fp32-sse41-ld128.c
  src/qu8-gemm/gen/qu8-gemm-4x4c2s4-minmax-fp32-sse41-ld64.c
  src/qu8-gemm/gen/qu8-gemm-4x4c2s4-minmax-fp32-sse41-ld128.c
  src/qu8-igemm/gen/qu8-igemm-1x4c2-minmax-fp32-sse41-ld64.c
  src/qu8-igemm/gen/qu8-igemm-1x4c2-minmax-fp32-sse41-ld128.c
  src/qu8-igemm/gen/qu8-igemm-1x4c2s4-minmax-fp32-sse41-ld64.c
  src/qu8-igemm/gen/qu8-igemm-1x4c2s4-minmax-fp32-sse41-ld128.c
  src/qu8-igemm/gen/qu8-igemm-1x4c8-minmax-fp32-sse41-ld64.c
  src/qu8-igemm/gen/qu8-igemm-1x4c8-minmax-fp32-sse41-ld128.c
  src/qu8-igemm/gen/qu8-igemm-2x4c2-minmax-fp32-sse41-ld64.c
  src/qu8-igemm/gen/qu8-igemm-2x4c2-minmax-fp32-sse41-ld128.c
  src/qu8-igemm/gen/qu8-igemm-2x4c2s4-minmax-fp32-sse41-ld64.c
  src/qu8-igemm/gen/qu8-igemm-2x4c2s4-minmax-fp32-sse41-ld128.c
  src/qu8-igemm/gen/qu8-igemm-2x4c8-minmax-fp32-sse41-ld64.c
  src/qu8-igemm/gen/qu8-igemm-2x4c8-minmax-fp32-sse41-ld128.c
  src/qu8-igemm/gen/qu8-igemm-3x4c2-minmax-fp32-sse41-ld64.c
  src/qu8-igemm/gen/qu8-igemm-3x4c2-minmax-fp32-sse41-ld128.c
  src/qu8-igemm/gen/qu8-igemm-3x4c2s4-minmax-fp32-sse41-ld64.c
  src/qu8-igemm/gen/qu8-igemm-3x4c2s4-minmax-fp32-sse41-ld128.c
  src/qu8-igemm/gen/qu8-igemm-3x4c8-minmax-fp32-sse41-ld64.c
  src/qu8-igemm/gen/qu8-igemm-3x4c8-minmax-fp32-sse41-ld128.c
  src/qu8-igemm/gen/qu8-igemm-4x4c2-minmax-fp32-sse41-ld64.c
  src/qu8-igemm/gen/qu8-igemm-4x4c2-minmax-fp32-sse41-ld128.c
  src/qu8-igemm/gen/qu8-igemm-4x4c2s4-minmax-fp32-sse41-ld64.c
  src/qu8-igemm/gen/qu8-igemm-4x4c2s4-minmax-fp32-sse41-ld128.c
  src/qu8-requantization/qu8-requantization-gemmlowp-sse41.c
  src/qu8-requantization/qu8-requantization-rndna-sse41.c
  src/qu8-vadd/gen/qu8-vadd-minmax-sse41-mul16-ld64-x8.c
  src/qu8-vadd/gen/qu8-vadd-minmax-sse41-mul16-ld64-x16.c
  src/qu8-vadd/gen/qu8-vadd-minmax-sse41-mul32-ld32-x8.c
  src/qu8-vadd/gen/qu8-vadd-minmax-sse41-mul32-ld32-x16.c
  src/qu8-vaddc/gen/qu8-vaddc-minmax-sse41-mul16-ld64-x8.c
  src/qu8-vaddc/gen/qu8-vaddc-minmax-sse41-mul16-ld64-x16.c
  src/qu8-vaddc/gen/qu8-vaddc-minmax-sse41-mul32-ld32-x8.c
  src/qu8-vaddc/gen/qu8-vaddc-minmax-sse41-mul32-ld32-x16.c
  src/qu8-vcvt/gen/qu8-vcvt-sse41-x8.c
  src/qu8-vcvt/gen/qu8-vcvt-sse41-x16.c
  src/qu8-vcvt/gen/qu8-vcvt-sse41-x32.c
  src/qu8-vlrelu/gen/qu8-vlrelu-sse41-x8.c
  src/qu8-vlrelu/gen/qu8-vlrelu-sse41-x16.c
  src/qu8-vlrelu/gen/qu8-vlrelu-sse41-x32.c
  src/qu8-vmul/gen/qu8-vmul-minmax-fp32-sse41-mul16-ld64-x8.c
  src/qu8-vmul/gen/qu8-vmul-minmax-fp32-sse41-mul16-ld64-x16.c
  src/qu8-vmulc/gen/qu8-vmulc-minmax-fp32-sse41-mul16-ld64-x8.c
  src/qu8-vmulc/gen/qu8-vmulc-minmax-fp32-sse41-mul16-ld64-x16.c
  src/s8-ibilinear/gen/s8-ibilinear-sse41-c8.c
  src/s8-ibilinear/gen/s8-ibilinear-sse41-c16.c
  src/s8-maxpool/s8-maxpool-9p8x-minmax-sse41-c16.c
  src/s8-vclamp/s8-vclamp-sse41-x64.c
  src/u8-ibilinear/gen/u8-ibilinear-sse41-c8.c
  src/u8-ibilinear/gen/u8-ibilinear-sse41-c16.c)

SET(ALL_SSSE3_MICROKERNEL_SRCS
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-ssse3-1x4-acc2.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-ssse3-1x4-acc3.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-ssse3-1x4-acc4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-ssse3-1x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-ssse3-2x4-acc2.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-ssse3-2x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-ssse3-3x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-ssse3-4x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-ssse3-5x4.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-ssse3-6x4.c
  src/qs8-gemm/gen/qs8-gemm-1x4c8-minmax-fp32-ssse3-ld64.c
  src/qs8-gemm/gen/qs8-gemm-1x4c8-minmax-fp32-ssse3-ld128.c
  src/qs8-gemm/gen/qs8-gemm-1x4c8-xw-minmax-fp32-ssse3.c
  src/qs8-gemm/gen/qs8-gemm-2x4c8-minmax-fp32-ssse3-ld64.c
  src/qs8-gemm/gen/qs8-gemm-2x4c8-minmax-fp32-ssse3-ld128.c
  src/qs8-gemm/gen/qs8-gemm-2x4c8-xw-minmax-fp32-ssse3.c
  src/qs8-gemm/gen/qs8-gemm-3x4c8-minmax-fp32-ssse3-ld64.c
  src/qs8-gemm/gen/qs8-gemm-3x4c8-minmax-fp32-ssse3-ld128.c
  src/qs8-gemm/gen/qs8-gemm-3x4c8-xw-minmax-fp32-ssse3.c
  src/qs8-igemm/gen/qs8-igemm-1x4c8-minmax-fp32-ssse3-ld64.c
  src/qs8-igemm/gen/qs8-igemm-1x4c8-minmax-fp32-ssse3-ld128.c
  src/qs8-igemm/gen/qs8-igemm-2x4c8-minmax-fp32-ssse3-ld64.c
  src/qs8-igemm/gen/qs8-igemm-2x4c8-minmax-fp32-ssse3-ld128.c
  src/qs8-igemm/gen/qs8-igemm-3x4c8-minmax-fp32-ssse3-ld64.c
  src/qs8-igemm/gen/qs8-igemm-3x4c8-minmax-fp32-ssse3-ld128.c
  src/qs8-requantization/qs8-requantization-gemmlowp-ssse3.c
  src/qs8-requantization/qs8-requantization-rndna-ssse3.c
  src/qs8-vcvt/gen/qs8-vcvt-ssse3-x16.c
  src/qs8-vcvt/gen/qs8-vcvt-ssse3-x32.c
  src/qs8-vlrelu/gen/qs8-vlrelu-ssse3-x16.c
  src/qs8-vlrelu/gen/qs8-vlrelu-ssse3-x32.c
  src/qs16-qs8-vcvt/gen/qs16-qs8-vcvt-ssse3-x4.c
  src/qs16-qs8-vcvt/gen/qs16-qs8-vcvt-ssse3-x8.c
  src/qs16-qs8-vcvt/gen/qs16-qs8-vcvt-ssse3-x16.c
  src/qu8-requantization/qu8-requantization-gemmlowp-ssse3.c
  src/qu8-requantization/qu8-requantization-rndna-ssse3.c
  src/qu8-vcvt/gen/qu8-vcvt-ssse3-x16.c
  src/qu8-vcvt/gen/qu8-vcvt-ssse3-x32.c
  src/qu8-vlrelu/gen/qu8-vlrelu-ssse3-x16.c
  src/qu8-vlrelu/gen/qu8-vlrelu-ssse3-x32.c
  src/x8-lut/gen/x8-lut-ssse3-x16.c
  src/x8-lut/gen/x8-lut-ssse3-x32.c
  src/x24-transposec/x24-transposec-4x4-ssse3.c)

SET(ALL_WASM_MICROKERNEL_SRCS
  src/f32-avgpool/f32-avgpool-9p8x-minmax-wasm-c1.c
  src/f32-avgpool/f32-avgpool-9x-minmax-wasm-c1.c
  src/f32-dwconv/gen/f32-dwconv-3f3m3l1c1s1r-minmax-wasm-acc2.c
  src/f32-dwconv/gen/f32-dwconv-3f3m3l1c1s1r-minmax-wasm.c
  src/f32-dwconv/gen/f32-dwconv-3p1c-minmax-wasm-acc2.c
  src/f32-dwconv/gen/f32-dwconv-3p1c-minmax-wasm.c
  src/f32-dwconv/gen/f32-dwconv-3p2c-minmax-wasm-acc2.c
  src/f32-dwconv/gen/f32-dwconv-3p2c-minmax-wasm.c
  src/f32-dwconv/gen/f32-dwconv-4p1c-minmax-wasm-acc2.c
  src/f32-dwconv/gen/f32-dwconv-4p1c-minmax-wasm.c
  src/f32-dwconv/gen/f32-dwconv-4p2c-minmax-wasm-acc2.c
  src/f32-dwconv/gen/f32-dwconv-4p2c-minmax-wasm.c
  src/f32-dwconv/gen/f32-dwconv-5f5m5l1c1s1r-minmax-wasm-acc2.c
  src/f32-dwconv/gen/f32-dwconv-5f5m5l1c1s1r-minmax-wasm.c
  src/f32-dwconv/gen/f32-dwconv-6f6m7l1c1s1r-minmax-wasm-acc2.c
  src/f32-dwconv/gen/f32-dwconv-6f6m7l1c1s1r-minmax-wasm.c
  src/f32-dwconv/gen/f32-dwconv-8f8m9l1c1s1r-minmax-wasm-acc2.c
  src/f32-dwconv/gen/f32-dwconv-8f8m9l1c1s1r-minmax-wasm.c
  src/f32-dwconv/gen/f32-dwconv-9p1c-minmax-wasm-acc2.c
  src/f32-dwconv/gen/f32-dwconv-9p1c-minmax-wasm.c
  src/f32-dwconv/gen/f32-dwconv-9p2c-minmax-wasm-acc2.c
  src/f32-dwconv/gen/f32-dwconv-9p2c-minmax-wasm.c
  src/f32-dwconv/gen/f32-dwconv-25p1c-minmax-wasm-acc2.c
  src/f32-dwconv/gen/f32-dwconv-25p1c-minmax-wasm.c
  src/f32-dwconv/gen/f32-dwconv-25p2c-minmax-wasm-acc2.c
  src/f32-dwconv/gen/f32-dwconv-25p2c-minmax-wasm.c
  src/f32-gavgpool/f32-gavgpool-7p7x-minmax-wasm-c1.c
  src/f32-gavgpool/f32-gavgpool-7x-minmax-wasm-c1.c
  src/f32-gemm/gen/f32-gemm-1x4-minmax-wasm.c
  src/f32-gemm/gen/f32-gemm-1x4-relu-wasm.c
  src/f32-gemm/gen/f32-gemm-2x4-minmax-wasm.c
  src/f32-gemm/gen/f32-gemm-2x4-relu-wasm.c
  src/f32-gemm/gen/f32-gemm-4x2-minmax-wasm.c
  src/f32-gemm/gen/f32-gemm-4x2-relu-wasm.c
  src/f32-gemm/gen/f32-gemm-4x4-minmax-wasm.c
  src/f32-gemm/gen/f32-gemm-4x4-relu-wasm.c
  src/f32-gemminc/gen/f32-gemminc-1x4-minmax-wasm.c
  src/f32-gemminc/gen/f32-gemminc-2x4-minmax-wasm.c
  src/f32-gemminc/gen/f32-gemminc-4x4-minmax-wasm.c
  src/f32-igemm/gen/f32-igemm-1x4-minmax-wasm.c
  src/f32-igemm/gen/f32-igemm-1x4-relu-wasm.c
  src/f32-igemm/gen/f32-igemm-2x4-minmax-wasm.c
  src/f32-igemm/gen/f32-igemm-2x4-relu-wasm.c
  src/f32-igemm/gen/f32-igemm-4x2-minmax-wasm.c
  src/f32-igemm/gen/f32-igemm-4x2-relu-wasm.c
  src/f32-igemm/gen/f32-igemm-4x4-minmax-wasm.c
  src/f32-igemm/gen/f32-igemm-4x4-relu-wasm.c
  src/f32-maxpool/f32-maxpool-9p8x-minmax-wasm-c1.c
  src/f32-pavgpool/f32-pavgpool-9p8x-minmax-wasm-c1.c
  src/f32-pavgpool/f32-pavgpool-9x-minmax-wasm-c1.c
  src/f32-prelu/gen/f32-prelu-wasm-2x1.c
  src/f32-prelu/gen/f32-prelu-wasm-2x4.c
  src/f32-qc4w-gemm/gen/f32-qc4w-gemm-1x4-minmax-wasm.c
  src/f32-qc4w-gemm/gen/f32-qc4w-gemm-2x4-minmax-wasm.c
  src/f32-qc4w-gemm/gen/f32-qc4w-gemm-4x2-minmax-wasm.c
  src/f32-qc4w-gemm/gen/f32-qc4w-gemm-4x4-minmax-wasm.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x4-minmax-wasm.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x4-relu-wasm.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-2x4-minmax-wasm.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-2x4-relu-wasm.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x2-minmax-wasm.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x2-relu-wasm.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x4-minmax-wasm.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x4-relu-wasm.c
  src/f32-qs8-vcvt/gen/f32-qs8-vcvt-wasm-fmagic-x1.c
  src/f32-qs8-vcvt/gen/f32-qs8-vcvt-wasm-fmagic-x2.c
  src/f32-qs8-vcvt/gen/f32-qs8-vcvt-wasm-fmagic-x3.c
  src/f32-qs8-vcvt/gen/f32-qs8-vcvt-wasm-fmagic-x4.c
  src/f32-qu8-vcvt/gen/f32-qu8-vcvt-wasm-fmagic-x1.c
  src/f32-qu8-vcvt/gen/f32-qu8-vcvt-wasm-fmagic-x2.c
  src/f32-qu8-vcvt/gen/f32-qu8-vcvt-wasm-fmagic-x3.c
  src/f32-qu8-vcvt/gen/f32-qu8-vcvt-wasm-fmagic-x4.c
  src/f32-rminmax/gen/f32-rmax-wasm-x1.c
  src/f32-rminmax/gen/f32-rmax-wasm-x2-acc2.c
  src/f32-rminmax/gen/f32-rmax-wasm-x3-acc3.c
  src/f32-rminmax/gen/f32-rmax-wasm-x4-acc2.c
  src/f32-rminmax/gen/f32-rmax-wasm-x4-acc4.c
  src/f32-rminmax/gen/f32-rmin-wasm-x1.c
  src/f32-rminmax/gen/f32-rmin-wasm-x2-acc2.c
  src/f32-rminmax/gen/f32-rmin-wasm-x3-acc3.c
  src/f32-rminmax/gen/f32-rmin-wasm-x4-acc2.c
  src/f32-rminmax/gen/f32-rmin-wasm-x4-acc4.c
  src/f32-rminmax/gen/f32-rminmax-wasm-x1.c
  src/f32-rminmax/gen/f32-rminmax-wasm-x2-acc2.c
  src/f32-rminmax/gen/f32-rminmax-wasm-x3-acc3.c
  src/f32-rminmax/gen/f32-rminmax-wasm-x4-acc2.c
  src/f32-rminmax/gen/f32-rminmax-wasm-x4-acc4.c
  src/f32-vbinary/gen/f32-vadd-minmax-wasm-x1.c
  src/f32-vbinary/gen/f32-vadd-minmax-wasm-x2.c
  src/f32-vbinary/gen/f32-vadd-minmax-wasm-x4.c
  src/f32-vbinary/gen/f32-vadd-minmax-wasm-x8.c
  src/f32-vbinary/gen/f32-vadd-relu-wasm-x1.c
  src/f32-vbinary/gen/f32-vadd-relu-wasm-x2.c
  src/f32-vbinary/gen/f32-vadd-relu-wasm-x4.c
  src/f32-vbinary/gen/f32-vadd-relu-wasm-x8.c
  src/f32-vbinary/gen/f32-vaddc-minmax-wasm-x1.c
  src/f32-vbinary/gen/f32-vaddc-minmax-wasm-x2.c
  src/f32-vbinary/gen/f32-vaddc-minmax-wasm-x4.c
  src/f32-vbinary/gen/f32-vaddc-minmax-wasm-x8.c
  src/f32-vbinary/gen/f32-vaddc-relu-wasm-x1.c
  src/f32-vbinary/gen/f32-vaddc-relu-wasm-x2.c
  src/f32-vbinary/gen/f32-vaddc-relu-wasm-x4.c
  src/f32-vbinary/gen/f32-vaddc-relu-wasm-x8.c
  src/f32-vbinary/gen/f32-vdiv-minmax-wasm-x1.c
  src/f32-vbinary/gen/f32-vdiv-minmax-wasm-x2.c
  src/f32-vbinary/gen/f32-vdiv-minmax-wasm-x4.c
  src/f32-vbinary/gen/f32-vdiv-minmax-wasm-x8.c
  src/f32-vbinary/gen/f32-vdiv-relu-wasm-x1.c
  src/f32-vbinary/gen/f32-vdiv-relu-wasm-x2.c
  src/f32-vbinary/gen/f32-vdiv-relu-wasm-x4.c
  src/f32-vbinary/gen/f32-vdiv-relu-wasm-x8.c
  src/f32-vbinary/gen/f32-vdivc-minmax-wasm-x1.c
  src/f32-vbinary/gen/f32-vdivc-minmax-wasm-x2.c
  src/f32-vbinary/gen/f32-vdivc-minmax-wasm-x4.c
  src/f32-vbinary/gen/f32-vdivc-minmax-wasm-x8.c
  src/f32-vbinary/gen/f32-vdivc-relu-wasm-x1.c
  src/f32-vbinary/gen/f32-vdivc-relu-wasm-x2.c
  src/f32-vbinary/gen/f32-vdivc-relu-wasm-x4.c
  src/f32-vbinary/gen/f32-vdivc-relu-wasm-x8.c
  src/f32-vbinary/gen/f32-vmax-wasm-x1.c
  src/f32-vbinary/gen/f32-vmax-wasm-x2.c
  src/f32-vbinary/gen/f32-vmax-wasm-x4.c
  src/f32-vbinary/gen/f32-vmax-wasm-x8.c
  src/f32-vbinary/gen/f32-vmaxc-wasm-x1.c
  src/f32-vbinary/gen/f32-vmaxc-wasm-x2.c
  src/f32-vbinary/gen/f32-vmaxc-wasm-x4.c
  src/f32-vbinary/gen/f32-vmaxc-wasm-x8.c
  src/f32-vbinary/gen/f32-vmin-wasm-x1.c
  src/f32-vbinary/gen/f32-vmin-wasm-x2.c
  src/f32-vbinary/gen/f32-vmin-wasm-x4.c
  src/f32-vbinary/gen/f32-vmin-wasm-x8.c
  src/f32-vbinary/gen/f32-vminc-wasm-x1.c
  src/f32-vbinary/gen/f32-vminc-wasm-x2.c
  src/f32-vbinary/gen/f32-vminc-wasm-x4.c
  src/f32-vbinary/gen/f32-vminc-wasm-x8.c
  src/f32-vbinary/gen/f32-vmul-minmax-wasm-x1.c
  src/f32-vbinary/gen/f32-vmul-minmax-wasm-x2.c
  src/f32-vbinary/gen/f32-vmul-minmax-wasm-x4.c
  src/f32-vbinary/gen/f32-vmul-minmax-wasm-x8.c
  src/f32-vbinary/gen/f32-vmul-relu-wasm-x1.c
  src/f32-vbinary/gen/f32-vmul-relu-wasm-x2.c
  src/f32-vbinary/gen/f32-vmul-relu-wasm-x4.c
  src/f32-vbinary/gen/f32-vmul-relu-wasm-x8.c
  src/f32-vbinary/gen/f32-vmulc-minmax-wasm-x1.c
  src/f32-vbinary/gen/f32-vmulc-minmax-wasm-x2.c
  src/f32-vbinary/gen/f32-vmulc-minmax-wasm-x4.c
  src/f32-vbinary/gen/f32-vmulc-minmax-wasm-x8.c
  src/f32-vbinary/gen/f32-vmulc-relu-wasm-x1.c
  src/f32-vbinary/gen/f32-vmulc-relu-wasm-x2.c
  src/f32-vbinary/gen/f32-vmulc-relu-wasm-x4.c
  src/f32-vbinary/gen/f32-vmulc-relu-wasm-x8.c
  src/f32-vbinary/gen/f32-vrdivc-minmax-wasm-x1.c
  src/f32-vbinary/gen/f32-vrdivc-minmax-wasm-x2.c
  src/f32-vbinary/gen/f32-vrdivc-minmax-wasm-x4.c
  src/f32-vbinary/gen/f32-vrdivc-minmax-wasm-x8.c
  src/f32-vbinary/gen/f32-vrdivc-relu-wasm-x1.c
  src/f32-vbinary/gen/f32-vrdivc-relu-wasm-x2.c
  src/f32-vbinary/gen/f32-vrdivc-relu-wasm-x4.c
  src/f32-vbinary/gen/f32-vrdivc-relu-wasm-x8.c
  src/f32-vbinary/gen/f32-vrsubc-minmax-wasm-x1.c
  src/f32-vbinary/gen/f32-vrsubc-minmax-wasm-x2.c
  src/f32-vbinary/gen/f32-vrsubc-minmax-wasm-x4.c
  src/f32-vbinary/gen/f32-vrsubc-minmax-wasm-x8.c
  src/f32-vbinary/gen/f32-vrsubc-relu-wasm-x1.c
  src/f32-vbinary/gen/f32-vrsubc-relu-wasm-x2.c
  src/f32-vbinary/gen/f32-vrsubc-relu-wasm-x4.c
  src/f32-vbinary/gen/f32-vrsubc-relu-wasm-x8.c
  src/f32-vbinary/gen/f32-vsub-minmax-wasm-x1.c
  src/f32-vbinary/gen/f32-vsub-minmax-wasm-x2.c
  src/f32-vbinary/gen/f32-vsub-minmax-wasm-x4.c
  src/f32-vbinary/gen/f32-vsub-minmax-wasm-x8.c
  src/f32-vbinary/gen/f32-vsub-relu-wasm-x1.c
  src/f32-vbinary/gen/f32-vsub-relu-wasm-x2.c
  src/f32-vbinary/gen/f32-vsub-relu-wasm-x4.c
  src/f32-vbinary/gen/f32-vsub-relu-wasm-x8.c
  src/f32-vbinary/gen/f32-vsubc-minmax-wasm-x1.c
  src/f32-vbinary/gen/f32-vsubc-minmax-wasm-x2.c
  src/f32-vbinary/gen/f32-vsubc-minmax-wasm-x4.c
  src/f32-vbinary/gen/f32-vsubc-minmax-wasm-x8.c
  src/f32-vbinary/gen/f32-vsubc-relu-wasm-x1.c
  src/f32-vbinary/gen/f32-vsubc-relu-wasm-x2.c
  src/f32-vbinary/gen/f32-vsubc-relu-wasm-x4.c
  src/f32-vbinary/gen/f32-vsubc-relu-wasm-x8.c
  src/f32-vclamp/gen/f32-vclamp-wasm-x1.c
  src/f32-vclamp/gen/f32-vclamp-wasm-x2.c
  src/f32-vclamp/gen/f32-vclamp-wasm-x4.c
  src/f32-velu/gen/f32-velu-wasm-rr2-lut16-p3-x1.c
  src/f32-velu/gen/f32-velu-wasm-rr2-lut16-p3-x2.c
  src/f32-velu/gen/f32-velu-wasm-rr2-lut16-p3-x3.c
  src/f32-velu/gen/f32-velu-wasm-rr2-lut16-p3-x4.c
  src/f32-velu/gen/f32-velu-wasm-rr2-lut16-p3-x5.c
  src/f32-velu/gen/f32-velu-wasm-rr2-lut16-p3-x6.c
  src/f32-velu/gen/f32-velu-wasm-rr2-p6-x1.c
  src/f32-velu/gen/f32-velu-wasm-rr2-p6-x2.c
  src/f32-velu/gen/f32-velu-wasm-rr2-p6-x3.c
  src/f32-velu/gen/f32-velu-wasm-rr2-p6-x4.c
  src/f32-velu/gen/f32-velu-wasm-rr2-p6-x5.c
  src/f32-velu/gen/f32-velu-wasm-rr2-p6-x6.c
  src/f32-vhswish/gen/f32-vhswish-wasm-x1.c
  src/f32-vhswish/gen/f32-vhswish-wasm-x2.c
  src/f32-vhswish/gen/f32-vhswish-wasm-x4.c
  src/f32-vlrelu/gen/f32-vlrelu-wasm-x1.c
  src/f32-vlrelu/gen/f32-vlrelu-wasm-x2.c
  src/f32-vlrelu/gen/f32-vlrelu-wasm-x4.c
  src/f32-vmulcaddc/gen/f32-vmulcaddc-c1-minmax-wasm-2x.c
  src/f32-vmulcaddc/gen/f32-vmulcaddc-c2-minmax-wasm-2x.c
  src/f32-vmulcaddc/gen/f32-vmulcaddc-c4-minmax-wasm-2x.c
  src/f32-vrelu/gen/f32-vrelu-wasm-x1.c
  src/f32-vrelu/gen/f32-vrelu-wasm-x2.c
  src/f32-vrelu/gen/f32-vrelu-wasm-x4.c
  src/f32-vrelu/gen/f32-vrelu-wasm-x8.c
  src/f32-vtanh/gen/f32-vtanh-wasm-expm1minus-rr1-lut8-p4h3ts-div-x1.c
  src/f32-vtanh/gen/f32-vtanh-wasm-expm1minus-rr1-lut8-p4h3ts-div-x2.c
  src/f32-vtanh/gen/f32-vtanh-wasm-expm1minus-rr1-lut8-p4h3ts-div-x4.c
  src/f32-vtanh/gen/f32-vtanh-wasm-expm1minus-rr1-p6h5ts-div-x1.c
  src/f32-vtanh/gen/f32-vtanh-wasm-expm1minus-rr1-p6h5ts-div-x2.c
  src/f32-vtanh/gen/f32-vtanh-wasm-expm1minus-rr1-p6h5ts-div-x4.c
  src/math/gen/f32-tanh-wasm-expm1minus-rr1-lut8-p4h3ps-div.c
  src/math/gen/f32-tanh-wasm-expm1minus-rr1-p6h5ts-div.c
  src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x2-minmax-wasm.c
  src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x4-minmax-wasm.c
  src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x8-minmax-wasm.c
  src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x2-minmax-wasm.c
  src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x4-minmax-wasm.c
  src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x8-minmax-wasm.c
  src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-4x4-minmax-wasm.c
  src/qs8-dwconv/gen/qs8-dwconv-5f5m5l1c1s1r-minmax-fp32-wasm-fmagic.c
  src/qs8-dwconv/gen/qs8-dwconv-5f5m5l2c1s1r-minmax-fp32-wasm-fmagic.c
  src/qs8-dwconv/gen/qs8-dwconv-5f5m5l4c1s1r-minmax-fp32-wasm-fmagic.c
  src/qs8-dwconv/gen/qs8-dwconv-6f6m7l1c1s1r-minmax-fp32-wasm-fmagic.c
  src/qs8-dwconv/gen/qs8-dwconv-6f6m7l2c1s1r-minmax-fp32-wasm-fmagic.c
  src/qs8-dwconv/gen/qs8-dwconv-6f6m7l4c1s1r-minmax-fp32-wasm-fmagic.c
  src/qs8-dwconv/gen/qs8-dwconv-8f8m9l1c1s1r-minmax-fp32-wasm-fmagic.c
  src/qs8-dwconv/gen/qs8-dwconv-8f8m9l2c1s1r-minmax-fp32-wasm-fmagic.c
  src/qs8-dwconv/gen/qs8-dwconv-8f8m9l4c1s1r-minmax-fp32-wasm-fmagic.c
  src/qs8-dwconv/gen/qs8-dwconv-9p1c-minmax-fp32-wasm-fmagic.c
  src/qs8-dwconv/gen/qs8-dwconv-9p2c-minmax-fp32-wasm-fmagic.c
  src/qs8-dwconv/gen/qs8-dwconv-9p4c-minmax-fp32-wasm-fmagic.c
  src/qs8-dwconv/gen/qs8-dwconv-25p1c-minmax-fp32-wasm-fmagic.c
  src/qs8-dwconv/gen/qs8-dwconv-25p2c-minmax-fp32-wasm-fmagic.c
  src/qs8-dwconv/gen/qs8-dwconv-25p4c-minmax-fp32-wasm-fmagic.c
  src/qs8-gemm/gen/qs8-gemm-1x2-minmax-fp32-wasm-fmagic.c
  src/qs8-gemm/gen/qs8-gemm-1x4-minmax-fp32-wasm-fmagic.c
  src/qs8-gemm/gen/qs8-gemm-2x2-minmax-fp32-wasm-fmagic.c
  src/qs8-gemm/gen/qs8-gemm-2x4-minmax-fp32-wasm-fmagic.c
  src/qs8-gemm/gen/qs8-gemm-3x2-minmax-fp32-wasm-fmagic.c
  src/qs8-gemm/gen/qs8-gemm-3x4-minmax-fp32-wasm-fmagic.c
  src/qs8-gemm/gen/qs8-gemm-4x2-minmax-fp32-wasm-fmagic.c
  src/qs8-gemm/gen/qs8-gemm-4x4-minmax-fp32-wasm-fmagic.c
  src/qs8-igemm/gen/qs8-igemm-1x2-minmax-fp32-wasm-fmagic.c
  src/qs8-igemm/gen/qs8-igemm-1x4-minmax-fp32-wasm-fmagic.c
  src/qs8-igemm/gen/qs8-igemm-2x2-minmax-fp32-wasm-fmagic.c
  src/qs8-igemm/gen/qs8-igemm-2x4-minmax-fp32-wasm-fmagic.c
  src/qs8-igemm/gen/qs8-igemm-3x2-minmax-fp32-wasm-fmagic.c
  src/qs8-igemm/gen/qs8-igemm-3x4-minmax-fp32-wasm-fmagic.c
  src/qs8-igemm/gen/qs8-igemm-4x2-minmax-fp32-wasm-fmagic.c
  src/qs8-igemm/gen/qs8-igemm-4x4-minmax-fp32-wasm-fmagic.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-3p2c-minmax-fp32-wasm-fmagic.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l1c1s1r-minmax-fp32-wasm-fmagic.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l2c1s1r-minmax-fp32-wasm-fmagic.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l4c1s1r-minmax-fp32-wasm-fmagic.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l1c1s1r-minmax-fp32-wasm-fmagic.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l2c1s1r-minmax-fp32-wasm-fmagic.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l4c1s1r-minmax-fp32-wasm-fmagic.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l1c1s1r-minmax-fp32-wasm-fmagic.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l2c1s1r-minmax-fp32-wasm-fmagic.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l4c1s1r-minmax-fp32-wasm-fmagic.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p1c-minmax-fp32-wasm-fmagic.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p2c-minmax-fp32-wasm-fmagic.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p4c-minmax-fp32-wasm-fmagic.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p1c-minmax-fp32-wasm-fmagic.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p2c-minmax-fp32-wasm-fmagic.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p4c-minmax-fp32-wasm-fmagic.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x2-minmax-fp32-wasm-fmagic.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4-minmax-fp32-wasm-fmagic.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x2-minmax-fp32-wasm-fmagic.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4-minmax-fp32-wasm-fmagic.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x2-minmax-fp32-wasm-fmagic.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4-minmax-fp32-wasm-fmagic.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x2-minmax-fp32-wasm-fmagic.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4-minmax-fp32-wasm-fmagic.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x2-minmax-fp32-wasm-fmagic.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4-minmax-fp32-wasm-fmagic.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x2-minmax-fp32-wasm-fmagic.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4-minmax-fp32-wasm-fmagic.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x2-minmax-fp32-wasm-fmagic.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4-minmax-fp32-wasm-fmagic.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x2-minmax-fp32-wasm-fmagic.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4-minmax-fp32-wasm-fmagic.c
  src/qu8-dwconv/gen/qu8-dwconv-5f5m5l1c1s1r-minmax-fp32-wasm-fmagic.c
  src/qu8-dwconv/gen/qu8-dwconv-5f5m5l2c1s1r-minmax-fp32-wasm-fmagic.c
  src/qu8-dwconv/gen/qu8-dwconv-5f5m5l4c1s1r-minmax-fp32-wasm-fmagic.c
  src/qu8-dwconv/gen/qu8-dwconv-6f6m7l1c1s1r-minmax-fp32-wasm-fmagic.c
  src/qu8-dwconv/gen/qu8-dwconv-6f6m7l2c1s1r-minmax-fp32-wasm-fmagic.c
  src/qu8-dwconv/gen/qu8-dwconv-6f6m7l4c1s1r-minmax-fp32-wasm-fmagic.c
  src/qu8-dwconv/gen/qu8-dwconv-8f8m9l1c1s1r-minmax-fp32-wasm-fmagic.c
  src/qu8-dwconv/gen/qu8-dwconv-8f8m9l2c1s1r-minmax-fp32-wasm-fmagic.c
  src/qu8-dwconv/gen/qu8-dwconv-8f8m9l4c1s1r-minmax-fp32-wasm-fmagic.c
  src/qu8-dwconv/gen/qu8-dwconv-9p1c-minmax-fp32-wasm-fmagic.c
  src/qu8-dwconv/gen/qu8-dwconv-9p2c-minmax-fp32-wasm-fmagic.c
  src/qu8-dwconv/gen/qu8-dwconv-9p4c-minmax-fp32-wasm-fmagic.c
  src/qu8-dwconv/gen/qu8-dwconv-25p1c-minmax-fp32-wasm-fmagic.c
  src/qu8-dwconv/gen/qu8-dwconv-25p2c-minmax-fp32-wasm-fmagic.c
  src/qu8-dwconv/gen/qu8-dwconv-25p4c-minmax-fp32-wasm-fmagic.c
  src/qu8-gemm/gen/qu8-gemm-1x2-minmax-fp32-wasm-fmagic.c
  src/qu8-gemm/gen/qu8-gemm-1x4-minmax-fp32-wasm-fmagic.c
  src/qu8-gemm/gen/qu8-gemm-2x2-minmax-fp32-wasm-fmagic.c
  src/qu8-gemm/gen/qu8-gemm-2x4-minmax-fp32-wasm-fmagic.c
  src/qu8-gemm/gen/qu8-gemm-3x2-minmax-fp32-wasm-fmagic.c
  src/qu8-gemm/gen/qu8-gemm-3x4-minmax-fp32-wasm-fmagic.c
  src/qu8-gemm/gen/qu8-gemm-4x2-minmax-fp32-wasm-fmagic.c
  src/qu8-gemm/gen/qu8-gemm-4x4-minmax-fp32-wasm-fmagic.c
  src/qu8-igemm/gen/qu8-igemm-1x2-minmax-fp32-wasm-fmagic.c
  src/qu8-igemm/gen/qu8-igemm-1x4-minmax-fp32-wasm-fmagic.c
  src/qu8-igemm/gen/qu8-igemm-2x2-minmax-fp32-wasm-fmagic.c
  src/qu8-igemm/gen/qu8-igemm-2x4-minmax-fp32-wasm-fmagic.c
  src/qu8-igemm/gen/qu8-igemm-3x2-minmax-fp32-wasm-fmagic.c
  src/qu8-igemm/gen/qu8-igemm-3x4-minmax-fp32-wasm-fmagic.c
  src/qu8-igemm/gen/qu8-igemm-4x2-minmax-fp32-wasm-fmagic.c
  src/qu8-igemm/gen/qu8-igemm-4x4-minmax-fp32-wasm-fmagic.c)

SET(ALL_WASMRELAXEDSIMD_MICROKERNEL_SRCS
  src/f16-f32-vcvt/gen/f16-f32-vcvt-wasmrelaxedsimd-int16-x8.c
  src/f16-f32-vcvt/gen/f16-f32-vcvt-wasmrelaxedsimd-int16-x16.c
  src/f16-f32-vcvt/gen/f16-f32-vcvt-wasmrelaxedsimd-int16-x24.c
  src/f16-f32-vcvt/gen/f16-f32-vcvt-wasmrelaxedsimd-int16-x32.c
  src/f16-f32-vcvt/gen/f16-f32-vcvt-wasmrelaxedsimd-int32-x8.c
  src/f16-f32-vcvt/gen/f16-f32-vcvt-wasmrelaxedsimd-int32-x16.c
  src/f16-f32-vcvt/gen/f16-f32-vcvt-wasmrelaxedsimd-int32-x24.c
  src/f16-f32-vcvt/gen/f16-f32-vcvt-wasmrelaxedsimd-int32-x32.c
  src/f32-dwconv/gen/f32-dwconv-3p4c-minmax-wasmrelaxedsimd-acc2.c
  src/f32-dwconv/gen/f32-dwconv-3p4c-minmax-wasmrelaxedsimd-fma-acc2.c
  src/f32-dwconv/gen/f32-dwconv-3p4c-minmax-wasmrelaxedsimd-fma.c
  src/f32-dwconv/gen/f32-dwconv-3p4c-minmax-wasmrelaxedsimd.c
  src/f32-dwconv/gen/f32-dwconv-3p4c-wasmrelaxedsimd-fma.c
  src/f32-dwconv/gen/f32-dwconv-3p8c-minmax-wasmrelaxedsimd-acc2.c
  src/f32-dwconv/gen/f32-dwconv-3p8c-minmax-wasmrelaxedsimd-fma-acc2.c
  src/f32-dwconv/gen/f32-dwconv-3p8c-minmax-wasmrelaxedsimd-fma.c
  src/f32-dwconv/gen/f32-dwconv-3p8c-minmax-wasmrelaxedsimd.c
  src/f32-dwconv/gen/f32-dwconv-3p8c-wasmrelaxedsimd-fma.c
  src/f32-dwconv/gen/f32-dwconv-4p4c-minmax-wasmrelaxedsimd-acc2.c
  src/f32-dwconv/gen/f32-dwconv-4p4c-minmax-wasmrelaxedsimd-fma-acc2.c
  src/f32-dwconv/gen/f32-dwconv-4p4c-minmax-wasmrelaxedsimd-fma.c
  src/f32-dwconv/gen/f32-dwconv-4p4c-minmax-wasmrelaxedsimd.c
  src/f32-dwconv/gen/f32-dwconv-4p4c-wasmrelaxedsimd-fma.c
  src/f32-dwconv/gen/f32-dwconv-4p8c-minmax-wasmrelaxedsimd-acc2.c
  src/f32-dwconv/gen/f32-dwconv-4p8c-minmax-wasmrelaxedsimd-fma-acc2.c
  src/f32-dwconv/gen/f32-dwconv-4p8c-minmax-wasmrelaxedsimd-fma.c
  src/f32-dwconv/gen/f32-dwconv-4p8c-minmax-wasmrelaxedsimd.c
  src/f32-dwconv/gen/f32-dwconv-4p8c-wasmrelaxedsimd-fma.c
  src/f32-dwconv/gen/f32-dwconv-5f5m5l4c4s4r-minmax-wasmrelaxedsimd-acc2.c
  src/f32-dwconv/gen/f32-dwconv-5f5m5l4c4s4r-minmax-wasmrelaxedsimd-fma-acc2.c
  src/f32-dwconv/gen/f32-dwconv-5f5m5l4c4s4r-minmax-wasmrelaxedsimd-fma.c
  src/f32-dwconv/gen/f32-dwconv-5f5m5l4c4s4r-minmax-wasmrelaxedsimd.c
  src/f32-dwconv/gen/f32-dwconv-5f5m5l4c4s4r-wasmrelaxedsimd-fma-acc2.c
  src/f32-dwconv/gen/f32-dwconv-5f5m5l4c4s4r-wasmrelaxedsimd-fma.c
  src/f32-dwconv/gen/f32-dwconv-9p4c-minmax-wasmrelaxedsimd-acc2.c
  src/f32-dwconv/gen/f32-dwconv-9p4c-minmax-wasmrelaxedsimd-fma-acc2.c
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  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-relu-wasmrelaxedsimd-fma-loadsplat.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-relu-wasmrelaxedsimd-fma-splat.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-wasmrelaxedsimd-fma-loadsplat.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-wasmrelaxedsimd-fma-splat.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8s4-minmax-wasmrelaxedsimd-fma.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8s4-minmax-wasmrelaxedsimd.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8s4-relu-wasmrelaxedsimd-fma.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8s4-wasmrelaxedsimd-fma.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8-minmax-wasmrelaxedsimd-fma-loadsplat.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8-minmax-wasmrelaxedsimd-fma-splat.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8-minmax-wasmrelaxedsimd-loadsplat.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8-minmax-wasmrelaxedsimd-splat.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8-relu-wasmrelaxedsimd-fma-loadsplat.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8-relu-wasmrelaxedsimd-fma-splat.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8-wasmrelaxedsimd-fma-loadsplat.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8-wasmrelaxedsimd-fma-splat.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8s4-minmax-wasmrelaxedsimd-fma.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8s4-minmax-wasmrelaxedsimd.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8s4-relu-wasmrelaxedsimd-fma.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-3x8s4-wasmrelaxedsimd-fma.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x2c4-minmax-wasmrelaxedsimd-fma.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x2c4-minmax-wasmrelaxedsimd.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x2c4-relu-wasmrelaxedsimd-fma.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x2c4-wasmrelaxedsimd-fma.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-minmax-wasmrelaxedsimd-fma-loadsplat.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-minmax-wasmrelaxedsimd-fma-splat.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-minmax-wasmrelaxedsimd-loadsplat.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-minmax-wasmrelaxedsimd-splat.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-relu-wasmrelaxedsimd-fma-loadsplat.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-relu-wasmrelaxedsimd-fma-splat.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-wasmrelaxedsimd-fma-loadsplat.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-wasmrelaxedsimd-fma-splat.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8s4-minmax-wasmrelaxedsimd-fma.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8s4-minmax-wasmrelaxedsimd.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8s4-relu-wasmrelaxedsimd-fma.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8s4-wasmrelaxedsimd-fma.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-minmax-wasmrelaxedsimd-fma-loadsplat.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-minmax-wasmrelaxedsimd-fma-splat.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-minmax-wasmrelaxedsimd-loadsplat.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-minmax-wasmrelaxedsimd-splat.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-relu-wasmrelaxedsimd-fma-loadsplat.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-relu-wasmrelaxedsimd-fma-splat.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-wasmrelaxedsimd-fma-loadsplat.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8-wasmrelaxedsimd-fma-splat.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8s4-minmax-wasmrelaxedsimd-fma.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8s4-minmax-wasmrelaxedsimd.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8s4-relu-wasmrelaxedsimd-fma.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-5x8s4-wasmrelaxedsimd-fma.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-minmax-wasmrelaxedsimd-fma-loadsplat.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-minmax-wasmrelaxedsimd-fma-splat.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-minmax-wasmrelaxedsimd-loadsplat.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-minmax-wasmrelaxedsimd-splat.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-relu-wasmrelaxedsimd-fma-loadsplat.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-relu-wasmrelaxedsimd-fma-splat.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-wasmrelaxedsimd-fma-loadsplat.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8-wasmrelaxedsimd-fma-splat.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8s4-minmax-wasmrelaxedsimd-fma.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8s4-minmax-wasmrelaxedsimd.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8s4-relu-wasmrelaxedsimd-fma.c
  src/f32-qc8w-gemm/gen/f32-qc8w-gemm-6x8s4-wasmrelaxedsimd-fma.c
  src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmrelaxedsimd-rr2-p5-x4.c
  src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmrelaxedsimd-rr2-p5-x8-acc2.c
  src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmrelaxedsimd-rr2-p5-x8.c
  src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmrelaxedsimd-rr2-p5-x12-acc2.c
  src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmrelaxedsimd-rr2-p5-x12-acc3.c
  src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmrelaxedsimd-rr2-p5-x12.c
  src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmrelaxedsimd-rr2-p5-x16-acc2.c
  src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmrelaxedsimd-rr2-p5-x16-acc4.c
  src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmrelaxedsimd-rr2-p5-x16.c
  src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmrelaxedsimd-rr2-p5-x20-acc2.c
  src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmrelaxedsimd-rr2-p5-x20-acc5.c
  src/f32-raddstoreexpminusmax/gen/f32-raddstoreexpminusmax-wasmrelaxedsimd-rr2-p5-x20.c
  src/f32-velu/gen/f32-velu-wasmrelaxedsimd-fma-rr2-lut16-p3-x4.c
  src/f32-velu/gen/f32-velu-wasmrelaxedsimd-fma-rr2-lut16-p3-x8.c
  src/f32-velu/gen/f32-velu-wasmrelaxedsimd-fma-rr2-lut16-p3-x12.c
  src/f32-velu/gen/f32-velu-wasmrelaxedsimd-fma-rr2-lut16-p3-x16.c
  src/f32-velu/gen/f32-velu-wasmrelaxedsimd-fma-rr2-lut16-p3-x20.c
  src/f32-velu/gen/f32-velu-wasmrelaxedsimd-fma-rr2-lut16-p3-x24.c
  src/f32-velu/gen/f32-velu-wasmrelaxedsimd-fma-rr2-p6-x4.c
  src/f32-velu/gen/f32-velu-wasmrelaxedsimd-fma-rr2-p6-x8.c
  src/f32-velu/gen/f32-velu-wasmrelaxedsimd-fma-rr2-p6-x12.c
  src/f32-velu/gen/f32-velu-wasmrelaxedsimd-fma-rr2-p6-x16.c
  src/f32-velu/gen/f32-velu-wasmrelaxedsimd-fma-rr2-p6-x20.c
  src/f32-velu/gen/f32-velu-wasmrelaxedsimd-fma-rr2-p6-x24.c
  src/f32-velu/gen/f32-velu-wasmrelaxedsimd-rr2-lut16-p3-x4.c
  src/f32-velu/gen/f32-velu-wasmrelaxedsimd-rr2-lut16-p3-x8.c
  src/f32-velu/gen/f32-velu-wasmrelaxedsimd-rr2-lut16-p3-x12.c
  src/f32-velu/gen/f32-velu-wasmrelaxedsimd-rr2-lut16-p3-x16.c
  src/f32-velu/gen/f32-velu-wasmrelaxedsimd-rr2-lut16-p3-x20.c
  src/f32-velu/gen/f32-velu-wasmrelaxedsimd-rr2-lut16-p3-x24.c
  src/f32-velu/gen/f32-velu-wasmrelaxedsimd-rr2-p6-x4.c
  src/f32-velu/gen/f32-velu-wasmrelaxedsimd-rr2-p6-x8.c
  src/f32-velu/gen/f32-velu-wasmrelaxedsimd-rr2-p6-x12.c
  src/f32-velu/gen/f32-velu-wasmrelaxedsimd-rr2-p6-x16.c
  src/f32-velu/gen/f32-velu-wasmrelaxedsimd-rr2-p6-x20.c
  src/f32-velu/gen/f32-velu-wasmrelaxedsimd-rr2-p6-x24.c
  src/f32-vlrelu/gen/f32-vlrelu-wasmrelaxedsimd-iminmax-x4.c
  src/f32-vlrelu/gen/f32-vlrelu-wasmrelaxedsimd-iminmax-x8.c
  src/f32-vlrelu/gen/f32-vlrelu-wasmrelaxedsimd-laneselect-x4.c
  src/f32-vlrelu/gen/f32-vlrelu-wasmrelaxedsimd-laneselect-x8.c
  src/f32-vmulcaddc/gen/f32-vmulcaddc-c4-minmax-wasmrelaxedsimd-2x.c
  src/f32-vmulcaddc/gen/f32-vmulcaddc-c4-minmax-wasmrelaxedsimd-fma-2x.c
  src/f32-vmulcaddc/gen/f32-vmulcaddc-c8-minmax-wasmrelaxedsimd-2x.c
  src/f32-vmulcaddc/gen/f32-vmulcaddc-c8-minmax-wasmrelaxedsimd-fma-2x.c
  src/f32-vsigmoid/gen/f32-vsigmoid-wasmblendvps-fma-rr2-p5-div-x4.c
  src/f32-vsigmoid/gen/f32-vsigmoid-wasmblendvps-fma-rr2-p5-div-x8.c
  src/f32-vsigmoid/gen/f32-vsigmoid-wasmblendvps-fma-rr2-p5-div-x12.c
  src/f32-vsigmoid/gen/f32-vsigmoid-wasmblendvps-fma-rr2-p5-div-x16.c
  src/f32-vsigmoid/gen/f32-vsigmoid-wasmblendvps-fma-rr2-p5-div-x20.c
  src/f32-vsigmoid/gen/f32-vsigmoid-wasmblendvps-fma-rr2-p5-div-x24.c
  src/f32-vsigmoid/gen/f32-vsigmoid-wasmblendvps-rr2-p5-div-x4.c
  src/f32-vsigmoid/gen/f32-vsigmoid-wasmblendvps-rr2-p5-div-x8.c
  src/f32-vsigmoid/gen/f32-vsigmoid-wasmblendvps-rr2-p5-div-x12.c
  src/f32-vsigmoid/gen/f32-vsigmoid-wasmblendvps-rr2-p5-div-x16.c
  src/f32-vsigmoid/gen/f32-vsigmoid-wasmblendvps-rr2-p5-div-x20.c
  src/f32-vsigmoid/gen/f32-vsigmoid-wasmblendvps-rr2-p5-div-x24.c
  src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-fma-rr2-lut64-p2-div-x4.c
  src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-fma-rr2-lut64-p2-div-x8.c
  src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-fma-rr2-lut64-p2-div-x12.c
  src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-fma-rr2-lut64-p2-div-x16.c
  src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-fma-rr2-lut64-p2-div-x20.c
  src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-fma-rr2-lut64-p2-div-x24.c
  src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-fma-rr2-p5-div-x4.c
  src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-fma-rr2-p5-div-x8.c
  src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-fma-rr2-p5-div-x12.c
  src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-fma-rr2-p5-div-x16.c
  src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-fma-rr2-p5-div-x20.c
  src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-fma-rr2-p5-div-x24.c
  src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-rr2-lut64-p2-div-x4.c
  src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-rr2-lut64-p2-div-x8.c
  src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-rr2-lut64-p2-div-x12.c
  src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-rr2-lut64-p2-div-x16.c
  src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-rr2-lut64-p2-div-x20.c
  src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-rr2-lut64-p2-div-x24.c
  src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-rr2-p5-div-x4.c
  src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-rr2-p5-div-x8.c
  src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-rr2-p5-div-x12.c
  src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-rr2-p5-div-x16.c
  src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-rr2-p5-div-x20.c
  src/f32-vsigmoid/gen/f32-vsigmoid-wasmrelaxedsimd-rr2-p5-div-x24.c
  src/qs8-gemm/gen/qs8-gemm-1x4c16-minmax-fp32-wasmsdot.c
  src/qs8-gemm/gen/qs8-gemm-2x4c16-minmax-fp32-wasmsdot.c
  src/qs8-gemm/gen/qs8-gemm-3x4c16-minmax-fp32-wasmsdot.c
  src/qs8-gemm/gen/qs8-gemm-4x4c16-minmax-fp32-wasmsdot.c
  src/qs8-igemm/gen/qs8-igemm-1x4c16-minmax-fp32-wasmsdot.c
  src/qs8-igemm/gen/qs8-igemm-2x4c16-minmax-fp32-wasmsdot.c
  src/qs8-igemm/gen/qs8-igemm-3x4c16-minmax-fp32-wasmsdot.c
  src/qs8-igemm/gen/qs8-igemm-4x4c16-minmax-fp32-wasmsdot.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c16-minmax-fp32-wasmsdot.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c16-minmax-fp32-wasmsdot.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c16-minmax-fp32-wasmsdot.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4c16-minmax-fp32-wasmsdot.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c16-minmax-fp32-wasmsdot.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c16-minmax-fp32-wasmsdot.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c16-minmax-fp32-wasmsdot.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c16-minmax-fp32-wasmsdot.c
  src/qs8-vcvt/gen/qs8-vcvt-wasmrelaxedsimd-x8.c
  src/qs8-vcvt/gen/qs8-vcvt-wasmrelaxedsimd-x16.c
  src/qs8-vcvt/gen/qs8-vcvt-wasmrelaxedsimd-x32.c
  src/qs8-vlrelu/gen/qs8-vlrelu-wasmrelaxedsimd-arm-x16.c
  src/qs8-vlrelu/gen/qs8-vlrelu-wasmrelaxedsimd-arm-x32.c
  src/qs8-vlrelu/gen/qs8-vlrelu-wasmrelaxedsimd-x86-x8.c
  src/qs8-vlrelu/gen/qs8-vlrelu-wasmrelaxedsimd-x86-x16.c
  src/qs8-vlrelu/gen/qs8-vlrelu-wasmrelaxedsimd-x86-x32.c
  src/qu8-vcvt/gen/qu8-vcvt-wasmrelaxedsimd-x8.c
  src/qu8-vcvt/gen/qu8-vcvt-wasmrelaxedsimd-x16.c
  src/qu8-vcvt/gen/qu8-vcvt-wasmrelaxedsimd-x32.c
  src/qu8-vlrelu/gen/qu8-vlrelu-wasmrelaxedsimd-arm-x16.c
  src/qu8-vlrelu/gen/qu8-vlrelu-wasmrelaxedsimd-arm-x32.c
  src/qu8-vlrelu/gen/qu8-vlrelu-wasmrelaxedsimd-x86-x8.c
  src/qu8-vlrelu/gen/qu8-vlrelu-wasmrelaxedsimd-x86-x16.c
  src/qu8-vlrelu/gen/qu8-vlrelu-wasmrelaxedsimd-x86-x32.c
  src/x8-lut/gen/x8-lut-wasmpshufb-x16.c
  src/x8-lut/gen/x8-lut-wasmpshufb-x32.c
  src/x8-lut/gen/x8-lut-wasmpshufb-x48.c
  src/x8-lut/gen/x8-lut-wasmpshufb-x64.c)

SET(ALL_WASMSIMD_MICROKERNEL_SRCS
  src/f16-f32-vcvt/gen/f16-f32-vcvt-wasmsimd-int16-x8.c
  src/f16-f32-vcvt/gen/f16-f32-vcvt-wasmsimd-int16-x16.c
  src/f16-f32-vcvt/gen/f16-f32-vcvt-wasmsimd-int16-x24.c
  src/f16-f32-vcvt/gen/f16-f32-vcvt-wasmsimd-int16-x32.c
  src/f16-f32-vcvt/gen/f16-f32-vcvt-wasmsimd-int32-x8.c
  src/f16-f32-vcvt/gen/f16-f32-vcvt-wasmsimd-int32-x16.c
  src/f16-f32-vcvt/gen/f16-f32-vcvt-wasmsimd-int32-x24.c
  src/f16-f32-vcvt/gen/f16-f32-vcvt-wasmsimd-int32-x32.c
  src/f32-argmaxpool/f32-argmaxpool-4x-wasmsimd-c4.c
  src/f32-argmaxpool/f32-argmaxpool-9p8x-wasmsimd-c4.c
  src/f32-argmaxpool/f32-argmaxpool-9x-wasmsimd-c4.c
  src/f32-avgpool/f32-avgpool-9p8x-minmax-wasmsimd-arm-c4.c
  src/f32-avgpool/f32-avgpool-9p8x-minmax-wasmsimd-x86-c4.c
  src/f32-avgpool/f32-avgpool-9x-minmax-wasmsimd-arm-c4.c
  src/f32-avgpool/f32-avgpool-9x-minmax-wasmsimd-x86-c4.c
  src/f32-conv-hwc2chw/f32-conv-hwc2chw-3x3s2p1c3x4-wasmsimd-2x2.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-wasmsimd-arm-loadsplat-1x4-acc2.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-wasmsimd-arm-loadsplat-1x4-acc3.c
  src/f32-dwconv2d-chw/gen/f32-dwconv2d-chw-3x3p1-minmax-wasmsimd-arm-loadsplat-1x4-acc4.c
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  src/qu8-vadd/gen/qu8-vadd-minmax-wasmsimd-x16.c
  src/qu8-vadd/gen/qu8-vadd-minmax-wasmsimd-x32.c
  src/qu8-vaddc/gen/qu8-vaddc-minmax-wasmsimd-x8.c
  src/qu8-vaddc/gen/qu8-vaddc-minmax-wasmsimd-x16.c
  src/qu8-vaddc/gen/qu8-vaddc-minmax-wasmsimd-x32.c
  src/qu8-vcvt/gen/qu8-vcvt-wasmsimd-x8.c
  src/qu8-vcvt/gen/qu8-vcvt-wasmsimd-x16.c
  src/qu8-vcvt/gen/qu8-vcvt-wasmsimd-x32.c
  src/qu8-vlrelu/gen/qu8-vlrelu-wasmsimd-arm-x16.c
  src/qu8-vlrelu/gen/qu8-vlrelu-wasmsimd-arm-x32.c
  src/qu8-vlrelu/gen/qu8-vlrelu-wasmsimd-x86-x8.c
  src/qu8-vlrelu/gen/qu8-vlrelu-wasmsimd-x86-x16.c
  src/qu8-vlrelu/gen/qu8-vlrelu-wasmsimd-x86-x32.c
  src/qu8-vmul/gen/qu8-vmul-minmax-fp32-wasmsimd-mul32-ld64-x8.c
  src/qu8-vmul/gen/qu8-vmul-minmax-fp32-wasmsimd-mul32-ld64-x16.c
  src/qu8-vmulc/gen/qu8-vmulc-minmax-fp32-wasmsimd-mul32-ld64-x8.c
  src/qu8-vmulc/gen/qu8-vmulc-minmax-fp32-wasmsimd-mul32-ld64-x16.c
  src/s8-ibilinear/gen/s8-ibilinear-wasmsimd-dot16x2-c8.c
  src/s8-ibilinear/gen/s8-ibilinear-wasmsimd-dot16x2-c16.c
  src/s8-ibilinear/gen/s8-ibilinear-wasmsimd-mul32-c8.c
  src/s8-ibilinear/gen/s8-ibilinear-wasmsimd-mul32-c16.c
  src/s8-maxpool/s8-maxpool-9p8x-minmax-wasmsimd-c16.c
  src/s8-vclamp/s8-vclamp-wasmsimd-x64.c
  src/u8-ibilinear/gen/u8-ibilinear-wasmsimd-dot16x2-c8.c
  src/u8-ibilinear/gen/u8-ibilinear-wasmsimd-dot16x2-c16.c
  src/u8-ibilinear/gen/u8-ibilinear-wasmsimd-mul32-c8.c
  src/u8-ibilinear/gen/u8-ibilinear-wasmsimd-mul32-c16.c
  src/u8-maxpool/u8-maxpool-9p8x-minmax-wasmsimd-c16.c
  src/u8-vclamp/u8-vclamp-wasmsimd-x64.c
  src/x8-lut/gen/x8-lut-wasmsimd-x16.c
  src/x8-lut/gen/x8-lut-wasmsimd-x32.c
  src/x8-lut/gen/x8-lut-wasmsimd-x48.c
  src/x8-lut/gen/x8-lut-wasmsimd-x64.c
  src/x8-transposec/gen/x8-transposec-16x16-reuse-mov-wasmsimd.c
  src/x8-transposec/gen/x8-transposec-16x16-reuse-switch-wasmsimd.c
  src/x16-transposec/gen/x16-transposec-8x8-multi-mov-wasmsimd.c
  src/x16-transposec/gen/x16-transposec-8x8-multi-switch-wasmsimd.c
  src/x16-transposec/gen/x16-transposec-8x8-reuse-mov-wasmsimd.c
  src/x16-transposec/gen/x16-transposec-8x8-reuse-multi-wasmsimd.c
  src/x16-transposec/gen/x16-transposec-8x8-reuse-switch-wasmsimd.c
  src/x32-packw/gen/x32-packw-x2c4-gemm-goi-wasmsimd-x4.c
  src/x32-packw/gen/x32-packw-x8-gemm-goi-wasmsimd-x4.c
  src/x32-packw/gen/x32-packw-x8s4-gemm-goi-wasmsimd-x4.c
  src/x32-packx/x32-packx-4x-wasmsimd.c
  src/x32-transposec/gen/x32-transposec-4x4-multi-mov-wasmsimd.c
  src/x32-transposec/gen/x32-transposec-4x4-multi-multi-wasmsimd.c
  src/x32-transposec/gen/x32-transposec-4x4-multi-switch-wasmsimd.c
  src/x32-transposec/gen/x32-transposec-4x4-reuse-mov-wasmsimd.c
  src/x32-transposec/gen/x32-transposec-4x4-reuse-multi-wasmsimd.c
  src/x32-transposec/gen/x32-transposec-4x4-reuse-switch-wasmsimd.c
  src/x32-unpool/x32-unpool-wasmsimd.c
  src/x32-zip/x32-zip-x2-wasmsimd.c
  src/x32-zip/x32-zip-x3-wasmsimd.c
  src/x32-zip/x32-zip-x4-wasmsimd.c
  src/x32-zip/x32-zip-xm-wasmsimd.c
  src/xx-fill/xx-fill-wasmsimd-x64.c
  src/xx-pad/xx-pad-wasmsimd.c)

SET(ALL_XOP_MICROKERNEL_SRCS
  src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x4c8-minmax-xop-ld64.c
  src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-1x4c8-minmax-xop-ld128.c
  src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x4c8-minmax-xop-ld64.c
  src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-2x4c8-minmax-xop-ld128.c
  src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-3x4c8-minmax-xop-ld64.c
  src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-3x4c8-minmax-xop-ld128.c
  src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-4x4c8-minmax-xop-ld64.c
  src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-4x4c8-minmax-xop-ld128.c
  src/qs8-dwconv/gen/qs8-dwconv-5f5m5l8c4s4r-minmax-fp32-xop-mul32.c
  src/qs8-dwconv/gen/qs8-dwconv-5f5m5l16c4s4r-minmax-fp32-xop-mul32.c
  src/qs8-dwconv/gen/qs8-dwconv-6f6m7l8c4s4r-minmax-fp32-xop-mul32.c
  src/qs8-dwconv/gen/qs8-dwconv-6f6m7l16c4s4r-minmax-fp32-xop-mul32.c
  src/qs8-dwconv/gen/qs8-dwconv-8f8m9l8c4s4r-minmax-fp32-xop-mul32.c
  src/qs8-dwconv/gen/qs8-dwconv-8f8m9l16c4s4r-minmax-fp32-xop-mul32.c
  src/qs8-dwconv/gen/qs8-dwconv-9p8c-minmax-fp32-xop-mul16-add16.c
  src/qs8-dwconv/gen/qs8-dwconv-9p8c-minmax-fp32-xop-mul32.c
  src/qs8-dwconv/gen/qs8-dwconv-9p16c-minmax-fp32-xop-mul16-add16.c
  src/qs8-dwconv/gen/qs8-dwconv-9p16c-minmax-fp32-xop-mul32.c
  src/qs8-dwconv/gen/qs8-dwconv-25p8c-minmax-fp32-xop-mul16-add16.c
  src/qs8-dwconv/gen/qs8-dwconv-25p8c-minmax-fp32-xop-mul32.c
  src/qs8-dwconv/gen/qs8-dwconv-25p16c-minmax-fp32-xop-mul16-add16.c
  src/qs8-dwconv/gen/qs8-dwconv-25p16c-minmax-fp32-xop-mul32.c
  src/qs8-gemm/gen/qs8-gemm-1x4c2-minmax-fp32-xop-ld64.c
  src/qs8-gemm/gen/qs8-gemm-1x4c2-minmax-fp32-xop-ld128.c
  src/qs8-gemm/gen/qs8-gemm-1x4c2-xw-minmax-fp32-xop.c
  src/qs8-gemm/gen/qs8-gemm-1x4c2s4-minmax-fp32-xop-ld64.c
  src/qs8-gemm/gen/qs8-gemm-1x4c2s4-minmax-fp32-xop-ld128.c
  src/qs8-gemm/gen/qs8-gemm-1x4c2s4-xw-minmax-fp32-xop.c
  src/qs8-gemm/gen/qs8-gemm-1x4c8-minmax-fp32-xop-ld64.c
  src/qs8-gemm/gen/qs8-gemm-1x4c8-minmax-fp32-xop-ld128.c
  src/qs8-gemm/gen/qs8-gemm-1x4c8-xw-minmax-fp32-xop.c
  src/qs8-gemm/gen/qs8-gemm-2x4c2-minmax-fp32-xop-ld64.c
  src/qs8-gemm/gen/qs8-gemm-2x4c2-minmax-fp32-xop-ld128.c
  src/qs8-gemm/gen/qs8-gemm-2x4c2-xw-minmax-fp32-xop.c
  src/qs8-gemm/gen/qs8-gemm-2x4c2s4-minmax-fp32-xop-ld64.c
  src/qs8-gemm/gen/qs8-gemm-2x4c2s4-minmax-fp32-xop-ld128.c
  src/qs8-gemm/gen/qs8-gemm-2x4c2s4-xw-minmax-fp32-xop.c
  src/qs8-gemm/gen/qs8-gemm-2x4c8-minmax-fp32-xop-ld64.c
  src/qs8-gemm/gen/qs8-gemm-2x4c8-minmax-fp32-xop-ld128.c
  src/qs8-gemm/gen/qs8-gemm-2x4c8-xw-minmax-fp32-xop.c
  src/qs8-gemm/gen/qs8-gemm-3x4c2-minmax-fp32-xop-ld64.c
  src/qs8-gemm/gen/qs8-gemm-3x4c2-minmax-fp32-xop-ld128.c
  src/qs8-gemm/gen/qs8-gemm-3x4c2-xw-minmax-fp32-xop.c
  src/qs8-gemm/gen/qs8-gemm-3x4c2s4-minmax-fp32-xop-ld64.c
  src/qs8-gemm/gen/qs8-gemm-3x4c2s4-minmax-fp32-xop-ld128.c
  src/qs8-gemm/gen/qs8-gemm-3x4c2s4-xw-minmax-fp32-xop.c
  src/qs8-gemm/gen/qs8-gemm-3x4c8-minmax-fp32-xop-ld64.c
  src/qs8-gemm/gen/qs8-gemm-3x4c8-minmax-fp32-xop-ld128.c
  src/qs8-gemm/gen/qs8-gemm-3x4c8-xw-minmax-fp32-xop.c
  src/qs8-gemm/gen/qs8-gemm-4x4c2-minmax-fp32-xop-ld64.c
  src/qs8-gemm/gen/qs8-gemm-4x4c2-minmax-fp32-xop-ld128.c
  src/qs8-gemm/gen/qs8-gemm-4x4c2-xw-minmax-fp32-xop.c
  src/qs8-gemm/gen/qs8-gemm-4x4c2s4-minmax-fp32-xop-ld64.c
  src/qs8-gemm/gen/qs8-gemm-4x4c2s4-minmax-fp32-xop-ld128.c
  src/qs8-gemm/gen/qs8-gemm-4x4c2s4-xw-minmax-fp32-xop.c
  src/qs8-igemm/gen/qs8-igemm-1x4c2-minmax-fp32-xop-ld64.c
  src/qs8-igemm/gen/qs8-igemm-1x4c2-minmax-fp32-xop-ld128.c
  src/qs8-igemm/gen/qs8-igemm-1x4c2s4-minmax-fp32-xop-ld64.c
  src/qs8-igemm/gen/qs8-igemm-1x4c2s4-minmax-fp32-xop-ld128.c
  src/qs8-igemm/gen/qs8-igemm-1x4c8-minmax-fp32-xop-ld64.c
  src/qs8-igemm/gen/qs8-igemm-1x4c8-minmax-fp32-xop-ld128.c
  src/qs8-igemm/gen/qs8-igemm-2x4c2-minmax-fp32-xop-ld64.c
  src/qs8-igemm/gen/qs8-igemm-2x4c2-minmax-fp32-xop-ld128.c
  src/qs8-igemm/gen/qs8-igemm-2x4c2s4-minmax-fp32-xop-ld64.c
  src/qs8-igemm/gen/qs8-igemm-2x4c2s4-minmax-fp32-xop-ld128.c
  src/qs8-igemm/gen/qs8-igemm-2x4c8-minmax-fp32-xop-ld64.c
  src/qs8-igemm/gen/qs8-igemm-2x4c8-minmax-fp32-xop-ld128.c
  src/qs8-igemm/gen/qs8-igemm-3x4c2-minmax-fp32-xop-ld64.c
  src/qs8-igemm/gen/qs8-igemm-3x4c2-minmax-fp32-xop-ld128.c
  src/qs8-igemm/gen/qs8-igemm-3x4c2s4-minmax-fp32-xop-ld64.c
  src/qs8-igemm/gen/qs8-igemm-3x4c2s4-minmax-fp32-xop-ld128.c
  src/qs8-igemm/gen/qs8-igemm-3x4c8-minmax-fp32-xop-ld64.c
  src/qs8-igemm/gen/qs8-igemm-3x4c8-minmax-fp32-xop-ld128.c
  src/qs8-igemm/gen/qs8-igemm-4x4c2-minmax-fp32-xop-ld64.c
  src/qs8-igemm/gen/qs8-igemm-4x4c2-minmax-fp32-xop-ld128.c
  src/qs8-igemm/gen/qs8-igemm-4x4c2s4-minmax-fp32-xop-ld64.c
  src/qs8-igemm/gen/qs8-igemm-4x4c2s4-minmax-fp32-xop-ld128.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-3p16c-minmax-fp32-xop-mul16-add16.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l8c4s4r-minmax-fp32-xop-mul32.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-5f5m5l16c4s4r-minmax-fp32-xop-mul32.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l8c4s4r-minmax-fp32-xop-mul32.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-6f6m7l16c4s4r-minmax-fp32-xop-mul32.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l8c4s4r-minmax-fp32-xop-mul32.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-8f8m9l16c4s4r-minmax-fp32-xop-mul32.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p8c-minmax-fp32-xop-mul16-add16.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p8c-minmax-fp32-xop-mul32.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-xop-mul16-add16.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-9p16c-minmax-fp32-xop-mul32.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p8c-minmax-fp32-xop-mul16-add16.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p8c-minmax-fp32-xop-mul32.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-xop-mul16-add16.c
  src/qs8-qc8w-dwconv/gen/qs8-qc8w-dwconv-25p16c-minmax-fp32-xop-mul32.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c2-minmax-fp32-xop-ld64.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c2-minmax-fp32-xop-ld128.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c2s4-minmax-fp32-xop-ld64.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c2s4-minmax-fp32-xop-ld128.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c8-minmax-fp32-xop-ld64.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x4c8-minmax-fp32-xop-ld128.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c2-minmax-fp32-xop-ld64.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c2-minmax-fp32-xop-ld128.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c2s4-minmax-fp32-xop-ld64.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c2s4-minmax-fp32-xop-ld128.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c8-minmax-fp32-xop-ld64.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x4c8-minmax-fp32-xop-ld128.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c2-minmax-fp32-xop-ld64.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c2-minmax-fp32-xop-ld128.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c2s4-minmax-fp32-xop-ld64.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c2s4-minmax-fp32-xop-ld128.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c8-minmax-fp32-xop-ld64.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-3x4c8-minmax-fp32-xop-ld128.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4c2-minmax-fp32-xop-ld64.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4c2-minmax-fp32-xop-ld128.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4c2s4-minmax-fp32-xop-ld64.c
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x4c2s4-minmax-fp32-xop-ld128.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c2-minmax-fp32-xop-ld64.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c2-minmax-fp32-xop-ld128.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c2s4-minmax-fp32-xop-ld64.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c2s4-minmax-fp32-xop-ld128.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c8-minmax-fp32-xop-ld64.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x4c8-minmax-fp32-xop-ld128.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c2-minmax-fp32-xop-ld64.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c2-minmax-fp32-xop-ld128.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c2s4-minmax-fp32-xop-ld64.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c2s4-minmax-fp32-xop-ld128.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c8-minmax-fp32-xop-ld64.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x4c8-minmax-fp32-xop-ld128.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c2-minmax-fp32-xop-ld64.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c2-minmax-fp32-xop-ld128.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c2s4-minmax-fp32-xop-ld64.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c2s4-minmax-fp32-xop-ld128.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c8-minmax-fp32-xop-ld64.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-3x4c8-minmax-fp32-xop-ld128.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c2-minmax-fp32-xop-ld64.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c2-minmax-fp32-xop-ld128.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c2s4-minmax-fp32-xop-ld64.c
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x4c2s4-minmax-fp32-xop-ld128.c
  src/qs8-vadd/gen/qs8-vadd-minmax-xop-mul32-ld32-x8.c
  src/qs8-vadd/gen/qs8-vadd-minmax-xop-mul32-ld32-x16.c
  src/qs8-vadd/gen/qs8-vadd-minmax-xop-mul32-ld32-x24.c
  src/qs8-vadd/gen/qs8-vadd-minmax-xop-mul32-ld32-x32.c
  src/qs8-vaddc/gen/qs8-vaddc-minmax-xop-mul32-ld32-x8.c
  src/qs8-vaddc/gen/qs8-vaddc-minmax-xop-mul32-ld32-x16.c
  src/qs8-vaddc/gen/qs8-vaddc-minmax-xop-mul32-ld32-x24.c
  src/qs8-vaddc/gen/qs8-vaddc-minmax-xop-mul32-ld32-x32.c
  src/qu8-dwconv/gen/qu8-dwconv-5f5m5l8c4s4r-minmax-fp32-xop-mul32.c
  src/qu8-dwconv/gen/qu8-dwconv-5f5m5l16c4s4r-minmax-fp32-xop-mul32.c
  src/qu8-dwconv/gen/qu8-dwconv-6f6m7l8c4s4r-minmax-fp32-xop-mul32.c
  src/qu8-dwconv/gen/qu8-dwconv-6f6m7l16c4s4r-minmax-fp32-xop-mul32.c
  src/qu8-dwconv/gen/qu8-dwconv-8f8m9l8c4s4r-minmax-fp32-xop-mul32.c
  src/qu8-dwconv/gen/qu8-dwconv-8f8m9l16c4s4r-minmax-fp32-xop-mul32.c
  src/qu8-dwconv/gen/qu8-dwconv-9p8c-minmax-fp32-xop-mul32.c
  src/qu8-dwconv/gen/qu8-dwconv-9p16c-minmax-fp32-xop-mul32.c
  src/qu8-dwconv/gen/qu8-dwconv-25p8c-minmax-fp32-xop-mul32.c
  src/qu8-dwconv/gen/qu8-dwconv-25p16c-minmax-fp32-xop-mul32.c
  src/qu8-gemm/gen/qu8-gemm-1x4c2-minmax-fp32-xop-ld64.c
  src/qu8-gemm/gen/qu8-gemm-1x4c2-minmax-fp32-xop-ld128.c
  src/qu8-gemm/gen/qu8-gemm-1x4c2s4-minmax-fp32-xop-ld64.c
  src/qu8-gemm/gen/qu8-gemm-1x4c2s4-minmax-fp32-xop-ld128.c
  src/qu8-gemm/gen/qu8-gemm-1x4c8-minmax-fp32-xop-ld64.c
  src/qu8-gemm/gen/qu8-gemm-1x4c8-minmax-fp32-xop-ld128.c
  src/qu8-gemm/gen/qu8-gemm-2x4c2-minmax-fp32-xop-ld64.c
  src/qu8-gemm/gen/qu8-gemm-2x4c2-minmax-fp32-xop-ld128.c
  src/qu8-gemm/gen/qu8-gemm-2x4c2s4-minmax-fp32-xop-ld64.c
  src/qu8-gemm/gen/qu8-gemm-2x4c2s4-minmax-fp32-xop-ld128.c
  src/qu8-gemm/gen/qu8-gemm-2x4c8-minmax-fp32-xop-ld64.c
  src/qu8-gemm/gen/qu8-gemm-2x4c8-minmax-fp32-xop-ld128.c
  src/qu8-gemm/gen/qu8-gemm-3x4c2-minmax-fp32-xop-ld64.c
  src/qu8-gemm/gen/qu8-gemm-3x4c2-minmax-fp32-xop-ld128.c
  src/qu8-gemm/gen/qu8-gemm-3x4c2s4-minmax-fp32-xop-ld64.c
  src/qu8-gemm/gen/qu8-gemm-3x4c2s4-minmax-fp32-xop-ld128.c
  src/qu8-gemm/gen/qu8-gemm-3x4c8-minmax-fp32-xop-ld64.c
  src/qu8-gemm/gen/qu8-gemm-3x4c8-minmax-fp32-xop-ld128.c
  src/qu8-gemm/gen/qu8-gemm-4x4c2-minmax-fp32-xop-ld64.c
  src/qu8-gemm/gen/qu8-gemm-4x4c2-minmax-fp32-xop-ld128.c
  src/qu8-gemm/gen/qu8-gemm-4x4c2s4-minmax-fp32-xop-ld64.c
  src/qu8-gemm/gen/qu8-gemm-4x4c2s4-minmax-fp32-xop-ld128.c
  src/qu8-igemm/gen/qu8-igemm-1x4c2-minmax-fp32-xop-ld64.c
  src/qu8-igemm/gen/qu8-igemm-1x4c2-minmax-fp32-xop-ld128.c
  src/qu8-igemm/gen/qu8-igemm-1x4c2s4-minmax-fp32-xop-ld64.c
  src/qu8-igemm/gen/qu8-igemm-1x4c2s4-minmax-fp32-xop-ld128.c
  src/qu8-igemm/gen/qu8-igemm-1x4c8-minmax-fp32-xop-ld64.c
  src/qu8-igemm/gen/qu8-igemm-1x4c8-minmax-fp32-xop-ld128.c
  src/qu8-igemm/gen/qu8-igemm-2x4c2-minmax-fp32-xop-ld64.c
  src/qu8-igemm/gen/qu8-igemm-2x4c2-minmax-fp32-xop-ld128.c
  src/qu8-igemm/gen/qu8-igemm-2x4c2s4-minmax-fp32-xop-ld64.c
  src/qu8-igemm/gen/qu8-igemm-2x4c2s4-minmax-fp32-xop-ld128.c
  src/qu8-igemm/gen/qu8-igemm-2x4c8-minmax-fp32-xop-ld64.c
  src/qu8-igemm/gen/qu8-igemm-2x4c8-minmax-fp32-xop-ld128.c
  src/qu8-igemm/gen/qu8-igemm-3x4c2-minmax-fp32-xop-ld64.c
  src/qu8-igemm/gen/qu8-igemm-3x4c2-minmax-fp32-xop-ld128.c
  src/qu8-igemm/gen/qu8-igemm-3x4c2s4-minmax-fp32-xop-ld64.c
  src/qu8-igemm/gen/qu8-igemm-3x4c2s4-minmax-fp32-xop-ld128.c
  src/qu8-igemm/gen/qu8-igemm-3x4c8-minmax-fp32-xop-ld64.c
  src/qu8-igemm/gen/qu8-igemm-3x4c8-minmax-fp32-xop-ld128.c
  src/qu8-igemm/gen/qu8-igemm-4x4c2-minmax-fp32-xop-ld64.c
  src/qu8-igemm/gen/qu8-igemm-4x4c2-minmax-fp32-xop-ld128.c
  src/qu8-igemm/gen/qu8-igemm-4x4c2s4-minmax-fp32-xop-ld64.c
  src/qu8-igemm/gen/qu8-igemm-4x4c2s4-minmax-fp32-xop-ld128.c
  src/qu8-vadd/gen/qu8-vadd-minmax-xop-mul32-ld32-x8.c
  src/qu8-vadd/gen/qu8-vadd-minmax-xop-mul32-ld32-x16.c
  src/qu8-vaddc/gen/qu8-vaddc-minmax-xop-mul32-ld32-x8.c
  src/qu8-vaddc/gen/qu8-vaddc-minmax-xop-mul32-ld32-x16.c)

SET(AARCH32_ASM_MICROKERNEL_SRCS
  src/cs16-bfly4/cs16-bfly4-samples1-asm-aarch32-neon-x1.S
  src/cs16-bfly4/cs16-bfly4-samples1-asm-aarch32-neon-x2.S
  src/cs16-bfly4/cs16-bfly4-samples1-asm-aarch32-neon-x4.S
  src/cs16-fftr/cs16-fftr-asm-aarch32-neon-x1.S
  src/cs16-fftr/cs16-fftr-asm-aarch32-neon-x4.S
  src/f32-gemm/gen/f32-gemm-1x8-minmax-asm-aarch32-neon-cortex-a53-prfm.S
  src/f32-gemm/gen/f32-gemm-1x8-minmax-asm-aarch32-neon-cortex-a53.S
  src/f32-gemm/gen/f32-gemm-4x4-asm-aarch32-vfp-ld64.S
  src/f32-gemm/gen/f32-gemm-4x4-minmax-asm-aarch32-vfp-ld64.S
  src/f32-gemm/gen/f32-gemm-4x8-minmax-asm-aarch32-neon-cortex-a7.S
  src/f32-gemm/gen/f32-gemm-4x8-minmax-asm-aarch32-neon-cortex-a53-prfm.S
  src/f32-gemm/gen/f32-gemm-4x8-minmax-asm-aarch32-neon-cortex-a53.S
  src/f32-gemm/gen/f32-gemm-4x8-minmax-asm-aarch32-neon-cortex-a55.S
  src/f32-gemm/gen/f32-gemm-4x8-minmax-asm-aarch32-neon-cortex-a75-prfm.S
  src/f32-gemm/gen/f32-gemm-4x8-minmax-asm-aarch32-neon-cortex-a75.S
  src/f32-gemm/gen/f32-gemm-4x8-minmax-asm-aarch32-neon-ld64.S
  src/f32-igemm/f32-igemm-4x8-minmax-asm-aarch32-neon-cortex-a55.S
  src/f32-igemm/gen/f32-igemm-1x8-minmax-asm-aarch32-neon-cortex-a53-prfm.S
  src/f32-igemm/gen/f32-igemm-1x8-minmax-asm-aarch32-neon-cortex-a53.S
  src/f32-igemm/gen/f32-igemm-4x8-minmax-asm-aarch32-neon-cortex-a7.S
  src/f32-igemm/gen/f32-igemm-4x8-minmax-asm-aarch32-neon-cortex-a53-prfm.S
  src/f32-igemm/gen/f32-igemm-4x8-minmax-asm-aarch32-neon-cortex-a53.S
  src/f32-igemm/gen/f32-igemm-4x8-minmax-asm-aarch32-neon-cortex-a75-prfm.S
  src/f32-igemm/gen/f32-igemm-4x8-minmax-asm-aarch32-neon-cortex-a75.S
  src/f32-igemm/gen/f32-igemm-4x8-minmax-asm-aarch32-neon-ld64.S
  src/qd8-f32-qc8w-gemm/gen/qd8-f32-qc8w-gemm-4x8c4-minmax-asm-aarch32-neondot-cortex-a55.S
  src/qs8-gemm/gen/qs8-gemm-1x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-cortex-a7-prfm.S
  src/qs8-gemm/gen/qs8-gemm-1x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-cortex-a7.S
  src/qs8-gemm/gen/qs8-gemm-4x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-cortex-a7-prfm.S
  src/qs8-gemm/gen/qs8-gemm-4x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-cortex-a7.S
  src/qs8-gemm/gen/qs8-gemm-4x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-cortex-a53-prfm.S
  src/qs8-gemm/gen/qs8-gemm-4x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-cortex-a53.S
  src/qs8-gemm/gen/qs8-gemm-4x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-ld64-prfm.S
  src/qs8-gemm/gen/qs8-gemm-4x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-ld64.S
  src/qs8-gemm/gen/qs8-gemm-4x8c4-minmax-rndnu-asm-aarch32-neondot-cortex-a55.S
  src/qs8-gemm/gen/qs8-gemm-4x8c4-minmax-rndnu-asm-aarch32-neondot-ld64.S
  src/qs8-igemm/gen/qs8-igemm-1x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-cortex-a7-prfm.S
  src/qs8-igemm/gen/qs8-igemm-1x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-cortex-a7.S
  src/qs8-igemm/gen/qs8-igemm-4x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-cortex-a7-prfm.S
  src/qs8-igemm/gen/qs8-igemm-4x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-cortex-a7.S
  src/qs8-igemm/gen/qs8-igemm-4x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-cortex-a53-prfm.S
  src/qs8-igemm/gen/qs8-igemm-4x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-cortex-a53.S
  src/qs8-igemm/gen/qs8-igemm-4x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-ld64-prfm.S
  src/qs8-igemm/gen/qs8-igemm-4x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-ld64.S
  src/qs8-igemm/gen/qs8-igemm-4x8c4-minmax-rndnu-asm-aarch32-neondot-cortex-a55.S
  src/qs8-igemm/gen/qs8-igemm-4x8c4-minmax-rndnu-asm-aarch32-neondot-ld64.S
  src/qs8-qc8w-dwconv/qs8-qc8w-dwconv-3p8c-minmax-fp32-asm-aarch32-neonv8-mla8-cortex-a35.S
  src/qs8-qc8w-dwconv/qs8-qc8w-dwconv-3p16c-minmax-fp32-asm-aarch32-neonv8-mla8-cortex-a35.S
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8-minmax-fp32-asm-aarch32-neon-mlal-lane-cortex-a7-prfm.S
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8-minmax-fp32-asm-aarch32-neon-mlal-lane-cortex-a7.S
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8-minmax-fp32-asm-aarch32-neonv8-mlal-lane-cortex-a35-prfm.S
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8-minmax-fp32-asm-aarch32-neonv8-mlal-lane-cortex-a35.S
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x8-minmax-fp32-asm-aarch32-neon-mlal-lane-cortex-a7-prfm.S
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x8-minmax-fp32-asm-aarch32-neon-mlal-lane-cortex-a7.S
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x8-minmax-fp32-asm-aarch32-neon-mlal-lane-cortex-a53-prfm.S
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x8-minmax-fp32-asm-aarch32-neon-mlal-lane-cortex-a53.S
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x8-minmax-fp32-asm-aarch32-neon-mlal-lane-ld64-prfm.S
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x8-minmax-fp32-asm-aarch32-neon-mlal-lane-ld64.S
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x8-minmax-fp32-asm-aarch32-neonv8-mlal-lane-cortex-a35-prfm.S
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x8-minmax-fp32-asm-aarch32-neonv8-mlal-lane-cortex-a35.S
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x8-minmax-fp32-asm-aarch32-neonv8-mlal-lane-cortex-a53-prfm.S
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x8-minmax-fp32-asm-aarch32-neonv8-mlal-lane-cortex-a53.S
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x8-minmax-fp32-asm-aarch32-neonv8-mlal-lane-ld64-prfm.S
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x8-minmax-fp32-asm-aarch32-neonv8-mlal-lane-ld64.S
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x8c4-minmax-fp32-asm-aarch32-neondot-cortex-a55.S
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x8c4-minmax-fp32-asm-aarch32-neondot-ld64.S
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8-minmax-fp32-asm-aarch32-neon-mlal-lane-cortex-a7-prfm.S
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8-minmax-fp32-asm-aarch32-neon-mlal-lane-cortex-a7.S
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8-minmax-fp32-asm-aarch32-neonv8-mlal-lane-cortex-a35-prfm.S
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8-minmax-fp32-asm-aarch32-neonv8-mlal-lane-cortex-a35.S
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x8-minmax-fp32-asm-aarch32-neon-mlal-lane-cortex-a7-prfm.S
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x8-minmax-fp32-asm-aarch32-neon-mlal-lane-cortex-a7.S
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x8-minmax-fp32-asm-aarch32-neon-mlal-lane-cortex-a53-prfm.S
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x8-minmax-fp32-asm-aarch32-neon-mlal-lane-cortex-a53.S
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x8-minmax-fp32-asm-aarch32-neon-mlal-lane-ld64-prfm.S
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x8-minmax-fp32-asm-aarch32-neon-mlal-lane-ld64.S
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x8-minmax-fp32-asm-aarch32-neonv8-mlal-lane-cortex-a35-prfm.S
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x8-minmax-fp32-asm-aarch32-neonv8-mlal-lane-cortex-a35.S
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x8-minmax-fp32-asm-aarch32-neonv8-mlal-lane-cortex-a53-prfm.S
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x8-minmax-fp32-asm-aarch32-neonv8-mlal-lane-cortex-a53.S
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x8-minmax-fp32-asm-aarch32-neonv8-mlal-lane-ld64-prfm.S
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x8-minmax-fp32-asm-aarch32-neonv8-mlal-lane-ld64.S
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x8c4-minmax-fp32-asm-aarch32-neondot-cortex-a55.S
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x8c4-minmax-fp32-asm-aarch32-neondot-ld64.S
  src/qs16-qs8-vcvt/qs16-qs8-vcvt-asm-aarch32-neon-x16.S
  src/qu8-gemm/gen/qu8-gemm-1x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-cortex-a7-prfm.S
  src/qu8-gemm/gen/qu8-gemm-1x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-cortex-a7.S
  src/qu8-gemm/gen/qu8-gemm-4x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-cortex-a7-prfm.S
  src/qu8-gemm/gen/qu8-gemm-4x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-cortex-a7.S
  src/qu8-gemm/gen/qu8-gemm-4x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-cortex-a53-prfm.S
  src/qu8-gemm/gen/qu8-gemm-4x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-cortex-a53.S
  src/qu8-gemm/gen/qu8-gemm-4x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-ld64-prfm.S
  src/qu8-gemm/gen/qu8-gemm-4x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-ld64.S
  src/qu8-igemm/gen/qu8-igemm-1x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-cortex-a7-prfm.S
  src/qu8-igemm/gen/qu8-igemm-1x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-cortex-a7.S
  src/qu8-igemm/gen/qu8-igemm-4x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-cortex-a7-prfm.S
  src/qu8-igemm/gen/qu8-igemm-4x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-cortex-a7.S
  src/qu8-igemm/gen/qu8-igemm-4x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-cortex-a53-prfm.S
  src/qu8-igemm/gen/qu8-igemm-4x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-cortex-a53.S
  src/qu8-igemm/gen/qu8-igemm-4x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-ld64-prfm.S
  src/qu8-igemm/gen/qu8-igemm-4x8-minmax-rndnu-asm-aarch32-neon-mlal-lane-ld64.S
  src/u32-filterbank-accumulate/u32-filterbank-accumulate-asm-aarch32-arm-x1.S
  src/u32-filterbank-accumulate/u32-filterbank-accumulate-asm-aarch32-neon-x1.S
  src/u32-filterbank-accumulate/u32-filterbank-accumulate-asm-aarch32-neon-x2.S)

SET(AARCH64_ASM_MICROKERNEL_SRCS
  src/f16-gemm/gen/f16-gemm-1x8-minmax-asm-aarch64-neonfp16arith-ld64.S
  src/f16-gemm/gen/f16-gemm-1x16-minmax-asm-aarch64-neonfp16arith-ld32.S
  src/f16-gemm/gen/f16-gemm-1x16-minmax-asm-aarch64-neonfp16arith-ld64.S
  src/f16-gemm/gen/f16-gemm-4x8-minmax-asm-aarch64-neonfp16arith-ld64.S
  src/f16-gemm/gen/f16-gemm-4x16-minmax-asm-aarch64-neonfp16arith-ld32.S
  src/f16-gemm/gen/f16-gemm-4x16-minmax-asm-aarch64-neonfp16arith-ld64.S
  src/f16-gemm/gen/f16-gemm-6x8-minmax-asm-aarch64-neonfp16arith-ld64.S
  src/f16-gemm/gen/f16-gemm-6x16-minmax-asm-aarch64-neonfp16arith-cortex-a55.S
  src/f16-gemm/gen/f16-gemm-6x16-minmax-asm-aarch64-neonfp16arith-cortex-a55r0.S
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  src/qs8-gemm/gen/qs8-gemm-1x8c8-minmax-fp32-asm-aarch64-neon-mlal-cortex-a53.S
  src/qs8-gemm/gen/qs8-gemm-1x8c8-minmax-fp32-asm-aarch64-neon-mlal-prfm.S
  src/qs8-gemm/gen/qs8-gemm-1x8c8-minmax-fp32-asm-aarch64-neon-mlal.S
  src/qs8-gemm/gen/qs8-gemm-1x8c8-minmax-rndnu-asm-aarch64-neon-mlal-cortex-a53-prfm.S
  src/qs8-gemm/gen/qs8-gemm-1x8c8-minmax-rndnu-asm-aarch64-neon-mlal-cortex-a53.S
  src/qs8-gemm/gen/qs8-gemm-1x8c8-minmax-rndnu-asm-aarch64-neon-mlal-prfm.S
  src/qs8-gemm/gen/qs8-gemm-1x8c8-minmax-rndnu-asm-aarch64-neon-mlal.S
  src/qs8-gemm/gen/qs8-gemm-1x16c4-minmax-fp32-asm-aarch64-neondot-ld32.S
  src/qs8-gemm/gen/qs8-gemm-1x16c4-minmax-fp32-asm-aarch64-neondot-ld64.S
  src/qs8-gemm/gen/qs8-gemm-1x16c4-minmax-rndnu-asm-aarch64-neondot-ld32.S
  src/qs8-gemm/gen/qs8-gemm-1x16c4-minmax-rndnu-asm-aarch64-neondot-ld64.S
  src/qs8-gemm/gen/qs8-gemm-2x8c8-minmax-fp32-asm-aarch64-neon-mlal-cortex-a53-prfm.S
  src/qs8-gemm/gen/qs8-gemm-2x8c8-minmax-fp32-asm-aarch64-neon-mlal-cortex-a53.S
  src/qs8-gemm/gen/qs8-gemm-2x8c8-minmax-fp32-asm-aarch64-neon-mlal-prfm.S
  src/qs8-gemm/gen/qs8-gemm-2x8c8-minmax-fp32-asm-aarch64-neon-mlal.S
  src/qs8-gemm/gen/qs8-gemm-2x8c8-minmax-fp32-asm-aarch64-neon-mull.S
  src/qs8-gemm/gen/qs8-gemm-2x8c8-minmax-rndnu-asm-aarch64-neon-mlal-cortex-a53-prfm.S
  src/qs8-gemm/gen/qs8-gemm-2x8c8-minmax-rndnu-asm-aarch64-neon-mlal-cortex-a53.S
  src/qs8-gemm/gen/qs8-gemm-2x8c8-minmax-rndnu-asm-aarch64-neon-mlal-prfm.S
  src/qs8-gemm/gen/qs8-gemm-2x8c8-minmax-rndnu-asm-aarch64-neon-mlal.S
  src/qs8-gemm/gen/qs8-gemm-2x8c8-minmax-rndnu-asm-aarch64-neon-mull.S
  src/qs8-gemm/gen/qs8-gemm-2x8c16-minmax-fp32-asm-aarch64-neon-mlal.S
  src/qs8-gemm/gen/qs8-gemm-2x8c16-minmax-rndnu-asm-aarch64-neon-mlal.S
  src/qs8-gemm/gen/qs8-gemm-4x8-minmax-rndnu-asm-aarch64-neon-mlal-lane-ld64-prfm.S
  src/qs8-gemm/gen/qs8-gemm-4x8-minmax-rndnu-asm-aarch64-neon-mlal-lane-ld64.S
  src/qs8-gemm/gen/qs8-gemm-4x16-minmax-fp32-asm-aarch64-neon-mlal-lane-cortex-a53-prfm.S
  src/qs8-gemm/gen/qs8-gemm-4x16-minmax-fp32-asm-aarch64-neon-mlal-lane-cortex-a53.S
  src/qs8-gemm/gen/qs8-gemm-4x16-minmax-fp32-asm-aarch64-neon-mlal-lane-ld64-prfm.S
  src/qs8-gemm/gen/qs8-gemm-4x16-minmax-fp32-asm-aarch64-neon-mlal-lane-ld64.S
  src/qs8-gemm/gen/qs8-gemm-4x16-minmax-rndnu-asm-aarch64-neon-mlal-lane-cortex-a53-prfm.S
  src/qs8-gemm/gen/qs8-gemm-4x16-minmax-rndnu-asm-aarch64-neon-mlal-lane-cortex-a53.S
  src/qs8-gemm/gen/qs8-gemm-4x16-minmax-rndnu-asm-aarch64-neon-mlal-lane-ld64-prfm.S
  src/qs8-gemm/gen/qs8-gemm-4x16-minmax-rndnu-asm-aarch64-neon-mlal-lane-ld64.S
  src/qs8-gemm/gen/qs8-gemm-4x16c4-minmax-fp32-asm-aarch64-neondot-cortex-a55.S
  src/qs8-gemm/gen/qs8-gemm-4x16c4-minmax-fp32-asm-aarch64-neondot-ld32.S
  src/qs8-gemm/gen/qs8-gemm-4x16c4-minmax-fp32-asm-aarch64-neondot-ld64.S
  src/qs8-gemm/gen/qs8-gemm-4x16c4-minmax-fp32-asm-aarch64-neondot-ld128.S
  src/qs8-gemm/gen/qs8-gemm-4x16c4-minmax-rndnu-asm-aarch64-neondot-cortex-a55.S
  src/qs8-gemm/gen/qs8-gemm-4x16c4-minmax-rndnu-asm-aarch64-neondot-ld32.S
  src/qs8-gemm/gen/qs8-gemm-4x16c4-minmax-rndnu-asm-aarch64-neondot-ld64.S
  src/qs8-gemm/gen/qs8-gemm-4x16c4-minmax-rndnu-asm-aarch64-neondot-ld128.S
  src/qs8-igemm/gen/qs8-igemm-1x8c8-minmax-fp32-asm-aarch64-neon-mlal-cortex-a53-prfm.S
  src/qs8-igemm/gen/qs8-igemm-1x8c8-minmax-fp32-asm-aarch64-neon-mlal-cortex-a53.S
  src/qs8-igemm/gen/qs8-igemm-1x8c8-minmax-fp32-asm-aarch64-neon-mlal-prfm.S
  src/qs8-igemm/gen/qs8-igemm-1x8c8-minmax-fp32-asm-aarch64-neon-mlal.S
  src/qs8-igemm/gen/qs8-igemm-1x8c8-minmax-rndnu-asm-aarch64-neon-mlal-cortex-a53-prfm.S
  src/qs8-igemm/gen/qs8-igemm-1x8c8-minmax-rndnu-asm-aarch64-neon-mlal-cortex-a53.S
  src/qs8-igemm/gen/qs8-igemm-1x8c8-minmax-rndnu-asm-aarch64-neon-mlal-prfm.S
  src/qs8-igemm/gen/qs8-igemm-1x8c8-minmax-rndnu-asm-aarch64-neon-mlal.S
  src/qs8-igemm/gen/qs8-igemm-2x8c8-minmax-fp32-asm-aarch64-neon-mlal-cortex-a53-prfm.S
  src/qs8-igemm/gen/qs8-igemm-2x8c8-minmax-fp32-asm-aarch64-neon-mlal-cortex-a53.S
  src/qs8-igemm/gen/qs8-igemm-2x8c8-minmax-fp32-asm-aarch64-neon-mlal-prfm.S
  src/qs8-igemm/gen/qs8-igemm-2x8c8-minmax-fp32-asm-aarch64-neon-mlal.S
  src/qs8-igemm/gen/qs8-igemm-2x8c8-minmax-rndnu-asm-aarch64-neon-mlal-cortex-a53-prfm.S
  src/qs8-igemm/gen/qs8-igemm-2x8c8-minmax-rndnu-asm-aarch64-neon-mlal-cortex-a53.S
  src/qs8-igemm/gen/qs8-igemm-2x8c8-minmax-rndnu-asm-aarch64-neon-mlal-prfm.S
  src/qs8-igemm/gen/qs8-igemm-2x8c8-minmax-rndnu-asm-aarch64-neon-mlal.S
  src/qs8-igemm/gen/qs8-igemm-2x8c16-minmax-fp32-asm-aarch64-neon-mlal.S
  src/qs8-igemm/gen/qs8-igemm-2x8c16-minmax-rndnu-asm-aarch64-neon-mlal.S
  src/qs8-igemm/gen/qs8-igemm-4x8-minmax-rndnu-asm-aarch64-neon-mlal-lane-ld64-prfm.S
  src/qs8-igemm/gen/qs8-igemm-4x8-minmax-rndnu-asm-aarch64-neon-mlal-lane-ld64.S
  src/qs8-igemm/gen/qs8-igemm-4x16-minmax-fp32-asm-aarch64-neon-mlal-lane-cortex-a53-prfm.S
  src/qs8-igemm/gen/qs8-igemm-4x16-minmax-fp32-asm-aarch64-neon-mlal-lane-cortex-a53.S
  src/qs8-igemm/gen/qs8-igemm-4x16-minmax-fp32-asm-aarch64-neon-mlal-lane-ld64-prfm.S
  src/qs8-igemm/gen/qs8-igemm-4x16-minmax-fp32-asm-aarch64-neon-mlal-lane-ld64.S
  src/qs8-igemm/gen/qs8-igemm-4x16-minmax-rndnu-asm-aarch64-neon-mlal-lane-cortex-a53-prfm.S
  src/qs8-igemm/gen/qs8-igemm-4x16-minmax-rndnu-asm-aarch64-neon-mlal-lane-cortex-a53.S
  src/qs8-igemm/gen/qs8-igemm-4x16-minmax-rndnu-asm-aarch64-neon-mlal-lane-ld64-prfm.S
  src/qs8-igemm/gen/qs8-igemm-4x16-minmax-rndnu-asm-aarch64-neon-mlal-lane-ld64.S
  src/qs8-igemm/gen/qs8-igemm-4x16c4-minmax-fp32-asm-aarch64-neondot-cortex-a55.S
  src/qs8-igemm/gen/qs8-igemm-4x16c4-minmax-fp32-asm-aarch64-neondot-ld64.S
  src/qs8-igemm/gen/qs8-igemm-4x16c4-minmax-fp32-asm-aarch64-neondot-ld128.S
  src/qs8-igemm/gen/qs8-igemm-4x16c4-minmax-rndnu-asm-aarch64-neondot-cortex-a55.S
  src/qs8-igemm/gen/qs8-igemm-4x16c4-minmax-rndnu-asm-aarch64-neondot-ld64.S
  src/qs8-igemm/gen/qs8-igemm-4x16c4-minmax-rndnu-asm-aarch64-neondot-ld128.S
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8c8-minmax-fp32-asm-aarch64-neon-mlal-cortex-a53-prfm.S
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8c8-minmax-fp32-asm-aarch64-neon-mlal-cortex-a53.S
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8c8-minmax-fp32-asm-aarch64-neon-mlal-prfm.S
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x8c8-minmax-fp32-asm-aarch64-neon-mlal.S
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x16c4-minmax-fp32-asm-aarch64-neondot-ld32.S
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-1x16c4-minmax-fp32-asm-aarch64-neondot-ld64.S
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8c8-minmax-fp32-asm-aarch64-neon-mlal-cortex-a53-prfm.S
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8c8-minmax-fp32-asm-aarch64-neon-mlal-cortex-a53.S
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8c8-minmax-fp32-asm-aarch64-neon-mlal-prfm.S
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8c8-minmax-fp32-asm-aarch64-neon-mlal.S
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8c8-minmax-fp32-asm-aarch64-neon-mull.S
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-2x8c16-minmax-fp32-asm-aarch64-neon-mlal.S
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x16-minmax-fp32-asm-aarch64-neon-mlal-lane-cortex-a53-prfm.S
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x16-minmax-fp32-asm-aarch64-neon-mlal-lane-cortex-a53.S
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x16-minmax-fp32-asm-aarch64-neon-mlal-lane-ld64-prfm.S
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x16-minmax-fp32-asm-aarch64-neon-mlal-lane-ld64.S
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x16c4-minmax-fp32-asm-aarch64-neondot-cortex-a55.S
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x16c4-minmax-fp32-asm-aarch64-neondot-ld32.S
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x16c4-minmax-fp32-asm-aarch64-neondot-ld64.S
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x16c4-minmax-fp32-asm-aarch64-neondot-ld128.S
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8c8-minmax-fp32-asm-aarch64-neon-mlal-cortex-a53-prfm.S
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8c8-minmax-fp32-asm-aarch64-neon-mlal-cortex-a53.S
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8c8-minmax-fp32-asm-aarch64-neon-mlal-prfm.S
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-1x8c8-minmax-fp32-asm-aarch64-neon-mlal.S
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8c8-minmax-fp32-asm-aarch64-neon-mlal-cortex-a53-prfm.S
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8c8-minmax-fp32-asm-aarch64-neon-mlal-cortex-a53.S
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8c8-minmax-fp32-asm-aarch64-neon-mlal-prfm.S
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8c8-minmax-fp32-asm-aarch64-neon-mlal.S
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-2x8c16-minmax-fp32-asm-aarch64-neon-mlal.S
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x16-minmax-fp32-asm-aarch64-neon-mlal-lane-cortex-a53-prfm.S
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x16-minmax-fp32-asm-aarch64-neon-mlal-lane-cortex-a53.S
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x16-minmax-fp32-asm-aarch64-neon-mlal-lane-ld64-prfm.S
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x16-minmax-fp32-asm-aarch64-neon-mlal-lane-ld64.S
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x16c4-minmax-fp32-asm-aarch64-neondot-cortex-a55.S
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x16c4-minmax-fp32-asm-aarch64-neondot-ld64.S
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x16c4-minmax-fp32-asm-aarch64-neondot-ld128.S
  src/qu8-gemm/gen/qu8-gemm-4x8c4-minmax-rndnu-asm-aarch64-neondot-cortex-a55.S
  src/qu8-gemm/gen/qu8-gemm-4x8c4-minmax-rndnu-asm-aarch64-neondot-ld128.S
  src/qu8-gemm/gen/qu8-gemm-4x16-minmax-rndnu-asm-aarch64-neon-mlal-lane-cortex-a53-prfm.S
  src/qu8-gemm/gen/qu8-gemm-4x16-minmax-rndnu-asm-aarch64-neon-mlal-lane-cortex-a53.S
  src/qu8-gemm/gen/qu8-gemm-4x16-minmax-rndnu-asm-aarch64-neon-mlal-lane-cortex-a75-prfm.S
  src/qu8-gemm/gen/qu8-gemm-4x16-minmax-rndnu-asm-aarch64-neon-mlal-lane-cortex-a75.S
  src/qu8-gemm/gen/qu8-gemm-4x16-minmax-rndnu-asm-aarch64-neon-mlal-lane-ld64-prfm.S
  src/qu8-gemm/gen/qu8-gemm-4x16-minmax-rndnu-asm-aarch64-neon-mlal-lane-ld64.S
  src/qu8-gemm/gen/qu8-gemm-4x16c4-minmax-fp32-asm-aarch64-neondot-cortex-a55.S
  src/qu8-gemm/gen/qu8-gemm-4x16c4-minmax-fp32-asm-aarch64-neondot-ld128.S
  src/qu8-gemm/gen/qu8-gemm-4x16c4-minmax-rndnu-asm-aarch64-neondot-cortex-a55.S
  src/qu8-gemm/gen/qu8-gemm-4x16c4-minmax-rndnu-asm-aarch64-neondot-ld128.S
  src/qu8-igemm/gen/qu8-igemm-4x8c4-minmax-rndnu-asm-aarch64-neondot-cortex-a55.S
  src/qu8-igemm/gen/qu8-igemm-4x8c4-minmax-rndnu-asm-aarch64-neondot-ld128.S
  src/qu8-igemm/gen/qu8-igemm-4x16-minmax-rndnu-asm-aarch64-neon-mlal-lane-cortex-a53-prfm.S
  src/qu8-igemm/gen/qu8-igemm-4x16-minmax-rndnu-asm-aarch64-neon-mlal-lane-cortex-a53.S
  src/qu8-igemm/gen/qu8-igemm-4x16-minmax-rndnu-asm-aarch64-neon-mlal-lane-cortex-a75-prfm.S
  src/qu8-igemm/gen/qu8-igemm-4x16-minmax-rndnu-asm-aarch64-neon-mlal-lane-cortex-a75.S
  src/qu8-igemm/gen/qu8-igemm-4x16-minmax-rndnu-asm-aarch64-neon-mlal-lane-ld64-prfm.S
  src/qu8-igemm/gen/qu8-igemm-4x16-minmax-rndnu-asm-aarch64-neon-mlal-lane-ld64.S
  src/qu8-igemm/gen/qu8-igemm-4x16c4-minmax-fp32-asm-aarch64-neondot-cortex-a55.S
  src/qu8-igemm/gen/qu8-igemm-4x16c4-minmax-fp32-asm-aarch64-neondot-ld128.S
  src/qu8-igemm/gen/qu8-igemm-4x16c4-minmax-rndnu-asm-aarch64-neondot-cortex-a55.S
  src/qu8-igemm/gen/qu8-igemm-4x16c4-minmax-rndnu-asm-aarch64-neondot-ld128.S)

SET(WASM32_ASM_MICROKERNEL_SRCS
  src/f32-vrelu/f32-vrelu-asm-wasm32-shr-x1.S
  src/f32-vrelu/f32-vrelu-asm-wasm32-shr-x2.S
  src/f32-vrelu/f32-vrelu-asm-wasm32-shr-x4.S)

SET(WASMRELAXEDSIMD32_ASM_MICROKERNEL_SRCS)

SET(WASMSIMD32_ASM_MICROKERNEL_SRCS)

SET(AARCH32_JIT_MICROKERNEL_SRCS
  src/f32-gemm/gen/f32-gemm-1x8-aarch32-neon-cortex-a53.cc
  src/f32-gemm/gen/f32-gemm-4x8-aarch32-neon-cortex-a7.cc
  src/f32-gemm/gen/f32-gemm-4x8-aarch32-neon-cortex-a53.cc
  src/f32-gemm/gen/f32-gemm-4x8-aarch32-neon-cortex-a55.cc
  src/f32-gemm/gen/f32-gemm-4x8-aarch32-neon-cortex-a75.cc
  src/f32-gemm/gen/f32-gemm-4x8-aarch32-neon-ld64.cc
  src/f32-igemm/gen/f32-igemm-1x8-aarch32-neon-cortex-a53.cc
  src/f32-igemm/gen/f32-igemm-4x8-aarch32-neon-cortex-a7.cc
  src/f32-igemm/gen/f32-igemm-4x8-aarch32-neon-cortex-a53.cc
  src/f32-igemm/gen/f32-igemm-4x8-aarch32-neon-cortex-a55.cc
  src/f32-igemm/gen/f32-igemm-4x8-aarch32-neon-cortex-a75.cc
  src/f32-igemm/gen/f32-igemm-4x8-aarch32-neon-ld64.cc
  src/qs8-gemm/gen/qs8-gemm-4x8-rndnu-aarch32-neon-mlal-lane-ld64.cc
  src/qs8-gemm/gen/qs8-gemm-4x8c4-rndnu-aarch32-neondot-ld64.cc
  src/qs8-igemm/gen/qs8-igemm-4x8-rndnu-aarch32-neon-mlal-lane-ld64.cc
  src/qs8-igemm/gen/qs8-igemm-4x8c4-rndnu-aarch32-neondot-ld64.cc
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x8-fp32-aarch32-neonv8-mlal-lane-ld64.cc
  src/qs8-qc8w-gemm/gen/qs8-qc8w-gemm-4x8c4-fp32-aarch32-neondot-ld64.cc
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x8-fp32-aarch32-neonv8-mlal-lane-ld64.cc
  src/qs8-qc8w-igemm/gen/qs8-qc8w-igemm-4x8c4-fp32-aarch32-neondot-ld64.cc)

SET(AARCH64_JIT_MICROKERNEL_SRCS
  src/f16-gemm/gen/f16-gemm-1x16-aarch64-neonfp16arith-ld64.cc
  src/f16-gemm/gen/f16-gemm-4x16-aarch64-neonfp16arith-ld64.cc
  src/f16-gemm/gen/f16-gemm-6x16-aarch64-neonfp16arith-cortex-a55.cc
  src/f16-gemm/gen/f16-gemm-6x16-aarch64-neonfp16arith-cortex-a55r0.cc
  src/f16-gemm/gen/f16-gemm-6x16-aarch64-neonfp16arith-cortex-a75.cc
  src/f16-gemm/gen/f16-gemm-6x16-aarch64-neonfp16arith-ld64.cc
  src/f16-igemm/gen/f16-igemm-1x16-aarch64-neonfp16arith-ld64.cc
  src/f16-igemm/gen/f16-igemm-4x16-aarch64-neonfp16arith-ld64.cc
  src/f16-igemm/gen/f16-igemm-6x16-aarch64-neonfp16arith-cortex-a55.cc
  src/f16-igemm/gen/f16-igemm-6x16-aarch64-neonfp16arith-cortex-a55r0.cc
  src/f16-igemm/gen/f16-igemm-6x16-aarch64-neonfp16arith-cortex-a75.cc
  src/f16-igemm/gen/f16-igemm-6x16-aarch64-neonfp16arith-ld64.cc
  src/f32-gemm/gen/f32-gemm-1x8-aarch64-neonfma-cortex-a53.cc
  src/f32-gemm/gen/f32-gemm-1x8-aarch64-neonfma-cortex-a75.cc
  src/f32-gemm/gen/f32-gemm-1x8-aarch64-neonfma-ld64.cc
  src/f32-gemm/gen/f32-gemm-4x8-aarch64-neonfma-cortex-a53.cc
  src/f32-gemm/gen/f32-gemm-4x8-aarch64-neonfma-cortex-a55.cc
  src/f32-gemm/gen/f32-gemm-4x8-aarch64-neonfma-cortex-a75.cc
  src/f32-gemm/gen/f32-gemm-4x8-aarch64-neonfma-ld128.cc
  src/f32-gemm/gen/f32-gemm-6x8-aarch64-neonfma-cortex-a53.cc
  src/f32-gemm/gen/f32-gemm-6x8-aarch64-neonfma-cortex-a55.cc
  src/f32-gemm/gen/f32-gemm-6x8-aarch64-neonfma-cortex-a75.cc
  src/f32-gemm/gen/f32-gemm-6x8-aarch64-neonfma-ld128.cc
  src/f32-igemm/gen/f32-igemm-1x8-aarch64-neonfma-cortex-a53.cc
  src/f32-igemm/gen/f32-igemm-1x8-aarch64-neonfma-cortex-a75.cc
  src/f32-igemm/gen/f32-igemm-4x8-aarch64-neonfma-cortex-a53.cc
  src/f32-igemm/gen/f32-igemm-4x8-aarch64-neonfma-cortex-a55.cc
  src/f32-igemm/gen/f32-igemm-4x8-aarch64-neonfma-cortex-a75.cc
  src/f32-igemm/gen/f32-igemm-4x8-aarch64-neonfma-ld128.cc
  src/f32-igemm/gen/f32-igemm-6x8-aarch64-neonfma-cortex-a53.cc
  src/f32-igemm/gen/f32-igemm-6x8-aarch64-neonfma-cortex-a55.cc
  src/f32-igemm/gen/f32-igemm-6x8-aarch64-neonfma-cortex-a75.cc
  src/f32-igemm/gen/f32-igemm-6x8-aarch64-neonfma-ld128.cc)

SET(WASM32_JIT_MICROKERNEL_SRCS
  src/f32-vrelu/f32-vrelu-ukernel-jit-wasm32-shr.cc)

SET(WASMRELAXEDSIMD32_JIT_MICROKERNEL_SRCS)

SET(WASMSIMD32_JIT_MICROKERNEL_SRCS
  src/f32-gemm/MRx8-wasmsimd32-x86-loadsplat.cc
  src/f32-gemm/MRx8s4-wasmsimd32-x86.cc
  src/f32-igemm/MRx8-wasmsimd32-x86-loadsplat.cc)