// Copyright 2020 Google LLC
//
// This source code is licensed under the BSD-style license found in the
// LICENSE file in the root directory of this source tree.

$assert ROW_TILE >= 1
$assert ACCUMULATORS >= 1
#include <assert.h>

#include <arm_neon.h>

#include <xnnpack/dwconv.h>
#include <xnnpack/intrinsics-polyfill.h>
#include <xnnpack/math.h>


void xnn_f16_dwconv2d_chw_ukernel_3x3s2p1__neonfp16arith_${ROW_TILE}x8${"_acc%d" % ACCUMULATORS if ACCUMULATORS > 1 else ""}(
    size_t input_height,
    size_t input_width,
    const void* input,
    const void* weights,
    const void* zero,
    void* output,
    uint32_t padding_top,
    const union xnn_f16_chw_params params[restrict XNN_MIN_ELEMENTS(1)]) XNN_OOB_READS
{
  assert(input_height != 0);
  assert(input_width != 0);
  assert(input_width % sizeof(uint16_t) == 0);
  assert(padding_top <= 1);

  #if XNN_ARCH_ARM64
    const uint16x8x2_t vminmax = vld2q_dup_u16(&params->neonfp16arith_stride2.min);
    const float16x8_t vmin = vreinterpretq_f16_u16(vminmax.val[0]);
    const float16x8_t vmax = vreinterpretq_f16_u16(vminmax.val[1]);
  #else
    // vld2_dup is to work around aarch32 clang bug with vld1q_dup
    const uint16x4x2_t vminmax = vld2_dup_u16(&params->neonfp16arith_stride2.min);
    const float16x8_t vmin = vreinterpretq_f16_u16(vcombine_u16(vminmax.val[0], vminmax.val[0]));
    const float16x8_t vmax = vreinterpretq_f16_u16(vcombine_u16(vminmax.val[1], vminmax.val[1]));
  #endif
  const uint16x8_t vmask_even = vld1q_u16(params->neonfp16arith_stride2.mask_even);
  const uint16x8_t vmask_odd  = vld1q_u16(params->neonfp16arith_stride2.mask_odd);

  const uint16_t* w = (const uint16_t*) weights;
  const float16x8_t vw01234567 = vreinterpretq_f16_u16(vld1q_u16(w));
  const float16x4_t vw89 = vreinterpret_f16_u32(vld1_dup_u32((const void*) (w + 8)));

  const size_t input_decrement = round_down_po2(input_width, 8 /* SIMD output width */ * 2 /* subsampling */ * sizeof(uint16_t));
  $if ROW_TILE > 1:
    const size_t output_width = round_down_po2((input_width + (2 /* padding */ - 3 /* kernel size */ + 2 /* subsampling */) * sizeof(uint16_t)) / 2, sizeof(uint16_t));

  const uint16_t* i0 = (const uint16_t*) ((uintptr_t) input - ((-padding_top) & input_width));
  const uint16_t* i1 = (const uint16_t*) ((uintptr_t) i0 + input_width);
  if XNN_UNPREDICTABLE(padding_top != 0) {
    i0 = zero;
  }
  $for M in range(2, 1 + 2 * ROW_TILE):
    const uint16_t* i${M} = (const uint16_t*) ((uintptr_t) i${M-1} + input_width);

  uint16_t* o0 = output;
  $for M in range(1, ROW_TILE):
    uint16_t* o${M} = (uint16_t*) ((uintptr_t) o${M-1} + output_width);

  size_t padded_input_height = input_height + padding_top + 1 /* padding bottom */;
  size_t output_height = (padded_input_height - 3 /* kernel size */ + 2 /* subsampling */) / 2;
  do {
    $for M in range(2, 1 + 2 * ROW_TILE):
      if XNN_UNPREDICTABLE(padded_input_height < ${2 + M}) {
        i${M} = zero;
        $if M % 2 == 1:
          o${(M - 1) // 2} = o${(M - 1) // 2 - 1};
      }

    $for M in range(1 + 2 * ROW_TILE):
      float16x8_t vi${M}x13579BDF = vreinterpretq_f16_u16(vmovq_n_u16(0));

    size_t w = input_width;
    for (; w >= 16 * sizeof(uint16_t); w -= 16 * sizeof(uint16_t)) {
      $for M in range(ROW_TILE):
        float16x8_t vo${M}p0 = vdupq_lane_f16(vget_low_f16(vw01234567), 0);

      $for M in range(1 + 2 * ROW_TILE):
        const uint16x8x2_t vi${M}xGIKMOQSUHJLNPRTV = vld2q_u16(i${M}); i${M} += 16;

      // Center column
      $for M in range(ROW_TILE):
        $if ACCUMULATORS > 1:
          float16x8_t vo${M}p1 = vmulq_lane_f16(vreinterpretq_f16_u16(vi${2*M}xGIKMOQSUHJLNPRTV.val[0]), vget_low_f16(vw01234567), 2);
        $else:
          #if XNN_ARCH_ARM64
            vo${M}p0 = vfmaq_laneq_f16(vo${M}p0, vreinterpretq_f16_u16(vi${2*M}xGIKMOQSUHJLNPRTV.val[0]), vw01234567, 2);
          #else
            vo${M}p0 = vmlaq_lane_f16(vo${M}p0, vreinterpretq_f16_u16(vi${2*M}xGIKMOQSUHJLNPRTV.val[0]), vget_low_f16(vw01234567), 2);
          #endif
      $for M in range(ROW_TILE):
        $if ACCUMULATORS > 2:
          float16x8_t vo${M}p2 = vmulq_lane_f16(vreinterpretq_f16_u16(vi${2*M+1}xGIKMOQSUHJLNPRTV.val[0]), vget_high_f16(vw01234567), 1);
        $else:
          #if XNN_ARCH_ARM64
            vo${M}p0 = vfmaq_laneq_f16(vo${M}p0, vreinterpretq_f16_u16(vi${2*M+1}xGIKMOQSUHJLNPRTV.val[0]), vw01234567, 5);
          #else
            vo${M}p0 = vmlaq_lane_f16(vo${M}p0, vreinterpretq_f16_u16(vi${2*M+1}xGIKMOQSUHJLNPRTV.val[0]), vget_high_f16(vw01234567), 1);
          #endif
      $for M in range(ROW_TILE):
        $if ACCUMULATORS > 3:
          float16x8_t vo${M}p3 = vmulq_lane_f16(vreinterpretq_f16_u16(vi${2*M+2}xGIKMOQSUHJLNPRTV.val[0]), vw89, 0);
        $else:
          #if XNN_ARCH_ARM64
            vo${M}p${4 % ACCUMULATORS} = vfmaq_lane_f16(vo${M}p${4 % ACCUMULATORS}, vreinterpretq_f16_u16(vi${2*M+2}xGIKMOQSUHJLNPRTV.val[0]), vw89, 0);
          #else
            vo${M}p${4 % ACCUMULATORS} = vmlaq_lane_f16(vo${M}p${4 % ACCUMULATORS}, vreinterpretq_f16_u16(vi${2*M+2}xGIKMOQSUHJLNPRTV.val[0]), vw89, 0);
          #endif
      // Left column
      $for M in range(1 + 2 * ROW_TILE):
        const float16x8_t vi${M}xFHJLNPRT = vextq_f16(vi${M}x13579BDF, vreinterpretq_f16_u16(vi${M}xGIKMOQSUHJLNPRTV.val[1]), 7);
        vi${M}x13579BDF = vreinterpretq_f16_u16(vi${M}xGIKMOQSUHJLNPRTV.val[1]);

      $for M in range(ROW_TILE):
        $if ACCUMULATORS > 4:
          float16x8_t vo${M}p4 = vmulq_lane_f16(vi${2*M}xFHJLNPRT, vget_low_f16(vw01234567), 1);
        $else:
          #if XNN_ARCH_ARM64
            vo${M}p${5 % ACCUMULATORS} = vfmaq_laneq_f16(vo${M}p${5 % ACCUMULATORS}, vi${2*M}xFHJLNPRT, vw01234567, 1);
          #else
            vo${M}p${5 % ACCUMULATORS} = vmlaq_lane_f16(vo${M}p${5 % ACCUMULATORS}, vi${2*M}xFHJLNPRT, vget_low_f16(vw01234567), 1);
          #endif
      $for M in range(ROW_TILE):
        $if ACCUMULATORS > 5:
          float16x8_t vo${M}p5 = vmulq_lane_f16(vi${2*M+1}xFHJLNPRT, vget_high_f16(vw01234567), 0);
        $else:
          #if XNN_ARCH_ARM64
            vo${M}p${6 % ACCUMULATORS} = vfmaq_laneq_f16(vo${M}p${6 % ACCUMULATORS}, vi${2*M+1}xFHJLNPRT, vw01234567, 4);
          #else
            vo${M}p${6 % ACCUMULATORS} = vmlaq_lane_f16(vo${M}p${6 % ACCUMULATORS}, vi${2*M+1}xFHJLNPRT, vget_high_f16(vw01234567), 0);
          #endif
      $for M in range(ROW_TILE):
        $if ACCUMULATORS > 6:
          float16x8_t vo${M}p6 = vmulq_lane_f16(vi${2*M+2}xFHJLNPRT, vget_high_f16(vw01234567), 1);
        $else:
          #if XNN_ARCH_ARM64
            vo${M}p${7 % ACCUMULATORS} = vfmaq_laneq_f16(vo${M}p${7 % ACCUMULATORS}, vi${2*M+2}xFHJLNPRT, vw01234567, 7);
          #else
            vo${M}p${7 % ACCUMULATORS} = vmlaq_lane_f16(vo${M}p${7 % ACCUMULATORS}, vi${2*M+2}xFHJLNPRT, vget_high_f16(vw01234567), 3);
          #endif
      // Right column
      $for M in range(ROW_TILE):
        #if XNN_ARCH_ARM64
          vo${M}p${8 % ACCUMULATORS} = vfmaq_laneq_f16(vo${M}p${8 % ACCUMULATORS}, vreinterpretq_f16_u16(vi${2*M}xGIKMOQSUHJLNPRTV.val[1]), vw01234567, 3);
        #else
          vo${M}p${8 % ACCUMULATORS} = vmlaq_lane_f16(vo${M}p${8 % ACCUMULATORS}, vreinterpretq_f16_u16(vi${2*M}xGIKMOQSUHJLNPRTV.val[1]), vget_low_f16(vw01234567), 3);
        #endif
      $for M in range(ROW_TILE):
        #if XNN_ARCH_ARM64
          vo${M}p${9 % ACCUMULATORS} = vfmaq_laneq_f16(vo${M}p${9 % ACCUMULATORS}, vreinterpretq_f16_u16(vi${2*M+1}xGIKMOQSUHJLNPRTV.val[1]), vw01234567, 6);
        #else
          vo${M}p${9 % ACCUMULATORS} = vmlaq_lane_f16(vo${M}p${9 % ACCUMULATORS}, vreinterpretq_f16_u16(vi${2*M+1}xGIKMOQSUHJLNPRTV.val[1]), vget_high_f16(vw01234567), 2);
        #endif
      $for M in range(ROW_TILE):
        #if XNN_ARCH_ARM64
          vo${M}p${10 % ACCUMULATORS} = vfmaq_lane_f16(vo${M}p${10 % ACCUMULATORS}, vreinterpretq_f16_u16(vi${2*M+2}xGIKMOQSUHJLNPRTV.val[1]), vw89, 1);
        #else
          vo${M}p${10 % ACCUMULATORS} = vmlaq_lane_f16(vo${M}p${10 % ACCUMULATORS}, vreinterpretq_f16_u16(vi${2*M+2}xGIKMOQSUHJLNPRTV.val[1]), vw89, 1);
        #endif
      $if ACCUMULATORS > 1:
        $ACC_SLICE = 1
        $while ACC_SLICE < ACCUMULATORS:
          $for A in range(0, ACCUMULATORS, ACC_SLICE * 2):
            $if A + ACC_SLICE < ACCUMULATORS:
              $for M in range(ROW_TILE):
                vo${M}p${A} = vaddq_f16(vo${M}p${A}, vo${M}p${A + ACC_SLICE});
          $ACC_SLICE *= 2

      $for M in range(ROW_TILE):
        float16x8_t vo${M} = vmaxq_f16(vo${M}p0, vmin);

      $for M in range(ROW_TILE):
        vo${M} = vminq_f16(vo${M}, vmax);

      $for M in reversed(range(ROW_TILE)):
        vst1q_u16(o${M}, vreinterpretq_u16_f16(vo${M})); o${M} += 8;
    }

    // Last block has 0-15 pixels to process.
    assert(w < 16 * sizeof(uint16_t));
    if XNN_LIKELY(w != 0) {
      $for M in range(ROW_TILE):
        float16x8_t vo${M}p0 = vdupq_lane_f16(vget_low_f16(vw01234567), 0);

      $for M in range(1 + 2 * ROW_TILE):
        const uint16x8x2_t vi${M}xGIKMOQSUHJLNPRTV = vld2q_u16(i${M});

      $for M in range(1 + 2 * ROW_TILE):
        const float16x8_t vi${M}xGIKMOQSU = vreinterpretq_f16_u16(vandq_u16(vmask_even, vi${M}xGIKMOQSUHJLNPRTV.val[0]));
        const float16x8_t vi${M}xHJLNPRTV = vreinterpretq_f16_u16(vandq_u16(vmask_odd,  vi${M}xGIKMOQSUHJLNPRTV.val[1]));

      // Center column
      $for M in range(ROW_TILE):
        $if ACCUMULATORS > 1:
          float16x8_t vo${M}p1 = vmulq_lane_f16(vi${2*M}xGIKMOQSU, vget_low_f16(vw01234567), 2);
        $else:
          #if XNN_ARCH_ARM64
            vo${M}p0 = vfmaq_laneq_f16(vo${M}p0, vi${2*M}xGIKMOQSU, vw01234567, 2);
          #else
            vo${M}p0 = vmlaq_lane_f16(vo${M}p0, vi${2*M}xGIKMOQSU, vget_low_f16(vw01234567), 2);
          #endif
      $for M in range(ROW_TILE):
        $if ACCUMULATORS > 2:
          float16x8_t vo${M}p2 = vmulq_lane_f16(vi${2*M+1}xGIKMOQSU, vget_high_f16(vw01234567), 1);
        $else:
          #if XNN_ARCH_ARM64
            vo${M}p0 = vfmaq_laneq_f16(vo${M}p0, vi${2*M+1}xGIKMOQSU, vw01234567, 5);
          #else
            vo${M}p0 = vmlaq_lane_f16(vo${M}p0, vi${2*M+1}xGIKMOQSU, vget_high_f16(vw01234567), 1);
          #endif
      $for M in range(ROW_TILE):
        $if ACCUMULATORS > 3:
          float16x8_t vo${M}p3 = vmulq_lane_f16(vi${2*M+2}xGIKMOQSU, vw89, 0);
        $else:
          #if XNN_ARCH_ARM64
            vo${M}p${4 % ACCUMULATORS} = vfmaq_lane_f16(vo${M}p${4 % ACCUMULATORS}, vi${2*M+2}xGIKMOQSU, vw89, 0);
          #else
            vo${M}p${4 % ACCUMULATORS} = vmlaq_lane_f16(vo${M}p${4 % ACCUMULATORS}, vi${2*M+2}xGIKMOQSU, vw89, 0);
          #endif
      // Left column
      $for M in range(1 + 2 * ROW_TILE):
        const float16x8_t vi${M}xFHJLNPRT = vextq_f16(vi${M}x13579BDF, vi${M}xHJLNPRTV, 7);

      $for M in range(ROW_TILE):
        $if ACCUMULATORS > 4:
          float16x8_t vo${M}p4 = vmulq_lane_f16(vi${2*M}xFHJLNPRT, vget_low_f16(vw01234567), 1);
        $else:
          #if XNN_ARCH_ARM64
            vo${M}p${5 % ACCUMULATORS} = vfmaq_laneq_f16(vo${M}p${5 % ACCUMULATORS}, vi${2*M}xFHJLNPRT, vw01234567, 1);
          #else
            vo${M}p${5 % ACCUMULATORS} = vmlaq_lane_f16(vo${M}p${5 % ACCUMULATORS}, vi${2*M}xFHJLNPRT, vget_low_f16(vw01234567), 1);
          #endif
      $for M in range(ROW_TILE):
        $if ACCUMULATORS > 5:
          float16x8_t vo${M}p5 = vmulq_lane_f16(vi${2*M+1}xFHJLNPRT, vget_high_f16(vw01234567), 0);
        $else:
          #if XNN_ARCH_ARM64
            vo${M}p${6 % ACCUMULATORS} = vfmaq_laneq_f16(vo${M}p${6 % ACCUMULATORS}, vi${2*M+1}xFHJLNPRT, vw01234567, 4);
          #else
            vo${M}p${6 % ACCUMULATORS} = vmlaq_lane_f16(vo${M}p${6 % ACCUMULATORS}, vi${2*M+1}xFHJLNPRT, vget_high_f16(vw01234567), 0);
          #endif
      $for M in range(ROW_TILE):
        $if ACCUMULATORS > 6:
          float16x8_t vo${M}p6 = vmulq_lane_f16(vi${2*M+2}xFHJLNPRT, vget_high_f16(vw01234567), 1);
        $else:
          #if XNN_ARCH_ARM64
            vo${M}p${7 % ACCUMULATORS} = vfmaq_laneq_f16(vo${M}p${7 % ACCUMULATORS}, vi${2*M+2}xFHJLNPRT, vw01234567, 7);
          #else
            vo${M}p${7 % ACCUMULATORS} = vmlaq_lane_f16(vo${M}p${7 % ACCUMULATORS}, vi${2*M+2}xFHJLNPRT, vget_high_f16(vw01234567), 3);
          #endif
      // Right column
      $for M in range(ROW_TILE):
        #if XNN_ARCH_ARM64
          vo${M}p${8 % ACCUMULATORS} = vfmaq_laneq_f16(vo${M}p${8 % ACCUMULATORS}, vi${2*M}xHJLNPRTV, vw01234567, 3);
        #else
          vo${M}p${8 % ACCUMULATORS} = vmlaq_lane_f16(vo${M}p${8 % ACCUMULATORS}, vi${2*M}xHJLNPRTV, vget_low_f16(vw01234567), 3);
        #endif
      $for M in range(ROW_TILE):
        #if XNN_ARCH_ARM64
          vo${M}p${9 % ACCUMULATORS} = vfmaq_laneq_f16(vo${M}p${9 % ACCUMULATORS}, vi${2*M+1}xHJLNPRTV, vw01234567, 6);
        #else
          vo${M}p${9 % ACCUMULATORS} = vmlaq_lane_f16(vo${M}p${9 % ACCUMULATORS}, vi${2*M+1}xHJLNPRTV, vget_high_f16(vw01234567), 2);
        #endif
      $for M in range(ROW_TILE):
        #if XNN_ARCH_ARM64
          vo${M}p${10 % ACCUMULATORS} = vfmaq_lane_f16(vo${M}p${10 % ACCUMULATORS}, vi${2*M+2}xHJLNPRTV, vw89, 1);
        #else
          vo${M}p${10 % ACCUMULATORS} = vmlaq_lane_f16(vo${M}p${10 % ACCUMULATORS}, vi${2*M+2}xHJLNPRTV, vw89, 1);
        #endif
      $if ACCUMULATORS > 1:
        $ACC_SLICE = 1
        $while ACC_SLICE < ACCUMULATORS:
          $for A in range(0, ACCUMULATORS, ACC_SLICE * 2):
            $if A + ACC_SLICE < ACCUMULATORS:
              $for M in range(ROW_TILE):
                vo${M}p${A} = vaddq_f16(vo${M}p${A}, vo${M}p${A + ACC_SLICE});
          $ACC_SLICE *= 2

      $for M in range(ROW_TILE):
        float16x8_t vo${M} = vmaxq_f16(vo${M}p0, vmin);

      $for M in range(ROW_TILE):
        vo${M} = vminq_f16(vo${M}, vmax);

      w += 1 * sizeof(uint16_t);

      if XNN_LIKELY(w == 16 * sizeof(uint16_t)) {
        $for M in reversed(range(ROW_TILE)):
          vst1q_u16(o${M}, vreinterpretq_u16_f16(vo${M})); o${M} += 8;
      } else {
        $for M in reversed(range(ROW_TILE)):
          float16x4_t vo${M}_lo = vget_low_f16(vo${M});

        if (w & (8 * sizeof(uint16_t))) {
         $for M in reversed(range(ROW_TILE)):
            vst1_u16(o${M}, vreinterpret_u16_f16(vo${M}_lo)); o${M} += 4;

          $for M in reversed(range(ROW_TILE)):
            vo${M}_lo = vget_high_f16(vo${M});
        }
        if (w & (4 * sizeof(uint16_t))) {
          $for M in reversed(range(ROW_TILE)):
            vst1_lane_u32((void*) o${M}, vreinterpret_u32_f16(vo${M}_lo), 0); o${M} += 2;

          $for M in range(ROW_TILE):
            vo${M}_lo = vext_f16(vo${M}_lo, vo${M}_lo, 2);
        }
        if (w & (2 * sizeof(uint16_t))) {
          $for M in reversed(range(ROW_TILE)):
            vst1_lane_u16(o${M}, vreinterpret_u16_f16(vo${M}_lo), 0); o${M} += 1;
        }
      }
    }

    i0 = (const uint16_t*) ((uintptr_t) i${2 * ROW_TILE} - input_decrement);
    $for M in range(1, 1 + 2 * ROW_TILE):
      i${M} = (const uint16_t*) ((uintptr_t) i${M-1} + input_width);

    $if ROW_TILE > 1:
      o0 = o${ROW_TILE - 1};
      $for M in range(1, ROW_TILE):
        o${M} = (uint16_t*) ((uintptr_t) o${M-1} + output_width);

    $if ROW_TILE > 1:
      output_height = doz(output_height, ${ROW_TILE});
      padded_input_height = doz(padded_input_height, ${ROW_TILE * 2});
    $else:
      output_height -= 1;
      padded_input_height -= 2;
  } while (output_height != 0);
}