// Copyright 2020 Google LLC
//
// This source code is licensed under the BSD-style license found in the
// LICENSE file in the root directory of this source tree.

$assert BATCH_TILE % 8 == 0
$assert BATCH_TILE >= 8
$ABC = "01234567456789ABCDEFGHIJKLMNOPQRSTUVWXYZ"
$assert OP in ["ADD", "DIV", "MAX", "MIN", "MUL", "SUB", "SQRDIFF"]
$assert ACTIVATION in ["LINEAR", "MINMAX"]
#include <assert.h>

#include <arm_neon.h>

#include <xnnpack/common.h>
#include <xnnpack/vbinary.h>


$VOPQ_F16 = {
$  "ADD": lambda x, y: "vaddq_f16(%s, %s)" % (x, y),
$  "DIV": lambda x, y: "vdivq_f16(%s, %s)" % (x, y),
$  "MAX": lambda x, y: "vmaxq_f16(%s, %s)" % (x, y),
$  "MIN": lambda x, y: "vminq_f16(%s, %s)" % (x, y),
$  "MUL": lambda x, y: "vmulq_f16(%s, %s)" % (x, y),
$  "SUB": lambda x, y: "vsubq_f16(%s, %s)" % (x, y),
$  "SQRDIFF": lambda x, y: "vsubq_f16(%s, %s)" % (x, y),
$}[OP]
$SUFFIX = {"LINEAR": "", "MINMAX": "_minmax"}[ACTIVATION]
$PARAMS = {"LINEAR": "xnn_f16_default_params", "MINMAX": "xnn_f16_minmax_params"}[ACTIVATION]
$ISA = "aarch64_neonfp16arith" if OP == "DIV" else "neonfp16arith"
void xnn_f16_v${OP.lower()}${SUFFIX}_ukernel__${ISA}_x${BATCH_TILE}(
    size_t batch,
    const void* restrict input_a,
    const void* restrict input_b,
    void* restrict output,
    const union ${PARAMS} params[restrict XNN_MIN_ELEMENTS(1)]) XNN_OOB_READS
{
  assert(batch != 0);
  assert(batch % sizeof(uint16_t) == 0);
  assert(input_a != NULL);
  assert(input_b != NULL);
  assert(output != NULL);

  const uint16_t* a = (const uint16_t*) input_a;
  const uint16_t* b = (const uint16_t*) input_b;
  uint16_t* o = (uint16_t*) output;

  $if ACTIVATION == "MINMAX":
    const float16x8_t vy_min = vreinterpretq_f16_u16(vld1q_dup_u16(&params->fp16arith.min));
    const float16x8_t vy_max = vreinterpretq_f16_u16(vld1q_dup_u16(&params->fp16arith.max));

  $if BATCH_TILE > 8:
    for (; batch >= ${BATCH_TILE} * sizeof(uint16_t); batch -= ${BATCH_TILE} * sizeof(uint16_t)) {
      $for N in range(0, BATCH_TILE, 8):
        const float16x8_t va${ABC[N:N+8]} = vreinterpretq_f16_u16(vld1q_u16(a)); a += 8;
        const float16x8_t vb${ABC[N:N+8]} = vreinterpretq_f16_u16(vld1q_u16(b)); b += 8;

      $for N in range(0, BATCH_TILE, 8):
        float16x8_t vy${ABC[N:N+8]} = ${VOPQ_F16("va" + ABC[N:N+8], "vb" + ABC[N:N+8])};

      $if OP == "SQRDIFF":
        $for N in range(0, BATCH_TILE, 8):
          vy${ABC[N:N+8]} = vmulq_f16(vy${ABC[N:N+8]}, vy${ABC[N:N+8]});

      $if ACTIVATION == "MINMAX":
        $for N in range(0, BATCH_TILE, 8):
          vy${ABC[N:N+8]} = vmaxq_f16(vy${ABC[N:N+8]}, vy_min);

        $for N in range(0, BATCH_TILE, 8):
          vy${ABC[N:N+8]} = vminq_f16(vy${ABC[N:N+8]}, vy_max);

      $for N in range(0, BATCH_TILE, 8):
        vst1q_u16(o, vreinterpretq_u16_f16(vy${ABC[N:N+8]})); o += 8;
    }
  for (; batch >= 8 * sizeof(uint16_t); batch -= 8 * sizeof(uint16_t)) {
    const float16x8_t va01234567 = vreinterpretq_f16_u16(vld1q_u16(a)); a += 8;
    const float16x8_t vb01234567 = vreinterpretq_f16_u16(vld1q_u16(b)); b += 8;

    float16x8_t vy01234567 = ${VOPQ_F16("va01234567", "vb01234567")};
    $if OP == "SQRDIFF":
      vy01234567 = vmulq_f16(vy01234567, vy01234567);
    $if ACTIVATION == "MINMAX":
      vy01234567 = vmaxq_f16(vy01234567, vy_min);
      vy01234567 = vminq_f16(vy01234567, vy_max);
    vst1q_u16(o, vreinterpretq_u16_f16(vy01234567)); o += 8;
  }
  if XNN_UNLIKELY(batch != 0) {
    const float16x8_t va01234567 = vreinterpretq_f16_u16(vld1q_u16(a));
    const float16x8_t vb01234567 = vreinterpretq_f16_u16(vld1q_u16(b));

    float16x8_t vy01234567 = ${VOPQ_F16("va01234567", "vb01234567")};
    $if OP == "SQRDIFF":
      vy01234567 = vmulq_f16(vy01234567, vy01234567);
    $if ACTIVATION == "MINMAX":
      vy01234567 = vmaxq_f16(vy01234567, vy_min);
      vy01234567 = vminq_f16(vy01234567, vy_max);

    float16x4_t vy0123 = vget_low_f16(vy01234567);
    if (batch & (4 * sizeof(uint16_t))) {
      vst1_u16(o, vreinterpret_u16_f16(vy0123)); o += 4;
      vy0123 = vget_high_f16(vy01234567);
    }

    if (batch & (2 * sizeof(uint16_t))) {
      vst1_lane_u32((void*) o, vreinterpret_u32_f16(vy0123), 0); o += 2;
      vy0123 = vext_f16(vy0123, vy0123, 2);
    }

    if (batch & (1 * sizeof(uint16_t))) {
      vst1_lane_u16(o, vreinterpret_u16_f16(vy0123), 0);
    }
  }
}